From newsfish@newsfish Tue Aug 9 07:52:55 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i9g2000vby.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: CFP with extended deadline of Mar. 31, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Sun, 20 Mar 2011 03:14:04 -0700 (PDT) Organization: http://groups.google.com Lines: 275 Message-ID: <86d38e7f-21c7-40d4-99a5-6818728a4c84@i9g2000vby.googlegroups.com> NNTP-Posting-Host: 174.2.56.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300616047 10601 127.0.0.1 (20 Mar 2011 10:14:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 20 Mar 2011 10:14:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i9g2000vby.googlegroups.com; posting-host=174.2.56.216; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; .NET4.0C; OfficeLiveConnector.1.5; OfficeLivePatch.1.3; FDM; AskTbTRL2/5.7.0.231),gzip(gfe) Xref: feeder.eternal-september.org sci.electronics.design:162768 sci.electronics.cad:7840 sci.electronics.misc:3705 sci.engr.semiconductors:764 comp.lang.vhdl:4858 Dear Colleagues: Please share the announcement below with those who may be interested. Thank you, Organizing Committee ------------ CALL FOR PAPERS =========================================== Paper Submission Deadline: March 31, 2011 MSV'11 The 2011 International Conference on Modeling, Simulation and Visualization Methods July 18-21, 2011, Las Vegas, USA http://www.world-academy-of-science.org/ ================================================== You are invited to submit a full paper for consideration. All accepted papers will be published in the respective conference proceedings. The proceedings will be indexed in Inspec / IET / The Institute for Engineering & Technology, DBLP / Computer Science Bibliography, and others.) In the past, all tracks of this federated conference have also been included in EI Compendex/Elsevier. Like prior years, extended versions of selected papers will appear in journals and edited research books (a large number of book projects and journal special issues are in the pipeline: Springer, Elsevier, BMC journals, ...) The main keynote lecture will be presented by Prof. David Lorge Parnas (Fellow of IEEE, ACM, RSC, CAE, GI; MRIA); there will also be 8 other distinguished invited speakers and 12 planned tutorials and panel discussions as well as 75 research paper presentations. SCOPE: Topics of interest include, but are not limited to: O Simulation languages O Modeling and simulation for computer engineering O Modeling and simulation for education and training O Molecular modeling and simulation O Performance modeling, simulation, and prediction O Modeling, simulation, and emulation of large-scale, volatile environments O Modeling and simulation tools for nanotechnology O Information and scientific visualization O Real-time modeling and simulation O Geometric modeling O Perceptual issues in visualization and modeling O Modeling methodologies O Specification issues for modeling and simulation O Visual interactive simulation and modeling O Visualization tools and systems for simulation and modeling O Java-based modelers O Scalability issues O Numerical methods used in simulation and modeling O Finite and boundary element techniques O Process simulation/modeling O Device simulation/modeling O Circuit simulation/modeling O Performance evaluation and simulation tools O Multi-level modeling O Simulation of machine architectures O Simulation of wireless systems O Simulation and modeling with applications in biotechnology O CAD/CAE/CAM O Prototyping and simulation O Biomedical visualization and applications O Databases and visualization O Interaction paradigms and human factors O Parallel and distributed simulation O Discrete and numeric simulation O Geographic information systems and visualization O Internet, web and security visualization O Virtual reality and simulation O Virtual environments and data visualization O Petri nets and applications O Finite element methods O Soft computing / fuzzy logic O Tools and applications O Object-oriented simulation O Knowledge-based simulation O Emerging technologies and applications USEFUL WEB LINKS: The DBLP list of accepted papers of MSV 2010 appears at: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2010.html The main web site of MSV'11 can be accessed via: http://www.world-academy-of-science.org/ IMPORTANT DATES: March 31, 2011: Submission of papers (about 5 to 7 pages) April 20, 2011: Notification of acceptance (+/- 6 days) May 7, 2011: Final papers + Copyright/Consent + Registration July 18-21, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11) Those who have submitted papers during the month of February will receive the decision on their papers by the end of March 2011. ACADEMIC CO-SPONSORS: Currently being prepared - The Academic sponsors of the last offering of MSV (2010) included research labs and centers affiliated with (a partial list): University of California, Berkeley; University of Southern California; University of Texas at Austin; Harvard University, Cambridge, Massachusetts; Georgia Institute of Technology, Georgia; Emory University, Georgia; University of Minnesota; University of Iowa; University of North Dakota; NDSU-CIIT Green Computing & Comm. Lab.; University of Siegen, Germany; UMIT, Austria; SECLAB (University of Naples Federico II + University of Naples Parthenope + Second University of Naples, Italy); National Institute for Health Research; World Academy of Biomedical Sciences and Technologies; Russian Academy of Sciences, Russia; International Society of Intelligent Biological Medicine (ISIBM); The International Council on Medical and Care Compunetics; Eastern Virginia Medical School & the American College of Surgeons, USA. SUBMISSION OF PAPERS: Prospective authors are invited to submit their papers by uploading them to the evaluation web site at: http://world-comp.org Submissions must be uploaded by March 31, 2011 and they must be in either MS doc (but not docx) or pdf formats (about 5 to 7 pages - single space, font size of 10 to 12). All reasonable typesetting formats are acceptable (later, the authors of accepted papers will be asked to follow a particular typesetting format to prepare their final papers for publication.) Papers must not have been previously published or currently submitted for publication elsewhere. The first page of the paper should include: title of the paper, name, affiliation, postal address, and email address for each author. The first page should also identify the name of the Contact Author and a maximum of 5 topical keywords that would best represent the content of the paper. Finally, the name of the conference (ie, MSV) that the paper is being submitted for consideration must be stated on the first page. The length of the final/Camera-Ready papers (if accepted) will be limited to 7 (two-column IEEE style) pages. Each paper will be peer-reviewed by two experts in the field for originality, significance, clarity, impact, and soundness. In cases of contradictory recommendations, a member of the conference program committee will be charged to make the final decision (accept/reject) - often, this would involve seeking help from additional referees by using a double-blinded review process. In addition, all papers whose authors included a member of the conference program committee will be evaluated using the double-blinded review process. (Essay/philosophical papers will not be refereed but may be considered for discussion/panels). All proceedings of WORLDCOMP will be published and indexed in: Inspec / IET / The Institute for Engineering & Technology, DBLP / CS Bibliography, and others. The printed proceedings will be available for distribution on site at the conference. In the past, all tracks of the federated congress have also been included in EI Compendex/Elsevier. MEMBERS OF PROGRAM AND ORGANIZING COMMITTEES: The members of the Steering Committee of The 2010 congress included: Dr. Selim Aissi (Chief Strategist, Intel Corporation, USA); Prof. Hamid Arabnia (ISIBM Fellow & Professor, University of Georgia; Associate Editor, IEEE Transactions on Information Technology in Biomedicine; Editor-in-Chief, Journal of Supercomputing, Springer; Advisory Board, IEEE TC on Scalable Computing); Prof. Ruzena Bajcsy (Member, National Academy of Engineering, IEEE Fellow, ACM Fellow, Professor; University of California, Berkeley, USA); Prof. Hyunseung Choo (ITRC Director of Ministry of Information & Communication; Director, ITRC; Director, Korea Information Processing Society; Assoc. Editor, ACM Transactions on Internet Technology; Professor, Sungkyunkwan University, Korea); Prof. Winston Wai-Chi Fang (IEEE Fellow, TSMC Distinguished Chair Professor, National ChiaoTung University, Hsinchu, Taiwan, ROC); Prof. Andy Marsh (Director HoIP, Secretary-General WABT; Vice-president ICET and ICMCC, Visiting Professor, University of Westminster, UK); Dr. Rahman Tashakkori (Director, S-STEM NSF Supported Scholarship Program and NSF Supported AUAS, Appalachian State U., USA); Prof. Layne T. Watson (IEEE Fellow, NIA Fellow, ISIBM Fellow, Fellow of The National Institute of Aerospace, Virginia Polytechnic Institute & State University, USA); and Prof. Lotfi A. Zadeh (Member, National Academy of Engineering; IEEE Fellow, ACM Fellow, AAAS Fellow, AAAI Fellow, IFSA Fellow; Director, BISC; Professor, University of California, Berkeley, USA). The list of Program Committee of MSV 2010 appears at: http://www.world-academy-of-science.org/worldcomp10/ws/conferences/msv10/committee The MSV 2011 program committee is currently being compiled. Many who have already joined the committee are renowned leaders, scholars, researchers, scientists and practitioners of the highest ranks; many are directors of research labs., members of National Academy of Engineering, fellows of various societies, heads/chairs of departments, program directors of research funding agencies, deans and provosts as well as members of chapters of World Academy of Science. 2011 PUBLICITY CHAIR: A. M. G. Solo BCS Fellow (British Computer Society Fellow) Principal/R&D Engineer, Maverick Technologies America Inc. Principal/Intelligent Systems Instructor, Trailblazer Intelligent Systems, Inc. GENERAL INFORMATION: MSV conference is an important track of a federated research conference. It is being held jointly (same location and dates) with a number of other research conferences (WORLDCOMP). WORLDCOMP is the largest annual gathering of researchers in computer science, computer engineering and applied computing. We anticipate to have 2,000 or more attendees from over 85 countries. WORLDCOMP 2011 will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations. In recent past, keynote/tutorial/panel speakers have included: Prof. David A. Patterson (pioneer/ architecture, U. of California, Berkeley), Dr. K. Eric Drexler (known as Father of Nanotechnology), Prof. John H. Holland (known as Father of Genetic Algorithms; U. of Michigan), Prof. Ian Foster (known as Father of Grid Computing; U. of Chicago & ANL), Prof. Ruzena Bajcsy (pioneer/VR, U. of California, Berkeley), Prof. Barry Vercoe (Founding member of MIT Media Lab, MIT), Dr. Jim Gettys (known as X-man, developer of X Window System, xhost; OLPC), Prof. John Koza (known as Father of Genetic Programming, Stanford U.), Prof. Brian D. Athey (NIH Program Director, U. of Michigan), Prof. Viktor K. Prasanna (pioneer, U. of Southern California), Dr. Jose L. Munoz (NSF Program Director and Consultant), Prof. Jun Liu (Broad Institute of MIT & Harvard U.), Prof. Lotfi A. Zadeh (Father of Fuzzy Logic), Dr. Firouz Naderi (Head, NASA Mars Exploration Program/2000-2005 and Associate Director, Project Formulation & Strategy, Jet Propulsion Lab, CalTech/NASA), and many other distinguished speakers. To get a feeling about the conferences' atmosphere, see the 2010 delegates photos available at: www.pixagogo.com/1676934789 An important mission of WORLDCOMP is "Providing a unique platform for a diverse community of constituents composed of scholars, researchers, developers, educators, and practitioners. The Congress makes concerted effort to reach out to participants affiliated with diverse entities (such as: universities, institutions, corporations, government agencies, and research centers/labs) from all over the world. The congress also attempts to connect participants from institutions that have teaching as their main mission with those who are affiliated with institutions that have research as their main mission. The congress uses a quota system to achieve its institution and geography diversity objectives." One main goal of the congress is to assemble a spectrum of affiliated research conferences, workshops, and symposiums into a coordinated research meeting held in a common place at a common time. This model facilitates communication among researchers in different branches of computer science, computer engineering, and applied computing. The Congress also encourages multi-disciplinary and inter-disciplinary research initiatives; ie, facilitating increased opportunities for cross-fertilization across sub- disciplines. According to "Microsoft Academic Search" (a Microsoft initiative) all tracks of WORLDCOMP are listed as worldwide "Top-ranked Conferences" (based on various metrics but mainly based on the number of citations). You can access "Microsoft Academic Search" to extract citation data for each individual track of worldcomp using the following link: http://academic.research.microsoft.com/ As of March 4, 2011, the papers published in the proceeedings have received 14,385 citations which is a higher citation than many reputable journals in computer science. From newsfish@newsfish Tue Aug 9 07:52:55 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v31g2000vbs.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Only 11 More Days Until the Incessant Posting Ends Date: Sun, 20 Mar 2011 09:37:52 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300639073 19054 127.0.0.1 (20 Mar 2011 16:37:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 20 Mar 2011 16:37:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v31g2000vbs.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Firefox/3.6.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4859 Am I the only user of this group who does not appreciate the endless posting about the multi-conference being held in Las Vegas this summer? They seem to be having a couple of dozen conferences all in the same place on the same day. Sounds a little odd to me. Wouldn't it make more sense to have one conference that covers all the topics? I guess if they did that they couldn't post every other day without it being obvious. Instead the advertise each of the two dozen conferences once a month. BTW, who wants to go to Las Vegas in July??? If they want people to come, why didn't they pick a more seasonable time of year.... oh yeah, it would cost them more! At least the deadline for the call for papers is close at hand. Maybe then the advertising will slack off. Rick From newsfish@newsfish Tue Aug 9 07:52:55 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Sun, 20 Mar 2011 21:34:14 -0500 Lines: 16 Message-ID: <8unrp7Fm7aU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net e3StSbUiVbmuMuhLXQPADA6XdKr2M0qCL7IH5GV1dVuWIpAGQe Cancel-Lock: sha1:MmoWUM38zhH9tssq7tf1EBwtbWc= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.14) Gecko/20110221 Lightning/1.0b2 Thunderbird/3.1.8 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4860 On 3/20/2011 11:37 AM, rickman wrote: > Am I the only user of this group who does not appreciate the endless > posting about the multi-conference being held in Las Vegas this > summer? They seem to be having a couple of dozen conferences all in > the same place on the same day. Sounds a little odd to me. Wouldn't > it make more sense to have one conference that covers all the topics? > I guess if they did that they couldn't post every other day without it > being obvious. Instead the advertise each of the two dozen > conferences once a month. > > Rick You may "kill file" those messages. Check this option with your news reader. If you are using Google Groups there's no hope (I'm sorry). Al From newsfish@newsfish Tue Aug 9 07:52:55 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Mon, 21 Mar 2011 19:02:08 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <927d203a-b6bb-4816-b458-af7498101f32@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 70.16.209.40 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300759328 12199 127.0.0.1 (22 Mar 2011 02:02:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Mar 2011 02:02:08 +0000 (UTC) Cc: Alessandro Basili In-Reply-To: <8unrp7Fm7aU1@mid.individual.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.16.209.40; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4862 On Sunday, March 20, 2011 10:34:14 PM UTC-4, Alessandro Basili wrote: > On 3/20/2011 11:37 AM, rickman wrote: > > Am I the only user of this group who does not appreciate the endless > > posting about the multi-conference being held in Las Vegas this > > summer? They seem to be having a couple of dozen conferences all in > > the same place on the same day. Sounds a little odd to me. Wouldn't > > it make more sense to have one conference that covers all the topics? > > I guess if they did that they couldn't post every other day without it > > being obvious. Instead the advertise each of the two dozen > > conferences once a month. > > > > Rick > > You may "kill file" those messages. Check this option with your news reader. > If you are using Google Groups there's no hope (I'm sorry). > > Al Actually I'm using Google Groups and those messages are already hidden. I guess I have Rick to thank for that. -- Gabor From newsfish@newsfish Tue Aug 9 07:52:55 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d19g2000yql.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Mon, 21 Mar 2011 22:18:56 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <90ca38d3-17c8-415c-9b89-6fc4b05b6eb5@d19g2000yql.googlegroups.com> References: <927d203a-b6bb-4816-b458-af7498101f32@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1300771136 2066 127.0.0.1 (22 Mar 2011 05:18:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Mar 2011 05:18:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d19g2000yql.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Firefox/3.6.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4863 On Mar 21, 10:02=A0pm, Gabor Sz wrote: > On Sunday, March 20, 2011 10:34:14 PM UTC-4, Alessandro Basili wrote: > > On 3/20/2011 11:37 AM, rickman wrote: > > > Am I the only user of this group who does not appreciate the endless > > > posting about the multi-conference being held in Las Vegas this > > > summer? =A0They seem to be having a couple of dozen conferences all i= n > > > the same place on the same day. =A0Sounds a little odd to me. =A0Woul= dn't > > > it make more sense to have one conference that covers all the topics? > > > I guess if they did that they couldn't post every other day without i= t > > > being obvious. =A0Instead the advertise each of the two dozen > > > conferences once a month. > > > > Rick > > > You may "kill file" those messages. Check this option with your news re= ader. > > If you are using Google Groups there's no hope (I'm sorry). > > > Al > > Actually I'm using Google Groups and those messages > are already hidden. =A0I guess I have Rick to thank for > that. > > -- Gabor That's funny, I do flag them as spam, but they never seem to go away. The other spam tends to disappear. Oh, I am still using the older style interface. I tried the new groups interface and there all the spam goes away pretty quickly and anything I flag is gone immediately. I wonder why Google can't clear out the spam effectively from their standard interface while they do with the new interface. Rick From newsfish@newsfish Tue Aug 9 07:52:56 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin.stu.neva.ru!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!hq-usenetpeers.eweka.nl!81.171.88.15.MISMATCH!eweka.nl!lightspeed.eweka.nl!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Wed, 23 Mar 2011 12:28:32 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: <01090dfd-564b-4929-ad7e-63c7c4da86b5@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1300908512 15178 127.0.0.1 (23 Mar 2011 19:28:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 23 Mar 2011 19:28:32 +0000 (UTC) Cc: rickman In-Reply-To: <90ca38d3-17c8-415c-9b89-6fc4b05b6eb5@d19g2000yql.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4864 On Tuesday, March 22, 2011 1:18:56 AM UTC-4, rickman wrote: > On Mar 21, 10:02=A0pm, Gabor Sz wrote: > > On Sunday, March 20, 2011 10:34:14 PM UTC-4, Alessandro Basili wrote: > > > On 3/20/2011 11:37 AM, rickman wrote: > > > > Am I the only user of this group who does not appreciate the endles= s > > > > posting about the multi-conference being held in Las Vegas this > > > > summer? =A0They seem to be having a couple of dozen conferences all= in > > > > the same place on the same day. =A0Sounds a little odd to me. =A0Wo= uldn't > > > > it make more sense to have one conference that covers all the topic= s? > > > > I guess if they did that they couldn't post every other day without= it > > > > being obvious. =A0Instead the advertise each of the two dozen > > > > conferences once a month. > > > > > > Rick > > > > > You may "kill file" those messages. Check this option with your news = reader. > > > If you are using Google Groups there's no hope (I'm sorry). > > > > > Al > > > > Actually I'm using Google Groups and those messages > > are already hidden. =A0I guess I have Rick to thank for > > that. > > > > -- Gabor >=20 > That's funny, I do flag them as spam, but they never seem to go away. > The other spam tends to disappear. Oh, I am still using the older > style interface. I tried the new groups interface and there all the > spam goes away pretty quickly and anything I flag is gone > immediately. >=20 > I wonder why Google can't clear out the spam effectively from their > standard interface while they do with the new interface. >=20 > Rick Well they don't really go away. They're just "hidden" in plain sight. Still a bit less annoying that seeing the bold uppercase thread titles... -- Gabor From newsfish@newsfish Tue Aug 9 07:52:56 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!feeder.news-service.com!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Wed, 23 Mar 2011 22:30:00 -0500 Lines: 44 Message-ID: <8uvs5nFq7kU1@mid.individual.net> References: <01090dfd-564b-4929-ad7e-63c7c4da86b5@glegroupsg2000goo.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net tbGc6wZ4DEWlKTz9AFYAaQmpxJK6ZJm/l7bR3jvGToj/3DVjIN Cancel-Lock: sha1:OwJQo2pNbewPnjTude3mIH/OUIY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: <01090dfd-564b-4929-ad7e-63c7c4da86b5@glegroupsg2000goo.googlegroups.com> X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4865 On 3/23/2011 2:28 PM, Gabor Sz wrote: > On Tuesday, March 22, 2011 1:18:56 AM UTC-4, rickman wrote: >> On Mar 21, 10:02 pm, Gabor Sz wrote: [snip] >> >> That's funny, I do flag them as spam, but they never seem to go away. >> The other spam tends to disappear. Oh, I am still using the older >> style interface. I tried the new groups interface and there all the >> spam goes away pretty quickly and anything I flag is gone >> immediately. >> >> I wonder why Google can't clear out the spam effectively from their >> standard interface while they do with the new interface. >> >> Rick > > Well they don't really go away. They're just "hidden" > in plain sight. Still a bit less annoying that seeing > the bold uppercase thread titles... > > -- Gabor FYI there is an interesting article with a tentative explanation of why GG does not work so effectively on SPAM: http://ejohn.org/blog/google-groups-is-dead/ I disagree with the claim that GG is dead, but I believe GG hit the usenet community really bad, giving a false impression to newbies about what is a newsgroup at large. You may also read "current usenet spam threshold and guidelines" (), which gives you an idea of how the newsgroup administrators deal with the spam. Given the BI of the post the OP was complaining about, there's no chance any newsgroup, nor GG may flag that post as spam. Nevertheless with your newsreader you may easily "kill file" it. Al p.s.: Gabor if you find the time please read the "Common questions about using newsgroups" (), especially Q6 and the related A6 From newsfish@newsfish Tue Aug 9 07:52:56 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Thu, 24 Mar 2011 07:25:39 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <5c7c53b4-a3ee-4428-b072-d42c07de6a12@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300976739 22006 127.0.0.1 (24 Mar 2011 14:25:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 24 Mar 2011 14:25:39 +0000 (UTC) Cc: Alessandro Basili In-Reply-To: <8uvs5nFq7kU1@mid.individual.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4866 On Wednesday, March 23, 2011 11:30:00 PM UTC-4, Alessandro Basili wrote: [snip] > p.s.: Gabor if you find the time please read the "Common questions about > using newsgroups" (), > especially Q6 and the related A6 I suppose if I used a newsreader instead of Google Groups, then I could find the topic you posted the "link" to. -- Gabor From newsfish@newsfish Tue Aug 9 07:52:56 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "scrts" Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Sun, 27 Mar 2011 13:47:45 +0300 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <5c7c53b4-a3ee-4428-b072-d42c07de6a12@glegroupsg2000goo.googlegroups.com> Injection-Date: Sun, 27 Mar 2011 10:47:54 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="PCoXu+X2HClsEvAir5PNww"; logging-data="24162"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IfbQId5oPAvNxX0lsAOnl" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5994 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:6pLzYExBcl2ivYy72+Xkz3AJW3w= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:4867 > I suppose if I used a newsreader instead of Google Groups, > then I could find the topic you posted the "link" to. I use Outlook Express to read the news and also Google Groups via news.eternal-september.org. Registration is easy, I see no spam and also threaded messages is a huge advantage instead of web interface. Tomas D. From newsfish@newsfish Tue Aug 9 07:52:56 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Mon, 28 Mar 2011 15:58:24 -0400 Organization: Alacron, Inc. Lines: 20 Message-ID: References: <5c7c53b4-a3ee-4428-b072-d42c07de6a12@glegroupsg2000goo.googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Mar 2011 19:57:50 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="SUqs68xEs9YfAtSSdphhXg"; logging-data="29686"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18jg33wB7y0RqYvX1AxbIMl" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:vQKxyYZtLD21MhssxBn3thfSMiY= Xref: feeder.eternal-september.org comp.lang.vhdl:4868 scrts wrote: >> I suppose if I used a newsreader instead of Google Groups, >> then I could find the topic you posted the "link" to. > > I use Outlook Express to read the news and also Google Groups via > news.eternal-september.org. Registration is easy, I see no spam and also > threaded messages is a huge advantage instead of web interface. > > Tomas D. > > O.K. I'll give "Eternal September" a shot. This is posted via Thunderbird. Still from within TB I can see the links to but clicking on them doesn't do anything. With any luck, though this method doesn't send the reply to each author in addition to the group... Regards, Gabor From newsfish@newsfish Tue Aug 9 07:52:57 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q12g2000prb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Synthesis of Logic on Non-boolean Constants Date: Tue, 29 Mar 2011 09:13:18 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301415199 13923 127.0.0.1 (29 Mar 2011 16:13:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 16:13:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q12g2000prb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4869 I was using some logic to shorten typing of some operations where I was trying to create tristate drivers. To be sure of the result I looked up the logic tables and found that, for example the OR function on a constant 'z' and a signal produces a '1' when the signal is a '1', but when the signal is a zero results in an 'x'. This is not the same as a 'z' obviously, which is what I wanted. Clearly this is not a good idea even if it is shorter to type. But I realized, how do I know what will be synthesized by this expression? Then I came to my senses and realized I just needed to use the IF statement and not worry about brevity. Reading the sysnthesis standard 1076.6 it says, 'Three-state logic shall be modeled when an object, or an element of the object, is explicitly assigned the IEEE Std 1164-1993 value =93Z.=94 The assignment to =93Z=94 shall be a conditional assignment; that is, assignment occurs under the control of a condition.' So trying to get a logic function to do the job of a conditional assignment just won't work, eh? Rick From newsfish@newsfish Tue Aug 9 07:52:57 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feed.cnntp.org!news.cnntp.org!weretis.net!feeder4.news.weretis.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!a21g2000prj.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 09:42:05 -0700 (PDT) Organization: http://groups.google.com Lines: 86 Message-ID: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301416926 32678 127.0.0.1 (29 Mar 2011 16:42:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 16:42:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a21g2000prj.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4870 Hello folks, I'm posting this in hopes that folks have some suggestions on how to handle this in a clean way. I find myself (not surprisingly) writing testbenches for a lot of very similar bus interfaces. At the simplest I've got an address signal, data out, data in, and a write enable signal. On a more complex one I might have the full backend interface to the Actel PCI core or the Altera Avalon interface. Regardless, I would really like to be able to write my basic interaction procedures once and just use them after that. However I'm running into some difficulty with the language and scoping rules. So for talking purposes, here's a little skeleton use work.generic_bus_if_pkg.all; -- entity just_a_testbench is end entity just_a_testbench; architecture behavioral of just_a_testbench is signal be_addr : unsigned(15 downto 0); signal be_rddata : std_logic_vector(31 downto 0); signal be_wrdata : std_logic_vector(31 downto 0); signal be_wren : std_logic; begin DUT : entity work.foo port map ( .... be_addr => be_addr, be_rddata => be_rddata, be_wrdata => be_wrdata, be_wren => be_wren, .... ); BUS_CONTROL : process is begin ..... be_read32(); be_write32(); ..... end process BUS_CONTROL; end architecture behavioral; Alright, I think that's enough to give an idea. So I'd really like my procedure calls to be something I can abstract preferably into a package. Also I'd really like to keep the parameter list as minimal as possible. However I run into scope issues with signals. So if I use region A for declaring my read/write procedures, I can directly access all the signals running into the DUT. I don't have to pass them in. I can simply have an address and data parameters. However this means every testbench has to declare everything right there in the process and that's ugly to me. Now if I use B or C, then I no longer have scope on the signals. If I want to use a procedure for reading and writing, I've got to pass them into the procedure. With the example described, it's not really too big a deal, but consider a PCI interface with all its myriad signals or another example various PCI core backend interfaces with start, stop, rdcyc, wrcyc, and various other signals for backpressure. It seems to me that the parameter list could get unwieldy very quickly. So I can put the procedures here, but that violates my desire to have manageable calls. So, I'm hoping there's some sort of clever way of passing a bus in and out of procedure declarations to keep code readable and maintainable. The only way I've thought that might work is to declare a record that comprises the entire bus interface. Then I could pass in a single token that represents the entire bus. I haven't really worked out how that might work with different naming conventions (I'm usually pretty consistent with signal names, but sometimes there are variations.) There are very likely other ways to do it, but I haven't had a lot of exposure to folks who do large scale testbenches and have already worked out these tricks. So, in summary does anyone have any technique or best practice for how to organize bus interfaces for passing in and out of procedure calls? Thanks for any ideas. I appreciate it. Best regards, Mark Norton From newsfish@newsfish Tue Aug 9 07:52:57 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 12:24:19 -0700 Lines: 25 Message-ID: <8vepu0FtmdU1@mid.individual.net> References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 9JQ4bnYQHgVEuhEOxUJfrg0t++FqLk14ES37c018+Oe23nhxxZ Cancel-Lock: sha1:fas9PZQmC52Vh71QXVFUxFjXK9g= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4871 On 3/29/2011 9:42 AM, M. Norton wrote: > So, I'm hoping there's some sort of clever way of passing a bus in and > out of procedure declarations to keep code readable and maintainable. I haven't seen it, if we include the "readable" part. I like to use variables and procedures and minimize processes. Something like: ... constant reps : natural := 8; begin -- process main: Top level loop invokes top procedures. init; for i in 1 to reps loop timed_cycle; end loop; for i in 1 to reps loop handshake_cycle; end loop; coda; end process main; for details, see the testbench here: http://mysite.ncnetwork.net/reszotzl/ -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:52:57 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!17g2000prr.googlegroups.com!not-for-mail From: Vikram Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl,comp.dsp,comp.arch.embedded Subject: only 7 days to go - 4th FPGA Camp - 6'Apr 2011 Silicon Valley Date: Tue, 29 Mar 2011 12:42:22 -0700 (PDT) Organization: http://groups.google.com Lines: 47 Message-ID: <67767519-7edb-4527-b11c-91fa658bdeee@17g2000prr.googlegroups.com> NNTP-Posting-Host: 8.4.225.30 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301427743 17061 127.0.0.1 (29 Mar 2011 19:42:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 19:42:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 17g2000prr.googlegroups.com; posting-host=8.4.225.30; posting-account=ROblUgoAAABUCieY-adRND7iPJOdhLol User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:15063 comp.lang.verilog:2931 comp.lang.vhdl:4872 comp.dsp:29489 comp.arch.embedded:20883 FPGA Camp (http://www.fpgacentral.com/fpgacamp) is a conference, which brings engineers together to discuss FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories. Since its inception in Year 2009, FPGA Camp decided to stay vendor neutral. The attendance is completely FREE and so is putting up a booth. Due to the this approach we soon have been coined as an Open Source conference by Industry leaders like Eric Bogatin, Colin Warwick & Max Maxfield. REGISTER NOW http://bit.ly/fcjHCJ The event will focus on demonstrating key technologies available to bring processor inside the FPGAs. It will provide a glimpse of what to expect in the future, and how to use these great features for your next project. AGENDA (visit http://www.fpgacentral.com/fpgacamp for details) 4:00 PM Exhibit booths 4:25 PM Introductions 4:30 PM Tech Talk 1: On Die Instrumentation 5:05 PM Tech Talk 2: PCIe 3.0 case study 5:40 PM Tech Talk 3: Design Choices for Embedded Real-Time Control Systems 6:15 PM Dinner & Exhibit 6:45 PM Vendor Presentation 7:00 PM Panel: "State Of FPGAs - Current & Future" - Moderated by Dave Orecchio, CEO, Gaterocket 8:15 PM Closing Speakers & Moderator Dave Orecchio - GateRocket Gordon Hands - Lattice Chris Eddington - Synopsys Dave Bursky - Chip Design Magazine and more... Sponsors Lattice Semiconductor Altium Rhino Labs Agilent Technologies IEEE CNSV PLDA REGISTER NOW http://bit.ly/fcjHCJ (registration is FREE & Simple) Organized by: FPGA Cenral ( http://www.fpgacentral.com ) From newsfish@newsfish Tue Aug 9 07:52:57 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k3g2000prl.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 12:51:19 -0700 (PDT) Organization: http://groups.google.com Lines: 95 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301428279 22108 127.0.0.1 (29 Mar 2011 19:51:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 19:51:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k3g2000prl.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4873 On Mar 29, 11:42=A0am, "M. Norton" wrote: > Hello folks, > > I'm posting this in hopes that folks have some suggestions on how to > handle this in a clean way. =A0I find myself (not surprisingly) writing > testbenches for a lot of very similar bus interfaces. =A0At the simplest > I've got an address signal, data out, data in, and a write enable > signal. =A0On a more complex one I might have the full backend interface > to the Actel PCI core or the Altera Avalon interface. > > Regardless, I would really like to be able to write my basic > interaction procedures once and just use them after that. =A0However I'm > running into some difficulty with the language and scoping rules. =A0So > for talking purposes, here's a little skeleton > > use work.generic_bus_if_pkg.all; -- preferred> > > entity just_a_testbench is > end entity just_a_testbench; > > architecture behavioral of just_a_testbench is > =A0 =A0 =A0 > =A0 =A0 =A0signal be_addr : unsigned(15 downto 0); > =A0 =A0 =A0signal be_rddata : std_logic_vector(31 downto 0); > =A0 =A0 =A0signal be_wrdata : std_logic_vector(31 downto 0); > =A0 =A0 =A0signal be_wren : std_logic; > begin > =A0 =A0 DUT : entity work.foo > =A0 =A0 =A0 =A0 =A0port map ( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 .... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 be_addr =3D> be_addr, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 be_rddata =3D> be_rddata, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 be_wrdata =3D> be_wrdata, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 be_wren =3D> be_wren, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 .... > =A0 =A0 =A0 =A0 =A0); > > =A0 =A0 =A0BUS_CONTROL : process is > =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 =A0 =A0..... > =A0 =A0 =A0 =A0 =A0 =A0be_read32(); > =A0 =A0 =A0 =A0 =A0 =A0be_write32(); > =A0 =A0 =A0 =A0 =A0 =A0..... > =A0 =A0 =A0end process BUS_CONTROL; > > end architecture behavioral; > > Alright, I think that's enough to give an idea. =A0So I'd really like my > procedure calls to be something I can abstract preferably into a > package. =A0Also I'd really like to keep the parameter list as minimal > as possible. =A0However I run into scope issues with signals. =A0So if I > use region A for declaring my read/write procedures, I can directly > access all the signals running into the DUT. =A0I don't have to pass > them in. =A0I can simply have an address and data parameters. =A0However > this means every testbench has to declare everything right there in > the process and that's ugly to me. > > Now if I use B or C, then I no longer have scope on the signals. =A0If I > want to use a procedure for reading and writing, I've got to pass them > into the procedure. =A0With the example described, it's not really too > big a deal, but consider a PCI interface with all its myriad signals > or another example various PCI core backend interfaces with start, > stop, rdcyc, wrcyc, and various other signals for backpressure. =A0It > seems to me that the parameter list could get unwieldy very quickly. > So I can put the procedures here, but that violates my desire to have > manageable calls. > > So, I'm hoping there's some sort of clever way of passing a bus in and > out of procedure declarations to keep code readable and maintainable. > The only way I've thought that might work is to declare a record that > comprises the entire bus interface. =A0Then I could pass in a single > token that represents the entire bus. =A0I haven't really worked out how > that might work with different naming conventions (I'm usually pretty > consistent with signal names, but sometimes there are variations.) > There are very likely other ways to do it, but I haven't had a lot of > exposure to folks who do large scale testbenches and have already > worked out these tricks. > > So, in summary does anyone have any technique or best practice for how > to organize bus interfaces for passing in and out of procedure calls? > > Thanks for any ideas. =A0I appreciate it. > > Best regards, > Mark Norton I've used a single record with an inout port on the procedure(s). All of the elements of the record must be resolved types. I declare an "undriven" constant of that record such that the elements that are never used as outputs by each process are harmlessly driven to 'Z'. Andy From newsfish@newsfish Tue Aug 9 07:52:57 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!f15g2000pro.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 13:26:55 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <9e56f7c7-02de-45b5-8233-b640dcc12295@f15g2000pro.googlegroups.com> References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> <8vepu0FtmdU1@mid.individual.net> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301430415 18489 127.0.0.1 (29 Mar 2011 20:26:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 20:26:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f15g2000pro.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4874 On Mar 29, 2:24=A0pm, Mike Treseler wrote: > I haven't seen it, if we include the "readable" part. > I like to use variables and procedures and minimize processes. > Something like: ... > for details, see the testbench here:http://mysite.ncnetwork.net/reszotzl/ Yeah, this is essentially what I'm doing right now, one process describing test over time (with loops and whatnot as need requires) and then a lot of local procedures to handle the transactions. The only trouble I've got is that I end up repeating myself quite a lot over a number of testbenches that use identical or more-likely near- identical protocols. All it takes is a few names changed and my cut and paste of previously written transaction procedures gets smoked. I suppose I'm glad to know I'm not too far off in what I've come up with but it'd be nice to find something that's more reusable. Thanks for the information! Mark From newsfish@newsfish Tue Aug 9 07:52:58 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v11g2000prb.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 13:36:13 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301430973 17243 127.0.0.1 (29 Mar 2011 20:36:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 20:36:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v11g2000prb.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4875 On Mar 29, 2:51=A0pm, Andy wrote: > I've used a single record with an inout port on the procedure(s). All > of the elements of the record must be resolved types. I declare an > "undriven" constant of that record such that the elements that are > never used as outputs by each process are harmlessly driven to 'Z'. I've read and reread this a bit and while I get the theory of what you're doing with the constant, I'm not sure how it's being applied. So if we've got a package with a record containing the signal elements of a bus, including control lines, that would allow harnessing up a generic procedure to a testbench component. However when do you apply the constant that's got things set to high impedance? Does that happen inside the procedure at the beginning of the procedure and then subsequent assignments override it? So, possibly something like this? procedure my_generic_write( ... ; signal my_bus : T_BUS_RECORD; ... ) is begin my_bus <=3D C_HARMLESSLY_DRIVEN_TO_Z; wait until rising_edge(some_clk); my_bus.address <=3D some_address; my_bus.wr_cyc <=3D '1'; wait until rising_edge(some_clk); my_bus.data <=3D some_data; my_bus.wren <=3D '1'; wait until rising_edge(some_clk); my_bus_wren <=3D '0'; wait until rising_edge(some_clk); my_bus.wr_cyc <=3D '0'; wait until rising_edge(some_clk); my_bus <=3D C_HARMLESSLY_DRIVEN_TO_Z; end procedure my_generic_write; Then during that procedure call, all the my_bus.rd_cyc, my_bus.rd_stb, etc would remain Z. I will have to try that out and see how it goes. Seems like it might do what I want (assuming I have your intent divined correctly). Thanks for the information! Mark From newsfish@newsfish Tue Aug 9 07:52:58 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!e21g2000yqe.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Tue, 29 Mar 2011 14:00:52 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <551ae42e-f669-41cd-aef2-8fa60508a8fc@e21g2000yqe.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301432452 8128 127.0.0.1 (29 Mar 2011 21:00:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 21:00:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000yqe.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4876 Using an existing operator may not work, but you could write a function that encapsulates the conditional assignment. For example: ts_out <= bufz(input, enable); You could also overload bufz() for SL and SLV inputs & return values (and SL and SLV [bitwise] enables). Andy From newsfish@newsfish Tue Aug 9 07:52:58 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 22:08:46 +0100 Organization: A noiseless patient Spider Lines: 228 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="8624"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/A+mmnLZMxVSV7n3d90Eac0U2fyY7A798=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:kZB88h36cMNT2FV42xUedVjA/q0= Xref: feeder.eternal-september.org comp.lang.vhdl:4877 On Tue, 29 Mar 2011 09:42:05 -0700 (PDT), "M. Norton" wrote: >I'm posting this in hopes that folks have some suggestions on how to >handle this in a clean way. I find myself (not surprisingly) writing >testbenches for a lot of very similar bus interfaces.[...] >I would really like to be able to write my basic >interaction procedures once and just use them after that. However I'm >running into some difficulty with the language and scoping rules. Yup. >Alright, I think that's enough to give an idea. So I'd really like my >procedure calls to be something I can abstract preferably into a >package. Also I'd really like to keep the parameter list as minimal >as possible. But, as you've found, a procedure in a package can only hit signals through its arguments (parameters). Which may be numerous, for any reasonably complex model. There are other issues too. Your bus model probably needs to keep track of some persistent state, which you can't comfortably do with a package either. So, here's what I would regard as the preferred way to start. Others will doubtless have different opinions, of course. First off, consider encapsulating your bus model not as a package but as an entity. That way it can have persistent PER-INSTANCE state, i.e. you can use the same model for numerous different buses in the same testbench with no difficulty. And you can provide ports on the entity that will connect to the physical pins of your interface. As a super-simple example we can model an asynchronous serial data (UART) protocol where the DUT is a receiver, and your testbench is the transmitter. So the physical interface is just two wires: TxD from TB to DUT, and CTS (Clear to Send) from DUT to TB. Something like this (yes I know it's no use like this: bear with me as I build up the example.) Lots of details and declarations missing, but I'm sure you can fill it all in yourself. entity UART_TX_incomplete is port ( TXD: out std_logic; -- to DUT CTS: in std_logic ); -- from DUT end; architecture incomplete of UART_TX_incomplete is begin Transmitter: process procedure Tx(bit_to_send: std_logic); begin TXD <= bit_to_send; wait for BIT_TIME; end; procedure Tx(byte_to_send: unsigned(7 downto 0)); begin wait until CTS = '1'; -- handshake Tx('0'); -- start bit for i in byte_to_send'reverse_range loop Tx(byte_to_send(i)); -- LSB first end loop; Tx('1'); -- stop bit end; begin end process; -- eh??? nothing in this process!!! end; OK, this is cool; we just create an instance of this thing, hook its ports to our DUT interface, and, errm, call the procedure... oh dear, we can't because the procedure is hidden away inside a process, inside the instance. So, how do we call that procedure from OUTSIDE the UART_TX entity? Answer: provide a port on said entity that allows your testbench to command it to do things. This port won't connect to DUT wires; it will be hooked to a very abstract signal in the TB, conveying commands. So we can usefully create a record type that represents a command. In our case that's kinda simple (just a byte) but you get the idea. While we're writing a package that defines this record, we can also write a procedure to encapsulate the whole business of getting the UART_TX to do something for us. package UART_TB_CONTROL_pkg is type UART_TB_CONTROL_RECORD is record info: unsigned(7 downto 0); end record; procedure send_message( data_to_send: unsigned(7 downto 0); signal request: out UART_TB_CONTROL_RECORD; signal response: in boolean ); begin -- issue command to UART_TX request.info <= data_to_send; -- wait for response signal to toggle wait on response; end endpackage Now, of course, we must modify our UART_TX so that it can cope with this request/response protocol. That costs a couple more ports, but thanks to the record type, there will ONLY be two such ports no matter how complex the protocol. entity UART_TX is port ( TXD: out std_logic; -- signals to DUT CTS: in std_logic; -- signals from DUT REQ: in UART_TB_CONTROL_RECORD; RSP: out boolean); end; architecture OK of UART_TX is signal response_toggle: boolean; begin Transmitter: process procedure Tx(bit_to_send: std_logic); begin TXD <= bit_to_send; wait for BIT_TIME; end; procedure Tx(byte_to_send: unsigned(7 downto 0)); begin wait until CTS = '1'; -- handshake Tx('0'); -- start bit for i in byte_to_send'reverse_range loop Tx(byte_to_send(i)); -- LSB first end loop; Tx('1'); -- stop bit end; begin -- here's the management process -- Wait for the TB to request a new action wait on REQ'transaction; -- Implement the requested action Tx(REQ.info); -- Indicate completion response_toggle <= not response_toggle; -- then loop back to wait for next command end process; -- Echo out the response indication RSP <= response_toggle; end; Now we're really ready to go. In your TB, create an instance of UART_TX with its TXD and CTS signals connected up to the DUT in the obvious way. Of course, in your real world there will be many more signals than two - but the same principles apply. Then, in the TB, provide signals for the REQ and RSP ports of your UART_TX instance. And then a process in the TB can generate stimulus like this: send_many_characters: process variable L: line; -- to get stimulus data from a file? variable Ch: character; variable V: unsigned(7 downto 0); begin -- Read L from a file using usual textio stuff. -- Or anything else to get some interesting data. -- Then, send the characters stored in L to the UART: for i in L'range loop Ch := L(i); V := to_unsigned(character'pos(Ch), V'length); send_message(V, REQ_signal, RSP_signal); end loop; end process; Now the send_message procedure (defined in the package) has only a small number of arguments, regardless of the complexity of your physical interface - the complexity is abstracted-away in the transaction record type. If you find yourself calling the procedure send_message() many times in the same process, with the same signal arguments every time, you can tidy that up too: process .... -- Simplified local version of the package procedure procedure send_message(V: unsigned(7 downto 0); begin -- Call the package procedure, with appropriate -- signals provided as arguments. These signals -- must be declared in the architecture, of course. send_message(V, REQ_signal, RSP_signal); end; begin -- main body of process -- calls the local procedure, which fills in the signals send_message("00001111"); -- it's that simple send_message("10101010"); ... I'm aware that this example has been quite sketchy, and uses some "advanced" (whatever that means) tricks like 'transaction, but I hope at least it points you in some interesting directions. Many details yet to fill in - initialization, declarations, you name it. Over to you. You can make this work the other way, too, for models that monitor (rather than drive) a DUT interface. Same idea applies: convert the messy signal-wiggles into a transaction record, and work with that in the TB. Capture the signal-to-record converter block as an entity, instantiate it with ports connected to DUT signals and just a couple of ports to expose the collected transaction record. Hook up those latter ports to TB-only signals so that the rest of the TB can see them. There are several interesting variants on this theme: for example, the blocks can be coded as procedures and "instanced" as concurrent procedure calls. That's convenient, but it causes some trouble with the 'transaction trickery, so personally I prefer to use entities. Enjoy, and thanks for asking all the right questions. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:52:58 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!cu4g2000vbb.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 14:42:16 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301434936 24183 127.0.0.1 (29 Mar 2011 21:42:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 21:42:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: cu4g2000vbb.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4878 On Mar 29, 4:08=A0pm, Jonathan Bromley wrote: > There are other issues too. =A0Your bus model probably > needs to keep track of some persistent state, which > you can't comfortably do with a package either. Glad you mentioned this. I hadn't even gotten to the point where I was concerned about persistent state. My initial examples were pretty straightforward and simple, but I do have in mind trying to create a PCI bus model to try to test this core we seem to be using and reusing and that absolutely would be a far more complex driver and would require persistent state for some transactions. > I'm aware that this example has been quite sketchy, > and uses some "advanced" (whatever that means) > tricks like 'transaction, but I hope at least > it points you in some interesting directions. > Many details yet to fill in - initialization, > declarations, you name it. =A0Over to you. Absolutely, sketchy is fine. I'm looking for theory mainly and this has given me a lot to chew on. In the past I have used entities as DUT drivers, usually for complex packet data, but I hadn't really thought of abstracting it a level further and giving myself command hooks into it. This also neatly dodges the issue of clocks. I was thinking about that when I wrote the little snippet asking about what Andy suggested, and was realizing I would need to pass in the clock as well as everything else, which seems a little on the messy side. Ideally the procedure call would be transaction and message related information only. And having a variety of tools in the toolbox is never a bad thing. Seems to me there's times when Mike's strategy is simplest, and then Andy's and then this feels like the sledgehammer. > Enjoy, and thanks for asking all the right questions. I appreciate it. Best regards, Mark From newsfish@newsfish Tue Aug 9 07:52:58 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d16g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Tue, 29 Mar 2011 20:55:51 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <551ae42e-f669-41cd-aef2-8fa60508a8fc@e21g2000yqe.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301457352 22420 127.0.0.1 (30 Mar 2011 03:55:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 03:55:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d16g2000yqd.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4879 On Mar 29, 5:00=A0pm, Andy wrote: > Using an existing operator may not work, but you could write a > function that encapsulates the conditional assignment. > > For example: > ts_out <=3D bufz(input, enable); > > You could also overload bufz() for SL and SLV inputs & return values > (and SL and SLV [bitwise] enables). > > Andy I found something that seems odd to me. I often forget details of a language when it is something that I don't use very often. I thought that VHDL did not care about case in all situations. But in the case of std_logic it would seem to care if the values assigned are 'x' or 'X' and 'z' or 'Z'! I was getting errors on assignments and comparisons along with a seemingly unrelated error in a separate file having to do with some intermediate conversion step that didn't involve the source code. When I changed the case to upper for the literals, it all worked again. I guess all these years I haven't made the mistake of using lower case for these values or possibly the other tools I've used don't care about the difference. Rick From newsfish@newsfish Tue Aug 9 07:52:58 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 21:45:51 -0700 Lines: 24 Message-ID: <8vfqqrFp4oU1@mid.individual.net> References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> <8vepu0FtmdU1@mid.individual.net> <9e56f7c7-02de-45b5-8233-b640dcc12295@f15g2000pro.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net fa/uySOQgYqXNGq+MNWi2gg7NLLUqeqTDNqYlg8uWgfwjB5KPu Cancel-Lock: sha1:FOSF/8auqy3HV0oTNY6K/0cTJaI= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: <9e56f7c7-02de-45b5-8233-b640dcc12295@f15g2000pro.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4880 On 3/29/2011 1:26 PM, M. Norton wrote: > Yeah, this is essentially what I'm doing right now, one process > describing test over time (with loops and whatnot as need requires) > and then a lot of local procedures to handle the transactions. The > only trouble I've got is that I end up repeating myself quite a lot > over a number of testbenches that use identical or more-likely near- > identical protocols. All it takes is a few names changed and my cut > and paste of previously written transaction procedures gets smoked. I try to do the heavy lifting in functions, which are easily packaged with required and default parameters. I use simple procedures with no parameters when possible for readable code. > I suppose I'm glad to know I'm not too far off in what I've come up > with but it'd be nice to find something that's more reusable. Thanks > for the information! Functions are easily packaged and reused. Procedures can at least eliminate the local cut and paste. -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:52:59 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!r13g2000yqk.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Wed, 30 Mar 2011 05:43:33 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <551ae42e-f669-41cd-aef2-8fa60508a8fc@e21g2000yqe.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301489013 15431 127.0.0.1 (30 Mar 2011 12:43:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 12:43:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r13g2000yqk.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 17j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4881 On Mar 30, 4:55=A0am, rickman wrote: > I found something that seems odd to me. =A0I often forget details of a > language when it is something that I don't use very often. =A0I thought > that VHDL did not care about case in all situations. =A0But in the case > of std_logic it would seem to care if the values assigned are 'x' or > 'X' and 'z' or 'Z'! =A0I was getting errors on assignments and > comparisons along with a seemingly unrelated error in a separate file > having to do with some intermediate conversion step that didn't > involve the source code. =A0When I changed the case to upper for the > literals, it all worked again. > > I guess all these years I haven't made the mistake of using lower case > for these values or possibly the other tools I've used don't care > about the difference. heh! VHDL is completely case-insensitive BUT the values 'X', '0' etc for std_logic are in fact CHARACTER LITERALS and therefore they ARE case-sensitive. 'z' is not one of the literals in the std_(u)logic set of 9 values. By contrast, if you have an enumeration type (like for a state machine) then the values of that type are ordinary VHDL identifiers like IDLE_STATE and they are NOT case-sensitive. You can use character literals as the enumeration values in your own enum types if you wish... type foo is ('a', 'b', 'c'); but almost no-one ever does that. And the really funny thing is... Verilog is a case-sensitive language in every respect, EXCEPT that its numeric bit values X and Z (and its radix specifiers 'b, 'h etc) are NOT case sensitive. Exactly the opposite way round from VHDL. Any tool that gets this wrong is non-compliant; it must simply be that you've not made that mistake before. I blame your exposure to Verilog :-) -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:52:59 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s11g2000yqh.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Wed, 30 Mar 2011 05:49:54 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301489395 14173 127.0.0.1 (30 Mar 2011 12:49:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 12:49:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s11g2000yqh.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9396) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4882 On 29 Mrz., 18:13, rickman wrote: > I was using some logic to shorten typing of some operations where I > was trying to create tristate drivers. =A0To be sure of the result I > looked up the logic tables and found that, for example the OR function > on a constant 'z' and a signal produces a '1' when the signal is a > '1', but when the signal is a zero results in an 'x'. =A0This is not the > same as a 'z' obviously, which is what I wanted. =A0Clearly this is not > a good idea even if it is shorter to type. So want the technology to contain a buffer that has an high impedance output in case of one input is high impedance? But else the output needs to be low impedance either driving '0' or '1'. Seems quite unusual to be found in any tech library. Your problems seems to me not vhdl related, instead you need to think in dedicated hardware functionality. It is quite easy to construct a logic function in vhdl that helps your need for simulation purpose, but quite a hard job, to build the needed transistor structure to implement the vhdl in real silicon. best regards Thomas From newsfish@newsfish Tue Aug 9 07:52:59 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a26g2000vbo.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Wed, 30 Mar 2011 07:57:11 -0700 (PDT) Organization: http://groups.google.com Lines: 71 Message-ID: <7b29c505-eb6c-486c-87bc-43e5652ac3b6@a26g2000vbo.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <551ae42e-f669-41cd-aef2-8fa60508a8fc@e21g2000yqe.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301497031 638 127.0.0.1 (30 Mar 2011 14:57:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 14:57:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a26g2000vbo.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4883 On Mar 30, 8:43=A0am, Jonathan Bromley wrote: > On Mar 30, 4:55=A0am, rickman wrote: > > > I found something that seems odd to me. =A0I often forget details of a > > language when it is something that I don't use very often. =A0I thought > > that VHDL did not care about case in all situations. =A0But in the case > > of std_logic it would seem to care if the values assigned are 'x' or > > 'X' and 'z' or 'Z'! =A0I was getting errors on assignments and > > comparisons along with a seemingly unrelated error in a separate file > > having to do with some intermediate conversion step that didn't > > involve the source code. =A0When I changed the case to upper for the > > literals, it all worked again. > > > I guess all these years I haven't made the mistake of using lower case > > for these values or possibly the other tools I've used don't care > > about the difference. > > heh! =A0VHDL is completely case-insensitive > BUT the values 'X', '0' etc for std_logic > are in fact CHARACTER LITERALS and therefore > they ARE case-sensitive. =A0'z' is not one of > the literals in the std_(u)logic set of 9 > values. =A0By contrast, if you have an > enumeration type (like for a state machine) > then the values of that type are ordinary > VHDL identifiers like IDLE_STATE and they > are NOT case-sensitive. =A0You can use character > literals as the enumeration values in your > own enum types if you wish... > =A0 =A0type foo is ('a', 'b', 'c'); > but almost no-one ever does that. > > And the really funny thing is... Verilog is a > case-sensitive language in every respect, > EXCEPT that its numeric bit values X and Z > (and its radix specifiers 'b, 'h etc) are > NOT case sensitive. =A0Exactly the opposite > way round from VHDL. > > Any tool that gets this wrong is non-compliant; > it must simply be that you've not made that mistake > before. =A0I blame your exposure to Verilog :-) > -- > Jonathan Bromley Nice try, but my exposure to Verilog is pretty minimal in this context. :^p Actually, if this test bench and test fixture hadn't already been coded in VHDL, I would have likely done it in Verilog as a further part of my exploration into Verilog. I did a small project a month or two ago and was pretty happy with Verilog. Test benches are an area in Verilog I want to explore further. The test bench I did for the project was pretty limited, reading some hex values from a file to drive an SPI port. This test bench is a lot more complicated having to read commands as well as numerical data from a file. It also has a lot more going on requiring synchronization between all the parts. I have a CPU design that I may be returning to later this year. I'm thinking of recoding it to improve efficiency and may swing a Verilog bat at that pitch. Who knows, I may hit a home run! I also want to explore the Silicon Blue devices a bit more and will likely try their parts to test the implementation. I don't recall much about their eval board, but I think they are a bit pricey. I may use one of those super low cost PCB services like DorkbotPDX to create my own board. There is another part from Green Arrays that I might want to explore as well. Rick From newsfish@newsfish Tue Aug 9 07:52:59 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.albasani.net!feeder.news-service.com!xlned.com!feeder5.xlned.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!r6g2000vbo.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Wed, 30 Mar 2011 08:04:25 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <67270d79-5df2-40e8-86e7-31d915ec7c85@r6g2000vbo.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301497466 5614 127.0.0.1 (30 Mar 2011 15:04:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 15:04:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r6g2000vbo.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4884 On Mar 30, 8:49=A0am, Thomas Stanka wrote: > On 29 Mrz., 18:13, rickman wrote: > > > I was using some logic to shorten typing of some operations where I > > was trying to create tristate drivers. =A0To be sure of the result I > > looked up the logic tables and found that, for example the OR function > > on a constant 'z' and a signal produces a '1' when the signal is a > > '1', but when the signal is a zero results in an 'x'. =A0This is not th= e > > same as a 'z' obviously, which is what I wanted. =A0Clearly this is not > > a good idea even if it is shorter to type. > > So want the technology to contain a buffer that has an high impedance > output in case of one input is high impedance? > But else the output needs to be low impedance either driving '0' or > '1'. Seems quite unusual to be found in any tech library. > > Your problems seems to me not vhdl related, instead you need to think > in dedicated hardware functionality. > It is quite easy to construct a logic function in vhdl that helps your > need for simulation purpose, but quite a hard job, to build the needed > transistor structure to implement the vhdl in real silicon. > > best regards Thomas That's funny, I have some parts on a current board design that do pretty much this. They are called switches. One of the inputs will cause a 'Z' on the output when the input is a 'Z'. A little logic added to the control input and it would do exactly what I was coding. Rick From newsfish@newsfish Tue Aug 9 07:52:59 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news.cgarbs.de!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!feeder.news-service.com!feeder.news-service.com!postnews.google.com!d28g2000yqc.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Wed, 30 Mar 2011 14:20:31 -0700 (PDT) Organization: http://groups.google.com Lines: 57 Message-ID: <859f951f-4ef0-4a3e-aa6c-86b19acc13e2@d28g2000yqc.googlegroups.com> References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301520031 25843 127.0.0.1 (30 Mar 2011 21:20:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 21:20:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d28g2000yqc.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4885 On Mar 29, 12:42=A0pm, "M. Norton" wrote: > > So, in summary does anyone have any technique or best practice for how > to organize bus interfaces for passing in and out of procedure calls? > 1. Similar to what Jonathon suggested, but a bit easier (I think) to draw good boundary lines for the testing entity is to model real parts. FPGAs in real applications do not exist untethered to the rest of the world, they are connected to real parts on a circuit board so your 'FPGA testbench' could (I think 'should') be a model of that PCBA (and surrounding systems)...which means that if you model the parts that go on that PCBA and connect them per the netlist then you're modelling your real system. In your case, you had mentioned in later posts about modelling a PCI bus. I'm guessing that there is a processor on the board, so model that processor and you'll have your PCI bus. Maybe for starters, the PCI bus is about all that you will model, the rest can come later when needed. In any case, by doing this, you'll be refining your cheezy processor model over time and making it closer to the real thing which will make that model better and better over time. What I've also found is that as I model more of the real system, there comes less of a need for that 'magic communications interface' between two parts that Jonathon mentioned in his post. If needed, I simply put that interface into a 'magic comms' package which is project specific (but can be named the same for each project). For the most part, simulations become watching the system perform whatever it is that you set it up to do without too much 'magic' communications between components. 2. Standardize on a comm interface. For the most part, interfaces simply need to read and write. Use Avalon as a guide, at the low level you can write once and use over and over that handshake for any interface. Then the task becomes to create an 'Avalon to PCI' widget (as an example). If that same type of PCI interface is needed in a different application that is a totally different processor, then guess what? You can use that Avalon to PCI widget that you created in your new processor. Both processors could use the same Avalon protocol on the one side with PCI on the other. 3. As has been pointed out and you've discovered, removing the signals from procedures means putting them into a process which can be a pain. However, if you implement #2, then this becomes a straightforward wrapper to portion of your your part model from #1. That description is likely unique to that model so you wouldn't really have a need to 'reuse it' somewhere else other than to plop down your part model from #1. However, there can still be cutting and pasting within that part model. Consider a processor model where you implement the equivalent of several 'threads' that wake up and run at appropriate times. Each thread would be a process, therefore each 'thread' would have to have the shorthand procedures cut and pasted. A pain, but again those procedures are only of use to that part model so you're likely editing a single file. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:52:59 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j13g2000pro.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Wed, 30 Mar 2011 15:10:19 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301523019 816 127.0.0.1 (30 Mar 2011 22:10:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 22:10:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j13g2000pro.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4886 On Mar 29, 3:36=A0pm, "M. Norton" wrote: > On Mar 29, 2:51=A0pm, Andy wrote: > > > I've used a single record with an inout port on the procedure(s). All > > of the elements of the record must be resolved types. I declare an > > "undriven" constant of that record such that the elements that are > > never used as outputs by each process are harmlessly driven to 'Z'. > > I've read and reread this a bit and while I get the theory of what > you're doing with the constant, I'm not sure how it's being applied. > So if we've got a package with a record containing the signal elements > of a bus, including control lines, that would allow harnessing up a > generic procedure to a testbench component. =A0However when do you apply > the constant that's got things set to high impedance? =A0Does that > happen inside the procedure at the beginning of the procedure and then > subsequent assignments override it? > > So, possibly something like this? > > =A0 =A0procedure my_generic_write( ... ; signal my_bus : > T_BUS_RECORD; ... ) is > =A0 =A0begin > =A0 =A0 =A0 =A0 my_bus <=3D C_HARMLESSLY_DRIVEN_TO_Z; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus.address <=3D some_address; > =A0 =A0 =A0 =A0 my_bus.wr_cyc <=3D '1'; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus.data <=3D some_data; > =A0 =A0 =A0 =A0 my_bus.wren <=3D '1'; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus_wren <=3D '0'; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus.wr_cyc <=3D '0'; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus <=3D C_HARMLESSLY_DRIVEN_TO_Z; > =A0 =A0end procedure my_generic_write; > > Then during that procedure call, all the my_bus.rd_cyc, my_bus.rd_stb, > etc would remain Z. =A0I will have to try that out and see how it goes. > Seems like it might do what I want (assuming I have your intent > divined correctly). > > Thanks for the information! > Mark Yes, you'd use it like that in the procedure(s), but you also need to make sure that processes in the DUT that interact with the record also drive the constant onto the signal, so that the DUT does not end up driving 'U' on input elements of the record. Andy From newsfish@newsfish Tue Aug 9 07:53:00 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!x3g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Odd Simulator Error Date: Thu, 31 Mar 2011 00:03:39 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <51c53c0a-4dfd-4497-a5a3-3e3bdfaf9e6e@x3g2000yqj.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301555019 29894 127.0.0.1 (31 Mar 2011 07:03:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 31 Mar 2011 07:03:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x3g2000yqj.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4887 I am working on a test bench for a design that is working ok. The code for the design is not changing, just the test bench code. Occasionally when I compile in the Aldec ActiveHDL simulator I get a very odd error that I've never seen before. # Error: DAGGEN_0007: mulaw.vhd : (0, 0): Error during conversion c: \Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest\compile \muLaw_RTL.dag to c:\Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest \compile\muLaw_RTL._x86.bin The file that this occurs on is random. It can happen on multiple files as well. If I recompile it usually goes away although sometimes I have to recompile more than once. I thought maybe it was a memory issue but closing it and restarting doesn't really fix the issue. It just seems to be totally random failing perhaps two times out of five. Any idea what this is about? Rick From newsfish@newsfish Tue Aug 9 07:53:00 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Thu, 31 Mar 2011 01:38:55 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: <46b1fa34-de95-47e8-9bba-e73d58651a40@k22g2000yqh.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> <67270d79-5df2-40e8-86e7-31d915ec7c85@r6g2000vbo.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301560735 15580 127.0.0.1 (31 Mar 2011 08:38:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 31 Mar 2011 08:38:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9396) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4888 On 30 Mrz., 17:04, rickman wrote: > On Mar 30, 8:49=A0am, Thomas Stanka > wrote: > > > > > On 29 Mrz., 18:13, rickman wrote: > > > > I was using some logic to shorten typing of some operations where I > > > was trying to create tristate drivers. =A0To be sure of the result I > > > looked up the logic tables and found that, for example the OR functio= n > > > on a constant 'z' and a signal produces a '1' when the signal is a > > > '1', but when the signal is a zero results in an 'x'. =A0This is not = the > > > same as a 'z' obviously, which is what I wanted. =A0Clearly this is n= ot > > > a good idea even if it is shorter to type. > > > So want the technology to contain a buffer that has an high impedance > > output in case of one input is high impedance? > > But else the output needs to be low impedance either driving '0' or > > '1'. Seems quite unusual to be found in any tech library. > > > Your problems seems to me not vhdl related, instead you need to think > > in dedicated hardware functionality. > > It is quite easy to construct a logic function in vhdl that helps your > > need for simulation purpose, but quite a hard job, to build the needed > > transistor structure to implement the vhdl in real silicon. > > > best regards Thomas > > That's funny, I have some parts on a current board design that do > pretty much this. =A0They are called switches. =A0One of the inputs will > cause a 'Z' on the output when the input is a 'Z'. =A0A little logic > added to the control input and it would do exactly what I was coding. Actually there is a difference between whats possible on a PCB, whats possible with dedicated structures in a device and whats possible using a given cell library. Your synthesis tool is only able to map a logic to the defined logic elements. And in fact the tool tends to be quite stupid when it comes to "unusual" functionality. I guess you will find no tool supporting your code even if it is possible map the functionlity in an ASIC library. For a lot of techologies it is impossible to build your described funtionlity using the given primitives. bye Thomas From newsfish@newsfish Tue Aug 9 07:53:00 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f2g2000yqf.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Odd Simulator Error Date: Thu, 31 Mar 2011 02:25:32 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: <51c53c0a-4dfd-4497-a5a3-3e3bdfaf9e6e@x3g2000yqj.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301563532 13705 127.0.0.1 (31 Mar 2011 09:25:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 31 Mar 2011 09:25:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f2g2000yqf.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 20j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4889 On Mar 31, 8:03=A0am, rickman wrote: > # Error: DAGGEN_0007: mulaw.vhd : (0, 0): Error during conversion c: > \Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest\compile > \muLaw_RTL.dag to c:\Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest > \compile\muLaw_RTL._x86.bin > > The file that this occurs on is random. =A0It can happen on multiple > files as well. =A0If I recompile it usually goes away although sometimes > I have to recompile more than once. > > I thought maybe it was a memory issue but closing it and restarting > doesn't really fix the issue. =A0It just seems to be totally random > failing perhaps two times out of five. > > Any idea what this is about? It's pretty clear that this is a tool bug. DAG =3D Directed Acyclic Graph, I would guess - the tree representation of your code that's created internally by the compiler. I cannot imagine why it should come and go on the same set of source code, unless there's some random seeding going on for the internal optimizations. Support case for Aldec, I'm afraid. A tool crash, or a tool failing on some internal operation, is NEVER your fault. If the tool can't report the problem back to something in your source code, it's the tool that's broken. Before anyone takes this the wrong way, let's point out that the name "Aldec" here is a placeholder for "any company whose tool misbehaves in such a way" - it's happened to me with tools from much bigger companies than Aldec :-) -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:01 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Odd Simulator Error Date: Thu, 31 Mar 2011 16:58:32 +0000 (UTC) Organization: A noiseless patient Spider Lines: 59 Message-ID: References: <51c53c0a-4dfd-4497-a5a3-3e3bdfaf9e6e@x3g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 31 Mar 2011 16:58:32 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="pg/RQe9DTLnap+ldrpWP+w"; logging-data="24310"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18QjSxImoy2FUCPnqmHP+h/XONc3N40niU=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:Z55otHFiM4EsFNJr2qMj6ZsYr8s= Xref: feeder.eternal-september.org comp.lang.vhdl:4899 On Thu, 31 Mar 2011 02:25:32 -0700, Jonathan Bromley wrote: > On Mar 31, 8:03 am, rickman wrote: > >> # Error: DAGGEN_0007: mulaw.vhd : (0, 0): Error during conversion c: >> \Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest\compile >> \muLaw_RTL.dag to c:\Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest >> \compile\muLaw_RTL._x86.bin >> >> The file that this occurs on is random.  It can happen on multiple >> files as well.  If I recompile it usually goes away although sometimes >> I have to recompile more than once. >> >> I thought maybe it was a memory issue but closing it and restarting >> doesn't really fix the issue.  It just seems to be totally random >> failing perhaps two times out of five. >> >> Any idea what this is about? > > It's pretty clear that this is a tool bug. DAG = Directed Acyclic > Graph, I would guess - the tree representation of your code that's > created internally by the compiler. > I agree, but even if it's a tool bug ... You can't just stop and wait until the tool supplier fixes it, unfortunately. What to do next? My experience with tool bugs is that often they have remained hidden because you are exercising some corner case ... possibly faulty VHDL that (another) tool bug allowed through the parser. In which case: (a) try building the project in other available systems (pref Modelsim, possibly Xilinx free ISIM or XST from Webpack, etc) and note any warnings or syntax errors. (b) go back to a previous version before the failure started (if there was one), and bisect until you find the suspect file. Not so easy if the failure is intermittent (c) comment out or rewrite to avoid any new VHDL tricks or constructs you are trying for the first time to see if there is a workaround. This way, you can often (a) carry on working in the absence of a fix, (b) localise the error to improve the bug report and (c) submit a tiny test case instead of having to hand over your whole project. If possible, it is better to report "Xilinx ISIM 10.1 exits suddenly with a Segment Violation when you return an access type (e.g. Line = access string) from a function" than "it crashed". Apologies to Rick if this is all old hat to him; however it may be useful to somebody else. - Brian From newsfish@newsfish Tue Aug 9 07:53:01 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!hg8g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Array pipeline Date: Thu, 31 Mar 2011 23:50:21 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: <7c6bc392-a398-448e-9a54-09975cacc96c@hg8g2000vbb.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301640622 13966 127.0.0.1 (1 Apr 2011 06:50:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 06:50:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hg8g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4900 Hi, I want to declare an array "vecarr " which consists of std_logic_vector, and a second array "arr3d " to pipeline the first array. When simuating the following test code Modelsim complains: ** Fatal: (vsim-3734) Index value 0 is out of range 4 downto 1. ------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity arr_pipe is end entity; architecture xy of arr_pipe is type t_vecarr is array(natural range <>) of std_logic_vector(7 downto 0); signal vecarr : t_vecarr(15 downto 0) := (others => (others => '1')); type t_arr3d is array(natural range <>) of t_vecarr(15 downto 0); signal arr3d : t_arr3d(4 downto 0); signal clk : std_logic; begin process begin clk <= '1'; wait for 5 ns; clk <= '0'; wait for 5 ns; end process; process(clk) begin if rising_edge(clk) then for m in 0 to 15 loop arr3d(arr3d'high)(m) <= vecarr(m); arr3d(arr3d'high-1 downto 0)(m) <= arr3d(arr3d'high downto 1)(m); --** ERROR end loop; end if; end process; end xy; ------------------------------------------------------------------------------------------------ Can someone explain to me what is wrong about that shift register ? Cheers, hssig From newsfish@newsfish Tue Aug 9 07:53:01 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!d2g2000yqn.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Fri, 1 Apr 2011 00:47:07 -0700 (PDT) Organization: http://groups.google.com Lines: 58 Message-ID: <83c3181f-f827-49fc-bc10-03ac0f38b043@d2g2000yqn.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> <67270d79-5df2-40e8-86e7-31d915ec7c85@r6g2000vbo.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301644028 16531 127.0.0.1 (1 Apr 2011 07:47:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 07:47:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d2g2000yqn.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.16) Gecko/20110323 Ubuntu/10.04 (lucid) Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4901 On 30 Mrz., 17:04, rickman wrote: > On Mar 30, 8:49=A0am, Thomas Stanka > wrote: > > > > > On 29 Mrz., 18:13, rickman wrote: > > > > I was using some logic to shorten typing of some operations where I > > > was trying to create tristate drivers. =A0To be sure of the result I > > > looked up the logic tables and found that, for example the OR functio= n > > > on a constant 'z' and a signal produces a '1' when the signal is a > > > '1', but when the signal is a zero results in an 'x'. =A0This is not = the > > > same as a 'z' obviously, which is what I wanted. =A0Clearly this is n= ot > > > a good idea even if it is shorter to type. > > > So want the technology to contain a buffer that has an high impedance > > output in case of one input is high impedance? > > But else the output needs to be low impedance either driving '0' or > > '1'. Seems quite unusual to be found in any tech library. > > > Your problems seems to me not vhdl related, instead you need to think > > in dedicated hardware functionality. > > It is quite easy to construct a logic function in vhdl that helps your > > need for simulation purpose, but quite a hard job, to build the needed > > transistor structure to implement the vhdl in real silicon. > > > best regards Thomas > > That's funny, I have some parts on a current board design that do > pretty much this. =A0They are called switches. =A0One of the inputs will > cause a 'Z' on the output when the input is a 'Z'. =A0A little logic > added to the control input and it would do exactly what I was coding. > > Rick Hi Rick, if some input of a CMOS device really sees a 'Z' and does not use some internal pullup, it may end up oscillating at some very high frequency. In the worst case this may even blow up your input buffer. So if you have some board with switches that leave the inputs "open" you are either required to use the internal pullups, or there's some connector parallel to the switches so you can use the I/Os for some other optional hardware (this requires the switches always to be held in the open position). In any case, a CMOS input will never properly recognize a 'Z' condition, the input driver will either drive a '0' or '1' and you can't establish a pure wire connection between two pads inside an FPGA. There's always an IBUF and OBUF. Have a nice synthesis Eilert From newsfish@newsfish Tue Aug 9 07:53:01 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!hg8g2000vbb.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Array pipeline Date: Fri, 1 Apr 2011 04:10:38 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: References: <7c6bc392-a398-448e-9a54-09975cacc96c@hg8g2000vbb.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301656238 9799 127.0.0.1 (1 Apr 2011 11:10:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 11:10:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hg8g2000vbb.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 11j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4902 On Apr 1, 7:50=A0am, hssig wrote: > arr3d(arr3d'high-1 downto 0)(m) > <=3D arr3d(arr3d'high downto 1)(m); =A0--** ERROR Huh? You're taking a slice of an array, and then trying to subscript it? I didn't think that was possible, but it seems that maybe it is (must go check the LRM!) and the (m) is being used as a subscript into the slice arr3d(arr3d'high-1 downto 0). You need an inner for-loop to do that copy, scanning over the first subscript of arr3d. I don't see why you need the m-loop at all, since you're just copying bits broadside. What's wrong with this: arr3d(arr3d'high) <=3D vecarr; arr3d(arr3d'high-1 downto 0) <=3D arr3d(arr3d'high downto 1); Or something like this... for i in arr3d'range loop if i =3D arr3d'high then arr3d(i) <=3D vecarr; else arr3d(i) <=3D arr3d(i+1); end if; end loop; I don't see the need for a loop scanning over the subcomponents of the t_vecarr objects. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:01 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Fri, 1 Apr 2011 06:47:19 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301665639 6756 127.0.0.1 (1 Apr 2011 13:47:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 13:47:19 +0000 (UTC) In-Reply-To: <859f951f-4ef0-4a3e-aa6c-86b19acc13e2@d28g2000yqc.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4903 On Wednesday, March 30, 2011 4:20:31 PM UTC-5, KJ wrote: > 1. Similar to what Jonathon suggested, but a bit easier (I think) to > draw good boundary lines for the testing entity is to model real > parts. FPGAs in real applications do not exist untethered to the rest > of the world, they are connected to real parts on a circuit board so > your 'FPGA testbench' could (I think 'should') be a model of that PCBA > (and surrounding systems)...which means that if you model the parts > that go on that PCBA and connect them per the netlist then you're > modelling your real system. In your case, you had mentioned in later I've actually done this for downstream effects. If the FPGA is driving a A= DC or DAC or other peripheral, I base the model on the datasheet and implem= ent it to some degree of fidelity (usually loose at first, and then growing= complexity over time, with timing checking assertions and the like.) I've= not done this with the stimulus side though, as frequently it seems like t= hat task is more daunting than time permits. I rough in some interface bas= ics but it's pretty rough and ready (hence trying to find a better solution= .) I appreciate the thoughts. I'll consider more involved stimulus models if = I can get the reuse and maintainability aspects in line. Best regards, Mark From newsfish@newsfish Tue Aug 9 07:53:02 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!news.glorb.com!news2.glorb.com!postnews.google.com!w21g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Fri, 1 Apr 2011 08:24:47 -0700 (PDT) Organization: http://groups.google.com Lines: 80 Message-ID: <298cbfbb-8d7b-4ebe-bd34-b766bb448bbb@w21g2000yqm.googlegroups.com> References: NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301671487 559 127.0.0.1 (1 Apr 2011 15:24:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 15:24:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w21g2000yqm.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4904 On Apr 1, 9:47=A0am, "M. Norton" wrote: > On Wednesday, March 30, 2011 4:20:31 PM UTC-5, KJ wrote: > > 1. Similar to what Jonathon suggested, but a bit easier (I think) to > > draw good boundary lines for the testing entity is to model real > > parts. =A0FPGAs in real applications do not exist untethered to the res= t > > of the world, they are connected to real parts on a circuit board so > > your 'FPGA testbench' could (I think 'should') be a model of that PCBA > > (and surrounding systems)...which means that if you model the parts > > that go on that PCBA and connect them per the netlist then you're > > modelling your real system. =A0In your case, you had mentioned in later > > I've actually done this for downstream effects. =A0If the FPGA is driving= a ADC or DAC or other peripheral, I base the model on the datasheet and im= plement it to some degree of fidelity (usually loose at first, and then gro= wing complexity over time, with timing checking assertions and the like.) = =A0I've not done this with the stimulus side though, as frequently it seems= like that task is more daunting than time permits. =A0 KJ: In what way would it be more daunting to put stimulus code within the entity for the model for a real part then it is to put it in some freeform testbench? In order to provide stimulus (and check responses) you have to write 'something', I'm simply saying that putting that 'something' inside the model of real part(s) would be a better overall location than just into some otherwise probably non- reusable testbench. The only additional work is the creation of the entity for the part(s) and the creation of a PCBA and/or system model. The PCBA model creation is simply instantiating the parts and connecting nets. Tedious perhaps if you have a lot of parts, but not difficult. However, if you have a lot of parts that need modelling in order to test the design, it likely indicates that you'd also need a rather large and cumbersome freeform testbench. > I rough in some interface basics but it's pretty rough and ready (hence t= rying to find a better solution.) > > I appreciate the thoughts. =A0I'll consider more involved stimulus models= if I can get the reuse and maintainability aspects in line. > : I think you'll find that creating part models is a good enabler for reuse and maintainability. The reason for this is that entities are the easiest things to reuse, you simply instantiate the component and connect it up. Entities are also the natural hierarchy boundary in VHDL. Within a part model you might use existing designs that you already have. Or, when you're creating a new part you might realize that if you only partitioned some other model a bit differently you could now reuse that part. That's when you go back and re-factor the original design to create a now reusable entity. Re-factoring is a natural result of design, sometimes you get it correct right from the git-go, other times you want to break designs down into even smaller, reusable, maybe more generally useful pieces. By using real parts that have real specifications as the basis for your testbench you also pick up the following advantages that apply to reuse and maintainability: - The part model can be validated to the specification independently of the design that the part model is being used to verify in the testbench...one spends as much time or more verifying a design as you do designing the thing, yet what is the objective criteria for validating that the testbench itself is correct? - As the part model is refined to be more inclusive of functions that weren't initially needed, backwards compatibility is maintained. Since the entity for the part model is not changing (that gets setup at the begining based on the pinout of the part that you get from the specification), only the code in the architecture for the part model is getting tweaked. All this is doing is refining the function to more closely reflect reality. If that 'breaks' something in a simulation testbench then it indicates that either the changes to the part model are not quite correct (refer back to the part specification to determine) or you've uncovered a hole in the older design that should probably be fixed. Any result is a 'good thing' resulting in a higher quality design or higher quality part model or additional validation that the design really does work as expected. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:02 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d28g2000yqc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Fri, 1 Apr 2011 22:17:10 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> <67270d79-5df2-40e8-86e7-31d915ec7c85@r6g2000vbo.googlegroups.com> <83c3181f-f827-49fc-bc10-03ac0f38b043@d2g2000yqn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301721430 14028 127.0.0.1 (2 Apr 2011 05:17:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 2 Apr 2011 05:17:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d28g2000yqc.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4905 On Apr 1, 3:47=A0am, backhus wrote: > On 30 Mrz., 17:04, rickman wrote: > > > > > On Mar 30, 8:49=A0am, Thomas Stanka > > wrote: > > > > On 29 Mrz., 18:13, rickman wrote: > > > > > I was using some logic to shorten typing of some operations where I > > > > was trying to create tristate drivers. =A0To be sure of the result = I > > > > looked up the logic tables and found that, for example the OR funct= ion > > > > on a constant 'z' and a signal produces a '1' when the signal is a > > > > '1', but when the signal is a zero results in an 'x'. =A0This is no= t the > > > > same as a 'z' obviously, which is what I wanted. =A0Clearly this is= not > > > > a good idea even if it is shorter to type. > > > > So want the technology to contain a buffer that has an high impedance > > > output in case of one input is high impedance? > > > But else the output needs to be low impedance either driving '0' or > > > '1'. Seems quite unusual to be found in any tech library. > > > > Your problems seems to me not vhdl related, instead you need to think > > > in dedicated hardware functionality. > > > It is quite easy to construct a logic function in vhdl that helps you= r > > > need for simulation purpose, but quite a hard job, to build the neede= d > > > transistor structure to implement the vhdl in real silicon. > > > > best regards Thomas > > > That's funny, I have some parts on a current board design that do > > pretty much this. =A0They are called switches. =A0One of the inputs wil= l > > cause a 'Z' on the output when the input is a 'Z'. =A0A little logic > > added to the control input and it would do exactly what I was coding. > > > Rick > > Hi Rick, > if some input of a CMOS device really sees a 'Z' and does not use some > internal pullup, > it may end up oscillating at some very high frequency. In the worst > case this may even blow up your input buffer. > > So if you have some board with switches that leave the inputs "open" > you are either required to use the internal pullups, > or there's some connector parallel to the switches so you can use the > I/Os for some other optional hardware (this requires the switches > always to be held in the open position). > > In any case, a CMOS input will never properly recognize a 'Z' > condition, the input driver will either drive a '0' or '1' > and you can't establish a pure wire connection between two pads inside > an FPGA. There's always an IBUF and OBUF. > > Have a nice synthesis > =A0 Eilert I think you are confusing two things. One is how synthesis works. It concerns with the resulting overall behavior, it does not care how you construct that behavior with your equations. The fact that I propagate a 'z' through a logic block in the HDL does not require that this block be replaced by some sort of gate that exactly implements that block. This can easily be combined with whatever logic is producing the 'z' that is to be propagated through the block and result in a tristate driver with some logic function driving the enable... which is exactly what I was trying to do. The other point of confusion is how a switch works. A switch has a logic input that operates as you describe and two switch I/Os that literally operate as a passive switch. These I/Os will not oscillate in any sense because they do not amplify. This is all moot or as George Costanza might say, "moop". The logic block does not propagate a 'z' and it is not worth writing my own function for this. Rick From newsfish@newsfish Tue Aug 9 07:53:02 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!k9g2000yqi.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Array pipeline Date: Mon, 4 Apr 2011 00:45:43 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: References: <7c6bc392-a398-448e-9a54-09975cacc96c@hg8g2000vbb.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301903143 30574 127.0.0.1 (4 Apr 2011 07:45:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 4 Apr 2011 07:45:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k9g2000yqi.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4906 Hi Jonathan, thank you for your alternative description. I have just been curious about the reason why my solution does not work. Now it is clear. Cheers, hssig From newsfish@newsfish Tue Aug 9 07:53:02 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "Harold Aptroot" Newsgroups: comp.lang.vhdl Subject: "Clockless" computing Date: Thu, 7 Apr 2011 09:39:48 +0200 Organization: A noiseless patient Spider Lines: 1 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; format=flowed; charset="utf-8"; reply-type=original Content-Transfer-Encoding: 7bit Injection-Date: Thu, 7 Apr 2011 07:39:46 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="Jl9kUHHBpr7ZpIKLJZRZZw"; logging-data="4710"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+OVIAXm9FueC+NN+oQYkvW" X-MimeOLE: Produced By Microsoft MimeOLE V12.0.1606 X-Newsreader: Microsoft Windows Live Mail 12.0.1606 Importance: Normal Cancel-Lock: sha1:+h83X6meME+339MG9QhFoKSBUmI= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:4907 This isn't really a VHDL question, but I'm not sure where else to ask it. I'm considering designing a system using only the following building blocks (and wires and memory cells): 1: in || out c | v || x | y 0 | 0 || 0 | 0 0 | 1 || 0 | 0 1 | 0 || 0 | 1 1 | 1 || 1 | 0 2: in || out x | y || c | v 0 | 0 || 0 | ? 0 | 1 || 1 | 1 1 | 0 || 1 | 0 1 | 1 || 0 | ? (? represents "don't care") The C is supposed to be connected to an X or Y or C, V is should be connected to V. C represents the "clock" that is explicitly passed around. X and Y encode 0 and 1 respectively. The purpose of block type 1 is doing the main calculations, block 2 takes a result and turns it into a pair of (clock, value). One motivation for this system is that the block type 1 directly encodes a node from a (reduced) binary decision diagram, which are easy to manipulate. I know it's "logically complete" in the sense that I could compute anything with those blocks, but is it also a good way? Are there better ways? -- harold From newsfish@newsfish Tue Aug 9 07:53:02 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a12g2000yqk.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: "Clockless" computing Date: Thu, 7 Apr 2011 01:50:19 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302166219 5229 127.0.0.1 (7 Apr 2011 08:50:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Apr 2011 08:50:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a12g2000yqk.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.16) Gecko/20110323 Ubuntu/10.04 (lucid) Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4908 On 7 Apr., 09:39, "Harold Aptroot" wrote: > This isn't really a VHDL question, but I'm not sure where else to ask it. > > I'm considering designing a system using only the following building blocks > (and wires and memory cells): > > 1: > in || out > c | v || x | y > 0 | 0 || 0 | 0 > 0 | 1 || 0 | 0 > 1 | 0 || 0 | 1 > 1 | 1 || 1 | 0 > > 2: > in || out > x | y || c | v > 0 | 0 || 0 | ? > 0 | 1 || 1 | 1 > 1 | 0 || 1 | 0 > 1 | 1 || 0 | ? > > (? represents "don't care") > > The C is supposed to be connected to an X or Y or C, V is should be > connected to V. > C represents the "clock" that is explicitly passed around. X and Y encode 0 > and 1 respectively. > The purpose of block type 1 is doing the main calculations, block 2 takes a > result and turns it into a pair of (clock, value). > One motivation for this system is that the block type 1 directly encodes a > node from a (reduced) binary decision diagram, which are easy to manipulate. > > I know it's "logically complete" in the sense that I could compute anything > with those blocks, but is it also a good way? Are there better ways? > > -- > harold Hi Harold, in this group and also in the rest of the net you find various informations when you look for "asynchronous logic" design. There are many projects and papers covering this topic. A starting point for your investigations may be this one, if you don't know it already: http://en.wikipedia.org/wiki/C-element Have a nice synthesis Eilert From newsfish@newsfish Tue Aug 9 07:53:02 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news.cgarbs.de!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!postnews.google.com!v8g2000yqb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Fri, 8 Apr 2011 08:12:52 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302275572 20269 127.0.0.1 (8 Apr 2011 15:12:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Apr 2011 15:12:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v8g2000yqb.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4909 Im building a model of a memory interface. The entity mimics the interface of the normal memory interface with multiple request, address, ack and data valid lines, one set per channel. Internally I have a protected type that handles the memory modelling (dynamically creating memory locations as they are accessed so I dont have a monstrous 256Mbyte array declared) and another protected that handles the read queue. As this is modelling a memory in a video system, I want to be able to dump whole images (ie bypassing the whole interface) into memory, for example if Im only testing the other bits of the design on the read side of the interface. I have everything I need for reading/writing bitmaps to specific array types, but I just need to get these arrays into this entity. Heres the pinch - I really dont want to specify the size of the image, as this may well handle multiple video standards on hardware, so I need the image sizes to vary accordingly. Id love to be able to pass in an access type and watch the transactions on it - but of course access types can only be variables - therefore not suitable for ports on an entity. Can anyone think of any other way I could get these arrays into the interface without padding? The only thing I can think of is sticking image sizes as generics and declaring the "image" port to this size, but I would prefer more flexibility. So - am I just pushing too hard? How long before someone pipes up that I should try System Verilog? From newsfish@newsfish Tue Aug 9 07:53:03 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!feedme.ziplink.net!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!2g2000vbl.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Fri, 8 Apr 2011 12:31:18 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: <518030f7-18bb-4fb6-b3dc-1cabf63c5d7d@2g2000vbl.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302291078 27884 127.0.0.1 (8 Apr 2011 19:31:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Apr 2011 19:31:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 2g2000vbl.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4910 On Apr 8, 11:12=A0am, Tricky wrote: > Im building a model of a memory interface. The entity mimics the > interface of the normal memory interface with multiple request, > address, ack and data valid lines, one set per channel. Internally I > have a protected type that handles the memory modelling (dynamically > creating memory locations as they are accessed so I dont have a > monstrous 256Mbyte array declared) and another protected that handles > the read queue. > > As this is modelling a memory in a video system, I want to be able to > dump whole images (ie bypassing the whole interface) into memory, for > example if Im only testing the other bits of the design on the read > side of the interface. I have everything I need for reading/writing > bitmaps to specific array types, but I just need to get these arrays > into this entity. > > Heres the pinch - I really dont want to specify the size of the image, > as this may well handle multiple video standards on hardware, so I > need the image sizes to vary accordingly. Id love to be able to pass > in an access type and watch the transactions on it - but of course > access types can only be variables - therefore not suitable for ports > on an entity. Can anyone think of any other way I could get these > arrays into the interface without padding? > Dump the data to a file. Use a string to pass the file name into the memory model. If the file name needs to be able to be changed during the simulation (i.e. if it must be a 'signal' rather than a 'generic') than the only limitation will be that the string name will need to be a fixed size. Even that limitation can be less onerous if you simply use a loooooong string size, null terminate the string and then have the memory model construct the file name by looking for the null termination. Even better, if you're using standard bitmap file formats like .BMP for the exchange than you can create read/write BMP file procedures which you will no doubt use somewhere down the road and not be tied to this particular memory model instance. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:03 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j13g2000yqj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Fri, 8 Apr 2011 13:54:48 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <46151aa6-c206-40a9-bb80-d2e8d40ce0c1@j13g2000yqj.googlegroups.com> References: NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302296088 13231 127.0.0.1 (8 Apr 2011 20:54:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Apr 2011 20:54:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j13g2000yqj.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4911 On Apr 8, 10:12=A0am, Tricky wrote: > Im building a model of a memory interface. The entity mimics the > interface of the normal memory interface with multiple request, > address, ack and data valid lines, one set per channel. Internally I > have a protected type that handles the memory modelling (dynamically > creating memory locations as they are accessed so I dont have a > monstrous 256Mbyte array declared) and another protected that handles > the read queue. > > As this is modelling a memory in a video system, I want to be able to > dump whole images (ie bypassing the whole interface) into memory, for > example if Im only testing the other bits of the design on the read > side of the interface. I have everything I need for reading/writing > bitmaps to specific array types, but I just need to get these arrays > into this entity. > > Heres the pinch - I really dont want to specify the size of the image, > as this may well handle multiple video standards on hardware, so I > need the image sizes to vary accordingly. Id love to be able to pass > in an access type and watch the transactions on it - but of course > access types can only be variables - therefore not suitable for ports > on an entity. Can anyone think of any other way I could get these > arrays into the interface without padding? > > The only thing I can think of is sticking image sizes as generics and > declaring the "image" port to this size, but I would prefer more > flexibility. > > So - am I just pushing too hard? How long before someone pipes up that > I should try System Verilog? How about flattening your image into a single vector, and pass it in on an unconstrained array (e.g. SLV) port? Add generics (static) or other ports (dynamic) for pixel/row/column size to tell the model how to extract the image from the linear vector. Andy From newsfish@newsfish Tue Aug 9 07:53:03 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Fri, 08 Apr 2011 22:48:12 +0100 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="1142"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+v6Iwo+hBc4HvWtmCGGYUt7PTU3qw0eWo=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:oQpjgMwJlQpQF1fa3gnA0gl0qX8= Xref: feeder.eternal-september.org comp.lang.vhdl:4912 On Fri, 8 Apr 2011 08:12:52 -0700 (PDT), Tricky wrote: > Id love to be able to pass >in an access type and watch the transactions on it - but of course >access types can only be variables - therefore not suitable for ports >on an entity. Can anyone think of any other way I could get these >arrays into the interface without padding? In the past when I've needed to do this kind of thing, one approach has been to create a package with a pool of objects (shared variables) in it, and then have entity instances register themselves with the package by calling appropriate functions in it. An instance can supply its own instance name to such a call as a string including 'PATH_NAME, allowing the package to work out which instance placed the call. It's a bit upside-down and clumsy, but can sometimes provide the kind of functional communication you seem to be wanting. You likely need some sort of side-channel into the instances, in the form of a regular port of boolean or some enumerated type, to allow you to signal interesting events from one instance to another; the instances can then use the package pool as a shared communication medium, and the idea of each instance registering itself with the package by means of its string instance name stops things being outrageously global. It's a while since I did any of this, so the details are a bit sketchy in my mind. But it looks as though I may soon be needing to dust off these tricks once again... -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:03 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l6g2000vbn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Sat, 9 Apr 2011 08:15:44 -0700 (PDT) Organization: http://groups.google.com Lines: 58 Message-ID: <4b9cc046-42e6-44bb-bb59-f0b979f1d417@l6g2000vbn.googlegroups.com> References: <518030f7-18bb-4fb6-b3dc-1cabf63c5d7d@2g2000vbl.googlegroups.com> NNTP-Posting-Host: 213.104.217.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302362145 26141 127.0.0.1 (9 Apr 2011 15:15:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 Apr 2011 15:15:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000vbn.googlegroups.com; posting-host=213.104.217.142; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16 ( .NET CLR 3.5.30729; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4913 On Apr 8, 8:31=A0pm, KJ wrote: > On Apr 8, 11:12=A0am, Tricky wrote: > > > > > Im building a model of a memory interface. The entity mimics the > > interface of the normal memory interface with multiple request, > > address, ack and data valid lines, one set per channel. Internally I > > have a protected type that handles the memory modelling (dynamically > > creating memory locations as they are accessed so I dont have a > > monstrous 256Mbyte array declared) and another protected that handles > > the read queue. > > > As this is modelling a memory in a video system, I want to be able to > > dump whole images (ie bypassing the whole interface) into memory, for > > example if Im only testing the other bits of the design on the read > > side of the interface. I have everything I need for reading/writing > > bitmaps to specific array types, but I just need to get these arrays > > into this entity. > > > Heres the pinch - I really dont want to specify the size of the image, > > as this may well handle multiple video standards on hardware, so I > > need the image sizes to vary accordingly. Id love to be able to pass > > in an access type and watch the transactions on it - but of course > > access types can only be variables - therefore not suitable for ports > > on an entity. Can anyone think of any other way I could get these > > arrays into the interface without padding? > > Dump the data to a file. =A0Use a string to pass the file name into the > memory model. =A0If the file name needs to be able to be changed during > the simulation (i.e. if it must be a 'signal' rather than a 'generic') > than the only limitation will be that the string name will need to be > a fixed size. =A0Even that limitation can be less onerous if you simply > use a loooooong string size, null terminate the string and then have > the memory model construct the file name by looking for the null > termination. > > Even better, if you're using standard bitmap file formats like .BMP > for the exchange than you can create read/write BMP file procedures > which you will no doubt use somewhere down the road and not be tied to > this particular memory model instance. > > Kevin Jennings Thanks all of you for the ideas. Kevins is definatly the most practical for me. Ive had a library full of bitmap reading, writing and colour space converting for about 3 years, so the string thing is easiest (already have a string pad function and string tokenising protected type, so I can easily pass in multiple images in a single generic from the top level testbench) - normally I throw images around in their own array type once read, which is probably why I didnt think of it myself. Im going to make a record type with start address and image path, and sit on that port waiting for a transaction. Cheers guys :) From newsfish@newsfish Tue Aug 9 07:53:03 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Mon, 11 Apr 2011 11:14:12 +0100 Organization: TRW Conekt Lines: 30 Message-ID: References: <518030f7-18bb-4fb6-b3dc-1cabf63c5d7d@2g2000vbl.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net jOHp5o4KpTlsm/mh8rfgtw6gtqre08lKGA+I9yqsd14KenbZw= Cancel-Lock: sha1:gLY6LMliJT+ohQtbxg/FQXA5BRo= sha1:tDsvF+yu/zEddQ1r6ntEdaYLZbA= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4914 KJ writes: > Dump the data to a file. Use a string to pass the file name into the > memory model. If the file name needs to be able to be changed during > the simulation (i.e. if it must be a 'signal' rather than a 'generic') > than the only limitation will be that the string name will need to be > a fixed size. Even that limitation can be less onerous if you simply > use a loooooong string size, null terminate the string and then have > the memory model construct the file name by looking for the null > termination. > > Even better, if you're using standard bitmap file formats like .BMP > for the exchange than you can create read/write BMP file procedures > which you will no doubt use somewhere down the road and not be tied to > this particular memory model instance. Seconded. For other readers (as I know both KJ and Tricky know this) when I do this, I use ASCII-PGM files, as I've found accessing binary files (like BMP) to be non-portable across simulators. If this doesn't matter to you, by all means use BMP :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Aug 9 07:53:03 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Mon, 11 Apr 2011 10:58:02 +0000 (UTC) Organization: A noiseless patient Spider Lines: 42 Message-ID: References: <518030f7-18bb-4fb6-b3dc-1cabf63c5d7d@2g2000vbl.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 11 Apr 2011 10:58:02 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9/3/IeP/twTQFh5cJa2wYg"; logging-data="11742"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18sevUHvbT3NNClqEOHIg20mQmn+3yAV/8=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:mOL8XlEPP8QGWl5UF+pefxRySDg= Xref: feeder.eternal-september.org comp.lang.vhdl:4915 On Mon, 11 Apr 2011 11:14:12 +0100, Martin Thompson wrote: > KJ writes: > >> Dump the data to a file. Use a string to pass the file name into the >> memory model. If the file name needs to be able to be changed during >> the simulation (i.e. if it must be a 'signal' rather than a 'generic') >> than the only limitation will be that the string name will need to be a >> fixed size. Even that limitation can be less onerous if you simply use >> a loooooong string size, null terminate the string and then have the >> memory model construct the file name by looking for the null >> termination. >> >> Even better, if you're using standard bitmap file formats like .BMP for >> the exchange than you can create read/write BMP file procedures which >> you will no doubt use somewhere down the road and not be tied to this >> particular memory model instance. > > Seconded. > > For other readers (as I know both KJ and Tricky know this) when I do > this, I use ASCII-PGM files, as I've found accessing binary files (like > BMP) to be non-portable across simulators. If this doesn't matter to > you, by all means use BMP :) > My approach has been to perform binary I/O through an unofficial "portability layer". Modelsim and Xilinx ISIM (10.3) are the two I have experience of. ISIM insists on reading a short undocumented* header before the actual data. To satisfy this, I have simple scripts to separate header and file (using "head" and "tail) from ISIM output files, and to "cat" a header onto any binary file before I read it into ISIM. The other difference is endian-ness; I set a boolean flag ("is_isim") which controls end-swapping in both input/output routines. (* Xilinx refused to provide any documentation on the header despite a Webcase specifically asking for it) - Brian From newsfish@newsfish Tue Aug 9 07:53:04 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!p3g2000vbv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Is this a VHDL limitation, or Modelsim bug Date: Mon, 11 Apr 2011 05:37:48 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302525468 10526 127.0.0.1 (11 Apr 2011 12:37:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Apr 2011 12:37:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p3g2000vbv.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4916 I have the following line of code: img_height := ( img.get_image )'length(1); img is a protected type. get_image is a function returning a 2D array containing the image data. img_height is an integer. Now, in modesim I get the compilation error: # ** Error: hdl/mem_interface_model.vhd(745): near "'": expecting ';' The error is pointing to the 'length attribute. So I can see that modelsim wants to end the like at the function call, but what's wrong with taking the attribute of a return value. Before anyone asks, Ive found an annoying bug that crashes the modelsim compiler which mean (for reasons of my file) I cannot have functions that return the width or height of the image in the protected type. It works when I return the image array, so Im trying to work around this bug with the code above. From newsfish@newsfish Tue Aug 9 07:53:04 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Is this a VHDL limitation, or Modelsim bug Date: Mon, 11 Apr 2011 11:13:55 -0800 Lines: 14 Message-ID: <90gulfFpn9U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net Fw90fNAv8C5sKBjV4MNGtw2OUgDYiqlBoaAR83YwgBXb3GGjqP Cancel-Lock: sha1:7J7TWiCHX7t5n7CXbvS96nshOuk= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4917 On 4/11/2011 4:37 AM, Tricky wrote: > I have the following line of code: > > img_height := ( img.get_image )'length(1); > > img is a protected type. > get_image is a function returning a 2D array containing the image > data. > img_height is an integer. Why doesn't the (1) go with the array? -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:53:04 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!o26g2000vby.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Is this a VHDL limitation, or Modelsim bug Date: Mon, 11 Apr 2011 15:12:58 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <1c8f0e93-01c7-498b-b2c6-5b69130544a7@o26g2000vby.googlegroups.com> References: <90gulfFpn9U1@mid.individual.net> NNTP-Posting-Host: 213.104.217.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302559978 14583 127.0.0.1 (11 Apr 2011 22:12:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Apr 2011 22:12:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o26g2000vby.googlegroups.com; posting-host=213.104.217.142; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4918 On Apr 11, 8:13=A0pm, Mike Treseler wrote: > On 4/11/2011 4:37 AM, Tricky wrote: > > > I have the following line of code: > > > img_height =A0 =A0 =A0 =A0 =A0 =A0 =A0:=3D ( img.get_image )'length(1); > > > img is a protected type. > > get_image is a function returning a 2D array containing the image > > data. > > img_height is an integer. > > Why doesn't the (1) go with the array? > > =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Mike Treseler n-d arrays, declared like this: type my_array is array( integer range <>, integer range <>, integer range etc etc) of integer; means that you have to specify which dimension you are talking about when you try and take an attribute, hence the (1). From newsfish@newsfish Tue Aug 9 07:53:04 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: devas Newsgroups: comp.lang.vhdl Subject: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 08:37:07 +0200 Organization: A noiseless patient Spider Lines: 16 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 12 Apr 2011 06:37:08 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="ZslfkjcUaqWzR39Tw0NfYg"; logging-data="15920"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18cI5Hfj4DdADJRG++lD2wq" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 Cancel-Lock: sha1:UDQPW+9x9Ry4KrdwClztjUN7ZSk= Xref: feeder.eternal-september.org comp.lang.vhdl:4919 Hi Gurus, What is your opinion for coding combinational logic (multiplexer) in VHDL. Using a conditional signal assignment or using a process? What are the pro's and con's for both? I can imagine that for simulation performance a process is efficienter as it will only be reached when one of the signals on the sens. list changes. A con could be the danger of an incomplete sens. list. I would like to know your opinion and what your are using. Thanks, Devas From newsfish@newsfish Tue Aug 9 07:53:04 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx01.iad01.newshosting.com!newshosting.com!novia!news-out.readnews.com!transit3.readnews.com!postnews.google.com!x18g2000yqe.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 00:01:49 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <19f24aaf-b117-47dd-9d23-6f67668efbc8@x18g2000yqe.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302591709 4442 127.0.0.1 (12 Apr 2011 07:01:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 07:01:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x18g2000yqe.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.16) Gecko/20110323 Ubuntu/10.04 (lucid) Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4920 On 12 Apr., 08:37, devas wrote: > Hi Gurus, > > What is your opinion for coding combinational logic (multiplexer) in > VHDL. Using a conditional signal assignment or using a process? What are > the pro's and con's for both? > > I can imagine that for simulation performance a process is efficienter > as it will only be reached when one of the signals on the sens. list > changes. A con could be the danger of an incomplete sens. list. > > I would like to know your opinion and what your are using. > > Thanks, > > Devas Hi Devas, with the upcoming of VHDL-2008 and the process(all) feature, the differences in performance and danger of simulation faults should be rendered to almost neglectable. Also with VHDL-2008 the when..else and with..select constructs can be used inside processes. So, even the coding style difference is mostly evened out. What's left is merely a question of personally prefered coding style. One might argue, that not all synthesis tools support this yet, but time flies and before long this won't be a problem anymore. --- My personal choice is to have as few concurrent code lines in my architecture as possible, and put every functional part in processes. Sometimes specific assignments to output ports are necessary, but that's just one-liners. Have a nice synthesis Eilert From newsfish@newsfish Tue Aug 9 07:53:05 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p16g2000vbi.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 01:16:41 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302596201 21762 127.0.0.1 (12 Apr 2011 08:16:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 08:16:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p16g2000vbi.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4921 On Apr 12, 7:37=A0am, devas wrote: > Hi Gurus, > > What is your opinion for coding combinational logic (multiplexer) in > VHDL. Using a conditional signal assignment or using a process? What are > the pro's and con's for both? > Theres not really a lot of difference. A signal assignment outside of a formal process is really just another process, with the sensitivity list set by the signals on the right hand side. so this code: output <=3D a when sel =3D '0' else b; is the same as: process(a, b, sel) begin if sel =3D '0' then output <=3D a; else output <=3D b; end if; end process; From newsfish@newsfish Tue Aug 9 07:53:05 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!d28g2000yqc.googlegroups.com!not-for-mail From: AllianceGlobalServices Newsgroups: comp.lang.vhdl Subject: IT consulting offshore application custom software development outsourcing services from Philadelphia, New Jersey, New York, Boston- Alliance Global Services Date: Tue, 12 Apr 2011 04:03:24 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: NNTP-Posting-Host: 183.82.117.168 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302606204 10103 127.0.0.1 (12 Apr 2011 11:03:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 11:03:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d28g2000yqc.googlegroups.com; posting-host=183.82.117.168; posting-account=K8umZQoAAADtiMCit-5hZ2nqeNYCEcor User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4922 Global IT consulting company in Boston, New Jersey, New York, Philadelphia specializing in offshore application custom software product development outsourcing maintenance, information publishing consulting and managed software testing outsourcing automation services www.allianceglobalservices.com From newsfish@newsfish Tue Aug 9 07:53:05 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!l11g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 07:11:55 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302617515 26327 127.0.0.1 (12 Apr 2011 14:11:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 14:11:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l11g2000yqb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4923 On Apr 12, 4:16=A0am, Tricky wrote: > On Apr 12, 7:37=A0am, devas wrote: > > > Hi Gurus, > > > What is your opinion for coding combinational logic (multiplexer) in > > VHDL. Using a conditional signal assignment or using a process? What ar= e > > the pro's and con's for both? > > Theres not really a lot of difference. A signal assignment outside of > a formal process is really just another process, with the sensitivity > list set by the signals on the right hand side. > > so this code: > > output <=3D a when sel =3D '0' else b; > > is the same as: > > process(a, b, sel) > begin > =A0 if sel =3D '0' then > =A0 =A0 output <=3D a; > =A0 else > =A0 =A0 output <=3D b; > =A0 end if; > end process; I see one major difference. The process is eight lines of code and the concurrent statement is only one. Which do you think is easier to read and provides fewer opportunities for errors? Rick From newsfish@newsfish Tue Aug 9 07:53:05 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v10g2000yqn.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 08:54:37 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302623948 26137 127.0.0.1 (12 Apr 2011 15:59:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 15:59:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v10g2000yqn.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 14j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4924 On Apr 12, 3:11=A0pm, rickman wrote: > > so this code: > > > output <=3D a when sel =3D '0' else b; > > > is the same as: > > > process(a, b, sel) > > begin > > =A0 if sel =3D '0' then > > =A0 =A0 output <=3D a; > > =A0 else > > =A0 =A0 output <=3D b; > > =A0 end if; > > end process; > > I see one major difference. =A0The process is eight lines of code and > the concurrent statement is only one. =A0Which do you think is easier to > read and provides fewer opportunities for errors? In the interests of civil discussion I'll temporarily pretend that this stance doesn't make my blood boil. Instead I'll politely point out that, on the very rare occasions when I really want something that simple as a standalone thing, then the concurrent statement is indeed probably better. Three-state I/O buffers are the best and commonest example. And I'll also politely point out that decomposing designs into pieces small enough to represent as concurrent statements makes each piece trivially easy to understand, but makes the whole design as comprehensible as a broken-up jigsaw puzzle. Taking a complicated thing and breaking it into lots of simple pieces doesn't make it simpler. It simply turns the complicated thing into a pile of pieces. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:05 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!tramontana.escomposlinux.org!cagarruta.escomposlinux.org!escomposlinux.org!news.antakira.com!news.glorb.com!postnews.google.com!l30g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 09:27:39 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302625941 23029 127.0.0.1 (12 Apr 2011 16:32:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 16:32:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l30g2000vbn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4925 On Apr 12, 11:54=A0am, Jonathan Bromley wrote: > On Apr 12, 3:11=A0pm, rickman wrote: > > I see one major difference. =A0The process is eight lines of code and > > the concurrent statement is only one. =A0Which do you think is easier t= o > > read and provides fewer opportunities for errors? > > Instead I'll politely point out that, on the > very rare occasions when I really want something > that simple as a standalone thing, then the > concurrent statement is indeed probably better. Based on what devas posted, the 'standalone thing' is all that one can guess that devas is interested in for the reasons that were listed. > > Taking a complicated thing and breaking it > into lots of simple pieces doesn't make it > simpler. =A0It simply turns the complicated > thing into a pile of pieces. I agree in principle...but in this case, the only context given by devas in his posting was in the pros and cons of coding a mux as either a conditional signal assignment or using a process. In this case, there is no 'complicated thing' being broken into simpler pieces. Your comment though is valid, but should be directed to devas within the context of 'hey, why are you spending time thinking about the coding of a mux'? The opportunities to code a mux by itself are relatively few and far between. The opportunities to describe logic that also includes mux-like behavior are far more numerous and rarely are enhanced by the ability to describe this behavior explicitly as a standalone thing (whether as a process or concurrent statement). But then again maybe devas is just getting started in design and/or VHDL or perhaps his interest is not in designing something in VHDL but is actually in simulator performance, or some theoretical language aspect, something more abstract, who knows? In any case, devas was already aware of the major drawback from the standpoint of creating reliable/maintainable designs of the process which is that of an incomplete sensitivity list (prior to VHDL-2008). On the other hand, devas seems misinformed (or maybe needs to experimentally try) about why he thinks the process approach would be more efficient in simulation than the concurrent assignment. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:05 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 19:58:57 +0100 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="2548"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18NJ8GIpJNfgEkL5hG8Eiz4jTaQD1gSqyA=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:GdaioJjCHLlyFsisWj0yTxcqrGA= Xref: feeder.eternal-september.org comp.lang.vhdl:4926 On Tue, 12 Apr 2011 09:27:39 -0700 (PDT), KJ wrote: >Based on what devas posted, the 'standalone thing' is all that one can >guess that devas is interested in for the reasons that were listed. I apologize if I confused or misled the OP. My post was responding to yet another clear description of the position that states "bugs increase monotonically with lines of code, therefore anything that locally reduces the number of lines of code is good". This I regard as such pernicious nonsense that I will unapologetically seize on any opportunity to challenge it, especially if expressed in a way that encourages the decomposition of designs into absurdly small and meaningless pieces. >In this case, there is no 'complicated thing' >being broken into simpler pieces. True. I carefully pointed out that this can happen, in some very specific situations, and there the shorter description is entirely appropriate. >Your comment though is valid, but should be directed to devas within >the context of 'hey, why are you spending time thinking about the >coding of a mux'? It could have been, but wasn't; that was not my target. The OP's question was reasonable, and evinced reasonable answers; it was the added spin on those answers that riled me. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:06 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!talisker.lacave.net!lacave.net!nospam.fr.eu.org!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!k30g2000yqb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 13:13:39 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 192.91.172.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302639219 5900 127.0.0.1 (12 Apr 2011 20:13:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 20:13:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k30g2000yqb.googlegroups.com; posting-host=192.91.172.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4927 For one simple, combinatorial function with one output, I prefer the concurrent assignment. Features that make me lean toward using a process include: more than one output controlled similarly by the same inputs, logic that feeds a register within the same architecture, nested if-then logic, existence of related logic that is already in a process Since one or more of these features is often present in my projects, I usually use processes with sequential statements, synchronous when possible. Extensive use of concurrent statements starts to look like coding a netlist (and reads like one too), instead of coding a synthesizeable behavior with sequential statements, which is usually easier to understand. Andy From newsfish@newsfish Tue Aug 9 07:53:06 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 13:23:03 -0800 Lines: 22 Message-ID: <90jqjiFhcaU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net YJ6yqRjObSMrQVKOwhE9GgklnjIOzI7lWwo3mrBOgl9AibKuBB Cancel-Lock: sha1:ZPkQlNwla96+5w9w1oltliqn+i0= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4928 On 4/11/2011 10:37 PM, devas wrote: > What is your opinion for coding combinational logic (multiplexer) in > VHDL. Using a conditional signal assignment or using a process? What are > the pro's and con's for both? > I would like to know your opinion and what your are using. Synthesis requires an entity. Since each entity has code overhead, I describe logic at a higher level for less overall code. I describe the entity output ports only in terms of input ports and local variables, rather than muxes and flops. For example in this stack design: http://bit.ly/fkbaqW no muxes are described directly, yet synthesis inferred several: http://bit.ly/g5Asyr -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:53:06 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r19g2000prm.googlegroups.com!not-for-mail From: "daniel.kho" Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 23:03:41 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> NNTP-Posting-Host: 203.126.136.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302674622 16019 127.0.0.1 (13 Apr 2011 06:03:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 06:03:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r19g2000prm.googlegroups.com; posting-host=203.126.136.142; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4929 On Apr 13, 4:13=A0am, Andy wrote: > For one simple, combinatorial function with one output, I prefer the > concurrent assignment. Yes, for me as well. If a block (or sub-block) seems simple enough to describe as a one-liner (or a few lines) of concurrent statements, go for it. If my block/sub-block starts getting a bit more complex, I'll start putting those concurrent statements within a process instead. When it gets difficult to behaviourally describe your functionality with just a few concurrent statements, and when you start breaking up a concurrent statement to multiple smaller concurrent statements, that's when you're beginning to change your behavioural design to a structural one, i.e. one that doesn't describe the behaviour and therefore is difficult to understand. When I could foresee that I'm heading this (wrong) direction, I'll steer myself back to enclose those statements in a process, and add whatever other functionality I need. Daniel Kho From newsfish@newsfish Tue Aug 9 07:53:06 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Joseph Newsgroups: comp.lang.vhdl Subject: Incorrect simulation of a shift register in multiplication Date: Wed, 13 Apr 2011 00:00:13 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <6a57293b-d385-4f19-9d50-f8781d3a95e8@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 78.133.124.146 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302678013 17390 127.0.0.1 (13 Apr 2011 07:00:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 07:00:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.133.124.146; posting-account=E3caeQkAAAAyJzC8H7b3MNpCrpcqXmGO User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4930 Hi all, I am synthesizing a well known add-shift multiplication routine. I have the= Multiplier register Q ,an addition register A and a Carry register C (the = carry of the adder) which are concatenated together to give the multiplicat= ion results. For the shifting part I am writing the following code: Q <=3D A(0) & Q(3 downto 1); A <=3D C & A(3 downto 1); That should perform a right shift in both A and Q. This is being done in a = clocked process so registers are being created (that is working). When synt= hesizing using Xilinx and simulating using ISIM the right shift is being pe= rformed but the LSB of Q never has the correct value. Am I coding it incorrectly in Xilinx? Regards, Joseph From newsfish@newsfish Tue Aug 9 07:53:06 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z7g2000prh.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 04:19:09 -0700 (PDT) Organization: http://groups.google.com Lines: 64 Message-ID: <0a450894-cc76-4769-be03-c32a169c5f84@z7g2000prh.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302693617 17444 127.0.0.1 (13 Apr 2011 11:20:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 11:20:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z7g2000prh.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4931 On Apr 12, 11:54=A0am, Jonathan Bromley wrote: > On Apr 12, 3:11=A0pm, rickman wrote: > > > > > > so this code: > > > > output <=3D a when sel =3D '0' else b; > > > > is the same as: > > > > process(a, b, sel) > > > begin > > > =A0 if sel =3D '0' then > > > =A0 =A0 output <=3D a; > > > =A0 else > > > =A0 =A0 output <=3D b; > > > =A0 end if; > > > end process; > > > I see one major difference. =A0The process is eight lines of code and > > the concurrent statement is only one. =A0Which do you think is easier t= o > > read and provides fewer opportunities for errors? > > In the interests of civil discussion I'll > temporarily pretend that this stance doesn't > make my blood boil. > > Instead I'll politely point out that, on the > very rare occasions when I really want something > that simple as a standalone thing, then the > concurrent statement is indeed probably better. > Three-state I/O buffers are the best and > commonest example. > > And I'll also politely point out that > decomposing designs into pieces small enough > to represent as concurrent statements makes > each piece trivially easy to understand, but > makes the whole design as comprehensible as > a broken-up jigsaw puzzle. > > Taking a complicated thing and breaking it > into lots of simple pieces doesn't make it > simpler. =A0It simply turns the complicated > thing into a pile of pieces. > -- > Jonathan Bromley Ok Jonathan, take a deep breath. Now, tell me what you *really* feel! I think if you read my post again, you will see that all I am saying is that the above code is much simpler written as one line of concurrent code than eight lines of process. I'm not espousing a philosophy or promoting anything about a standard practice. I'm just saying that the two code examples do exactly the same thing and one is *much* simpler than the other. What exactly did you think was in my post that I am not aware of? Rick From newsfish@newsfish Tue Aug 9 07:53:06 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!dr5g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 04:28:06 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302694087 17055 127.0.0.1 (13 Apr 2011 11:28:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 11:28:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dr5g2000vbb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4932 On Apr 12, 2:58=A0pm, Jonathan Bromley wrote: > On Tue, 12 Apr 2011 09:27:39 -0700 (PDT), KJ wrote: > >Based on what devas posted, the 'standalone thing' is all that one can > >guess that devas is interested in for the reasons that were listed. > > I apologize if I confused or misled the OP. =A0My post > was responding to yet another clear description of the > position that states "bugs increase monotonically with > lines of code, therefore anything that locally reduces > the number of lines of code is good". =A0This I regard as > such pernicious nonsense that I will unapologetically > seize on any opportunity to challenge it, especially > if expressed in a way that encourages the decomposition > of designs into absurdly small and meaningless pieces. > > >In this case, there is no 'complicated thing' > >being broken into simpler pieces. > > True. =A0I carefully pointed out that this can happen, in some > very specific situations, and there the shorter description > is entirely appropriate. > > >Your comment though is valid, but should be directed to devas within > >the context of 'hey, why are you spending time thinking about the > >coding of a mux'? > > It could have been, but wasn't; that was not my target. > The OP's question was reasonable, and evinced reasonable > answers; it was the added spin on those answers that > riled me. > -- > Jonathan Bromley I should have read all the posts before I replied to your earlier one. This tells me a bit more, but you are making claims without supporting them. Can you tell me why you believe your position? So far you have simply stated it. Rick M: An argument isn't just contradiction. A: It can be. M: No it can't. An argument is a connected series of statements intended to establish a proposition. A: No it isn't. M: Yes it is! It's not just contradiction. A: Look, if I argue with you, I must take up a contrary position. M: Yes, but that's not just saying 'No it isn't.' A: Yes it is! M: No it isn't! From newsfish@newsfish Tue Aug 9 07:53:07 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gandalf.srv.welterde.de!weretis.net!feeder4.news.weretis.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!dr5g2000vbb.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Incorrect simulation of a shift register in multiplication Date: Wed, 13 Apr 2011 05:28:46 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <4a32911a-acd2-452b-817f-80ab1b51981f@dr5g2000vbb.googlegroups.com> References: <6a57293b-d385-4f19-9d50-f8781d3a95e8@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302697726 30020 127.0.0.1 (13 Apr 2011 12:28:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 12:28:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dr5g2000vbb.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9396) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4933 On 13 Apr., 09:00, Joseph wrote: > Q <=3D A(0) & Q(3 downto 1); > A <=3D C & A(3 downto 1); > > That should perform a right shift in both A and Q. This is being done in = a clocked process so registers are being created (that is working). When sy= nthesizing using Xilinx and simulating using ISIM the right shift is being = performed but the LSB of Q never has the correct value. This code snipplet has to less information. Actually there are plenty of reasons why a vhdl code simulates different than the synthesis result of this code. Without further information it is not predictabel which reason is your problem. You can not "code it incorrect in Xilinx". But you can easily write vhdl code which has "misleading" simulation result compared to the netlist you get after synthesis independend of the used tools. bye Thomas From newsfish@newsfish Tue Aug 9 07:53:07 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!y31g2000vbp.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 06:05:10 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302699911 21554 127.0.0.1 (13 Apr 2011 13:05:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 13:05:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000vbp.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4934 On Apr 13, 2:03=A0am, "daniel.kho" wrote: > On Apr 13, 4:13=A0am, Andy wrote: > > > For one simple, combinatorial function with one output, I prefer the > > concurrent assignment. > > Yes, for me as well. If a block (or sub-block) seems simple enough to > describe as a one-liner (or a few lines) of concurrent statements, go > for it. If my block/sub-block starts getting a bit more complex, I'll > start putting those concurrent statements within a process instead. > > When it gets difficult to behaviourally describe your functionality > with just a few concurrent statements, and when you start breaking up > a concurrent statement to multiple smaller concurrent statements, > that's when you're beginning to change your behavioural design to a > structural one, i.e. one that doesn't describe the behaviour and > therefore is difficult to understand. When I could foresee that I'm > heading this (wrong) direction, I'll steer myself back to enclose > those statements in a process, and add whatever other functionality I > need. > > Daniel Kho I don't have any grand rules for when I describe combinatorial logic with a process, but it is seldom, mainly because I don't like maintaining the sensitivity list. Mostly the logic I code is included in sequential processes, but there are times when it doesn't make sense from a decomposition point of view to include some of the logic in the sequential process. Then I put it is concurrent statements. A data path mux is a perfect example of that. If the concurrent statements get too complex, I will use a process. I did that for some code controlling a couple of status LEDs. The concurrent logic was getting complex because of multiple modes displaying different status. The muxing was rather complex and hard to understand. In a process the IF statement structure was more clear. But for signal path logic it is often a series arrangement of processing steps. Putting that in a process requires that some of the outputs which feed into the logic for the next step be included in the sensitivity list. I find this rather messy. Otherwise these intermediate values need to be expressed with variables. But variables don't show up in the waveform display, at least in ActiveHDL. So I find variables harder to use in debug and only use them when there is a clear advantage, like in test benches. I've never had any real issues expressing a linear flow in four concurrent statements rather than four sequential statements inside the several lines of code to setup a process. Rick From newsfish@newsfish Tue Aug 9 07:53:07 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!w6g2000vbo.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Incorrect simulation of a shift register in multiplication Date: Wed, 13 Apr 2011 07:42:56 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: References: <6a57293b-d385-4f19-9d50-f8781d3a95e8@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302705776 20999 127.0.0.1 (13 Apr 2011 14:42:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 14:42:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w6g2000vbo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4935 Not enough info. Are the other bits getting "correct" values? How can you tell that Q(0) is not getting the "correct" value? (What is the correct value?) Andy From newsfish@newsfish Tue Aug 9 07:53:07 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w7g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 08:24:58 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302708299 15990 127.0.0.1 (13 Apr 2011 15:24:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 15:24:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w7g2000pre.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4936 I think there are two arguments in play here: how to describe combinatorial logic, and whether it needs to be described combinatorially at all. I very rarely need to describe combinatorial logic outside the context of a synchronous process, so that sensitivity lists and latches are rarely a problem. I usually debug source code, not waveforms, so variables not showing up in waveforms would not be a big issue for me, especially compared to the advantages of using variables. Andy From newsfish@newsfish Tue Aug 9 07:53:07 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!b13g2000prf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 09:06:26 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> NNTP-Posting-Host: 206.83.242.170 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302710918 12136 127.0.0.1 (13 Apr 2011 16:08:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 16:08:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b13g2000prf.googlegroups.com; posting-host=206.83.242.170; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4937 On Apr 13, 11:24=A0am, Andy wrote: > I think there are two arguments in play here: how to describe > combinatorial logic, and whether it needs to be described > combinatorially at all. > > I very rarely need to describe combinatorial logic outside the context > of a synchronous process, so that sensitivity lists and latches are > rarely a problem. > > I usually debug source code, not waveforms, so variables not showing > up in waveforms would not be a big issue for me, especially compared > to the advantages of using variables. > > Andy Wow, we work so differently. The big difference between HDL and software that I love is the fact that I can access any point in the design with a simulation scope probe to see just what is happening. The few times I have used the code debugging tools I find them to be fairly painful to get to the point of the issue. Maybe I'm just not experienced enough with them. Rick From newsfish@newsfish Tue Aug 9 07:53:07 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin.stu.neva.ru!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!o21g2000prh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 10:05:02 -0700 (PDT) Organization: http://groups.google.com Lines: 55 Message-ID: <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302714302 17198 127.0.0.1 (13 Apr 2011 17:05:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 17:05:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o21g2000prh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4938 On Apr 13, 12:06=A0pm, rickman wrote: > On Apr 13, 11:24=A0am, Andy wrote: > > > I think there are two arguments in play here: how to describe > > combinatorial logic, and whether it needs to be described > > combinatorially at all. > > > I very rarely need to describe combinatorial logic outside the context > > of a synchronous process, so that sensitivity lists and latches are > > rarely a problem. > > > I usually debug source code, not waveforms, so variables not showing > > up in waveforms would not be a big issue for me, especially compared > > to the advantages of using variables. > > > Andy > > Wow, we work so differently. =A0The big difference between HDL and > software that I love is the fact that I can access any point in the > design with a simulation scope probe to see just what is happening. I agree. Debugging the source code implies that you have identified an incorrect behavior (presumably via an assertion or observation of some other 'incorrect' output) AND you have restarted the simulation to get it up near the suspected time of the failure so you can step through or otherwise 'debug the source code'. Not only is restarting the sim wasted time (although maybe it's not a 'lot' of time depending on the particular design) but if you guess incorrectly about the time that the root cause of the failure occurred you may have to restart the sim again...all because there is no equivalent to 'log -r /*' that captures the history of all variables in a design. Debugging with the waveform allows one to easily plop down the entire history of any signal anywhere in the entire design and testbench. The cost is a single command ('log -r /*') and some extra wall clock time and disk space to store the data to disk. Whether or not that extra bit of wall clock time was 'well spent' or not can be user dependent, I've found it to be 'worth it'. Which is 'best', is most likely a very user dependent question. Either way can work. To be efficient at using one method or the other may take time, but in the end I would guess that one can be equally productive either way. If there is a compelling reason for one way versus the other, I haven't heard about it. As a side note, to work around the issue of wanting to use sequential statements (because it more readily conveys the design intent) but need an unclocked signal but don't want to bother with sensitivity lists, there is always the ability to define a function or a procedure and instantiate call that function/procedure out just like a concurrent assignment. You get all of the benefits of sequential statement syntax along with proper checking of inputs (no missing signals in the sensitivity list) and a combinatorial output. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:08 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l6g2000vbn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 15:31:08 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302733967 5454 127.0.0.1 (13 Apr 2011 22:32:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 22:32:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000vbn.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4939 I use waveforms occasionally to get a look at an interface (external or internal) but those are always signals anyway (ports). I use assertions in both the RTL and the testbench which stop the simulation when something goes wrong, then I can observe the variables and signals I need, and insert a few breakpoints and monitors if necessary. Given the cyclical nature of most hardware designs, it is often not necessary to "back up" to see what happened, just catch it again on the next time around. Backing up can be a pain though if I have to. Most of the RTL assertions get put in during design or unit testing, so they are already there by the time I have a larger system simulation that would be time consuming to restart (and that would be severely slowed down by dumping every signal to a file "just in case".) I'm a big proponent of self-checking testbenches, and they don't use waveforms either. Most of us use methods we are most comfortable with, and using waveforms is very similar to the typical test equipment in the lab that we learned on. I started using the source code debugger after working with the SW driver guys to debug HW/SW issues in the lab. I had also taken a couple of Ada courses to sharpen my VHDL, and was exposed to the techniques there. Then I started trying some of those techniques in my VHDL simulations, and it worked well for me. But what works well for me may not work for others. Having multiple examples to accomplish the same thing allows users to find what works best for them individually. Andy From newsfish@newsfish Tue Aug 9 07:53:08 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 00:04:03 +0100 Organization: A noiseless patient Spider Lines: 89 Message-ID: <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="20054"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+N0AK5K6tjig8pYjlH+C1Zh8XV2675Nrs=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:wpMS2cQSkfZUIPuLy5Gir+y0Gyo= Xref: feeder.eternal-september.org comp.lang.vhdl:4940 On Wed, 13 Apr 2011 04:28:06 -0700 (PDT), rickman wrote: > you are making claims without >supporting them. Can you tell me why you believe your position? So >far you have simply stated it. OK, let's keep separate things separate. The bit that got my dander up was your implied, but clear, statement that fewer lines of code makes for fewer bugs. Others have stated this much more starkly than you did. I rather strongly disagree with it. Whilst it is evidently true that adding more code to any project will of course increase the number of bugs, since code is rarely bug-free, that in itself provides not a shred of evidence that the implementation of a given set of functionality will have fewer bugs if implemented using coding techniques that result in fewer lines of code. My own experience suggests that very compact, dense coding styles increase the risk of subtle hidden bugs and oversights that are very hard to track down. A more literate coding style generally leads to more easily debugged code. Clearly you can go too far the other way - verbosity for its own sake is unlikely to help, and in particular it is never a good idea to have redundancy in code. But the basic argument that leads to the mantra "code it in fewer characters and you'll get fewer bugs" is groundless, and I'm convinced it has led to misguided choices in the design and application of HDLs. More directly related to what you posted is the question of the most desirable granularity to which you should decompose a problem. I think I was clear enough in my discomfort there. You can always make each piece of a design trivially easy to understand, simply by decomposing it into pieces that are small enough. Is a shift register small enough for you? A flop? A mux? A transistor? The snag is, this simplification comes at an unacceptable price: it hides the real functionality of the design or design fragment. As others have indicated, it's probably unhelpful to lay down rigid guidelines here. I can suggest some touchstones: is the piece of code amenable to testing that will show whether it does what you need it to do, without wasting effort by testing some function such as a mux that's already well-known to work? Can I write a few lines of comment in the code that describe succinctly what it does, and why it's there? Can I relate this fragment to any kind of specification or requirement? The reality, though, is that the optimum choices depend on the people doing the work, the nature of the problem, the customer's demands and a whole pile of other things. Despite all this fence-sitting, there is something that seems obvious to me. Breaking a design into excessively small pieces (transistors!!) clearly obscures its functionality. Leaving a design in huge monolithic chunks (an entire FPGA in one VHDL process!!) is clearly hopeless too; no-one could possibly understand it. Somewhere in the middle there is an optimum - not ideal, but certainly better than either end of that spectrum. Merely saying "simpler is better" is inadequate. For me, pieces of design small enough to write as a single concurrent statement are almost never big enough to give me useful clues about how they contribute to the overall functionality (unless you put a function call in the expression). Sorry about the lengthy ramblings. You did ask for a justification :-) -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:08 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!y31g2000vbp.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 01:18:23 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 195.27.20.17 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302769103 606 127.0.0.1 (14 Apr 2011 08:18:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 08:18:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000vbp.googlegroups.com; posting-host=195.27.20.17; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4941 On Apr 13, 11:31=A0pm, Andy wrote: > I use waveforms occasionally to get a look at an interface (external > or internal) but those are always signals anyway (ports). I use > assertions in both the RTL and the testbench which stop the simulation > when something goes wrong, then I can observe the variables and > signals I need, and insert a few breakpoints and monitors if > necessary. Given the cyclical nature of most hardware designs, it is > often not necessary to "back up" to see what happened, just catch it > again on the next time around. Backing up can be a pain though if I > have to. Most of the RTL assertions get put in during design or unit > testing, so they are already there by the time I have a larger system > simulation that would be time consuming to restart (and that would be > severely slowed down by dumping every signal to a file "just in > case".) I'm a big proponent of self-checking testbenches, and they > don't use waveforms either. > > Most of us use methods we are most comfortable with, and using > waveforms is very similar to the typical test equipment in the lab > that we learned on. I started using the source code debugger after > working with the SW driver guys to debug HW/SW issues in the lab. I > had also taken a couple of Ada courses to sharpen my VHDL, and was > exposed to the techniques there. Then I started trying some of those > techniques in my VHDL simulations, and it worked well for me. > > But what works well for me may not work for others. Having multiple > examples to accomplish the same thing allows users to find what works > best for them individually. > > Andy I can see where you're coming from andy. Ideally, your final test should be a black box test, with a self checking testbench. It worries me when I see designers stare at waveforms all day and using this for their verification. They should be using output data as the test - no waveforms needed. Working in video I use bitmaps for input and output data. Its so much easier looking at a whole picture than looking at a stream of pixels. Often this output picture gives you a clue as to whats wrong - its normally very obviously when something has gone wrong doing this. Then I can get in amongst the waveform for more specific debugging, using the clues from the output. From newsfish@newsfish Tue Aug 9 07:53:08 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 09:37:37 +0100 Organization: TRW Conekt Lines: 39 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net WVbF7vCgSRXe1/b9eM7PlQk4YzJMS5+94/zbzuwvch/rzqWHg= Cancel-Lock: sha1:qTYjznHdl1/r6SAUqqq1NxoT5R0= sha1:4WDupvi4GOAA7tnmOWHHd4z+nhw= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4942 Andy writes: > I use waveforms occasionally to get a look at an interface (external > or internal) but those are always signals anyway (ports). I use > assertions in both the RTL and the testbench which stop the simulation > when something goes wrong, then I can observe the variables and > signals I need, and insert a few breakpoints and monitors if > necessary. That's much the same as the methods I use (and even the odd printf^H^H^H^H^H report statement :) I'm sure Aldec can put variables in the wave window - it may be that (as with Modelsim) you have to do it before the sim for it to log them. At the subblock level, adding a few variables and restarting is not usually a killer - especially when you have asserts already in to stop the simulation as soon as things go wrong. (The variables I want to see are usually state variables - it'd be great to be able to do "log -r *state" on variables :) > Most of us use methods we are most comfortable with, and using > waveforms is very similar to the typical test equipment in the lab > that we learned on. I started using the source code debugger after > working with the SW driver guys to debug HW/SW issues in the lab. I > had also taken a couple of Ada courses to sharpen my VHDL, and was > exposed to the techniques there. Then I started trying some of those > techniques in my VHDL simulations, and it worked well for me. And there are times when I'm writing embedded software that I'd really like a waveform trace of my C variables :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Aug 9 07:53:08 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q40g2000prh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 05:56:36 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302785796 31242 127.0.0.1 (14 Apr 2011 12:56:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 12:56:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q40g2000prh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4943 On Apr 14, 4:18=A0am, Tricky wrote: > On Apr 13, 11:31=A0pm, Andy wrote: > > Ideally, your final test > should be a black box test, with a self checking testbench. It worries > me when I see designers stare at waveforms all day and using this for > their verification. They should be using output data as the test - no > waveforms needed. Just to be clear, I'm not talking about using waveforms for verification. What they are used for is investigation when the verification assertion fails...after all, one does not intentionally write bad code in the first place so the fact that an assertion has failed implies there is a problem somewhere that needs investigating. If the root cause of the problem (which you do not know a priori) happens to have occurred at the same time as the assertion (which is a symptom, not the problem itself), then one will have access to the *current* state of all signals and variables. Maybe that's enough to solve the problem, but many times one needs to see some history in addition to the current state of signals and variables in order to make the definitive diagnosis. By Andy's own admission he does not solve the current problem but typically can wait for the problem to occur again after the first time - "just catch it again on the next time around" - "and insert a few breakpoints and monitors if necessary" (implies running the sim s'more) Sometimes (maybe many times) that is sufficient. But it is just as likely that whatever the original problem that caused the first assertion, if you continue running the sim, has now caused a second downstream problem that just makes it more difficult because the symptoms of this secondary problem is less directly related to the original problem. Even the software guys write out a trace log file which captures important (to them) information about events that happen. They don't simply capture the current state of everything at the point of the failure...the history of what leads up to the problem is generally the key to solving the problem. The fact that this history gets stored in a file that is viewable as signals in a sim tool and not as a list of statement executions is not relevant and has nothing to do with 'source code debugging'. It means you're making use of the tools that are available. Not using the history that is available to you is a choice and has a cost, but that choice is not about 'source code debugging' versus 'waveform debugging' Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:08 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!matrix.darkstorm.co.uk!news-transit.tcx.org.uk!feeder.news-service.com!postnews.google.com!r35g2000prj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 10:34:15 -0700 (PDT) Organization: http://groups.google.com Lines: 55 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302802979 31174 127.0.0.1 (14 Apr 2011 17:42:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 17:42:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r35g2000prj.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4944 On Apr 14, 4:18=A0am, Tricky wrote: > On Apr 13, 11:31=A0pm, Andy wrote: > > > > > I use waveforms occasionally to get a look at an interface (external > > or internal) but those are always signals anyway (ports). I use > > assertions in both the RTL and the testbench which stop the simulation > > when something goes wrong, then I can observe the variables and > > signals I need, and insert a few breakpoints and monitors if > > necessary. Given the cyclical nature of most hardware designs, it is > > often not necessary to "back up" to see what happened, just catch it > > again on the next time around. Backing up can be a pain though if I > > have to. Most of the RTL assertions get put in during design or unit > > testing, so they are already there by the time I have a larger system > > simulation that would be time consuming to restart (and that would be > > severely slowed down by dumping every signal to a file "just in > > case".) I'm a big proponent of self-checking testbenches, and they > > don't use waveforms either. > > > Most of us use methods we are most comfortable with, and using > > waveforms is very similar to the typical test equipment in the lab > > that we learned on. I started using the source code debugger after > > working with the SW driver guys to debug HW/SW issues in the lab. I > > had also taken a couple of Ada courses to sharpen my VHDL, and was > > exposed to the techniques there. Then I started trying some of those > > techniques in my VHDL simulations, and it worked well for me. > > > But what works well for me may not work for others. Having multiple > > examples to accomplish the same thing allows users to find what works > > best for them individually. > > > Andy > > I can see where you're coming from andy. Ideally, your final test > should be a black box test, with a self checking testbench. It worries > me when I see designers stare at waveforms all day and using this for > their verification. They should be using output data as the test - no > waveforms needed. Working in video I use bitmaps for input and output > data. Its so much easier looking at a whole picture than looking at a > stream of pixels. Often this output picture gives you a clue as to > whats wrong - its normally very obviously when something has gone > wrong doing this. Then I can get in amongst the waveform for more > specific debugging, using the clues from the output. I agree that verification is best done by the code and not by viewing waveforms. In fact, sometimes I think that my project is actually a matter of debugging the test bench and the FPGA design being verified is just a side effect! The importance of proper verification is drummed into me every time I don't do it. Just like the time they omitted an unnecessary test on the Hubble Space Telescope. Rick From newsfish@newsfish Tue Aug 9 07:53:09 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!nx02.iad01.newshosting.com!newshosting.com!novia!news-out.readnews.com!transit3.readnews.com!postnews.google.com!l30g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 10:49:23 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302803364 9744 127.0.0.1 (14 Apr 2011 17:49:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 17:49:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l30g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4945 On Apr 14, 4:37=A0am, Martin Thompson wrote: > Andy writes: > > I use waveforms occasionally to get a look at an interface (external > > or internal) but those are always signals anyway (ports). I use > > assertions in both the RTL and the testbench which stop the simulation > > when something goes wrong, then I can observe the variables and > > signals I need, and insert a few breakpoints and monitors if > > necessary. > > That's much the same as the methods I use (and even the odd printf^H^H^H^= H^H > report statement :) =A0 > > I'm sure Aldec can put variables in the wave window - it may be that (as = with > Modelsim) you have to do it before the sim for it to log them. =A0At the = subblock > level, adding a few variables and restarting is not usually a killer - es= pecially > when you have asserts already in to stop the simulation as soon as things= go > wrong. Please show me how to do this. I have added variables to the waveform window until I was blue in the face and their values never show up. It makes some sense. Variables are not defined outside of the process, function or procedure and in many cases do not retain a value between invocations. So what would be displayed? I add variables by selecting them in the source file, right clicking and selecting "Add to waveform". But I can do this with anything in the design including VHDL keywords, so being able to add it to the waveform display doesn't mean anything. If I set a breakpoint and single step, I can see the variables in the Call Stack window and watch them change. But they never show up in the waveform. That further makes sense since a variable can change value several times with no time ticking off. How would you display that in a time based waveform? > (The variables I want to see are usually state variables - it'd be great > to be able to do "log -r *state" on variables :) > > > Most of us use methods we are most comfortable with, and using > > waveforms is very similar to the typical test equipment in the lab > > that we learned on. I started using the source code debugger after > > working with the SW driver guys to debug HW/SW issues in the lab. I > > had also taken a couple of Ada courses to sharpen my VHDL, and was > > exposed to the techniques there. Then I started trying some of those > > techniques in my VHDL simulations, and it worked well for me. > > And there are times when I'm writing embedded software that I'd really li= ke a > waveform trace of my C variables :) Too bad they don't have signals in C... Sometimes I turn variables into signals by outputting them on pins which can be displayed as waveforms by a logic analyzer. ;^) Rick From newsfish@newsfish Tue Aug 9 07:53:09 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z27g2000prz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 11:12:45 -0700 (PDT) Organization: http://groups.google.com Lines: 102 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302804766 23978 127.0.0.1 (14 Apr 2011 18:12:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 18:12:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z27g2000prz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4946 On Apr 13, 7:04=A0pm, Jonathan Bromley wrote: > On Wed, 13 Apr 2011 04:28:06 -0700 (PDT), rickman wrote: > > you are making claims without > >supporting them. =A0Can you tell me why you believe your position? =A0So > >far you have simply stated it. > > OK, let's keep separate things separate. > > The bit that got my dander up was your implied, but > clear, statement that fewer lines of code makes for > fewer bugs. =A0 Mistake #1. I didn't say that and you inferred rather than my implying it. "Which do you think is easier to read and provides fewer opportunities for errors?" I was comparing the two sets of code, not making a general statement. ...snipped resulting conclusions... > More directly related to what you posted > is the question of the most desirable > granularity to which you should decompose > a problem. =A0 At least here you don't say that I made a statement about granularity. This is your topic. I'm not even clear on how this issue results from the OP's post. I do see how it relates to a wider conversation about coding in general, but not how it connects to me or my post. What did I write in regards to this? ...snip resulting discussion... > Despite all this fence-sitting, there is > something that seems obvious to me. =A0 > Breaking a design into excessively small > pieces (transistors!!) clearly obscures > its functionality. =A0Leaving a design in > huge monolithic chunks (an entire FPGA > in one VHDL process!!) is clearly hopeless > too; no-one could possibly understand it. > Somewhere in the middle there is an > optimum - not ideal, but certainly better > than either end of that spectrum. =A0Merely > saying "simpler is better" is inadequate. I don't agree that any of the three approaches is the "right" one. Rather to understand the design you need to understand as many levels as are important to the design. Typically there are parts of an HDL design that I want to see from the 10,000 m view, some I want to see from 10 m, some while sitting in front of it and some I want to see with a microscope. It all depends on which parts are standard, straightforward stuff and which parts are doing something more complex that needs to be explained more clearly. There are many times I use concurrent code because adding it to a process adds nothing to the clarity. It is still an assignment, but now, for example, a data path mux is obscured by all the control logic statements or vice versa. But mostly I just don't use combinatorial processes except for exceptions where it makes the code more clear. > For me, pieces of design small enough to > write as a single concurrent statement are > almost never big enough to give me useful > clues about how they contribute to the > overall functionality (unless you put a > function call in the expression). I'm curious, how do you write, for example, a data path mux if you don't put it in a concurrent statement? Do you lump it in with unrelated stuff? I had a design for a mulaw encoder with two sources, the data from the CODEC and a tone generator as well as a mute function. I added the data path mux (with mute function) using a combinatorial statement because to me it was not part of the mulaw logic so I didn't want to put it in the process for the mulaw logic. In fact, all of the data path to connect the mulaw logic with the CODEC and the IP interface was concurrent statements, some just simple assignments with no logic to connect wires... er, I mean signals. Can you tell I've been working with Verilog lately? What would you have done differently? Funny, I think is was one time I used variables for the mulaw encoding because that seemed like the right way to go given that it was all combinatorial and required several sequential steps. It also translated easier from the C code I used as a reference. It had it's own test bench so debugging with variables was not really an issue. > Sorry about the lengthy ramblings. =A0You > did ask for a justification :-) Yup, be careful what you ask for... ;^) You are always good for some interesting perspectives. Thanks. Rick From newsfish@newsfish Tue Aug 9 07:53:09 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 15 Apr 2011 09:02:46 +0100 Organization: TRW Conekt Lines: 37 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net MpO7cc2mo02erF6ZjQyPqwV2QhHZ2eP2Vw7r63OlN8eOceUwg= Cancel-Lock: sha1:phWCIygQkcPKKJKNMuZvmce+RNg= sha1:EJU91+IoweAbjnSofSZLRI0ruBo= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4947 rickman writes: > Please show me how to do this. I have added variables to the waveform > window until I was blue in the face and their values never show up. > It makes some sense. Variables are not defined outside of the > process, function or procedure and in many cases do not retain a value > between invocations. So what would be displayed? I'm not an Aldec user, but on a brief perusal of the manual, I can't see how to do it either :( How disappointing! > If I set a breakpoint and single step, I can see the variables in the > Call Stack window and watch them change. But they never show up in > the waveform. That further makes sense since a variable can change > value several times with no time ticking off. How would you display > that in a time based waveform? Modelsim shows the value at the end of the process - effectively it wires it to a signal at the end of the process and displays that. >> And there are times when I'm writing embedded software that I'd really like a >> waveform trace of my C variables :) > > Too bad they don't have signals in C... Sometimes I turn variables > into signals by outputting them on pins which can be displayed as > waveforms by a logic analyzer. ;^) > Yep, BTDT too :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Aug 9 07:53:09 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!gu8g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 15 Apr 2011 07:16:30 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <548bc40d-239e-4d2a-bc3c-7c9186d4d711@gu8g2000vbb.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302876990 5222 127.0.0.1 (15 Apr 2011 14:16:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Apr 2011 14:16:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: gu8g2000vbb.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4948 On Apr 14, 1:12=A0pm, rickman wrote: > I'm curious, how do you write, for example, a data path mux if you > don't put it in a concurrent statement? =A0Do you lump it in with > unrelated stuff? =A0I had a design for a mulaw encoder with two sources, > the data from the CODEC and a tone generator as well as a mute > function. =A0I added the data path mux (with mute function) using a > combinatorial statement because to me it was not part of the mulaw > logic so I didn't want to put it in the process for the mulaw logic. > In fact, all of the data path to connect the mulaw logic with the > CODEC and the IP interface was concurrent statements, some just simple > assignments with no logic to connect wires... er, I mean signals. =A0Can > you tell I've been working with Verilog lately? > > What would you have done differently? > It depends... How is the datapath (mux) controlled? Is it some external control, or is it a mode within the encoder? If the encoder has a requirement that under certain internal modes or conditions, it needs to load data from a different source, then I generally code that behavior into the encoder. On the other hand, if something external is directly controlling the source of the data, then I might break that functionality out into a separate mux. And if that mux was the only thing related to that control, I might even make it a concurrent statement. The focus is more about the function than it is about the circuit that will implement the function. Think of the function not as a mux but as a choice of which data to load. Then asks questions like "who/what determines (not implements) the choice?" The answer will often lead to the appropriate coding. Also, a functional approach will more often lead to closer coupling between that code and the requirements documents for that code. Good requirements don't usually include "shall have a mux to select data...," but more like "shall load different data based on..." Andy From newsfish@newsfish Tue Aug 9 07:53:09 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!diablo2.news.osn.de!news.osn.de!diablo2.news.osn.de!195.114.241.69.MISMATCH!feeder.news-service.com!postnews.google.com!dn9g2000vbb.googlegroups.com!not-for-mail From: Peter Spjuth Newsgroups: comp.lang.vhdl Subject: Re: Is this a VHDL limitation, or Modelsim bug Date: Fri, 15 Apr 2011 11:20:40 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <1b282dd8-c48a-4f03-91c5-7a9f741abec9@dn9g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 62.119.43.195 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302891641 26163 127.0.0.1 (15 Apr 2011 18:20:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Apr 2011 18:20:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dn9g2000vbb.googlegroups.com; posting-host=62.119.43.195; posting-account=jm7q0goAAADpwFe3cgIgpxo53RNop6k7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4949 On 11 Apr, 14:37, Tricky wrote: > I have the following line of code: > > img_height =A0 =A0 =A0 =A0 =A0 =A0 =A0:=3D ( img.get_image )'length(1); I think ' must be preceeded by a name or function call, and in your case it is preceeded by a parenthesised expression. Does img.get_image'length(1) or img.get_image()'length(1) work? /Peter From newsfish@newsfish Tue Aug 9 07:53:10 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k36g2000vbr.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 15 Apr 2011 16:25:46 -0700 (PDT) Organization: http://groups.google.com Lines: 63 Message-ID: <14af7c89-4b3a-4618-93a6-0cac48f0873e@k36g2000vbr.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> <548bc40d-239e-4d2a-bc3c-7c9186d4d711@gu8g2000vbb.googlegroups.com> NNTP-Posting-Host: 65.201.150.158 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302909946 24758 127.0.0.1 (15 Apr 2011 23:25:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Apr 2011 23:25:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k36g2000vbr.googlegroups.com; posting-host=65.201.150.158; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4950 On Apr 15, 10:16=A0am, Andy wrote: > On Apr 14, 1:12=A0pm, rickman wrote: > > > I'm curious, how do you write, for example, a data path mux if you > > don't put it in a concurrent statement? =A0Do you lump it in with > > unrelated stuff? =A0I had a design for a mulaw encoder with two sources= , > > the data from the CODEC and a tone generator as well as a mute > > function. =A0I added the data path mux (with mute function) using a > > combinatorial statement because to me it was not part of the mulaw > > logic so I didn't want to put it in the process for the mulaw logic. > > In fact, all of the data path to connect the mulaw logic with the > > CODEC and the IP interface was concurrent statements, some just simple > > assignments with no logic to connect wires... er, I mean signals. =A0Ca= n > > you tell I've been working with Verilog lately? > > > What would you have done differently? > > It depends... How is the datapath (mux) controlled? Is it some > external control, or is it a mode within the encoder? If the encoder > has a requirement that under certain internal modes or conditions, it > needs to load data from a different source, then I generally code that > behavior into the encoder. On the other hand, if something external is > directly controlling the source of the data, then I might break that > functionality out into a separate mux. And if that mux was the only > thing related to that control, I might even make it a concurrent > statement. The mux is controlled by configuration register settings in a different module, but also has a real time Left/Right control. Really the mux is completely independent of the mulaw encode/decode. I wrote that up as a independent, reusable module and instantiate it. > The focus is more about the function than it is about the circuit that > will implement the function. Think of the function not as a mux but as > a choice of which data to load. Then asks questions like "who/what > determines (not implements) the choice?" The answer will often lead to > the appropriate coding. Also, a functional approach will more often > lead to closer coupling between that code and the requirements > documents for that code. Good requirements don't usually include > "shall have a mux to select data...," but more like "shall load > different data based on..." Yes, exactly. Many of these independent functions that can be made peripheral to a given function are coded as concurrent statements. But there are times when I use concurrent signals to support easier debugging. I don't recall the exact portion of the design, but I had another function in this same design that was largely arithmetic. To facilitate debugging I coded each step as concurrent so that each intermediate value was a signal. Even if Active HDL would display variables, they can't really be viewed properly if they are not updated in a signal like manner. How do you view a sum of products when it is updated in a loop as a variable? It all happens in one instant in time when viewed in a waveform. Yes, you can use breakpoints and such, but that is a separate issue. Maybe there are things I can learn about this. I'll give code debugging (vs waveform debugging) another try next time I code up some HDL. Rick From newsfish@newsfish Tue Aug 9 07:53:10 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m23g2000prl.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Sat, 16 Apr 2011 08:41:53 -0700 (PDT) Organization: http://groups.google.com Lines: 64 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> <548bc40d-239e-4d2a-bc3c-7c9186d4d711@gu8g2000vbb.googlegroups.com> <14af7c89-4b3a-4618-93a6-0cac48f0873e@k36g2000vbr.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302968514 25965 127.0.0.1 (16 Apr 2011 15:41:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 16 Apr 2011 15:41:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m23g2000prl.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4951 On Apr 15, 7:25=A0pm, rickman wrote: > > Maybe there are things I can learn about this. =A0I'll give code > debugging (vs waveform debugging) another try next time I code up some > HDL. > Just curious here... - Would you turn off your monitor and use a speech synthesizer to read what is on your display to you? - Do you close the source window (and not view the source code via an editor) when you're debugging HDL designs today? Presuming the answer to these questions is 'no', then what do you think is to be gained by not using information that is currently available to you? Do you think you would be more productive? If so, can you explain why? I'm making the assumption with these question that when you say "I'll give code debugging (vs waveform debugging) another try" that this would mean, among other things, not displaying waveforms, instead using only the source code window and their tools. Which leads to the questions above about why you think it would be better to not use information that is available to solve the problem at hand. But of course, based on your postings, you seem a bit more practical than that and the reality is that you probably mean that you would try supplementing using waveforms with source code tools such as breakpoints and single stepping and such. On that premise... - If a problem occurs, do you typically try to solve it by waiting for it to happen again? - Even if, in your experience, it has turned out that 'waiting for it to happen again' will not usually mask the true problem and allows you to fix the problem, do you think that is a good methodology? - When you've solved problems in the past, are you always (or almost always) able to solve it using no other information than what is currently available right now? Looking only at present signal and variable values at the time of the failure, with no history of what led up to the event other that what you must infer by knowledge of the design and must retain in your head (or perhaps scribbled down on paper) since there is no history that can be displayed? Presumably the answer to all of these questions is also 'no' which suggests that making use of information that is readily available in whatever form would be a 'good thing' that most anyone with experience would make use of when solving the problem at hand...which then brings us around to the wrap up... Othen than if you've measured and found that logging signal activity to the disk during sim to be too high of a cost, then there really is no rationale to saying "code debugging vs waveform debugging". I'm not trying to slam you or anyone here on methods, being proficient in using source code tools is not a handicap. But those source code tools can only be applied to events *after* the bad thing has happened, they are of no help in diagnosing what has *already* ocurred short of restarting the sim (i.e. turning back the clock) so you must live with that limitation and work around it. Source code tools do allow you to step through and watch things unfold...but that would be using those tools for verification rather than debug....personally, I prefer testbenches for that task. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:10 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z37g2000vbl.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 19 Apr 2011 02:57:44 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303207064 12634 127.0.0.1 (19 Apr 2011 09:57:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Apr 2011 09:57:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z37g2000vbl.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.7.62 Version/11.00,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4952 On Apr 15, 9:02=A0am, Martin Thompson wrote: > rickman writes: > > > > > Please show me how to do this. =A0I have added variables to the wavefor= m > > window until I was blue in the face and their values never show up. > > It makes some sense. =A0Variables are not defined outside of the > > process, function or procedure and in many cases do not retain a value > > between invocations. =A0So what would be displayed? > > I'm not an Aldec user, but on a brief perusal of the manual, I can't see = how to > do it either :( =A0How disappointing! =A0 > IIRC, compiling with the debug flag (acom -dbg) will allow variables to be traced in the same way as signals. From newsfish@newsfish Tue Aug 9 07:53:10 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!cs.uu.nl!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!feeder.news-service.com!postnews.google.com!hd10g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 19 Apr 2011 08:01:13 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303225273 3759 127.0.0.1 (19 Apr 2011 15:01:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Apr 2011 15:01:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hd10g2000vbb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4953 On Apr 19, 5:57=A0am, Chris Higgs wrote: > On Apr 15, 9:02=A0am, Martin Thompson wrote: > > > rickman writes: > > > > > > > Please show me how to do this. =A0I have added variables to the wavef= orm > > > window until I was blue in the face and their values never show up. > > > It makes some sense. =A0Variables are not defined outside of the > > > process, function or procedure and in many cases do not retain a valu= e > > > between invocations. =A0So what would be displayed? > > > I'm not an Aldec user, but on a brief perusal of the manual, I can't se= e how to > > do it either :( =A0How disappointing! =A0 > > IIRC, compiling with the debug flag (acom -dbg) will allow variables > to be traced in the same way as signals. I use the GUI and in checking the preferences I see the compiler option "Enable Debug" is checked. Is that what you mean? I'm still not able to view variable as waveforms. Rick From newsfish@newsfish Tue Aug 9 07:53:10 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!e26g2000vbz.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 19 Apr 2011 08:25:56 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: References: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303226757 18947 127.0.0.1 (19 Apr 2011 15:25:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Apr 2011 15:25:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e26g2000vbz.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.7.62 Version/11.00,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4954 On Apr 19, 4:01=A0pm, rickman wrote: > I use the GUI and in checking the preferences I see the compiler > option "Enable Debug" is checked. =A0Is that what you mean? =A0I'm still > not able to view variable as waveforms. > > Rick Using Riviera-PRO on Linux (YMMV on other Aldec simulators/platforms) View->Debug Windows enable Hierarchy Viewer (shortcut alt + 5) and Object Viewer (alt + 6) After elaboration, navigate to the appropriate process and the variables declared by that process will show up in Object Viewer. Right click->Add to->Waveform. Alternatively use the command "wave sim:/path/to/your/process/ variable" From newsfish@newsfish Tue Aug 9 07:53:10 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!feeder1.hal-mli.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!bl1g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 19 Apr 2011 11:34:59 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> References: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303238100 5356 127.0.0.1 (19 Apr 2011 18:35:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Apr 2011 18:35:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: bl1g2000vbb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4955 On Apr 19, 11:25=A0am, Chris Higgs wrote: > On Apr 19, 4:01=A0pm, rickman wrote: > > > I use the GUI and in checking the preferences I see the compiler > > option "Enable Debug" is checked. =A0Is that what you mean? =A0I'm stil= l > > not able to view variable as waveforms. > > > Rick > > Using Riviera-PRO on Linux (YMMV on other Aldec simulators/platforms) > > View->Debug Windows enable Hierarchy Viewer (shortcut alt + 5) and > Object Viewer (alt + 6) > > After elaboration, navigate to the appropriate process and the > variables declared by that process will show up in Object Viewer. > Right click->Add to->Waveform. > > Alternatively use the command "wave sim:/path/to/your/process/ > variable" My UI is not the same, but in the process of messing about with it to see if it comes close to yours, I found how to do it. The Design Browser sounds like it is similar to your Hierarchy Viewer. Once I select the appropriate process the variables are available to add to the waveform. It seems odd that I can add signals to the waveform display from the source file, but not variables. This will help with debugging variables, but it still does not supplant the Call Stack and breakpoints because variables update in zero time and so waveforms won't show everything that happens with them. Rick From newsfish@newsfish Tue Aug 9 07:53:11 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r6g2000vbz.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 06:16:39 -0700 (PDT) Organization: http://groups.google.com Lines: 54 Message-ID: <894cf72f-66f4-4877-9438-916fdd8870e1@r6g2000vbz.googlegroups.com> References: <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303305399 13643 127.0.0.1 (20 Apr 2011 13:16:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Apr 2011 13:16:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r6g2000vbz.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 18j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4956 On Apr 19, 7:34=A0pm, rickman wrote: [variables in the wave view] > will help with debugging variables, but it still does not > supplant the Call Stack and breakpoints because variables update in > zero time and so waveforms won't show everything that happens with > them. But this is a red herring. Waveforms can't show everything that happens with signals, either. A signal's driver can be updated many times in a given delta cycle, and only the last such update will actually affect the signal in the upcoming delta. (Of course the story isn't even that simple in the general case, but for zero-delay RTL code it's close.) You can't see these driver updates unless you watch the code executing. I know, of course, that people tend to do more complicated things with variables than they do with repeated assignment to signals, so the problem may be more severe with variables in practice. But there isn't much difference in principle. The truth is that we EEs have grown accustomed to a level of visibility of our code's activity that makes little sense to software people, for whom invisible variables are a matter of routine. We get that visibility only because almost all the objects whose values we care about are static and can be traced/dumped easily as a function of simulation time. As soon as you start to do anything interesting and software-like, you can't do that quite so easily and it becomes much more important to be able to trace code execution - there's no shortage of ways to do it. Better still is to be able to reason about your code so that you can think your way through the offending code's behaviour to see where you messed-up. For me, a great way to achieve that is to add plenty of assertions; figuring out how to write the assertions is a powerful encouragement to think rigorously about your code, and if you find you *can't* write assertions that make sense, it's a fair bet that the code in question isn't properly designed. And well- written assertions often find the cause of an error long before its effect would be visible in waves. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:11 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.ripco.com!news.glorb.com!news2.glorb.com!postnews.google.com!y31g2000vbp.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 09:40:07 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <5d35ecd2-ebfa-4dc9-b08c-ab9a601099cc@y31g2000vbp.googlegroups.com> References: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303317607 5367 127.0.0.1 (20 Apr 2011 16:40:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Apr 2011 16:40:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000vbp.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4957 On Apr 19, 11:25=A0am, Chris Higgs wrote: > > After elaboration, navigate to the appropriate process and the > variables declared by that process will show up in Object Viewer. > Right click->Add to->Waveform. > > Alternatively use the command "wave sim:/path/to/your/process/ > variable" When you do that, does it show the entire history of the variable from t=3D0 until t=3Dnow? Or does it only allow you to see the variable from t=3Dnow until t=3Dfuture? KJ From newsfish@newsfish Tue Aug 9 07:53:11 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w36g2000vbi.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 10:04:36 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <1db3c2a3-32e1-437b-80e3-c1ae3743bbd7@w36g2000vbi.googlegroups.com> References: <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <5d35ecd2-ebfa-4dc9-b08c-ab9a601099cc@y31g2000vbp.googlegroups.com> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303319076 29598 127.0.0.1 (20 Apr 2011 17:04:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Apr 2011 17:04:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w36g2000vbi.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.7.62 Version/11.00,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4958 On Apr 20, 5:40=A0pm, KJ wrote: > > Alternatively use the command "wave sim:/path/to/your/process/ > > variable" > > When you do that, does it show the entire history of the variable from > t=3D0 until t=3Dnow? =A0Or does it only allow you to see the variable fro= m > t=3Dnow until t=3Dfuture? The variable is traced from t=3Dnow onwards (this is the same behaviour as tracing signals). Recording everything in the database in case you want to retrospectively view it (to allow t=3D0 until t=3Dnow) sounds expensive! There may be an option to do that but I've never needed it - I trace whatever signals/variables (using wildcards) before starting the simulation. From newsfish@newsfish Tue Aug 9 07:53:11 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l30g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 12:23:15 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <5f78136b-c633-4e19-987d-b5333b0101d9@l30g2000vbn.googlegroups.com> References: <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <5d35ecd2-ebfa-4dc9-b08c-ab9a601099cc@y31g2000vbp.googlegroups.com> <1db3c2a3-32e1-437b-80e3-c1ae3743bbd7@w36g2000vbi.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303327395 18804 127.0.0.1 (20 Apr 2011 19:23:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Apr 2011 19:23:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l30g2000vbn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4959 On Apr 20, 1:04=A0pm, Chris Higgs wrote: > On Apr 20, 5:40=A0pm, KJ wrote: > > > > Alternatively use the command "wave sim:/path/to/your/process/ > > > variable" > > > When you do that, does it show the entire history of the variable from > > t=3D0 until t=3Dnow? =A0Or does it only allow you to see the variable f= rom > > t=3Dnow until t=3Dfuture? > > The variable is traced from t=3Dnow onwards (this is the same behaviour > as tracing signals). Recording everything in the database in case you > want to retrospectively view it (to allow t=3D0 until t=3Dnow) sounds > expensive! There may be an option to do that but I've never needed it OK, good to know. For Modelsim, the 'log -r /*' logs all signals to disk (one can also be more specific about which signals if one chooses). I agree it *seems* like it should be expensive, but I haven't really found that to be the case. Then when I need a signal for debug it can be added to the wave window and the entire history is displayed. Having the entire history of every signal available to be waved is mighty handy. > - I trace whatever signals/variables (using wildcards) before starting > the simulation. Since I don't generally know what assertion will fail ahead of time, I don't know what signals I would be interested in prior to starting the simulation. I dislike restarting and re-running simulations because I guessed wrong about which signals I might want. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:11 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!32g2000vbe.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 17:58:10 -0700 (PDT) Organization: http://groups.google.com Lines: 91 Message-ID: References: <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> <894cf72f-66f4-4877-9438-916fdd8870e1@r6g2000vbz.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303347490 20704 127.0.0.1 (21 Apr 2011 00:58:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Apr 2011 00:58:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 32g2000vbe.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4960 On Apr 20, 9:16=A0am, Jonathan Bromley wrote: > On Apr 19, 7:34=A0pm, rickman wrote: > > [variables in the wave view] > > > will help with debugging variables, but it still does not > > supplant the Call Stack and breakpoints because variables update in > > zero time and so waveforms won't show everything that happens with > > them. > > But this is a red herring. =A0Waveforms can't show > everything that happens with signals, either. > > A signal's driver can be updated many times in a > given delta cycle, and only the last such update > will actually affect the signal in the upcoming > delta. =A0(Of course the story isn't even that > simple in the general case, but for zero-delay > RTL code it's close.) =A0You can't see these driver > updates unless you watch the code executing. I think you misrepresent what happens with a signal. Although many assignments can be made to a signal, it is never updated until the process reaches a stopping point, either a wait or the end of the process. Only then is the value of the signal updated. You may feel this is semantics, but the point is that I don't care about assignments that don't impact the value of the signal, the intention of the code is for them to be ignored. A variable is different. It is updated just like a variable in software where each intermediate value can be significant. If I can't see those intermediate values, I have lost information about the process which can make it harder to debug. Perhaps there is value in single stepping multiple assignments to a signal if you want to debug the code making those assignments. But the way I write code this is seldom and issue. About the only time I have multiple assignments to a signal in a process is when I first assign a default value and later assign another value in specific instances. This is not complex to debug and does not require single stepping or breakpoints. Waveform viewing works just fine for that. > I know, of course, that people tend to do more > complicated things with variables than they do > with repeated assignment to signals, so the > problem may be more severe with variables in > practice. =A0But there isn't much difference > in principle. In theory, theory and practice are the same; in practice they can differ considerably. The reality is that I very seldom use breakpoints and single stepping to debug signals. My logic design methods are easy to debug using waveforms. I don't see any reason to make that more complex than it is. > The truth is that we EEs have grown accustomed > to a level of visibility of our code's activity > that makes little sense to software people, for > whom invisible variables are a matter of routine. > We get that visibility only because almost all > the objects whose values we care about are static > and can be traced/dumped easily as a function of > simulation time. =A0As soon as you start to do > anything interesting and software-like, you > can't do that quite so easily and it becomes > much more important to be able to trace code > execution - there's no shortage of ways to do it. > > Better still is to be able to reason about your > code so that you can think your way through the > offending code's behaviour to see where you > messed-up. =A0For me, a great way to achieve that > is to add plenty of assertions; figuring out > how to write the assertions is a powerful > encouragement to think rigorously about your > code, and if you find you *can't* write assertions > that make sense, it's a fair bet that the code > in question isn't properly designed. =A0And well- > written assertions often find the cause of an > error long before its effect would be visible > in waves. > -- > Jonathan Bromley I use assertions in my test benches. I don't use them in my target code. Maybe there are things I can learn about that idea. Rick From newsfish@newsfish Tue Aug 9 07:53:11 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!c26g2000vbq.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 19:49:59 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <3ab7ef8d-af96-4ac7-b4f8-c6301a25f4e1@c26g2000vbq.googlegroups.com> References: <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> <894cf72f-66f4-4877-9438-916fdd8870e1@r6g2000vbz.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303354199 24263 127.0.0.1 (21 Apr 2011 02:49:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Apr 2011 02:49:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c26g2000vbq.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4961 On Apr 20, 8:58=A0pm, rickman wrote: > > I use assertions in my test benches. =A0I don't use them in my target > code. =A0Maybe there are things I can learn about that idea. > Assertions should also be placed wherever possible, definitely not restricted to testbench code. What you get then is a self checking design which is even better but usually not as comprehensive as a self checking testbench. Assertions in the design can be thought of as 'better' in that they will be active and checked which each and every instantiation of that widget, not just in the original testbench for the widget. Assertion in the design are usually 'not as comprehensive' in that it is not always practical to compute all of the outputs within the design itself. Interface handshake signal protocols can almost always be checked, the data path might not short of writing a second copy of the code. As an example, if you were to write the code for a JPEG encoder, you would probably be better off validating correct operation by reading files that have been computed by some separate widely used tool that presumably has a few miles under its belt. This type of thing though would best be put into a testbench for the encoder. If you put that form of checking into the encoder than each and every instantiation would have to somehow get the file name inputs through some private interface. In any case, it quickly becomes obvious which things 'could' be checked in the design and which probably should not...and then put those that 'could' be checked into the design so that they will be checked forever and for always. You'll get a more robust design since your self-checking design will catch bugs (or validate correct operation) as that design gets reused in other applications. On the other hand, if you don't develop any reusable widgets, it probably doesn't matter where you put your assertions. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:12 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 21 Apr 2011 20:30:03 -0800 Lines: 28 Message-ID: <91cei7Fi4lU1@mid.individual.net> References: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net SOp1dWJFProhzC3IxfSXtgbs1o5fMlPcwLN8lVQZMtr1Vt2ut+ Cancel-Lock: sha1:Fk8vWZXjS95BjL4I4ewlZLlZ9zM= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4962 On 4/19/2011 10:34 AM, rickman wrote: > My UI is not the same, but in the process of messing about with it to > see if it comes close to yours, I found how to do it. The Design > Browser sounds like it is similar to your Hierarchy Viewer. Once I > select the appropriate process the variables are available to add to > the waveform. It seems odd that I can add signals to the waveform > display from the source file, but not variables. Not odd at all. Suppose that two processes each had a variable named cnt_v. Since the variables are not the same, the only way to properly label the waves is by process. > This will help with debugging variables, but it still does not > supplant the Call Stack and breakpoints because variables update in > zero time and so waveforms won't show everything that happens with > them. In a synchronous design, the value of the wave is probably the one I want. If I really need to see the "gate by gate" (delta by delta) value, I trace code and break on a variable value. -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:53:12 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!z31g2000vbs.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 22 Apr 2011 10:45:55 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: <868e5d81-cab8-4d1d-ad1e-984bc284c7a0@z31g2000vbs.googlegroups.com> References: <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> <91cei7Fi4lU1@mid.individual.net> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303494355 32077 127.0.0.1 (22 Apr 2011 17:45:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Apr 2011 17:45:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z31g2000vbs.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4963 On Apr 22, 12:30=A0am, Mike Treseler wrote: > On 4/19/2011 10:34 AM, rickman wrote: > > > My UI is not the same, but in the process of messing about with it to > > see if it comes close to yours, I found how to do it. =A0The Design > > Browser sounds like it is similar to your Hierarchy Viewer. =A0Once I > > select the appropriate process the variables are available to add to > > the waveform. =A0It seems odd that I can add signals to the waveform > > display from the source file, but not variables. > > Not odd at all. > Suppose that two processes > each had a variable named cnt_v. > Since the variables are not the same, > the only way to properly > label the waves is by process. Why wouldn't the tool know which process a variable is in from the source??? Everything else comes from the source... > > This will help with debugging variables, but it still does not > > supplant the Call Stack and breakpoints because variables update in > > zero time and so waveforms won't show everything that happens with > > them. > > In a synchronous design, > the value of the wave is probably the one I want. > If I really need to see the > "gate by gate" (delta by delta) value, > I trace code and break on a variable value. Not delta by delta, but yes, gate by gate flow. That is what I'm saying. You don't get a choice with variables. If you need to see how they are calculated when used for intermediate values you have to trace the code. With signals every time the value changes, it is reflected in the state of the signal in the waveform display and you only need to look at the source once you have found the location of the problem. Of course there is no one size fits all, but waveforms seem to be the best approach for most problems. Rick From newsfish@newsfish Tue Aug 9 07:53:12 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!r19g2000prm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 22 Apr 2011 12:02:08 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> <894cf72f-66f4-4877-9438-916fdd8870e1@r6g2000vbz.googlegroups.com> <3ab7ef8d-af96-4ac7-b4f8-c6301a25f4e1@c26g2000vbq.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303498928 14462 127.0.0.1 (22 Apr 2011 19:02:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Apr 2011 19:02:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r19g2000prm.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4964 On Apr 20, 9:49=A0pm, KJ wrote: > > On the other hand, if you don't develop any reusable widgets, it > probably doesn't matter where you put your assertions. > > Kevin Jennings It is much easier to control the conditions under which an assertion is evaluated when the assertion is inserted into the design (RTL) code. A single concurrent assertion statement can make sure something allways/never happens. Strategically placing a sequential assertion statement inside an existing branch of the code allows specifically targeting that part of the code. And it is easier to access local variables/signals from within their scope. On the other hand, RTL assertions don't do much good when verifying the gate level model! Andy From newsfish@newsfish Tue Aug 9 07:53:12 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!u12g2000prn.googlegroups.com!not-for-mail From: "PSD to XHTML Conversion Services and PSD to HTML CSS Conversion Services, PSD to Joomla, Drupal, Wordpress Conversion" Newsgroups: comp.lang.vhdl Subject: PSD to XHTML Conversion Services and PSD to HTML CSS Conversion Services, PSD to Joomla, Drupal, Wordpress Conversion Date: Sun, 24 Apr 2011 23:43:41 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: NNTP-Posting-Host: 183.82.117.168 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1303713821 8836 127.0.0.1 (25 Apr 2011 06:43:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Apr 2011 06:43:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u12g2000prn.googlegroups.com; posting-host=183.82.117.168; posting-account=qaN5UAoAAAB_4ToMJWe5zHTmrge20E7i User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4965 PSD to XHTML Conversion, PSD to HTML CSS, Joomla, Wordpress, Drupal, CMS, VBULLETIN, PHPBB and includes convert to XHTML like PSD to XHTML, web designing services, logos and banner design, website building, animation,presentations and virtual tours from XHTML Champs.www.xhtmlchamps.com From newsfish@newsfish Tue Aug 9 07:53:12 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!a19g2000prj.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Mon, 25 Apr 2011 16:42:55 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: <50c4ed33-e155-47b1-b2f0-140536a61af6@a19g2000prj.googlegroups.com> References: NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303774976 19657 127.0.0.1 (25 Apr 2011 23:42:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Apr 2011 23:42:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a19g2000prj.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.0.10 NET_mmhpset ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4966 On Apr 8, 8:12=A0am, Tricky wrote: > Im building a model of a memory interface. The entity mimics the > interface of the normal memory interface with multiple request, > address, ack and data valid lines, one set per channel. Internally I > have a protected type that handles the memory modelling (dynamically > creating memory locations as they are accessed so I dont have a > monstrous 256Mbyte array declared) and another protected that handles > the read queue. > > As this is modelling a memory in a video system, I want to be able to > dump whole images (ie bypassing the whole interface) into memory, for > example if Im only testing the other bits of the design on the read > side of the interface. I have everything I need for reading/writing > bitmaps to specific array types, but I just need to get these arrays > into this entity. > In the past, I have used a separate transaction type of interface to handle this. It was real basic - send a memory word at a time. However, in VHDL-2008, you should be able to access the shared variable of the memory with an external name and use the methods provided by your protected type. Have not tried this application of external names, but I intend to soon. Best, Jim From newsfish@newsfish Tue Aug 9 07:53:12 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!multikabel.net!newsfeed20.multikabel.net!eweka.nl!lightspeed.eweka.nl!postnews.google.com!a21g2000prj.googlegroups.com!not-for-mail From: "PSD to XHTML Conversion Services and PSD to HTML CSS Conversion Services, PSD to Joomla, Drupal, Wordpress Conversion" Newsgroups: comp.lang.vhdl Subject: Web design services | website designing | hire a website designer | creative web Date: Mon, 25 Apr 2011 21:59:50 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <67364442-7f11-4d7f-afdc-8fc0d04046b0@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 183.82.117.168 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1303793991 16833 127.0.0.1 (26 Apr 2011 04:59:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 Apr 2011 04:59:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a21g2000prj.googlegroups.com; posting-host=183.82.117.168; posting-account=qaN5UAoAAAB_4ToMJWe5zHTmrge20E7i User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4967 web design services, XHTML Conversion Services, Offshore outsourcing web design & SEO Expert Acedezines provides best services for your website design, search engine optimization, web design services, brochure design, flash intro animation, website designing, wordpress themes. From newsfish@newsfish Tue Aug 9 07:53:14 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.visyn.net!visyn.net!newsfeed.in-ulm.de!not-for-mail From: Steffen Koepf Newsgroups: comp.lang.vhdl Subject: Very fast PWM in Cyclone III FPGA Date: Thu, 28 Apr 2011 18:52:02 +0000 (UTC) Organization: [ posted via ] IN-Ulm Lines: 27 Sender: Steffen Koepf Message-ID: X-Trace: news.in-ulm.de 1B0ECEB31F3E8713D5B79A9C6A5A2A20 User-Agent: tin/pre-1.4-19990805 ("Preacher Man") (UNIX) (Linux/2.6.30.10 (i686)) Xref: feeder.eternal-september.org comp.lang.vhdl:4980 Hello, i need a very fast PWM in a Cyclone III FPGA. If necessary, a Cyclone IV will do it too. I need a 80 KHz PWM for direct Gate Control in a Switchmode Power Supply. At the moment the Cyclone III is running at 400 MHz, which gives at 80 KHz 5000 Steps. I made it to be able to use the falling edge in my PWM- Comparator, too, so i have now 10000 Steps at 80 KHz. But the resolution is still not enough, i would like to have more steps. Using a -6 speed grade Cyclone III would allow 600 MHz, which gives around 15000 Steps. Does one know a way to get even more? Is there a way to use the SERDES LVDS to get a fast PWM? Is it possible to use the PLL to generate higher frequencies and use them for example by ANDing them for 4 sub-steps (two more bits)? Thanks in advance, Steffen From newsfish@newsfish Tue Aug 9 07:53:14 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!nuzba.szn.dk!pnx.dk!weretis.net!feeder4.news.weretis.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!e25g2000prf.googlegroups.com!not-for-mail From: rich12345 Newsgroups: comp.lang.vhdl Subject: looking for 14 pin flying lead cable Date: Thu, 28 Apr 2011 16:28:39 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <088d1dda-17d1-45f9-8f4b-f74a6fe4ad47@e25g2000prf.googlegroups.com> NNTP-Posting-Host: 71.142.220.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1304033319 26174 127.0.0.1 (28 Apr 2011 23:28:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Apr 2011 23:28:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e25g2000prf.googlegroups.com; posting-host=71.142.220.160; posting-account=5kmk9wkAAAB22-WWGK8UTn8vQ5c3EvdQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4981 I found it on diligent website, $4.00 for the part, $8.00 for shipping. Does anyone have a spare that they would sell for a reasonable price? this is the 14pin 2mm for Xilinx PlatformCable USB DLC9LP -r From newsfish@newsfish Tue Aug 9 07:53:14 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!hd10g2000vbb.googlegroups.com!not-for-mail From: kclo4 Newsgroups: comp.lang.vhdl Subject: Re: Very fast PWM in Cyclone III FPGA Date: Fri, 29 Apr 2011 04:36:59 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <978437ef-5190-4ca1-a79a-15b956cd4af6@hd10g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 192.54.144.229 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304077019 14649 127.0.0.1 (29 Apr 2011 11:36:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Apr 2011 11:36:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hd10g2000vbb.googlegroups.com; posting-host=192.54.144.229; posting-account=SeKPuAoAAAAYDoY2DhCLjM2K04fcGufr User-Agent: G2/1.0 X-HTTP-Via: 1.1 proxy:8080 (squid/2.5.STABLE3) X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4982 On Apr 28, 8:52=A0pm, Steffen Koepf wrote: > Hello, > > i need a very fast PWM in a Cyclone III FPGA. > If necessary, a Cyclone IV will do it too. > > I need a 80 KHz PWM for direct Gate Control in a Switchmode Power Supply. > > At the moment the Cyclone III is running at 400 MHz, which gives at 80 KH= z > 5000 Steps. I made it to be able to use the falling edge in my PWM- > Comparator, too, so i have now 10000 Steps at 80 KHz. > Why don't you use a NCO? you can have resolution under 1Hz > But the resolution is still not enough, i would like to have more steps. > > Using a -6 speed grade Cyclone III would allow 600 MHz, which gives aroun= d > 15000 Steps. > > Does one know a way to get even more? > Is there a way to use the SERDES LVDS to get a fast PWM? > > Is it possible to use the PLL to generate higher frequencies and use them > for example by ANDing them for 4 sub-steps (two more bits)? > > Thanks in advance, > > Steffen From newsfish@newsfish Tue Aug 9 07:53:14 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!news-transit.tcx.org.uk!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!a19g2000prj.googlegroups.com!not-for-mail From: NeedCleverHandle Newsgroups: comp.lang.vhdl Subject: Re: looking for 14 pin flying lead cable Date: Fri, 29 Apr 2011 08:03:32 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <1275e28b-60f4-4cf4-8ee8-b16a8c2a66f8@a19g2000prj.googlegroups.com> References: <088d1dda-17d1-45f9-8f4b-f74a6fe4ad47@e25g2000prf.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304089433 21710 127.0.0.1 (29 Apr 2011 15:03:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Apr 2011 15:03:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a19g2000prj.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4983 On Apr 28, 4:28=A0pm, rich12345 wrote: > I found it on diligent website, $4.00 for the part, $8.00 for > shipping. > > Does anyone have a spare that they would sell for a reasonable > price? > > this is the 14pin 2mm for Xilinx PlatformCable USB DLC9LP > > -r You say that you can get it from Digilent for $12.00 US delivered. Just how much less does it have to be to be "a reasonable price", and do you think someone is going to send it to you for that? Just wondering, RK From newsfish@newsfish Tue Aug 9 07:53:14 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: Anti-benchmarking clauses Date: Sat, 30 Apr 2011 00:50:34 +0000 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx02.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="28317"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ve9DRdQ7bwGDifbdsZBEicJo31GMExv79NjEJ4tFadQ==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> Cancel-Lock: sha1:hL0umTESL7oLy4cdAibaJCOXorM= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4984 comp.arch.fpga:15369 comp.lang.verilog:3049 Philippe sent on March 8th, 2011: |---------------------------------------------------------------------| |"It was interesting to read some synthesis benchmarking results on | |comp.lang.vhdl last week. I feel it's high time that EDA vendors drop| |the anti-benchmarking clauses from their license agreements: | | | |[..]" | |---------------------------------------------------------------------| Who could feel confident about products which are not subjected to as much scrutiny as benchmarks from the Standard Performance Evaluation Corporation? From newsfish@newsfish Tue Aug 9 07:53:14 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.mixmin.net!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 01 May 2011 23:49:25 -0500 From: Harrell31Ola Subject: Re: [Help request] VHDL to Graphics Newsgroups: comp.lang.vhdl UserIpAddress: 91.201.66.6 InternalId: f3c1f461-70b2-4d76-9c0f-4d3258bcc8ea References: <4b5df3d7$0$702$5fc30a8@news.tiscali.it> Message-ID: Date: Sun, 01 May 2011 23:49:25 -0500 Lines: 3 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-0QdIq1ESYOPm48jk7dxsTHwVhrX1KlGoHtcglQgUjXpzvmU3CZd/frzXXnOSzHVikltZ0ZwDjQQ+sq7!7KytpzZicF0QFfxHIQakyZ2p4MwZv0ZzmUYo8TLq3BfPdKQHCwiq2+RJkN5wEmZ33XhA09aZcA== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1002 Xref: feeder.eternal-september.org comp.lang.vhdl:4985 freelance writer From newsfish@newsfish Tue Aug 9 07:53:15 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: [Help request] VHDL to Graphics Date: Sun, 01 May 2011 23:20:31 -0700 Lines: 9 Message-ID: <9270p3F7i0U1@mid.individual.net> References: <4b5df3d7$0$702$5fc30a8@news.tiscali.it> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 3qnJUND+r7ALPFEc+eJkUw+cwD204hvPn99El8kAc7Z/2dRj0L Cancel-Lock: sha1:Ik0SlgjmwjaTNKF8INxDxMgupVQ= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4986 On 5/1/2011 9:49 PM, Harrell31Ola wrote: > > [Help request] VHDL to Graphics > freelance writer [Answer] Quartus Web Editon, RTL Viewer freelance reader From newsfish@newsfish Tue Aug 9 07:53:15 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a10g2000vbz.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 02:41:23 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: NNTP-Posting-Host: 62.121.39.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1304588483 29695 127.0.0.1 (5 May 2011 09:41:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 09:41:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a10g2000vbz.googlegroups.com; posting-host=62.121.39.162; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4987 Hi, I am a little surprised that the following code refuses to synthesize (at least with Quartus and Synopsys (Lattice's)): ********************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity real_synth is port( a_in: in unsigned(15 downto 0); b_out: out unsigned(15 downto 0) ); end; architecture synth of real_synth is begin process(a_in) variable r: real; begin r := real(to_integer(a_in)); r := r*1.2; if r<0.0 then r := 0.0; elsif r>65535.0 then r := 65535.0; end if; b_out <= to_unsigned(integer(r),16); end process; end; **************************** Ok, I do understand that real values are a problem when they need to be stored, or transported (with signals/ports). But in this case the mapping of a_in => b_out can be evaluated by brute force (by going through all input states, and running the code inside the process for every possible input combination and noting the output values). Upto today I had thought that all synthesizers would fallback to the brute force method if intelligent algorithm generator fails. It seems that I had mistrusted them, though. Any ideas why the synthesizers DO NOT have this brute-force fallback method? - Topi From newsfish@newsfish Tue Aug 9 07:53:15 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l6g2000vbn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 03:26:29 -0700 (PDT) Organization: http://groups.google.com Lines: 62 Message-ID: References: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304591190 2246 127.0.0.1 (5 May 2011 10:26:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 10:26:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000vbn.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4988 On May 5, 10:41=A0am, Topi wrote: > Hi, > > I am a little surprised that the following code refuses to synthesize > (at least with Quartus and Synopsys (Lattice's)): > > ********************** > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity real_synth is > =A0 =A0 =A0 =A0 port( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 a_in: in unsigned(15 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 b_out: out unsigned(15 downto 0) > =A0 =A0 =A0 =A0 ); > end; > > architecture synth of real_synth is > begin > =A0 =A0 =A0 =A0 process(a_in) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable r: real; > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D real(to_integer(a_in)); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D r*1.2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if r<0.0 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D 0.0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif r>65535.0 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D 65535.0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 b_out <=3D to_unsigned(integer(r),16); > =A0 =A0 =A0 =A0 end process; > end; > > **************************** > > Ok, I do understand that real values are a problem when they need to > be stored, or transported (with signals/ports). > > But in this case the mapping of a_in =3D> b_out can be evaluated by > brute force (by going through all input states, and running the code > inside the process for every possible input combination and noting the > output values). > > Upto today I had thought that all synthesizers would fallback to the > brute force method if intelligent algorithm generator fails. It seems > that I had mistrusted them, though. > > Any ideas why the synthesizers DO NOT have this brute-force fallback > method? > > - Topi Real types are not appropriate for synthesis in any shape or form. There is no definition of how they exist in binary (because it is not an array type) and so cannot be synthesised into gates and register. You will have to convert your real values to fixed point. Try looking at the new IEEE fixed packages. 93 compatible versions of the library can be found here: http://www.vhdl.org/fphdl/ From newsfish@newsfish Tue Aug 9 07:53:15 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 10:38:52 +0000 (UTC) Organization: A noiseless patient Spider Lines: 32 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 5 May 2011 10:38:52 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="GYkF6yd5NlcG1TQKOHSQHQ"; logging-data="30729"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jLWz58+4wdFXOLLGciawcmI0N+9UOKDc=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:a6BmTo+VOS6U8YqnLFiJkiJaF+s= Xref: feeder.eternal-september.org comp.lang.vhdl:4989 On Thu, 05 May 2011 02:41:23 -0700, Topi wrote: > Hi, > > I am a little surprised that the following code refuses to synthesize > (at least with Quartus and Synopsys (Lattice's)): > > > process(a_in) > variable r: real; > begin > r := real(to_integer(a_in)); > r := r*1.2; > if r<0.0 then > r := 0.0; > elsif r>65535.0 then > r := 65535.0; > end if; > b_out <= to_unsigned(integer(r),16); > end process; Rearrange the computation such that all the real arithmetic operates on constants, to return a (constant) integer or unsigned result, and synthesis tools should behave correctly. For this simple example you can afford to test every interesting input value in simulation against the "real" version to prove that no rounding errors have occurred; in general that may not be feasible. Alternatively, explore the fixed point libraries as Tricky suggested. - Brian From newsfish@newsfish Tue Aug 9 07:53:15 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Synthesizing code with intermediate real values Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.133 (House of Butterflies) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 05 May 2011 12:18:34 GMT Lines: 75 Message-ID: <4dc2959a$0$11101$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 59c6cdd3.news.astraweb.com X-Trace: DXC=o9SB[7A6MITLZ1S`DSi2W0=_RHW7EWfMMB7T1k`HXR7B7X] Xref: feeder.eternal-september.org comp.lang.vhdl:4990 On Thu, 05 May 2011 03:26:29 -0700, Tricky wrote: > On May 5, 10:41 am, Topi wrote: >> Hi, >> >> I am a little surprised that the following code refuses to synthesize >> (at least with Quartus and Synopsys (Lattice's)): >> >> ********************** >> >> library ieee; >> use ieee.std_logic_1164.all; >> use ieee.numeric_std.all; >> >> entity real_synth is >>         port( >>                 a_in: in unsigned(15 downto 0); >>                 b_out: out unsigned(15 downto 0) >>         ); >> end; >> >> architecture synth of real_synth is >> begin >>         process(a_in) >>                 variable r: real; >>         begin >>                 r := real(to_integer(a_in)); >>                 r := r*1.2; >>                 if r<0.0 then >>                         r := 0.0; >>                 elsif r>65535.0 then >>                         r := 65535.0; >>                 end if; >>                 b_out <= to_unsigned(integer(r),16); >>         end process; >> end; >> >> **************************** >> >> Ok, I do understand that real values are a problem when they need to be >> stored, or transported (with signals/ports). >> >> But in this case the mapping of a_in => b_out can be evaluated by brute >> force (by going through all input states, and running the code inside >> the process for every possible input combination and noting the output >> values). >> >> Upto today I had thought that all synthesizers would fallback to the >> brute force method if intelligent algorithm generator fails. It seems >> that I had mistrusted them, though. >> >> Any ideas why the synthesizers DO NOT have this brute-force fallback >> method? >> >> - Topi > > Real types are not appropriate for synthesis in any shape or form. It's quite ok to use real types in synthesisable VHDL for code that only gets executed at compile or elaboration time. For example, you could write a function that uses real types internally, which is used to produce a (non real, e.g. unsigned) value which is assigned to a constant. generic myreal : real = 0.0; ... constant foo : natural := myfuncthatusesreals(myreal); This has had major tool support for a long time. Regards, Allan From newsfish@newsfish Tue Aug 9 07:53:15 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!e21g2000vbz.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: boldport Date: Thu, 5 May 2011 10:58:56 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <4206215d-031e-46e0-9e11-c50159662586@e21g2000vbz.googlegroups.com> NNTP-Posting-Host: 86.6.9.112 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1304618336 20322 127.0.0.1 (5 May 2011 17:58:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 17:58:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000vbz.googlegroups.com; posting-host=86.6.9.112; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:15421 comp.lang.vhdl:4991 comp.lang.verilog:3061 In a bit of a self promotional move, though probably pretty relevant to this group, I'd like to mention http://www.boldport.com which I released on Monday, and https://www.boldport.com/docs/fpgaproj for easing the migration from GUI to command-line use of FPGA tools, and more effective project/build management. The project is at an early stage, and more features will be added with time. Praise, constructive feedback, and well-mannered bashing are welcome, of course... be as honest as this group knows how to be (feel free to email me privately as well). Finally, I'm looking for early adopter projects, and offer my help with the setup. Thanks for your attention, saar. From newsfish@newsfish Tue Aug 9 07:53:16 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!24g2000yqk.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 13:12:40 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <9ec99126-920e-4026-9a4d-c07f88ff71b9@24g2000yqk.googlegroups.com> References: <4dc2959a$0$11101$c3e8da3@news.astraweb.com> NNTP-Posting-Host: 86.60.209.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1304626360 8065 127.0.0.1 (5 May 2011 20:12:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 20:12:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 24g2000yqk.googlegroups.com; posting-host=86.60.209.165; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110422 Ubuntu/10.10 (maverick) Firefox/3.6.17,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4992 Thanks for the suggestions. My point of interest is towards understanding synthesizing process, not circumventing the problem. As Brian pointed out, in simple cases it _could be feasible_ to crawl all possible combinations to get a truth table a_in =to> b_out. But in more complex cases the result might be too complex to fit in to the target (or to optimize the truth table). Tricky: The synthesizer does not need to implement any real-valued signals in the synthesized netlist. Actually there aren't any in the source code either (the variable is not persistent, so it does not map to a register). The synthesized result could be, e.g. a 64kx16 bit rom memory. Anyway I still don't know/understand why the synthesizer companies have opted out from supporting "discrete input =to> discrete output mapping, even if there are non-trivial intermediate phased". I could easily make a vhdl to vhdl preprosessor to crawl through all possible input combinations and to produce truth table from input to output. Wonder what the synthesizers would think, if e.g. I would replace 8 x 8 multiplier by 65536 entry table. Would it utilize DSP-block (in FPGA) to implement the function? - Topi From newsfish@newsfish Tue Aug 9 07:53:16 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!b35g2000yqn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 13:53:03 -0700 (PDT) Organization: http://groups.google.com Lines: 66 Message-ID: References: <4dc2959a$0$11101$c3e8da3@news.astraweb.com> <9ec99126-920e-4026-9a4d-c07f88ff71b9@24g2000yqk.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304628783 32714 127.0.0.1 (5 May 2011 20:53:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 20:53:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b35g2000yqn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4993 On May 5, 4:12=A0pm, Topi wrote: > Thanks for the suggestions. > > As Brian pointed out, in simple cases it _could be feasible_ to crawl > all possible combinations to get a truth table a_in =3Dto> b_out. That's not what Brian said at all. He said you can use reals to compute constants that, in the end, vanish in the resulting function output. > But in more complex cases the result might be too complex to fit in to > the target (or to optimize the truth table). > Such as what? Your example is not such an example if that's what you had in mind. For starters, the comparison with 0 is not needed, the input is unsigned, therefore could never be less than 0. Second, rather than taking the input and multiplying by 1.2 and comparing that to 65535.0, one could instead compare r with the computed constant 65535.0 / 1.2 converted to an unsigned. That is what Brian general case suggestion would be for your specific example by the way. There may indeed be more complex examples as you stated, but give an example of such that cannot be trivially changed to be equivalent as is the case with your original posting. > Anyway I still don't know/understand why the synthesizer companies > have opted out from supporting "discrete input =3Dto> discrete output > mapping, even if there are non-trivial intermediate phased". > Most likely because there is little market demand from users. Even real constants didn't use to be supported. Now (and for the past several years) they are. Given a compelling reason the synthesis vendors do support user requests although usually not nearly as fast as some might like. If you can come up with a compelling use case then you should submit it to all the vendors as a feature suggestion. However, you would have to do better than your example where the only motivation you could provide is that you don't like the looks of "65535.0 / 1.2" as compared to "r * 1.2". > I could easily make a vhdl to vhdl preprosessor to crawl through all > possible input combinations and to produce truth table from input to > output. > OK. And then compare what you get with that approach versus computing the constant as suggested here. The metrics of importance to most people would be amount of logic resources used and performance. If your approach is an improvement you're on to something. If not, maybe the synthesis vendors aren't doing such a bad job after all. > Wonder what the synthesizers would think, if e.g. I would replace 8 x > 8 multiplier by 65536 entry table. Would it utilize DSP-block (in > FPGA) to implement the function? > I would find it highly unlikely that any synthesis tool would take a truth table specification in the source code and infer a multiply operation from it and then use a DSP block to implement the multiply...not to say that it couldn't, I would just be very surprised if it did. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:16 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 06 May 2011 01:14:11 -0500 Subject: Re: Very fast PWM in Cyclone III FPGA Date: Fri, 06 May 2011 00:14:10 -0600 From: "David M. Palmer" Newsgroups: comp.lang.vhdl Message-ID: <060520110014104755%dmpalmer@email.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 8bit User-Agent: Thoth/1.8.4 (Carbon/OS X) Lines: 42 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.167.133.208 X-Trace: sv3-aQLiw90ow/R+0pFmK2MSnVztRJzagCMeLmEhuuB9RgmfsiNjUX7uxlH7MX7YG9wMhp24Yh8azZyws9a!DWzkqIz+IFz7GR3QK0yoYWGgVE3VPQwF0OR/BLoRZeCd8yGlUWh3XymoER/SgKqKnRmuJl0Ro5al!E6F95Ohle8OUN3heFEL+tZRj X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2358 Xref: feeder.eternal-september.org comp.lang.vhdl:4994 In article , Steffen Koepf wrote: > Hello, > > i need a very fast PWM in a Cyclone III FPGA. > If necessary, a Cyclone IV will do it too. > > I need a 80 KHz PWM for direct Gate Control in a Switchmode Power Supply. > > At the moment the Cyclone III is running at 400 MHz, which gives at 80 KHz > 5000 Steps. I made it to be able to use the falling edge in my PWM- > Comparator, too, so i have now 10000 Steps at 80 KHz. > > But the resolution is still not enough, i would like to have more steps. > > Using a -6 speed grade Cyclone III would allow 600 MHz, which gives around > 15000 Steps. > > Does one know a way to get even more? If you need a value of e.g. 3128.357/5000 out of your PWM, then make your pulse width either 3129 (35.7% of the time) or 3128 (64.3% of the time). If necessary for your application, apply randomness cleverly enough that you don't get significant subharmonics (undertones) of the 80 kHz. > Is there a way to use the SERDES LVDS to get a fast PWM? > > Is it possible to use the PLL to generate higher frequencies and use them > for example by ANDing them for 4 sub-steps (two more bits)? > > > Thanks in advance, > > Steffen > -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com) From newsfish@newsfish Tue Aug 9 07:53:16 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n10g2000yqf.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: Re: Very fast PWM in Cyclone III FPGA Date: Fri, 6 May 2011 00:25:30 -0700 (PDT) Organization: http://groups.google.com Lines: 130 Message-ID: <62d02e14-dbcb-42c4-ade8-7df6988f912f@n10g2000yqf.googlegroups.com> References: NNTP-Posting-Host: 62.121.39.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304666730 11514 127.0.0.1 (6 May 2011 07:25:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 6 May 2011 07:25:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n10g2000yqf.googlegroups.com; posting-host=62.121.39.162; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4995 On Apr 28, 9:52=A0pm, Steffen Koepf wrote: > I need a 80 KHz PWM for direct Gate Control in a Switchmode Power Supply. > > At the moment the Cyclone III is running at 400 MHz, which gives at 80 KH= z > 5000 Steps. I made it to be able to use the falling edge in my PWM- > Comparator, too, so i have now 10000 Steps at 80 KHz. Here is an example of PWM generator with sub-cycle (average) accuracy: input_max is the resolution of pwm you want. count_num defines the pwm frequency. Does it fit to your needs? - Topi ******** library ieee; use ieee.std_logic_1164.all; entity pwm_gen_fast is generic( input_max: integer :=3D 1e6; -- PWM input range max value. count_num: integer :=3D 100e6/80e3 -- number of clk cycles of one PWM cycle. ); port( clk_in: in std_logic; pwm_in: in integer range 0 to input_max; pwm_out: out std_logic ); end; architecture synth of pwm_gen_fast is constant rat_val: integer :=3D (input_max)/(count_num); signal store: integer range 0 to input_max :=3D 0; signal counter: integer range 0 to count_num-1 :=3D 0; signal pwm: std_logic; begin process(clk_in) variable new_store: integer range 0 to input_max+rat_val :=3D 0; variable rst_counter: boolean; variable new_pwm: std_logic; variable new_counter : integer; begin if rising_edge(clk_in) then rst_counter :=3D false; new_pwm :=3D pwm; new_store :=3D store; if new_store < pwm_in then new_store :=3D new_store + rat_val; end if; if counter =3D count_num-1 then new_counter :=3D 0; rst_counter :=3D true; else new_counter :=3D counter + 1; end if; if rst_counter then new_store :=3D new_store - pwm_in; store <=3D new_store; end if; if new_counter =3D 0 then new_pwm :=3D '1'; end if; if new_store >=3D pwm_in then new_pwm :=3D '0'; end if; pwm <=3D new_pwm; counter <=3D new_counter; store <=3D new_store; end if; end process; pwm_out <=3D pwm; end; library ieee; use ieee.std_logic_1164.all; entity tb_pwm_gen_fast is end; architecture tb of tb_pwm_gen_fast is signal clk: std_logic; signal pwm_in: integer range 0 to 100 :=3D 0; signal pwm_out: std_logic; begin DUT: entity work.pwm_gen_fast generic map( input_max =3D> 100, count_num =3D> 10 ) port map( clk_in =3D> clk, pwm_in =3D> pwm_in, pwm_out =3D> pwm_out ); process begin clk <=3D '0'; wait for 500 ns; clk <=3D '1'; wait for 500 ns; end process; process begin pwm_in <=3D 1; wait for 5000 us; pwm_in <=3D 80; wait for 1000 us; pwm_in <=3D 82; wait for 1000 us; pwm_in <=3D 100; wait for 1000 us; pwm_in <=3D 99; wait for 1000 us; assert false report "all done" severity failure; wait; end process; end; ******** From newsfish@newsfish Tue Aug 9 07:53:16 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Fri, 6 May 2011 13:22:14 +0000 (UTC) Organization: A noiseless patient Spider Lines: 57 Message-ID: References: <4dc2959a$0$11101$c3e8da3@news.astraweb.com> <9ec99126-920e-4026-9a4d-c07f88ff71b9@24g2000yqk.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 6 May 2011 13:22:14 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="rXzJ5MDsuKq5UTEB2rLg2g"; logging-data="27745"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX194RSEO5sFRf+bIoB4dszwhe0NLyzgJyuw=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:AR4ZLXyTSpIAt4MN5KQaVSV3Z34= Xref: feeder.eternal-september.org comp.lang.vhdl:4996 On Thu, 05 May 2011 13:53:03 -0700, KJ wrote: > On May 5, 4:12 pm, Topi wrote: >> Thanks for the suggestions. >> >> As Brian pointed out, in simple cases it _could be feasible_ to crawl >> all possible combinations to get a truth table a_in =to> b_out. > > That's not what Brian said at all. He said you can use reals to compute > constants that, in the end, vanish in the resulting function output. Thanks, that was it. > Such as what? Your example is not such an example if that's what you > had in mind. For starters, the comparison with 0 is not needed, the > input is unsigned, therefore could never be less than 0. Second, rather > than taking the input and multiplying by 1.2 and comparing that to > 65535.0, one could instead compare r with the computed constant 65535.0 > / 1.2 converted to an unsigned. That is what Brian general case > suggestion would be for your specific example by the way. Indeed. But to expand on this, the original code would output r * 1.2 in cases where saturation did not occur, so at least an integer constant multiplication is necessary. However it should be a multiplication of the form : r := a_in * to_unsigned(1.2 * 65536) / 65536; where the division is trivial. Now if careful attention is paid to issues of rounding vs. truncation, this will deliver identical results to the original, while eliminating run-time floating point arithmetic; otherwise it may deliver results differing by +/-1 LSB. To be explicit about this, you may need to round the coefficient r := a_in * to_unsigned(1.2 * 65536 + 0.5) / 65536; or the r := (a_in * to_unsigned(1.2 * 65536) + 0.5)/ 65536; or both to match the integer(r) function in the original version. THIS is where I recommend exhaustive testing; comparing the modified process vs. the original, IN SIMULATION, for every input value. Assert the outputs are equal; regard any difference as a failure. This is the brute force approach, but for only 2**16 input values it is the easiest. I have used it up to 2**24 inputs without too much pain. Alternatively, you may find a mathematical analysis to reduce the number of test cases required (otherwise, for 2 independent 32-bit inputs, 2**64 testcases would be required!) Or you may need to justify (and document!) that a 1 LSB error is permissible in your use case; e.g. because the input data has a noise component much grater than this level. - Brian From newsfish@newsfish Tue Aug 9 07:53:16 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!q30g2000vbs.googlegroups.com!not-for-mail From: Mark Christiaens Newsgroups: comp.lang.vhdl Subject: Accessing field of record aggregate Followup-To: comp.lang.vhdl Date: Wed, 11 May 2011 02:46:16 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305107177 22970 127.0.0.1 (11 May 2011 09:46:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 May 2011 09:46:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q30g2000vbs.googlegroups.com; posting-host=195.144.71.15; posting-account=VvmngAoAAACfNKqnkCfwI3NfVc3Fvw96 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.65 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4997 I was wondering what is going on in this test case: --------------------------------------------- entity top is end entity top; architecture RTL of top is type rtype is record i1 : integer; i2 : integer; end record; begin process is variable i : rtype; begin i := rtype'(0, 0); -- OK assert i.i1 = 0; -- OK assert rtype'(0, 0).i1 = 0; -- Not OK wait; end process; end architecture RTL; --------------------------------------------- As you can see, I've defined a record type "rtype". Using a record aggregate to initialize a record variable is fine (according to ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of that variable is fine but building a complete expression that uses the record aggregate is not fine. ModelSim complains: # -- Loading package standard # -- Compiling entity top # -- Compiling architecture rtl of top # ** Error: top.vhd(18): Qualified expression type mark rtype is not type std.standard.boolean. # ** Error: top.vhd(18): near ".": expecting ';' # ** Error: top.vhd(22): VHDL Compiler exiting Why exactly is this not allowed? --- Mark Christiaens Discover the Future of VHDL Design www.sigasi.com From newsfish@newsfish Tue Aug 9 07:53:17 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!194.109.133.85.MISMATCH!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4dcabb8a$0$41102$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Accessing field of record aggregate Newsgroups: comp.lang.vhdl Date: Wed, 11 May 2011 18:38:34 +0200 References: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 69 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1305131915 news.xs4all.nl 41102 puiterl/[::ffff:195.242.97.150]:34114 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4998 Mark Christiaens wrote: > I was wondering what is going on in this test case: > --------------------------------------------- > entity top is > end entity top; > > architecture RTL of top is > type rtype is record > i1 : integer; > i2 : integer; > end record; > > begin > process is > variable i : rtype; > begin > i := rtype'(0, 0); -- OK There is no ambiguity, so a qualifier is not needed. This works just as well: i := (0, 0); Or: i := (i1 => 0, i2 => 0); Even this is OK: i := (others => 0); > assert i.i1 = 0; -- OK > assert rtype'(0, 0).i1 = 0; -- Not OK > wait; > end process; > > end architecture RTL; > --------------------------------------------- > > As you can see, I've defined a record type "rtype". Using a record > aggregate to initialize a record variable is fine (according to > ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of > that variable is fine but building a complete expression that uses the > record aggregate is not fine. ModelSim complains: > > # -- Loading package standard > # -- Compiling entity top > # -- Compiling architecture rtl of top > # ** Error: top.vhd(18): Qualified expression type mark rtype is not > type std.standard.boolean. > # ** Error: top.vhd(18): near ".": expecting ';' > # ** Error: top.vhd(22): VHDL Compiler exiting > > Why exactly is this not allowed? I don't know exactly why. But I also don't know why you would want to use that construct that way. Taking a record element works with variables, constants and signals. It seems that you want to use a constant built with literals. Using a real constant avoids the whole problem constant c : rtype := (0, 0); ... assert c.i1 = 0; -- OK -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:17 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 11 May 2011 17:29:25 -0500 Date: Wed, 11 May 2011 23:29:24 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Accessing field of record aggregate References: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> In-Reply-To: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 75 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-sZsWpKVmTNZGrkBTS45k2nBEd3qibI/VEF1kACtCppTJ8vh6KTEuFyF0e+wz6wN+zat9Kd9RauKsHvx!LHciixC7xWfNTH6edI10VNVdYBYrarfArauKxQBft4f43nkhRkdYJxV80marCUQUTTV6/KfTDUVG!ukQM9rQXFBF9gQ0QKNR7eloDvc8= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3319 Xref: feeder.eternal-september.org comp.lang.vhdl:4999 On 11/05/11 10:46, Mark Christiaens wrote: > I was wondering what is going on in this test case: > --------------------------------------------- > entity top is > end entity top; > > architecture RTL of top is > type rtype is record > i1 : integer; > i2 : integer; > end record; > > begin > process is > variable i : rtype; > begin > i := rtype'(0, 0); -- OK > assert i.i1 = 0; -- OK > assert rtype'(0, 0).i1 = 0; -- Not OK > wait; > end process; > > end architecture RTL; > --------------------------------------------- > > As you can see, I've defined a record type "rtype". Using a record > aggregate to initialize a record variable is fine (according to > ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of > that variable is fine but building a complete expression that uses the > record aggregate is not fine. ModelSim complains: > > # -- Loading package standard > # -- Compiling entity top > # -- Compiling architecture rtl of top > # ** Error: top.vhd(18): Qualified expression type mark rtype is not > type std.standard.boolean. > # ** Error: top.vhd(18): near ".": expecting ';' > # ** Error: top.vhd(22): VHDL Compiler exiting > > Why exactly is this not allowed? In section 6.1 the VHDL standard defines a name as simple_name | operator_symbol | selected_name | indexed_name | slice_name | attribute_name It then defines the prefix of a selected name as prefix ::= name | funtion_call A qualified expression is not a name so the selected_name you've attempted to use is also not a name. It doesn't seem surprising to me as you haven't created an object with a name, just a literal. regards Alan P.S. Cadence ncvhdl helpfully says assert rtype'(0,0).i1 = 0; | ncvhdl_p: *E,QLXNOP (test.vhd,18|22): a qualified expression is not a legal name prefix [6.1] [7.3.4]. errors: 1, warnings: 0 irun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting. -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:17 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h36g2000pro.googlegroups.com!not-for-mail From: Mark Christiaens Newsgroups: comp.lang.vhdl Subject: Re: Accessing field of record aggregate Date: Thu, 12 May 2011 01:00:22 -0700 (PDT) Organization: http://groups.google.com Lines: 88 Message-ID: <6155a8b6-97eb-4e3a-afc7-764ecc89e358@h36g2000pro.googlegroups.com> References: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1305187222 20924 127.0.0.1 (12 May 2011 08:00:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 May 2011 08:00:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h36g2000pro.googlegroups.com; posting-host=195.144.71.15; posting-account=VvmngAoAAACfNKqnkCfwI3NfVc3Fvw96 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.65 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5000 On May 12, 12:29=A0am, Alan Fitch wrote: > On 11/05/11 10:46, Mark Christiaens wrote: > > > > > > > > > > > I was wondering what is going on in this test case: > > --------------------------------------------- > > entity top is > > end entity top; > > > architecture RTL of top is > > =A0 =A0 type rtype is record > > =A0 =A0 =A0 =A0 i1 : integer; > > =A0 =A0 =A0 =A0 i2 : integer; > > =A0 =A0 end record; > > > begin > > =A0 =A0 process is > > =A0 =A0 =A0 =A0 variable i : rtype; > > =A0 =A0 begin > > =A0 =A0 =A0 =A0 i :=3D rtype'(0, 0); -- OK > > =A0 =A0 =A0 =A0 assert i.i1 =3D 0; -- OK > > =A0 =A0 =A0 =A0 assert rtype'(0, 0).i1 =3D 0; -- Not OK > > =A0 =A0 =A0 =A0 wait; > > =A0 =A0 end process; > > > end architecture RTL; > > --------------------------------------------- > > > As you can see, I've defined a record type "rtype". =A0Using a record > > aggregate to initialize a record variable is fine (according to > > ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of > > that variable is fine but building a complete expression that uses the > > record aggregate is not fine. =A0ModelSim complains: > > > # -- Loading package standard > > # -- Compiling entity top > > # -- Compiling architecture rtl of top > > # ** Error: top.vhd(18): Qualified expression type mark rtype is not > > type std.standard.boolean. > > # ** Error: top.vhd(18): near ".": expecting ';' > > # ** Error: top.vhd(22): VHDL Compiler exiting > > > Why exactly is this not allowed? > > In section 6.1 the VHDL standard defines a name as > > =A0 simple_name | operator_symbol | selected_name | indexed_name | > slice_name | attribute_name > > It then defines the prefix of a selected name as > > =A0 prefix ::=3D name | funtion_call > > A qualified expression is not a name so the selected_name you've > attempted to use is also not a name. > > It doesn't seem surprising to me as you haven't created an object with a > name, just a literal. > > regards > Alan > > P.S. Cadence ncvhdl helpfully says > > =A0assert rtype'(0,0).i1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | > ncvhdl_p: *E,QLXNOP (test.vhd,18|22): a qualified expression is not a > legal name prefix [6.1] [7.3.4]. > =A0 =A0 =A0 =A0 errors: 1, warnings: 0 > irun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting. > > -- > Alan Fitch I was not having a particular use case in mind. I was just curious how "orthogonal" the VHDL grammar exactly is with regards to such expressions. My conclusion is that it's not very orthogonal ;) Anyway, thank you for clarifying. Mark From newsfish@newsfish Tue Aug 9 07:53:17 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!k17g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Accessing field of record aggregate Date: Thu, 12 May 2011 09:17:38 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <86170afb-c209-44ba-94dc-20a8521314d8@k17g2000vbn.googlegroups.com> References: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> <6155a8b6-97eb-4e3a-afc7-764ecc89e358@h36g2000pro.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1305217059 10393 127.0.0.1 (12 May 2011 16:17:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 May 2011 16:17:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k17g2000vbn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5001 On May 12, 4:00=A0am, Mark Christiaens wrote: > I was just curious > how "orthogonal" the VHDL grammar exactly is with regards to such > expressions. =A0My conclusion is that it's not very orthogonal ;) > My conclusion is that your usage is not a measure of orthogonality. KJ From newsfish@newsfish Tue Aug 9 07:53:17 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4dcd1f68$0$81484$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Visibility rules Newsgroups: comp.lang.vhdl Date: Fri, 13 May 2011 14:09:12 +0200 Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 98 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1305288552 news.xs4all.nl 81484 puiterl/[::ffff:195.242.97.150]:42319 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5002 I am curious how simulators deal with code as shown below when analyzing it: PACKAGE pkg IS FUNCTION min ( a : integer; b : integer ) RETURN integer; END PACKAGE pkg; PACKAGE BODY pkg IS FUNCTION min ( a : integer; b : integer ) RETURN integer IS BEGIN IF a < b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION min; END PACKAGE BODY pkg; ENTITY ent IS END ENTITY ent; USE work.pkg.ALL; ARCHITECTURE arch OF ent IS BEGIN p: PROCESS IS VARIABLE v : integer; BEGIN v := min(123, 456); WAIT; END PROCESS p; END ARCHITECTURE arch; I use ModelSim. Up to version 10.0 (including 10.0beta1) this used to work fine. Version 10.0a (and I suppose 10.0 as well) now complains: ** Error: vhdl/function_min.vhd(34): (vcom-1078) Identifier "min" is not directly visible. Potentially visible declarations are: std.STANDARD.min (physical unit) work.pkg.min (function) So clearly there is a collision now with the physical unit "min" from type TIME. Technote MG539708 by Mentor explains that the above behaviour is LRM compliant. The fact that this used to work in earlier versions is an unlucky event, based on the order in which declarations were found (USE clauses). The clause "USE std.standard.all" always is present implicitly. So, could somebody please analyze the above code in a different simulator to see if it is accepted or not? Additionally, I wonder why a function name "DEL" (instead of "min) *is* accepted. DEL is one of the enumeration literals of type CHARACTER. To add to the fun: this is not accepted by any version of ModelSim: PACKAGE pkg IS COMPONENT del IS END COMPONENT del; END PACKAGE pkg; ENTITY ent IS END ENTITY ent; USE work.pkg.ALL; ARCHITECTURE arch OF ent IS BEGIN del_i: del; END ARCHITECTURE arch; Ah, wait a minute: the clarification of error message 1078 explains why del can be used as function and not as a component (both declared in a package): vcom Message # 1078: The name is ambiguous according to the visibility rules. IEEE Std 1076-1993, 10.4 Use clauses, line 234: Potentially visible declarations that have the same designator are not made directly visible unless each of them is either an enumeration literal specification or the declaration of a subprogram (either by a subprogram declaration or by an implicit declaration). Still, I am curious if my code with function min fails in other simulators. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:17 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!usenet.pasdenom.info!selfless.tophat.at!news.glorb.com!postnews.google.com!t16g2000vbi.googlegroups.com!not-for-mail From: Philippe Newsgroups: comp.lang.vhdl,comp.emacs Subject: Emacs VHDL mode with CTAGS / etags Date: Fri, 13 May 2011 07:32:52 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <0520ced9-8558-4493-925f-8fc6dceb2bb9@t16g2000vbi.googlegroups.com> NNTP-Posting-Host: 83.134.177.166 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305297172 26752 127.0.0.1 (13 May 2011 14:32:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 May 2011 14:32:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t16g2000vbi.googlegroups.com; posting-host=83.134.177.166; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.68 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5003 comp.emacs:3846 Is there anybody out there who still uses CTAGS (or rather: etags) for VHDL? I was surprised to see how crude it really is. No scoping, the regular expressions get confused easily, problems with name clashes... http://www.sigasi.com/content/navigating-through-vhdl-project-emacs-vs-sigasi have a nice weekend! -- Philippe Sigasi From newsfish@newsfish Tue Aug 9 07:53:18 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4dcd5850$0$81485$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Emacs VHDL mode with CTAGS / etags Newsgroups: comp.lang.vhdl,comp.emacs Followup-To: comp.lang.vhdl Date: Fri, 13 May 2011 18:12:00 +0200 References: <0520ced9-8558-4493-925f-8fc6dceb2bb9@t16g2000vbi.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 20 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1305303120 news.xs4all.nl 81485 puiterl/[::ffff:195.242.97.150]:59599 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5004 comp.emacs:3847 Philippe wrote: > Is there anybody out there who still uses CTAGS (or rather: etags) for > VHDL? Yes, I use vtags in combination with Nedit or Vim. I got vtags from http://tams-www.informatik.uni-hamburg.de/vhdl/tools/vtags/, but it seems not to be accessible from there anymore. > I was surprised to see how crude it really is. No scoping, the > regular expressions get confused easily, problems with name clashes... Still, it is simple to use and adequate in a lot of cases. And it's free. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:18 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!17g2000prr.googlegroups.com!not-for-mail From: -DeeT Newsgroups: comp.lang.vhdl Subject: slice of signed = unsigned? Date: Fri, 13 May 2011 10:43:11 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: NNTP-Posting-Host: 97.65.186.18 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305308592 9383 127.0.0.1 (13 May 2011 17:43:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 May 2011 17:43:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 17g2000prr.googlegroups.com; posting-host=97.65.186.18; posting-account=Khn83QoAAAC4ziDcW7Lr35LufiqQCIcd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.65 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5005 If you take a slice of a signed vector which doesn't include the sign bit, is that slice considered to be signed or unsigned? Here's an illustration: signal v : signed(7 downto 0); alias a is v(3 downto 0); variable i : integer; i := to_integer(a); In the above scenario, what is the range of possible values for 'i'? Is it 0 to 15, or -8 to +7? I ask because a compiler upgrade broke some of my code, by changing this behavior (which admittedly I shouldn't have counted on either way!). Thanks in advance for your thoughts... -DT From newsfish@newsfish Tue Aug 9 07:53:18 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news-transit.tcx.org.uk!feeder.news-service.com!216.196.110.144.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 13 May 2011 19:11:19 -0500 Date: Sat, 14 May 2011 01:11:18 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Visibility rules References: <4dcd1f68$0$81484$e4fe514c@news.xs4all.nl> In-Reply-To: <4dcd1f68$0$81484$e4fe514c@news.xs4all.nl> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 112 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-fgcWI+v58Zi+qncZqrAftPRIHC68eTgGEorC6RBzMA0Ldzi5tCK/p94hmAkknx/b9rAYRibSud9im8Y!EYlfdCo6pJlMW1D2ORBwdsQ7ijX81HqzYgn7bPCpE9fPzVtDoPNaqS+PmXx4BAkPKHT/aaHGKTMX!FyNPMU0WTVucz40u2pv5OV/BJwI= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4441 Xref: feeder.eternal-september.org comp.lang.vhdl:5006 On 13/05/11 13:09, Paul Uiterlinden wrote: > I am curious how simulators deal with code as shown below when analyzing it: > > PACKAGE pkg IS > FUNCTION min > ( > a : integer; > b : integer > ) RETURN integer; > END PACKAGE pkg; > > PACKAGE BODY pkg IS > FUNCTION min > ( > a : integer; > b : integer > ) RETURN integer IS > BEGIN > IF a < b THEN > RETURN a; > ELSE > RETURN b; > END IF; > END FUNCTION min; > END PACKAGE BODY pkg; > > ENTITY ent IS > END ENTITY ent; > > USE work.pkg.ALL; > > ARCHITECTURE arch OF ent IS > BEGIN > p: PROCESS IS > VARIABLE v : integer; > BEGIN > v := min(123, 456); > WAIT; > END PROCESS p; > END ARCHITECTURE arch; > > I use ModelSim. Up to version 10.0 (including 10.0beta1) this used to work > fine. Version 10.0a (and I suppose 10.0 as well) now complains: > > ** Error: vhdl/function_min.vhd(34): (vcom-1078) Identifier "min" is not > directly visible. > Potentially visible declarations are: > std.STANDARD.min (physical unit) > work.pkg.min (function) > > So clearly there is a collision now with the physical unit "min" from type > TIME. > > Technote MG539708 by Mentor explains that the above behaviour is LRM > compliant. The fact that this used to work in earlier versions is an > unlucky event, based on the order in which declarations were found (USE > clauses). The clause "USE std.standard.all" always is present implicitly. > > So, could somebody please analyze the above code in a different simulator to > see if it is accepted or not? > > Additionally, I wonder why a function name "DEL" (instead of "min) *is* > accepted. DEL is one of the enumeration literals of type CHARACTER. > > To add to the fun: this is not accepted by any version of ModelSim: > > PACKAGE pkg IS > COMPONENT del IS > END COMPONENT del; > END PACKAGE pkg; > > ENTITY ent IS > END ENTITY ent; > > USE work.pkg.ALL; > > ARCHITECTURE arch OF ent IS > BEGIN > del_i: del; > END ARCHITECTURE arch; > > Ah, wait a minute: the clarification of error message 1078 explains why del > can be used as function and not as a component (both declared in a > package): > > vcom Message # 1078: > The name is ambiguous according to the visibility rules. > IEEE Std 1076-1993, 10.4 Use clauses, line 234: > Potentially visible declarations that have the same designator are not > made directly visible unless each of them is either an enumeration > literal specification or the declaration of a subprogram (either by a > subprogram declaration or by an implicit declaration). > > Still, I am curious if my code with function min fails in other simulators. > It fails in Cadence: ncvhdl -v93 test.vhd ncvhdl: 10.20-s009: (c) Copyright 1995-2011 Cadence Design Systems, Inc. v := min(123, 456); | ncvhdl_p: *E,IDENRD (test.vhd,34|13): identifier (MIN) is not visible, as it is directly visible via use clauses from more than one design unit. This results in conflict. This object is defined at: STD.STANDARD WORKLIB.PKG Alan -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:18 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d27g2000vbz.googlegroups.com!not-for-mail From: hhanff Newsgroups: comp.lang.vhdl Subject: Re: Emacs VHDL mode with CTAGS / etags Date: Sat, 14 May 2011 03:35:06 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <1321e0c6-e0fc-4dd7-8b6d-2fa8aad433f2@d27g2000vbz.googlegroups.com> References: <0520ced9-8558-4493-925f-8fc6dceb2bb9@t16g2000vbi.googlegroups.com> <4dcd5850$0$81485$e4fe514c@news.xs4all.nl> NNTP-Posting-Host: 88.71.194.8 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305369307 22559 127.0.0.1 (14 May 2011 10:35:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 14 May 2011 10:35:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d27g2000vbz.googlegroups.com; posting-host=88.71.194.8; posting-account=TIldIAoAAAD4kpJj3f9wLt8pW9aqX3pw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5007 On 13 Mai, 18:12, Paul Uiterlinden wrote: > Philippe wrote: > > Is there anybody out there who still uses CTAGS (or rather: etags) for > > VHDL? I just discovered etags a few weeks ago. Currently I'm working on C code and it really eases the analysis of foreign code. Honestly: etags is one of the most important emacs features that I discovered in the last years I would say. I'm already looking forward to the next VHDL project where I can give etags a try... hhanff > > Yes, I use vtags in combination with Nedit or Vim. > > I got vtags fromhttp://tams-www.informatik.uni-hamburg.de/vhdl/tools/vtags/, but it seems > not to be accessible from there anymore. > > > I was surprised to see how crude it really is. No scoping, the > > regular expressions get confused easily, problems with name clashes... > > Still, it is simple to use and adequate in a lot of cases. And it's free. > > -- > Paul Uiterlindenwww.aimvalley.nl > e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:18 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.albasani.net!.POSTED!not-for-mail From: Alexander Bartolich Newsgroups: comp.lang.vhdl Subject: Re: slice of signed = unsigned? Date: Sat, 14 May 2011 20:02:24 +0000 (UTC) Organization: albasani.net Lines: 38 Message-ID: References: X-Trace: news.albasani.net ybB+XxxaAJKpx8Jo4I8lcVx4Bh0UsKDKtGKHuU8JCuoC727SQORP5iKZ/mA3pC87IBsfAZcPynmWZPLtAbGrNA== NNTP-Posting-Date: Sat, 14 May 2011 20:02:24 +0000 (UTC) Injection-Info: news.albasani.net; logging-data="Y8Z20mHuMJSpZiRG8lgdTokkGqbSI4SdIhodbaHG43q1snISa+y9mDWQN/JlPmBJV9SB+So8P8VtTnkSZXFQaIS/MohT1gLTpkCmeAWfEMVgqkkZzxRCDVGNNPTzPGB+"; mail-complaints-to="abuse@albasani.net" User-Agent: slrn/pre1.0.0-16 (Linux) Cancel-Lock: sha1:6R1QD8MH/2FQOpt9Z4i7xC2LVik= Xref: feeder.eternal-september.org comp.lang.vhdl:5008 -DeeT wrote: > If you take a slice of a signed vector which doesn't include the sign > bit, is that slice considered to be signed or unsigned? Here's an > illustration: > > signal v : signed(7 downto 0); > alias a is v(3 downto 0); > variable i : integer; > i := to_integer(a); IEEE Std 1076-1993 (Revision of IEEE Std 1076-1987), page 75 # 4.3.3.1 Object aliases # [...] # The name must be a static name (see 6.1) that denotes an object. The # base type of the name specified in an alias declaration must be the # same as the base type of the type mark in the subtype indication (if # the subtype indication is present); this type must not be a multi- # dimensional array type. When the object denoted by the name is # referenced via the alias defined by the alias declaration, the following # rules apply: # - If the subtype indication is absent or if it is present and denotes # an unconstrained array type: # - If the alias designator denotes a slice of an object, then the # subtype of the object is viewed as if it were of the subtype # specified by the slice # - Otherwise, the object is viewed as if it were of the subtype # specified in the declaration of the object denoted by the name > In the above scenario, what is the range of possible values for 'i'? > Is it 0 to 15, or -8 to +7? To my understanding the alias is equivalent to a declaration like signal a: signed(3 downto 0); -- host -t mx moderators.isc.org From newsfish@newsfish Tue Aug 9 07:53:18 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g12g2000yqd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: slice of signed = unsigned? Date: Sat, 14 May 2011 15:47:56 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <16be61c9-9962-4119-b70b-1a7dcb3f3dd4@g12g2000yqd.googlegroups.com> References: NNTP-Posting-Host: 86.135.20.20 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1305413276 32608 127.0.0.1 (14 May 2011 22:47:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 14 May 2011 22:47:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g12g2000yqd.googlegroups.com; posting-host=86.135.20.20; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5009 On May 13, 6:43=A0pm, -DeeT wrote: > If you take a slice of a signed vector which doesn't include the sign > bit, is that slice considered to be signed or unsigned? =A0Here's an > illustration: > > signal v : signed(7 downto 0); > alias a is v(3 downto 0); > variable i : integer; > i :=3D to_integer(a); > > In the above scenario, what is the range of possible values for 'i'? > Is it 0 to 15, or -8 to +7? > > I ask because a compiler upgrade broke some of my code, by changing > this behavior (which admittedly I shouldn't have counted on either > way!). > > Thanks in advance for your thoughts... > -DT Signed and Unsigned are two completely different types, so slicing them just returns a subtype of the base type. But they are similar types, so you can cast from one type to the other without a conversion function. So you could write this instead: i :=3D to_integer( unsigned(a) ); From newsfish@newsfish Tue Aug 9 07:53:19 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4dd11199$0$81474$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Visibility rules Newsgroups: comp.lang.vhdl Date: Mon, 16 May 2011 13:59:20 +0200 References: <4dcd1f68$0$81484$e4fe514c@news.xs4all.nl> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 30 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1305547161 news.xs4all.nl 81474 puiterl/[::ffff:195.242.97.150]:53205 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5010 Alan Fitch wrote: >> Still, I am curious if my code with function min fails in other >> simulators. >> > > It fails in Cadence: > > ncvhdl -v93 test.vhd > ncvhdl: 10.20-s009: (c) Copyright 1995-2011 Cadence Design Systems, Inc. > v := min(123, 456); > | > ncvhdl_p: *E,IDENRD (test.vhd,34|13): identifier (MIN) is not visible, > as it is directly visible via use clauses from more than one design > unit. This results in conflict. This object is defined at: > STD.STANDARD > WORKLIB.PKG Thanks. That is the correct answer (LRM-wise). If only ModelSim would have given that answer years ago. Now I'm stuck with many many VHDL files that are not LRM compliant. I was happy when I read that in VHDL-2008 the functions minimum and maximum where added, instead of min and max. Those function names where already in use by me. Now I now that min was a bad choice anyway. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:19 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!34g2000pru.googlegroups.com!not-for-mail From: NeedCleverHandle Newsgroups: comp.lang.vhdl,comp.emacs Subject: Re: Emacs VHDL mode with CTAGS / etags Date: Mon, 16 May 2011 11:55:27 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: References: <0520ced9-8558-4493-925f-8fc6dceb2bb9@t16g2000vbi.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1305572127 28728 127.0.0.1 (16 May 2011 18:55:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 16 May 2011 18:55:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 34g2000pru.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5011 comp.emacs:3849 On May 13, 7:32=A0am, Philippe wrote: > Is there anybody out there who still uses CTAGS (or rather: etags) for > VHDL? I was surprised to see how crude it really is. No scoping, the > regular expressions get confused easily, problems with name clashes... > > http://www.sigasi.com/content/navigating-through-vhdl-project-emacs-v... > > have a nice weekend! > > -- > Philippe > Sigasi SPAM? Yup, it's spam. Have a nice day. From newsfish@newsfish Tue Aug 9 07:53:19 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c1g2000yqe.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: Last Call for Papers: The 2011 International Conference on Modeling, Simulation, and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Tue, 17 May 2011 02:30:32 -0700 (PDT) Organization: http://groups.google.com Lines: 271 Message-ID: <754765bb-afd8-44a9-b3c9-8e61b852fd72@c1g2000yqe.googlegroups.com> NNTP-Posting-Host: 174.2.56.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305624632 4559 127.0.0.1 (17 May 2011 09:30:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 17 May 2011 09:30:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c1g2000yqe.googlegroups.com; posting-host=174.2.56.216; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; .NET4.0C; OfficeLiveConnector.1.5; OfficeLivePatch.1.3; FDM; AskTbTRL2/5.7.0.231),gzip(gfe) Xref: feeder.eternal-september.org sci.electronics.design:174308 sci.electronics.cad:8246 sci.electronics.misc:3804 sci.engr.semiconductors:782 comp.lang.vhdl:5012 Dear Colleagues: Please share the announcement below with those who might be interested. Thank you very much. Best regards, Organizing Committee ------------ ==================================================== CALL FOR PAPERS - Deadline: May 23, 2011 MSV'11 The 2011 International Conference on Modeling, Simulation and Visualization Methods July 18-21, 2011, Las Vegas, USA ==================================================== INVITATION: This announcement is ONLY for those who MISSED the opportunity to submit their papers in response to earlier "Call For Papers". You are invited to submit a full paper (about 7 pages) for consideration (see instructions below). Full papers will be considered for both, oral presentation and publication in the conference proceedings as full papers. In addition, after the conference, selected authors will be asked to provide an extended version of their papers for publication consideration in research books to be published and indexed by Springer as well as by various journals. For a few examples of recent books and journal issues based on WORLDCOMP (MSV is an important track of WORLDCOMP, a federated congress in CS and CE), see the links below: (indexed by Medline, Scopus, EMBASE, BIOSIS, Biological Abstracts, CSA, Biological Sciences and Living Resources, Biological Sciences, and others): http://www.springer.com/life+sciences/bioinformatics/book/978-1-4419-7045-9 http://www.springer.com/life+sciences/bioinformatics/book/978-1-4419-5912-6 + a number of journal special issues published by BMC Genomics: http://www.biomedcentral.com . Abstract submissions (one/two-page) will be considered for poster presentations and one/two-page publication in the proceedings. The conference proceedings will be made available in printed book as well as online. INDEXING: MSV proceedings will be indexed by Inspec / IET / The Institute for Engineering and Technology, DBLP / CS Bibliography, and others (in the past, all tracks of the federated congress, WORLDCOMP, in which MSV is part of have also been included in EI Compendex/Elsevier.) NOTE - Important: This announcement is ONLY for those who MISSED the opportunity to submit their papers in response to earlier "Call For Papers". Therefore, authors who have already submitted papers in response to earlier "Call For Papers" should IGNORE this announcement. (Those who have been notified that their papers have been accepted, MUST still follow the instructions that were emailed to them; including meeting the deadlines mentioned in the notifications that were sent to them). IMPORTANT DATES: May 23, 2011: Submission of papers for evaluation June 6, 2011: Notification of acceptance/not-acceptance June 21, 2011: Registration July 18-21, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11) July 30, 2011: Camera-Ready Papers Due for publication in the Final Edition of the proceedings. SCOPE: Topics of interest include, but are not limited to, the following: MSV'11 is composed of a number of tracks (keynote presentations, invited talks, regular research presentations, tutorials, and workshops); all will be held simultaneously, same location and dates: July 18-21, 2011. See below for the topical list: O Simulation languages O Modeling and simulation for computer engineering O Modeling and simulation for education and training O Molecular modeling and simulation O Performance modeling, simulation, and prediction O Modeling, simulation, and emulation of large-scale, volatile environments O Modeling and simulation tools for nanotechnology O Information and scientific visualization O Real-time modeling and simulation O Geometric modeling O Perceptual issues in visualization and modeling O Modeling methodologies O Specification issues for modeling and simulation O Visual interactive simulation and modeling O Visualization tools and systems for simulation and modeling O Java-based modelers O Scalability issues O Numerical methods used in simulation and modeling O Finite and boundary element techniques O Process simulation/modeling O Device simulation/modeling O Circuit simulation/modeling O Performance evaluation and simulation tools O Multi-level modeling O Simulation of machine architectures O Simulation of wireless systems O Simulation and modeling with applications in biotechnology O CAD/CAE/CAM O Prototyping and simulation O Biomedical visualization and applications O Databases and visualization O Interaction paradigms and human factors O Parallel and distributed simulation O Discrete and numeric simulation O Geographic information systems and visualization O Internet, web and security visualization O Virtual reality and simulation O Virtual environments and data visualization O Petri nets and applications O Finite element methods O Soft computing / fuzzy logic O Tools and applications O Object-oriented simulation O Knowledge-based simulation O Emerging technologies and applications USEFUL WEB LINKS: The DBLP list of accepted papers of MSV 2010 appears at: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2010.html The main web site of MSV'11 can be found at: http://www.worldacademyofscience.org/worldcomp11/ws/conferences/msv11 SUBMISSION OF PAPERS: This announcement is ONLY for those who MISSED the opportunity to submit their papers in response to earlier "Call For Papers". Therefore, authors who have already submitted papers in response to earlier "Call For Papers" should IGNORE this announcement. Authors who submit papers in response to this announcement, will have their papers evaluated for publication consideration in the Final Edition of the conference proceedings which will go to press in late August 2011 (the conference would then make the necessary arrangements to ship the printed proceedings/book to such authors). The Final Edition of the conference proceedings will be identical to earlier edition except for a number of sections/chapters appended to the proceedings/book. The Final Edition will be indexed by Inspec / IET / The Institute for Engineering and Technology, DBLP / CS Bibliography, and others (in the past, all tracks of the federated congress, WORLDCOMP, in which MSV is part of, have also been included in EI Compendex/Elsevier.) The proceedings will be published in both, printed book/ISBN form as well as online. Prospective authors are invited to submit their papers by uploading them to the evaluation web site at: http://world-comp.org Submissions must be uploaded by May 23, 2011 and they must be in either MS doc (but not docx) or pdf formats (about 5 to 7 pages - single space, font size of 10 to 12). All reasonable typesetting formats are acceptable (later, the authors of accepted papers will be asked to follow a particular typesetting format to prepare their final papers for publication.) Papers must not have been previously published or currently submitted for publication elsewhere. The first page of the paper should include: title of the paper, name, affiliation, postal address, and email address for each author. The first page should also identify the name of the Contact Author and a maximum of 5 topical keywords that would best represent the content of the paper. Finally, the name of the conference (ie, MSV) should be mentioned. The length of the final/Camera-Ready papers (if accepted) will be limited to 7 (two-column IEEE style) pages. Each paper will be peer-reviewed by two experts in the field for originality, significance, clarity, impact, and soundness. In cases of contradictory recommendations, a member of the conference program committee will be charged to make the final decision (accept/reject); often, this would involve seeking help from additional referees by using a double-blinded review process. In addition, all papers whose authors included a member of the conference program committee will be evaluated using the double-blinded review process. (Essay/ philosophical papers will not be refereed but may be considered for discussion/ panels). 2011 PUBLICITY CHAIR: A. M. G. Solo Fellow of British Computer Society Principal/R&D Engineer, Maverick Technologies America Inc. Intelligent Systems Instructor, Trailblazer Intelligent Systems, Inc. GENERAL INFORMATION: MSV 2011 Conference is being held jointly (same location and dates) with a number of other research conferences (WORLDCOMP). WORLDCOMP is the largest annual gathering of researchers in computer science, computer engineering and applied computing. We anticipate to have 2,100 or more attendees from over 85 countries. WORLDCOMP 2011 will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations. In recent past, keynote/tutorial/panel speakers have included: Prof. David A. Patterson (pioneer/ architecture, U. of California, Berkeley), Dr. K. Eric Drexler (known as Father of Nanotechnology), Prof. John H. Holland (known as Father of Genetic Algorithms; U. of Michigan), Prof. Ian Foster (known as Father of Grid Computing; U. of Chicago & ANL), Prof. Ruzena Bajcsy (pioneer/VR, U. of California, Berkeley), Prof. Barry Vercoe (Founding member of MIT Media Lab, MIT), Dr. Jim Gettys (known as X-man, developer of X Window System, xhost; OLPC), Prof. John Koza (known as Father of Genetic Programming, Stanford U.), Prof. Brian D. Athey (NIH Program Director, U. of Michigan), Prof. Viktor K. Prasanna (pioneer, U. of Southern California), Dr. Jose L. Munoz (NSF Program Director and Consultant), Prof. Jun Liu (Broad Institute of MIT & Harvard U.), Prof. Lotfi A. Zadeh (Father of Fuzzy Logic), Dr. Firouz Naderi (Head, NASA Mars Exploration Program/2000-2005 and Associate Director, Project Formulation & Strategy, Jet Propulsion Lab, CalTech/NASA), and many other distinguished speakers. To get a feeling about the conferences' atmosphere, see the 2010 delegates photos available at: www.pixagogo.com/1676934789 An important mission of WORLDCOMP is "Providing a unique platform for a diverse community of constituents composed of scholars, researchers, developers, educators, and practitioners. The Congress makes concerted effort to reach out to participants affiliated with diverse entities (such as: universities, institutions, corporations, government agencies, and research centers/labs) from all over the world. The congress also attempts to connect participants from institutions that have teaching as their main mission with those who are affiliated with institutions that have research as their main mission. The congress uses a quota system to achieve its institution and geography diversity objectives." One main goal of the congress is to assemble a spectrum of affiliated research conferences, workshops, and symposiums into a coordinated research meeting held in a common place at a common time. This model facilitates communication among researchers in different fields of computer science, computer engineering, and applied computing. The Congress also encourages multi-disciplinary and inter-disciplinary research initiatives; ie, facilitating increased opportunities for cross-fertilization across sub-disciplines. According to "Microsoft Academic Search" (a Microsoft initiative) all tracks of WORLDCOMP are listed as worldwide "Top-ranked Conferences" (based on various metrics but mainly based on the number of citations). You can access "Microsoft Academic Search" to extract citation data for each individual track of worldcomp using the following link: http://academic.research.microsoft.com/ As of March 4, 2011, the papers published in the proceedings have received 14,385 citations which is a higher citation than many reputable journals in computer science. From newsfish@newsfish Tue Aug 9 07:53:19 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r35g2000prj.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: SystemRDL Date: Thu, 19 May 2011 16:12:32 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <61fc1cde-f427-4c6e-8760-e6035f77da0b@r35g2000prj.googlegroups.com> NNTP-Posting-Host: 220.233.20.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305846753 1426 127.0.0.1 (19 May 2011 23:12:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 May 2011 23:12:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r35g2000prj.googlegroups.com; posting-host=220.233.20.160; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5013 I have come across the SystemRDL standard to define a devices register space. Are there any open source tools for generating documentation from systemRDL? I currently use propriety scripts for converting a register definition spreadsheet into code. Before I bash out another scripts to generate a document I thought this could be an opportunity to dabble with this new standard. I don't need all the verification bells and whistles that seem to be offered by commercial tools - just the documentation generator part. From newsfish@newsfish Tue Aug 9 07:53:19 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: VHDL 2008 syntax error Date: Fri, 20 May 2011 22:01:27 -0700 Organization: A noiseless patient Spider Lines: 31 Message-ID: Injection-Date: Sat, 21 May 2011 05:12:35 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="15937"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19txJ8p20f3JYgXodlQtkDSm+j/KRg/lqU=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6090 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:X71Pp/UyJ7qHVEHvtkOWFAebpbs= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5014 I have been learning about VHDL 2008 and wanted to try a simple example of the 2008 enhancements. I created the following test file: entity generic_mux2 is generic (type data_type); port (sel : in bit; a, b : in data_type; z : out data_type ); end entity generic_mux2; architecture rtl of generic_mux2 is begin z <= a when sel = '0' else b; end architecture rtl; I installed ModelSim SE 10.0a. It claims to support a significant subset of the 2008 enhancements. When I try to compile the above file it get: vcom -2008 generic_mux2.vhdl # Model Technology ModelSim SE vcom 10.0a Compiler 2011.02 Feb 20 2011 # -- Loading package STANDARD # -- Compiling entity generic_mux2 # ** Error: generic_mux2.vhdl(2): near "type": expecting IDENTIFIER # C:/modeltech_10.0a/win32/vcom failed. Does ModelSim SE 10.0 not support generic types? Hard to imagine... This is the first thing mentioned in Peter Ashenden's "VHDL-2008: Just the New Stuff". (and I copied the above example right out of the book) Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:19 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sat, 21 May 2011 04:29:43 -0500 Date: Sat, 21 May 2011 10:29:43 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 43 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ItRXQZj1F8Q3quZy4JZXA5UIpzokEhPEr1ZdCCNfGP6mZwzm6ALN6ltA55bZLgPv5IMOCjgGrTapvWq!YRzGO9vXP43IE060YgZrS9pLc0RoKFepu0rcDo+a20m7bqBO/v0EOi+jsbvm1Gwa/F1kMrZvFl+3!VOSGeRmodfJ94EJKI4XXCPUwqw== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2506 Xref: feeder.eternal-september.org comp.lang.vhdl:5015 On 21/05/11 06:01, logic_guy wrote: > I have been learning about VHDL 2008 and wanted to try a simple example > of the 2008 enhancements. I created the following test file: > entity generic_mux2 is > generic (type data_type); > port (sel : in bit; a, b : in data_type; > z : out data_type ); > end entity generic_mux2; > > architecture rtl of generic_mux2 is > begin > z <= a when sel = '0' else b; > end architecture rtl; > > > I installed ModelSim SE 10.0a. It claims to support a significant > subset of the 2008 enhancements. When I try to compile the above file > it get: > vcom -2008 generic_mux2.vhdl > # Model Technology ModelSim SE vcom 10.0a Compiler 2011.02 Feb 20 2011 > # -- Loading package STANDARD > # -- Compiling entity generic_mux2 > # ** Error: generic_mux2.vhdl(2): near "type": expecting IDENTIFIER > # C:/modeltech_10.0a/win32/vcom failed. > > Does ModelSim SE 10.0 not support generic types? Hard to imagine... > This is the first thing mentioned in Peter Ashenden's "VHDL-2008: Just > the New Stuff". (and I copied the above example right out of the book) > The VHDL 2008 support is documented under Help > Technotes > vhdl2008 You might also be interested in my colleague John Aynsley's video: http://www.doulos.com/knowhow/video_gallery/#anchor0 regards Alan -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:20 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error Date: Sat, 21 May 2011 11:27:58 -0700 Lines: 32 Message-ID: <93qegsFdkkU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net SMKCPz641AA5rul8KGNrbQLZk4JJiDy2P2Zxw7HPHPa6FnnEug Cancel-Lock: sha1:28vQ7j3Hh2KSEwnZzhkRi3ysrDY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5016 On 5/20/2011 10:01 PM, logic_guy wrote: > I have been learning about VHDL 2008 and wanted to try a simple example > of the 2008 enhancements. I created the following test file: > entity generic_mux2 is > generic (type data_type); > port (sel : in bit; a, b : in data_type; > z : out data_type ); > end entity generic_mux2; > > architecture rtl of generic_mux2 is > begin > z<= a when sel = '0' else b; > end architecture rtl; ... > # ** Error: generic_mux2.vhdl(2): near "type": expecting IDENTIFIER > # C:/modeltech_10.0a/win32/vcom failed. ) -- Did you have library ieee; use ieee.std_logic_1164.all; -- at the top? Would a generic entity need an instance and generic map? incr_inst : entity work.generic_mux2 generic map ( data_type => std_ulogic) port map ( ... ); Good luck. -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:53:20 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error Date: Sat, 21 May 2011 14:57:14 -0700 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: Injection-Date: Sat, 21 May 2011 21:57:03 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="30789"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19/FTBOAt+UVahy5V2yIe2eSSs+d+MX4Sg=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6090 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:pP9PccpCxjJLrQnfim96K6p+XDk= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5017 "Alan Fitch" wrote in message > > The VHDL 2008 support is documented under Help > Technotes > vhdl2008 Both the vhdl2008 and vhdl2008migration technotes are completely mum about the topic of generic types. They don't say they support it and they don't say it's not supported. Apparently, the answer is "no". (The business of generic types does appear to be a fairly big leap for the language.) Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:20 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error Date: Sat, 21 May 2011 20:03:23 -0700 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <93qegsFdkkU1@mid.individual.net> Injection-Date: Sun, 22 May 2011 03:02:36 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="25967"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CaWNGJlK2Tdpu6fHJ7MmDCmlv/r5ThFc=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6090 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:fyHAMjDOz9xBLi5loODeTSBSoLQ= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5018 "Mike Treseler" wrote in message news:93qegsFdkkU1@mid.individual.net... > > -- Did you have > library ieee; > use ieee.std_logic_1164.all; > -- at the top? > > Would a generic entity need an instance and generic map? > > incr_inst : entity work.generic_mux2 > generic map ( data_type => std_ulogic) > port map ( ... ); > > Good luck. > > -- Mike Treseler Adding library ieee; use ieee.std_logic_1164.all; to the top doesn't help. Same error message. Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:20 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a26g2000vbo.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error Date: Tue, 24 May 2011 04:00:06 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <91903f33-8fa0-4455-8f42-222c2f3f9416@a26g2000vbo.googlegroups.com> References: <93qegsFdkkU1@mid.individual.net> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1306234806 17590 127.0.0.1 (24 May 2011 11:00:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 May 2011 11:00:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a26g2000vbo.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5019 Hi, I have tried your example with ModelsimPE 10.0b and I got the same error message. Cheers, hssig From newsfish@newsfish Tue Aug 9 07:53:20 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!s9g2000yqm.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Help Getting some VHDL code Date: Tue, 24 May 2011 16:48:35 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: NNTP-Posting-Host: 82.132.211.5 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1306280915 29434 127.0.0.1 (24 May 2011 23:48:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 May 2011 23:48:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s9g2000yqm.googlegroups.com; posting-host=82.132.211.5; posting-account=SCzijgoAAAAa4zEhr_42BlqsvJquENQ2 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UALERCHNK X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5020 Hi I am trying to learn VHDL on modem design Where could I get the hdl code (I think it would be easy to learn form a already made code) for doing PSK modulation? Additionally I am looking for Communications ports -Serial, USB, Ethernet, Memory Microcontroller for DSP purpose -CPU DSP - Filtering Other Digital modulations Thank you in advance for your help! From newsfish@newsfish Tue Aug 9 07:53:21 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!e26g2000vbz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Help Getting some VHDL code Date: Wed, 25 May 2011 05:49:57 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: References: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306327797 10589 127.0.0.1 (25 May 2011 12:49:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 May 2011 12:49:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e26g2000vbz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5021 On May 24, 7:48=A0pm, Peter wrote: > Hi I am trying to learn VHDL on modem design > > Where could I get the hdl code (I think it would be easy to learn form > a already made code) for doing PSK modulation? > > Additionally I am looking for > > Communications ports > > -Serial, USB, Ethernet, > > Memory > > Microcontroller for DSP purpose > =A0 =A0 =A0 =A0 -CPU > > DSP - Filtering > > Other Digital modulations > > Thank you in advance for your help! Opencores is a place to start for existing code. But looking at existing code is not a good way or even a viable way of learning modem design. Some of it you can learn from books. But there will be a lot you need to learn from others. Then you will do well to post in comp.dsp to ask specific questions. You are trying to learn a field that is large and complex. Don't expect it to happen overnight. Rick From newsfish@newsfish Tue Aug 9 07:53:21 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g28g2000yqa.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: Help Getting some VHDL code Date: Wed, 25 May 2011 14:55:18 -0700 (PDT) Organization: http://groups.google.com Lines: 89 Message-ID: <0ea4f008-bfe5-4c08-b3cb-d4c7cb08b03c@g28g2000yqa.googlegroups.com> References: NNTP-Posting-Host: 82.132.210.210 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306360518 19066 127.0.0.1 (25 May 2011 21:55:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 May 2011 21:55:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g28g2000yqa.googlegroups.com; posting-host=82.132.210.210; posting-account=SCzijgoAAAAa4zEhr_42BlqsvJquENQ2 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UALERCHNK X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5022 On May 25, 1:49=A0pm, rickman wrote: > On May 24, 7:48=A0pm, Peter wrote: > > > > > > > Hi I am trying to learn VHDL on modem design > > > Where could I get the hdl code (I think it would be easy to learn form > > a already made code) for doing PSK modulation? > > > Additionally I am looking for > > > Communications ports > > > -Serial, USB, Ethernet, > > > Memory > > > Microcontroller for DSP purpose > > =A0 =A0 =A0 =A0 -CPU > > > DSP - Filtering > > > Other Digital modulations > > > Thank you in advance for your help! > > Opencores is a place to start for existing code. =A0But looking at > existing code is not a good way or even a viable way of learning modem > design. =A0Some of it you can learn from books. =A0But there will be a lo= t > you need to learn from others. =A0Then you will do well to post in > comp.dsp to ask specific questions. =A0You are trying to learn a field > that is large and complex. =A0Don't expect it to happen overnight. > > Rick Thanks Rick for giving a input! I've already came across that website before when I was looking for DDS. it it Opencores.org? Have you got any code and material that could I use to learn? I would like to get my hard on these books: (have you got any of those?) The student's guide to VHDL by Peter J. Ashenden System-on-a-chip: design and test by Rochit Rajsuman Applications of VHDL to circuit design By Randolph E. Harr, Alec G. Stanculescu The electronic design automation handbook By Dirk Jansen Electronic engineering, Volume 68, Issues 835-840 VHDL-2008: just the new stuff By Peter J. Ashenden, Jim Lewis Proceedings of the 2009 International Conference on Signals, Syatems and ... By Himanshu Soni Software defined radio: origins, drivers, and international perspectives By Wally H. W. Tuttlebee Analog circuit design: structured mixed-mode design, multi-bit sigma- delta ... By Michiel Steyaert, Arthur H. M. van Roermund, Johan Customizable embedded processors: design technologies and applications By Paolo Ienne, Rainer Leupers New Data Formats for DSP Applications By Manuel Richey Signal processing in telecommunications: proceedings of the 7th International Thyrrhenian Workshop on Digital Communications, Viareggio, Italy, September 10-14, 1995, Volume 1995 by Ezio Biglieri, Marco Luise Software radio architecture: object-oriented approaches to wireless systems ... By Joseph Mitola VHDL user's forum in Europe : SIG-VHDL Spring'97 working conference, Toledo ... By F=E9d=E9ration internationale pour le traitement de Delta-Sigma Understanding Delta-Sigma Data Converters by R. Schreier, G Delta Sigma Data Converters: Theory, Design and Simulation by R. Schreier, G. Temes, S Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation James C. Candy, Gabor C The system designer's guide to VHDL-AMS: analog, mixed-signal, and mixed ... By Peter J. Ashenden, Gregory D. Peterson, Darrell A From newsfish@newsfish Tue Aug 9 07:53:21 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r20g2000yqd.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: Help Getting some VHDL code Date: Wed, 25 May 2011 15:30:28 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: References: NNTP-Posting-Host: 82.132.210.208 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306362628 17844 127.0.0.1 (25 May 2011 22:30:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 May 2011 22:30:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r20g2000yqd.googlegroups.com; posting-host=82.132.210.208; posting-account=SCzijgoAAAAa4zEhr_42BlqsvJquENQ2 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UALERCHNK X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5023 On May 25, 1:49=A0pm, rickman wrote: > On May 24, 7:48=A0pm, Peter wrote: > > > > > > > Hi I am trying to learn VHDL on modem design > > > Where could I get the hdl code (I think it would be easy to learn form > > a already made code) for doing PSK modulation? > > > Additionally I am looking for > > > Communications ports > > > -Serial, USB, Ethernet, > > > Memory > > > Microcontroller for DSP purpose > > =A0 =A0 =A0 =A0 -CPU > > > DSP - Filtering > > > Other Digital modulations > > > Thank you in advance for your help! > > Opencores is a place to start for existing code. =A0But looking at > existing code is not a good way or even a viable way of learning modem > design. =A0Some of it you can learn from books. =A0But there will be a lo= t > you need to learn from others. =A0Then you will do well to post in > comp.dsp to ask specific questions. =A0You are trying to learn a field > that is large and complex. =A0Don't expect it to happen overnight. > > Rick Thanks Rick for giving an input! I've already came across that website before when I was looking for DDS. it it Opencores.org? Have you got any code and material that could I use to learn? I would like to get my hard on these books: (have you got any of those?) The student's guide to VHDL by Peter J. Ashenden System-on-a-chip: design and test by Rochit Rajsuman Applications of VHDL to circuit design By Randolph E. Harr, Alec G. Stanculescu The electronic design automation handbook By Dirk Jansen Electronic engineering, Volume 68, Issues 835-840 VHDL-2008: just the new stuff By Peter J. Ashenden, Jim Lewis Proceedings of the 2009 International Conference on Signals, Syatems and ... By Himanshu Soni Software defined radio: origins, drivers, and international perspectives By Wally H. W. Tuttlebee Analog circuit design: structured mixed-mode design, multi-bit sigma- delta ... By Michiel Steyaert, Arthur H. M. van Roermund, Johan Customizable embedded processors: design technologies and applications By Paolo Ienne, Rainer Leupers New Data Formats for DSP Applications By Manuel Richey Signal processing in telecommunications: proceedings of the 7th International Thyrrhenian Workshop on Digital Communications, Viareggio, Italy, September 10-14, 1995, Volume 1995 by Ezio Biglieri, Marco Luise Software radio architecture: object-oriented approaches to wireless systems ... By Joseph Mitola VHDL user's forum in Europe : SIG-VHDL Spring'97 working conference, Toledo ... By F=E9d=E9ration internationale pour le traitement de Delta-Sigma Understanding Delta-Sigma Data Converters by R. Schreier, G Delta Sigma Data Converters: Theory, Design and Simulation by R. Schreier, G. Temes, S Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation James C. Candy, Gabor C The system designer's guide to VHDL-AMS: analog, mixed-signal, and mixed ... By Peter J. Ashenden, Gregory D. Peterson, Darrell A From newsfish@newsfish Tue Aug 9 07:53:21 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l26g2000yqm.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Help Getting some VHDL code Date: Thu, 26 May 2011 00:29:43 -0700 (PDT) Organization: http://groups.google.com Lines: 94 Message-ID: <9c0a1d7b-d92c-444a-aedf-daf29516d660@l26g2000yqm.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306394983 11366 127.0.0.1 (26 May 2011 07:29:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 26 May 2011 07:29:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l26g2000yqm.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5024 On May 25, 11:30=A0pm, Peter wrote: > On May 25, 1:49=A0pm, rickman wrote: > > > > > > > > > > > On May 24, 7:48=A0pm, Peter wrote: > > > > Hi I am trying to learn VHDL on modem design > > > > Where could I get the hdl code (I think it would be easy to learn for= m > > > a already made code) for doing PSK modulation? > > > > Additionally I am looking for > > > > Communications ports > > > > -Serial, USB, Ethernet, > > > > Memory > > > > Microcontroller for DSP purpose > > > =A0 =A0 =A0 =A0 -CPU > > > > DSP - Filtering > > > > Other Digital modulations > > > > Thank you in advance for your help! > > > Opencores is a place to start for existing code. =A0But looking at > > existing code is not a good way or even a viable way of learning modem > > design. =A0Some of it you can learn from books. =A0But there will be a = lot > > you need to learn from others. =A0Then you will do well to post in > > comp.dsp to ask specific questions. =A0You are trying to learn a field > > that is large and complex. =A0Don't expect it to happen overnight. > > > Rick > > Thanks Rick for giving an input! > > I've already came across that website before when I was looking for > =A0DDS. it it Opencores.org? > > Have you got any code and material that could I use to learn? > > I would like to get my hard on these books: (have you got any of > =A0those?) > > The student's guide to VHDL by Peter J. Ashenden > =A0System-on-a-chip: design and test by Rochit Rajsuman > =A0Applications of VHDL to circuit design By Randolph E. Harr, Alec G. > =A0Stanculescu > =A0The electronic design automation handbook By Dirk Jansen > =A0Electronic engineering, Volume 68, Issues 835-840 > =A0VHDL-2008: just the new stuff By Peter J. Ashenden, Jim Lewis > =A0Proceedings of the 2009 International Conference on Signals, Syatems > =A0and ... By Himanshu Soni > =A0Software defined radio: origins, drivers, and international > =A0perspectives By Wally H. W. Tuttlebee > =A0Analog circuit design: structured mixed-mode design, multi-bit > sigma- > =A0delta ... By Michiel Steyaert, Arthur H. M. van Roermund, Johan > =A0Customizable embedded processors: design technologies and > applications > =A0By Paolo Ienne, Rainer Leupers > =A0New Data Formats for DSP Applications By Manuel Richey > =A0Signal processing in telecommunications: proceedings of the 7th > =A0International Thyrrhenian Workshop on Digital Communications, > =A0Viareggio, Italy, September 10-14, 1995, Volume 1995 by Ezio > Biglieri, > =A0Marco Luise > =A0Software radio architecture: object-oriented approaches to wireless > =A0systems ... By Joseph Mitola > =A0VHDL user's forum in Europe : SIG-VHDL Spring'97 working conference, > =A0Toledo ... By F=E9d=E9ration internationale pour le traitement de > > Delta-Sigma > =A0Understanding Delta-Sigma Data Converters by R. Schreier, G > =A0Delta Sigma Data Converters: Theory, Design and Simulation by R. > =A0Schreier, G. Temes, S > =A0Oversampling Delta-Sigma Data Converters: Theory, Design and > =A0Simulation James C. Candy, Gabor C > =A0The system designer's guide to VHDL-AMS: analog, mixed-signal, and > =A0mixed ... By Peter J. Ashenden, Gregory D. Peterson, Darrell A Have you tried checking amazon.com? Or your local library? From newsfish@newsfish Tue Aug 9 07:53:21 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder2.cambriumusenet.nl!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!newsfeed.neostrada.pl!unt-exc-02.news.neostrada.pl!unt-spo-a-01.news.neostrada.pl!news.neostrada.pl.POSTED!not-for-mail Date: Fri, 27 May 2011 04:53:37 +0200 From: Piotr User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; pl; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: std_logic_vector to integer Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 39 Message-ID: <4ddf1231$0$2456$65785112@news.neostrada.pl> Organization: Telekomunikacja Polska NNTP-Posting-Host: 83.27.148.7 X-Trace: 1306464817 unt-rea-a-01.news.neostrada.pl 2456 83.27.148.7:1720 X-Complaints-To: abuse@news.neostrada.pl Xref: feeder.eternal-september.org comp.lang.vhdl:5025 Hi! I'm beginner. I can't solve this problem. I'm trying to convert std_logic_vector to integer. It doesn't work. I have an error: line 215: Different types for port on entity and component for ------------ -- Code: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; entity VectorToInteger is port ( Clk_50MHz: in std_logic; i: in std_logic_vector(7 downto 0); o: out Integer range 300 downto -127); end VectorToInteger; architecture Behavioral of VectorToInteger is begin process(Clk_50MHz, i) begin if (rising_edge(Clk_50MHz)) then o <= conv_integer(i); end if; end process; end Behavioral; ----------------- This is very important for me. Please help me... Piotr From newsfish@newsfish Tue Aug 9 07:53:21 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "scrts" Newsgroups: comp.lang.vhdl Subject: Re: std_logic_vector to integer Date: Fri, 27 May 2011 08:07:19 +0300 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <4ddf1231$0$2456$65785112@news.neostrada.pl> Injection-Date: Fri, 27 May 2011 05:07:15 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="iT5NBGfOsLgPoft0V0gh3A"; logging-data="26750"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/kEnzGC4hfbNruSVDJD/m/" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6090 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:bFXiEtNR7z+Ij11YDPs+eaC4NRU= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5026 "Piotr" wrote in message news:4ddf1231$0$2456$65785112@news.neostrada.pl... > Hi! > > I'm beginner. I can't solve this problem. I'm trying to convert > std_logic_vector to integer. > > It doesn't work. I have an error: > line 215: Different types for port on entity and component for > > > ------------ > -- Code: > > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use IEEE.std_logic_signed.all; Do not use std_logic_arith and std_logic_signed. Use numeric_std instead. You will find all the required functions there From newsfish@newsfish Tue Aug 9 07:53:22 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!l18g2000yql.googlegroups.com!not-for-mail From: hhanff Newsgroups: comp.lang.vhdl Subject: Re: std_logic_vector to integer Date: Thu, 26 May 2011 22:30:19 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <55132911-f064-416d-a541-d64aff4b4dbd@l18g2000yql.googlegroups.com> References: <4ddf1231$0$2456$65785112@news.neostrada.pl> NNTP-Posting-Host: 178.3.205.199 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1306474219 2180 127.0.0.1 (27 May 2011 05:30:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 May 2011 05:30:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l18g2000yql.googlegroups.com; posting-host=178.3.205.199; posting-account=TIldIAoAAAD4kpJj3f9wLt8pW9aqX3pw User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5027 On 27 Mai, 07:07, "scrts" wrote: > "Piotr" wrote in message > > news:4ddf1231$0$2456$65785112@news.neostrada.pl... > > > > > > > > > > > Hi! > > > I'm beginner. I can't solve this problem. I'm trying to convert > > std_logic_vector to integer. > > > It doesn't work. I have an error: > > line 215: Different types for port on entity and component for > > > > > ------------ > > -- Code: > > > library IEEE; > > use IEEE.std_logic_1164.all; > > use IEEE.std_logic_arith.all; > > use IEEE.std_logic_signed.all; > > Do not use std_logic_arith and std_logic_signed. Use numeric_std instead. > You will find all the required functions there If you do not know how to convert between different types using numeric_std, you might find this http://www.lothar-miller.de/s9y/uploads/Bilder/Usage_of_numeric_std.pdf helpfull. Greetings from rainy Bremen, hhanff From newsfish@newsfish Tue Aug 9 07:53:22 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!newsfeed.neostrada.pl!unt-exc-01.news.neostrada.pl!unt-spo-b-01.news.neostrada.pl!news.neostrada.pl.POSTED!not-for-mail Date: Fri, 27 May 2011 08:17:11 +0200 From: Piotr User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; pl; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: std_logic_vector to integer References: <4ddf1231$0$2456$65785112@news.neostrada.pl> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 7bit Lines: 3 Message-ID: <4ddf41e7$0$2453$65785112@news.neostrada.pl> Organization: Telekomunikacja Polska NNTP-Posting-Host: 83.27.150.105 X-Trace: 1306477031 unt-rea-a-01.news.neostrada.pl 2453 83.27.150.105:4171 X-Complaints-To: abuse@news.neostrada.pl Xref: feeder.eternal-september.org comp.lang.vhdl:5028 Thank You very much. I've solved the problem. Piotr From newsfish@newsfish Tue Aug 9 07:53:22 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!j13g2000pro.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: SystemRDL Date: Tue, 31 May 2011 16:22:13 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <912d5c26-28d5-479c-b033-79539dcd1540@j13g2000pro.googlegroups.com> References: <61fc1cde-f427-4c6e-8760-e6035f77da0b@r35g2000prj.googlegroups.com> NNTP-Posting-Host: 203.58.241.190 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306884134 28414 127.0.0.1 (31 May 2011 23:22:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 May 2011 23:22:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j13g2000pro.googlegroups.com; posting-host=203.58.241.190; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5029 Clearly not a popular standard then? Anyone using at all? On May 20, 9:12=A0am, Dal wrote: > I have come across the SystemRDL standard to define a devices register > space. =A0Are there any open source tools for generating documentation > from systemRDL? > > I currently use propriety scripts for converting a register definition > spreadsheet into code. =A0Before I bash out another scripts to generate > a document I thought this could be an opportunity to dabble with this > new standard. > > I don't need all the verification bells and whistles that seem to be > offered by commercial tools - just the documentation generator part. From newsfish@newsfish Tue Aug 9 07:53:22 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Tue, 31 May 2011 18:27:00 -0500 Date: Tue, 31 May 2011 16:27:06 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: SystemRDL References: <61fc1cde-f427-4c6e-8760-e6035f77da0b@r35g2000prj.googlegroups.com> <912d5c26-28d5-479c-b033-79539dcd1540@j13g2000pro.googlegroups.com> In-Reply-To: <912d5c26-28d5-479c-b033-79539dcd1540@j13g2000pro.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 28 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-sGH8AZ6rmyEjQNjIw1gedvg+uauvVQkaaPDjb/a9iG0KxZhAH6f33DxqKEYegUkIBqFFO21Eoyy/NKC!4m0SD5w6rHm+bH2WWHM+oB0nezg+1F9ndmLoGmEz6NDFf2mNtfdHTRJGT3tAKoJbi47Wd6mnUdOA!Zw== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2330 Xref: feeder.eternal-september.org comp.lang.vhdl:5030 On 5/31/2011 4:22 PM, Dal wrote: > Clearly not a popular standard then? > > Anyone using at all? > > > On May 20, 9:12 am, Dal wrote: >> I have come across the SystemRDL standard to define a devices register >> space. Are there any open source tools for generating documentation >> from systemRDL? >> >> I currently use propriety scripts for converting a register definition >> spreadsheet into code. Before I bash out another scripts to generate >> a document I thought this could be an opportunity to dabble with this >> new standard. >> >> I don't need all the verification bells and whistles that seem to be >> offered by commercial tools - just the documentation generator part. > I gave it a look over after you asked; since I'm in the process of putting together a proprietary solution to do much the same. It seemed too complicated by half. Which is, I suppose, better than IP-XACT, which as near as I can tell is too complicated by tenfold. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Tue Aug 9 07:53:22 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!noris.net!news.internetdienste.de!news.tu-darmstadt.de!news.belwue.de!news.uni-stuttgart.de!news.nask.pl!news.nask.org.pl!news.icm.edu.pl!not-for-mail From: Wojciech M. Zabolotny Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Connecting of IP core simulated in GHDL to pseudoterminal via UART-like interface Followup-To: comp.arch.fpga Date: Thu, 2 Jun 2011 17:45:10 +0000 (UTC) Organization: Dzial Sieciowy ICM, Uniwersytet Warszawski Lines: 53 Message-ID: NNTP-Posting-Host: koral.ise.pw.edu.pl X-Trace: news.net.icm.edu.pl 1307036710 27164 194.29.161.2 (2 Jun 2011 17:45:10 GMT) X-Complaints-To: usenet@news.net.icm.edu.pl NNTP-Posting-Date: Thu, 2 Jun 2011 17:45:10 +0000 (UTC) Keywords: GHDL, VPI, VHDL, simulation, UART, interactive, debug User-Agent: slrn/pre1.0.0-18 (Linux) Xref: feeder.eternal-september.org comp.arch.fpga:15640 comp.lang.vhdl:5031 When working with simulated soft CPUs to be implemented in FPGA, I often needed a possibility to connect terminal emulator (e.g. Minicom) or my own program to serial port of the simulated IP core. Finally I've found a solution, which seems to be good enough to share it with others. I use the pseudoterminal (ptmx) found in Linux to establish communication between GHDL simulator and my terminal program. However GHDL does not offer functions needed to control pseudoterminals, therefore I've prepared a small C library (ghdl_pty.c) providing necessary functions via VPI. Additionally I needed to provide nonblocking reading from the pseudoterminal, to avoid stopping of simulation when no data is available this functionality is also implemented in ghdl_pty.c, in function ghdl_pty_read. >From the VHDL side, my pseudo UART is visible as: component ghdl_uart port ( data_out : out std_logic_vector(7 downto 0); data_in : in std_logic_vector(7 downto 0); dav : out std_logic; -- received data available ready : out std_logic; -- there is free space in transmit buffer empty : out std_logic; -- the transmit buffer is empty rd : in std_logic; -- asynchronous read strobe wr : in std_logic -- asynchronous write strobe ); end component; When new data arrives, "dav" goes high. To read the data, you should set "rd" to '1' and the data will be visible on "data_out". If no more data are in the input queue, "dav" goes low. If you want to write data, you put them on "data_in", and rise "wr". The data are transmitted to the output queue, and later transmitted to the pseudoterminal. Full sources, published as public domain are available on alt.sources usenet group, in thread "Pseudo UART allowing to connect via pseudoterminal to GHDL simulated IP core" ( news: http://http://groups.google.com/group/alt.sources/msg/bc8eb919101839ba ) You can find more information in the "desc.txt" file available in the archive contained in the alt.sources message. I hope, that the emulated UART will be useful for you. Wojciech M. Zabolotny wzabise.pw.edu.pl From newsfish@newsfish Tue Aug 9 07:53:22 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Vivek Menon Newsgroups: comp.lang.vhdl Subject: Parallel in, Parallel out shift register Date: Tue, 7 Jun 2011 17:00:10 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 146.5.8.107 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307491210 25106 127.0.0.1 (8 Jun 2011 00:00:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 00:00:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.5.8.107; posting-account=GtBy8QoAAADwGUEYPAR_dKzOh-XAf-VG User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5033 I am trying to synthesize and simulate a parallel shift register that keeps shifting the input data as long as the enable pin is active. entity shift_out is Port ( --Inputs clk : in std_logic; en : in std_logic; rst : in std_logic; in1 : in std_logic_vector(31 downto 0); -- Outputs shift_val : out std_logic_vector(31 downto 0) ); end entity shift_out; architecture arch of shift_out is signal shift_t1 : std_logic_vector(31 downto 0) := (others => '0'); ... process (clk, rst, in1, en) is begin if rst = '1' then shift_t1 <= (others=>'0'); shift_val <= (others=>'0'); elsif rising_edge(clk) then if (en = '1') then shift_t1 <= shift_t1 ror x"10"; shift_t1 <= in1; end if ; end if; end process; shift_val <= shift_t1; end arch; I am confused with the ror approach, I have tried array slicing and that did not simulate as well. ANy suggestions?? From newsfish@newsfish Tue Aug 9 07:53:23 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!e21g2000vbz.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Tue, 7 Jun 2011 23:28:30 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: <5e7162d0-1002-492e-a9c1-30fb9c9cc4e1@e21g2000vbz.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307514512 32652 127.0.0.1 (8 Jun 2011 06:28:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 06:28:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000vbz.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.17) Gecko/20110422 Ubuntu/10.04 (lucid) Firefox/3.6.17,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5034 On 8 Jun., 02:00, Vivek Menon wrote: > I am trying to synthesize and simulate a parallel shift register that kee= ps shifting the input data as long as the enable pin is active. > > entity shift_out is > =A0 =A0 =A0 =A0 Port ( > =A0 =A0 =A0 =A0 --Inputs > =A0 =A0 =A0 =A0 clk =A0 =A0 : in std_logic; > =A0 =A0 en =A0 =A0 =A0: in std_logic; > =A0 =A0 rst =A0 =A0 : in std_logic; > =A0 =A0 =A0 =A0 in1 =A0 =A0 : in =A0std_logic_vector(31 downto 0); > > =A0 =A0 =A0 =A0 -- Outputs > =A0 =A0 =A0 =A0 shift_val : out std_logic_vector(31 downto 0) > =A0 =A0 =A0); > end entity shift_out; > > architecture arch of shift_out is > > signal shift_t1 =A0 : std_logic_vector(31 downto 0) :=3D (others =3D> '0'= ); > ... > =A0 =A0 =A0 =A0 process (clk, rst, in1, en) is > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if rst =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 <=3D (others=3D>= '0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_val <=3D (others=3D= >'0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif rising_edge(clk) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (en =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 = <=3D shift_t1 ror x"10"; =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 = <=3D in1; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if ; =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > > =A0 =A0 =A0 =A0 shift_val <=3D shift_t1; > > end arch; > > I am confused with the ror approach, I have tried array slicing and that = did not simulate as well. > ANy suggestions?? Hi, What error messages are you getting from the tools? Have you checked wether the ror function works for the data type you are using? Another way to shift/rotate vectors goes like this: shift_t1 <=3D shift_t1(shift_t1'length-2 downto 0) & shift_t1(shift_t1'length-1); -- simple rotate by one, missing an input, but you can overwrite the LSB Have a nice synthesis Eilert From newsfish@newsfish Tue Aug 9 07:53:23 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t16g2000vbi.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Tue, 7 Jun 2011 23:36:23 -0700 (PDT) Organization: http://groups.google.com Lines: 78 Message-ID: <2afe77ba-4382-4111-9f70-7244096d51db@t16g2000vbi.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307514984 25924 127.0.0.1 (8 Jun 2011 06:36:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 06:36:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t16g2000vbi.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.17) Gecko/20110422 Ubuntu/10.04 (lucid) Firefox/3.6.17,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5035 On 8 Jun., 02:00, Vivek Menon wrote: > I am trying to synthesize and simulate a parallel shift register that kee= ps shifting the input data as long as the enable pin is active. > > entity shift_out is > =A0 =A0 =A0 =A0 Port ( > =A0 =A0 =A0 =A0 --Inputs > =A0 =A0 =A0 =A0 clk =A0 =A0 : in std_logic; > =A0 =A0 en =A0 =A0 =A0: in std_logic; > =A0 =A0 rst =A0 =A0 : in std_logic; > =A0 =A0 =A0 =A0 in1 =A0 =A0 : in =A0std_logic_vector(31 downto 0); > > =A0 =A0 =A0 =A0 -- Outputs > =A0 =A0 =A0 =A0 shift_val : out std_logic_vector(31 downto 0) > =A0 =A0 =A0); > end entity shift_out; > > architecture arch of shift_out is > > signal shift_t1 =A0 : std_logic_vector(31 downto 0) :=3D (others =3D> '0'= ); > ... > =A0 =A0 =A0 =A0 process (clk, rst, in1, en) is > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if rst =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 <=3D (others=3D>= '0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_val <=3D (others=3D= >'0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif rising_edge(clk) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (en =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 = <=3D shift_t1 ror x"10"; =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 = <=3D in1; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if ; =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > > =A0 =A0 =A0 =A0 shift_val <=3D shift_t1; > > end arch; > > I am confused with the ror approach, I have tried array slicing and that = did not simulate as well. > ANy suggestions?? Hi, What error messages are you getting from the tools? Have you checked wether the ror function works for the data type you are using? Another way to shift/rotate vectors goes like this: shift_t1 <=3D shift_t1(shift_t1'length-2 downto 0) & shift_t1(shift_t1'length-1); -- simple rotate by one, missing an input, but you can overwrite the LSB Also there's some big flaw in your approach. You have no signal to distinguish between load and shift operation. Enable is working for both actions and so you are only always loading when enable is active and do not see any effect of the ror function. Do something like this: Define a port load : in std_logic; and in your enable branch: if load =3D '1' then shift_t1 <=3D in1; else -- rotate shift_t1 <=3D shift_t1(shift_t1'length-2 downto 0) & shift_t1(shift_t1'length-1); end if; Have a nice synthesis Eilert From newsfish@newsfish Tue Aug 9 07:53:23 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!h12g2000pro.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Wed, 8 Jun 2011 06:18:43 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <48b2d219-dbf1-4e9e-95e5-dd770dd1150f@h12g2000pro.googlegroups.com> References: NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307539347 24990 127.0.0.1 (8 Jun 2011 13:22:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 13:22:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h12g2000pro.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLEUCHNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5036 Take shift_val out of the clocked process. It should not be assigned in both the process and the concurrent assignment statement. Also, remove everything but clk and rst from the process sensitivity list. Andy From newsfish@newsfish Tue Aug 9 07:53:23 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g12g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Wed, 8 Jun 2011 08:48:32 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: <01a0ad2e-f672-47db-90d5-a6b6d6b81c26@g12g2000yqd.googlegroups.com> References: NNTP-Posting-Host: 74.126.85.132 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307548113 31561 127.0.0.1 (8 Jun 2011 15:48:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 15:48:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g12g2000yqd.googlegroups.com; posting-host=74.126.85.132; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB7.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5037 On Jun 7, 8:00=A0pm, Vivek Menon wrote: > I am trying to synthesize and simulate a parallel shift register that kee= ps shifting the input data as long as the enable pin is active. > Have you simulated your design and does it work as intended? If not, then get that working before synthesizing. If so, then I'm surprised because... > if (en =3D '1') then > =A0 shift_t1 <=3D shift_t1 ror x"10"; > =A0 =A0 shift_t1 <=3D in1; The second assignment to shift_t1 will override the first assignment. The net of all this is that the assignment with the 'ror' won't do anything. > I am confused with the ror approach, I have tried array slicing and that = did not simulate as well. Until you get the simulation working properly, it will likely not make much sense for you to try to synthesize. You have a basic issue with your design in that you don't have a method for loading and for shifting the data. Typically one would have a 'load' and a 'shift' input but it might be that you intend to load any time you're not shifting in which case you should have written if (en =3D '1') then shift_t1 <=3D shift_t1 ror x"10"; else -- KJ added shift_t1 <=3D in1; ... > ANy suggestions?? Also, the 'ror' function is defined for unsigned types, not std_logic_vector. function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; I would suggest changing the data type of shift_t1 shift_t1 : unsigned(31 downto 0); Then convert to/from std_logic_vectors on the various assignments. Also see Andy's suggestions. To have the compiler catch the first error that Andy pointed out, consider using std_ulogic rather than std_logic. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:23 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4def9b9f$0$49048$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Parallel in, Parallel out shift register Newsgroups: comp.lang.vhdl Date: Wed, 08 Jun 2011 17:56:15 +0200 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 100 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1307548575 news.xs4all.nl 49048 puiterl/[::ffff:195.242.97.150]:36768 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5038 Vivek Menon wrote: > I am trying to synthesize and simulate a parallel shift register that > keeps shifting the input data as long as the enable pin is active. > > entity shift_out is > Port ( > --Inputs > clk : in std_logic; > en : in std_logic; > rst : in std_logic; > in1 : in std_logic_vector(31 downto 0); > > -- Outputs > shift_val : out std_logic_vector(31 downto 0) > ); > end entity shift_out; > > architecture arch of shift_out is > > signal shift_t1 : std_logic_vector(31 downto 0) := (others => '0'); > ... > process (clk, rst, in1, en) is > begin > if rst = '1' then > shift_t1 <= (others=>'0'); > shift_val <= (others=>'0'); > elsif rising_edge(clk) then > if (en = '1') then > shift_t1 <= shift_t1 ror x"10"; > shift_t1 <= in1; > end if ; > end if; > end process; > > shift_val <= shift_t1; > > end arch; > > I am confused with the ror approach, Me too. What ror operator? What packages are you using? The only ror operator that I know of is from ieee.numeric_std: ------------------------------------------------------------------------------ -- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 -- compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_RIGHT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 -- compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_RIGHT(ARG, COUNT) > I have tried array slicing and that did not simulate as well. > ANy suggestions?? Posting error messages would be nice. Or observed/expected behaviour. I also suspect a missing else: if (en = '1') then shift_t1 <= shift_t1 ror x"10"; else --< !! shift_t1 <= in1; end if; And for the shift operation I would suggest something like: shift_t1 <= shift_t1(shift_t1'low) & shift_t1(shift_t1'high downto shift_t1'low+1); Which is the same as shift_t1 <= shift_t1(0) & shift_t1(31 downto 1); without the hard coded numbers. For the rest: remove 'in1' and 'en' from the sensitivity list. They are not needed. Oh, and resetting shift_val is not needed: it is not a flip-flop, shift_t1 is. And why using shift_t1 at all? Why not just shift_val? There is no need for the extra signal. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:24 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!tranq7.tranquility.net!feeder.erje.net!fdn.fr!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!l6g2000vbn.googlegroups.com!not-for-mail From: JohnSmith Newsgroups: comp.lang.vhdl Subject: simulation script Date: Wed, 8 Jun 2011 09:32:26 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> NNTP-Posting-Host: 84.236.127.63 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307550746 10876 127.0.0.1 (8 Jun 2011 16:32:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 16:32:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000vbn.googlegroups.com; posting-host=84.236.127.63; posting-account=xPZEcAoAAABZVb8HlkUfjHjXa4_YJ-uv User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5039 Hi, How can I use an environment variable in a ".do" script running it in the modelsim window? I tried the windows environment variable in % characters, but doesnt work. Absolute paths work but I want use this scripts on different computers. vsim -sdftyp {/UUT=%MYDIR%/dir/.../timesim.sdf} ... Thanks From newsfish@newsfish Tue Aug 9 07:53:24 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l14g2000pro.googlegroups.com!not-for-mail From: MJB Newsgroups: comp.lang.vhdl Subject: Re: simulation script Date: Wed, 8 Jun 2011 09:45:04 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <97a9f4db-e769-4376-906e-8aa8c45de3f2@l14g2000pro.googlegroups.com> References: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> NNTP-Posting-Host: 199.46.200.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307551504 363 127.0.0.1 (8 Jun 2011 16:45:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 16:45:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l14g2000pro.googlegroups.com; posting-host=199.46.200.230; posting-account=XsPsLQoAAABg05Q6wOj-nB1nqE0qsC-B User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRU X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5040 On Jun 8, 9:32=A0am, JohnSmith wrote: > Hi, > > How can I use an environment variable in a ".do" script running it in > the modelsim window? > > I tried the windows environment variable in % characters, but doesnt > work. Absolute paths work but I want use this scripts on different > computers. > > vsim -sdftyp {/UUT=3D%MYDIR%/dir/.../timesim.sdf} ... > > Thanks Try using the Tcl env() function. Modelsim's shell is essentially a Tcl command line evironment and the .do files are .tcl scripts. to get your directory, try /UUT=3Denv(MYDIR)/ ..... I don't have a Modelsim installation handy so this is just off the top of my head. Hope you find the solution! From newsfish@newsfish Tue Aug 9 07:53:24 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!dn9g2000vbb.googlegroups.com!not-for-mail From: JohnSmith Newsgroups: comp.lang.vhdl Subject: Re: simulation script Date: Wed, 8 Jun 2011 10:00:54 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: References: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> <97a9f4db-e769-4376-906e-8aa8c45de3f2@l14g2000pro.googlegroups.com> NNTP-Posting-Host: 84.236.127.63 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307552454 27974 127.0.0.1 (8 Jun 2011 17:00:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 17:00:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dn9g2000vbb.googlegroups.com; posting-host=84.236.127.63; posting-account=xPZEcAoAAABZVb8HlkUfjHjXa4_YJ-uv User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5041 On Jun 8, 6:45=A0pm, MJB wrote: > On Jun 8, 9:32=A0am, JohnSmith wrote: > > > Hi, > > > How can I use an environment variable in a ".do" script running it in > > the modelsim window? > > > I tried the windows environment variable in % characters, but doesnt > > work. Absolute paths work but I want use this scripts on different > > computers. > > > vsim -sdftyp {/UUT=3D%MYDIR%/dir/.../timesim.sdf} ... > > > Thanks > > Try using the Tcl env() function. =A0Modelsim's shell is essentially a > Tcl command line evironment and the .do files are .tcl scripts. > > to get your directory, try /UUT=3Denv(MYDIR)/ ..... > > I don't have a Modelsim installation handy so this is just off the top > of my head. =A0Hope you find the solution! Doesnt work.. From newsfish@newsfish Tue Aug 9 07:53:24 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!69.16.177.254.MISMATCH!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe21.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: simulation script References: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> <97a9f4db-e769-4376-906e-8aa8c45de3f2@l14g2000pro.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110608-1, 08/06/2011), Outbound message X-Antivirus-Status: Clean Lines: 36 Message-ID: NNTP-Posting-Host: 82.31.236.233 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe21.ams2 1307605525 82.31.236.233 (Thu, 09 Jun 2011 07:45:25 UTC) NNTP-Posting-Date: Thu, 09 Jun 2011 07:45:25 UTC Organization: virginmedia.com Date: Thu, 09 Jun 2011 08:45:21 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5042 On 08/06/2011 18:00, JohnSmith wrote: > On Jun 8, 6:45 pm, MJB wrote: >> On Jun 8, 9:32 am, JohnSmith wrote: >> >>> Hi, >> >>> How can I use an environment variable in a ".do" script running it in >>> the modelsim window? >> >>> I tried the windows environment variable in % characters, but doesnt >>> work. Absolute paths work but I want use this scripts on different >>> computers. >> >>> vsim -sdftyp {/UUT=%MYDIR%/dir/.../timesim.sdf} ... >> >>> Thanks >> >> Try using the Tcl env() function. Modelsim's shell is essentially a >> Tcl command line evironment and the .do files are .tcl scripts. >> >> to get your directory, try /UUT=env(MYDIR)/ ..... >> >> I don't have a Modelsim installation handy so this is just off the top >> of my head. Hope you find the solution! > > Doesnt work.. > MJB forgot the variable sign, vsim -sdftyp /UUT=$env(MYDIR)... Hans www.ht-lab.com From newsfish@newsfish Tue Aug 9 07:53:24 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g24g2000vbz.googlegroups.com!not-for-mail From: Matheus Arleson Newsgroups: comp.lang.vhdl Subject: generic circuit for read data from n files Date: Thu, 9 Jun 2011 10:42:40 -0700 (PDT) Organization: http://groups.google.com Lines: 57 Message-ID: <6ac0bf07-8c41-49ad-bf06-447112861e69@g24g2000vbz.googlegroups.com> NNTP-Posting-Host: 189.90.160.57 Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307641360 17030 127.0.0.1 (9 Jun 2011 17:42:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Jun 2011 17:42:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g24g2000vbz.googlegroups.com; posting-host=189.90.160.57; posting-account=AlwOaQoAAAAqhN3ZjLkuhW6ExoGtHdap User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.24 (KHTML, like Gecko) Ubuntu/10.04 Chromium/11.0.696.71 Chrome/11.0.696.71 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5043 hello, I'm currently working on a component that has the following behavior: 1) control component: ENTITY CONTROL IS GENERIC (FILE_NUMBER: NATURAL: =3D 10); PORT (FINISHED: IN STD_LOGIC_VECTOR ((FILE_NUMBER - 1) downto 0); CLK: IN std_logic; RST: IN std_logic; ENABLE: OUT STD_LOGIC_VECTOR ((FILE_NUMBER - 1) downto 0)); END CONTROL; 1.1 - Has the function of signaling which file must be read. It indicates that through a bit of door ENABLE. 1.2 - when the file finished being read, it indicates through a bit of door FINISHED. 1.3 - The control then passes to another file and repeat 1 and 2 until no more files to be read. ------------------------- 2) component of the reading of files ENTITY IS ARQ_MOD GENERIC (DATA_SIZE: NATURAL: =3D 16); PORT (ENABLE: IN std_logic; FINISHED: OUT std_logic; OUTPUT_DATA: OUT STD_LOGIC_VECTOR ((DATA_SIZE - 1) downto 0)); ARQ_MOD END; 1.1 - Has the function to open a file when the door ENABLE =3D '1 '. 1.2 - Read the file until the end. 1.3 - FINISHED =3D '1 '. indicates that the file over. 1.4 - OUTPUT_DATA =3D 'Z'. because the modules file are all connected to a bus. -------------------------------- need help on the following issues: * A plan to use a control unit and connect a number N of modules file to this control unit, for example using a LOOP GENERATE. the output of them was connected to a single bus. When ENABLE =3D '0 '-> OUTPUT_DATA =3D' Z ', then only the module in use has possession of the bus. * I would like to know how to pass the path of the file to file_open dynamically. * also, i need some ideas of implementation.... here is the idea of =E2=80=8B=E2=80=8Bthe circuit. http://www.photoshop.com/users/masx/...b35e3090d4c66c thanks. From newsfish@newsfish Tue Aug 9 07:53:24 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!17g2000prr.googlegroups.com!not-for-mail From: Amish Rughoonundon Newsgroups: comp.lang.vhdl Subject: divide by zero error from XILINX ISE Date: Fri, 10 Jun 2011 08:53:59 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <7460e134-de1c-46b7-9983-60576fd9d69f@17g2000prr.googlegroups.com> NNTP-Posting-Host: 65.116.131.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307721353 15024 127.0.0.1 (10 Jun 2011 15:55:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Jun 2011 15:55:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 17g2000prr.googlegroups.com; posting-host=65.116.131.6; posting-account=EkeN9woAAABH74ilPlXRsoxaDuvo-cEm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5044 Hi, I have this code. XILINX ISE Is giving me an error HDLParsers:866 "Division by zero" during synthesis. Why is that? Thanks for the help [CODE] CONSTANT CLOCK_FREQUENCY : integer := 50000000; -- Input clock frequency in hertz CONSTANT SWITCHING_FREQUENCY : integer := 400000; -- date drive frequency in hertz CONSTANT CLOCK_END_RAMP_RESET_A : integer := INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/ REAL(CLOCK_FREQUENCY)))-1; [/CODE] From newsfish@newsfish Tue Aug 9 07:53:25 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4df25005$0$49047$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: divide by zero error from XILINX ISE Newsgroups: comp.lang.vhdl Date: Fri, 10 Jun 2011 19:10:29 +0200 References: <7460e134-de1c-46b7-9983-60576fd9d69f@17g2000prr.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 33 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1307725829 news.xs4all.nl 49047 puiterl/[::ffff:195.242.97.150]:50857 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5045 Amish Rughoonundon wrote: > Hi, > I have this code. XILINX ISE Is giving me an error HDLParsers:866 > "Division by zero" during synthesis. Why is that? Thanks for the help > > [CODE] > CONSTANT CLOCK_FREQUENCY : integer := 50000000; -- Input > clock frequency in hertz > > CONSTANT SWITCHING_FREQUENCY : integer := 400000; -- date > drive frequency in hertz > > CONSTANT CLOCK_END_RAMP_RESET_A : integer := > INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/ > REAL(CLOCK_FREQUENCY)))-1; > [/CODE] I have no idea. One thing I do know: your code looks overcomplicated (to me). If I'm not mistaken, the above is identical to: constant CLOCK_END_RAMP_RESET_A : integer := integer(0.5 * real(CLOCK_FREQUENCY) / real(SWITCHING_FREQUENCY)) - 1; For the rest: I don't have real experience with Xilinx (or any other synthesizer for that matter). -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:25 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Vivek Menon Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Fri, 10 Jun 2011 15:15:14 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <111ee521-27c3-49da-89b1-420dc14a5cef@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 146.5.8.107 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307744116 1239 127.0.0.1 (10 Jun 2011 22:15:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Jun 2011 22:15:16 +0000 (UTC) In-Reply-To: <4def9b9f$0$49048$e4fe514c@news.xs4all.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.5.8.107; posting-account=GtBy8QoAAADwGUEYPAR_dKzOh-XAf-VG User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5046 Thanks for the tips, I was trying to synthesize a shift register using array slicing. Since that was not working, I tried all the remaining options, ror, sra, srl, etc. Here's how I did it finally: architecture arch of shift_out is -- Signals signal shift_t1 : std_logic_vector(1727 downto 0) := (others => '0'); begin process (clk, rst) is begin if rst = '1' then shift_t1 <= (others=>'0'); elsif rising_edge(clk) then if (load = '1') then shift_t1 <= in1; elsif (shift_en ='1') then shift_t1 <= shift_t1(15 downto 0) & shift_t1(1727 downto 16); end if ; end if; end process; shift_val <= shift_t1(15 downto 0); end architecture arch; From newsfish@newsfish Tue Aug 9 07:53:25 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c26g2000vbq.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: divide by zero error from XILINX ISE Date: Sat, 11 Jun 2011 09:06:11 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <46930f5f-d9fe-4008-babb-747d8916ca56@c26g2000vbq.googlegroups.com> References: <7460e134-de1c-46b7-9983-60576fd9d69f@17g2000prr.googlegroups.com> NNTP-Posting-Host: 71.255.155.168 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307808372 22257 127.0.0.1 (11 Jun 2011 16:06:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Jun 2011 16:06:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c26g2000vbq.googlegroups.com; posting-host=71.255.155.168; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5047 On Jun 10, 11:53=A0am, Amish Rughoonundon wrote: > Hi, > =A0I have this code. XILINX ISE Is giving me an error HDLParsers:866 > "Division by zero" during synthesis. Why is that? Thanks for the help > > [CODE] > CONSTANT CLOCK_FREQUENCY =A0 =A0 =A0 =A0: integer :=3D 50000000; =A0 =A0 = =A0-- Input > clock frequency in hertz > > CONSTANT SWITCHING_FREQUENCY =A0 =A0: integer :=3D 400000; =A0 =A0 =A0 = =A0-- date > drive frequency in hertz > > CONSTANT CLOCK_END_RAMP_RESET_A =A0 =A0 =A0 =A0 =A0 =A0 : integer :=3D > INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/ > REAL(CLOCK_FREQUENCY)))-1; > [/CODE] I'm going to take a wild guess that Xilinx is taking 1/CLOCK_FREQUENCY and converting it to integer zero, instead of using a real for the final divide operation. Perhaps using Paul's simplified version will fix the problem. The other possibility is that Xilinx's real format has an underflow for 1/50000000. This might happen if they don't use enough bits when dividing the mantissas for the intermediate result. Either way it could be called a bug. IEEE floating point has defined the temporary precision just for this sort of issue. -- Gabor From newsfish@newsfish Tue Aug 9 07:53:25 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: alivingstone Newsgroups: comp.lang.vhdl Subject: Post-synthesis simulation errors at generic map Date: Mon, 13 Jun 2011 08:49:53 -0700 (PDT) Organization: http://groups.google.com Lines: 64 Message-ID: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 20.132.68.148 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307980194 9025 127.0.0.1 (13 Jun 2011 15:49:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Jun 2011 15:49:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=20.132.68.148; posting-account=DxCl9goAAADG_waculUDLRA24J16aofl User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5049 I think this may be a common problem for the pros out there... I have a project where I use top-level generics to size aspects of the desi= gn. I allow the synthesis tool to use the default bindings, but I like to a= ssign different values during my behavioral testbench to speed things up. Pre-synthesis simulation works great, but post-synthesis or post-route simu= lations crash because the testbench is trying to map generics to a synthesi= zed component with no generics. This must come up often -- is there a stand= ard strategy for this? Configuration=20 Code snippet from the testbench: entity testbench is generic ( HPIXELS : positive :=3D 251; VPIXELS : positive :=3D 2 ); end entity; =20 architecture bhvr of testbench is=20 =20 component camera_top generic ( HPIXELS : positive :=3D 320; VPIXELS : positive :=3D 240; PIXDEPTH : integer range 1 to 16 :=3D 16 ); port ( ... ); end component; begin uut : camera_top generic map ( HPIXELS =3D> HPIXELS, VPIXELS =3D> VPIXELS ) port map ( ... ); end architecture; Errors from simulator (ModelSim PE 10.0a): # ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for compo= nent at 'uut'. # (Generic 'PIXDEPTH' is not on the entity.) # (Entity has no generics.) # Region: /testbench/uut # ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for compo= nent at 'uut'. # (Generic 'VPIXELS' is not on the entity.) # (Entity has no generics.) # Region: /testbench/uut # ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for compo= nent at 'uut'. # (Generic 'HPIXELS' is not on the entity.) # (Entity has no generics.) # Region: /testbench/uut Thanks all. From newsfish@newsfish Tue Aug 9 07:53:25 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!news.glorb.com!postnews.google.com!28g2000yqu.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map Date: Mon, 13 Jun 2011 12:38:16 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307993896 15620 127.0.0.1 (13 Jun 2011 19:38:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Jun 2011 19:38:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 28g2000yqu.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5050 On Jun 13, 11:49=A0am, alivingstone wrote: > I think this may be a common problem for the pros out there... > > Pre-synthesis simulation works great, but post-synthesis or post-route si= mulations crash because the testbench is trying to map generics to a synthe= sized component with no generics. This must come up often -- is there a sta= ndard strategy for this? Configuration > To do this you need to compile and produce a post route simulation file for each and every set of generics that you would like to simulate. In your case, for each specific combination of HPIXELS, VPIXELS and PIXDEPTH that you want to simulate you need to do a new build that has that specific setting and then repeat that process for each set of settings. Then in the testbench you'll need to select (via a generate statement) which specific post-route simulation you want to instantiate. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:26 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 14 Jun 2011 08:36:47 -0500 Date: Tue, 14 Jun 2011 14:36:47 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 28 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Kg8DzumCVZQ2qTwXygtQOy/5wy1w2Xve/hT2GJp+sIIv9/qr5pYeJbvK+sPgx1cpRJIGuN3ROqduKNh!XVbA2p8RhuswQFj0E1lyV0ZCTpzXXsCZ7LExzy7fG2Aowj6NX4mwidlQ9PBUJG5MY8+hfLo7G1Pg!SjeJyIQfGGJM6TOnLE8D+x+0 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2597 Xref: feeder.eternal-september.org comp.lang.vhdl:5051 On 13/06/11 20:38, KJ wrote: > On Jun 13, 11:49 am, alivingstone wrote: >> I think this may be a common problem for the pros out there... >> >> Pre-synthesis simulation works great, but post-synthesis or post-route simulations crash because the testbench is trying to map generics to a synthesized component with no generics. This must come up often -- is there a standard strategy for this? Configuration >> > > To do this you need to compile and produce a post route simulation > file for each and every set of generics that you would like to > simulate. In your case, for each specific combination of HPIXELS, > VPIXELS and PIXDEPTH that you want to simulate you need to do a new > build that has that specific setting and then repeat that process for > each set of settings. Then in the testbench you'll need to select > (via a generate statement) which specific post-route simulation you > want to instantiate. > > Kevin Jennings If it's just at the top level, another plan is to write a wrapper architecture for your design with the original generics, and instance your gate level design inside that wrapper. Of course there will be a certain amount of manual faffing to keep the values of the generic in sync, regards Alan -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:26 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c20g2000vbv.googlegroups.com!not-for-mail From: alivingstone Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map Date: Tue, 14 Jun 2011 14:23:21 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <87cbde7e-7bbe-432d-bc46-3743b649f08e@c20g2000vbv.googlegroups.com> References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 20.132.68.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308086602 3237 127.0.0.1 (14 Jun 2011 21:23:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Jun 2011 21:23:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000vbv.googlegroups.com; posting-host=20.132.68.147; posting-account=DxCl9goAAADG_waculUDLRA24J16aofl User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UHALRCNK X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5052 On Jun 13, 3:38=A0pm, KJ wrote: > On Jun 13, 11:49=A0am, alivingstone wrote: > > > I think this may be a common problem for the pros out there... > KJ- That sounds do-able. Is there a slick way to pass the testbench an argument so that it can generate the correct simulation without having to manually update the file? -Abel > > Pre-synthesis simulation works great, but post-synthesis or post-route = simulations crash because the testbench is trying to map generics to a synt= hesized component with no generics. This must come up often -- is there a s= tandard strategy for this? Configuration > > To do this you need to compile and produce a post route simulation > file for each and every set of generics that you would like to > simulate. =A0In your case, for each specific combination of HPIXELS, > VPIXELS and PIXDEPTH that you want to simulate you need to do a new > build that has that specific setting and then repeat that process for > each set of settings. =A0Then in the testbench you'll need to select > (via a generate statement) which specific post-route simulation you > want to instantiate. > > Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:26 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r20g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map Date: Tue, 14 Jun 2011 20:37:50 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <252018ef-b8fa-4fd1-9bdb-21239ed77d10@r20g2000yqd.googlegroups.com> References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> <87cbde7e-7bbe-432d-bc46-3743b649f08e@c20g2000vbv.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308109072 3434 127.0.0.1 (15 Jun 2011 03:37:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Jun 2011 03:37:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r20g2000yqd.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB7.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5053 On Jun 14, 5:23=A0pm, alivingstone wrote: > On Jun 13, 3:38=A0pm, KJ wrote:> On Jun 13, 11= :49=A0am, alivingstone wrote: > > > > I think this may be a common problem for the pros out there... > > KJ- > > That sounds do-able. Is there a slick way to pass the testbench an > argument so that it can generate the correct simulation without having > to manually update the file? > Simulators will let you set top level generics. If you're using Modelsim, then start it up and type 'vsim' . That will display a dialog box that (among other things) lets you specify top level generics. If you consider that slick, then use that method. If not, then after you have the generics set up in the dialog box, hit return and the resulting command line will be echoed into the transcript window and the simulator will be started. Copy and paste that command into whatever form you would consider to be slick. KJ From newsfish@newsfish Tue Aug 9 07:53:26 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!dn9g2000vbb.googlegroups.com!not-for-mail From: alivingstone Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map Date: Wed, 15 Jun 2011 06:14:22 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> <87cbde7e-7bbe-432d-bc46-3743b649f08e@c20g2000vbv.googlegroups.com> <252018ef-b8fa-4fd1-9bdb-21239ed77d10@r20g2000yqd.googlegroups.com> NNTP-Posting-Host: 20.132.68.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308143662 28049 127.0.0.1 (15 Jun 2011 13:14:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Jun 2011 13:14:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dn9g2000vbb.googlegroups.com; posting-host=20.132.68.147; posting-account=DxCl9goAAADG_waculUDLRA24J16aofl User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UHALRCNK X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5054 On Jun 14, 11:37=A0pm, KJ wrote: > On Jun 14, 5:23=A0pm, alivingstone wrote: > > > On Jun 13, 3:38=A0pm, KJ wrote:> On Jun 13, = 11:49=A0am, alivingstone wrote: > > > > > I think this may be a common problem for the pros out there... > > > KJ- > > > That sounds do-able. Is there a slick way to pass the testbench an > > argument so that it can generate the correct simulation without having Thanks KJ. Looks like I can set a generic string "SimType" and just send in the desired simulation type using the -g or -G switch in vsim. > > to manually update the file? > > Simulators will let you set top level generics. =A0If you're using > Modelsim, then start it up and type 'vsim' . =A0That will display > a dialog box that (among other things) lets you specify top level > generics. =A0If you consider that slick, then use that method. > > If not, then after you have the generics set up in the dialog box, hit > return and the resulting command line will be echoed into the > transcript window and the simulator will be started. =A0Copy and paste > that command into whatever form you would consider to be slick. > > KJ From newsfish@newsfish Tue Aug 9 07:53:26 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!34g2000pru.googlegroups.com!not-for-mail From: debolina Newsgroups: comp.lang.vhdl Subject: implement Expectation maximization algo in vhdl Date: Thu, 16 Jun 2011 08:22:11 -0700 (PDT) Organization: http://groups.google.com Lines: 2 Message-ID: <5bb24523-678a-415a-8cea-2d832d31a43b@34g2000pru.googlegroups.com> NNTP-Posting-Host: 117.194.2.73 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308237731 2458 127.0.0.1 (16 Jun 2011 15:22:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Jun 2011 15:22:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 34g2000pru.googlegroups.com; posting-host=117.194.2.73; posting-account=m1ToDQoAAABiI3QkpepQ20GRKPZxNno2 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110420 AskTbFXTV5/3.12.2.16749 Firefox/3.6.17,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5055 can anybody help me giving me the idea about implementation of EM algo in vhdl?plz reply From newsfish@newsfish Tue Aug 9 07:53:26 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a10g2000vbz.googlegroups.com!not-for-mail From: Gerhard Newsgroups: comp.lang.vhdl Subject: one signal set ffrom two processes ..... Date: Fri, 17 Jun 2011 03:05:28 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> NNTP-Posting-Host: 62.99.175.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308305210 28555 127.0.0.1 (17 Jun 2011 10:06:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Jun 2011 10:06:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a10g2000vbz.googlegroups.com; posting-host=62.99.175.233; posting-account=N_oVwQoAAAAVT5wpiHpHxQ3LYp9caoKS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; chromeframe/12.0.742.100; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; .NET CLR 1.1.4322; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; FDM; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5056 Hi, newbe needs help. My problem: I have a Moor state machine sitting around and waiting. After a falling edge on a port the state machine needs to start out working, which take about 96 clock cycles. the work mainly is clocking data in from a spi interface. After that the state machine wents sleeping again. I try to create a signal (later a variable) and set it in a process which monitors the start signal. The state machine consists of three processes (synced Moor state machine) and monitors my start signal (which is like a reset if not active) and starts out working on the next clock transition. After finishing the work, I try to reset my start signal, after entering the neutral state (sleeping), but .. I always get compiler errors, telling me that the net 'start' is constantely driven from different places .... Please tell me, how i should solve such an scenario in VHDL .... Thinking in 'plain hardware'. I need a FF, which is set by a port signal and some edge of the clock and is reset by some condition .... Sounds quite easy in hardware, but seems not so easy to implement in VHDL for a rouky... Thanks for helping. With best regards gerhard Here some snippets: nDRdy_sync: process begin wait until falling_edge(nDRDY); transfer := '1'; end process; some other: process (mySCLK) begin ... ... transfer := '0'; end process; From newsfish@newsfish Tue Aug 9 07:53:27 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Fri, 17 Jun 2011 11:29:53 +0000 (UTC) Organization: A noiseless patient Spider Lines: 84 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 17 Jun 2011 11:29:53 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="yJp5FpId2jBgPu981SiaiA"; logging-data="21438"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GIytSs65aN63uutTqN+f4X1qThtapuXA=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:HgUuIxaMhKyU0h8pG3nkk/z8DnY= Xref: feeder.eternal-september.org comp.lang.vhdl:5057 On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: > Hi, > > newbe needs help. > > My problem: > I always get compiler errors, telling me that the net 'start' is > constantely driven from different places .... That is a very bad design pattern. There are ways to make it work, but it's unnecessary here. > Please tell me, how i should solve such an scenario in VHDL .... Drive "start" from one single process. The state machine can feed a second signal ("started", or "finished") back to that process to let it know when it is safe to return "start" to zero. > Thinking in 'plain hardware'. I need a FF, which is set by a port signal > and some edge of the clock and is reset by some condition .... > Here some snippets: > > nDRdy_sync: > process > begin > wait until falling_edge(nDRDY); > --transfer := '1'; -- "transfer" should be a signal. -- A variable local to the process is OK but invisible outside the process -- A "shared variable" is likely to cause problems and best avoided. transfer <= '1'; wait until active; -- a signal of type boolean transfer <= '0'; > end process; > > some other: > process (mySCLK) > begin > ... > ... > -- transfer := '0'; active <= true; ... -- now the state machine has returned to idle active <= false; > end process; Incidentally the first of these processes will probably not synthesise into an FPGA. You would be better off adopting synchronous design using one internal clock, for example: nDRdy_sync: process(clk) variable idle: boolean := true; begin if rising_edge(clk) then if idle then if nDRDY = '0' then idle := false; transfer <= '1'; end if; else if active then transfer <= '0'; idle := true; end if; end if; end if; end process; You will also simplify your state machine if you transform the obsolete three-process style into the equivalent single-process state machine. The archives of this group cover state machines on a regular basis. See also http://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html and some of Mike Treseler's examples on http://mysite.ncnetwork.net/reszotzl/ - Brian From newsfish@newsfish Tue Aug 9 07:53:27 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!eq2g2000vbb.googlegroups.com!not-for-mail From: Gerhard Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Fri, 17 Jun 2011 07:06:50 -0700 (PDT) Organization: http://groups.google.com Lines: 119 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> NNTP-Posting-Host: 62.99.175.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308319720 11987 127.0.0.1 (17 Jun 2011 14:08:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Jun 2011 14:08:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: eq2g2000vbb.googlegroups.com; posting-host=62.99.175.233; posting-account=N_oVwQoAAAAVT5wpiHpHxQ3LYp9caoKS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; chromeframe/12.0.742.100; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; .NET CLR 1.1.4322; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; FDM; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5058 On Jun 17, 1:29=A0pm, Brian Drummond wrote: > On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: > > Hi, > > > newbe needs help. > > > My problem: > > I always get compiler errors, telling me that the net 'start' is > > constantely driven from different places .... > > That is a very bad design pattern. There are ways to make it work, but > it's unnecessary here. > > > Please tell me, how i should solve such an scenario in VHDL .... > > Drive "start" from one single process. > > The state machine can feed a second signal ("started", or "finished") > back to that process to let it know when it is safe to return "start" to > zero. > > > Thinking in 'plain hardware'. I need a FF, which is set by a port signa= l > > and some edge of the clock and is reset by some condition .... > > Here some snippets: > > > nDRdy_sync: > > =A0 =A0 =A0 process > > =A0 =A0 =A0 =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0 wait until falling_edge(nDRDY); > > =A0 =A0 =A0 =A0 =A0 =A0 --transfer :=3D '1'; > > -- "transfer" should be a signal. > -- A variable local to the process is OK but invisible outside the proces= s > -- A "shared variable" is likely to cause problems and best avoided. > =A0 =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait until active; =A0 =A0 =A0 =A0-- a signal= of type boolean > =A0 =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '0';> =A0 =A0 =A0 =A0 =A0end pr= ocess; > > > some other: > > =A0 =A0 =A0 process (mySCLK) > > =A0 =A0 =A0 =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0 ... > > =A0 =A0 =A0 =A0 =A0 =A0 ... > > =A0 =A0 =A0 =A0 =A0 =A0 -- transfer :=3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 active <=3D true; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 ... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- now the state machine has returned to idle > =A0 =A0 =A0 =A0 =A0 =A0 =A0 active <=3D false; > > > =A0 =A0 =A0 =A0 =A0end process; > > Incidentally the first of these processes will probably not synthesise > into an FPGA. You would be better off adopting synchronous design using > one internal clock, for example: > > nDRdy_sync: process(clk) > variable idle: boolean :=3D true; > begin > =A0 =A0if rising_edge(clk) then > =A0 =A0 =A0 if idle then > =A0 =A0 =A0 =A0 =A0if nDRDY =3D '0' then > =A0 =A0 =A0 =A0 =A0 =A0 idle :=3D false; > =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '1'; > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0if active then > =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 idle :=3D true; > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0 =A0 end if; > =A0 =A0end if; > end process; > > You will also simplify your state machine if you transform the obsolete > three-process style into the equivalent single-process state machine. The > archives of this group cover state machines on a regular basis. > > See alsohttp://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html > and some of Mike Treseler's examples onhttp://mysite.ncnetwork.net/reszot= zl/ > > - Brian ??? I get the book VHDL-synthese by J=FCrgen Reichardt and Bernd Schwarz, which discuss a three process, two process and one process approach, so I try the first one, because its more clear for the beginning and fully synchronized. Speed isn't an issue here. Ah, I should implement some kind of hand-shaking, one process rise start and waiting for some reply. The other process generate 'stopped' after the work is done and the first process clears the start signal. But, when the state machine enters the idle state and the start signal is still present ..... ok, my state machine runs through some sequential states so I can drop the 'stopped' info earlier, but code will be not very clear ... Strange idea, but syntactically there is a chance of working. Problem is, that the start signal is async (came from another chip, running on another clock, no chance to change that) and is only held active as long as I start reading data via SPI. So I have to sync and I have to stretch this puls until the state machine is done or I have to make changes so the state machine doesnt need a permanent signal for running. Thanks a lot With best regards Gerhard From newsfish@newsfish Tue Aug 9 07:53:27 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 17 Jun 2011 11:16:17 -0500 Date: Fri, 17 Jun 2011 09:16:19 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> In-Reply-To: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 14 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-e6I59GHh8oOqqiR4qYxKpXQT5cEf14e0GjugGsRMuAgh7hi5j1QOIU6DcEC66cjcWiJOxs7O+n7oLNx!HMWAWAntZwNsfhKCPnRfxiPaTfU+QDZ85i90mDiNLpnfYZIkKQa4/xO7jz+1mpjwNn9T74iyZM2V!Ng== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1493 Xref: feeder.eternal-september.org comp.lang.vhdl:5059 On 6/17/2011 3:05 AM, Gerhard wrote: > Hi, > > newbe needs help. > > My problem: > I have a Moor state machine sitting around and waiting. > Gerhard seems to be working on the Othello exercise. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Tue Aug 9 07:53:27 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!news.albasani.net!newsfeed1.swip.net!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 17 Jun 2011 11:37:48 -0500 Date: Fri, 17 Jun 2011 09:37:50 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 142 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-pwLiBRlQvQ63D3l/NC6Vk+CjassQcJqjwOy6LjHAJ2eV1PjgNDJeFUVdv6onSCdlpmG2YmIceYI2SgH!pleBETG5t9Mxdz6uGbNPdXu9OUiU36avTa716i0danqxuS1eZwCL6CUFeu+rdEyfcVBM23wQgK6W!+Q== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 6759 Xref: feeder.eternal-september.org comp.lang.vhdl:5060 On 6/17/2011 7:06 AM, Gerhard wrote: > On Jun 17, 1:29 pm, Brian Drummond wrote: >> On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: >>> Hi, >> >>> newbe needs help. >> >>> My problem: >>> I always get compiler errors, telling me that the net 'start' is >>> constantely driven from different places .... >> >> That is a very bad design pattern. There are ways to make it work, but >> it's unnecessary here. >> >>> Please tell me, how i should solve such an scenario in VHDL .... >> >> Drive "start" from one single process. >> >> The state machine can feed a second signal ("started", or "finished") >> back to that process to let it know when it is safe to return "start" to >> zero. >> >>> Thinking in 'plain hardware'. I need a FF, which is set by a port signal >>> and some edge of the clock and is reset by some condition .... >>> Here some snippets: >> >>> nDRdy_sync: >>> process >>> begin >>> wait until falling_edge(nDRDY); >>> --transfer := '1'; >> >> -- "transfer" should be a signal. >> -- A variable local to the process is OK but invisible outside the process >> -- A "shared variable" is likely to cause problems and best avoided. >> transfer<= '1'; >> wait until active; -- a signal of type boolean >> transfer<= '0';> end process; >> >>> some other: >>> process (mySCLK) >>> begin >>> ... >>> ... >>> -- transfer := '0'; >> >> active<= true; >> ... >> -- now the state machine has returned to idle >> active<= false; >> >>> end process; >> >> Incidentally the first of these processes will probably not synthesise >> into an FPGA. You would be better off adopting synchronous design using >> one internal clock, for example: >> >> nDRdy_sync: process(clk) >> variable idle: boolean := true; >> begin >> if rising_edge(clk) then >> if idle then >> if nDRDY = '0' then >> idle := false; >> transfer<= '1'; >> end if; >> else >> if active then >> transfer<= '0'; >> idle := true; >> end if; >> end if; >> end if; >> end process; >> >> You will also simplify your state machine if you transform the obsolete >> three-process style into the equivalent single-process state machine. The >> archives of this group cover state machines on a regular basis. >> >> See alsohttp://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html >> and some of Mike Treseler's examples onhttp://mysite.ncnetwork.net/reszotzl/ >> >> - Brian > > > > ??? > I get the book VHDL-synthese by Jürgen Reichardt and Bernd Schwarz, > which discuss a three process, two process and one process approach, > so I try the first one, because its more clear for the beginning and > fully synchronized. Speed isn't an issue here. > > Ah, I should implement some kind of hand-shaking, one process rise > start and waiting for some reply. The other process generate 'stopped' > after the work is done and the first process clears the start signal. > > But, when the state machine enters the idle state and the start signal > is still present ..... > ok, my state machine runs through some sequential states so I can drop > the 'stopped' info earlier, but code will be not very clear ... > > Strange idea, but syntactically there is a chance of working. > > Problem is, that the start signal is async (came from another chip, > running on another clock, no chance to change that) and is only held > active as long as I start reading data via SPI. > So I have to sync and I have to stretch this puls until the state > machine is done or I have to make changes so the state machine doesnt > need a permanent signal for running. > > Thanks a lot > > With best regards > > Gerhard The advantage of the single process state machine is that it works out being cleaner, and really forces the entire thing to be purely synchronous. You're starting to talk about handshaking between multiple processes in order to get a simple state machine working. That's making the logic more and more complex; you want to move in the direction of simple. I don't know how long "as long as I start reading data" is, but the usual way to deal with an asynchronous signal is to re-clock it through a two-flop long shift register. You want to always deal with asynchronous signals at a single point of entry, such as one flip-flop. The moment you've got multiple different logical paths looking at that signal, as you will in most state machine implementations, you've buried yourself in race conditions. Once you've got your resynchronized signal, I'd say to change the state machine to not need a permanent signal. That can actually be encoded as one of the states of the machine; you spend much of your time in an IDLE state, hanging out waiting for the input signal to drop. Signal drops, you transition to other states that do things, and at the end wind up back in IDLE. I can actually think of very few state machines I've written that don't operate on that principle. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Tue Aug 9 07:53:27 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Fri, 17 Jun 2011 19:15:23 +0000 (UTC) Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 17 Jun 2011 19:15:23 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="yJp5FpId2jBgPu981SiaiA"; logging-data="28111"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/zNBt7x6Mz9OdCLDL7QsBh604DdhSzBPw=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:I9HbSdqb6obejwYOikpAJW7Wy44= Xref: feeder.eternal-september.org comp.lang.vhdl:5061 On Fri, 17 Jun 2011 07:06:50 -0700, Gerhard wrote: > On Jun 17, 1:29 pm, Brian Drummond wrote: >> On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: >> >> > Please tell me, how i should solve such an scenario in VHDL .... >> >> Drive "start" from one single process. >> You will also simplify your state machine if you transform the obsolete >> three-process style into the equivalent single-process state machine. >> The archives of this group cover state machines on a regular basis. > ??? > I get the book VHDL-synthese by Jürgen Reichardt and Bernd Schwarz, > which discuss a three process, two process and one process approach, so > I try the first one, because its more clear for the beginning and fully > synchronized. Speed isn't an issue here. All three will work, and should generate identical hardware. But the single-process variant is generally easier to get right, and easier to maintain. > Ah, I should implement some kind of hand-shaking, one process rise start > and waiting for some reply. The other process generate 'stopped' after > the work is done and the first process clears the start signal. YES, exactly. > But, when the state machine enters the idle state and the start signal > is still present ..... then it would re-trigger. If the start signal is of indeterminate length, the SM should be designed to wait for start to be retracted before entering idle. (the "transfer" signal in my example should be maintained until n_RDY -> '1') > Problem is, that the start signal is async (came from another chip, > running on another clock, no chance to change that) and is only held > active as long as I start reading data via SPI. So I have to sync and I > have to stretch this puls until the state machine is done or I have to > make changes so the state machine doesnt need a permanent signal for > running. I think you have an understanding of the remaining issues. - Brian From newsfish@newsfish Tue Aug 9 07:53:27 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u30g2000vby.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Mon, 20 Jun 2011 15:46:03 -0700 (PDT) Organization: http://groups.google.com Lines: 158 Message-ID: <5606c1b2-9edc-41bd-ac66-1c76b0dcc9bb@u30g2000vby.googlegroups.com> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> NNTP-Posting-Host: 70.109.95.41 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308610785 13855 127.0.0.1 (20 Jun 2011 22:59:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Jun 2011 22:59:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u30g2000vby.googlegroups.com; posting-host=70.109.95.41; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5062 On Jun 17, 10:06=A0am, Gerhard wrote: > On Jun 17, 1:29=A0pm, Brian Drummond wrote: > > > > > > > > > > > On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: > > > Hi, > > > > newbe needs help. > > > > My problem: > > > I always get compiler errors, telling me that the net 'start' is > > > constantely driven from different places .... > > > That is a very bad design pattern. There are ways to make it work, but > > it's unnecessary here. > > > > Please tell me, how i should solve such an scenario in VHDL .... > > > Drive "start" from one single process. > > > The state machine can feed a second signal ("started", or "finished") > > back to that process to let it know when it is safe to return "start" t= o > > zero. > > > > Thinking in 'plain hardware'. I need a FF, which is set by a port sig= nal > > > and some edge of the clock and is reset by some condition .... > > > Here some snippets: > > > > nDRdy_sync: > > > =A0 =A0 =A0 process > > > =A0 =A0 =A0 =A0 =A0begin > > > =A0 =A0 =A0 =A0 =A0 =A0 wait until falling_edge(nDRDY); > > > =A0 =A0 =A0 =A0 =A0 =A0 --transfer :=3D '1'; > > > -- "transfer" should be a signal. > > -- A variable local to the process is OK but invisible outside the proc= ess > > -- A "shared variable" is likely to cause problems and best avoided. > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '1'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait until active; =A0 =A0 =A0 =A0-- a sign= al of type boolean > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '0';> =A0 =A0 =A0 =A0 =A0end = process; > > > > some other: > > > =A0 =A0 =A0 process (mySCLK) > > > =A0 =A0 =A0 =A0 =A0begin > > > =A0 =A0 =A0 =A0 =A0 =A0 ... > > > =A0 =A0 =A0 =A0 =A0 =A0 ... > > > =A0 =A0 =A0 =A0 =A0 =A0 -- transfer :=3D '0'; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 active <=3D true; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 ... > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- now the state machine has returned to id= le > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 active <=3D false; > > > > =A0 =A0 =A0 =A0 =A0end process; > > > Incidentally the first of these processes will probably not synthesise > > into an FPGA. You would be better off adopting synchronous design using > > one internal clock, for example: > > > nDRdy_sync: process(clk) > > variable idle: boolean :=3D true; > > begin > > =A0 =A0if rising_edge(clk) then > > =A0 =A0 =A0 if idle then > > =A0 =A0 =A0 =A0 =A0if nDRDY =3D '0' then > > =A0 =A0 =A0 =A0 =A0 =A0 idle :=3D false; > > =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '1'; > > =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 =A0if active then > > =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 idle :=3D true; > > =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 end if; > > =A0 =A0end if; > > end process; > > > You will also simplify your state machine if you transform the obsolete > > three-process style into the equivalent single-process state machine. T= he > > archives of this group cover state machines on a regular basis. > > > See alsohttp://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html > > and some of Mike Treseler's examples onhttp://mysite.ncnetwork.net/resz= otzl/ > > > - Brian > > ??? > I get the book VHDL-synthese by J=FCrgen Reichardt and Bernd Schwarz, > which discuss a three process, two process and one process approach, > so I try the first one, because its more clear for the beginning and > fully synchronized. Speed isn't an issue here. > > Ah, I should implement some kind of hand-shaking, one process rise > start and waiting for some reply. The other process generate 'stopped' > after the work is done and the first process clears the start signal. > > But, when the state machine enters the idle state and the start signal > is still present ..... > ok, my state machine runs through some sequential states so I can drop > the 'stopped' info earlier, but code will be not very clear ... > > Strange idea, but syntactically there is a chance of working. > > Problem is, that the start signal is async (came from another chip, > running on another clock, no chance to change that) and is only held > active as long as I start reading data via SPI. > So I have to sync and I have to stretch this puls until the state > machine is done or I have to make changes so the state machine doesnt > need a permanent signal for running. Can you explain what makes the start signal go away? You mkae it sound like accessing the SPI port makes it go away which would be perfect if I understand your problem. But you say that your Finite State Machine (FSM) reads the SPI port, finishes and the start signal is still active. So something is not right with my understanding. If the start signal is asserted and cleared independently of your FSM then you need to design your machine to detect the assertion, not the fact that it is asserted. When the FSM gets to the end of its work, the start signal needs to be cleared before the FSM will trigger again, in other words, enter a state where you wait for Start to be false before you enter the state where it waits for Start to be true. If the Start signal can be cleared by the FSM, then do that before entering the state where it waits for the Start signal to be true. That is pretty simple, no? I can't say I understand your last part about stretching the Start signal. It only needs to be true long enough for the FSM to see that it is asserted. As long as that is two clock cycles, it is guaranteed to be seen. Then you only need to see it cleared before you return to the starting state waiting for Start to be true. Have you somehow written your code so that if Start goes away the FSM resets? That would be very bad and should be changed. One other thought, the code you give that seems to be waiting for nDRDY it treating nDRDY as a clock. Probably not a good idea unless nDRDY is not guaranteed to be at least two clock cycles long. Rick From newsfish@newsfish Tue Aug 9 07:53:28 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g12g2000yqd.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: VHDL signal sources problem Date: Tue, 21 Jun 2011 05:23:33 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> NNTP-Posting-Host: 62.121.39.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308659128 3020 127.0.0.1 (21 Jun 2011 12:25:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Jun 2011 12:25:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g12g2000yqd.googlegroups.com; posting-host=62.121.39.162; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5063 Hi, I don't understand why the following code won't elaborate. The compiler thinks that v(7 downto 4) is driven by both processes. But process "a" definitely doesn't touch it. Tested with GHDL and Active HDL. Ideas appreciated ... - Topi ***************** library ieee; use ieee.std_logic_1164.all; entity process_for_tester is end; architecture test of process_for_tester is signal v: std_ulogic_vector(7 downto 0); signal i: integer; begin a: process(i) variable n: integer; begin for n in 0 to 3 loop if i mod 2 = 0 then v(n) <= '1'; else v(n) <= '0'; end if; end loop; end process; b: process begin v(7 downto 4) <= "0101"; wait; end process; process begin i <= 0; wait for 1 us; loop i <= i + 1; wait for 1 us; end loop; end process; end; From newsfish@newsfish Tue Aug 9 07:53:28 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!not-for-mail From: Benjamin Krill Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem Date: Tue, 21 Jun 2011 16:10:53 +0200 Lines: 28 Message-ID: <1308665454.22729.1.camel@bne> References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Trace: news.uni-berlin.de fctEbyDg6qZ+k0bfl4/HGQ4VcOLNfxSHQj49FBPIUJC4PxcSI= In-Reply-To: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> X-Mailer: Evolution 3.0.2 (3.0.2-2.fc15) Xref: feeder.eternal-september.org comp.lang.vhdl:5064 Hi, On Tue, 2011-06-21 at 05:23 -0700, Topi wrote: > Hi, >=20 > I don't understand why the following code won't elaborate. >=20 > The compiler thinks that v(7 downto 4) is driven by both processes. > But process "a" definitely doesn't touch it. It does touch v ... > a: process(i) > variable n: integer; > begin > for n in 0 to 3 loop > if i mod 2 =3D 0 then > v(n) <=3D '1'; ^^^^^^^^^^ here > else > v(n) <=3D '0'; ^^^^^^^^^^ here > end if; > end loop; > end process; ben From newsfish@newsfish Tue Aug 9 07:53:28 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.x-privat.org!itgate.net!tornado.fastwebnet.it!53ab2750!not-for-mail From: DavCori80 User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: [OT] One click, one (buggy) life... Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 13 Message-ID: Date: Tue, 21 Jun 2011 16:47:48 +0200 NNTP-Posting-Host: 28.21.170.74 X-Complaints-To: newsmaster@fastweb.it X-Trace: tornado.fastwebnet.it 1308667669 28.21.170.74 (Tue, 21 Jun 2011 16:47:49 CEST) NNTP-Posting-Date: Tue, 21 Jun 2011 16:47:49 CEST Xref: feeder.eternal-september.org comp.lang.vhdl:5065 Hi everyone, I would like to share a youtube clip...one click costs nothing while can save lives sometimes (especially mine). http://www.youtube.com/watch?v=PiCeqtGHpJI Thanks a lot and cheers. DavCori http://www.ar4tro.com From newsfish@newsfish Tue Aug 9 07:53:28 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem Date: Tue, 21 Jun 2011 16:25:35 +0100 Organization: A noiseless patient Spider Lines: 68 Message-ID: References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> <1308665454.22729.1.camel@bne> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="23194"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+uiIpMBHJuQZbC+CxKBZ08P/XlMiU7ge0=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:IPU0AaA7cDNHOKMgg3H5XQIWzGM= Xref: feeder.eternal-september.org comp.lang.vhdl:5066 On Tue, 21 Jun 2011 16:10:53 +0200, Benjamin Krill wrote: >On Tue, 2011-06-21 at 05:23 -0700, Topi wrote: >> Hi, >> >> I don't understand why the following code won't elaborate. >> >> The compiler thinks that v(7 downto 4) is driven by both processes. >> But process "a" definitely doesn't touch it. > >It does touch v ... > >> a: process(i) >> variable n: integer; >> begin >> for n in 0 to 3 loop >> if i mod 2 = 0 then >> v(n) <= '1'; > ^^^^^^^^^^ here >> else >> v(n) <= '0'; > ^^^^^^^^^^ here >> end if; >> end loop; >> end process; Ben is completely correct, but the reason is not at all obvious. It's clear that "n" is statically restricted to be only 0 to 3. However, this isn't enough. The 'for' loop is dynamically elaborated, even though its loop range is in fact static. So the assignment target v(n) has simply "v" as its longest static prefix. Consequently, the process drives all eight bits of v. Since bits (7 downto 4) are never updated, they are permanently driven with 'U'. Because v's type is std_ulogic_vector, the multiple drivers are illegal. If v were a std_logic_vector, the multiple drivers would be resolved and you would see an unchanging 'U' value on v(7 downto 4). The solution is to construct two signals and mux them together. You could use a for-loop to do that: signal p,q,v: std_ulogic_vector(7 downto 0); choose_bits: process(...) begin for i in v'range loop if i>BOUNDARY then v(i) <= p(i); else v(i) <= q(i); end if; end loop; end process; Or something like that. BOUNDARY is a generic or constant indicating where in the vector you should switch over from p to q. By the way, your declaration of n as an integer is redundant and inappropriate. The "loop counter" in a for-loop is implicitly declared, and exists only in the scope of the loop. From newsfish@newsfish Tue Aug 9 07:53:28 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Tue, 21 Jun 2011 11:11:40 -0500 Date: Tue, 21 Jun 2011 09:11:42 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> <1308665454.22729.1.camel@bne> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 13 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-ucYNWq+j1inz3YIH9b8drWeyAwF6GYuinPoLQxMpvEwzkSxSkEuiQm8CYX0Lh2rC0LZxFXYGfxBLd6j!z4wiM+urwAovmKJy4zqjDF6ctkXSR13udxrQsmYNTFV9Q5gI4fpicBqlPUIC+dS0My7jinjVLRkt!hQ== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1713 Xref: feeder.eternal-september.org comp.lang.vhdl:5067 On 6/21/2011 8:25 AM, Jonathan Bromley wrote: > [snip] > By the way, your declaration of n as an integer > is redundant and inappropriate. The "loop counter" > in a for-loop is implicitly declared, and exists > only in the scope of the loop. Huh. I've been using them for years, happily declaring them as variables, and never knew that. You learn something new every day. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Tue Aug 9 07:53:28 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!16g2000yqy.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem Date: Tue, 21 Jun 2011 11:39:23 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <5a16daef-bb11-41d0-9ed8-2e385ba340ee@16g2000yqy.googlegroups.com> References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> <1308665454.22729.1.camel@bne> NNTP-Posting-Host: 62.121.39.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308681563 30538 127.0.0.1 (21 Jun 2011 18:39:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Jun 2011 18:39:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 16g2000yqy.googlegroups.com; posting-host=62.121.39.162; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5068 On Jun 21, 6:25=A0pm, Jonathan Bromley wrote: > It's clear that "n" is statically restricted to be > only 0 to 3. =A0However, this isn't enough. =A0The 'for' > loop is dynamically elaborated, even though its loop > range is in fact static. =A0So the assignment target > v(n) has simply "v" as its longest static prefix. Thanks, got it. I managed to change it to for-generate and if-generate structure: http://vhdlmodels.blogspot.com/2011/06/registers-getting-even-better.html - Topi From newsfish@newsfish Tue Aug 9 07:53:29 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: catherine saranya Newsgroups: comp.lang.vhdl Subject: Re: 10bit Calculator design help me! Date: Thu, 23 Jun 2011 07:52:27 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <992e4187-8e19-4a41-bec4-62f84969caff@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 106.51.35.99 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308841642 19149 127.0.0.1 (23 Jun 2011 15:07:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Jun 2011 15:07:22 +0000 (UTC) In-Reply-To: <91atk6$fi5$1@news1-2.kornet.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=106.51.35.99; posting-account=PUIYRAoAAAB5kDjG4MqOzlyeOv9saSkp User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5069 Hey simon, did you manage to get the code for this? I really need it too- if u do have it can u post it on the forum. Thanks From newsfish@newsfish Tue Aug 9 07:53:29 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!h12g2000pro.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Enumerated integer type Date: Fri, 24 Jun 2011 09:24:45 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: NNTP-Posting-Host: 67.188.14.102 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308932793 7791 127.0.0.1 (24 Jun 2011 16:26:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Jun 2011 16:26:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h12g2000pro.googlegroups.com; posting-host=67.188.14.102; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5070 Hello, I'd like to declare a type like this type mytype is (-1,1); However, it appears that enumerated types aren't allowed to be integers. Is there a way to create an integer subtype where the values of the type are constrained to certain hand-picked values, rather than a range? The workaround for this is to use std_logic and convert it to signed when you need to, but it seems an integer subtype would work better. Colin From newsfish@newsfish Tue Aug 9 07:53:29 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!cs.uu.nl!weretis.net!feeder1.news.weretis.net!feeder.erje.net!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 24 Jun 2011 13:54:00 -0500 Date: Fri, 24 Jun 2011 19:54:00 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Enumerated integer type References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 33 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-o0MTnpb5k6a3SJISow8c26hnDwLfO5Jglofj9XIj1pRoZsrI8cT5uPjwDj6ti+mYgoG6CBQY2tJcNxx!EpjW9gsBBeYjrf9Fo/Nn8JxYiBCzxom6BlBfXa/6hvk8hl/98zjql/c1oeeKaesyMAx6XDvINs/q!cjLgtP4Vsgc6T1tg8PqPhIypCr4= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2042 Xref: feeder.eternal-september.org comp.lang.vhdl:5071 On 24/06/11 17:24, Colin Beighley wrote: > Hello, > > I'd like to declare a type like this > > type mytype is (-1,1); > > However, it appears that enumerated types aren't allowed to be > integers. > > Is there a way to create an integer subtype where the values of the > type are constrained to certain hand-picked values, rather than a > range? The workaround for this is to use std_logic and convert it to > signed when you need to, but it seems an integer subtype would work > better. > > Colin Enumerated types can be a mixture of character literals and identifiers. What you probably want is an integer subtype, e.g. subtype mytype is integer range -1 to 1; Because this is a subtype of integer, it can be assigned to and from integers and other integer subtypes. regards Alan -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:29 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!feeder.news-service.com!postnews.google.com!gc3g2000vbb.googlegroups.com!not-for-mail From: MJB Newsgroups: comp.lang.vhdl Subject: Re: simulation script Date: Fri, 24 Jun 2011 12:57:58 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: <1e07ed24-bd63-43c3-a036-2a73a41f291d@gc3g2000vbb.googlegroups.com> References: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> <97a9f4db-e769-4376-906e-8aa8c45de3f2@l14g2000pro.googlegroups.com> NNTP-Posting-Host: 199.46.200.231 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308945478 3416 127.0.0.1 (24 Jun 2011 19:57:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Jun 2011 19:57:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: gc3g2000vbb.googlegroups.com; posting-host=199.46.200.231; posting-account=XsPsLQoAAABg05Q6wOj-nB1nqE0qsC-B User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRU X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5072 On Jun 9, 12:45=A0am, HT-Lab wrote: > On 08/06/2011 18:00, JohnSmith wrote: > > > > > > > > > On Jun 8, 6:45 pm, MJB =A0wrote: > >> On Jun 8, 9:32 am, JohnSmith =A0wrote: > > >>> Hi, > > >>> How can I use an environment variable in a ".do" script running it in > >>> the modelsim window? > > >>> I tried the windows environment variable in % characters, but doesnt > >>> work. Absolute paths work but I want use this scripts on different > >>> computers. > > >>> vsim -sdftyp {/UUT=3D%MYDIR%/dir/.../timesim.sdf} ... > > >>> Thanks > > >> Try using the Tcl env() function. =A0Modelsim's shell is essentially a > >> Tcl command line evironment and the .do files are .tcl scripts. > > >> to get your directory, try /UUT=3Denv(MYDIR)/ ..... > > >> I don't have a Modelsim installation handy so this is just off the top > >> of my head. =A0Hope you find the solution! > > > Doesnt work.. > > MJB forgot the variable sign, > > vsim -sdftyp /UUT=3D$env(MYDIR)... > > Hanswww.ht-lab.com Thanks for the correction! :) From newsfish@newsfish Tue Aug 9 07:53:29 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Sat, 25 Jun 2011 10:30:17 -0700 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Injection-Date: Sat, 25 Jun 2011 17:31:38 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="29804"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/qEzb4fvKnyuCYcgXMCYmvy5PCrVCpkKo=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:Q3mYLF905J7ArO3nllPRIR4XkaE= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5073 I looks to me like you need something like this. Here is a basic single-process state machine with a synchronized start pulse. Input signal nDRDY is first synchronized to the state machine clock. When nDRDY makes a 1 -> 0 transition, you will get a 1-clock cycle pulse on start. This starts the state machine going through its steps. When done, it goes back to the IDLE state to wait for another start pulse. TYPE states is (IDLE, S1, S2, S3, S4); SIGNAL state : _states; SIGNAL nDRDY_1, nDRDY_2, start : std_logic; start <= NOT nDRDY_1 and nDRDY_2; clk_proc: PROCESS BEGIN WAIT until rising_edge(clk); nDRDY_1 <= nDRDY; nDRDY_2 <= nDRDY_1; CASE state is WHEN IDLE => If start='1' state <= S1; end if; WHEN S1 => -- Do state 1 processing here -- when done: state <= S2; WHEN S2 => -- Do state 2 processing here -- when done: state <= S3; WHEN S3 => -- Do state 3 processing here -- when done: state <= S4; WHEN S4 => -- Do state 4 processing here -- when done: state <= IDLE; -- Add or subtract states as needed END CASE; END PROCESS; Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:29 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: generic circuit for read data from n files Date: Sat, 25 Jun 2011 10:31:41 -0700 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <6ac0bf07-8c41-49ad-bf06-447112861e69@g24g2000vbz.googlegroups.com> Injection-Date: Sat, 25 Jun 2011 17:31:39 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="29804"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19IOAE5OVFJo7uti0pj7hVCvrW8dyLxMN0=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:VwKoon87Md8hE5mHb39jRlt9vOs= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5074 ARQ_MOD probably needs a CLK input so you can sequence through the input file and output data on OUTPUT_DATA one DATA_SIZE chunk per clock cycle. You may also want a DATA_VALID output to indicate that there is valid data on OUTPUT_DATA on any given clock cycle. You can pass the name of the file to be read to ARQ_MOD via a "string" port type. You may also need to pass string length via a "natural" port type to indicate the number of valid characters in the string. Or, always pass a string with trailing blanks and have ARQ_MOD search for a trailing blank to determine the length of the string. Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:30 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem Date: Sat, 25 Jun 2011 10:47:40 -0700 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> Injection-Date: Sat, 25 Jun 2011 17:52:06 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="5377"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19bqSy80Fqtn5mQYyAducUPwtcTWIU4O4g=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:75SamulkDGo+UnOXW0xtFFZ5/uI= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5075 Something like this should work: a: process(i) variable t : std_ulogic_vector(3 downto 0); begin for n in 0 to 3 loop if i mod 2 = 0 then t(n) := '1'; else t(n) := '0'; end if; end loop; v(3 downto 0) <= t; end process; -- And, your "b" process can be boiled down to just v(7 downto 4) <= "0101"; Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:30 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l2g2000prg.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Enumerated integer type Date: Sun, 26 Jun 2011 10:18:58 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: References: NNTP-Posting-Host: 98.234.25.72 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309108738 9588 127.0.0.1 (26 Jun 2011 17:18:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 26 Jun 2011 17:18:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l2g2000prg.googlegroups.com; posting-host=98.234.25.72; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5076 On Jun 24, 11:54=A0am, Alan Fitch wrote: > On 24/06/11 17:24, Colin Beighley wrote: > > > > > > > > > > > Hello, > > > I'd like to declare a type like this > > > type mytype is (-1,1); > > > However, it appears that enumerated types aren't allowed to be > > integers. > > > Is there a way to create an integer subtype where the values of the > > type are constrained to certain hand-picked values, rather than a > > range? The workaround for this is to use std_logic and convert it to > > signed when you need to, but it seems an integer subtype would work > > better. > > > Colin > > Enumerated types can be a mixture of character literals and identifiers. > > What you probably want is an integer subtype, e.g. > > subtype mytype is integer range -1 to 1; > > Because this is a subtype of integer, it can be assigned to and from > integers and other integer subtypes. > > regards > Alan > > -- > Alan Fitch My problem is that I want this type to only be able to assume the values of -1 and 1, not 0. However, I suppose the declaration of a new type for this is inconvenient because if I want to do any math with the type I have to convert to a new integer type if the result assumes a value that is not (-1,1)? From newsfish@newsfish Tue Aug 9 07:53:30 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 26 Jun 2011 14:37:43 -0500 Date: Sun, 26 Jun 2011 20:37:43 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Enumerated integer type References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 53 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-xfwz7wmSUk6gSbhzIFKoIcXVWRz7duXMMDrxBFZ+sOl+/PvgF9OTfU7yoVu+amforDvXIceYjoxG+aT!lCyh1J3bTjcCV3OwIcPlsu2RPW5jkIC/CdVWwTxZ+IlOJKBcVfkzbKfVWyHNj77CeeddTNRpBTR4!iVkqN+bDeltDPX2P8YYPxWah X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2962 Xref: feeder.eternal-september.org comp.lang.vhdl:5077 On 26/06/11 18:18, Colin Beighley wrote: > On Jun 24, 11:54 am, Alan Fitch wrote: >> On 24/06/11 17:24, Colin Beighley wrote: >> >> >>> Hello, >> >>> I'd like to declare a type like this >> >>> type mytype is (-1,1); >> >>> However, it appears that enumerated types aren't allowed to be >>> integers. >> >>> Is there a way to create an integer subtype where the values of the >>> type are constrained to certain hand-picked values, rather than a >>> range? The workaround for this is to use std_logic and convert it to >>> signed when you need to, but it seems an integer subtype would work >>> better. >> >>> Colin >> >> Enumerated types can be a mixture of character literals and identifiers. >> >> What you probably want is an integer subtype, e.g. >> >> subtype mytype is integer range -1 to 1; >> >> Because this is a subtype of integer, it can be assigned to and from >> integers and other integer subtypes. >> > > My problem is that I want this type to only be able to assume the > values of -1 and 1, not 0. However, I suppose the declaration of a new > type for this is inconvenient because if I want to do any math with > the type I have to convert to a new integer type if the result assumes > a value that is not (-1,1)? I guess you could go the whole hog and declared an enumerated type representing -1 and 1, e.g. type mytype is (minusone, plusone); then overload operators on that type. You'd also have to write conversion functions to and from integer. It's all quite feasible, you just need the time and inclination :-) regards Alan -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:30 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!q1g2000vbj.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Enumerated integer type Date: Sun, 26 Jun 2011 22:59:51 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <104bc36e-4158-46ab-9402-49e3afb80bf6@q1g2000vbj.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309154391 32366 127.0.0.1 (27 Jun 2011 05:59:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Jun 2011 05:59:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q1g2000vbj.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.18) Gecko/20110615 Ubuntu/10.04 (lucid) Firefox/3.6.18,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5078 On 24 Jun., 18:24, Colin Beighley wrote: > Hello, > > I'd like to declare a type like this > > type mytype is (-1,1); > > However, it appears that enumerated types aren't allowed to be > integers. > > Is there a way to create an integer subtype where the values of the > type are constrained to certain hand-picked values, rather than a > range? The workaround for this is to use std_logic and convert it to > signed when you need to, but it seems an integer subtype would work > better. > > Colin Hi, Not sure what you are about to do with this kind of type declaration You can declare some ordinary enumerated type like : type mytype is (neg,pos); Then you can access the integers then with some simple conversion function: function getint(a : mytype) return integer range -1 to 1; -- or whatever you like to call that function usage example: xx <= xx * getint(neg); Have a nice synthesis Eilert From newsfish@newsfish Tue Aug 9 07:53:30 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c29g2000yqd.googlegroups.com!not-for-mail From: Philippe Faes Newsgroups: comp.emacs,comp.lang.vhdl Subject: Are there technical reasons why Emacs is better than an IDE? Followup-To: comp.emacs, comp.lang.vhdl Date: Mon, 27 Jun 2011 04:06:04 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309174510 1947 127.0.0.1 (27 Jun 2011 11:35:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Jun 2011 11:35:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c29g2000yqd.googlegroups.com; posting-host=195.144.71.15; posting-account=Dh2KDAoAAACN2skkW5NrnTSyvGjOAQ7F User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.100 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3950 comp.lang.vhdl:5079 It is no secret that Sigasi wants to take on Emacs and the Emacs VHDL mode. I have posted several articles about the fundamental differences between Emacs and Sigasi: http://www.sigasi.com/emacs It usually boils down to the limitations of regular expressions and pattern matching. There are just certain things that require a parser rather than a simple pattern matcher. To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am interested to hear what you think: are there any _technical_ reasons why Emacs is still better than an IDE solution? Or is it just a matter of "I love this tool and nobody is going to deny me my rights?" http://www.sigasi.com/content/room-improvement thanks Philippe -- Philippe Faes http://www.sigasi.com From newsfish@newsfish Tue Aug 9 07:53:30 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: boldport Date: Mon, 27 Jun 2011 07:08:03 -0500 Lines: 85 Message-ID: <96ra54FpqdU1@mid.individual.net> References: <4206215d-031e-46e0-9e11-c50159662586@e21g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 9w2Fmtj983QslkwY5k0awwapZCuJCC1szaJbcLW6vXPZHdULmf Cancel-Lock: sha1:fG/55IqEWMGT9ijiCYBi4ZPUBSg= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <4206215d-031e-46e0-9e11-c50159662586@e21g2000vbz.googlegroups.com> X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.arch.fpga:15792 comp.lang.vhdl:5080 comp.lang.verilog:3096 On 5/5/2011 12:58 PM, saar drimer wrote: > In a bit of a self promotional move, though probably pretty relevant > to this group, I'd like to mention [snip] As a reminder and a caution for future posting: http://www.faqs.org/faqs/usenet/advertising/how-to/part1/ which reminded me why your post didn't get much of a feedback even though I found the content rather interesting. > for easing the migration from GUI to command-line use of FPGA tools, > and more effective project/build management. I want to say that I'm on your side when you say that a "command-line" use of FPGA tools is a nice to have, but I have to admit that the overall tendency is to use GUI and integrated environments where the designer has the (deceived) perception that everything is at his own hand and control. We can argue a lifetime on what is better, but IMHO the market has chosen its horse and is not the command-line, regardless efficiency drawbacks. The portability problem is often used as an argument to propose yet another model that will have eventually the same problems of portability that previous models had. That is why I always intend portability in the sense that is easy to carry around for it doesn't depend on system's features or device's features and ultimately tool's features. In addition I believe most of the designers out there are not really moving from a linux machine to a windows machine every day and they don't switch from an ABC device to a CBA device every other day and whenever they would be in the place where they *have to* switch, it's going to be a hard day and no magic can be at hand but a previously thought through approach to design in an as abstract way as possible. Hardware Description Languages have been invented for good because they give the designer a mean which will help him looking at the big picture instead of the gates and flops actually used. And this level of abstraction has an enormous potential that most of the time is overlooked in the names of concepts like "optimization" or "I had to put that GCLK buffer otherwise it wouldn't work!". > > The project is at an early stage, and more features will be added with > time. Praise, constructive feedback, and well-mannered bashing are > welcome, of course... be as honest as this group knows how to be (feel > free to email me privately as well). Finally, I'm looking for early > adopter projects, and offer my help with the setup. Talking about scalability problems, how do you intend to provide help on the long run? Say you have 10 million users instead of 10, I think numbers do play a difference. On top of it, what make your company different from yet another EDA company willing for designers to adopt their approach and strangle them with incompatibility features that will shackle them for the rest of their life? Since is not open-source and is profit oriented, do you think it's enough to say that your approach "is better" to convince designers to change their habits? After all a designer wants to design as much as a painter wants to paint. If art can be made with any tool available in your garage, hardware can follow the same line and be built with just an editor or any available tool you have in your computer (maybe a text editor is enough!). That is why IMHO we should foster good designing approaches that will enhance the portability in terms of code, as opposed to project structure. The project approach is borrowed from the management world and has nothing to do with HDL. Indeed I always asked myself why should I create a project when my goal is to describe how a piece of hardware should work. "Project" is a name poorly defined, a concept poorly defined, with no boundaries and no constraints and that is the root of all your and our problems. > > Thanks for your attention, Believe me, even though I might have sounded harsh, I paid a lot of attention to it! > saar. > > From newsfish@newsfish Tue Aug 9 07:53:31 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.internetdienste.de!news.tu-darmstadt.de!news.muc.de!not-for-mail From: Alan Mackenzie Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Mon, 27 Jun 2011 21:23:27 +0000 (UTC) Organization: muc.de e.V. Lines: 48 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: marvin.muc.de X-Trace: colin2.muc.de 1309209807 49628 2001:608:1000::2 (27 Jun 2011 21:23:27 GMT) X-Complaints-To: news-admin@muc.de NNTP-Posting-Date: Mon, 27 Jun 2011 21:23:27 +0000 (UTC) User-Agent: tin/1.6.2-20030910 ("Pabbay") (UNIX) (FreeBSD/4.11-RELEASE (i386)) Xref: feeder.eternal-september.org comp.emacs:3951 comp.lang.vhdl:5081 In comp.emacs Philippe Faes wrote: > It is no secret that Sigasi .... Who? What? > .... wants to take on Emacs and the Emacs VHDL mode. Emacs is free software. Anybody may take it on. > I have posted several articles about the fundamental differences > between Emacs and Sigasi: http://www.sigasi.com/emacs It usually boils > down to the limitations of regular expressions and pattern matching. "It"? Differences come down to limitations? Sir, you are not expressing yourself at all clearly. > There are just certain things that require a parser rather than a > simple pattern matcher. Of course there are. What's new? Arbitrarily nested structures (think program source) cannot be parsed by regexps. Try using a push-down automaton. > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Yes. > Or is it just a matter of "I love this tool and nobody is going to deny > me my rights?" Hmmm. On comp.emacs. You wouldn't happen to be trolling, now, would you? > http://www.sigasi.com/content/room-improvement > thanks > Philippe > -- > Philippe Faes > http://www.sigasi.com -- Alan Mackenzie (Nuremberg, Germany). From newsfish@newsfish Tue Aug 9 07:53:31 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Mon, 27 Jun 2011 16:42:37 -0700 Lines: 33 Message-ID: <4E09156D.50400@gmail.com> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 32oxysq1ELTiY4ZyGsHlbQyXu2unbDrWxLYWlXD1K2VsXRMSwa Cancel-Lock: sha1:dKAE1hiEY2kJptagx1q7GXcdc6k= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:5082 On 6/27/2011 4:06 AM, Philippe Faes wrote: > It is no secret that Sigasi wants to take on Emacs and the Emacs VHDL > mode. I have posted several articles about the fundamental differences > between Emacs and Sigasi: http://www.sigasi.com/emacs > It usually boils down to the limitations of regular expressions and > pattern matching. There are just certain things that require a parser > rather than a simple pattern matcher. The full language is hard for a parser as well, but all you need to cover are the parts that my simulator can't feed back. I am most interested in clean sim interfaces and makefile generation because my simulator is already good and fast at marking errors in syntax (vcom -c a_unit) and elaboration (vsim -c a_unit). Getting these errors fed back to emacs vhdl-mode requires careful configuration and a few custom elisp functions. This seems to be an area where you might have an advantage. > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" In any case, there are many fewer emacs users than non-users, so you have a good chance. -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:53:31 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!34g2000pru.googlegroups.com!not-for-mail From: NeedCleverHandle Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Wed, 29 Jun 2011 12:02:57 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <48a44f72-3517-4408-84b5-efc7f258a1d4@34g2000pru.googlegroups.com> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309374178 21413 127.0.0.1 (29 Jun 2011 19:02:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 29 Jun 2011 19:02:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 34g2000pru.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3954 comp.lang.vhdl:5083 On Jun 27, 4:06=A0am, Philippe Faes wrote: > It is no secret that Sigasi wants to take on Emacs and the Emacs VHDL > mode. I have posted several articles about the fundamental differences > between Emacs and Sigasi:http://www.sigasi.com/emacs > It usually boils down to the limitations of regular expressions and > pattern matching. There are just certain things that require a parser > rather than a simple pattern matcher. > > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" > > http://www.sigasi.com/content/room-improvement > > thanks > > Philippe > > -- > Philippe Faeshttp://www.sigasi.com Just a few off the top: 1) emacs can be run in batch mode, so all of the 'AUTOs' can be updated at once. 2) emacs is a much more powerful editor. There are times you NEED rectangle cut/paste. 3) emacs developers don't spam usenet. I prefer less volatile discussions than editor choices - religion and politics are typically less incendiary. From newsfish@newsfish Tue Aug 9 07:53:31 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp17-1.free.fr!not-for-mail Date: Wed, 29 Jun 2011 22:03:37 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 MIME-Version: 1.0 Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> In-Reply-To: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 11 Message-ID: <4e0b8518$0$16389$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 29 Jun 2011 22:03:37 MEST NNTP-Posting-Host: 82.246.229.10 X-Trace: 1309377817 news-4.free.fr 16389 82.246.229.10:58095 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.emacs:3955 comp.lang.vhdl:5084 Le 27/06/2011 13:06, Philippe Faes a écrit : > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" Emacs can do soooooo many more things than VHDL editing. Why use a different IDE for each language ? Nicolas From newsfish@newsfish Tue Aug 9 07:53:31 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Thu, 30 Jun 2011 01:24:55 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <4e0b8518$0$16389$426a34cc@news.free.fr> In-Reply-To: <4e0b8518$0$16389$426a34cc@news.free.fr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 21 Message-ID: <4e0bb447$0$14245$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: a6fa0f48.news.skynet.be X-Trace: 1309389895 news.skynet.be 14245 91.177.169.145:34166 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.emacs:3956 comp.lang.vhdl:5085 On 06/29/2011 10:03 PM, Nicolas Matringe wrote: > Le 27/06/2011 13:06, Philippe Faes a écrit : > >> To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am >> interested to hear what you think: are there any _technical_ reasons >> why Emacs is still better than an IDE solution? Or is it just a matter >> of "I love this tool and nobody is going to deny me my rights?" > > Emacs can do soooooo many more things than VHDL editing. > Why use a different IDE for each language ? That is not the proposal, quite the opposite. The proposal is to use Eclipse as the IDE, and Sigasi HDT as its "VHDL mode". Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Tue Aug 9 07:53:31 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!uio.no!news.tele.dk!news.tele.dk!small.news.tele.dk!bnewspeer01.bru.ops.eu.uu.net!bnewspeer00.bru.ops.eu.uu.net!emea.uu.net!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Thu, 30 Jun 2011 01:32:26 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <48a44f72-3517-4408-84b5-efc7f258a1d4@34g2000pru.googlegroups.com> In-Reply-To: <48a44f72-3517-4408-84b5-efc7f258a1d4@34g2000pru.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 49 Message-ID: <4e0bb60a$0$14252$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: a6fa0f48.news.skynet.be X-Trace: 1309390347 news.skynet.be 14252 91.177.169.145:57744 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.emacs:3957 comp.lang.vhdl:5086 On 06/29/2011 09:02 PM, NeedCleverHandle wrote: > On Jun 27, 4:06 am, Philippe Faes wrote: >> It is no secret that Sigasi wants to take on Emacs and the Emacs VHDL >> mode. I have posted several articles about the fundamental differences >> between Emacs and Sigasi:http://www.sigasi.com/emacs >> It usually boils down to the limitations of regular expressions and >> pattern matching. There are just certain things that require a parser >> rather than a simple pattern matcher. >> >> To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am >> interested to hear what you think: are there any _technical_ reasons >> why Emacs is still better than an IDE solution? Or is it just a matter >> of "I love this tool and nobody is going to deny me my rights?" >> >> http://www.sigasi.com/content/room-improvement >> >> thanks >> >> Philippe >> >> -- >> Philippe Faeshttp://www.sigasi.com > > Just a few off the top: > 1) emacs can be run in batch mode, so all of the 'AUTOs' can be > updated at once. The fact that you actually need 'AUTOs' (?) and batch mode shows that a more powerful IDE may be quite useful. > 2) emacs is a much more powerful editor. There are times you NEED > rectangle cut/paste. Whatever it is in emacs, this is certainly not easier than 'Toggle Block Selection' (Shift+Alt+A). > 3) emacs developers don't spam usenet. This is on-topic content, written on a specific occasion by real people. Calling it spam just because you thoroughly dislike the message is a little cheap. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Tue Aug 9 07:53:32 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d14g2000yqb.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Thu, 30 Jun 2011 06:19:01 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <4487d336-ac46-4dbd-a69a-d8dd0cc7e42a@d14g2000yqb.googlegroups.com> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309439942 25036 127.0.0.1 (30 Jun 2011 13:19:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Jun 2011 13:19:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d14g2000yqb.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9979) X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRUV X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3960 comp.lang.vhdl:5087 On 27 Jun., 13:06, Philippe Faes wrote: > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" Maybe it is just the fact that emacs is for free and good enough, so why bother about Sigasi? I assume you already included open script interface in your sigasi tool to be at least on the obvious parts on-pair with emacs, but as long as I'm fine with gnu tool, I see no reason to check alternatives every 6 months. From newsfish@newsfish Tue Aug 9 07:53:32 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: How do you introduce delays into 3-state (bi-dir) lines? Date: Thu, 30 Jun 2011 19:36:28 +0300 Organization: A noiseless patient Spider Lines: 1 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 30 Jun 2011 16:36:31 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="10581"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+dAfCOU5DeYhHuzzYgTBlRaKaWhgPjLH8=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 Cancel-Lock: sha1:ibTXGjzNNzJAKN5bEicsfRfTDa0= Xref: feeder.eternal-september.org comp.lang.vhdl:5088 This is needed for bus simulation From newsfish@newsfish Tue Aug 9 07:53:32 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h25g2000prf.googlegroups.com!not-for-mail From: Philippe Faes Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Thu, 30 Jun 2011 11:33:51 -0700 (PDT) Organization: http://groups.google.com Lines: 58 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 83.134.176.236 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309458832 16408 127.0.0.1 (30 Jun 2011 18:33:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Jun 2011 18:33:52 +0000 (UTC) Cc: tzz@lifelogs.com Complaints-To: groups-abuse@google.com Injection-Info: h25g2000prf.googlegroups.com; posting-host=83.134.176.236; posting-account=Dh2KDAoAAACN2skkW5NrnTSyvGjOAQ7F User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3963 comp.lang.vhdl:5089 Thank you all for your input. The technical arguments I hear are: Mike Treseler wrote: > The full language is hard for a parser as well, > but all you need to cover are the parts > that my simulator can't feed back. Some editor features require a full parser (and: yes, it is hard), including correct navigation and refactoring. > I am most interested in clean sim interfaces > and makefile generation [=85] Duly noted. Sigasi offers some of this, but we know we still need to improve on this. NeedCleverHandle wrote: > 1) emacs can be run in batch mode, so all of the 'AUTOs' can be > updated at once. Note that you are bringing up Verilog as opposed to VHDL now. This particular use case (automatic template expansion in Verilog) would be a good argument for interactive tools rather than batch processing. Checking and updating sensitivity list is something that can easily be done interactively. If you want to discuss any specific other use cases for batch mode, I'll be happy to dig deeper into this subject. > 2) emacs is a much more powerful editor. There are times you NEED > rectangle cut/paste. As Jan Decaluwe points out, Eclipse supports block editing. I am interested to learn of other features that make Emacs a much more powerful editor. Nicolas Matringe wrote: > Emacs can do soooooo many more things than VHDL editing. > Why use a different IDE for each language ? Again as Jan points out: that is exactly my point. The Eclipse platform will offer a wide range of language-specific plug-ins to choose from. Ted Zlatanov (received this by email) wrote: > Emacs has very capable parsers built-in. =A0Whether VHDL editing needs > them is not clear; [...] Emacs has a very capable regex matcher, but not a VHDL parser. A built-in parser enables several things such as semantic highlighting and correct navigation. As I pointed out in my original post, I have discussed this at length elsewhere. I'll throw in one myself: Sorting lines alphabetically is a pain in Eclipse. There are some not- so-stable or not-so-recent plugins that support this feature, but people usually don't install a new plugin just to get one simple operation. Any other thoughts are still more than welcome. -- Philippe From newsfish@newsfish Tue Aug 9 07:53:32 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe05.ams2.POSTED!00000000!not-for-mail From: William Stevenson Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.0.50 (gnu/linux) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAFVBMVEVMEhl7LzAuAwhMHiLd wLuFQkNaJilixb28AAACHElEQVQ4jV3Ty3biMAwGYMWZskYw8TqjTLtm4pInSPb1OTHrhBS//yPM b9lQWu/Qd6xLLGgcxymEcInlbEPsu3kcCTACwhfwVZ5Br2zOubM99ref4ESkktifvyCnyVD1rwWm cHFuwIUeYOXt8BrKjdWLuJwJ0NmXEBQ8ASjDbi+y3gpcKBiilWO0jGZlF11U+DANc2otWDKip0ow fZhzCA3ivoSl/0ep2eOpjUSB+QGDpSnMl+2EQOUZp0CMFMIYXQL2DVe813i3/wTMmzuJ/AkcPFFq Cj/inMFI2zCqX4UOqfSwzjRNwSLTLuwBi7QJOtfM6GpCBnnzFeBo3g5aZP2d5vAblVR2qQ5SWSPV rwKE2YOCEUZr1Yum4obpxafJ92wqJl7WJUH6GpxhqZiJdsw3yksSfJNvrGwJEvsMHgUUIhLV9Ymc I92EkFpKxeOCWDrnAqg/g4/15sqhcZonlZk5Xtt7fMANBXxClDRSD/GRKoNP7aNq/AnplaKjQfe0 z8XLDcBWxwLvKP4Euo+Arnu/d5XAuiGlB/cJxjmUGtbF+xid7i5eVzOxrrxzWwFkGjNwpPt8z5A+ K9ZIhz9rqkkhxfW9Ee/fH8ALtWRao/E7YPiA9DtKJ9eYH/9BrfwFj/+gjrE84p8Fcrd2MYJ3RVzG O0yaCqvd1uSwut/Axg3vRGKk//sN8FlNW59a/HW/gU2AsX+CB6C4oHaG/7449jZiFODnAAAAAElF TkSuQmCC Message-ID: Cancel-Lock: sha1:+yZ9j/oGkrpMahVMyS75ImxJZzE= MIME-Version: 1.0 Content-Type: text/plain Lines: 7 NNTP-Posting-Host: 81.99.65.51 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe05.ams2 1309461128 81.99.65.51 (Thu, 30 Jun 2011 19:12:08 UTC) NNTP-Posting-Date: Thu, 30 Jun 2011 19:12:08 UTC Organization: virginmedia.com Date: Thu, 30 Jun 2011 20:12:04 +0100 Xref: feeder.eternal-september.org comp.emacs:3964 comp.lang.vhdl:5090 Read "Beautiful Architecture" [1] chapter on emacs for a good look at how and why emacs is great, and how it compares to other architectures, namely Eclipse and Firefox. [1] http://oreilly.com/catalog/9780596517984 Chapter 11 GNU Emacs: Creeping Featurism Is a Strength From newsfish@newsfish Tue Aug 9 07:53:32 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!j31g2000yqe.googlegroups.com!not-for-mail From: Lieven Lemiengre Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Fri, 1 Jul 2011 07:46:35 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309531595 19327 127.0.0.1 (1 Jul 2011 14:46:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Jul 2011 14:46:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j31g2000yqe.googlegroups.com; posting-host=195.144.71.15; posting-account=Ah6zaAoAAAACT7jhwwcVLW7AYlcH3abR User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3970 comp.lang.vhdl:5091 On 30 jun, 21:12, William Stevenson wrote: > Read "Beautiful Architecture" [1] chapter on emacs for a good look at > how and why emacs is great, and how it compares to other architectures, > namely Eclipse and Firefox. > > [1]http://oreilly.com/catalog/9780596517984 > =A0 =A0 Chapter 11 GNU Emacs: Creeping Featurism Is a Strength I looked it up and I quote: "As a development environment, Eclipse provides valuable features that Emacs lacks. For example, the Java Development Tools plug-ins provide extensive support for refactoring and code analysis. In comparison, Emacs has only a limited understanding of the semantic structure of the programs it edit and can't offer comparable support." From newsfish@newsfish Tue Aug 9 07:53:32 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n5g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Fri, 1 Jul 2011 09:20:34 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> References: NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309537234 10551 127.0.0.1 (1 Jul 2011 16:20:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Jul 2011 16:20:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n5g2000yqh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5092 On Jun 30, 12:36=A0pm, valtih1978 wrote: > This is needed for bus simulation Check out Ben Cohen's model at the link below http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/de067db0= 14e088d7/7d14832588a0cabb Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:33 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!g12g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Fri, 1 Jul 2011 09:29:30 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <9a20bb33-0f97-4e55-858b-8896f43d1099@g12g2000yqd.googlegroups.com> References: NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309537770 15462 127.0.0.1 (1 Jul 2011 16:29:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Jul 2011 16:29:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g12g2000yqd.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5093 On Jun 30, 12:36=A0pm, valtih1978 wrote: > This is needed for bus simulation Take a look at Ben Cohen's model at the link below http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/de067db0= 14e088d7/7d14832588a0cabb Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:33 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!xmission!nnrp.xmission!not-for-mail From: Jason Earl Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Fri, 01 Jul 2011 13:02:07 -0600 Organization: XMission http://xmission.com/ Lines: 32 Message-ID: <877h81eseo.fsf@notengoamigos.org> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 67.214.244.122 Mime-Version: 1.0 Content-Type: text/plain X-Trace: news.xmission.com 1309546956 6741 67.214.244.122 (1 Jul 2011 19:02:36 GMT) X-Complaints-To: abuse@xmission.com NNTP-Posting-Date: Fri, 1 Jul 2011 19:02:36 +0000 (UTC) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwCAAAAAByaaZbAAAABGdBTUEAALGPC/xhBQAAAAFz UkdCAK7OHOkAAAAgY0hSTQAAeiYAAICEAAD6AAAAgOgAAHUwAADqYAAAOpgAABdwnLpRPAAAAAlw SFlzAAASmwAAEpsB4JJZDAAAAAl2cEFnAAAAMAAAADAAzu6MVwAAAaFJREFUSMe1VtuxxSAIzIz9 2Iyl2Aj1bBX0k5+LrwjGjJyPy2ROwtGNBJbVCwwwy1UNoOL3f+SBxkj15Lr4NsboN24DWMZxYQNA TjGmjC1gswJiqBbpDeANYMwXBFyAFB5L7ADMBcoSDgAFBSDHR2tA8ABMSB4AawB76pAnILsKx2lm 1VfpgUi3kxrySylRHdmQj40Jva2/jl8EY3Twv/phhsC9nIQR0hnAOUptYsL3RxvAk+YIH2AWsvTH GYBgKn8GaPYm5jNANaCQ8WfAzyH9x0crFfGl9X4QVdg8gEqN2KjBHi6V/iBq6iyAxTqd+Yvupwai VwM9LZkxQ6otihmS6H+mHlK5URwi0UQgWxHoxS5JagBSed7IzJRCallS2pg2QsamcGUFNSHgLZUv augJIUualv1Bv6+yVat1oeMq92s/mBBWQJH7dQX7CnpvWWs/4CazpHlB2RR1BFSzNGdIaTbbLil8 U76BKKU0GztapXP3C78bNYQ6MTQybY8OkIaITf9HPzyHkXE4YXs4mf5VDz+jAepj3RTQ3Ubv0SPy 9AcCrfKh0TBgvgAAACV0RVh0ZGF0ZTpjcmVhdGUAMjAxMS0wMS0wM1QxMDo1MDo1NC0wNzowMIgC s0IAAAAldEVYdGRhdGU6bW9kaWZ5ADIwMTAtMDQtMDVUMTM6MjQ6NDgtMDY6MDCtwF/YAAAAAElF TkSuQmCC User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.0.50 (gnu/linux) Cancel-Lock: sha1:avqlY/9rseIlpnY1JdeznDOlvt0= Xref: feeder.eternal-september.org comp.emacs:3974 comp.lang.vhdl:5094 On Thu, Jun 30 2011, Philippe Faes wrote: [...] > I'll throw in one myself: > Sorting lines alphabetically is a pain in Eclipse. There are some not- > so-stable or not-so-recent plugins that support this feature, but > people usually don't install a new plugin just to get one simple > operation. Emacs has a couple of advantages over tools like Eclipse. The biggest advantage, IMHO, is that it is easy to add new code. You don't have to compile anything, or install any plugins. You can add a new function to your currently running instance of Emacs with just a few keystrokes. I often find myself creating "throw-away" code to do some little editing task that would be very tedious to do otherwise. Not only does Emacs have code for sorting lines (and paragraphs and pages), but it is easy to add code to sort however or whatever you would like. Another big advantage is that you can realistically use it for most of your text editing tasks. I spend quite a bit of my time in front of a computer writing code. However, the fact that the Emacs skills that serve me while writing code are also useful when creating other documents, reading email, planning my day, taking notes, etc. means that time spent learning to use Emacs well can be leveraged across most of my computer-using activities. Personally, I have high hopes that the recent integration of CEDET into Emacs will begin to give Emacs hackers the tools that they need to build smarter Emacs modes. Jason From newsfish@newsfish Tue Aug 9 07:53:33 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!u19g2000vbi.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Mon, 4 Jul 2011 17:22:23 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <877h81eseo.fsf@notengoamigos.org> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309825343 27087 127.0.0.1 (5 Jul 2011 00:22:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Jul 2011 00:22:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u19g2000vbi.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-Google-Web-Client: true X-Google-Header-Order: VCRUHALSNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3982 comp.lang.vhdl:5095 Hi everyone, One thing I have trouble understanding is the following. Designers typically spend way more time debugging VHDL code, running simulations, debugging "real" hardware than writing actual code. Therefore, I have trouble understanding why comparing Sigasi to Emacs is so important? A lot of the Emacs feature are basically tools to write code faster (code completion, sensitivity list updating, etc.). Even If I write code 10% faster, this is probably the equivalent of a driver speeding up only to being forced to stop because the light is red. The analogy is imperfect, but basically in real life I'm limited by the simulation speed of my simulator, I'm limited by the synthesis/ p&r of Xilinx/Altera/etc. I'm limited by real-life issues like a faulty board, unclear specifications, project management, etc. Rarely have I felt limited by notepad++ even though it is a simple code editor with syntax highlighting. I agree than Sigasi looks interesting from a code refactoring, project management and code comprehension perspective but less so from a "writing code faster point of view". What would be important for me, is good integration with Xilinx (or Altera) and good integration with Modelsim (or Aldec). Just my 2 cents. Benjamin From newsfish@newsfish Tue Aug 9 07:53:33 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a7g2000vby.googlegroups.com!not-for-mail From: Philippe Faes Newsgroups: comp.lang.vhdl Subject: VHDL Product Announcement: Sigasi Starter Edition Date: Tue, 5 Jul 2011 02:11:01 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309857063 22087 127.0.0.1 (5 Jul 2011 09:11:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Jul 2011 09:11:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a7g2000vby.googlegroups.com; posting-host=195.144.71.15; posting-account=Dh2KDAoAAACN2skkW5NrnTSyvGjOAQ7F User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5096 Hi everybody, At Sigasi, we have launched the "Sigasi 2.0 Starter Edition", an IDE for the VHDL language. The number one new feature is type-time error checking. The Starter Edition will be permanently free of charge. If your project is small enough, you get to use all of the Pro features as well (Pro version will be launched later this year). Read the full announcement: http://www.sigasi.com/clv/announcing-starter-edition Download: http://www.sigasi.com/clv/download-sigasi-20 best regards Philippe Sigasi From newsfish@newsfish Tue Aug 9 07:53:33 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l18g2000yql.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: boldport Date: Tue, 5 Jul 2011 10:37:19 -0700 (PDT) Organization: http://groups.google.com Lines: 111 Message-ID: <7c578462-2fad-41fd-8802-be192ec6c3c4@l18g2000yql.googlegroups.com> References: <4206215d-031e-46e0-9e11-c50159662586@e21g2000vbz.googlegroups.com> <96ra54FpqdU1@mid.individual.net> NNTP-Posting-Host: 86.6.9.112 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309890102 31567 127.0.0.1 (5 Jul 2011 18:21:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Jul 2011 18:21:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l18g2000yql.googlegroups.com; posting-host=86.6.9.112; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:15842 comp.lang.vhdl:5097 comp.lang.verilog:3108 On Jun 27, 1:08=A0pm, Alessandro Basili wrote: > I want to say that I'm on your side when you say that a "command-line" > use of FPGA tools is a nice to have, but I have to admit that the > overall tendency is to use GUI and integrated environments where the > designer has the (deceived) perception that everything is at his own > hand and control. > > We can argue a lifetime on what is better, but IMHO the market has > chosen its horse and is not the command-line, regardless efficiency > drawbacks. I understand that we do agree that scripted flows are better, so there's no need to argue. My view is that that horse is running out of steam in the face of progress in development methods and complexity. I'm not saying "nice to have", I'm saying that scripted flows are *essential* if we want to adopt any of the good stuff that software development has benefited from in the past decade. I'm talking about revision control, transparent IP/code reuse and distribution, modularity, team-based design, and so on. I also don't think it's the "market" that's made a choice, it's the vendors that have bet on the wrong horse. I've elaborated on this a bit here: https://www.boldport.com/blog/?p=3D369 > The portability problem is often used as an argument to propose yet > another model that will have eventually the same problems of portability > that previous models had. That is why I always intend portability in the > sense that is easy to carry around for it doesn't depend on system's > features or device's features and ultimately tool's features. That's a separate issue of generic vs architecture-specific design, which I've not gotten into in the context of the structure I'm proposing. Or, rather, I'm not arguing for either side. > In addition I believe most of the designers out there are not really > moving from a linux machine to a windows machine every day and they > don't switch from an ABC device to a CBA device every other day and > whenever they would be in the place where they *have to* switch, it's > going to be a hard day and no magic can be at hand but a previously > thought through approach to design in an as abstract way as possible. > > Hardware Description Languages have been invented for good because they > give the designer a mean which will help him looking at the big picture > instead of the gates and flops actually used. And this level of > abstraction has an enormous potential that most of the time is > overlooked in the names of concepts like "optimization" or "I had to put > that GCLK buffer otherwise it wouldn't work!". OK. > Talking about scalability problems, how do you intend to provide help on > the long run? Say you have 10 million users instead of 10, I think > numbers do play a difference. They sure do. 10 million is about two orders of magnitude off from my rough estimate for the potential user space. But the answer is that I don't know... I'll first deal with 10, then 100 and then see how things go. > On top of it, what make your company different from yet another EDA > company willing for designers to adopt their approach and strangle them > with incompatibility features that will shackle them for the rest of > their life? I'm conscious of this, and am doing my best to minimise lock-in, now and for the future (see here: https://www.boldport.com/blog/?p=3D103 ). Of course, there's a certain investment of resources in learning / adopting anything -- my hope is that what I'm proposing / offering has enough benefit for people to make that investment. Maybe I'm wrong; I'm testing my hypothesis right now. > Since is not open-source and is profit oriented, do you think it's > enough to say that your approach "is better" to convince designers to > change their habits? No; that's why I've written that long document. I tried to provide reasoning behind every choice I made, hoping to get feedback and revise as needed. > After all a designer wants to design as much as a painter wants to > paint. If art can be made with any tool available in your garage, > hardware can follow the same line and be built with just an editor or > any available tool you have in your computer (maybe a text editor is > enough!). Yes. > That is why IMHO we should foster good designing approaches that will > enhance the portability in terms of code, as opposed to project structure= . I don't see a reason why we can't have both. > The project approach is borrowed from the management world and has > nothing to do with HDL. Indeed I always asked myself why should I create > a project when my goal is to describe how a piece of hardware should > work. "Project" is a name poorly defined, a concept poorly defined, with > no boundaries and no constraints and that is the root of all your and > our problems. :) > > Thanks for your attention, > > Believe me, even though I might have sounded harsh, I paid a lot of > attention to it! Your feedback is greatly appreciated! I'm happy to continue this discussion here or privately. From newsfish@newsfish Tue Aug 9 07:53:33 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Tue, 05 Jul 2011 21:41:14 +0200 Lines: 116 Message-ID: <97h7mpF1seU1@mid.individual.net> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <877h81eseo.fsf@notengoamigos.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 1E3CSUA4426iha9HxMfMAADcMURuIYNnhsTn9rZ2DUWg4GX2bj Cancel-Lock: sha1:CqQn1pxlhyBPlFyHW36/Juxj0uk= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.emacs:3984 comp.lang.vhdl:5098 On 7/5/2011 2:22 AM, Benjamin Couillard wrote: > Hi everyone, > > One thing I have trouble understanding is the following. Designers > typically spend way more time debugging VHDL code, running > simulations, debugging "real" hardware than writing actual code. How do you debug your code? Isn't this process of "debugging real hardware" just a matter of reading your code and understanding what it is doing? After all if the hardware doesn't work (except for pathological cases of bad pcb/pca, see later) is just because you wrote something wrong. >From this perspective having an editor that helps you out in the process of reading and editing your file is definitely a powerful tool. Would you write code with notepad? or a word processor? or with a pen and paper? If the answer is no (as I presume), than the added value of a smart editor is not negligible. > Therefore, I have trouble understanding why comparing Sigasi to Emacs > is so important? A lot of the Emacs feature are basically tools to > write code faster (code completion, sensitivity list updating, etc.). > Even If I write code 10% faster, this is probably the equivalent of a > driver speeding up only to being forced to stop because the light is > red. The analogy is imperfect, but basically in real life I'm limited > by the simulation speed of my simulator, I'm limited by the synthesis/ > p&r of Xilinx/Altera/etc. That is why you should spend more time reading and editing the file rather than running simulation. If you try to write an ARM architecture full of peripherals and then assume your simulation will run through and spot all the problems then I understand your frustration, but I also believe the approach is wrong. Project segmentation is a very old technique that is always applicable. Make your components generic enough to be reusable, not too small otherwise you will loose the overview of your design and you will clutter the code with components instantiation. Not to big otherwise you will loose valuable details of the design (usually the brain is the best tool to decide where to put the boundary). At this point test your components individually with a dedicated test bench (try "C-c C-p C-t" on emacs and then let's review your 10% speed increase) in order to trust your basic elements of your design. Only then you can more reliably move to the next step of connecting the components together, to build a bigger piece. Usually this approach force the designer to think about the interface between the components and maybe try to make it standard (like a bus). So the outcome of this process is not only more reliable, but enable the designer to build a mental toolbox of "good practices" rather than "dirty tricks". > I'm limited by real-life issues like a > faulty board, unclear specifications, project management, etc. Rarely > have I felt limited by notepad++ even though it is a simple code > editor with syntax highlighting. The faulty board, unclear specifications, project management, etc. issue are certainly part of the process. This is why your work flow should be such that the PCB is going through a verified building process, your PCA is visually inspected and your components are previously screened for "infant mortality" before you can even think about testing anything. About the unclear specification that is certainly something you need to work out earlier with your customer, otherwise you'll be off doing something different from what he/she had in mind. And this has nothing to do with the hardware at all. Same conclusion applies to the project management problems which are not a good reason to justify your faulty design (even though they maybe blamed for an incomplete one). My background comes from antifuse-logic, where one chip programmed is certainly one chip thrown away if you don't verify your code. Code review and also "rubber duck debugging" are most of the times very good practices that helps you out in getting rid of clumsy and unmaintainable implementations. I understand that it's tempting sometime to "load it and see if it works", but if you face all the problems at once you may get in real trouble with your schedule. IMHO this temptation is mostly due to the volatility of the work, which comes from the nature of the hardware used. The so called firmware we load in fpgas is similar to software from an "easy to change" standpoint and this affect deeply the mindset we have in the design and implementation phase. Should you pay from your own pocket every time you release a version that needs to be one time programmed on a chip at a cost of several K$ I bet my salary you would definitely go back and thoroughly review your process to make sure you don't miss anything anywhere and if you do I bet the second salary you will try to understand what you did wrong the first time. > > I agree than Sigasi looks interesting from a code refactoring, project > management and code comprehension perspective but less so from a > "writing code faster point of view". What would be important for me, > is good integration with Xilinx (or Altera) and good integration with > Modelsim (or Aldec). > Code refactoring is not the only motivation for a good editor. Browsing capabilities in the components structure is extremely important since it allows you to navigate your source in a faster and more efficient way, leaving you the time to think about the problem, as opposed to the simulation where you need to go for a coffee or maybe two, since you are "waiting" for the result. Spending more time with your editor will also allow you to write better maintainable code, since if you do have some sense of aesthetic you will find that a poorly written code is poorly maintainable also. > Just my 2 cents. > In response to the OP I have to say that having an editor instead of a tool is way much better, since editing is something that is part of our daily work and every time we use the editor we learn better how to use it, regardless of the mode. From newsfish@newsfish Tue Aug 9 07:53:34 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!w24g2000yqw.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Tue, 5 Jul 2011 13:54:18 -0700 (PDT) Organization: http://groups.google.com Lines: 1 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <877h81eseo.fsf@notengoamigos.org> <97h7mpF1seU1@mid.individual.net> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309899381 29129 127.0.0.1 (5 Jul 2011 20:56:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Jul 2011 20:56:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w24g2000yqw.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-Google-Web-Client: true X-Google-Header-Order: VCRUHALSNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3986 comp.lang.vhdl:5099 Sorry for raising a doubt about Emacs, won't happen again... From newsfish@newsfish Tue Aug 9 07:53:34 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b21g2000yqc.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: can any one help me in VHDL codes plz Date: Wed, 6 Jul 2011 00:51:03 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <055fd9d3-c959-4b7f-8f1f-9d3c77cbf1e2@b21g2000yqc.googlegroups.com> NNTP-Posting-Host: 188.55.63.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309938669 5867 127.0.0.1 (6 Jul 2011 07:51:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 07:51:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b21g2000yqc.googlegroups.com; posting-host=188.55.63.142; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5100 hi all, really i want a help in these 2 problems : 1) I want a structural VHDL code of 1 to 16 Demultiplexers. with an active low Enable signal using 1 to 2 Demultiplexer. [ use Generate statement] __________________________________________________ ____________ 2) Also I need a structure and behavior VHDL code of 5-bits binary counter with a synchronous load signal to preset the counter to a specific initial state. the output of the counter ( Q0 to Q4) are connected to a binary decoder that shows the state of the counter. From newsfish@newsfish Tue Aug 9 07:53:34 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!o4g2000vbv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: can any one help me in VHDL codes plz Date: Wed, 6 Jul 2011 06:06:17 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <3661428b-1616-488f-8514-9fe6efc9d5d5@o4g2000vbv.googlegroups.com> References: <055fd9d3-c959-4b7f-8f1f-9d3c77cbf1e2@b21g2000yqc.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309960201 28466 127.0.0.1 (6 Jul 2011 13:50:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 13:50:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o4g2000vbv.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5101 Wheres the problem? Looks like a set of exercises you havent started yet. Or is the problem you're too lazy to do it yourself? On Jul 6, 8:51=A0am, majmoat_ensan wrote: > hi all, > > really i want a help in these 2 problems : > > 1) > I want a structural VHDL code of 1 to 16 Demultiplexers. with an > active low Enable signal using 1 to 2 Demultiplexer. [ use Generate > statement] > > __________________________________________________ ____________ > 2) > Also I need a structure and behavior VHDL code of 5-bits binary > counter with a synchronous load signal to preset the counter to a > specific initial state. the output of the counter ( Q0 to Q4) are > connected to a binary decoder that shows the state of the counter. From newsfish@newsfish Tue Aug 9 07:53:34 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Wed, 06 Jul 2011 18:24:51 +0200 Lines: 48 Message-ID: <97jgiiFe8vU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net WvCidfnDnijK7jfRlm7i1QTFRv4b35+av95WosiLPrXtsJq69D Cancel-Lock: sha1:e58xWOhA+uttXU2n2R4u8lBCMpE= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5102 On 6/25/2011 7:30 PM, logic_guy wrote: > TYPE states is (IDLE, S1, S2, S3, S4); > SIGNAL state : _states; > SIGNAL nDRDY_1, nDRDY_2, start : std_logic; > > start <= NOT nDRDY_1 and nDRDY_2; > > clk_proc: PROCESS > BEGIN > WAIT until rising_edge(clk); > nDRDY_1 <= nDRDY; > nDRDY_2 <= nDRDY_1; > CASE state is > WHEN IDLE => If start='1' > state <= S1; > end if; > WHEN S1 => -- Do state 1 processing here > -- when done: > state <= S2; > WHEN S2 => -- Do state 2 processing here > -- when done: > state <= S3; > WHEN S3 => -- Do state 3 processing here > -- when done: > state <= S4; > WHEN S4 => -- Do state 4 processing here > -- when done: > state <= IDLE; > -- Add or subtract states as needed > END CASE; > END PROCESS; > I would put start in the process to have it clocked. This would avoid any racing problems between nDRDY_1 and nDRDY_2. The clause "when others =>" should also be added, to land always on a "safe" state. I would also honor the OP choice of naming, being the start the input signal to this component. Last comment is on the choice of the structure "WAIT until" which I'm not very accustomed to and seems to me lacking of the "block" view which you would get with an "if then end if" syntax. I extremely appreciated the simplicity of the example and how well it describes what the hardware should do. Al From newsfish@newsfish Tue Aug 9 07:53:34 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Wed, 06 Jul 2011 19:22:02 +0200 Lines: 48 Message-ID: <97jjtqF89fU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <5606c1b2-9edc-41bd-ac66-1c76b0dcc9bb@u30g2000vby.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net UX7aHc8d0QekkrNBkCJ55QkbSg+vJgM0/428vI4dzWwfwYGHDE Cancel-Lock: sha1:wFBRBpkUyD9hzmiZE2UCvyaFvok= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <5606c1b2-9edc-41bd-ac66-1c76b0dcc9bb@u30g2000vby.googlegroups.com> X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5103 On 6/21/2011 12:46 AM, rickman wrote: > If the start signal is asserted and cleared independently of your FSM > then you need to design your machine to detect the assertion, not the > fact that it is asserted. When the FSM gets to the end of its work, > the start signal needs to be cleared before the FSM will trigger > again, in other words, enter a state where you wait for Start to be > false before you enter the state where it waits for Start to be > true. If you "detect the assertion" there's no need to wait anywhere, since you will need another "assertion". > > If the Start signal can be cleared by the FSM, then do that before > entering the state where it waits for the Start signal to be true. > Again if the FSM is designed to "detect the assertion" as you (and I also would) suggest, there's no need to do anything with it. > I can't say I understand your last part about stretching the Start > signal. It only needs to be true long enough for the FSM to see that > it is asserted. As long as that is two clock cycles, it is guaranteed > to be seen. Then you only need to see it cleared before you return to > the starting state waiting for Start to be true. Have you somehow > written your code so that if Start goes away the FSM resets? That > would be very bad and should be changed. If the start signal is asynchronous it should be first synchronized. Once it's synchronized, why the length should be two clock cycles to be seen? Why would it be bad if the start signal is used to start and reset the FSM? I agree the name would be absolutely wrong, since it should be called "enable". Certainly the reset should be synchronous. > > One other thought, the code you give that seems to be waiting for > nDRDY it treating nDRDY as a clock. Probably not a good idea unless > nDRDY is not guaranteed to be at least two clock cycles long. > I agree is a bad choice to use nDRDY as a clock, but I don't quite understand the argument of two clock cycles long, since there's no other clock in the process being nDRDY the only one. > Rick From newsfish@newsfish Tue Aug 9 07:53:34 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n5g2000yqh.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: wait for argument a variable? Date: Wed, 6 Jul 2011 13:16:01 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309983449 6011 127.0.0.1 (6 Jul 2011 20:17:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 20:17:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n5g2000yqh.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5104 Simple question: Can the argument in a "wait for (time)" be a variable? (in a test bench of course. not worried about synthesis) i.e. some_integer := 7 ... holdtime := 10 * some_integer * 1 us; wait for holdtime; From newsfish@newsfish Tue Aug 9 07:53:35 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r18g2000vbs.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Wed, 6 Jul 2011 16:08:38 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309993807 12765 127.0.0.1 (6 Jul 2011 23:10:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 23:10:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r18g2000vbs.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5105 On Jul 6, 4:16=A0pm, Shannon wrote: > Simple question: =A0Can the argument in a "wait for (time)" be a > variable? =A0(in a test bench of course. =A0not worried about synthesis) > > i.e. > some_integer :=3D 7 > ... > holdtime :=3D 10 * some_integer * 1 us; > wait for holdtime; Yes. KJ P.S. Wouldn't it be easier to just try this on a simulator rather than posting to a newsgroup? From newsfish@newsfish Tue Aug 9 07:53:35 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!e7g2000vbw.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: can any one help me in VHDL codes plz Date: Wed, 6 Jul 2011 16:10:09 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <9799d27d-12ec-485c-bcc3-dcbeecba9208@e7g2000vbw.googlegroups.com> References: <055fd9d3-c959-4b7f-8f1f-9d3c77cbf1e2@b21g2000yqc.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309993809 12771 127.0.0.1 (6 Jul 2011 23:10:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 23:10:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e7g2000vbw.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5106 On Jul 6, 3:51=A0am, majmoat_ensan wrote: > hi all, > > really i want a help in these 2 problems : > > 1) > I want a structural VHDL code of 1 to 16 Demultiplexers. with an > active low Enable signal using 1 to 2 Demultiplexer. [ use Generate > statement] > > __________________________________________________ ____________ > 2) > Also I need a structure and behavior VHDL code of 5-bits binary > counter with a synchronous load signal to preset the counter to a > specific initial state. the output of the counter ( Q0 to Q4) are > connected to a binary decoder that shows the state of the counter. What have you tried so far? What were the results? If you're just fishing for homework help, try a different pond where somebody must be silly enough to bite. KJ From newsfish@newsfish Tue Aug 9 07:53:35 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a10g2000vbz.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Wed, 6 Jul 2011 19:20:06 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> NNTP-Posting-Host: 75.37.3.30 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310005206 30073 127.0.0.1 (7 Jul 2011 02:20:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Jul 2011 02:20:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a10g2000vbz.googlegroups.com; posting-host=75.37.3.30; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5107 On Jul 6, 4:08=A0pm, KJ wrote: > On Jul 6, 4:16=A0pm, Shannon wrote: > > > Simple question: =A0Can the argument in a "wait for (time)" be a > > variable? =A0(in a test bench of course. =A0not worried about synthesis= ) > > > i.e. > > some_integer :=3D 7 > > ... > > holdtime :=3D 10 * some_integer * 1 us; > > wait for holdtime; > > Yes. > > KJ > > P.S. =A0Wouldn't it be easier to just try this on a simulator rather > than posting to a newsgroup? My professors always told me to ask questions in class. If I have a question likely others do too. Thank you for educating more than just me today. From newsfish@newsfish Tue Aug 9 07:53:35 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.albasani.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Thu, 07 Jul 2011 05:06:17 +0200 Lines: 38 Message-ID: <97km57Ftc7U1@mid.individual.net> References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 9bMIysIFuFZIt4kh6wx+fwSzLmHohCq85whSlPMfmH1AGs/CW+ Cancel-Lock: sha1:CE/sJAHoJ2c4OTqyFcS++d2610g= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5108 On 7/7/2011 4:20 AM, Shannon wrote: > My professors always told me to ask questions in class. If I have a > question likely others do too. Thank you for educating more than just > me today. Your professors are definitely right in telling you so and I am also very well convinced that none of your professors encouraged you to post a question on a newsgroup if the answer is readily available somewhere else or with some minor effort. In this context I strongly suggest you a couple of readings that will help you out building relationships in the community: from the comp.lang.vhdl FAQ: - http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#0.3 from an interesting link that you can also find in the FAQ but that I would like to underline as well: - http://www.catb.org/~esr/faqs/smart-questions.html#before For what concerns your question in particular, quoting the "IEEE Standard VHDL Language Reference Manual" (IEEE Std 1076, 2000 Edition): > The wait statement causes the suspension of a process statement or a procedure. > wait_statement ::= > [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ; > sensitivity_clause ::= on sensitivity_list > sensitivity_list ::= signal_name { , signal_name } > condition_clause ::= until condition > condition ::= boolean_expression > timeout_clause ::= for time_expression Since your variable/constant is of type TIME, your situation does follow the standard. Al From newsfish@newsfish Tue Aug 9 07:53:35 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b2g2000vbo.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Wed, 6 Jul 2011 20:23:15 -0700 (PDT) Organization: http://groups.google.com Lines: 54 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> NNTP-Posting-Host: 75.37.3.30 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310009115 4702 127.0.0.1 (7 Jul 2011 03:25:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Jul 2011 03:25:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b2g2000vbo.googlegroups.com; posting-host=75.37.3.30; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5109 wow. seriously? I'm being scolded for asking a simple question. REALLY?? I mean sorry to put you out. Sorry to massively affect the traffic in this NG. If it's beneath you to help then DON'T REPLY! Is this the way you really want to moderate this group? Sheesh. I apologize if my question was not up to your standards. P.S. seriously? On Jul 6, 8:06=A0pm, Alessandro Basili wrote: > On 7/7/2011 4:20 AM, Shannon wrote: > > > My professors always told me to ask questions in class. =A0If I have a > > question likely others do too. =A0Thank you for educating more than jus= t > > me today. > > Your professors are definitely right in telling you so and I am also > very well convinced that none of your professors encouraged you to post > a question on a newsgroup if the answer is readily available somewhere > else or with some minor effort. > > In this context I strongly suggest you a couple of readings that will > help you out building relationships in the community: > > from the comp.lang.vhdl FAQ: > > =A0-http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#0.3 > > from an interesting link that you can also find in the FAQ but that I > would like to underline as well: > > =A0-http://www.catb.org/~esr/faqs/smart-questions.html#before > > For what concerns your question in particular, quoting the "IEEE > Standard VHDL Language Reference Manual" (IEEE Std 1076, 2000 Edition): > > > The wait statement causes the suspension of a process statement or a pr= ocedure. > > wait_statement ::=3D > > [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_= clause ] ; > > sensitivity_clause ::=3D on sensitivity_list > > sensitivity_list ::=3D signal_name { , signal_name } > > condition_clause ::=3D until condition > > condition ::=3D boolean_expression > > timeout_clause ::=3D for time_expression > > Since your variable/constant is of type TIME, your situation does follow > the standard. > > Al From newsfish@newsfish Tue Aug 9 07:53:35 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.ripco.com!news.glorb.com!postnews.google.com!u26g2000vby.googlegroups.com!not-for-mail From: JB Newsgroups: comp.lang.vhdl Subject: Combined AFTER and WHEN statement Date: Thu, 7 Jul 2011 01:44:09 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <799412f6-d220-46c9-b513-52cb1263001e@u26g2000vby.googlegroups.com> NNTP-Posting-Host: 80.14.138.198 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310028250 2205 127.0.0.1 (7 Jul 2011 08:44:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Jul 2011 08:44:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u26g2000vby.googlegroups.com; posting-host=80.14.138.198; posting-account=S4wEMQoAAADRjpmXQT29euLGCs6HM3WR User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5110 Hi folks, I'm stuggling with a problem using the following VHDL syntax: <= WHEN ELSE AFTER WHEN ELSE AFTER WHEN ELSE ... ; My testbench was working well with modelsim 6.5. But my client wan't me to use modelsim 6.3, so I tried running it on that version and BOOM: This statement generates 'X' result on my target signal when one of the is true. Is this statement valid VHDL? or is modelsim 6.3 erroneous ? Thanks in adavance. From newsfish@newsfish Tue Aug 9 07:53:36 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!eb1g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Combined AFTER and WHEN statement Date: Thu, 7 Jul 2011 02:55:04 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <4d20acc8-9583-4cf3-8bcf-1ee24d93270e@eb1g2000vbb.googlegroups.com> References: <799412f6-d220-46c9-b513-52cb1263001e@u26g2000vby.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310034162 29051 127.0.0.1 (7 Jul 2011 10:22:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Jul 2011 10:22:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: eb1g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5111 Hi, I have tried the following test with Modelsim PE 10.0b, no problems. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test_when is end entity; architecture test of test_when is signal clk : std_logic := '0'; signal cnt : unsigned(2 downto 0) := (others => '0'); signal sig : std_logic := 'X'; begin clk <= (not clk) after 10 ns; cnt <= cnt + 1 when rising_edge(clk); sig <= '1' when cnt="000" else '0' after 1.5 ns when cnt="001" else 'Z' after 1.5 ns when cnt="010" else 'H'; end architecture; Cheers, hssig From newsfish@newsfish Tue Aug 9 07:53:36 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Thu, 7 Jul 2011 21:04:04 -0700 Organization: A noiseless patient Spider Lines: 68 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> Injection-Date: Fri, 8 Jul 2011 04:04:38 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="7532"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+da6xgWb7fBT7DGGoJoLimhTfOGIJ89Q8=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:KrmJPJ3PWRT1o1UisWMiR/HLNq0= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5112 "Alessandro Basili" wrote in message news:97jgiiFe8vU1@mid.individual.net... > On 6/25/2011 7:30 PM, logic_guy wrote: >> TYPE states is (IDLE, S1, S2, S3, S4); >> SIGNAL state : _states; >> SIGNAL nDRDY_1, nDRDY_2, start : std_logic; >> >> start <= NOT nDRDY_1 and nDRDY_2; >> >> clk_proc: PROCESS >> BEGIN >> WAIT until rising_edge(clk); >> nDRDY_1 <= nDRDY; >> nDRDY_2 <= nDRDY_1; >> CASE state is >> WHEN IDLE => If start='1' >> state <= S1; >> end if; >> WHEN S1 => -- Do state 1 processing here >> -- when done: >> state <= S2; >> WHEN S2 => -- Do state 2 processing here >> -- when done: >> state <= S3; >> WHEN S3 => -- Do state 3 processing here >> -- when done: >> state <= S4; >> WHEN S4 => -- Do state 4 processing here >> -- when done: >> state <= IDLE; >> -- Add or subtract states as needed >> END CASE; >> END PROCESS; >> > > I would put start in the process to have it clocked. This would avoid > any racing problems between nDRDY_1 and nDRDY_2. It is not necessary to put "start" in the process because it is the AND of nDRDY_1 and nDRDY_2, which are clocked by "clk", so "start" is already synchronized with "clk". Also, "start" should not have any glitches on it the way it is generated in the example. Even if it did, glitches are no problem in a synchronous system as long as the longest latch-to-latch path delay is less than the clock period. > The clause "when others =>" should also be added, to land always on a > "safe" state. An "others" clause is not needed here since "state" is defined with exactly 5 states, so there are no other states. If you did put an "others" clause there some tools would give you a warning that the "others" clause is unreachable. > I would also honor the OP choice of naming, being the start the input > signal to this component. > > Last comment is on the choice of the structure "WAIT until" which I'm > not very accustomed to and seems to me lacking of the "block" view > which > you would get with an "if then end if" syntax. "WAIT until rising_edge(clk);" is a perfectly legitimate way of specifying the clock of a clocked process and is simpler to code than the "if then end if" syntax. I work on a team that has been designing large, multi-million gate ASICs for years and we have 100,000's of lines of VHDL coded like that. Charles From newsfish@newsfish Tue Aug 9 07:53:36 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Fri, 08 Jul 2011 07:02:02 +0200 Lines: 43 Message-ID: <97nha9FtquU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net vbF2UkCAKNA0EVYwHdq9XQODiexpP6p63zSwH8guwuc8r6RlL7 Cancel-Lock: sha1:N/vAySpnoQTezb/zTpPeseeM7bk= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5113 On 7/8/2011 6:04 AM, logic_guy wrote: > "Alessandro Basili" wrote in message >> I would put start in the process to have it clocked. This would avoid >> any racing problems between nDRDY_1 and nDRDY_2. > It is not necessary to put "start" in the process because it is the AND > of nDRDY_1 and nDRDY_2, which are clocked by "clk", so "start" is > already synchronized with "clk". Also, "start" should not have any > glitches on it the way it is generated in the example. Even if it did, > glitches are no problem in a synchronous system as long as the longest > latch-to-latch path delay is less than the clock period. > Indeed, my bad! >> The clause "when others =>" should also be added, to land always on a >> "safe" state. > An "others" clause is not needed here since "state" is defined with > exactly 5 states, so there are no other states. If you did put an > "others" clause there some tools would give you a warning that the > "others" clause is unreachable. > Depending on the encoding (onehot, gray, etc.) the number of FF you are going to use certainly gives you more than 5 states (32 for onehot, 8 for gray). How the synthesizer is going to know what to do in case your FF are presenting a state that is not among the 5? But maybe you care if a bit flip will put your FSM in a state out of which it cannot get out. > "WAIT until rising_edge(clk);" is a perfectly legitimate way of > specifying the clock of a clocked process and is simpler to code than > the "if then end if" syntax. I'm not blaming the illegitimacy of the statement, I simply dislike it as to me it lacks of readability and as well the possibility to include an asynch reset to the process. If you can post a snippet of a code including an asynch reset I would appreciate. > > Charles > > From newsfish@newsfish Tue Aug 9 07:53:36 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!34g2000yqr.googlegroups.com!not-for-mail From: r_hwdesigner Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: job offer fpga designer genova Date: Fri, 8 Jul 2011 01:28:11 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <4f2117d3-637b-4133-bf81-67e16e05744e@34g2000yqr.googlegroups.com> NNTP-Posting-Host: 79.15.85.115 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310113766 24185 127.0.0.1 (8 Jul 2011 08:29:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Jul 2011 08:29:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 34g2000yqr.googlegroups.com; posting-host=79.15.85.115; posting-account=4cNljQoAAADEztxJHxlcD1P5IeazTZCn User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; CMNTDF; .NET4.0C; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:15859 comp.lang.vhdl:5114 comp.lang.verilog:3110 we are looking for an fpga designer in Genova with the following knowledges: Operating systems Windows, Linux Programming Languages VHDL, verilog, System Verilog, C++ Tools FPGA synthesis (Precision RTL Mentor, Synplify Synplicity) FPGA verification (QuestaSim, Modelsim) FPGA implementation (QuartusII Altera, ISE Xilinx) Matlab/Simulink Versioning control (Clearcase) Competences, Skills Development of digital communication systems with ASIC/FPGA Verification of implemented functions with development of testbench and test patterns Knowledge of static timing analysis concepts (multi-clock domains, exceptions analysis) Team working capability Languages English (good in writing & speaking) From newsfish@newsfish Tue Aug 9 07:53:36 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: one signal set from two processes ..... Newsgroups: comp.lang.vhdl Date: Fri, 08 Jul 2011 14:11:27 +0200 References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 29 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1310127087 news2.news.xs4all.nl 21846 puiterl/195.242.97.150:33613 Xref: feeder.eternal-september.org comp.lang.vhdl:5115 Alessandro Basili wrote: >> "WAIT until rising_edge(clk);" is a perfectly legitimate way of >> specifying the clock of a clocked process and is simpler to code than >> the "if then end if" syntax. > > I'm not blaming the illegitimacy of the statement, I simply dislike it > as to me it lacks of readability For me readability is the main reason for using and promoting to use "WAIT UNTIL clk='1'" (or "WAIT UNTIL rising_edge(clk)"). As soon as I see "WAIT UNTIL clk='1'", I know that I need not look further to see what kind of process it is. It is a pure clocked process without any asynchronicities. Another (visual/layout) advantage is the lack of a long stretched if-end-if statement, which eats up indentation as well. > and as well the possibility to include > an asynch reset to the process. If you can post a snippet of a code > including an asynch reset I would appreciate. That is not possible with the WAIT statement. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:36 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Fri, 8 Jul 2011 08:20:47 -0700 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> Injection-Date: Fri, 8 Jul 2011 15:22:06 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="3710"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ZareYcqkzbTt+rOwPCfFy0BR9RjHraa4=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:ABlXL2DPZaq6ObY4HykVE8UxhHk= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5116 "Paul Uiterlinden" wrote in message news:4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl... > For me readability is the main reason for using and promoting to use > "WAIT > UNTIL clk='1'" (or "WAIT UNTIL rising_edge(clk)"). > > As soon as I see "WAIT UNTIL clk='1'", I know that I need not look > further > to see what kind of process it is. It is a pure clocked process > without any > asynchronicities. > > Another (visual/layout) advantage is the lack of a long stretched > if-end-if > statement, which eats up indentation as well. > My sentiments exactly. Also, regarding asynchronous resets, those should be avoided wherever possible. The logic team I work with is just finishing an ASIC with over 900,000 latches. Only a very small handful of those have asynchronous resets. That was for a case where some logic needed to be reset when the clock wasn't running. Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:36 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t5g2000yqj.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Fri, 8 Jul 2011 09:08:51 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310141331 11707 127.0.0.1 (8 Jul 2011 16:08:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Jul 2011 16:08:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t5g2000yqj.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5117 On Jul 8, 1:02=A0am, Alessandro Basili wrote: > On 7/8/2011 6:04 AM, logic_guy wrote: > >> The clause "when others =3D>" should also be added, to land always on = a > >> "safe" state. > > An "others" clause is not needed here since "state" is defined with > > exactly 5 states, so there are no other states. =A0If you did put an > > "others" clause there some tools would give you a warning that the > > "others" clause is unreachable. > > Depending on the encoding (onehot, gray, etc.) the number of FF you are > going to use certainly gives you more than 5 states (32 for onehot, 8 > for gray). How the synthesizer is going to know what to do in case your > FF are presenting a state that is not among the 5? > But maybe you care if a bit flip will put your FSM in a state out of > which it cannot get out. > The synthesis tool default is not to implement safe state machines (i.e. ones that return to a particular state if it ever gets into an 'illegal' state). Unless you play with that synthesis tool setting you will not get 'safe state machines'. In particular, you will not get 'safe state machines' regardless of how the FSM states are encoded. But don't take my word for it, try your own state machine with and without an otherwise unreachable 'when others' clause, and you should see that you get the same implementation regardless of state bit encoding...or likely regardless of any other settings other than the tool control specifically for implementing safe state machines. As a parting note, the causes for getting into an illegal state are: - Timing problem - SEU In neither of these situations would it be likely that the correct course of action would be to simply go to some arbitrary reset state. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:37 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Sat, 09 Jul 2011 07:23:25 +0200 Lines: 51 Message-ID: <97q6udF98pU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net qlvFxEW6r5nx7U8SnJ219g/vMXYmco6OF0WEbVv6/ByKpChski Cancel-Lock: sha1:UPT35aP6qgYSr0whXIPEtSHY3Vs= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5118 On 7/8/2011 6:08 PM, KJ wrote: > The synthesis tool default is not to implement safe state machines > (i.e. ones that return to a particular state if it ever gets into an > 'illegal' state). > Indeed I used to turn on the "safe" mode in Synplify to have what I "wanted". > Unless you play with that synthesis tool setting you will not get > 'safe state machines'. In particular, you will not get 'safe state > machines' regardless of how the FSM states are encoded. But don't > take my word for it, try your own state machine with and without an > otherwise unreachable 'when others' clause, and you should see that > you get the same implementation regardless of state bit encoding...or > likely regardless of any other settings other than the tool control > specifically for implementing safe state machines. > And indeed the tool tends to optimize away all the "unnecessary" FF regardless of the encoding. What I did not know is that in the "safe" mode the 'when others' clause is not really followed the way it is written and Synplify will resolve the illegal state to the reset state, whether it is asynchronous or synchronous: > http://klabs.org/richcontent/software_content/safe_state_machines_synplify_1.pdf To force the tool to follow the 'when others' clause it is suggested to turn off the the FSM compiler. At this point the 'when others' clause will be exactly followed (provided the "enumerated type" is changed with constants [why???]). > As a parting note, the causes for getting into an illegal state are: > - Timing problem > - SEU > > In neither of these situations would it be likely that the correct > course of action would be to simply go to some arbitrary reset state. > Assuming the design has gone through timing analysis, the SEU is really a concern that in some applications may get you in troubles. That is why some communication protocols for space applications (ex. spacewire) can recover if the FSM fail over the reset state, causing the link on both sides to an "exchange of silence" procedure that will restore communication. I do agree that some time a "safe" state maybe safe from the FSM point of view but system wise doesn't help that much, unless every part of the design is designed to tolerate it. Al From newsfish@newsfish Tue Aug 9 07:53:37 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Sat, 09 Jul 2011 19:36:31 +0100 Organization: A noiseless patient Spider Lines: 37 Message-ID: <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="14925"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+27ewa7vgP6xijzqdcEjYgrJv20JOz8UM=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:mquP4mwOAkBTJqIS3LeSG7Y7mIg= Xref: feeder.eternal-september.org comp.lang.vhdl:5119 On Thu, 07 Jul 2011 05:06:17 +0200, Alessandro Basili wrote: >from an interesting link that you can also find in the > FAQ but that I would like to underline as well: > > - http://www.catb.org/~esr/faqs/smart-questions.html#before Whoa. First off, what's "not smart" about the OP's question? It shows inquiry, interest, and a reasonable grasp of the basics. Looks fine to me. How many VHDL users do _you_ know who can tell you the _full_ story about the wait statement? It's complicated and subtle. Second, let's not get too hung up about Eric Raymond's priggish and defensive protection of his chosen tribe of hackers. As usual with his stuff, you'll find much wisdom in that article - but also much that irritates and makes little sense outside the self-satisfied community of hackers. Take with a pinch of salt. Sure, the OP could have found the answer for himself. But KJ's suggestion that he try it in a simulator is disingenuous: tools have bugs, and sometimes support non-LRM-conforming constructs because some big customer demanded it, so that's not a safe way to decide what's OK and what's not. And the VHDL LRM is a very densely written and highly technical document; it's usually easier to ask an expert than to ask the LRM, especially if you're not an experienced LRM wonk. To Shannon: yes, wait-for can be given an arbitrary expression provided it yields a result of type "time". The expression is computed at the moment execution hits the wait statement, and its value determines the wait behaviour. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:37 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u2g2000yqb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Sat, 9 Jul 2011 18:32:42 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310261675 25611 127.0.0.1 (10 Jul 2011 01:34:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 10 Jul 2011 01:34:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u2g2000yqb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5120 On Jul 9, 2:36=A0pm, Jonathan Bromley wrote: > > Sure, the OP could have found the answer for himself. =A0 > But KJ's suggestion that he try it in a simulator is > disingenuous: Perhaps you should re-read my post. I answered the OP's question straight off, clearly, concisely and politely. As a postscript, I simply suggested that it would likely be easier to simply try the idea out rather than posting to a newsgroup and waiting for an answer (and did not write it in a way that suggested that the question was somehow beneath the standards of the group). As I did in this case, there are many times in the past when I've suggested that people try it out for themselves. That is sound advice. Trying and doing for yourself in almost all cases makes for a better learning experience than simply reading the words of others. Not only that, but sometimes you find that people post rubbish...but the way that you find out that it is rubbish is by actually trying it out for yourself. You stating that I was being disingenuous when I wasn't seems to show that you got torqued by Basili's response and decided to take it out on both him and me. You likely know the saying about 'Give a man a fish...'. I gave the OP the fish as well as a lesson in fishing. > tools have bugs, and sometimes support > non-LRM-conforming constructs because some big customer > demanded it, so that's not a safe way to decide what's > OK and what's not. You're off on a tangent here...but OK. But let me also point out that in the situations you just described the *only* way to demonstrate the bug or non-conformance is to *use* the tool. > And the VHDL LRM is a very densely > written and highly technical document; it's usually > easier to ask an expert than to ask the LRM, especially > if you're not an experienced LRM wonk. > I agree, but will add - Many times an 'expert' comes in the form of software that can be queried rather than the response from a human. - The human can also be in error as well whether or not they are an 'expert' or not. Learning can come about in many ways, don't discount any method...unless it has really been shown to be a poor learning method, or a method that just simply doesn't work for you. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:37 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Sun, 10 Jul 2011 10:48:16 +0100 Organization: A noiseless patient Spider Lines: 38 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="12386"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19NWa4sexXuplDBQ40zG5utVEYbnPp4o7Y=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:j8PEZHFrBtPF+3l5zPOh1WI3Tow= Xref: feeder.eternal-september.org comp.lang.vhdl:5121 On Sat, 9 Jul 2011 18:32:42 -0700 (PDT), KJ wrote: >As a postscript, I simply suggested that it would likely be easier to >simply try the idea out rather than posting to a newsgroup and waiting >for an answer (and did not write it in a way that suggested that the >question was somehow beneath the standards of the group). Accepted. > You stating that I was being disingenuous when I >wasn't seems to show that you got torqued by Basili's response and >decided to take it out on both him and me. Could be, although I still think it's worth pointing out the possible weakness in "trying it out" as a way of checking whether something is legal in the language. I would never dispute that experiment is a valuable learning tool, though. >- Many times an 'expert' comes in the form of software that can be >queried rather than the response from a human. >- The human can also be in error as well whether or not they are an >'expert' or not. All entirely true. We're in a field where Stuff Is Complicated, and any source of information - experts, commonsense, software, even the LRM - can be flawed by human error. Oftentimes the answer is simple, unambiguous and pretty much universally agreed. But you need to be on your guard for those few places where something goes wrong. For context, and as an excuse: I'm struggling right now (along with a lot of colleagues) on migrating a large codebase from one tool to another, and finding that their LRM conformance is imperfect. So I'm a tad sensitive about such things. Should mention, though, that my woes are with SystemVerilog. VHDL is much better specified and less messy. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:37 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news2.arglkargh.de!news.wiretrip.org!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sun, 10 Jul 2011 15:00:31 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 20 Message-ID: <4e19a270$0$14260$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 22b74744.news.skynet.be X-Trace: 1310302832 news.skynet.be 14260 91.177.121.47:36527 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:5122 On 07/10/2011 11:48 AM, Jonathan Bromley wrote: > > For context, and as an excuse: I'm struggling right now (along > with a lot of colleagues) on migrating a large codebase from > one tool to another, and finding that their LRM conformance > is imperfect. So I'm a tad sensitive about > such things. Should mention, though, that my woes are with > SystemVerilog. VHDL is much better specified and less messy. Are you also struggling with LRM-compliant but different behavior among tools? (As fas as I can tell, SystemVerilog has produced even more opportunities for nondeterministic races than Verilog.) -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Tue Aug 9 07:53:37 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Mon, 11 Jul 2011 11:07:52 +0100 Organization: TRW Conekt Lines: 38 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net xEQerKwXI2JdTRYbeGrtRweXus1ayQ5TUzMEb9XvElU4kuccI= Cancel-Lock: sha1:qkGF8gfDxeLxxsJXsReagNnttvo= sha1:lZPKQstxsS+Xjci0EVFh2Lyu6AU= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5123 Paul Uiterlinden writes: > Alessandro Basili wrote: >> and as well the possibility to include >> an asynch reset to the process. If you can post a snippet of a code >> including an asynch reset I would appreciate. > > That is not possible with the WAIT statement. It sort of is... but it's unpleasant in various ways: process is begin -- do_reset things here wait until reset = '0'; -- wait until reset goes away main : loop wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; -- do one set of things wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; -- do another set of things -- etc.. repeat long wait until line as many times as necessary end loop; end process; Also on "inferred state machines": http://parallelpoints.com/node/69 (apologies to Chrome users, the code wraps rather than providing scroll-bars like in Firefox. I haven't figured out why yet) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Aug 9 07:53:38 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Mon, 11 Jul 2011 15:23:23 +0200 Lines: 102 Message-ID: <980bq7Fpl5U1@mid.individual.net> References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 8VvSpZlFiq8dc3tBdbwoLQ7jym7ohZbHptNRbg/kR/FVrhazTq Cancel-Lock: sha1:4ugfU58CPf36XVxf49pTbJQJs8g= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5124 On 7/9/2011 8:36 PM, Jonathan Bromley wrote: > On Thu, 07 Jul 2011 05:06:17 +0200, Alessandro Basili wrote: > >>from an interesting link that you can also find in the >> FAQ but that I would like to underline as well: >> >> - http://www.catb.org/~esr/faqs/smart-questions.html#before > > Whoa. First off, what's "not smart" about the OP's > question? It shows inquiry, interest, and a reasonable > grasp of the basics. Looks fine to me. How many VHDL > users do _you_ know who can tell you the _full_ story > about the wait statement? It's complicated and subtle. > I have never qualified the question as "not smart" (it's not my fault if the link name is called that way) and indeed I took the time to point out a reference (in this case the LRM) to solve the OP's doubt. My point was rather about the method than the subject. I never talked about "standards" of any question, but I felt that the OP confused the newsgroup with her class: > My professors always told me to ask questions in class. If I have a > question likely others do too. Thank you for educating more than just > me today. which IMHO is not true. Therefore the suggestions to follow the NG's FAQs. > Second, let's not get too hung up about Eric Raymond's > priggish and defensive protection of his chosen tribe > of hackers. As usual with his stuff, you'll find much > wisdom in that article - but also much that irritates > and makes little sense outside the self-satisfied > community of hackers. Take with a pinch of salt. > I do agree that *everything* should be taken with a pinch of salt, even the words of an expert that share his wisdom or simply his point of view. I find Eric Raymond's article quite to the point when he talks about doing something "before you ask", that is why I pointed out the link to that paragraph. If you are concerned that Eric Raymond's article does not embody the spirit of this NG I would probably be on the same boat, nevertheless I take it with the grain of salt it needs to extract any useful information from the noise of nowadays communications. If you think the quoted article is disrespectful and should be removed from the FAQs of this NG than probably we need to face this issue more intensively and I encourage you to send your comments to the editor of the FAQ: > edwin@ds.e-technik.uni-dortmund.de (Edwin Naroska) or maybe open a dedicated thread (which can be ignored by people not interested). > Sure, the OP could have found the answer for himself. That is why I also pointed out the "try yourself first" approach reported in Raymond's article. This approach is surely the most powerful even though potentially very dangerous, since we can be deceived by the fact that "it worked" and miss the grasp on the problem. I doubt though the OP was interested in your mentioned complicated and subtle nuances of the "wait statement". She showed interest in a case where the wait statement was involved and the time expression was a variable of TIME type and that's it (or at least I didn't catch anything between the lines). > But KJ's suggestion that he try it in a simulator is > disingenuous: tools have bugs, and sometimes support > non-LRM-conforming constructs because some big customer > demanded it, so that's not a safe way to decide what's > OK and what's not. And the VHDL LRM is a very densely > written and highly technical document; it's usually > easier to ask an expert than to ask the LRM, especially > if you're not an experienced LRM wonk. Do you really believe the OP would have asked the question if she went through a simulator without any problem? And what is the added value of an expert with the respect to a tool which is used by tons of users who are actively reporting all sorts of bugs? On top of it the OP didn't ask: > Can the argument in a "wait for (time)" be a > variable? since the simulator XYZ is giving me an error of type 123. which would have been much more appropriate, showing the interest of the OP to solve his/her problem and triggering the possibility for a "bug report". I found KJ's suggestion rather to the point and I admit I got a little shaky myself on the OP's reply to that post when she disingenuously wrote about her professors. I do not argue the value of the question, but I do disagree with the process the OP chose to learn something. Have I been too rude? Did I hurt somebody's feeling? Well I didn't intend to, but I do believe the NG is a valuable resource for people to learn, stimulating thoughts and doubting answers, in a process that foster searches and exchange of point of views and I did not read any of the former in the OP's first intent. Al From newsfish@newsfish Tue Aug 9 07:53:38 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Mon, 11 Jul 2011 17:07:58 +0200 Lines: 65 Message-ID: <980huaF95fU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 4r1ON0D3uWuNEmH6juQF+Q0Zk1Kd3z8xFmGgGfMVNSMsVdJYbc Cancel-Lock: sha1:dM+Fp+QC8/Ws/AnVAQYLhyQcUdg= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5125 On 7/11/2011 12:07 PM, Martin Thompson wrote: [...] > process is > begin > -- do_reset things here > wait until reset = '0'; -- wait until reset goes away > main : loop > wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; > -- do one set of things > wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; > -- do another set of things > -- etc.. repeat long wait until line as many times as necessary > end loop; > end process; > Isn't the "exit main when reset = '1'" a synchronous reset? The way I read is the following: - wait until rising_edge(clk) and then - if reset = '1' exit the main loop. Am I wrong (*)? > Also on "inferred state machines": > > http://parallelpoints.com/node/69 > very interesting approach. And I do share the same view when you say: > it saves you having to think of names for your states since IMHO what is more critical is the condition under which an FSM moves from one state to the other, rather than the state itself. The suggestion to move at a higher level of description and leave the synthesizer infer whatever is needed to perform the functionality described is the right way of exploiting the language. Too many times we loose ourselves amongst gates and flops forgetting the big picture. Two comments though: - giving the impression that "less code is usually good" is a misconception (as Nemo's father would say about clownfish). Being on the defense line "the smaller the better" usually drives designers to write unreadable and therefore unmaintainable code. - comparing vhdl with C# in terms of lines of code is risky. Hardware acceleration is nothing related to the lines of code and its main goal is to search for tasks in the sequential (and/or multi-threaded) computing that can be performed in parallel by an external device (or additional dedicated CPU) in the hope of being more efficient (number of computations/cycle). Nothing related to lines of code. > (apologies to Chrome users, the code wraps rather than providing scroll-bars > like in Firefox. I haven't figured out why yet) > Didn't work for me as well, but found the following: http://code.google.com/p/chromium/issues/detail?id=10533 even though they claim they fixed this problem... (*) my apologies I cannot try it out myself...reinstalling my pc! :-( From newsfish@newsfish Tue Aug 9 07:53:38 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h14g2000yqd.googlegroups.com!not-for-mail From: Nikolaos Kavvadias Newsgroups: comp.lang.vhdl Subject: [ANN] HercuLeS high-level synthesis tool Date: Mon, 11 Jul 2011 08:35:51 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: <955f8beb-c212-4091-bcc8-b30e2d2502f3@h14g2000yqd.googlegroups.com> NNTP-Posting-Host: 94.70.55.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310398726 14318 127.0.0.1 (11 Jul 2011 15:38:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Jul 2011 15:38:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h14g2000yqd.googlegroups.com; posting-host=94.70.55.49; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5126 Hi everyone i'm pleased to announce that after two years (and about 2000 man- hours), the HercuLeS high-level synthesis tool is ready for non- trivial work. HercuLeS allows you to synthesize ANSI C code (certain rules apply) to RTL VHDL. HercuLeS is named after the homonymous constellation and not after the demigod. You can find information on HercuLeS here: http://www.nkavvadias.com/hercules/index.html Some of its features: 1. Integer and fixed-point (VHDL-2008) arithmetic of arbitrary lengths 2. It is able to synthesize VHDL from code spanning across several C functions 3. Support for both the Synopsys "de-facto standard" libraries and the official IEEE standard libraries 4. Support of synchronous read ROM and RAM memories (directly mapped to FPGA block RAMs) 5. Functions can pass single-dimensional array arguments 6. Support of streaming outputs (producing a sample at a time) You can either code your input in ANSI C or in a bit-accurate typed- assembly language called NAC (N-Address Code). Then, your input is converted to a series of CDFGs (Control/Data Flow Graphs), expressed as Graphviz graphs with user-defined attributes, which again are translated to VHDL code adhering to the FSMD (Finite-State Machine with Datapath) paradigm. I would appreciate if you had a look at the sample files available at the website. They illustrate complete examples of automatically synthesized algorithms such as Bresenham's line drawing algorithm, and the Sieve of Eratosthenes. Overall, eight complete examples can be found at the HercuLeS website. There will be regular updates on the HercuLeS webpage (every 1-1.5 months). The October update, scheduled for 2011/10/11, will allow access to HercuLeS via a web interface! But first I would appreciate feedback on whatever related to the HercuLeS webpage. Best regards, Nikolaos Kavvadias Lecturer, Research Scientist, Hardware developer, Ph.D., M.Sc., B.Sc. From newsfish@newsfish Tue Aug 9 07:53:38 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.mixmin.net!feeder.news-service.com!postnews.google.com!r27g2000prr.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Synthesis of 'X' Date: Mon, 11 Jul 2011 09:28:19 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <16abce21-841a-4b51-a8c9-ac24397dc235@r27g2000prr.googlegroups.com> NNTP-Posting-Host: 67.188.14.18 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310401700 11999 127.0.0.1 (11 Jul 2011 16:28:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Jul 2011 16:28:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r27g2000prr.googlegroups.com; posting-host=67.188.14.18; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5127 Hello, Is there a standard way in which the value 'X' assigned to a signal gets synthesized? I would assume that it would just trigger a synchronous LUT reset. Thanks, Colin From newsfish@newsfish Tue Aug 9 07:53:38 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!z14g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of 'X' Date: Mon, 11 Jul 2011 09:48:03 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <16abce21-841a-4b51-a8c9-ac24397dc235@r27g2000prr.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310402884 23878 127.0.0.1 (11 Jul 2011 16:48:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Jul 2011 16:48:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z14g2000yqh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5128 On Jul 11, 12:28=A0pm, Colin Beighley wrote: > Hello, > > Is there a standard way in which the value 'X' assigned to a signal > gets synthesized? > Since 'X' is the result of driving '0' and '1' together I would hope that this would not be synthesizable. I'm guessing though that you mean 'X' as a "don't care". In that case, I don't think there is a 'standard', but the synthesis tools will report to you what they are using when they come across your use of 'X'. However, you mentioned X getting assigned to a signal which implies you mean sig <=3D 'X'; Maybe you meant a don't care which is sig <=3D '-'; In either case, you're at the mercy of the synthesis tools which as I mentioned should report what value it is using for 'X' or '-'. > I would assume that it would just trigger a synchronous LUT reset. > Wow...that is not at all what I would assume. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:38 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l28g2000yqc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of 'X' Date: Tue, 12 Jul 2011 00:47:38 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <2ac48be7-58da-4add-9af9-d112a34b43c2@l28g2000yqc.googlegroups.com> References: <16abce21-841a-4b51-a8c9-ac24397dc235@r27g2000prr.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310457748 26911 127.0.0.1 (12 Jul 2011 08:02:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Jul 2011 08:02:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l28g2000yqc.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5129 On Jul 11, 5:28=A0pm, Colin Beighley wrote: > Hello, > > Is there a standard way in which the value 'X' assigned to a signal > gets synthesized? > > I would assume that it would just trigger a synchronous LUT reset. > > Thanks, > Colin Given that LUTs are not even resettable, I dont know how you'd come to this conclusion. 'X's should only ever be used to indicate a problem in simulation, like this: if en =3D '1' then output <=3D a; elsif en =3D '0' then output <=3D 'b; else output <=3D (others =3D> 'X'); end if; If you really mean dont care, its not until recently that the language had much support for dont care ('-', not 'X'). now, in VHDL you can use them in case statements, but thats about it afaik. Before VHDL 2008 it would literally compare the string to dont care, so even if the bits were '1' or '0', the test would fail. now you can write: case? s is when "00--" =3D> --do something with MSBs =3D 0 when "001-" =3D> --etc. From newsfish@newsfish Tue Aug 9 07:53:39 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Tue, 12 Jul 2011 09:46:37 +0100 Organization: TRW Conekt Lines: 88 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> <980huaF95fU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net AMKRvLDU/0oMhuHMFwniFArdEcTozfSqWedqeqLtJMMqMrekw= Cancel-Lock: sha1:UqmbZTu7aAtCdarbDdzikCul7Lk= sha1:So7bDxCqCJyLxJhKuh9LYrGgNl8= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5130 Alessandro Basili writes: > On 7/11/2011 12:07 PM, Martin Thompson wrote: > [...] >> process is >> begin >> -- do_reset things here >> wait until reset = '0'; -- wait until reset goes away >> main : loop >> wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; >> -- do one set of things >> wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; >> -- do another set of things >> -- etc.. repeat long wait until line as many times as necessary >> end loop; >> end process; >> > > Isn't the "exit main when reset = '1'" a synchronous reset? The way I > read is the following: > > - wait until rising_edge(clk) and then wait until rising_edge(clk) or falling_edge(reset) ^^^^^^^^^^^^^^^^^^^^^^ > - if reset = '1' exit the main loop. > > Am I wrong (*)? > reset is also "in the sensitivity list" of the wait statement. >> Also on "inferred state machines": >> >> http://parallelpoints.com/node/69 >> > > very interesting approach. And I do share the same view when you say: > >> it saves you having to think of names for your states > > since IMHO what is more critical is the condition under which an FSM > moves from one state to the other, rather than the state itself. > The suggestion to move at a higher level of description and leave the > synthesizer infer whatever is needed to perform the functionality > described is the right way of exploiting the language. Too many times we > loose ourselves amongst gates and flops forgetting the big picture. > > Two comments though: > > - giving the impression that "less code is usually good" is a > misconception (as Nemo's father would say about clownfish). Being on the > defense line "the smaller the better" usually drives designers to write > unreadable and therefore unmaintainable code. > Yes, it always needs some common-sense applying. But note that I didn't say "smaller is better". "Less code is *usually* good". A much weaker assertion :) > - comparing vhdl with C# in terms of lines of code is risky. Oh, yes of course - it's not meant to be much more than a pseudo-academic "playing with possibilities". My original motivation was simply in response to the originally presented HDL solution to show that the VHDL *could* look much like the C# approach. (Bar the horrible-ness of the clocking construct). But I also feel that "lines of code" is not a metric to be completely discarded. > Hardware acceleration is nothing related to the lines of code and its > main goal is to search for tasks in the sequential (and/or > multi-threaded) computing that can be performed in parallel by an > external device (or additional dedicated CPU) in the hope of being > more efficient (number of computations/cycle). Nothing related to > lines of code. No, but if you can (readably!) do the same thing in many less lines of code, that's a win, surely? LOC matters not to the machine, but it is still a significant metric to the programmer/designer, and even more so to the reviewers of said code. Cheers, Martin (all his own opinions) From newsfish@newsfish Tue Aug 9 07:53:39 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of 'X' Date: Tue, 12 Jul 2011 12:34:33 +0100 Organization: TRW Conekt Lines: 39 Message-ID: References: <16abce21-841a-4b51-a8c9-ac24397dc235@r27g2000prr.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 8xk9MUrOp6IVKv8HpJ3Y5Akznywo1BmtSgYnUbwImIaAXfRyA= Cancel-Lock: sha1:RQQUvsJV125zWrkru/E+SEuQnEQ= sha1:wlK2KfS2q6vjysoS8j9kUeeM3QA= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5131 Colin Beighley writes: > Hello, > > Is there a standard way in which the value 'X' assigned to a signal > gets synthesized? 'X' tends not to be assigned to signals directly - it's the result of driving a '0' and a '1' at the same time. You *can* assign it yourself, and synthesis tools *may* treat it as a don't care. (If you want a don't care, '-' is the VHDL value which you can assign to a signal/variable. Synthesis tools (IME) will treat it properly and use that knowledge to optimise logic. Be aware that the normal '=' operator doesn't work that way though - you have to use std_match) > > I would assume that it would just trigger a synchronous LUT reset. > That's an interesting assumption on a few counts: 1) The LUTs are not synchronous 2) *Assuming* you meant a flipflop, the synchronous (or not) nature of a write to a signal depends on the context in which it's written, not the value that's written. 3) *Assuming* 'X' were to be representable and assigned in a clocked process, would the flipflop not just take the value 'X' (as in simulation) and propagate it to the output? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Aug 9 07:53:39 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Tue, 12 Jul 2011 15:20:09 +0200 Lines: 32 Message-ID: <983004F8p9U1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> <980huaF95fU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net IIXPQJ7VH/EbEHgkrVJFpwBPVBSwk1eJqYqhLvUQjsNjRJ8l5j Cancel-Lock: sha1:wafoGooBJb/GbHaEqOTAYRYdLvw= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5132 On 7/12/2011 10:46 AM, Martin Thompson wrote: > Alessandro Basili writes: > >> On 7/11/2011 12:07 PM, Martin Thompson wrote: >> [...] >>> process is >>> begin >>> -- do_reset things here >>> wait until reset = '0'; -- wait until reset goes away >>> main : loop >>> wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; >>> -- do one set of things >>> wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; >>> -- do another set of things >>> -- etc.. repeat long wait until line as many times as necessary >>> end loop; >>> end process; >>> >> >> Isn't the "exit main when reset = '1'" a synchronous reset? The way I >> read is the following: >> >> - wait until rising_edge(clk) and then > > wait until rising_edge(clk) or falling_edge(reset) > ^^^^^^^^^^^^^^^^^^^^^^ > I was much too distracted by the "exit main when reset = '1';" that I totally miss that! Uhm, talking about readability I do admit the reader sometimes has his/her own responsability :-) My apologies. From newsfish@newsfish Tue Aug 9 07:53:39 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!uio.no!news.ctrl-c.liu.se!nntp Newsgroups: comp.emacs, comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Message-ID: From: Andreas Ehliar Date: 12 Jul 11 17:47:10 CEST Followup-To: comp.emacs, comp.lang.vhdl References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> Nntp-Posting-Host: sabor.isy.liu.se User-Agent: slrn/0.9.8.1pl1 (Linux) Lines: 107 Xref: feeder.eternal-september.org comp.emacs:4013 comp.lang.vhdl:5133 On 2011-06-27, Philippe Faes wrote: > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" Well, I think I could characterize myself as a fairly competent Emacs user. However, just for fun I have just downloaded Sigasi 2.0 to look into whether it could replace Emacs for my VHDL editing tasks. However, do be aware that I've used Emacs as my main editor since about 1998. So this is not likely to be a very fair comparison since I haven't used Sigasi for more than an hour or so by following the tutorial and trying it on one of my own VHDL projects. What follows are some notes from my testing and what I find missing as compared to Emacs. Of course, some of these features may be present but not working in exactly the same way as in Emacs which is why I didn't find them. * When using Emacs I can just type "emacs filename.vhd" (or an alias for emacsclient if I expect that I will need to look into a lot of different files using the same editor instance). I'm not sure how to do this in Sigasi. Merely typing sigasi filename.vhd doesn't seem to work at least and sigasi -h or sigasi --help didn't give me any indication that it is possible to do this from the commandline easily. * It was fairly easy to find and enable the Emacs key scheme which made it quite a bit more comfortable to use for me. Good. * Incremental search worked as expected when pressing C-s and C-r. However, some useful commands in Emacs are not present. Of this the greatest loss is C-w (which adds the string following the cursor to the search string). Very convenient when you want to search for the word you are currently looking at. Nevertheless, merely the presence of an easy to use incremental search is a big plus. * Ctrl-g didn't work to abort a search and return to the start location of the search as expected. However, Ctrl-x Ctrl-x worked as expected which is good. * I use M-q in Emacs all the time when writing text (for example in the form of comments) to make sure that the text is nicely aligned and doesn't exceed a user configurable number of characters per line. (Usually a little less than 80.) In Sigasi M-q doesn't seem to do anything. * There doesn't seem to be any kill ring functionality. (Or similar history functionality for other commands such as search.) * The keys for rectangular cut and paste and string rectangle don't do anything. (Neither the standard keybindings nor the cua-mode version where you press ctrl-enter to start a rectangular selection.) * I couldn't find any keyboard macro functionality :( This is actually a really big issue for me. If you don't have macros you can't do a lot of really really neat tricks. While I don't use keybaord macros every day, they can really save you a lot of work in some situations. See the following youtube clip for some inspiration: http://www.youtube.com/watch?v=zropjwVQlWQ&NR=1 * C-x C-b worked to select the buffer as expected. Good! (However, it is not as powerful as iswitchb-mode in Emacs.) * I turned off the Emacs keybindings to enable the use of C-SPACE for template insertion. I'm somewhat skeptical about how these are implemented, but I admit that this may be because I'm not used to them. * After trying out C-SPACE I changed the keys back to Emacs again. But this change didn't seem to take effect. Perhaps I did something wrong? A restart of Sigasi didn't fix it either. * When opening an existing design which included components written in both VHDL and Verilog there was no support for Verilog at all in the editor. (Since I use both Verilog and VHDL fairly frequently this is an issue for me. If you use Verilog rarely it may not be a big problem though.) All in all, Sigasi seems to be a major step up as compared to some other VHDL editing solutions (for example, I'd much rather use Sigasi than the ISE text editor). However, it will not replace Emacs for me anytime soon I'm afraid. The main reason why it is very hard to get me to change from Emacs to some other editor is that my entire workflow is based around Emacs. This allows me to utilize the same skill set regardless of whether I edit Verilog, VHDL, HTML, C, shell script, or MP3 files. (Yes, I have done some simple editing of MP3 files in Emacs in some situations.) In addition to text editing I'm also using Emacs for reading mail, organizing my schedule, and dealing with my TODO-list. I often find myself running a shell from within Emacs as well. (The unix shell running in split screen with a scratch buffer in Emacs can do some really powerful things when combined with macros.) I could probably spend another hour here merely listing some nice Emacs tricks but I think I'll end here by wishing you good luck. While I don't expect many die hard Emacs users to switch to Sigasi I think you may have a good chance of snatching up people who only use Emacs for VHDL editing. regards /Andreas From newsfish@newsfish Tue Aug 9 07:53:39 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Tue, 12 Jul 2011 19:17:42 +0100 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> <4e19a270$0$14260$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="18381"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19X3Ccx4j9z2ODDLlM2+Ls08NSbaM0qhWs=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:dmIji/+EGgu1yD/+UdjQnduEPiw= Xref: feeder.eternal-september.org comp.lang.vhdl:5134 On Sun, 10 Jul 2011 15:00:31 +0200, Jan Decaluwe wrote: >Are you also struggling with LRM-compliant but different >behavior among tools? (As fas as I can tell, SystemVerilog >has produced even more opportunities for nondeterministic races >than Verilog.) After all these years, my sanity-preservation strategies are fairly well honed :-) I'm not sure why you think SV is any worse than vanilla Verilog. It also provides various tools to help you if you are perverse enough to want to get things right: clocking blocks, $sampled, ... although those too have their pitfalls, and the poor RTL designer is in just as much of a mess as always (pun intended). -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:39 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!tranq7.tranquility.net!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!195.114.241.41.MISMATCH!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 12 Jul 2011 22:09:31 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> <4e19a270$0$14260$ba620e4c@news.skynet.be> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 31 Message-ID: <4e1ca9fc$0$14255$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 864a082d.news.skynet.be X-Trace: 1310501372 news.skynet.be 14255 91.177.8.150:53829 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:5135 On 07/12/2011 08:17 PM, Jonathan Bromley wrote: > On Sun, 10 Jul 2011 15:00:31 +0200, Jan Decaluwe wrote: > >> Are you also struggling with LRM-compliant but different >> behavior among tools? (As fas as I can tell, SystemVerilog >> has produced even more opportunities for nondeterministic races >> than Verilog.) > > After all these years, my sanity-preservation strategies > are fairly well honed :-) I had inferred - probably incorrectly - that the original code was written by someone else :-) > I'm not sure why you think SV is any worse than vanilla > Verilog. Not from personal experience, and perhaps incorrect again. My thoughts about this orginate from reading Janick Bergeron's "Writing Testbenches with SystemVerilog", when he explains program versus module threads and why you need "clocking" blocks to describe proper synchronous behaviour. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Tue Aug 9 07:53:40 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Tue, 12 Jul 2011 22:15:12 +0100 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> <4e19a270$0$14260$ba620e4c@news.skynet.be> <4e1ca9fc$0$14255$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="28360"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18k+3l4HVGUighjn4vLq6cjmuf0iJq+V78=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:VkYFfjuJYjFLTmOryGI1rciv8Bk= Xref: feeder.eternal-september.org comp.lang.vhdl:5136 On Tue, 12 Jul 2011 22:09:31 +0200, Jan Decaluwe wrote: >My thoughts about this orginate from reading Janick Bergeron's >"Writing Testbenches with SystemVerilog", when he explains >program versus module threads and why you need "clocking" >blocks to describe proper synchronous behaviour. This is getting a bit OT for c.l.vhdl, but it may at least provide a few moments of schadenfreude. Way back when, program blocks, clocking blocks and modules all worked together in a specific way to give race-free interaction between testbench and DUT. Unfortunately, when SV hit the public streets, people started doing odd things. First they asked what would happen if you used a clocking block without a program block, or vice versa, since there's nothing in the language syntax to say you can't do that. Second, people had the temerity to create verification environments where the DUT/TB division was perhaps not quite so clear-cut as the inventors of clocking and program blocks might have imagined. And finally, they sometimes manipulated signals (and even, horror of horrors, clocking blocks) in a way that wasn't directly related to any clock. Faced with this rebellious and perverse behaviour by users, the SV community had no choice but to specify in reasonable detail what these constructs actually do. And some of those things are not terribly convenient, but at least they are now (since 1800-2009) fairly well defined. Used properly, they are not plagued by nondeterminism. So we're now left with the situation that clocking blocks and programs give a certain set of very useful behaviours if used in just the right way; but, when abused, those same constructs can do remarkably silly things. Anyway... like I said, it's way OT for here. Still kinda fun, though. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:40 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?Q?Nicholas_Collin_Paul_de_Glouce=C5=BFter?= Newsgroups: comp.lang.verilog,comp.arch.fpga,comp.arch,comp.arch.embedded,comp.lang.vhdl Subject: Re: [ANN] HercuLeS high-level synthesis tool Date: Wed, 13 Jul 2011 11:34:31 +0000 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx04.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="9724"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/eKxa9Kt8rQBE62S5j9dC6q0H4xQvhPmTSg5vZz71v8A==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: Cancel-Lock: sha1:YsyqbVV1MZaU6sWpsXb5Btkwx+c= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.verilog:3121 comp.arch.fpga:15891 comp.arch:17081 comp.arch.embedded:23322 comp.lang.vhdl:5137 Dr. Kavvadias sent on July 11th, 2011: |----------------------------------------------------------| |"[..] | | | |You can [..] code your input [..] in a bit-accurate typed-| |assembly language called NAC (N-Address Code). [..] | |[..] | | | |[..]" | |----------------------------------------------------------| Ah, strongly typed assembly languages. One does not see many of those. From newsfish@newsfish Tue Aug 9 07:53:40 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!y13g2000yqy.googlegroups.com!not-for-mail From: Philippe Faes Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Wed, 13 Jul 2011 05:24:56 -0700 (PDT) Organization: http://groups.google.com Lines: 150 Message-ID: <9d298138-b181-4624-8624-3d1a6f7828c2@y13g2000yqy.googlegroups.com> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310559897 20018 127.0.0.1 (13 Jul 2011 12:24:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 12:24:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y13g2000yqy.googlegroups.com; posting-host=195.144.71.15; posting-account=Dh2KDAoAAACN2skkW5NrnTSyvGjOAQ7F User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:4020 comp.lang.vhdl:5138 On Jul 12, 5:47=A0pm, Andreas Ehliar wrote: > Well, I think I could characterize myself as a fairly competent Emacs > user. However, just for fun I have just downloaded Sigasi 2.0 to look > into whether it could replace Emacs for my VHDL editing tasks. > > However, do be aware that I've used Emacs as my main editor since > about 1998. So this is not likely to be a very fair comparison since I > haven't used Sigasi for more than an hour or so by following the > tutorial and trying it on one of my own VHDL projects. Andreas, thank you for your in-depth evaluation. It seems you have focussed on text editing and search operations. Obviously, the tool you have known for years will give you better results. I'm not sure if you have looked at type-time compilation (with error checking), and other advanced VHDL-specific features (navigation, hovers, refactoring). If anybody is to be convinced of dropping Emacs, it would be because of those features. > What follows are some notes from my testing and what I find missing as > compared to Emacs. Of course, some of these features may be present > but not working in exactly the same way as in Emacs which is why I > didn't find them. > > * When using Emacs I can just type "emacs filename.vhd" (or an alias > =A0 for emacsclient if I expect that I will need to look into a lot of > =A0 different files using the same editor instance). > > =A0 I'm not sure how to do this in Sigasi. Merely typing sigasi > =A0 filename.vhd doesn't seem to work at least and sigasi -h or sigasi > =A0 --help didn't give me any indication that it is possible to do this > =A0 from the commandline easily. We'll get that working soon. Thanks for pointing it out. > > * It was fairly easy to find and enable the Emacs key scheme which > =A0 made it quite a bit more comfortable to use for me. Good. Thanks > * Incremental search worked as expected when pressing C-s and > =A0 C-r. However, some useful commands in Emacs are not present. Of this > =A0 the greatest loss is C-w (which adds the string following the cursor > =A0 to the search string). Very convenient when you want to search for > =A0 the word you are currently looking at. Nevertheless, merely the > =A0 presence of an easy to use incremental search is a big plus. > > * Ctrl-g didn't work to abort a search and return to the start > =A0 location of the search as expected. However, Ctrl-x Ctrl-x worked as > =A0 expected which is good. > > * I use M-q in Emacs all the time when writing text (for example in > =A0 the form of comments) to make sure that the text is nicely aligned > =A0 and doesn't exceed a user configurable number of characters per > =A0 line. (Usually a little less than 80.) In Sigasi M-q doesn't seem to > =A0 do anything. Code formatting is mapped to CTRL+SHIFT+F. Remappable, though. > * There doesn't seem to be any kill ring functionality. (Or similar > =A0 history functionality for other commands such as search.) Not that I know of... > * The keys for rectangular cut and paste and string rectangle don't do > =A0 anything. (Neither the standard keybindings nor the cua-mode version > =A0 where you press ctrl-enter to start a rectangular selection.) > Rectangle editing (block select) can be activated using CRTL+ALT+A with normal key bindings. There is also an icon in the tool bar: http://www.vasanth.in/2009/03/31/eclipse-tip-block-selection-mode/ > * I couldn't find any keyboard macro functionality :( This is actually > =A0 a really big issue for me. If you don't have macros you can't do a > =A0 lot of really really neat tricks. While I don't use keybaord macros > =A0 every day, they can really save you a lot of work in some > =A0 situations. See the following youtube clip for some inspiration: > =A0http://www.youtube.com/watch?v=3DzropjwVQlWQ&NR=3D1 Good point. There might be an Eclipse plugin that offers marcros in a way that you need. I'm not sure. > > * C-x C-b worked to select the buffer as expected. Good! (However, it > =A0 is not as powerful as iswitchb-mode in Emacs.) > > * I turned off the Emacs keybindings to enable the use of C-SPACE > =A0 for template insertion. I'm somewhat skeptical about how these are > =A0 implemented, but I admit that this may be because I'm not used to > =A0 them. You can tie the template insertion to another key combination if you like: http://www.sigasi.com/faq/can-i-change-default-key-bindings > > * After trying out C-SPACE I changed the keys back to Emacs again. But > =A0 this change didn't seem to take effect. Perhaps I did something > =A0 wrong? A restart of Sigasi didn't fix it either. Bug in Eclipse. Try "restore to defaults". > * When opening an existing design which included components written in > =A0 both VHDL and Verilog there was no support for Verilog at all in the > =A0 editor. (Since I use both Verilog and VHDL fairly frequently this is > =A0 an issue for me. If you use Verilog rarely it may not be a big > =A0 problem though.) Yeah, we'll get to Verilog. We didn't want to offer syntax highlighting because that could create false expectations. http://www.sigasi.com/keep-me-informed-about-verilog > All in all, Sigasi seems to be a major step up as compared to some > other VHDL editing solutions (for example, I'd much rather use Sigasi > than the ISE text editor). However, it will not replace Emacs for me > anytime soon I'm afraid. > > The main reason why it is very hard to get me to change from Emacs to > some other editor is that my entire workflow is based around > Emacs. This allows me to utilize the same skill set regardless of > whether I edit Verilog, VHDL, HTML, C, shell script, or MP3 > files. (Yes, I have done some simple editing of MP3 files in Emacs in > some situations.) You can edit HTML, C and shell scripts in Eclipse. Just install the right plugin. (No MP3 editing in Eclipse, though!) > In addition to text editing I'm also using Emacs for reading mail, > organizing my schedule, and dealing with my TODO-list. I often find > myself running a shell from within Emacs as well. (The unix shell > running in split screen with a scratch buffer in Emacs can do some > really powerful things when combined with macros.) > > I could probably spend another hour here merely listing some nice > Emacs tricks but I think I'll end here by wishing you good luck. While > I don't expect many die hard Emacs users to switch to Sigasi I think > you may have a good chance of snatching up people who only use Emacs > for VHDL editing. > > regards > /Andreas Thanks for the encouraging words! -- kind regards Philippe From newsfish@newsfish Tue Aug 9 07:53:40 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder.news-service.com!postnews.google.com!u26g2000vby.googlegroups.com!not-for-mail From: Julien REINAULD Newsgroups: comp.lang.vhdl Subject: empty array litteral Date: Wed, 13 Jul 2011 05:54:09 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <1903e24a-3097-468a-90e9-7b4a13673514@u26g2000vby.googlegroups.com> NNTP-Posting-Host: 88.162.182.86 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310561650 4981 127.0.0.1 (13 Jul 2011 12:54:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 12:54:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u26g2000vby.googlegroups.com; posting-host=88.162.182.86; posting-account=rrbtogoAAABnM_lBzLFGDjhSlgIHQgSY User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.133 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5139 Hi all! According to std.standard: TYPE string IS ARRAY ( positive RANGE <> OF character); "hello" is a valid string litteral "" is a valid string litteral too, it is the empty string. Let TYPE foo IS ARRAY ( positive RANGE <> OF integer); (0, 1, 1, 2, 3, 5) is a valid foo litteral What is the litteral for an empty foo? Thx Julien From newsfish@newsfish Tue Aug 9 07:53:40 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r18g2000vbs.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: empty array litteral Date: Wed, 13 Jul 2011 06:25:42 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <1903e24a-3097-468a-90e9-7b4a13673514@u26g2000vby.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310563543 24464 127.0.0.1 (13 Jul 2011 13:25:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 13:25:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r18g2000vbs.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5140 On Jul 13, 1:54=A0pm, Julien REINAULD wrote: > Hi all! > > According to std.standard: > > TYPE string IS ARRAY ( positive RANGE <> OF character); > > "hello" is a valid string litteral > "" is a valid string litteral too, it is the empty string. > > Let > > TYPE foo IS ARRAY ( positive RANGE <> OF integer); > > (0, 1, 1, 2, 3, 5) is a valid foo litteral > > What is the litteral for an empty foo? > > Thx > > Julien That is an interesting question. You can make a null constant like this: constant NULL_FOO : foo(1 downto 2) :=3D (others =3D> 0); then use the constant in place of a literal. From newsfish@newsfish Tue Aug 9 07:53:40 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!00000000!not-for-mail From: Tom Gardner User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.16) Gecko/20101206 SeaMonkey/2.0.11 MIME-Version: 1.0 Newsgroups: comp.lang.verilog,comp.arch.fpga,comp.arch,comp.arch.embedded,comp.lang.vhdl Subject: Re: [ANN] HercuLeS high-level synthesis tool References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 17 Message-ID: NNTP-Posting-Host: 94.169.71.150 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1310572172 94.169.71.150 (Wed, 13 Jul 2011 15:49:32 UTC) NNTP-Posting-Date: Wed, 13 Jul 2011 15:49:32 UTC Organization: virginmedia.com Date: Wed, 13 Jul 2011 16:49:32 +0100 Xref: feeder.eternal-september.org comp.lang.verilog:3122 comp.arch.fpga:15895 comp.arch:17091 comp.arch.embedded:23332 comp.lang.vhdl:5141 Nicholas Collin Paul de GlouceÅ¿ter wrote: > Dr. Kavvadias sent on July 11th, 2011: > |----------------------------------------------------------| > |"[..] | > | | > |You can [..] code your input [..] in a bit-accurate typed-| > |assembly language called NAC (N-Address Code). [..] | > |[..] | > | | > |[..]" | > |----------------------------------------------------------| > > > Ah, strongly typed assembly languages. One does not see many of > those. You do if you are assembling hardware :) From newsfish@newsfish Tue Aug 9 07:53:41 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!e35g2000yqc.googlegroups.com!not-for-mail From: Nikolaos Kavvadias Newsgroups: comp.lang.verilog,comp.arch.fpga,comp.arch,comp.arch.embedded,comp.lang.vhdl Subject: Re: HercuLeS high-level synthesis tool Date: Wed, 13 Jul 2011 10:51:22 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <47b14a51-e117-4276-b89c-1057138b8571@e35g2000yqc.googlegroups.com> References: NNTP-Posting-Host: 94.70.55.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310579482 23856 127.0.0.1 (13 Jul 2011 17:51:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 17:51:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e35g2000yqc.googlegroups.com; posting-host=94.70.55.49; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.verilog:3123 comp.arch.fpga:15896 comp.arch:17096 comp.arch.embedded:23336 comp.lang.vhdl:5142 Hi > > Ah, strongly typed assembly languages. One does not see many of > > those. > > You do if you are assembling hardware :) Yes, bit-accurate, strongly-typed (generic) assembly languages is the way to go as an intermediate representation especially for hardware compilation. It provides some other benefits for the infrastructure in the long term. I decided to develop and extend an extremely lightweight typed- assembly language (called NAC), to keep all the infrastructure light and manageable by a single person. It certainly is manageable at the present time. Best regards, Nikolaos Kavvadias From newsfish@newsfish Tue Aug 9 07:53:41 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r11g2000prd.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Synthesis of multiple wait statements per VHDL-200X Date: Wed, 13 Jul 2011 11:40:23 -0700 (PDT) Organization: http://groups.google.com Lines: 84 Message-ID: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 67.188.14.18 Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310582423 20886 127.0.0.1 (13 Jul 2011 18:40:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 18:40:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r11g2000prd.googlegroups.com; posting-host=67.188.14.18; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5143 Hello, I'm trying to write a state machine in VHDL using code like the below, so that I can use for loops in the state machine. This code implements an asynchronous reset. However, in ISE the synthesizer gives me the error : ERROR:HDLCompiler:609=EF=BB=BF : Multiple signals in event expression is no= t synthesizable=EF=BB=BF. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DCODE=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D state_machine : process begin state_machine_loop : loop wait until (rising_edge(CLOCK) or RST =3D '1'); if RST =3D '1' then do_reset_stuff;=EF=BB=BF=EF=BB=BF next state_machine_loop; end if; =EF=BB=BF internal_loop : for i in 0 to SOME_VALUE loop do_internal_loop_stuff; wait until (rising_edge(CLOCK) or RST =3D '1'); if RST =3D '1' then do_reset_stuff;=EF=BB=BF next state_machine_loop; end if; end loop; end loop; end process; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DEND CODE=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D So I figured, okay, I'll make a state machine with a synchronous reset, as shown below. However, now I get this error: ERROR:HDLCompiler:926=EF=BB=BF : Multiple wait statements in one process ar= e not supported in this case.=EF=BB=BF =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DCODE=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D state_machine : process begin state_machine_loop : loop wait until rising_edge(CLOCK); if RST =3D '1' then do_reset_stuff;=EF=BB=BF next state_machine_loop; end if; =EF=BB=BF internal_loop : for i in 0 to SOME_VALUE loop do_internal_loop_stuff; wait until rising_edge(CLOCK); if RST =3D '1' then do_reset_stuff; next state_machine_loop; end if; end loop; end loop; end process =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DEND CODE=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D I'm reading in my copy of The Designers Guide to VHDL : Third Edition that these state machine coding styles ARE part of the IEEE 1076.6- VHDL-200X synthesis standard. I posted this on the Xilinx forum and was told the same thing that the tool told me : multiple wait statements are not supported for synthesis. Are there any other tools that will synthesize this or a similar coding style? I mean, in theory there is nothing un-synthesizable about this code. Thanks, Colin From newsfish@newsfish Tue Aug 9 07:53:41 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Wed, 13 Jul 2011 21:44:35 -0700 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> Injection-Date: Thu, 14 Jul 2011 04:46:00 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="6444"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/QAAbuEW2bOADPSfBJlv/CZe0vdiqFLjY=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:N0nd9f99jGwsKvwGTaUhS7+LCsk= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5144 Do you really need a loop? Maybe something like this will do what you need: state_machine : PROCESS variable do_internal_loop : boolean; BEGIN WAIT until rising_edge(CLOCK); IF RST = '1' THEN do_reset_stuff; ELSE IF do_internal_loop THEN do_internal_loop_stuff; IF some_end_condition THEN do_internal_loop := false; END IF; ELSE do_non_internal_loop_stuff; IF some_start_condition THEN do_internal_loop := true; END IF; END IF; END IF; END PROCESS; The process will execute once per clock cycle. Various conditional statements decide what to do on each cycle. A process with one WAIT statement as I have shown is definitely synthesizable. Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:41 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!m6g2000prh.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Wed, 13 Jul 2011 23:19:51 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 98.234.25.187 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310624391 23296 127.0.0.1 (14 Jul 2011 06:19:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Jul 2011 06:19:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m6g2000prh.googlegroups.com; posting-host=98.234.25.187; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5145 On Jul 13, 9:44=A0pm, "logic_guy" wrote: > Do you really need a loop? =A0Maybe something like this will do what you > need: > > state_machine : PROCESS > variable do_internal_loop : boolean; > BEGIN > =A0 =A0 WAIT until rising_edge(CLOCK); > =A0 =A0 IF RST =3D '1' THEN > =A0 =A0 =A0 do_reset_stuff; > =A0 =A0 ELSE > =A0 =A0 =A0 IF do_internal_loop THEN > =A0 =A0 =A0 =A0 do_internal_loop_stuff; > =A0 =A0 =A0 =A0 IF some_end_condition THEN > =A0 =A0 =A0 =A0 =A0 do_internal_loop :=3D false; > =A0 =A0 =A0 =A0 END IF; > =A0 =A0 =A0 ELSE > =A0 =A0 =A0 =A0 do_non_internal_loop_stuff; > =A0 =A0 =A0 =A0 IF some_start_condition THEN > =A0 =A0 =A0 =A0 =A0 do_internal_loop :=3D true; > =A0 =A0 =A0 =A0 END IF; > =A0 =A0 =A0 END IF; > =A0 =A0 END IF; > END PROCESS; > > The process will execute once per clock cycle. =A0Various conditional > statements decide what to do on each cycle. > > A process with one WAIT statement as I have shown is definitely > synthesizable. > > Charles Bailey Unfortunately the example I provided is pretty boiled down. In reality I need three nested for loops, which starts to get hairy. From newsfish@newsfish Tue Aug 9 07:53:41 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder2.news.elisa.fi!newsfeed3.funet.fi!newsfeed2.funet.fi!newsfeeds.funet.fi!uio.no!news.ctrl-c.liu.se!nntp Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Message-ID: From: Andreas Ehliar Date: 14 Jul 11 09:05:17 CEST References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> Nntp-Posting-Host: sabor.isy.liu.se User-Agent: slrn/0.9.8.1pl1 (Linux) Lines: 21 Xref: feeder.eternal-september.org comp.lang.vhdl:5146 On 2011-07-13, Colin Beighley wrote: > I'm reading in my copy of The Designers Guide to VHDL : Third Edition > that these state machine coding styles ARE part of the IEEE 1076.6- > VHDL-200X synthesis standard. I posted this on the Xilinx forum and > was told the same thing that the tool told me : multiple wait > statements are not supported for synthesis. Are there any other tools > that will synthesize this or a similar coding style? I mean, in theory > there is nothing un-synthesizable about this code. I've been able to synthesize similar state machines in Precision. However, I have not yet jumped ship to this style of FSM design yet. The reason being that it is not possible to do Mealy style state machines in it (AFAIK). Another is that it is quite tedious to handle the reset signal. This posting also implies that Synplify can handle such state machines but I haven't tested this myself: http://www.parallelpoints.com/node/69 regards /Andreas From newsfish@newsfish Tue Aug 9 07:53:41 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Aliaksei Newsgroups: comp.lang.vhdl Subject: Re: free waveform drawing tool Date: Thu, 14 Jul 2011 21:23:26 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <654b992b-7c1f-414d-ac34-91b4e82813ae@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 68.2.84.237 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310703897 14138 127.0.0.1 (15 Jul 2011 04:24:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Jul 2011 04:24:57 +0000 (UTC) In-Reply-To: <874oltklyw.fsf@harnisch.dyndns.org> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=68.2.84.237; posting-account=DO8HUwoAAABarIvwczwGgNHPyBoOVZ-E User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5147 http://wavedrom.googlecode.com WaveDrom is Free and Open Source online digital timing diagram editor that uses JavaScript?, HTML5 and SVG to render WaveJSON input text description into vector graphics. The project is in progress. Any feedback appreciated. From newsfish@newsfish Tue Aug 9 07:53:42 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Fri, 15 Jul 2011 07:44:48 -0700 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> Injection-Date: Fri, 15 Jul 2011 14:44:47 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="10224"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/B6caon3aEC/GmrByaYnh7HRvvDiGEd20=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:5vhnnvVfHRTpOShKp+XOjfne0BI= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5148 "Colin Beighley" wrote in message news:a9201a47-730d-443f-9960-0e2fee37b9e1@m6g2000prh.googlegroups.com... On Jul 13, 9:44 pm, "logic_guy" wrote: > Do you really need a loop? Maybe something like this will do what you > need: > > state_machine : PROCESS > variable do_internal_loop : boolean; > BEGIN > WAIT until rising_edge(CLOCK); > IF RST = '1' THEN > do_reset_stuff; > ELSE > IF do_internal_loop THEN > do_internal_loop_stuff; > IF some_end_condition THEN > do_internal_loop := false; > END IF; > ELSE > do_non_internal_loop_stuff; > IF some_start_condition THEN > do_internal_loop := true; > END IF; > END IF; > END IF; > END PROCESS; > > The process will execute once per clock cycle. Various conditional > statements decide what to do on each cycle. > > A process with one WAIT statement as I have shown is definitely > synthesizable. > > Charles Bailey > Unfortunately the example I provided is pretty boiled down. In reality > I need three nested for loops, which starts to get hairy. LOOPs in a clocked process are normally used when you need to operate on multiple elements of an array in a single clock cycle. If the operations span multiple clock cycles then you need to define your own counter variable to keep track of what happens on each clock cycle. By expanding on the example I've show, you should be able to do anything you want, and do it with just one WAIT statement. Charles Bailey From newsfish@newsfish Tue Aug 9 07:53:42 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t8g2000prm.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Fri, 15 Jul 2011 10:23:19 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310751056 3343 127.0.0.1 (15 Jul 2011 17:30:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Jul 2011 17:30:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t8g2000prm.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5149 On Jul 15, 7:44=A0am, "logic_guy" wrote: > "Colin Beighley" wrote in message > > news:a9201a47-730d-443f-9960-0e2fee37b9e1@m6g2000prh.googlegroups.com... > On Jul 13, 9:44 pm, "logic_guy" wrote: > > > > > > > > > > > Do you really need a loop? Maybe something like this will do what you > > need: > > > state_machine : PROCESS > > variable do_internal_loop : boolean; > > BEGIN > > WAIT until rising_edge(CLOCK); > > IF RST =3D '1' THEN > > do_reset_stuff; > > ELSE > > IF do_internal_loop THEN > > do_internal_loop_stuff; > > IF some_end_condition THEN > > do_internal_loop :=3D false; > > END IF; > > ELSE > > do_non_internal_loop_stuff; > > IF some_start_condition THEN > > do_internal_loop :=3D true; > > END IF; > > END IF; > > END IF; > > END PROCESS; > > > The process will execute once per clock cycle. Various conditional > > statements decide what to do on each cycle. > > > A process with one WAIT statement as I have shown is definitely > > synthesizable. > > > Charles Bailey > > Unfortunately the example I provided is pretty boiled down. In reality > > I need three nested for loops, which starts to get hairy. > > LOOPs in a clocked process are normally used when you need to operate on > multiple elements of an array in a single clock cycle. =A0If the > operations span multiple clock cycles then you need to define your own > counter variable to keep track of what happens on each clock cycle. =A0By > expanding on the example I've show, you should be able to do anything > you want, and do it with just one WAIT statement. > > Charles Bailey Yes, you can use one WAIT statement and synthesize your state machine thus, but you don't gain anything over the : if rst elsif rising_edge(clk) end if : model. However, the benefit of using the WAIT UNTIL RISING_EDGE(CLK) at various places within your process is that you can describe a state machine in a much more abstract, easily understood manner. It's quite a mystery to me that HDL's are still so primitive in some respects - there simply MUST be a better way to do, for instance, nested for loops than keeping track of the variables with the two-process case statement. I've wondered if FPGA bitstreams were not proprietary would there be open-source toolchains that would spring forth and better HDL's as a result? From newsfish@newsfish Tue Aug 9 07:53:42 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a2g2000prf.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Fri, 15 Jul 2011 11:28:50 -0700 (PDT) Organization: http://groups.google.com Lines: 78 Message-ID: <92d928a8-ab10-4860-a9d4-84327d5b6216@a2g2000prf.googlegroups.com> References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310756188 23573 127.0.0.1 (15 Jul 2011 18:56:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Jul 2011 18:56:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a2g2000prf.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5150 On Jul 15, 10:23=A0am, Colin Beighley wrote: > On Jul 15, 7:44=A0am, "logic_guy" wrote: > > > > > > > > > > > "Colin Beighley" wrote in message > > >news:a9201a47-730d-443f-9960-0e2fee37b9e1@m6g2000prh.googlegroups.com... > > On Jul 13, 9:44 pm, "logic_guy" wrote: > > > > Do you really need a loop? Maybe something like this will do what you > > > need: > > > > state_machine : PROCESS > > > variable do_internal_loop : boolean; > > > BEGIN > > > WAIT until rising_edge(CLOCK); > > > IF RST =3D '1' THEN > > > do_reset_stuff; > > > ELSE > > > IF do_internal_loop THEN > > > do_internal_loop_stuff; > > > IF some_end_condition THEN > > > do_internal_loop :=3D false; > > > END IF; > > > ELSE > > > do_non_internal_loop_stuff; > > > IF some_start_condition THEN > > > do_internal_loop :=3D true; > > > END IF; > > > END IF; > > > END IF; > > > END PROCESS; > > > > The process will execute once per clock cycle. Various conditional > > > statements decide what to do on each cycle. > > > > A process with one WAIT statement as I have shown is definitely > > > synthesizable. > > > > Charles Bailey > > > Unfortunately the example I provided is pretty boiled down. In realit= y > > > I need three nested for loops, which starts to get hairy. > > > LOOPs in a clocked process are normally used when you need to operate o= n > > multiple elements of an array in a single clock cycle. =A0If the > > operations span multiple clock cycles then you need to define your own > > counter variable to keep track of what happens on each clock cycle. =A0= By > > expanding on the example I've show, you should be able to do anything > > you want, and do it with just one WAIT statement. > > > Charles Bailey > > Yes, you can use one WAIT statement and synthesize your state machine > thus, but you don't gain anything over the : if rst elsif > rising_edge(clk) end if : model. However, the benefit of using the > WAIT UNTIL RISING_EDGE(CLK) at various places within your process is > that you can describe a state machine in a much more abstract, easily > understood manner. It's quite a mystery to me that HDL's are still so > primitive in some respects - there simply MUST be a better way to do, > for instance, nested for loops than keeping track of the variables > with the two-process case statement. > > I've wondered if FPGA bitstreams were not proprietary would there be > open-source toolchains that would spring forth and better HDL's as a > result? P.S. : gcc, gdb, and a number of microcontrollers spring to mind as an example From newsfish@newsfish Tue Aug 9 07:53:42 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p14g2000yqj.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Fri, 15 Jul 2011 14:25:09 -0700 (PDT) Organization: http://groups.google.com Lines: 81 Message-ID: <569a6d4c-831c-4d70-bc63-00f686e80095@p14g2000yqj.googlegroups.com> References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310765209 17781 127.0.0.1 (15 Jul 2011 21:26:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Jul 2011 21:26:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p14g2000yqj.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5151 On Jul 15, 1:23=A0pm, Colin Beighley wrote: > > Yes, you can use one WAIT statement and synthesize your state machine > thus, but you don't gain anything over the : if rst elsif > rising_edge(clk) end if : model. It's not clear to me just what you think you gain with your model either. There's nothing inherently wrong about being different, but different is not neccessarily better (assuming that's what you mean by 'don't gain anything...') > However, the benefit of using the > WAIT UNTIL RISING_EDGE(CLK) at various places within your process is > that you can describe a state machine in a much more abstract, easily > understood manner. I disagree, see (1) at the end of this post for how I manipulated your original process into a form that is synthesizable and at least as clear as your process. Repeating things over and over again is error prone which is far worse than what you think may be 'easily understood'. For example, if you start having several conditions tacked on, and then you change those over time as you develop the code both of the following lines of code (separated by large amounts of text) are 'easily understood', but are they both correct or did the designer forget a condition? wait until rising_edge(clock) and (this =3D '1') and (that /=3D 5) and (moon =3D rising); wait until rising_edge(clock) and (this =3D '1') and (moon =3D rising); > It's quite a mystery to me that HDL's are still so > primitive in some respects - there simply MUST be a better way to do, > for instance, nested for loops than keeping track of the variables Keeping track of the variables boils down to the following. Preferring one over the other simply says you like the looks of a 'for' statement rather than an 'if'...but that preference is up to anyone to have and is simply cosmetic for i in 0 to SOME_VALUE loop (your method) if i <=3D SOME_VALUE then (currently synthesizable method) The currently synthesizable method with the 'if' statement has some baggage: - Loop variable must be declared - Loop variable increment is explicit What you're proposing has some baggage: - Global conditions (like checking that Reset =3D '1' and what to do under that condition) must be physically repeated in the code...that is best accomplished via copy/paste which is not good practice in hardly any language - More local condition checking gets problematic. By this I mean conditions that are not quite as global as 'Reset =3D 1' but are not specific to a single code branch. Now you're copying code in certain areas. Again, copy/paste will be your friend but copy/paste is not good practice. > with the two-process case statement. > Ummmm...nobody should be using two-process. Use a single clocked process and a concurrent statement to pick up the unclocked outputs. Kevin Jennings ---- (1) Synthesizable version of the process from your original post. state_machine : process variable i: integer range 0 to SOME_VALUE + 1; begin wait until (rising_edge(CLOCK) or RST =3D '1'); if RST =3D '1' then do_reset_stuff;?? next state_machine_loop; --KJ: What do you mean here?? i :=3D 0; else if i <=3D SOME_VALUE then do_internal_loop_stuff; i :=3D i + 1; end if; end if; end process; From newsfish@newsfish Tue Aug 9 07:53:42 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!t9g2000vbs.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: 1to8 Demux code, can you look plz Date: Sat, 16 Jul 2011 18:02:37 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> NNTP-Posting-Host: 188.51.4.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310864557 18177 127.0.0.1 (17 Jul 2011 01:02:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 Jul 2011 01:02:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t9g2000vbs.googlegroups.com; posting-host=188.51.4.222; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5152 Hi all, I am tried to write VHDL code for 1 to 8 Demux and that's what i finish with it LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY Dmux1to8 IS PORT ( X : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(0 TO 2); En : IN STD_LOGIC; W : OUT STD_LOGIC_VECTOR(0 TO 7)); END Dmux1to2; ARCHITECTURE Structure OF Dmux1to8 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); BEGIN G1: FOR i IN 0 TO 1 GENERATE Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X); G2: FOR i IN 2 TO 5 GENERATE Dec_left: Demux1to2 PORT MAP ( m(i), S(1)); END GENERATE ; END GENERATE ; Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO 7) ); END Structure; can any one told me if is it right or not? if there are any mistakes can you help me to correct it ? From newsfish@newsfish Tue Aug 9 07:53:42 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!proxad.net!feeder1-2.proxad.net!cleanfeed2-a.proxad.net!nnrp10-2.free.fr!not-for-mail Date: Sun, 17 Jul 2011 09:48:28 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> In-Reply-To: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 55 Message-ID: <4e2293c5$0$20183$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 17 Jul 2011 09:48:21 MEST NNTP-Posting-Host: 82.246.229.10 X-Trace: 1310888901 news-1.free.fr 20183 82.246.229.10:51482 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:5153 Le 17/07/2011 03:02, majmoat_ensan a écrit : > Hi all, Hi > I am tried to write VHDL code for 1 to 8 Demux and that's what i > finish with it > > LIBRARY IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > use ieee.std_logic_unsigned.all; Do NOT use non-standard libraries like std_logic_arith, std_logic_signed or std_logic_unsigned. Use numeric_std instead. > ENTITY Dmux1to8 IS > PORT ( X : IN STD_LOGIC; > S : IN STD_LOGIC_VECTOR(0 TO 2); > En : IN STD_LOGIC; > W : OUT STD_LOGIC_VECTOR(0 TO 7)); > END Dmux1to2; Although it doesn't change anything in terms of behaviour, it is common practice to declare vectors with a descending range (e.g. 7 downto 0) because the higher index bit is then the leftmost bit (which helps a lot when you use arithmetic vectors) > ARCHITECTURE Structure OF Dmux1to8 IS > SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); > > BEGIN > G1: FOR i IN 0 TO 1 GENERATE > Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X); > G2: FOR i IN 2 TO 5 GENERATE > Dec_left: Demux1to2 PORT MAP ( m(i), S(1)); > END GENERATE ; > END GENERATE ; > Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO > 7) ); There are spaces in your (intended) component name. You can't do this. Besides, it is also common practice to use named association for port maps because it is much less error prone (but is adds a lot of typing unless you use an Editor with MACroS) > END Structure; It is absolutely impossible to say if this is good or not because you don't give the code for components demux1to2 and demux1to8. I find it strange that you map the same demux1to2 component with 3 ports in your first generate loop and only 2 ports in the second one. Nicolas From newsfish@newsfish Tue Aug 9 07:53:43 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 18 Jul 2011 11:23:59 -0500 Date: Mon, 18 Jul 2011 09:24:02 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> In-Reply-To: <4e2293c5$0$20183$426a74cc@news.free.fr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 62 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-BJ0JHiA+vv9NzkfhHJmWuS4yiG2mQui95AHBf5719Nzz7RURR5bkVyOu/RRxN6qum2cc/HiwzkfC24i!GRKR7Qw/K2qCPo99G0kuC0QpmCe632F/JDeICG8DRBpJbm7+ZC6kzdGOg2wZ69ygErOYOv93Bgrl X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3185 Xref: feeder.eternal-september.org comp.lang.vhdl:5154 On 7/17/2011 12:48 AM, Nicolas Matringe wrote: > Le 17/07/2011 03:02, majmoat_ensan a écrit : >> Hi all, > > Hi > >> I am tried to write VHDL code for 1 to 8 Demux and that's what i >> finish with it >> >> LIBRARY IEEE; >> USE IEEE.STD_LOGIC_1164.ALL; >> use ieee.std_logic_unsigned.all; > > Do NOT use non-standard libraries like std_logic_arith, std_logic_signed > or std_logic_unsigned. Use numeric_std instead. > > >> ENTITY Dmux1to8 IS >> PORT ( X : IN STD_LOGIC; >> S : IN STD_LOGIC_VECTOR(0 TO 2); >> En : IN STD_LOGIC; >> W : OUT STD_LOGIC_VECTOR(0 TO 7)); >> END Dmux1to2; > > Although it doesn't change anything in terms of behaviour, it is common > practice to declare vectors with a descending range (e.g. 7 downto 0) > because the higher index bit is then the leftmost bit (which helps a lot > when you use arithmetic vectors) > > >> ARCHITECTURE Structure OF Dmux1to8 IS >> SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); >> >> BEGIN >> G1: FOR i IN 0 TO 1 GENERATE >> Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X); >> G2: FOR i IN 2 TO 5 GENERATE >> Dec_left: Demux1to2 PORT MAP ( m(i), S(1)); >> END GENERATE ; >> END GENERATE ; >> Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO >> 7) ); > > There are spaces in your (intended) component name. You can't do this. > Besides, it is also common practice to use named association for port > maps because it is much less error prone (but is adds a lot of typing > unless you use an Editor with MACroS) > >> END Structure; > > It is absolutely impossible to say if this is good or not because you > don't give the code for components demux1to2 and demux1to8. I find it > strange that you map the same demux1to2 component with 3 ports in your > first generate loop and only 2 ports in the second one. > > Nicolas Also, you reused 'i' as your loop variable in the inner loop. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Tue Aug 9 07:53:43 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 18 Jul 2011 18:09:16 -0500 Date: Tue, 19 Jul 2011 00:09:16 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc15 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: empty array litteral References: <1903e24a-3097-468a-90e9-7b4a13673514@u26g2000vby.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <_Z-dnUwc2eSBILnTnZ2dnUVZ8lGdnZ2d@brightview.co.uk> Lines: 44 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-h1hdJPfTpbmctc6bqLsZ4B6flScsIoCdOSDhMiO8pPPTBAHcsGBBpJzqwpHn+JKDOE9zIsYc7omaxAH!twJv8W3IfxlYnqEaFKFaNdPFHA9MRuNExWyYw1Df23so+Gh30n3+udhPcud51pxkH7YFyHI6ebfj!4hJapIy8HHOKrRpGa7BfSt/t X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2181 Xref: feeder.eternal-september.org comp.lang.vhdl:5155 On 13/07/11 14:25, Tricky wrote: > On Jul 13, 1:54 pm, Julien REINAULD wrote: >> Hi all! >> >> According to std.standard: >> >> TYPE string IS ARRAY ( positive RANGE <> OF character); >> >> "hello" is a valid string litteral >> "" is a valid string litteral too, it is the empty string. >> >> Let >> >> TYPE foo IS ARRAY ( positive RANGE <> OF integer); >> >> (0, 1, 1, 2, 3, 5) is a valid foo litteral >> >> What is the litteral for an empty foo? >> >> Thx >> >> Julien > > That is an interesting question. > > You can make a null constant like this: > > constant NULL_FOO : foo(1 downto 2) := (others => 0); > > then use the constant in place of a literal. > I haven't tried it, or looked it up in the LRM, but I imagine you may be able to use (1 downto 2 => 0) though of course a named constant is nicer. regards Alan -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:43 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Tue, 19 Jul 2011 12:36:34 +0200 Lines: 20 Message-ID: <98l51iFmp5U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net DHU4JiITXRO22MS+yoK/iwP4+DAo0ByVHUJy30nGrsaBFof2w/ Cancel-Lock: sha1:anDHcNMwYPKEjvI/S4VCjylyLOg= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5156 Mr. Google did not find this article/book (I don't know what it is). Mr. Amazon did not find this article/book (same as before...). It is mentioned in the vmkr documentation by Bell-Northern Research VHDL Group (http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhdl/tools/vmkr/doc/vmkr.doc.ps) but no other references found. Does anyone know where I can find this article/book? As a parting note, does anyone have any suggestion/recommendation on the usage of vmkr? Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Aug 9 07:53:43 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: "nemgreen@gmail.com" Newsgroups: comp.lang.vhdl Subject: Re: re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Tue, 19 Jul 2011 07:53:24 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <7183d5d4-ade1-47ff-8b3a-810b18764824@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 192.94.31.2 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311087610 3191 127.0.0.1 (19 Jul 2011 15:00:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Jul 2011 15:00:10 +0000 (UTC) In-Reply-To: <98l51iFmp5U1@mid.individual.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.94.31.2; posting-account=A7jt9goAAAAU2UzdI3fZ3NM4v1Vq2uHr User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5157 ModelSim and Questa have the vmake command to build a makefile from a compi= led library: vmake The vmake utility allows you to use a UNIX or Windows MAKE program to maint= ain individual libraries. You run vmake on a compiled design library. This = utility operates on multiple source files per design unit; it supports Veri= log include files as well as Verilog and VHDL PSL vunit files. From newsfish@newsfish Tue Aug 9 07:53:43 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 19 Jul 2011 18:31:03 -0500 Date: Wed, 20 Jul 2011 00:31:03 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc15 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron References: <98l51iFmp5U1@mid.individual.net> In-Reply-To: <98l51iFmp5U1@mid.individual.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 26 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-rjIxy30fSGybHj1faUQk4BiLReuDpvTL4ogzYqhFZkFpjZjgbNE+4CIiAhAWkQOOiqNb8QKvuJ8VgIJ!ivSF1ctK1vKZ/oPRkWb6f+3aRmJ1s5FqjdRzEgB4sBDlTSAzXCj5uH+vtBBKWKBFk8Fk9qXE36Qo!JIZop411pM12G8nXbVNoxMoa X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1936 Xref: feeder.eternal-september.org comp.lang.vhdl:5158 On 19/07/11 11:36, Alessandro Basili wrote: > Mr. Google did not find this article/book (I don't know what it is). > Mr. Amazon did not find this article/book (same as before...). > > It is mentioned in the vmkr documentation by Bell-Northern Research VHDL > Group > (http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhdl/tools/vmkr/doc/vmkr.doc.ps) > but no other references found. > > Does anyone know where I can find this article/book? > > As a parting note, does anyone have any suggestion/recommendation on the > usage of vmkr? > > Al > Try posting your message on the Verification Guild http://verificationguild.com (I think, from memory). Janick started the website, and often posts there, regards Alan -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:43 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h12g2000vbx.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz Date: Wed, 20 Jul 2011 07:48:59 -0700 (PDT) Organization: http://groups.google.com Lines: 107 Message-ID: References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> NNTP-Posting-Host: 90.148.43.73 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311173339 21611 127.0.0.1 (20 Jul 2011 14:48:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 14:48:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h12g2000vbx.googlegroups.com; posting-host=90.148.43.73; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5159 On Jul 18, 7:24=A0pm, Rob Gaddi wrote: > On 7/17/2011 12:48 AM, Nicolas Matringe wrote: > > > > > > > > > > > Le 17/07/2011 03:02, majmoat_ensan a =E9crit : > >> Hi all, > > > Hi > > >> I am tried to write VHDL code for 1 to 8 Demux and that's what i > >> finish with it > > >> LIBRARY IEEE; > >> USE IEEE.STD_LOGIC_1164.ALL; > >> use ieee.std_logic_unsigned.all; > > > Do NOT use non-standard libraries like std_logic_arith, std_logic_signe= d > > or std_logic_unsigned. Use numeric_std instead. > > >> ENTITY Dmux1to8 IS > >> PORT ( X : IN STD_LOGIC; > >> S : IN STD_LOGIC_VECTOR(0 TO 2); > >> En : IN STD_LOGIC; > >> W : OUT STD_LOGIC_VECTOR(0 TO 7)); > >> END Dmux1to2; > > > Although it doesn't change anything in terms of behaviour, it is common > > practice to declare vectors with a descending range (e.g. 7 downto 0) > > because the higher index bit is then the leftmost bit (which helps a lo= t > > when you use arithmetic vectors) > > >> ARCHITECTURE Structure OF Dmux1to8 IS > >> SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); > > >> BEGIN > >> G1: FOR i IN 0 TO 1 GENERATE > >> Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X); > >> G2: FOR i IN 2 TO 5 GENERATE > >> Dec_left: Demux1to2 PORT MAP ( m(i), S(1)); > >> END GENERATE ; > >> END GENERATE ; > >> Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO > >> 7) ); > > > There are spaces in your (intended) component name. You can't do this. > > Besides, it is also common practice to use named association for port > > maps because it is much less error prone (but is adds a lot of typing > > unless you use an Editor with MACroS) > > >> END Structure; > > > It is absolutely impossible to say if this is good or not because you > > don't give the code for components demux1to2 and demux1to8. I find it > > strange that you map the same demux1to2 component with 3 ports in your > > first generate loop and only 2 ports in the second one. > > > Nicolas > > Also, you reused 'i' as your loop variable in the inner loop. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order ummm if i tried to wrote it in this way is it right or not? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY Dmux1to8 IS PORT ( X : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(0 TO 2); W : OUT STD_LOGIC_VECTOR(0 TO 7)); END Dmux1to8; ARCHITECTURE Structure OF Dmux1to8 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); BEGIN Dmux1: Dmux1to8 PORT MAP ( X, s(0), m(0), m(1) ) ; Dmux2: Dmux1to8 PORT MAP ( m(0), s(1), m(2), m(3) ) ; Dmux3: Dmux1to8 PORT MAP ( m(1), s(1), m(4), m(5) ) ; Dmux4: Dmux1to8 PORT MAP ( m(2), s(2), w(0), w(1) ) ; Dmux5: Dmux1to8 PORT MAP ( m(3), s(2), w(2), w(3) ) ; Dmux6: Dmux1to8 PORT MAP ( m(4), s(2), w(4), w(5) ) ; Dmux7: Dmux1to8 PORT MAP ( m(5), s(2), w(6), w(7) ) ; END Structure ; From newsfish@newsfish Tue Aug 9 07:53:44 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 20 Jul 2011 11:35:50 -0500 Date: Wed, 20 Jul 2011 09:35:53 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 51 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-88gykf82ACnNeERu/5w/BVBY375eNyEE3j7N4l5PQl7VDXiGGSJJoS/3T/sE3qjpfU97ram/gLjdJ4W!10rG4LZnec/hJm39x7bAeoMeDlTr0V/S4lrZ9vfhRJduM3u6ut+nTGIQpsTJna0sjrEDeSy1tNEk X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2822 Xref: feeder.eternal-september.org comp.lang.vhdl:5160 On 7/20/2011 7:48 AM, majmoat_ensan wrote: > [snip] > > ummm if i tried to wrote it in this way is it right or not? > > > LIBRARY IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > use ieee.std_logic_unsigned.all; > > > ENTITY Dmux1to8 IS > PORT ( X : IN STD_LOGIC; > S : IN STD_LOGIC_VECTOR(0 TO 2); > W : OUT STD_LOGIC_VECTOR(0 TO 7)); > END Dmux1to8; > > ARCHITECTURE Structure OF Dmux1to8 IS > SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); > > BEGIN > Dmux1: Dmux1to8 PORT MAP > ( X, s(0), m(0), m(1) ) ; > Dmux2: Dmux1to8 PORT MAP > ( m(0), s(1), m(2), m(3) ) ; > Dmux3: Dmux1to8 PORT MAP > ( m(1), s(1), m(4), m(5) ) ; > Dmux4: Dmux1to8 PORT MAP > ( m(2), s(2), w(0), w(1) ) ; > Dmux5: Dmux1to8 PORT MAP > ( m(3), s(2), w(2), w(3) ) ; > Dmux6: Dmux1to8 PORT MAP > ( m(4), s(2), w(4), w(5) ) ; > Dmux7: Dmux1to8 PORT MAP > ( m(5), s(2), w(6), w(7) ) ; > END Structure ; No, now you're trying to recursively instantiate the element inside of itself. What on earth are you actually trying to accomplish, and why are you trying to build something as simple as a demux with anything inside of it? Just write the stupid thing in RTL. Honestly even that borders on the insane, the RTL demux should just be written directly into whatever higher level block it was going to go into. http://lmgtfy.com/?q=demultiplexer+vhdl -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Tue Aug 9 07:53:44 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!m3g2000pre.googlegroups.com!not-for-mail From: Daniel Leu Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Wed, 20 Jul 2011 10:14:02 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: References: <98l51iFmp5U1@mid.individual.net> NNTP-Posting-Host: 76.254.35.229 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311182043 13050 127.0.0.1 (20 Jul 2011 17:14:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 17:14:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m3g2000pre.googlegroups.com; posting-host=76.254.35.229; posting-account=vg5e4goAAAAGOhAcfiR_nSjiLBi7pokl User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5161 On Jul 19, 3:36=A0am, Alessandro Basili wrote: > Mr. Google did not find this article/book (I don't know what it is). > Mr. Amazon did not find this article/book (same as before...). > > It is mentioned in the vmkr documentation by Bell-Northern Research VHDL > Group > (http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhd...= ) > but no other references found. > > Does anyone know where I can find this article/book? > > As a parting note, does anyone have any suggestion/recommendation on the > usage of vmkr? Google provides some links if you just search for "makefiles bergeron": - www.vhdl.org/misc/ModelingGuidelines.paper.ps - pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf Regards, Daniel From newsfish@newsfish Tue Aug 9 07:53:44 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!m6g2000prh.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Conditional declarations Date: Wed, 20 Jul 2011 11:14:55 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311185696 17473 127.0.0.1 (20 Jul 2011 18:14:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 18:14:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m6g2000prh.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5162 Hello, I keep running across situations where a conditional variable or signal declaration would be very useful in simulation (for instance, declaring full range integers or reals), but I don't want any of these to attempt to be synthesized. Is there an eloquent way of doing this? I don't believe you can use the generate statement for declarations. I have heard of people using the C preprocessor for this, but this seems like a hack IMO. Colin From newsfish@newsfish Tue Aug 9 07:53:44 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!x19g2000prc.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations Date: Wed, 20 Jul 2011 11:52:09 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311187929 7249 127.0.0.1 (20 Jul 2011 18:52:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 18:52:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x19g2000prc.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5163 On Jul 20, 11:14=A0am, Colin Beighley wrote: > Hello, > > I keep running across situations where a conditional variable or > signal declaration would be very useful in simulation (for instance, > declaring full range integers or reals), but I don't want any of these > to attempt to be synthesized. Is there an eloquent way of doing this? > I don't believe you can use the generate statement for declarations. I > have heard of people using the C preprocessor for this, but this seems > like a hack IMO. > > Colin Okay so I had a brain fart and forgot about --synthesis translate_off. I've also looked into the archives and seen that it doesn't seem to be supported for synthesis, though, except for within conditional generate statements. From newsfish@newsfish Tue Aug 9 07:53:44 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 20 Jul 2011 14:47:13 -0500 Date: Wed, 20 Jul 2011 20:47:12 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc15 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 34 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-SioX3dfj62tkLiundsiGqLo2Xx2hOXtNe5I9nNqOaasIkfUhcfGUWQAuBHstn8lHxXPwaV5ja6mDdJy!pnybO07QLgtvt5PJzZN1NWK+leLdYn+5wEtXp91BYE3iIiDBs8of7e1Dh7jalQeI6HcmAqZUyzaG!LQfHe7U4VMCCkjaknzwWhapf X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2494 Xref: feeder.eternal-september.org comp.lang.vhdl:5164 On 20/07/11 19:52, Colin Beighley wrote: > On Jul 20, 11:14 am, Colin Beighley wrote: >> Hello, >> >> I keep running across situations where a conditional variable or >> signal declaration would be very useful in simulation (for instance, >> declaring full range integers or reals), but I don't want any of these >> to attempt to be synthesized. Is there an eloquent way of doing this? >> I don't believe you can use the generate statement for declarations. I >> have heard of people using the C preprocessor for this, but this seems >> like a hack IMO. >> >> Colin > > Okay so I had a brain fart and forgot about --synthesis translate_off. > I've also looked into the archives and seen that it doesn't seem to be > supported for synthesis, though, except for within conditional > generate statements. Synthesis meta comments should work fine - just use the right ones :-) I wrote a little technote on the Doulos Website about such issues which might be of interest http://www.doulos.com/knowhow/fpga/technotes/index.php#Technote2 regards Alan P.S. There *is* an option to opt out of being contacted during registration for the download, honestly! -- Alan Fitch From newsfish@newsfish Tue Aug 9 07:53:44 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h17g2000yqn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz Date: Wed, 20 Jul 2011 13:59:43 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311195659 20504 127.0.0.1 (20 Jul 2011 21:00:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 21:00:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h17g2000yqn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5165 On Jul 20, 12:35=A0pm, Rob Gaddi wrote: > > What on earth are you actually trying to accomplish Homework perhaps. From newsfish@newsfish Tue Aug 9 07:53:45 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!x10g2000vbl.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations Date: Wed, 20 Jul 2011 14:03:41 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <6f67e2e7-6eb1-449a-ad09-66bfad04e371@x10g2000vbl.googlegroups.com> References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311196186 25698 127.0.0.1 (20 Jul 2011 21:09:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 21:09:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x10g2000vbl.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5166 On Jul 20, 2:14=A0pm, Colin Beighley wrote: > Hello, > > I keep running across situations where a conditional variable or > signal declaration would be very useful in simulation (for instance, > declaring full range integers or reals), but I don't want any of these > to attempt to be synthesized. Is there an eloquent way of doing this? > I don't believe you can use the generate statement for declarations. I > have heard of people using the C preprocessor for this, but this seems > like a hack IMO. > You can declare signals within a generate statement. Then set the generate condition appropriately to not generate for synthesis. if xxx generate signal xyz_real: real; begin xyz <=3D to_real(xyz_fp); end generate xxx; Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:45 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d1g2000yqm.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: automating bringing of signals in hierarchical VHDL model to top level entity Date: Wed, 20 Jul 2011 15:09:04 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: NNTP-Posting-Host: 86.45.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311199744 29046 127.0.0.1 (20 Jul 2011 22:09:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 22:09:04 +0000 (UTC) Cc: fearghal.morgan@nuigalway.ie Complaints-To: groups-abuse@google.com Injection-Info: d1g2000yqm.googlegroups.com; posting-host=86.45.244.35; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5167 Hi, I=92d be grateful if anyone could advise on whether an application is available to do the following for VHDL models. Fearghal 1. Make a replica copy of a selected multi-file and hierarchical VHDL design 2. Modify each VHDL file in the copied hierarchical VHDL model (possibly using the make file sequence), in order to bring all (or selected) signals to the top level VHDL entity. 3. Steps: a. modify each VHDL files in turn to bring every (or selected) internal signal as an output signals in VHDL entity b. Modify the associated component declarations within package files to reflect the modified entity ports c. Rebuild the VHDL hierarchy adding the new output ports to all entities in the hierarchy d. Modify all port map assignments to mirror the extended entity ports. My application requires interpreting any existing VHDL model, selecting signals from within the VHDL model to bring to the top level entity in order to connect to a series of display devices. I do not wish to modify the underlying VHDL code. From newsfish@newsfish Tue Aug 9 07:53:45 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!j9g2000prj.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Wed, 20 Jul 2011 17:24:14 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311207936 14323 127.0.0.1 (21 Jul 2011 00:25:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 00:25:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000prj.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5168 On Jul 20, 3:09=A0pm, fearg wrote: > Hi, I=92d be grateful if anyone could advise on whether an application > is available to do the following for VHDL models. > Fearghal > > 1. =A0 =A0 =A0Make a replica copy of a selected multi-file and hierarchic= al VHDL > design > 2. =A0 =A0 =A0Modify each VHDL file in the copied hierarchical VHDL model > (possibly using the make file sequence), in order to bring all (or > selected) signals to the top level VHDL entity. > 3. =A0 =A0 =A0Steps: > a. =A0 =A0 =A0modify each VHDL files in turn to bring every (or selected) > internal signal as an output signals in VHDL entity > b. =A0 =A0 =A0Modify the associated component declarations within package= files > to reflect the modified entity ports > c. =A0 =A0 =A0Rebuild the VHDL hierarchy adding the new output ports to a= ll > entities in the hierarchy > d. =A0 =A0 =A0Modify all port map assignments to mirror the extended enti= ty > ports. > > My application requires interpreting any existing VHDL model, > selecting signals from within the VHDL model to bring to the top level > entity in order to connect to a series of display devices. I do not > wish to modify the underlying VHDL code. It seems VHDL-2008 has some support similar to this. Doulos says that it is not synthesizable, however. http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease= /#hierarchicalnames Look at the section Hierarchical Names. From newsfish@newsfish Tue Aug 9 07:53:45 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!ft10g2000vbb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz Date: Wed, 20 Jul 2011 18:18:54 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <1e70f957-6212-4924-add1-13995c0d1e66@ft10g2000vbb.googlegroups.com> References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311211501 17305 127.0.0.1 (21 Jul 2011 01:25:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 01:25:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: ft10g2000vbb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5169 On Jul 20, 10:48=A0am, majmoat_ensan wrote: > > ummm if i tried to wrote it in this way is it right or not? > Not. Not even close (to be more precise) Consider downloading either a free version of Modelsim or GHDL and start compiling and simulating your code. The tool will give you must quicker and more detailed responses to your questions...it will also let you simulate your design to see if it works as you intend. Learning by doing is a very effective method. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:45 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p20g2000yqp.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Wed, 20 Jul 2011 18:07:13 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311212098 22877 127.0.0.1 (21 Jul 2011 01:34:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 01:34:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p20g2000yqp.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5170 On Jul 20, 6:09=A0pm, fearg wrote: > > My application requires interpreting any existing VHDL model, > selecting signals from within the VHDL model to bring to the top level > entity in order to connect to a series of display devices. I do not > wish to modify the underlying VHDL code. The easiest method to do what you say in the above paragraph is to simply use the debug capabilities of the synthesis tool. Each tool will let you select arbitrary signals from within a design and bring them out to a set of pins which you select. These signals are generally intended to be connected to a logic analyzer...but there is no reason they can't be connected to the display devices that you require. No code changes required. However, if you have some other reason for requiring a VHDL model thus leading to your steps 1-3d than this method won't work. So you need to decide if you're looking for a VHDL model or simply something that is implemented in hardware. If it's hardware only, use the logic analyzer interface approach. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:45 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g5g2000prn.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Attribute that shows if signal is clocked or not? Date: Wed, 20 Jul 2011 19:17:21 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311214641 16573 127.0.0.1 (21 Jul 2011 02:17:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 02:17:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g5g2000prn.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5171 Hello, Is there a VHDL attribute that tells whether or not a signal is driven synchronously or asynchronously? I have found a place in my design where I think a latch would be nice to use, but I'd like to have some sort of assert statement like the following to make sure it isn't driven asynchronously. assert latch_enable'synchronous report "Latch enable must be a synchronous signal to avoid glitches" severity failure; Thanks, Colin From newsfish@newsfish Tue Aug 9 07:53:45 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!dp9g2000vbb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Attribute that shows if signal is clocked or not? Date: Wed, 20 Jul 2011 20:51:05 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <6ea926a5-34c8-4bbc-ba2d-3dc13fe456f7@dp9g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311220617 11093 127.0.0.1 (21 Jul 2011 03:56:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 03:56:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dp9g2000vbb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5172 On Jul 20, 10:17=A0pm, Colin Beighley wrote: > Hello, > > Is there a VHDL attribute that tells whether or not a signal is driven > synchronously or asynchronously? No > I have found a place in my design > where I think a latch would be nice to use, If this is targetting an FPGA, then check to make sure that the target device actually has a latch primitive. If not, then the synthesis tool will implement the latch with logic and you'll likely find that using a latch is not so nice after all. Even if the FPGA *does* have latches, you'll have to manually check to see that the implemented design actually does use the latch primitive rather than cobbling it together with logic cells. > but I'd like to have some > sort of assert statement like the following to make sure it isn't > driven asynchronously. > Sound like you're into generating internal clock-like signsls...if the target device is an FPGA you'll likely regret this decision. Data hold timing will bite you. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:46 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!e8g2000yqi.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Wed, 20 Jul 2011 23:56:03 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: References: NNTP-Posting-Host: 86.45.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311231765 25670 127.0.0.1 (21 Jul 2011 07:02:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 07:02:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e8g2000yqi.googlegroups.com; posting-host=86.45.244.35; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5173 thanks for the suggestions Colin and Kevin. I'll look into the synthesis debug and VHDL-2008 options. However, Ideally I'd like an easy to use an application independent of synthesis tools and may have to develop a generic solution myself. Fearghal Morgan From newsfish@newsfish Tue Aug 9 07:53:46 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Thu, 21 Jul 2011 10:05:27 +0200 Lines: 16 Message-ID: <98q4u5FfklU1@mid.individual.net> References: <98l51iFmp5U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Re64KJ6ETNrOr+FIc4Cgag1ps1pe6t/ErPtegzx1g7VLuUuM25 Cancel-Lock: sha1:DsVggtuUjP5SjZmBW3YEBWd1OKM= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5174 On 7/20/2011 7:14 PM, Daniel Leu wrote: > Google provides some links if you just search for "makefiles > bergeron": > - www.vhdl.org/misc/ModelingGuidelines.paper.ps This (IMHO very interesting) article is "Guidelines for Writing VHDL Models in a Team Environment". > - pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf > This is "Managing VHDL Models with Makefiles". Thanks for pointing them out, I'm trying to subscribe to "Verification Guild" but I still have some problems. From newsfish@newsfish Tue Aug 9 07:53:46 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!j9g2000prj.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations Date: Thu, 21 Jul 2011 09:13:09 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <19cfaf6d-f58f-4346-bf90-55b5d9f0a1d3@j9g2000prj.googlegroups.com> References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> <6f67e2e7-6eb1-449a-ad09-66bfad04e371@x10g2000vbl.googlegroups.com> NNTP-Posting-Host: 67.180.134.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311264872 31649 127.0.0.1 (21 Jul 2011 16:14:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 16:14:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000prj.googlegroups.com; posting-host=67.180.134.147; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5175 On Jul 20, 2:03=A0pm, KJ wrote: > On Jul 20, 2:14=A0pm, Colin Beighley wrote: > > > Hello, > > > I keep running across situations where a conditional variable or > > signal declaration would be very useful in simulation (for instance, > > declaring full range integers or reals), but I don't want any of these > > to attempt to be synthesized. Is there an eloquent way of doing this? > > I don't believe you can use the generate statement for declarations. I > > have heard of people using the C preprocessor for this, but this seems > > like a hack IMO. > > You can declare signals within a generate statement. =A0Then set the > generate condition appropriately to not generate for synthesis. > > if xxx generate > =A0 =A0signal xyz_real: =A0real; > begin > =A0 =A0xyz <=3D to_real(xyz_fp); > end generate xxx; > > Kevin Jennings So I think the --synthesis translate_off/on statements will give me the functionality I need for simulation vs synthesis, but a conditional declaration of the #ifdef type would still be useful. Signals declared in generate statements are limited in scope to their generate statement, correct? From newsfish@newsfish Tue Aug 9 07:53:46 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Thu, 21 Jul 2011 09:32:20 -0700 Lines: 21 Message-ID: <98r2l5Fjb4U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net cwRujlUFp+KtK0AgSWoCWQxXkPWGBGei77OGWm11ay4FkrlMVe Cancel-Lock: sha1:TqnM+a2CcG2WNhhBMnuCF+E6+44= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5176 On 7/20/2011 11:56 PM, fearg wrote: > thanks for the suggestions Colin and Kevin. > I'll look into the synthesis debug and VHDL-2008 options. > However, Ideally I'd like an easy to use an application independent of > synthesis tools How will you connect the "display devices" to the fpga without editing code and running synthesis to make the new interface. > and may have to develop a generic solution myself. 1. Copy code 2. Edit the code (manual or script) 3. Synthesize the code and load an fpga image 4. Hook up the displays and test. Seems to me that it might be easier to write a testbench and watch the internal waves directly, as Kevin suggests. -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:53:46 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!v7g2000vbk.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations Date: Thu, 21 Jul 2011 09:40:10 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> <6f67e2e7-6eb1-449a-ad09-66bfad04e371@x10g2000vbl.googlegroups.com> <19cfaf6d-f58f-4346-bf90-55b5d9f0a1d3@j9g2000prj.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311266410 14639 127.0.0.1 (21 Jul 2011 16:40:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 16:40:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v7g2000vbk.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5177 On Jul 21, 12:13=A0pm, Colin Beighley wrote: > On Jul 20, 2:03=A0pm, KJ wrote: > > > > > > > On Jul 20, 2:14=A0pm, Colin Beighley wrote: > > > > Hello, > > > > I keep running across situations where a conditional variable or > > > signal declaration would be very useful in simulation (for instance, > > > declaring full range integers or reals), but I don't want any of thes= e > > > to attempt to be synthesized. Is there an eloquent way of doing this? > > > I don't believe you can use the generate statement for declarations. = I > > > have heard of people using the C preprocessor for this, but this seem= s > > > like a hack IMO. > > > You can declare signals within a generate statement. =A0Then set the > > generate condition appropriately to not generate for synthesis. > > > if xxx generate > > =A0 =A0signal xyz_real: =A0real; > > begin > > =A0 =A0xyz <=3D to_real(xyz_fp); > > end generate xxx; > > > Kevin Jennings > > So I think the --synthesis translate_off/on statements will give me > the functionality I need for simulation vs synthesis, but a > conditional declaration of the #ifdef type would still be useful. > Signals declared in generate statements are limited in scope to their > generate statement, correct?- Hide quoted text - > Yes, the signals are limited in scope to being within the generate statement. But that doesn't mean that they can't access things that are outside of scope. You asked for a conditional method to declare signals (and presumably use them) for simulation but not synthesis. That's precisely what the language itself can provide you with the generate statement. The translate_off/on has some limitations: - translate_off/on is not conditional 'as-is' (which would seem to violate what you said you were looking for). People do play games with how they write the text to accomplish their specific goals, but it is always kludgy - translate_off/on is a pragma that is embedded within a comment...so it rightfully gets ignored by other tools. This implies that your simulations will compile and run just fine, only when you run the synthesis tool do you find that you have an 'off' without an 'on' or typed 'translate off' or 'translate on' or some other simple misspelling. They don't necessarily take long to clean up and fix, but why bother when the generate statement is accepted by all tools since it is part of the language and does what it appears that you need? If it doesn't perhaps you should explain a bit more about how the example I gave you doesn't meet your needs and we can go from there. About the only limitation of the generate statement I can think of is that it is only applicable inside the architecture of an entity. In particular it cannot be used in code that is in a package. There you would have to use translate_off/on. Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:46 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Attribute that shows if signal is clocked or not? Date: Thu, 21 Jul 2011 13:37:37 -0400 Organization: Alacron, Inc. Lines: 40 Message-ID: References: <6ea926a5-34c8-4bbc-ba2d-3dc13fe456f7@dp9g2000vbb.googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 21 Jul 2011 17:37:56 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="SUqs68xEs9YfAtSSdphhXg"; logging-data="2280"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+rpnt6Ydi6/ecaanBcM/K4" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <6ea926a5-34c8-4bbc-ba2d-3dc13fe456f7@dp9g2000vbb.googlegroups.com> Cancel-Lock: sha1:CzLC9HdfEfm33BCg6SUUGk7Vk8Q= Xref: feeder.eternal-september.org comp.lang.vhdl:5178 KJ wrote: > On Jul 20, 10:17 pm, Colin Beighley wrote: >> Hello, >> >> Is there a VHDL attribute that tells whether or not a signal is driven >> synchronously or asynchronously? > > No > >> I have found a place in my design >> where I think a latch would be nice to use, > > If this is targetting an FPGA, then check to make sure that the target > device actually has a latch primitive. If not, then the synthesis > tool will implement the latch with logic and you'll likely find that > using a latch is not so nice after all. > > Even if the FPGA *does* have latches, you'll have to manually check to > see that the implemented design actually does use the latch primitive > rather than cobbling it together with logic cells. > >> but I'd like to have some >> sort of assert statement like the following to make sure it isn't >> driven asynchronously. >> > > Sound like you're into generating internal clock-like signsls...if the > target device is an FPGA you'll likely regret this decision. Data > hold timing will bite you. > > Kevin Jennings Regardless of your target, most synthesis tools will warn when you create latches. I haven't seen any that allow you to promote a latch warning to an error, but you can always grep the synthesis report to see if any latch warnings were generated. I'm sure that reading through the warnings after synthesis is a useful exercise anyway... -- Gabor From newsfish@newsfish Tue Aug 9 07:53:47 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!i6g2000yqe.googlegroups.com!not-for-mail From: thunder Newsgroups: comp.lang.vhdl Subject: Assertions Date: Fri, 22 Jul 2011 04:21:07 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> NNTP-Posting-Host: 194.200.65.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311333667 14565 127.0.0.1 (22 Jul 2011 11:21:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Jul 2011 11:21:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i6g2000yqe.googlegroups.com; posting-host=194.200.65.239; posting-account=fYOi-AoAAAAftKwn8h0pIn0WrxqvjnVx User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18 GTB7.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5179 Hello We do our development work in VHDL. We are starting to formulate our ABV strategy and are currently thinking of using PSL assertions to either imbed in the VHDL code or define the PSL assertions as vunits. However, another line of thought is to use System Verilog assertions with the VHDL RTL, since later on we want to go down the UVM strategy and Random Constrained Verification. QS: Does anyone have any feel for 1) how easy/difficult it is to connect the System Verilog assertions to the VHDL RTL? 2) How easy/difficult it will be to debug the assertions if we adopt the System Verilog assertions and VHDL? Thanks J From newsfish@newsfish Tue Aug 9 07:53:47 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe13.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Assertions References: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> In-Reply-To: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110722-0, 22/07/2011), Outbound message X-Antivirus-Status: Clean Lines: 67 Message-ID: NNTP-Posting-Host: 82.31.236.233 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe13.ams2 1311347827 82.31.236.233 (Fri, 22 Jul 2011 15:17:07 UTC) NNTP-Posting-Date: Fri, 22 Jul 2011 15:17:07 UTC Organization: virginmedia.com Date: Fri, 22 Jul 2011 16:17:15 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5180 On 22/07/2011 12:21, thunder wrote: > Hello > > We do our development work in VHDL. > Good! > We are starting to formulate our ABV strategy and are currently > thinking of using PSL assertions to either imbed in the VHDL code or > define the PSL assertions as vunits. You will probably use both. > > However, another line of thought is to use System Verilog assertions > with the VHDL RTL, since later on we want to go down the UVM strategy I wouldn't worry to much, there is quite some similarity between PSL and SVA as both standards are maintained/developed by Accellera. If you use VHDL then I would suggest you stick with PSL. You will learn it quicker than SVA as you can use familiar operators and constructs (AND, OR, is, to, rising_edge etc). I also believe IMHO that PSL is easier to learn than SVA. The disadvantage of PSL (as is with VHDL) is that EDA vendors seem to spend their R&D budget on SV and SVA only. This is not because these languages are superior but simply because of the 20/80 rule (80% of their revenue comes from 20% of their customers and these 20% are all big Verilog/SV ASIC users). For PSL you also need to use a bit of extra code as bins and related verification constructs are not part of the standard. > and Random Constrained Verification. You can do CR with VHDL as well. Jim Lewis has a great CR package on his website. What is lacking is support for a constraint solver but you should be able to cook something up using the FLI/VHPI. > > QS: Does anyone have any feel for > 1) how easy/difficult it is to connect the System Verilog > assertions to the VHDL RTL? Not difficult, you simply "bind" the SVA module to your VHDL entity/architecture. Note that SVA does not support embedded assertions. > 2) How easy/difficult it will be to debug the assertions if > we adopt the System Verilog assertions and VHDL? It depends on your simulator but I suspect no different from debugging PSL. Good luck, Hans www.ht-lab.com > > > Thanks > > J From newsfish@newsfish Tue Aug 9 07:53:47 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!r18g2000vbs.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Fri, 22 Jul 2011 14:55:51 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <13559aa6-3773-4e6a-bfd8-814e2e0365f8@r18g2000vbs.googlegroups.com> References: NNTP-Posting-Host: 86.46.41.133 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311371752 12327 127.0.0.1 (22 Jul 2011 21:55:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Jul 2011 21:55:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r18g2000vbs.googlegroups.com; posting-host=86.46.41.133; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5181 Colin, the hierarchical access in VHDL-2008 is useful. I do need to synthesise the model with signal brought to the top level though. Fearghal > > It seems VHDL-2008 has some support similar to this. Doulos says that > it is not synthesizable, however.http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200... > Look at the section Hierarchical Names. From newsfish@newsfish Tue Aug 9 07:53:47 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b19g2000yqj.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Fri, 22 Jul 2011 15:16:21 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> NNTP-Posting-Host: 86.46.41.133 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311373833 960 127.0.0.1 (22 Jul 2011 22:30:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Jul 2011 22:30:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b19g2000yqj.googlegroups.com; posting-host=86.46.41.133; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5182 Kevin, I generally use Xilinx XST synthesis tool. Could you please point me to the debug facility within XST which allows the bringing of internal signals to the top level (if this exists)? I should clarify my requirement further: For any existing design VHDL model entity (e.g, designX), I wish to automatically modify the VHDL files to bring selected output signals from low levels of the design hierarchy to the designX entity. I then instantiate designX within another VHDL model (designTop) which contains the host interface and display device controller, and connect the newly accessible signals as required for output to host and display devices. If the above can be automated, I can quickly take any design and connect its internal signals to my host and display interfaces. I do not wish to use a logic analyser facility. > The easiest method to do what you say in the above paragraph is to > simply use the debug capabilities of the synthesis tool. =A0Each tool > will let you select arbitrary signals from within a design and bring > them out to a set of pins which you select. =A0These signals are > generally intended to be connected to a logic analyzer...but there is > no reason they can't be connected to the display devices that you > require. =A0No code changes required. > > However, if you have some other reason for requiring a VHDL model thus > leading to your steps 1-3d than this method won't work. =A0So you need > to decide if you're looking for a VHDL model or simply something that > is implemented in hardware. =A0If it's hardware only, use the logic > analyzer interface approach. > > Kevin Jennings From newsfish@newsfish Tue Aug 9 07:53:47 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a2g2000prf.googlegroups.com!not-for-mail From: abhishekshishodia Newsgroups: comp.lang.vhdl Subject: Design Built-in Self Test Date: Fri, 22 Jul 2011 23:05:20 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <72360074-df74-4637-8bf9-e8725151f1ba@a2g2000prf.googlegroups.com> NNTP-Posting-Host: 117.211.93.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311401467 20257 127.0.0.1 (23 Jul 2011 06:11:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 23 Jul 2011 06:11:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a2g2000prf.googlegroups.com; posting-host=117.211.93.74; posting-account=fcag1AoAAACji3PtI5a5Ab8a5Gkwbqqb User-Agent: G2/1.0 X-HTTP-Via: 1.0 Webcat-Skein-C010001296-GEHY2E (awarrenhttp/2.0.0.5.4) X-Google-Web-Client: true X-Google-Header-Order: ARLEUHNKCV X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5183 Hello freinds, I am final yr. graduating student of enginnering. I have to do a major project for which I have decided to design Built-in self test fo memory testing. Please tell me how could I design memory(eg. RAM) in VHDL. I only know that I could need ModelSIM and synopsys software dc_shell for doing this. Please tell me how could I implement RAM in VHDL and then design a built-in self test for testing that memory. -Abhishek From newsfish@newsfish Tue Aug 9 07:53:47 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!df3g2000vbb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Design Built-in Self Test Date: Sat, 23 Jul 2011 10:05:40 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: References: <72360074-df74-4637-8bf9-e8725151f1ba@a2g2000prf.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311441547 3792 127.0.0.1 (23 Jul 2011 17:19:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 23 Jul 2011 17:19:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: df3g2000vbb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5184 On Jul 23, 2:05=A0am, abhishekshishodia wrote: > Hello freinds, > > I am final yr. graduating student of enginnering. I have to do a major > project for which I have decided =A0to design Built-in self test fo > memory testing. > Please tell me how could I design memory(eg. RAM) in VHDL. I only know > that I could need ModelSIM and synopsys software dc_shell for doing > this. Please tell me how could I implement RAM in VHDL and then design > a built-in self test for testing that memory. > Try using Google http://lmgtfy.com/?q=3Dhow+could+I+implement+RAM+in+VHDL+and+then+design+ Some examples that pop out http://quartushelp.altera.com/current/mergedProjects/hdl/vhdl/vhdl_pro_ram_= inferred.htm http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.h= tml KJ From newsfish@newsfish Tue Aug 9 07:53:48 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Sun, 24 Jul 2011 00:27:45 +0200 Lines: 11 Message-ID: <99106uFbt6U1@mid.individual.net> References: <98l51iFmp5U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 5rOYWxieqiwSMUIBvOqdvA+nPokXt/0SOCBtc7y7nMYcDScFcV Cancel-Lock: sha1:AXqEQz91s6nWfY8xUkMy5997aVY= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5185 On 7/20/2011 1:31 AM, Alan Fitch wrote: > Try posting your message on the Verification Guild > http://verificationguild.com (I think, from memory). Janick started the > website, and often posts there, > In case somebody maybe interested, the article in the subject is indeed this one: "Managing VHDL Models with Makefiles" by Janick Bergeron (http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf) From newsfish@newsfish Tue Aug 9 07:53:48 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!o4g2000vbv.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Sun, 24 Jul 2011 06:53:05 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <05079553-9b34-40cb-a879-d4918cc70b6f@o4g2000vbv.googlegroups.com> References: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> NNTP-Posting-Host: 86.46.39.61 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311515585 6463 127.0.0.1 (24 Jul 2011 13:53:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 24 Jul 2011 13:53:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o4g2000vbv.googlegroups.com; posting-host=86.46.39.61; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5186 Hi, if I can extracta listing of component and signal hierarchy from ISE (to a file), I could investigate writing a program to automate the addition and connection of lower level signals up to the top level. Its tedious manually, and would benefit from automation. I'd require the generation of a listing something like the following from an EDA tool: topLevel/LA1:A1/LB1:B1/LC1:C1/sigX sigLC1X where: LA1 is the label for component A1, instantiated in topLevel VHDL model LB1 is the label for component B1, instantiated in A1 VHDL model LC1 is the label for component C1, instantiated in B1 VHDL model sigX is VHDL model C1 entity signal sigLC1X is the port map signal in the VHDL model B1, used to connect to component C1 port sigX topLevel/LA1:A1/LB1:B1/LC1:C1/sigY sigLC1Y topLevel/LA1:A1/LB1:B1/LC2:C1/sigX sigLC2X topLevel/LA1:A1/LB1:B1/LC2:C1/sigY sigLC2Y topLevel/LA1:A1/LB1:B1/LC3:C2/sigP sigLC3P etc Note: in this example, component C1 is used twice in VHDL model B1. sigLC2X is the port map signal in the VHDL model B1, used to connect to component C2 port sigX I would be grateful for any advice. regards, Fearghal From newsfish@newsfish Tue Aug 9 07:53:48 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!dp9g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Mon, 25 Jul 2011 05:57:25 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311598646 2706 127.0.0.1 (25 Jul 2011 12:57:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Jul 2011 12:57:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dp9g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5187 On 24 Jul., 00:27, Alessandro Basili wrote: > On 7/20/2011 1:31 AM, Alan Fitch wrote: > > > Try posting your message on the Verification Guild > >http://verificationguild.com(I think, from memory). Janick started the > > website, and often posts there, > > In case somebody maybe interested, the article in the subject is indeed > this one: > > "Managing VHDL Models with Makefiles" by Janick Bergeron > (http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf) Where can the tools described be downloaded ? Cheers, hssig From newsfish@newsfish Tue Aug 9 07:53:48 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Mon, 25 Jul 2011 16:32:05 +0200 Lines: 18 Message-ID: <995d36FlvbU1@mid.individual.net> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net bUS7jSuUlGmRNLqgpzdPewfw99GSuTz9Zi+V/Ze6HNhmz4chN+ Cancel-Lock: sha1:FA2p291dKg1ZWmWa7iQz880Y0Dc= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5188 On 7/25/2011 2:57 PM, hssig wrote: In case somebody maybe interested, the article in the subject is indeed >> this one: >> >> "Managing VHDL Models with Makefiles" by Janick Bergeron >> (http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf) > > > > > Where can the tools described be downloaded ? > http://sourceforge.net/projects/vmk/ > Cheers, hssig > From newsfish@newsfish Tue Aug 9 07:53:48 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Tue, 26 Jul 2011 08:05:52 +0200 Lines: 65 Message-ID: <9973q0Fvb9U1@mid.individual.net> References: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> <05079553-9b34-40cb-a879-d4918cc70b6f@o4g2000vbv.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net B7uofcO8EF1pwe7a0GHqAw9tXQ1YK6Smygfjmfoy4SODPIZsnE Cancel-Lock: sha1:FRKuzNzpH/7l4UiFB1MKk8CF2Vc= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <05079553-9b34-40cb-a879-d4918cc70b6f@o4g2000vbv.googlegroups.com> X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5189 On 7/24/2011 3:53 PM, fearg wrote: > Hi, > > if I can extracta listing of component and signal hierarchy from ISE > (to a file), Emacs speedbar does it for you, you only need the vhdl file(s). > I could investigate writing a program to automate the > addition and connection of lower level signals up to the top level. > Its tedious manually, and would benefit from automation. > For testing purposes you may add a jtag port to every component, connect it in a daisy chain and play around with Boundary Scan Register and Instruction Register. But you cannot have it operational while you are in (IN/EX)TEST mode. > I'd require the generation of a listing something like the following > from an EDA tool: [snip] > Note: in this example, component C1 is used twice in VHDL model B1. > sigLC2X is the port map signal in the VHDL model B1, used to > connect to component C2 port sigX > I once was convinced that defining the signals in a package so that they are seen as global and therefore "available" to the whole hierarchy was a good thing. In that case I could have set the registers in one module and use it in another without the need to go through In/Out. In that approach connecting a signal to the top level was as simple as doing: pin_out <= global_signal; I found later on it was a very bad practice, since it resulted in a very poorly reusable code and I spent most of my time trying to remember where the heck in my code I was using those registers (pretty much the same as any other programming/description language). > My application requires interpreting any existing VHDL model, > selecting signals from within the VHDL model to bring to the top level > entity in order to connect to a series of display devices. I do not > wish to modify the underlying VHDL code. I'm assuming your "existing VHDL model" is an open hierarchical model where you have access to all the components interfaces it uses. If that is the case editing the code and picking up the signals you want (as suggested) is much simpler. If your "existing VHDL model" is the output of an edif2vhdl converter or a back-annotate process there's no way to do what you want, since I'm pretty convinced the output vhdl would be rather "flat" as opposed to hierarchical. Bear in mind that if a signal is not accessible from the top level it might be a good thing. After all you are interested in the functionality of the code, not the details of the flops and gates. And if you are debugging the module there's no better place than your simulation, much more effective and less time consuming. Set aside that if your are targeting a antifuse logic device all your tries will end up in a lot of chips thrown out of the window. Al From newsfish@newsfish Tue Aug 9 07:53:48 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!y8g2000vba.googlegroups.com!not-for-mail From: Zaid Al-Hilli Newsgroups: comp.lang.vhdl Subject: Exponential code in VHDL Date: Wed, 27 Jul 2011 02:19:26 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 156.83.0.157 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311758467 7948 127.0.0.1 (27 Jul 2011 09:21:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 Jul 2011 09:21:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y8g2000vba.googlegroups.com; posting-host=156.83.0.157; posting-account=LM0U2goAAACleGp6JGa5rJniGZDMIzml User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5190 Hi all, I am about implementing a VHDL code but I am facing problem, I have an exponential operation and I want to run that code op an FPGA board!! Generally speaking the assignment is: X = (1 / (1+ exp((y + 87.8) / 8.5))); Would you please help me in that? Many thanks in advance... Zaid From newsfish@newsfish Tue Aug 9 07:53:49 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!v7g2000vbk.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Wed, 27 Jul 2011 05:36:08 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311770270 19289 127.0.0.1 (27 Jul 2011 12:37:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 Jul 2011 12:37:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v7g2000vbk.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.19) Gecko/20110707 Firefox/3.6.19,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5191 Is there a possibility to use that tool under Windows (7) ? How do I have to install it? Cheers, hssig From newsfish@newsfish Tue Aug 9 07:53:49 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Wed, 27 Jul 2011 15:18:18 +0200 Lines: 17 Message-ID: <99ahgpF1ndU1@mid.individual.net> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ROWFufP2WkP/eBl4YbjG+Asu9+Sl6TmZhJ/eFcgAEOezTh52/U Cancel-Lock: sha1:+NyZ4byOOoR+U/CYNhpmIWL5sqg= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5192 On 7/27/2011 2:36 PM, hssig wrote: > Is there a possibility to use that tool under Windows (7) ? How do I > have to install it? I think it is possible, if you have cygwin installed: http://www.cygwin.com/ you should be able to install with a simple "make" command from the top level directory. I have to say I have not tried it yet. Just looking into it these days. > > Cheers, > hssig > From newsfish@newsfish Tue Aug 9 07:53:49 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe24.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> In-Reply-To: <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110727-0, 27/07/2011), Outbound message X-Antivirus-Status: Clean Lines: 24 Message-ID: NNTP-Posting-Host: 82.31.236.233 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe24.ams2 1311778336 82.31.236.233 (Wed, 27 Jul 2011 14:52:16 UTC) NNTP-Posting-Date: Wed, 27 Jul 2011 14:52:16 UTC Organization: virginmedia.com Date: Wed, 27 Jul 2011 15:52:28 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5193 On 27/07/2011 13:36, hssig wrote: > Is there a possibility to use that tool under Windows (7) ? How do I > have to install it? > > Cheers, > hssig > As suggested earlier why don't you simply use vmake from Modelsim? Vmake can be used without a valid license (just extract after running the installer). Use vcom (also no valid license required) to compile your design followed by running vmake. You can now use any make program under windows (I use nmake from Visual C++) to process it. Vmake can also handle Verilog files but unfortunately not SystemC. Good luck, Hans www.ht-lab.com From newsfish@newsfish Tue Aug 9 07:53:49 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 27 Jul 2011 11:09:00 -0500 Date: Wed, 27 Jul 2011 09:09:02 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> In-Reply-To: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 21 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-PCc6DgvvJ7WjBjw15MDBoWXcEBb9ZvsdiSt651r+HcIvne7HhKlIqfX36VWE+cmBZDDHfJz9bvJkqMG!TD2WzP/sDdeoUIUXrFqRxLwSylWRnBcz3F/oI4OctJp8DBjArI3TsUTukTaZhF++j53HB7swHwJR X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1701 Xref: feeder.eternal-september.org comp.lang.vhdl:5194 On 7/27/2011 2:19 AM, Zaid Al-Hilli wrote: > Hi all, > > I am about implementing a VHDL code but I am facing problem, I have an > exponential operation and I want to run that code op an FPGA board!! > > Generally speaking the assignment is: X = (1 / (1+ exp((y + 87.8) / > 8.5))); > > Would you please help me in that? > > Many thanks in advance... > > Zaid Yeah, bound the range of y sufficiently that you can implement the entire thing in a RAM lookup table. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Tue Aug 9 07:53:49 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!t8g2000prm.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL Date: Wed, 27 Jul 2011 10:23:57 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311787788 12298 127.0.0.1 (27 Jul 2011 17:29:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 Jul 2011 17:29:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t8g2000prm.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-Google-Web-Client: true X-Google-Header-Order: VCRUHALSNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5195 On 27 juil, 05:19, Zaid Al-Hilli wrote: > Hi all, > > I am about implementing a VHDL code but I am facing problem, I have an > exponential operation and I want to run that code op an FPGA board!! > > Generally speaking the assignment is: =A0X =3D (1 / (1+ exp((y + 87.8) / > 8.5))); > > Would you please help me in that? > > Many thanks in advance... > > Zaid One simple way would be to use a look-up table implemented in a ROM. With "y" being the address and X being the data read at "y" address. This solution would work well if the range of "y" in bits is smaller or equal to 16 bits. If "y" is 32-bit wide then I don't think a look- up table implemented in a FPGA-Rom will work. From newsfish@newsfish Tue Aug 9 07:53:49 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c8g2000prn.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Assertions Date: Wed, 27 Jul 2011 18:20:11 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311816012 4662 127.0.0.1 (28 Jul 2011 01:20:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Jul 2011 01:20:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c8g2000prn.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5196 Hi, > We do our development work in VHDL. > > We are starting to formulate our ABV strategy and are currently > thinking of using PSL assertions to either imbed in the VHDL code or > define the PSL assertions as vunits. > > However, another line of thought is to use System Verilog assertions > with the VHDL RTL, since later on we want to go down the UVM strategy > and Random Constrained Verification. I would keep it simple. For assertions in a VHDL program, I would use PSL. Before you invest in System Verilog, you might want to take a look at: http://www.mentor.com/company/industry_keynotes/upload/DVCon-2011.pdf Their claim is that SV + UVM + CRV, but instead that you need an additional intelligent testbench tool to effectively do verification. Hence, it is a significant investment in tools. OTOH, in VHDL, in addition to our Randomization package that Hans mentioned, you might want to also check out our Coverage Package. The 2.1 release takes you part of the way to more effective verification, however, in the next several releases (2.2 due soon), the capability is growing. Check it out at: http://www.synthworks.com/downloads/index.htm Best, Jim From newsfish@newsfish Tue Aug 9 07:53:50 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!a2g2000prf.googlegroups.com!not-for-mail From: noobie Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL Date: Thu, 28 Jul 2011 00:31:40 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <907e30c3-a94a-4dfe-948b-646bbe444c86@a2g2000prf.googlegroups.com> References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 122.174.105.155 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311838301 4846 127.0.0.1 (28 Jul 2011 07:31:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Jul 2011 07:31:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a2g2000prf.googlegroups.com; posting-host=122.174.105.155; posting-account=T25uaQkAAACANge_Tfmo0_JXOli3REzM User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.124 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5197 On Jul 27, 2:19=A0pm, Zaid Al-Hilli wrote: > Hi all, > > I am about implementing a VHDL code but I am facing problem, I have an > exponential operation and I want to run that code op an FPGA board!! > > Generally speaking the assignment is: =A0X =3D (1 / (1+ exp((y + 87.8) / > 8.5))); > > Would you please help me in that? > > Many thanks in advance... > > Zaid Use Taylor series expansion for the calculation of this equation. Use fixed point arithmetic. From newsfish@newsfish Tue Aug 9 07:53:50 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!feeder.erje.net!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Newsgroups: comp.lang.vhdl Date: Thu, 28 Jul 2011 11:15:07 +0200 References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 29 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1311844507 news2.news.xs4all.nl 23870 puiterl/195.242.97.150:44935 Xref: feeder.eternal-september.org comp.lang.vhdl:5198 HT-Lab wrote: > On 27/07/2011 13:36, hssig wrote: >> Is there a possibility to use that tool under Windows (7) ? How do I >> have to install it? >> >> Cheers, >> hssig >> > > As suggested earlier why don't you simply use vmake from Modelsim? The major difference of course between vmake and a program like vmk is that vmake creates a makefile from already compiled libraries and that vmk creates a makefile directly from the VHDL sources. So for the initial compilation vmk must be used. Or manual compilation, and optional use of the vcom option "-just eapbc" and wildcards for the VHDL files. But that does not always work, for example if packages uses other packages from the same library. For keeping libraries up to date vmake might be more convenient to use. I use both vmake and vmk. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Tue Aug 9 07:53:50 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!fv14g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Thu, 28 Jul 2011 05:32:13 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311856760 28645 127.0.0.1 (28 Jul 2011 12:39:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Jul 2011 12:39:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fv14g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.19) Gecko/20110707 Firefox/3.6.19,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5199 Hi Hans, do you have a real example to share in which you use vmake from Modelsim ? Cheers, Hssig From newsfish@newsfish Tue Aug 9 07:53:50 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Should VHDL allow Unicode identifiers and comments Date: 28 Jul 2011 19:13:48 GMT Lines: 20 Message-ID: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Trace: individual.net aFh+Km90xgzFVXRn2JvSPg7hUXLFSC9HygmIs/r06UcbEGiZE= Cancel-Lock: sha1:o0DtTJGtX0kwIS8qhTACav8+Y5Q= User-Agent: Pan/0.133 (House of Butterflies) Xref: feeder.eternal-september.org comp.lang.vhdl:5200 Hi all, I'm asking for a bit of input from the community... As the title says, would you find it of use to allow Unicode identifiers and comments in a future VHDL revision? Would this be: a) Something VHDL should not allow b) Something that doesn't bother you either way c) Something you'd find useful sometimes d) Something you'd make use of all the time e) Something that you'd switch away from SystemVerilog just to get at (maybe I'm asking the wrong crowd for that :) Thanks, Martin -- http://parallelpoints.com/ From newsfish@newsfish Tue Aug 9 07:53:50 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Christopher Felton Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Thu, 28 Jul 2011 16:10:19 -0500 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 28 Jul 2011 21:10:19 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="N63w/DHusx/mn4zn8Evv7g"; logging-data="23350"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Nu2CuKGcewfw4hsEqqOCc" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <99dqncFsnU1@mid.individual.net> Cancel-Lock: sha1:GO+tSqYjKzviUQ1RsAj70Uxl97Y= Xref: feeder.eternal-september.org comp.lang.vhdl:5201 On 7/28/2011 2:13 PM, Martin Thompson wrote: > Hi all, > > I'm asking for a bit of input from the community... > > As the title says, would you find it of use to allow Unicode identifiers > and comments in a future VHDL revision? > > Would this be: > a) Something VHDL should not allow > b) Something that doesn't bother you either way > c) Something you'd find useful sometimes > d) Something you'd make use of all the time > e) Something that you'd switch away from SystemVerilog just to get at > (maybe I'm asking the wrong crowd for that :) > > Thanks, > Martin > b, Regards, Chris Fetlon From newsfish@newsfish Tue Aug 9 07:53:50 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u12g2000prc.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Assertions Date: Thu, 28 Jul 2011 14:10:32 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311887433 17030 127.0.0.1 (28 Jul 2011 21:10:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Jul 2011 21:10:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u12g2000prc.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5202 > We do our development work in VHDL. > > We are starting to formulate our ABV strategy and are currently > thinking of using PSL assertions to either imbed in the VHDL code or > define the PSL assertions as vunits. For VHDL, I would stick with PSL. > However, another line of thought is to use System Verilog assertions > with the VHDL RTL, since later on we want to go down the UVM strategy > and Random Constrained Verification. As an alternative to SV, check out our free open-source VHDL packages for functional coverage and randomization. At the end of the day, I think functional coverage is going to become more and more important. Currently our functional coverage methodology is setup so you can capture high-fidelity functional coverage models and use these go guide your randomization. The packages are available at: http://www.synthworks.com/downloads Best, Jim From newsfish@newsfish Tue Aug 9 07:53:51 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Thu, 28 Jul 2011 16:19:07 -0500 Date: Thu, 28 Jul 2011 14:19:09 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments References: <99dqncFsnU1@mid.individual.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 32 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-hSQ+/AaZB6qSPWLZuX8ga0zOIjeEQbchCsoPpX9W6F3A4y82kxIgVBM5XG0yd6pTcRr1VUABSouTMdG!DFWwFz/bm2hl4kThySdwHcFsWfqn2zO4QNM4oHDkFbXYl0g6F0OC25ZlLZpYVA/oPnnMh1h5q/7R X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1998 Xref: feeder.eternal-september.org comp.lang.vhdl:5203 On 7/28/2011 2:10 PM, Christopher Felton wrote: > On 7/28/2011 2:13 PM, Martin Thompson wrote: >> Hi all, >> >> I'm asking for a bit of input from the community... >> >> As the title says, would you find it of use to allow Unicode identifiers >> and comments in a future VHDL revision? >> >> Would this be: >> a) Something VHDL should not allow >> b) Something that doesn't bother you either way >> c) Something you'd find useful sometimes >> d) Something you'd make use of all the time >> e) Something that you'd switch away from SystemVerilog just to get at >> (maybe I'm asking the wrong crowd for that :) >> >> Thanks, >> Martin >> > > b, > > Regards, > Chris Fetlon Unless the introduction of said identifiers started breaking my existing tools, in which case (a). -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Tue Aug 9 07:53:51 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Thu, 28 Jul 2011 16:45:02 -0700 Lines: 24 Message-ID: <99eakqFo0rU1@mid.individual.net> References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net vUM7bot19e7eLiPWOCfQqQKAe67CpacAMgfbIzCpzHDueqtA6E Cancel-Lock: sha1:ORB23iG1sss9VjLe1lA15X0whBQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <99dqncFsnU1@mid.individual.net> Xref: feeder.eternal-september.org comp.lang.vhdl:5204 On 7/28/2011 12:13 PM, Martin Thompson wrote: > Hi all, > > I'm asking for a bit of input from the community... > > As the title says, would you find it of use to allow Unicode identifiers > and comments in a future VHDL revision? > > Would this be: > a) Something VHDL should not allow > b) Something that doesn't bother you either way > c) Something you'd find useful sometimes c) Yes, will be helpful in the near future. Otherwise everyone will have a different library for it. > d) Something you'd make use of all the time > e) Something that you'd switch away from SystemVerilog just to get at > (maybe I'm asking the wrong crowd for that :) > > Thanks, > Martin > From newsfish@newsfish Tue Aug 9 07:53:51 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t38g2000prj.googlegroups.com!not-for-mail From: JSreeniv Newsgroups: comp.lang.vhdl Subject: Regarding to the DUT configuration in testbench Date: Thu, 28 Jul 2011 19:29:03 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <76b40fe2-f4f9-4f86-83af-d93d2f0d5dd1@t38g2000prj.googlegroups.com> NNTP-Posting-Host: 203.92.217.80 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311906544 16213 127.0.0.1 (29 Jul 2011 02:29:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Jul 2011 02:29:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t38g2000prj.googlegroups.com; posting-host=203.92.217.80; posting-account=cCqSmQoAAAD72P5YVFrs1ZNFbeH4XiZ1 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HURAELSCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.125 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5205 Hi, I was exploring the DUT connectivity with my testbench(TB). What i am doing: With my encrypted DUT i wrote a TB (for reception) MIL 1553 FE by configuring the register to the mode as RT and start sending the command and number of data on 1553_rx lines (where the command and data are Valid) w.r.t the standard and after some response time the transmitter will send a status word followed by data word on 1553_tx lines. The actual query is that can i configure one DUT as BC mode and again same DUT as RT mode (Here we can change DUT names while configuring in ModelSim) so that my TB can handle the communication between BC and RT mode. Since i have only RT terminal register set i can access whatever i want, but i don't have register set for BC but mode setting facility is available for the register. Could anyone suggest me whether this is possible or not and some more analysis. Thanks Nivas. From newsfish@newsfish Tue Aug 9 07:53:51 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> In-Reply-To: <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110728-1, 28/07/2011), Outbound message X-Antivirus-Status: Clean Lines: 32 Message-ID: NNTP-Posting-Host: 82.31.236.233 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1311926302 82.31.236.233 (Fri, 29 Jul 2011 07:58:22 UTC) NNTP-Posting-Date: Fri, 29 Jul 2011 07:58:22 UTC Organization: virginmedia.com Date: Fri, 29 Jul 2011 08:58:35 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5206 On 28/07/2011 13:32, hssig wrote: > Hi Hans, > > do you have a real example to share in which you use vmake from > Modelsim ? > > > Cheers, Hssig > Hi Hssig, If you have Modelsim installed then you can use one of their examples: Navigate to ..\examples\tutorials\vhdl\basicSimulation, then execute vlib work vcom *.vhd vmake > Makefile nmake modify one of the VHDL files and run nmake/make etc again. I would recommend you have a quick look at the vmap command as well as you might need it. Good luck, Hans. www.ht-lab.com From newsfish@newsfish Tue Aug 9 07:53:51 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Fri, 29 Jul 2011 10:55:58 +0100 Organization: Parallel Points Lines: 17 Message-ID: References: <99dqncFsnU1@mid.individual.net> <99eakqFo0rU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net vz/yZxrWka9/m9mv7gPasQwyBk4fAvcYSrooiaQ6cxQKZhO9Q= Cancel-Lock: sha1:XtzvsmPJdk/nyO8psK/iZcjjoGc= sha1:uOhrOKTaBfCvLpO0Tv4oG2j9f4o= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5207 Mike Treseler writes: >> c) Something you'd find useful sometimes > > c) Yes, will be helpful in the near future. > Otherwise everyone will have a different library for it. > I'm not sure I follow Mike - library for what? The original question was about using Unicode within a VHDL source file (for example, variable names and comments). Or are you thinking of having a Unicode "string" replacement - which is a whole different ballgame, but one we maybe ought to think of also! Cheers, Martin From newsfish@newsfish Tue Aug 9 07:53:51 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r18g2000vbs.googlegroups.com!not-for-mail From: Zaid Al-Hilli Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL Date: Fri, 29 Jul 2011 03:41:24 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <59f442ea-cd33-4d80-9ea6-7b4f8fc00e59@r18g2000vbs.googlegroups.com> References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 156.83.0.157 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311936084 26579 127.0.0.1 (29 Jul 2011 10:41:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Jul 2011 10:41:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r18g2000vbs.googlegroups.com; posting-host=156.83.0.157; posting-account=LM0U2goAAACleGp6JGa5rJniGZDMIzml User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5208 On Jul 27, 7:23=A0pm, Benjamin Couillard wrote: > On 27 juil, 05:19, Zaid Al-Hilli wrote: > > > Hi all, > > > I am about implementing a VHDL code but I am facing problem, I have an > > exponential operation and I want to run that code op an FPGA board!! > > > Generally speaking the assignment is: =A0X =3D (1 / (1+ exp((y + 87.8) = / > > 8.5))); > > > Would you please help me in that? > > > Many thanks in advance... > > > Zaid > > One simple way would be to use a look-up table implemented in a ROM. > With "y" being the address and X being the data read at "y" address. > This solution would work well if the range of "y" in bits is smaller > or equal to 16 bits. If "y" is 32-bit wide then I don't think a look- > up table implemented in a FPGA-Rom will work. Thanks a lot! From newsfish@newsfish Tue Aug 9 07:53:52 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!p19g2000yqa.googlegroups.com!not-for-mail From: Zaid Al-Hilli Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL Date: Fri, 29 Jul 2011 03:41:57 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <48b56b50-ad96-49e7-b784-d91a0fb11877@p19g2000yqa.googlegroups.com> References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 156.83.0.157 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311936118 26839 127.0.0.1 (29 Jul 2011 10:41:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Jul 2011 10:41:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p19g2000yqa.googlegroups.com; posting-host=156.83.0.157; posting-account=LM0U2goAAACleGp6JGa5rJniGZDMIzml User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5209 On Jul 27, 6:09=A0pm, Rob Gaddi wrote: > On 7/27/2011 2:19 AM, Zaid Al-Hilli wrote: > > > Hi all, > > > I am about implementing a VHDL code but I am facing problem, I have an > > exponential operation and I want to run that code op an FPGA board!! > > > Generally speaking the assignment is: =A0X =3D (1 / (1+ exp((y + 87.8) = / > > 8.5))); > > > Would you please help me in that? > > > Many thanks in advance... > > > Zaid > > Yeah, bound the range of y sufficiently that you can implement the > entire thing in a RAM lookup table. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Thanks a lot! From newsfish@newsfish Tue Aug 9 07:53:52 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Sat, 30 Jul 2011 00:58:13 -0700 Lines: 25 Message-ID: <99hrsqFfgaU1@mid.individual.net> References: <99dqncFsnU1@mid.individual.net> <99eakqFo0rU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net iDBVZKrbI5LAEQTVvfX+iQUIYUAbVwCEfLOt6jULkztok6ANfB Cancel-Lock: sha1:38dZ3xOSQ5J4uMmLUjTlCrpCPdM= User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5210 On 7/29/2011 2:55 AM, Martin Thompson wrote: > Mike Treseler writes: > >>> c) Something you'd find useful sometimes >> >> c) Yes, will be helpful in the near future. >> Otherwise everyone will have a different library for it. >> > > I'm not sure I follow Mike - library for what? The original question > was about using Unicode within a VHDL source file (for example, variable > names and comments). OK. In that case probably (b) for English speakers. > Or are you thinking of having a Unicode "string" replacement - which is > a whole different ballgame, but one we maybe ought to think of also! Yes, I was thinking strings. That seems safe and probably useful. Programming languages without Unicode strings built-in suffer as a result. -- Mike Treseler From newsfish@newsfish Tue Aug 9 07:53:52 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Monitoring inout signal transactions Date: Sat, 30 Jul 2011 13:03:14 +0300 Organization: A noiseless patient Spider Lines: 37 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 30 Jul 2011 10:03:28 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="26843"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/jNOhoRvdpGVarG3XhF2fIjCKOSJSWzT8=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 Cancel-Lock: sha1:iEGjCoEd3ZHPuuImo9yzMsYH8pY= Xref: feeder.eternal-september.org comp.lang.vhdl:5211 entity SPY is port (A : inout Std_Logic); end SPY; architecture ARCH of SPY is begin process begin report time'image(now) & ": a = " & std_logic'image(a); wait on a'transaction; end process; end architecture; architecture TB is signal A: std_logic; begin SPY_I: entity SPY(a) process begin wait for 1 fs; a <= 'Z'; wait for 1 ps; a <= '1'; wait for 5 ns; a <= '0'; wait for 20 ns; end process I do not drive the signal from the Spy, so output must be (U, Z, 1, 0). Right? Yet, simulator tells 'a = U' all four times! I observed this hacking the Zero-Ohm model. Ben Cohen temporarly assigns a and b to Z there. I do not understand why but that is a solution to get the normal output (U,Z,1,0). Another is to change port type inout -> in. Is is supposed VHDL behaviour? IMO, it is strange furthermore because I consider normal, architecture-declared signals, as inout because you can read and write them but no problem happens when the monitoring process is located within the same architecture that drives the signal rather than in a separate entity. From newsfish@newsfish Tue Aug 9 07:53:52 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!newsreader4.netcologne.de!news.netcologne.de!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!h4g2000vbw.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Sat, 30 Jul 2011 04:07:57 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <87ad8c30-e4c5-4ed9-80b0-e417d079288e@h4g2000vbw.googlegroups.com> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312024078 21639 127.0.0.1 (30 Jul 2011 11:07:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 30 Jul 2011 11:07:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h4g2000vbw.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5212 Hi Hans, I have tried to run the example. But when typing "vmake > Makefile" I get the error message: # The vmake utility must be run from a Unix shell or a Windows/DOS prompt. I am using Modelsim PE 10.0b Cheers, Hssig From newsfish@newsfish Tue Aug 9 07:53:52 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Sat, 30 Jul 2011 14:42:35 +0100 Organization: A noiseless patient Spider Lines: 23 Message-ID: <992837p9u8qvgpi5ms8vm06lfn65c7df5a@4ax.com> References: <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> <87ad8c30-e4c5-4ed9-80b0-e417d079288e@h4g2000vbw.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="32458"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/NEtrPeWSw+czlc6l7NZCfOWeZ6yF4wFQ=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:g5mr78W5hXjoJCvy9SH6ZoIFl+Q= Xref: feeder.eternal-september.org comp.lang.vhdl:5213 On Sat, 30 Jul 2011 04:07:57 -0700 (PDT), hssig wrote: >I have tried to run the example. But when typing "vmake > Makefile" I >get the error message: ># The vmake utility must be run from a Unix shell or a Windows/DOS >prompt. Well, it's hard to see how the error message could be any clearer :-) Obviously you're running from within ModelSim's GUI, or Tcl console. Fortunately Tcl comes to your rescue here: exec vmake > Makefile should do what you want. Of course, you *could* perhaps RTFM and run vmake directly from the command prompt... PS: exec is Tcl's command to run an external program. It does a pretty good job of faking-up the environment to fool the program into thinking it has been run from the DOS prompt. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:52 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sat, 30 Jul 2011 14:59:57 +0100 Organization: A noiseless patient Spider Lines: 43 Message-ID: <0i383714a24kf80143p3tcph945sdfqgef@4ax.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6137"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Hw6EITjG1JWFqBk9RhgkZTpq9pSEMYBA=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:RxpNQWtyP0GvwnSAuJuTSKQcZw4= Xref: feeder.eternal-september.org comp.lang.vhdl:5214 On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer wrote: >I often use records within records, or records within records within >records, ad nausea. It's nice that I can currently do the following: > >A.A.A <= X; >A.A.B <= Y; >A.A.C <= Z; > >However, there's a lot of repetition in my code, so I often prefer the >following: > >A <= ( A => ( A => X, > B => Y, > C => Z ) ); > >The benefit is more noticeable with long and descriptive names for the >elements, but the problem is that if my intention is to set only the >A, B, and C leaf elements and leave any others unchanged it doesn't >seem possible. How about an alias? alias AA: ABC_record_type is A.A; ... AA.A <= X; Doesn't quite do what you asked for (I don't think that's possible) but it does simplify the naming problem somewhat. Functions and procedures might be useful too: procedure tweakJustTheLeafParts(signal T: inout ABC_record_type) is begin T.A <= X; ... end; ... tweakJustTheLeafParts(A.A); -- does A.A.A <= X; Watch out for multiple drivers, though, as Rob Gaddi points out. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:53 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sat, 30 Jul 2011 15:01:13 +0100 Organization: A noiseless patient Spider Lines: 46 Message-ID: References: <0i383714a24kf80143p3tcph945sdfqgef@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6137"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+vB4ZMw9nHfDcC82jGk9Ze8/kj5vcEoAI=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:1BfQQJYrD0aB9g5oKS4FiThS5LY= Xref: feeder.eternal-september.org comp.lang.vhdl:5215 On Sat, 30 Jul 2011 14:59:57 +0100, Jonathan Bromley .... sent a long-dead post by mistake. Sorry, please ignore. >On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer > wrote: > >>I often use records within records, or records within records within >>records, ad nausea. It's nice that I can currently do the following: >> >>A.A.A <= X; >>A.A.B <= Y; >>A.A.C <= Z; >> >>However, there's a lot of repetition in my code, so I often prefer the >>following: >> >>A <= ( A => ( A => X, >> B => Y, >> C => Z ) ); >> >>The benefit is more noticeable with long and descriptive names for the >>elements, but the problem is that if my intention is to set only the >>A, B, and C leaf elements and leave any others unchanged it doesn't >>seem possible. > >How about an alias? > > alias AA: ABC_record_type is A.A; > ... > AA.A <= X; > >Doesn't quite do what you asked for (I don't think that's >possible) but it does simplify the naming problem somewhat. > >Functions and procedures might be useful too: > procedure tweakJustTheLeafParts(signal T: inout ABC_record_type) is > begin > T.A <= X; > ... > end; > ... > tweakJustTheLeafParts(A.A); -- does A.A.A <= X; > >Watch out for multiple drivers, though, as Rob Gaddi points out. From newsfish@newsfish Tue Aug 9 07:53:53 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Sat, 30 Jul 2011 15:04:40 +0100 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6137"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/81G+NraD2NXqwdQ8Xqs3nyWaILUSN3vI=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:DBz2FJ0D7ZTqJCCWZViSd8Jm4X0= Xref: feeder.eternal-september.org comp.lang.vhdl:5216 On 28 Jul 2011 19:13:48 GMT, Martin Thompson wrote: >Hi all, > >I'm asking for a bit of input from the community... > >As the title says, would you find it of use to allow Unicode identifiers >and comments in a future VHDL revision? I'm not sure I see any use for it. What do you have in mind? Unicode *strings* and file-IO might well be useful, but I guess that's a very different story. A new type, either built-in or in std.standard, for Unicode *characters* would be a good start. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:53 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news-2.dfn.de!news.dfn.de!news.uni-stuttgart.de!news.belwue.de!rz.uni-karlsruhe.de!inka.de!chekov.starfleet.inka.de!.POSTED!not-for-mail From: Newsgroups: comp.lang.vhdl Subject: Re: Monitoring inout signal transactions Date: Sat, 30 Jul 2011 15:49:05 +0000 (UTC) Organization: void Lines: 45 Message-ID: References: NNTP-Posting-Host: chekov.starfleet.local X-Trace: chekov.starfleet.local 1312040945 585 192.168.128.1 (30 Jul 2011 15:49:05 GMT) X-Complaints-To: usenet@starfleet.inka.de NNTP-Posting-Date: Sat, 30 Jul 2011 15:49:05 +0000 (UTC) User-Agent: tin/1.9.6-20101126 ("Burnside") (UNIX) (Linux/2.6.38-8-generic (x86_64)) Xref: feeder.eternal-september.org comp.lang.vhdl:5217 valtih1978 wrote: > entity SPY is > port (A : inout Std_Logic); > end SPY; > > architecture ARCH of SPY is > begin > > process begin > report time'image(now) & ": a = " & std_logic'image(a); > wait on a'transaction; > end process; > > end architecture; > > > architecture TB is > signal A: std_logic; > begin > SPY_I: entity SPY(a) > process begin > wait for 1 fs; > a <= 'Z'; wait for 1 ps; > a <= '1'; wait for 5 ns; > a <= '0'; wait for 20 ns; > end process > > I do not drive the signal from the Spy, so output must be (U, Z, 1, 0). > Right? Yet, simulator tells 'a = U' all four times! Signal A in the Testbench TB has multiple sources[1]: spy's inout port and the driver from the process in the testbench. The inout source from spy is initialized with 'U' by default. That 'U' overdrives the other assignments like usual. If you initialize the inout port using 'Z', spy will report the values assigned by the testbench process. ... port (A: inout std_logic := 'Z'); ... [1]: LRM(93) 4.3.1.2 line 183 Enrik From newsfish@newsfish Tue Aug 9 07:53:53 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Mon, 01 Aug 2011 09:58:21 +0100 Organization: TRW Conekt Lines: 42 Message-ID: References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net t34vnpKcwg6m/3STJrI7qgWd+Q49rpKMjc28OFtsGrul7V8bg= Cancel-Lock: sha1:bh3chlQM3sT03WRzapj/IB5uPio= sha1:q9tAzFkwLk8hdVzrh8t/S2fi+CQ= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5218 Jonathan Bromley writes: > On 28 Jul 2011 19:13:48 GMT, Martin Thompson > wrote: > >>Hi all, >> >>I'm asking for a bit of input from the community... >> >>As the title says, would you find it of use to allow Unicode identifiers >>and comments in a future VHDL revision? > > I'm not sure I see any use for it. What do you have in mind? > The original question was asked without much in mind beyond allowing you to call a variable 'château' (to pull an example from the other end of the scale spectrum to our usual fare here :) > Unicode *strings* and file-IO might well be useful, but > I guess that's a very different story. A new type, either > built-in or in std.standard, for Unicode *characters* would > be a good start. >From other comments, Unicode strings appear to be of much more value than Unicode identifiers and comments. Although once you allow Unicode strings in a source file, you've opened the "source-file encoding" can of worms already, and then (I believe) allowing Unicode in comments becomes easy. Unicode identifiers may have some negative impact of parsing efficiency? In which case, as you say, W_CHARACTER here we (might) come. However, it also sounds like a large (huge?) amount of work which *may* be better spent elsewhere. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Aug 9 07:53:53 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Mon, 01 Aug 2011 11:03:01 +0100 Organization: A noiseless patient Spider Lines: 15 Message-ID: <06uc379imelvn6oc6dp66avibm5ki8eukk@4ax.com> References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="13803"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19s6+12bWhn7/8HLXlLVAL+F9Svawf0Gd0=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:c0i+0AKilkQGDeEAsrn0iRjfHZA= Xref: feeder.eternal-september.org comp.lang.vhdl:5219 On Mon, 01 Aug 2011 09:58:21 +0100, Martin Thompson wrote: >The original question was asked without much in mind beyond >allowing you to call a variable 'château' C'est tout possible de faire son logiciel sans aucun accent :-) >it also sounds like a large (huge?) amount of work which >*may* be better spent elsewhere. I think I tend to agree. The EDA industry as a whole is irremediably Anglophone, and muddles through pretty well without internationalization. -- Jonathan Bromley From newsfish@newsfish Tue Aug 9 07:53:53 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Tue, 02 Aug 2011 11:50:01 +0100 Organization: TRW Conekt Lines: 19 Message-ID: References: <99dqncFsnU1@mid.individual.net> <06uc379imelvn6oc6dp66avibm5ki8eukk@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net utlvgH2YKRwQx4p/iryemghQaFxkWbMVEUcwps+psB/5rCegU= Cancel-Lock: sha1:H2Ckq/1eXI/O/bgSQcVH66a6q4M= sha1:RNxQol+6A6G85q69Z93aBEMaROM= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5220 Jonathan Bromley writes: > The EDA industry as a whole is > irremediably Anglophone, I like that description :) > and muddles through pretty well > without internationalization. and likely will continue to do so! Thanks, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Aug 9 07:53:54 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Tue, 02 Aug 2011 14:38:49 +0300 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 2 Aug 2011 11:38:50 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="21297"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18kIW/iKKvNWlvQ/FsZoh4Xak7AqeArRrM=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 In-Reply-To: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> Cancel-Lock: sha1:YAyjYeOhwQVuidsVmHdRDiQ1lr8= Xref: feeder.eternal-september.org comp.lang.vhdl:5221 This is fine. But have you seen how it works? Given process begin c <= '1'; wait for 3 ns; c <= '0'; wait for 3 ns; c <= '1'; wait for 3 ns; end process; a <= c; I: entity ZeroOhm port map(a, b); it produces https://lh4.googleusercontent.com/-grNH7UAwVBw/Tjfe1819oII/AAAAAAAAADs/3jX6VMhFojA/s800/0ohm.png The problem is those transitions of the order of the delays. That is, listeners will not see your signal if the clock period is the same order as the line delay. Though, the bus driver may produce a perfect signal. From newsfish@newsfish Tue Aug 9 07:53:54 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?Q?Nicholas_Collin_Paul_de_Glouce=C5=BFter?= Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Fri, 5 Aug 2011 18:20:35 +0000 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: MULTIPART/MIXED; BOUNDARY="8323328-894931490-1312568451=:3551" Injection-Info: mx04.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="549"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jPPPYLtUxjbe0YlO/Qnb8nBRf7rZBQVpoluxFFtUEvA==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <99dqncFsnU1@mid.individual.net> Cancel-Lock: sha1:BGXnoH1IPuXLF2oOT0lz+iKF7mQ= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:5222 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-894931490-1312568451=:3551 Content-Type: TEXT/PLAIN; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Martin Thompson sent on July 28th, 2011: |-------------------------------------------------------------------------| |"Hi all, | | | |I'm asking for a bit of input from the community... | | | |As the title says, would you find it of use to allow Unicode identifiers | |and comments in a future VHDL revision? | | | |Would this be: | |a) Something VHDL should not allow | |b) Something that doesn't bother you either way | |c) Something you'd find useful sometimes | |d) Something you'd make use of all the time | |e) Something that you'd switch away from SystemVerilog just to get at | | (maybe I'm asking the wrong crowd for that :) | | | |Thanks, | |Martin | | | |-- | |http://parallelpoints.com/ " | |-------------------------------------------------------------------------| Hi Mr. Thompson, I respond more to point out that Unicode support in actual source code (such as identifiers) was added to Ada and one of the compiler developers which added this support remarked that it was not worth the hassle. Anyhow, as for my own voting: c) or maybe even d). Back to the issue of hassle in the real World though, there is a valid argument for a) because many tools such as text editors and terminals are still screwing up Unicode (such as UTF-8 versus UTF-7) years after it was introduced. Almost nothing around screws up ASCII (aside from CR and LF issues). Regards, Nicholas Collin Paul de Glouce=C5=BFter in Unicode (you asked for it) --8323328-894931490-1312568451=:3551-- From newsfish@newsfish Tue Aug 9 07:53:54 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!p5g2000vbl.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Fri, 5 Aug 2011 10:52:38 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: References: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> <05079553-9b34-40cb-a879-d4918cc70b6f@o4g2000vbv.googlegroups.com> <9973q0Fvb9U1@mid.individual.net> NNTP-Posting-Host: 212.129.66.131 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312566758 1429 127.0.0.1 (5 Aug 2011 17:52:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Aug 2011 17:52:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p5g2000vbl.googlegroups.com; posting-host=212.129.66.131; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5223 Al, thankyou for the suggestions. Please excuse the delay in replying. I've been on vacation. I will try the emacs solution. Also, since I plan to replicate the original design and modify the copy as described, the global signal suggestion may be be useful. regards, Fearghal From newsfish@newsfish Tue Aug 9 07:53:54 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!f20g2000yqm.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: help with binary decoder Date: Sat, 6 Aug 2011 10:33:43 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <059c7662-2449-4f35-b944-53555ef39aa7@f20g2000yqm.googlegroups.com> NNTP-Posting-Host: 90.148.52.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312652122 28027 127.0.0.1 (6 Aug 2011 17:35:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 6 Aug 2011 17:35:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000yqm.googlegroups.com; posting-host=90.148.52.225; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5224 hi all; i have this code for a 5-bits binary counter : LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY counter IS PORT ( count : OUT unsigned (4 DOWNTO 0); load : IN STD_LOGIC; pre :IN unsigned (4 DOWNTO 0); Clk : IN STD_LOGIC); END counter; ARCHITECTURE Behavioral OF counter IS SIGNAL c : unsigned(4 DOWNTO 0) := "00000"; BEGIN count <= c; PROCESS(Clk) BEGIN IF( rising_edge(Clk) ) THEN IF(load = '1') THEN c <= pre; ELSE c <= c + 1; END IF; END IF; END PROCESS; END Behavioral; I want to connect the output to a binary decoder that shows the state of the counter how can i do that? can any one help me plz From newsfish@newsfish Tue Aug 9 07:53:54 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a31g2000vbt.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: help with binary decoder Date: Sat, 6 Aug 2011 10:38:26 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <53dec8e3-9712-499f-948b-c490600de36f@a31g2000vbt.googlegroups.com> NNTP-Posting-Host: 90.148.52.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312652426 30814 127.0.0.1 (6 Aug 2011 17:40:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 6 Aug 2011 17:40:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a31g2000vbt.googlegroups.com; posting-host=90.148.52.225; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5225 hi all; i have this code for a 5-bits binary counter : LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY counter IS PORT ( count : OUT unsigned (4 DOWNTO 0); load : IN STD_LOGIC; pre :IN unsigned (4 DOWNTO 0); Clk : IN STD_LOGIC); END counter; ARCHITECTURE Behavioral OF counter IS SIGNAL c : unsigned(4 DOWNTO 0) := "00000"; BEGIN count <= c; PROCESS(Clk) BEGIN IF( rising_edge(Clk) ) THEN IF(load = '1') THEN c <= pre; ELSE c <= c + 1; END IF; END IF; END PROCESS; END Behavioral; I want to connect the output to a binary decoder that shows the state of the counter how can i do that? can any one help me plz From newsfish@newsfish Tue Aug 9 07:53:54 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!postnews.google.com!p20g2000yqp.googlegroups.com!not-for-mail From: Hendrik Eeckhaut Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Mon, 8 Aug 2011 01:37:57 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: References: NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1312792678 31427 127.0.0.1 (8 Aug 2011 08:37:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Aug 2011 08:37:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p20g2000yqp.googlegroups.com; posting-host=195.144.71.15; posting-account=fhflvgoAAAAsi8MNddt9P71xOtFYaqiV User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.57 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5226 On Jul 21, 12:09=A0am, fearg wrote: > Hi, I=92d be grateful if anyone could advise on whether an application > is available to do the following for VHDL models. > Fearghal > > 1. =A0 =A0 =A0Make a replica copy of a selected multi-file and hierarchic= al VHDL > design > 2. =A0 =A0 =A0Modify each VHDL file in the copied hierarchical VHDL model > (possibly using the make file sequence), in order to bring all (or > selected) signals to the top level VHDL entity. > 3. =A0 =A0 =A0Steps: > a. =A0 =A0 =A0modify each VHDL files in turn to bring every (or selected) > internal signal as an output signals in VHDL entity > b. =A0 =A0 =A0Modify the associated component declarations within package= files > to reflect the modified entity ports > c. =A0 =A0 =A0Rebuild the VHDL hierarchy adding the new output ports to a= ll > entities in the hierarchy > d. =A0 =A0 =A0Modify all port map assignments to mirror the extended enti= ty > ports. > > My application requires interpreting any existing VHDL model, > selecting signals from within the VHDL model to bring to the top level > entity in order to connect to a series of display devices. I do not > wish to modify the underlying VHDL code. Seems like you need a powerful VHDL refactoring tool. Sigasi HDT (http://www.sigasi.com/sigasi-hdt) does not completely automate the transformation you describe, but it will definitely help you avoid errors and will save you a lot of time. With Sigasi you can easily add ports and keep your complete design hierarchy consistent. If you are a student you can get an educational license, otherwise you can download a 4-week trial via http://www.sigasi.com/user/register Regards, Hendrik. From newsfish@newsfish Tue Aug 9 07:53:55 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!195.114.241.69.MISMATCH!feeder.news-service.com!postnews.google.com!en1g2000vbb.googlegroups.com!not-for-mail From: thunder Newsgroups: comp.lang.vhdl Subject: PSL book suggestions Date: Mon, 8 Aug 2011 07:44:47 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <971ab531-ce37-4675-84ef-381662d69fcc@en1g2000vbb.googlegroups.com> NNTP-Posting-Host: 194.200.65.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312814773 26996 127.0.0.1 (8 Aug 2011 14:46:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Aug 2011 14:46:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: en1g2000vbb.googlegroups.com; posting-host=194.200.65.239; posting-account=fYOi-AoAAAAftKwn8h0pIn0WrxqvjnVx User-Agent: G2/1.0 X-HTTP-Via: 1.1 IMGKLISA1 X-Google-Web-Client: true X-Google-Header-Order: VCRUHALSNK X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18 GTB7.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5227 All We are just starting to implement PSL assertions for our VHDL IP code. Just wondered, if any one has any suggestions for relevant PSL books to act as tutorial/reference? I have managed to download a fair amount of documents on PSL assertions from the Web and have written some simple assertions. I am aware of the Ben Cohen book on PSL/Sugar and would be interested on any reviews on this book. Thanks in advance JO From newsfish@newsfish Tue Aug 9 07:53:55 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Colin Paul Gloster Newsgroups: comp.lang.vhdl Subject: Re: PSL book suggestions Date: Mon, 8 Aug 2011 19:15:01 +0000 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <971ab531-ce37-4675-84ef-381662d69fcc@en1g2000vbb.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx04.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="30323"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/L5MJBuXagTwhBFu327S/wq+A23DG5TN8AEHpChke9QA==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <971ab531-ce37-4675-84ef-381662d69fcc@en1g2000vbb.googlegroups.com> Cancel-Lock: sha1:74dq5qaoyX9SpJUYPkh/FLCeaew= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:5228 JO sent on August 8th, 2011: |-----------------------------------------------------------------------| |"We are just starting to implement PSL assertions for our VHDL IP code.| | | |Just wondered, if any one has any suggestions for relevant PSL books | |to act as tutorial/reference? I have managed to download a fair amount | |of documents on PSL assertions from the Web and have written some | |simple assertions. | | | |I am aware of the Ben Cohen book on PSL/Sugar and would be interested | |on any reviews on this book." | |-----------------------------------------------------------------------| I have not read that particular book but I have read other things by Ben Cohen. He is a very good author. From newsfish@newsfish Tue Aug 9 07:53:55 2011 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!n35g2000yqf.googlegroups.com!not-for-mail From: thunder Newsgroups: comp.lang.vhdl Subject: PSL assertion book suggestion Date: Mon, 8 Aug 2011 13:25:45 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <84fe67b1-9bf0-43bc-8a83-f0a524f6b083@n35g2000yqf.googlegroups.com> NNTP-Posting-Host: 86.163.47.141 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312835269 8562 127.0.0.1 (8 Aug 2011 20:27:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Aug 2011 20:27:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n35g2000yqf.googlegroups.com; posting-host=86.163.47.141; posting-account=fYOi-AoAAAAftKwn8h0pIn0WrxqvjnVx User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5229 Hi All We have started using PSL assertins for our VHDL IP. I have downloadded some material from Google search and have written a small number of assertions. I wondered if any one has any suggestions for books to act as a more advanced tutorial/reference om PSL assertions. The google search pointef me to Ben Cohens' book on PSL/Sugar. I wonder if any one has used this book and if so have any comments on it. Thanks in advance JO