From newsfish@newsfish Thu Aug 1 00:29:15 2024 X-Received: by 10.67.30.197 with SMTP id kg5mr12541241pad.36.1396346670299; Tue, 01 Apr 2014 03:04:30 -0700 (PDT) X-Received: by 10.182.200.163 with SMTP id jt3mr560529obc.25.1396346670170; Tue, 01 Apr 2014 03:04:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!ur14no372050igb.0!news-out.google.com!xg2ni0igc.0!nntp.google.com!l13no1138302iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 1 Apr 2014 03:04:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.176.197.14; posting-account=JQXykgoAAAB5c7UjCcMIJQGNoGxD60UO NNTP-Posting-Host: 88.176.197.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> Subject: How dofor using generate or loop for this process ? From: Olivier Dir Injection-Date: Tue, 01 Apr 2014 10:04:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2944 Hi all, for this code I would like write this code with loop or generate. I don't know if it's possible. pSelFifo : process(Clk, SRst) begin if SRst = '1' then SelFifo <= (others=>'0'); elsif Clk'event and Clk='1' then if DataAvlble(1) = '1' then SelFifo <= "000001" elsif DataAvlble(2) = '1' then SelFifo <= "000010" elsif DataAvlble(3) = '1' then SelFifo <= "000100" elsif DataAvlble(4) = '1' then SelFifo <= "001000" elsif DataAvlble(5) = '1' then SelFifo <= "010000" elsif DataAvlble(6) = '1' then SelFifo <= "100000" else SelFifo <= (others=>'0'); end if; end if; end process; thank for your help. Olive From newsfish@newsfish Thu Aug 1 00:29:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx22.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: How dofor using generate or loop for this process ? Newsgroups: comp.lang.vhdl References: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 38 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1396351502 62.49.20.82 (Tue, 01 Apr 2014 11:25:02 UTC) NNTP-Posting-Date: Tue, 01 Apr 2014 11:25:02 UTC Date: Tue, 01 Apr 2014 11:25:02 GMT X-Received-Body-CRC: 1930554143 X-Received-Bytes: 1759 Xref: news.eternal-september.org comp.lang.vhdl:2945 On Tue, 01 Apr 2014 03:04:29 -0700, Olivier Dir wrote: > Hi all, > for this code I would like write this code with loop or generate. > I don't know if it's possible. > > > > pSelFifo : process(Clk, SRst) > begin > if SRst = '1' then > SelFifo <= (others=>'0'); > elsif Clk'event and Clk='1' then > if DataAvlble(1) = '1' then > SelFifo <= "000001" > elsif DataAvlble(2) = '1' then > SelFifo <= "000010" ... > thank for your help. > > Olive pSelFifo : process(Clk, SRst) begin if SRst = '1' then SelFifo <= (others=>'0'); elsif rising_edge(Clk) then SelFifo <= (others=>'0'); for i in DataAvlble'low to DataAvlble'high loop if DataAvlble(i) = '1' then SelFifo(i) <= '1'; exit; -- prevent multiple bit set, as in original end if; end loop; end if; end process; From newsfish@newsfish Thu Aug 1 00:29:16 2024 X-Received: by 10.50.62.106 with SMTP id x10mr3334710igr.2.1396420883189; Tue, 01 Apr 2014 23:41:23 -0700 (PDT) X-Received: by 10.182.60.228 with SMTP id k4mr3117obr.35.1396420882892; Tue, 01 Apr 2014 23:41:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no1640801iga.0!news-out.google.com!gi6ni106igc.0!nntp.google.com!l13no1640796iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 1 Apr 2014 23:41:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.176.197.14; posting-account=JQXykgoAAAB5c7UjCcMIJQGNoGxD60UO NNTP-Posting-Host: 88.176.197.14 References: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <324f8c12-b7ff-41d9-adf2-c2d4f49182c5@googlegroups.com> Subject: Re: How dofor using generate or loop for this process ? From: Olivier Dir Injection-Date: Wed, 02 Apr 2014 06:41:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:2946 Le mardi 1 avril 2014 13:25:02 UTC+2, Brian Drummond a =E9crit=A0: > On Tue, 01 Apr 2014 03:04:29 -0700, Olivier Dir wrote: >=20 >=20 >=20 > > Hi all, >=20 > > for this code I would like write this code with loop or generate. >=20 > > I don't know if it's possible. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > pSelFifo : process(Clk, SRst) >=20 > > begin >=20 > > if SRst =3D '1' then >=20 > > SelFifo <=3D (others=3D>'0'); >=20 > > elsif Clk'event and Clk=3D'1' then >=20 > > if DataAvlble(1) =3D '1' then >=20 > > SelFifo <=3D "000001" >=20 > > elsif DataAvlble(2) =3D '1' then >=20 > > SelFifo <=3D "000010" >=20 > ... >=20 >=20 >=20 > > thank for your help. >=20 > >=20 >=20 > > Olive >=20 >=20 >=20 > pSelFifo : process(Clk, SRst) >=20 > begin >=20 > if SRst =3D '1' then >=20 > SelFifo <=3D (others=3D>'0'); >=20 > elsif rising_edge(Clk) then >=20 > SelFifo <=3D (others=3D>'0'); >=20 > for i in DataAvlble'low to DataAvlble'high loop >=20 > if DataAvlble(i) =3D '1' then >=20 > SelFifo(i) <=3D '1'; >=20 > exit; -- prevent multiple bit set, as in original >=20 > end if; >=20 > end loop; >=20 > end if; >=20 > end process; Thank you. From newsfish@newsfish Thu Aug 1 00:29:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Wed, 02 Apr 2014 11:57:12 -0400 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 2 Apr 2014 15:56:45 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="3139"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18H9jiZGLynspNz6l0NXb5M" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:vL3Mqwhy5ynoR7xFNJo2qit4+V8= Xref: news.eternal-september.org comp.lang.vhdl:2947 On 3/17/2014 11:44 AM, alb wrote: > Dear all, > > I have a microcontroller with an FPU which is delivered as an IP (I mean > the FPU). In order to run at a decent frequency, some of the operations > are allowed to complete in within a certain amount of cycles, but the > main problem is that we do not know how many. > > That said, if we run the synthesis tool without timing constraints on > those paths, we have a design that is much slower than can be. > Multicycle constraints are out of question because they are hard to > verify and maintain, so we decided to set false paths and perform > post-layout sims to extract those values to be used in the RTL in a > second iteration. > > There are several reasons why I do not particularly like this approach: > > 1. it relies on post-layout sims which are resource consuming > 2. if we change technology we will likely need to do the whole process > again > 3. we are obliged to perform incremental place&route since an optimized > implementation (maybe done automatically) may have an impact on our > delays. > > So far we have not come out with an alternative solution that is not > going to imply redesign (like pipelining, c-slowing, retiming, ...). > > Any ideas/suggestions? > > Al If I understand you correctly, you have a piece of combinatorial logic and you need to know how fast it will run in your design. This will then let your surrounding circuitry wait some number of clock cycles to read the result, that give you a longer delay than the delay though the logic. I think your starting premise that multi-cycle constraints are "out of the question" is where you have erred. Multi-cycle constraints are exactly what are required and if you don't understand how to use them you are not likely to get a good result. Post P&R simulation is not a good way to validate timing because it is so hard to cover every path through the logic. Static timing analysis is the right way to do this and you need to learn to use it properly. -- Rick From newsfish@newsfish Thu Aug 1 00:29:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 3 Apr 2014 07:05:40 GMT Lines: 62 Message-ID: References: X-Trace: individual.net 0a/rtJ5zboBDtPERxzWHKAadCLF2Pm1ZJn9uzP0+rJNZyW6fcJ X-Orig-Path: not-for-mail Cancel-Lock: sha1:gjM3aZbTDua2sLSUUZ93939sDzM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2948 Hi Rick, rickman wrote: [] >> I have a microcontroller with an FPU which is delivered as an IP (I mean >> the FPU). In order to run at a decent frequency, some of the operations >> are allowed to complete in within a certain amount of cycles, but the >> main problem is that we do not know how many. >> >> That said, if we run the synthesis tool without timing constraints on >> those paths, we have a design that is much slower than can be. >> Multicycle constraints are out of question because they are hard to >> verify and maintain, so we decided to set false paths and perform >> post-layout sims to extract those values to be used in the RTL in a >> second iteration. [] > > If I understand you correctly, you have a piece of combinatorial logic > and you need to know how fast it will run in your design. This will > then let your surrounding circuitry wait some number of clock cycles to > read the result, that give you a longer delay than the delay though the > logic. Precisely. > I think your starting premise that multi-cycle constraints are "out of > the question" is where you have erred. Multi-cycle constraints are > exactly what are required and if you don't understand how to use them > you are not likely to get a good result. There are two aspects here to consider: 1. multicycle constraints need not only a /from/ and /to/ parameter, they also need a /through/ parameter. When you have a logic depth of 111 gates you start to understand why a multicycle constraint cannot be a sustainable solution. 2. My experience in setting up multicycle constraints is nearly zero and starting off with such an approach on this type of project would be begging for troubles. > Post P&R simulation is not a good way to validate timing because it is > so hard to cover every path through the logic. Static timing analysis > is the right way to do this and you need to learn to use it properly. I've read several times on this group the skepticism behind static timing analysis when multicycle constraints are in place. I have to search back in the archives to really understand the technical motivations, but the bottom line is: a. is difficult to maintain them; if the logic path has been optimized the constraint does not work anymore b. is difficult to verify them; if the path *is not* multicycle you may wrongly relax the timing too much and never realize until another optimization takes place and your circuit does not work any more. If anyone sees a flaw in my points above I'd be glad to be corrected. Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Thu Aug 1 00:29:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer02.fr7!news.highwinds-media.com!post02.fr7!fx11.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140402-5, 02/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 45 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396514969 86.29.12.221 (Thu, 03 Apr 2014 08:49:29 UTC) NNTP-Posting-Date: Thu, 03 Apr 2014 08:49:29 UTC Organization: virginmedia.com Date: Thu, 03 Apr 2014 09:49:27 +0100 X-Received-Body-CRC: 1106746054 X-Received-Bytes: 2616 Xref: news.eternal-september.org comp.lang.vhdl:2949 On 03/04/2014 08:05, alb wrote: Hi Al, .. > I've read several times on this group the skepticism behind static timing analysis > when multicycle constraints are in place. I have to search back in the archives to > really understand the technical motivations, but the bottom line is: > > a. is difficult to maintain them; if the logic path has been optimized the > constraint does not work anymore I think you are confusing propagation (or false path) delay with multicycle path delay. A multicycle delay is a synchronous "number of clock cycle" based delay, it does not depend on the clock frequency. You use this delay if you know your circuit takes n clock cycles to propagate the result to the destination register. > b. is difficult to verify them; You can easily verify them using assertions, see end of the pdf below: https://www.synopsys.com/Community/Interoperability/Documents/devforum_pres/2005april/17_SystemVerilog_FishTail.pdf As I mentioned in another thread, learn PSL, it is a real eye opener for verification. if the path *is not* multicycle you may wrongly > relax the timing too much and never realize until another optimization takes place > and your circuit does not work any more. Not exactly, you will simply not get timing closure and your will probably end up using more resources then necessary. Regards, Hans. www ht-lab.com > > If anyone sees a flaw in my points above I'd be glad to be corrected. > > Al > From newsfish@newsfish Thu Aug 1 00:29:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 3 Apr 2014 10:48:15 GMT Lines: 68 Message-ID: References: X-Trace: individual.net KeC53Blmp0Mbt2Xfp4f2+AuM0ofFpqbLhIYiQb6ls68OPo8KW8 X-Orig-Path: not-for-mail Cancel-Lock: sha1:z2o/EZc6APH7mOB42jwxOmA7zq0= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2950 Hi Hans, HT-Lab wrote: [removed text and added reference in square brackets] >> a. is difficult to maintain them [multicycle constraints]; if the >> logic path has been optimized the constraint does not work anymore > > I think you are confusing propagation (or false path) delay with > multicycle path delay. A multicycle delay is a synchronous "number of > clock cycle" based delay, it does not depend on the clock frequency. IMHO a multicycle path delay is a propagation delay specified as relative to the clock period. Hence it *does* depend on the clock frequency, while the propagation through your gates does not (it depends on the technology). If your path takes 12.3 ns you would have to set a multicycle constraint of 2 with a 100MHz clock, but 3 with a 200MHz one. A false path is a different story. You want to inform your synthesis tool that a certain path is never going to be used so do not bother optimizing it. > You > use this delay if you know your circuit takes n clock cycles to > propagate the result to the destination register. If I know when I will be reading the result on the destination register I may relax the time it will take to propagate the result, but on the contrary if I want to know when is the earliest moment to go and get the result, the multicycle path is of no use. >> b. is difficult to verify them; > > You can easily verify them using assertions, see end of the pdf below: > > https://www.synopsys.com/Community/Interoperability/Documents/devforum_pres/2005april/17_SystemVerilog_FishTail.pdf > > As I mentioned in another thread, learn PSL, it is a real eye opener for > verification. It's in the pipe...a very long one unfortunately ;-) But thanks for the pointer. Can you verify if a certain path is not violating the setup time of your register? Can you verify what is the delay it takes to go from register A to register B through some logic? > > if the path *is not* multicycle you may wrongly >> relax the timing too much and never realize until another optimization takes place >> and your circuit does not work any more. > > Not exactly, you will simply not get timing closure and your will > probably end up using more resources then necessary. Assume a single cycle path that you set to be multicycle because of mistake in your analysis. The synthesis tool will not know if your multicycle path is correct or wrong, therefore it will relax the timing between the selected end points and you will sample the result at the wrong time. The STA will correctly report the path is indeed fulfilling the constraint, but the logic will take the result too early. If you decided not to roll your postlayout sim because you relied on your STA, then you are set to find nasty surprises on the bench. Al From newsfish@newsfish Thu Aug 1 00:29:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!news.astraweb.com!border6.a.newsrouter.astraweb.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx24.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140403-0, 03/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 50 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396528421 86.29.12.221 (Thu, 03 Apr 2014 12:33:41 UTC) NNTP-Posting-Date: Thu, 03 Apr 2014 12:33:41 UTC Organization: virginmedia.com Date: Thu, 03 Apr 2014 13:33:39 +0100 X-Received-Body-CRC: 4197442378 X-Received-Bytes: 2754 Xref: news.eternal-september.org comp.lang.vhdl:2951 Hi Al, On 03/04/2014 11:48, alb wrote: > Hi Hans, > > HT-Lab wrote: > [removed text and added reference in square brackets] >>> a. is difficult to maintain them [multicycle constraints]; if the >>> logic path has been optimized the constraint does not work anymore >> >> I think you are confusing propagation (or false path) delay with >> multicycle path delay. A multicycle delay is a synchronous "number of >> clock cycle" based delay, it does not depend on the clock frequency. > > IMHO a multicycle path delay is a propagation delay specified as > relative to the clock period. Hence it *does* depend on the clock > frequency, while the propagation through your gates does not (it depends > on the technology). You still have your terminology wrong, here is a SDC example of an typical MCP constraint: set_multicycle_path 2 -from reg_alu* -to reg_mult* Notice there is no time, just a natural number of clock cycles. > > If your path takes 12.3 ns you would have to set a multicycle constraint > of 2 with a 100MHz clock, but 3 with a 200MHz one. You are mixing your constraints. If your combinational path takes 12.3 ns you set a clock constraint of 81MHz. If you have a MCP in your design you are most likely controlling the output register with an enable pin. You do not use a MCP to constraint a propagation delay. .. > > Can you verify if a certain path is not violating the setup time of your > register? Can you verify what is the delay it takes to go from > register A to register B through some logic? Not with assertions, Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:29:18 2024 X-Received: by 10.204.71.78 with SMTP id g14mr875956bkj.3.1396531855864; Thu, 03 Apr 2014 06:30:55 -0700 (PDT) X-Received: by 10.50.61.144 with SMTP id p16mr442164igr.16.1396531855391; Thu, 03 Apr 2014 06:30:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!z11no3080511lbi.1!news-out.google.com!vq6ni1257lbb.1!nntp.google.com!ur14no1814658igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Apr 2014 06:30:52 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> Subject: Re: [cross-post]path verification From: KJ Injection-Date: Thu, 03 Apr 2014 13:30:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2952 On Thursday, April 3, 2014 8:33:39 AM UTC-4, HT-Lab wrote: > > IMHO a multicycle path delay is a propagation delay specified as > > relative to the clock period. Hence it *does* depend on the clock > > frequency, while the propagation through your gates does not (it depends > > on the technology). > > You still have your terminology wrong, here is a SDC example of an > typical MCP constraint: > > set_multicycle_path 2 -from reg_alu* -to reg_mult* > > Notice there is no time, just a natural number of clock cycles. The value of '2' though is computed based on the clock period. Alb already pointed that out earlier in the thread "If your path takes 12.3 ns you would have to set a multicycle constraint of 2 with a 100MHz clock, but 3 with a 200MHz one." Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 3 Apr 2014 13:48:52 GMT Lines: 57 Message-ID: References: X-Trace: individual.net RZAfnu56yKov/Ga/LwuVpwnok30/TWqjN5dgSTQtvusgJHgL/g X-Orig-Path: not-for-mail Cancel-Lock: sha1:b4dtBtDCpYtTCKSqabUa6BBuxfU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2953 Hi Hans, HT-Lab wrote: [] >> IMHO a multicycle path delay is a propagation delay specified as >> relative to the clock period. Hence it *does* depend on the clock >> frequency, while the propagation through your gates does not (it depends >> on the technology). > > You still have your terminology wrong, here is a SDC example of an > typical MCP constraint: > > set_multicycle_path 2 -from reg_alu* -to reg_mult* > I apologize but I did not understand from this example what is wrong in my terminology. > Notice there is no time, just a natural number of clock cycles. > reading out loud your MCP constraint: 'the propagation delay from reg_alu* to reg_mult* has to be smaller than 2 clock cycles (minus setup time)' Notion of time is automatically inferred by your tool since it knows what is the clock period for those particular registers. If the two registers are in two different clock domains I doubt you can really set a multicycle path constraint (at least it does not make sense to me). >> If your path takes 12.3 ns you would have to set a multicycle constraint >> of 2 with a 100MHz clock, but 3 with a 200MHz one. > > You are mixing your constraints. If your combinational path takes 12.3 > ns you set a clock constraint of 81MHz. If you have a MCP in your design > you are most likely controlling the output register with an enable pin. I have to find out how much time I need to wait before sampling the logic with my output enable. There are several (in the 100s) paths between input and output (it's an fpu), therefore I can die under a pile of multicycle path constraints. > You do not use a MCP to constraint a propagation delay. IMHO yes you do. You are telling the synthesis tool that a particular path (or branch of a graph) can have a propagation delay: Tp < N * clock_period - Tsetup rather than the usual: Tp < clock_period - Tsetup Why would you think the MCP does not constraint the propagation delay? Al From newsfish@newsfish Thu Aug 1 00:29:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx05.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> In-Reply-To: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140403-0, 03/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 27 Message-ID: <19e%u.484$%U7.400@fx05.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396534973 86.29.12.221 (Thu, 03 Apr 2014 14:22:53 UTC) NNTP-Posting-Date: Thu, 03 Apr 2014 14:22:53 UTC Organization: virginmedia.com Date: Thu, 03 Apr 2014 15:22:51 +0100 X-Received-Body-CRC: 1980667029 X-Received-Bytes: 2258 Xref: news.eternal-september.org comp.lang.vhdl:2954 On 03/04/2014 14:30, KJ wrote: > On Thursday, April 3, 2014 8:33:39 AM UTC-4, HT-Lab wrote: >>> IMHO a multicycle path delay is a propagation delay specified as >>> relative to the clock period. Hence it *does* depend on the clock >>> frequency, while the propagation through your gates does not (it depends >>> on the technology). >> >> You still have your terminology wrong, here is a SDC example of an >> typical MCP constraint: >> >> set_multicycle_path 2 -from reg_alu* -to reg_mult* >> >> Notice there is no time, just a natural number of clock cycles. > > The value of '2' though is computed based on the clock period. Alb already pointed that out earlier in the thread "If your path takes 12.3 ns you would have to set a multicycle constraint of 2 with a 100MHz clock, but 3 with a 200MHz one." > We are taking about different issues here. My argument is that you should not exchange a clock constraint for an MCP one, Regards, Hans. www.ht-lab.com > Kevin Jennings > From newsfish@newsfish Thu Aug 1 00:29:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx26.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140403-0, 03/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 71 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396535525 86.29.12.221 (Thu, 03 Apr 2014 14:32:05 UTC) NNTP-Posting-Date: Thu, 03 Apr 2014 14:32:05 UTC Organization: virginmedia.com Date: Thu, 03 Apr 2014 15:32:03 +0100 X-Received-Body-CRC: 2509449848 X-Received-Bytes: 3516 Xref: news.eternal-september.org comp.lang.vhdl:2955 On 03/04/2014 14:48, alb wrote: Hi AL, > Hi Hans, > > HT-Lab wrote: > [] >>> IMHO a multicycle path delay is a propagation delay specified as >>> relative to the clock period. Hence it *does* depend on the clock >>> frequency, while the propagation through your gates does not (it depends >>> on the technology). >> >> You still have your terminology wrong, here is a SDC example of an >> typical MCP constraint: >> >> set_multicycle_path 2 -from reg_alu* -to reg_mult* >> > > I apologize but I did not understand from this example what is wrong in > my terminology. > >> Notice there is no time, just a natural number of clock cycles. >> > > reading out loud your MCP constraint: > > 'the propagation delay from reg_alu* to reg_mult* has to be smaller than > 2 clock cycles (minus setup time)' > > Notion of time is automatically inferred by your tool since it knows > what is the clock period for those particular registers. If the two > registers are in two different clock domains I doubt you can really set > a multicycle path constraint (at least it does not make sense to me). > >>> If your path takes 12.3 ns you would have to set a multicycle constraint >>> of 2 with a 100MHz clock, but 3 with a 200MHz one. >> >> You are mixing your constraints. If your combinational path takes 12.3 >> ns you set a clock constraint of 81MHz. If you have a MCP in your design >> you are most likely controlling the output register with an enable pin. > > I have to find out how much time I need to wait before sampling the > logic with my output enable. There are several (in the 100s) paths > between input and output (it's an fpu), therefore I can die under a pile > of multicycle path constraints. > >> You do not use a MCP to constraint a propagation delay. Poor choice of words on my part, I should have said you don't use an MCP constraint as a clock constraint. Regards, Hans. www.ht-lab.com > > IMHO yes you do. You are telling the synthesis tool that a particular > path (or branch of a graph) can have a propagation delay: > > Tp < N * clock_period - Tsetup > > rather than the usual: > > Tp < clock_period - Tsetup > > Why would you think the MCP does not constraint the propagation delay? > > Al > From newsfish@newsfish Thu Aug 1 00:29:19 2024 X-Received: by 10.15.53.136 with SMTP id r8mr2086915eew.5.1396543343899; Thu, 03 Apr 2014 09:42:23 -0700 (PDT) X-Received: by 10.50.9.71 with SMTP id x7mr484565iga.6.1396543340540; Thu, 03 Apr 2014 09:42:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!p9no3261021lbv.0!news-out.google.com!vq6ni1257lbb.1!nntp.google.com!ur14no1891891igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Apr 2014 09:42:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: [cross-post]path verification From: KJ Injection-Date: Thu, 03 Apr 2014 16:42:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2956 On Thursday, April 3, 2014 9:48:52 AM UTC-4, alb wrote: > I have to find out how much time I need to wait before sampling the > logic with my output enable. There are several (in the 100s) paths > between input and output (it's an fpu), therefore I can die under a pile > of multicycle path constraints. You should be able to wild card the path sources inside your block and specify exactly the output enable signal. There should be no need to specify each path source explicitly. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Thu, 03 Apr 2014 18:12:29 -0400 Organization: A noiseless patient Spider Lines: 96 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 3 Apr 2014 22:12:10 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="21453"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+YPgF9JgjAir02We0iCDhw" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:dJ4gV/2r8wlYqyQ57KoHwRVax6Y= Xref: news.eternal-september.org comp.lang.vhdl:2957 On 4/3/2014 3:05 AM, alb wrote:> Hi Rick, > > rickman wrote: > [] >>> I have a microcontroller with an FPU which is delivered as an IP (I mean >>> the FPU). In order to run at a decent frequency, some of the operations >>> are allowed to complete in within a certain amount of cycles, but the >>> main problem is that we do not know how many. >>> >>> That said, if we run the synthesis tool without timing constraints on >>> those paths, we have a design that is much slower than can be. >>> Multicycle constraints are out of question because they are hard to >>> verify and maintain, so we decided to set false paths and perform >>> post-layout sims to extract those values to be used in the RTL in a >>> second iteration. > [] >> >> If I understand you correctly, you have a piece of combinatorial logic >> and you need to know how fast it will run in your design. This will >> then let your surrounding circuitry wait some number of clock cycles to >> read the result, that give you a longer delay than the delay though the >> logic. > > Precisely. > >> I think your starting premise that multi-cycle constraints are "out of >> the question" is where you have erred. Multi-cycle constraints are >> exactly what are required and if you don't understand how to use them >> you are not likely to get a good result. > > There are two aspects here to consider: > > 1. multicycle constraints need not only a /from/ and /to/ parameter, they also > need a /through/ parameter. When you have a logic depth of 111 gates you start to > understand why a multicycle constraint cannot be a sustainable solution. I can't say I follow that. I have only ever specified a from and to parameter for a timing constraint. I have never needed to indicate a "through" parameter. If you have special sections of the logic that need a shorter timing constraint than others, I would expect that to be a subset of the from and to, not a special "though" path. Is there something unique about your design that a simple from and to spec doesn't capture the nuance? > 2. My experience in setting up multicycle constraints is nearly zero and starting > off with such an approach on this type of project would be begging for troubles. How much experience do you have with any of the other approaches you are trying? I mean, you are here asking for advice. So clearly there are things about each of these approaches you are not familiar with. >> Post P&R simulation is not a good way to validate timing because it is >> so hard to cover every path through the logic. Static timing analysis >> is the right way to do this and you need to learn to use it properly. > > I've read several times on this group the skepticism behind static timing analysis > when multicycle constraints are in place. I have to search back in the archives to > really understand the technical motivations, but the bottom line is: > > a. is difficult to maintain them; if the logic path has been optimized the > constraint does not work anymore I don't follow that either. It is seldom that any from/to path would be optimized away. If it is, it is likely due to an error in your code which you will need to fix anyway. > b. is difficult to verify them; if the path *is not* multicycle you may wrongly > relax the timing too much and never realize until another optimization takes place > and your circuit does not work any more. ALL timing constraints are difficult to verify... no, make that impossible. That has always been one of my complaints about static timing analysis, there is no way to verify the constraints other than the coverage number which is just a pass/fail sort of thing. > If anyone sees a flaw in my points above I'd be glad to be corrected. Perhaps I am missing something. ??? -- Rick From newsfish@newsfish Thu Aug 1 00:29:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Thu, 03 Apr 2014 18:21:53 -0400 Organization: A noiseless patient Spider Lines: 45 Message-ID: References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> <19e%u.484$%U7.400@fx05.am4> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 3 Apr 2014 22:21:33 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="24042"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/9R37M+2jCkQ+wm66euWRo" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: <19e%u.484$%U7.400@fx05.am4> Cancel-Lock: sha1:uHEqh49miEZZLZ1w3ARFWGj3XaU= Xref: news.eternal-september.org comp.lang.vhdl:2958 On 4/3/2014 10:22 AM, HT-Lab wrote:> On 03/04/2014 14:30, KJ wrote: >> On Thursday, April 3, 2014 8:33:39 AM UTC-4, HT-Lab wrote: >>>> IMHO a multicycle path delay is a propagation delay specified as >>>> relative to the clock period. Hence it *does* depend on the clock >>>> frequency, while the propagation through your gates does not (it >>>> depends >>>> on the technology). >>> >>> You still have your terminology wrong, here is a SDC example of an >>> typical MCP constraint: >>> >>> set_multicycle_path 2 -from reg_alu* -to reg_mult* >>> >>> Notice there is no time, just a natural number of clock cycles. >> >> The value of '2' though is computed based on the clock period. Alb >> already pointed that out earlier in the thread "If your path takes >> 12.3 ns you would have to set a multicycle constraint of 2 with a >> 100MHz clock, but 3 with a 200MHz one." >> > > We are taking about different issues here. My argument is that you > should not exchange a clock constraint for an MCP one, I think you are misreading what is intended. It is assumed there is already a clock timing constraint of 100 MHz. That is for the general logic in this clock domain. But for a certain section of logic the output of the logic is not used for some number of clock cycles that will be determined by the delay through the logic which is expected to be longer than one clock cycle. The OP wants to set this number of clock cycles in the timing constraints of that special path to verify that the P&R output will work with the timing he has picked. If the timing fails he has the options of working to improve the timing in the P&R or changing the logic of the register enable to allow more clock cycles for this path. In no case would he want to change the timing constraint on the clock since that constraint is set by other aspects of his design goals. Do I misunderstand what you are trying to say? -- Rick From newsfish@newsfish Thu Aug 1 00:29:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 4 Apr 2014 14:09:46 GMT Lines: 44 Message-ID: References: X-Trace: individual.net FKgR5kH/xYpARDDJ1AdfTgpO01nQpD/9M5VHPEY/8N3nouRkYi X-Orig-Path: not-for-mail Cancel-Lock: sha1:wT54wFsHemaiYDcfSOnsmnSQBaE= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2959 Hi Kevin, KJ wrote: >> I have to find out how much time I need to wait before sampling the >> logic with my output enable. There are several (in the 100s) paths >> between input and output (it's an fpu), therefore I can die under a pile >> of multicycle path constraints. > > You should be able to wild card the path sources inside your block and > specify exactly the output enable signal. There should be no need to > specify each path source explicitly. Imagine an fpu, with two input registers for the operands, one for the operator and an output register for the result. The result register is the one that will receive the output enable. Depending on the operator I will have a different path. If I wildcard the path sources than I'm overly constraining and a 'nop' operation will take as much as a division operation, which is not what we want. Since most of the combinatorial functions are reused several times in each operation, the datapath starts to be painfully complicated. That is the main reason why I discarded the option to setup multicycle constraints. The alternative, though, is not very palatable either. We decided to set false paths between the above mentioned registers and let post-par sim figure out whether we are in or out with our output enable. The problem is that post-par simulation may not cover the whole set of timing scerarios the logic will encounter. For instance I do not know if a backannotated simulation includes clock skew, while AFAIK it shoudl be taken into account in STA. The described approach tries to verify timing, but I'm not sure this is really going to be risk free. Certainly I can add some jitter to my clock within the simulation itself to make it more /realistic/ , but I will certainly not cover all the cases. Considering the target FPGA is an RTAX2000 (~20'000$), we are kind of unconfortable to proceed without a fully consistent picture. Al From newsfish@newsfish Thu Aug 1 00:29:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 4 Apr 2014 14:09:49 GMT Lines: 69 Message-ID: References: X-Trace: individual.net uVTN+L/pUHIyi4rGq0B3jQv7389nc5bWPUeVQXTxWZgdZqDcXQ X-Orig-Path: not-for-mail Cancel-Lock: sha1:WJHPLxHltwSOk8ef7xupOayRi1U= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2960 Hi Rick, rickman wrote: [] > > 1. multicycle constraints need not only a /from/ and /to/ > parameter, they also > > need a /through/ parameter. When you have a logic depth of 111 gates > you start to > > understand why a multicycle constraint cannot be a sustainable solution. > > I can't say I follow that. I have only ever specified a from and to > parameter for a timing constraint. I have never needed to indicate a > "through" parameter. If you have special sections of the logic that > need a shorter timing constraint than others, I would expect that to be > a subset of the from and to, not a special "though" path. Is there > something unique about your design that a simple from and to spec > doesn't capture the nuance? Imagine your path between two registers (A and B) is set by another register C. The resulting operation is to be stored in register D. If you do not set a /through/ clause you will constraint each path with the maximum delay, which is not desirable. > > > 2. My experience in setting up multicycle constraints is nearly > zero and starting > > off with such an approach on this type of project would be begging > for troubles. > > How much experience do you have with any of the other approaches you are > trying? I mean, you are here asking for advice. So clearly there are > things about each of these approaches you are not familiar with. I've often done post-par sims, but it was combined with an STA, therefore I've always been sure the design was correct as long as STA did not report anything fishy *and* post-par sim succeeded. Recently I started to look at post-par sims as an additional step which is not necessarily required for synchronous logic as long as your input constraints are well defined. In this case we cannot use STA to do time analysis and I'm unconfortable. > > > a. is difficult to maintain them; if the logic path has been > optimized the > > constraint does not work anymore > > I don't follow that either. It is seldom that any from/to path would be > optimized away. If it is, it is likely due to an error in your code > which you will need to fix anyway. I certainly was talking about the /through/ clause I mentioned earlier. The synthesis tool might optimize away (or maybe rename) certain nets and you're constraint will not be applicable anymore. > > b. is difficult to verify them; if the path *is not* multicycle you > may wrongly > > relax the timing too much and never realize until another > optimization takes place > > and your circuit does not work any more. > > ALL timing constraints are difficult to verify... no, make that > impossible. That has always been one of my complaints about static > timing analysis, there is no way to verify the constraints other than > the coverage number which is just a pass/fail sort of thing. That is why you'd be better off if you didn't have them! :-) From newsfish@newsfish Thu Aug 1 00:29:21 2024 X-Received: by 10.182.81.7 with SMTP id v7mr6507obx.28.1396625269036; Fri, 04 Apr 2014 08:27:49 -0700 (PDT) X-Received: by 10.182.241.70 with SMTP id wg6mr423obc.19.1396625268818; Fri, 04 Apr 2014 08:27:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no2815268iga.0!news-out.google.com!xg2ni98igc.0!nntp.google.com!ur14no2451962igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Apr 2014 08:27:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> Subject: Re: [cross-post]path verification From: KJ Injection-Date: Fri, 04 Apr 2014 15:27:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:2961 > >> I have to find out how much time I need to wait before sampling the=20 > >> logic with my output enable. There are several (in the 100s) paths=20 > >> between input and output (it's an fpu), therefore I can die under a pi= le=20 > >> of multicycle path constraints.=20 > >=20 > > You should be able to wild card the path sources inside your block and= =20 > > specify exactly the output enable signal. There should be no need to= =20 > > specify each path source explicitly.=20 >=20 > Imagine an fpu, with two input registers for the operands, one for the=20 > operator and an output register for the result. The result register is=20 > the one that will receive the output enable.=20 >=20 > Depending on the operator I will have a different path. If I wildcard=20 > the path sources than I'm overly constraining and a 'nop' operation will= =20 > take as much as a division operation, which is not what we want.=20 >=20 You're assuming (and you may be correct since you know the design better th= an I) that the logic path taken by the 'nop' operation is in fact segregate= d from that of the division operation. Certainly at the instruction opcode= decode level they're not separate...but maybe that occurs on a different c= lock cycle. > Since most of the combinatorial functions are reused several times in=20 > each operation, the datapath starts to be painfully complicated. That is= =20 > the main reason why I discarded the option to setup multicycle=20 > constraints.=20 >=20 And makes me think that things are not implemented in the logic in a segreg= ated fashion which could mean that seemingly unrelated instructions like 'n= op' might depend on logic used by division. > The alternative, though, is not very palatable either. We decided to set= =20 > false paths between the above mentioned registers and let post-par sim=20 > figure out whether we are in or out with our output enable. The problem= =20 > is that post-par simulation may not cover the whole set of timing=20 > scerarios the logic will encounter.=20 >=20 That's correct. Post route sim really tells you nothing about timing. The= only use I've found for that sim can be for finding that something wasn't = implemented correctly which then resulted in finding a work around and subm= itting a service request to the software provider. That has only happened = once (for me). > For instance I do not know if a backannotated simulation includes clock= =20 > skew, while AFAIK it shoudl be taken into account in STA. Sims do not take into account any timing variation. You may be able to run= them with 'min', 'typical' or 'maximum' but not combinations. It is no su= bstitute for static timing analysis (nor is it intended to be). > The described=20 > approach tries to verify timing, but I'm not sure this is really going=20 > to be risk free.=20 >=20 > Certainly I can add some jitter to my clock within the simulation itself= =20 > to make it more /realistic/ , but I will certainly not cover all the=20 > cases.=20 >=20 > Considering the target FPGA is an RTAX2000 (~20'000$), we are kind of=20 > unconfortable to proceed without a fully consistent picture.=20 My suggestions: 1. Since this is purchased IP, go back to the supplier, pay them some money= and tell them you need validated timing constraints for their design. 2. If #1 is not feasible for whatever reason, then see about altering the I= P to insert pipeline registers. This may be ugly and means you will have t= o reverse engineer the design but it is verifiable since you will be able t= o get through STA without having to wonder if your constraints are correct = and you can run original and modified sims to verify function is unchanged. 3. This might actually be the best option but I don't know how well it rea= lly works since I've never tried it. You can buy software that claims to v= erify that timing constraints are correct [1] Kevin Jennings [1] http://www.bluepearlsoftware.com/sdc/ From newsfish@newsfish Thu Aug 1 00:29:21 2024 X-Received: by 10.58.169.198 with SMTP id ag6mr4356573vec.22.1396631221570; Fri, 04 Apr 2014 10:07:01 -0700 (PDT) X-Received: by 10.50.59.179 with SMTP id a19mr116737igr.10.1396631221429; Fri, 04 Apr 2014 10:07:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w5no593295qac.0!news-out.google.com!gi6ni194igc.0!nntp.google.com!ur14no2573485igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Apr 2014 10:07:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <121818ae-9da8-4d75-a3f7-a92f92bfe92e@googlegroups.com> Subject: Re: How dofor using generate or loop for this process ? From: Andy Injection-Date: Fri, 04 Apr 2014 17:07:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:2962 It is not clear from the example what is the index range on SelFifo, and if= that range matches the range of DataAvlble. We do know that Selfifo has 6 = bits. DataAvlble has at least 6 bits, indexed between 6 and 1 inclusive, bu= t we do not know DataAvlble's index range direction. The loop would only work if SelFifo'range is 6 downto 1. The following would work if the index diretion of both DataAvlble and SelFi= fo is "downto", given the correct value for DaOffset: pSelFifo : process(Clk, SRst)=20 constant DaOffset : integer :=3D 1; begin=20 if SRst =3D '1' then=20 SelFifo <=3D (others=3D>'0');=20 elsif rising_edge(Clk) then=20 SelFifo <=3D (others=3D>'0');=20 for i in SelFifo'reverse_range loop -- right to left in SelFifo if DataAvlble(i + DaOffset) =3D '1' then=20 SelFifo(i) <=3D '1';=20 exit; -- prevent multiple bit set, as in original=20 end if;=20 end loop;=20 end if;=20 end process;=20 The sum (i + DaOffset) becomes a constant when synthesis unrolls the loop. Andy From newsfish@newsfish Thu Aug 1 00:29:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 4 Apr 2014 21:53:20 GMT Lines: 115 Message-ID: References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> X-Trace: individual.net is1Yj9rGx6h15qUyF320VQhI45tXza3dukrOjaaWJydnzIeYNZ X-Orig-Path: not-for-mail Cancel-Lock: sha1:Tzb/m29/qt1aR6U94QrPyt4LFsc= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2963 Hi Kevin, KJ wrote: [] >> Imagine an fpu, with two input registers for the operands, one for the >> operator and an output register for the result. The result register is >> the one that will receive the output enable. >> >> Depending on the operator I will have a different path. If I wildcard >> the path sources than I'm overly constraining and a 'nop' operation will >> take as much as a division operation, which is not what we want. >> > > You're assuming (and you may be correct since you know the design > better than I) that the logic path taken by the 'nop' operation is in > fact segregated from that of the division operation. Certainly at the > instruction opcode decode level they're not separate...but maybe that > occurs on a different clock cycle. there are a certain number of 'atomic' operations that are reused among several floating point ops, so there's no such a clear separation among them. The decode is performed on a different cycle, therefore is not of a concern. >> Since most of the combinatorial functions are reused several times in >> each operation, the datapath starts to be painfully complicated. That is >> the main reason why I discarded the option to setup multicycle >> constraints. >> > > And makes me think that things are not implemented in the logic in a > segregated fashion which could mean that seemingly unrelated > instructions like 'nop' might depend on logic used by division. That is correct. And this is why the need of a set of /through/ clauses need to be in place. Imagine the following: opcode path multicycle constraint X a + b + c -through a -through b -through c Y a + d + e + f -through a -through d -through e -through f Z q + r + t + a + d ... The rest of the constraint definition is the /from/ and /to/ clause which are simpler since they are the input registers and the output one. Now, since 'atomic' operations are separated into different entities (as far as I can tell) I may take the input ports to identify a path through that entity and maybe survive net renaming and the like, but you can imagine how much fun it might be to trace all individual paths. Oh and I forgot! some of the operations (notably the division) they do need registers to hold temporary results, therefore they will have to be treated separately (so I cannot really false path the whole block...jeez). >> The alternative, though, is not very palatable either. We decided to set >> false paths between the above mentioned registers and let post-par sim >> figure out whether we are in or out with our output enable. The problem >> is that post-par simulation may not cover the whole set of timing >> scerarios the logic will encounter. >> > > That's correct. Post route sim really tells you nothing about timing. > The only use I've found for that sim can be for finding that something > wasn't implemented correctly which then resulted in finding a work > around and submitting a service request to the software provider. you mean it wasn't implemented correctly in the p&r tool? >> For instance I do not know if a backannotated simulation includes clock >> skew, while AFAIK it shoudl be taken into account in STA. > > Sims do not take into account any timing variation. You may be able > to run them with 'min', 'typical' or 'maximum' but not combinations. > It is no substitute for static timing analysis (nor is it intended to > be). This is indeed what I also thought (I hate to be right!). > My suggestions: > 1. Since this is purchased IP, go back to the supplier, pay them some > money and tell them you need validated timing constraints for their > design. out of question, the developer is a chinese who left to Brazil hoping to find his karma... (cannot truly blame him) > 2. If #1 is not feasible for whatever reason, then see about altering > the IP to insert pipeline registers. This may be ugly and means you > will have to reverse engineer the design but it is verifiable since > you will be able to get through STA without having to wonder if your > constraints are correct and you can run original and modified sims to > verify function is unchanged. This was my very first proposal. Rejected with a simple: 'no design changes'. I understant - partially - the philosophy to keep the IP as is (considering that has been functionally verified), but maybe here it would be simpler and _safer_ to add a pipeline. I thought about C-slowing and retiming, I can start with large logic depth (maximum is 113!) and maybe add registers at the input ports of the 'atomic' operations I mentioned earlier. > 3. This might actually be the best option but I don't know how well > it really works since I've never tried it. You can buy software that > claims to verify that timing constraints are correct [1] I was wondering if they let us try their tool for a short period of time (maybe a couple of weeks), enough to get ourselves out of this painful situation and maybe convince the management is really a must have tool. > [1] http://www.bluepearlsoftware.com/sdc/ any user here? From newsfish@newsfish Thu Aug 1 00:29:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Fri, 04 Apr 2014 21:20:40 -0400 Organization: A noiseless patient Spider Lines: 51 Message-ID: References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 5 Apr 2014 01:20:20 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="9608"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19v+X/gygwKQBTCNFrofVAY" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> Cancel-Lock: sha1:mBOO9CY1g0gpgnEiyaA3PTL3Q/U= Xref: news.eternal-september.org comp.lang.vhdl:2964 On 4/4/2014 11:27 AM, KJ wrote: ...snip... >> The described >> approach tries to verify timing, but I'm not sure this is really going >> to be risk free. >> >> Certainly I can add some jitter to my clock within the simulation itself >> to make it more /realistic/ , but I will certainly not cover all the >> cases. >> >> Considering the target FPGA is an RTAX2000 (~20'000$), we are kind of >> unconfortable to proceed without a fully consistent picture. > > My suggestions: > 1. Since this is purchased IP, go back to the supplier, pay them some money and tell them you need validated timing constraints for their design. > 2. If #1 is not feasible for whatever reason, then see about altering the IP to insert pipeline registers. This may be ugly and means you will have to reverse engineer the design but it is verifiable since you will be able to get through STA without having to wonder if your constraints are correct and you can run original and modified sims to verify function is unchanged. > 3. This might actually be the best option but I don't know how well it really works since I've never tried it. You can buy software that claims to verify that timing constraints are correct [1] > > Kevin Jennings I concur. Right now I don't see how the design can be analyzed for timing. If the OP wants to set different timing constraints for different paths through the combinatorial logic, there either has to be some clearly identifiable approach to isolating the paths for static timing analysis or the design has to change. I guess one question would be why use the IP from this particular vendor? Another would be if there are clearly different paths within the combinatorial logic, can these could be broken out in some way to allow timing constraints to be applied separately? It would not be unreasonable to duplicate the input registers so that each differently timed operation would not have the same starting point in the design allowing separate from/to timing constraints. If information on the operation is available at the time the input registers are loaded each one could have a separate enable so the tools would clearly know they are equivalent. Otherwise the tools might try to be too smart for their own good and you may need to use modifiers to keep the duplicate registers from being optimized away. -- Rick From newsfish@newsfish Thu Aug 1 00:29:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Fri, 04 Apr 2014 21:22:41 -0400 Organization: A noiseless patient Spider Lines: 97 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 5 Apr 2014 01:22:33 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="9608"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Y3S7x/LmE22yQaFxvCkFz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:GAK09NqxX7B7fcJ901wZzIWSZFA= Xref: news.eternal-september.org comp.lang.vhdl:2965 On 4/4/2014 10:09 AM, alb wrote: > Hi Rick, > > rickman wrote: > [] >>> 1. multicycle constraints need not only a /from/ and /to/ >> parameter, they also >>> need a /through/ parameter. When you have a logic depth of 111 gates >> you start to >>> understand why a multicycle constraint cannot be a sustainable solution. >> >> I can't say I follow that. I have only ever specified a from and to >> parameter for a timing constraint. I have never needed to indicate a >> "through" parameter. If you have special sections of the logic that >> need a shorter timing constraint than others, I would expect that to be >> a subset of the from and to, not a special "though" path. Is there >> something unique about your design that a simple from and to spec >> doesn't capture the nuance? > > Imagine your path between two registers (A and B) is set by another > register C. The resulting operation is to be stored in register D. If > you do not set a /through/ clause you will constraint each path with the > maximum delay, which is not desirable. Ok, so where is the problem with specifying the through parameters if you know them? >>> 2. My experience in setting up multicycle constraints is nearly >> zero and starting >>> off with such an approach on this type of project would be begging >> for troubles. >> >> How much experience do you have with any of the other approaches you are >> trying? I mean, you are here asking for advice. So clearly there are >> things about each of these approaches you are not familiar with. > > I've often done post-par sims, but it was combined with an STA, > therefore I've always been sure the design was correct as long as STA > did not report anything fishy *and* post-par sim succeeded. I have never done post-par sims because they are pointless for timing verification and the logic should be good by construction. In essence this is only verifying the synthesis tools, not the design. > Recently I started to look at post-par sims as an additional step which > is not necessarily required for synchronous logic as long as your input > constraints are well defined. > > In this case we cannot use STA to do time analysis and I'm > unconfortable. I think uncomfortable would be an understatement. There is no other way to properly and fully verify timing than STA. Either make it work or find a different way to implement your design is my advice. >>> a. is difficult to maintain them; if the logic path has been >> optimized the >>> constraint does not work anymore >> >> I don't follow that either. It is seldom that any from/to path would be >> optimized away. If it is, it is likely due to an error in your code >> which you will need to fix anyway. > > I certainly was talking about the /through/ clause I mentioned earlier. > The synthesis tool might optimize away (or maybe rename) certain nets > and you're constraint will not be applicable anymore. If the tool optimizes away some part of your design you have problems. I believe the renaming is done with synonyms so that a constraint should still apply. You might want to get in touch with support. Who's parts are you using? If a specified through target can be optimized out it isn't a very useful feature to have in the STA tool is it? >>> b. is difficult to verify them; if the path *is not* multicycle you >> may wrongly >>> relax the timing too much and never realize until another >> optimization takes place >>> and your circuit does not work any more. >> >> ALL timing constraints are difficult to verify... no, make that >> impossible. That has always been one of my complaints about static >> timing analysis, there is no way to verify the constraints other than >> the coverage number which is just a pass/fail sort of thing. > > That is why you'd be better off if you didn't have them! I think of it like getting old. It is the worst thing in the world except for the alternative. -- Rick From newsfish@newsfish Thu Aug 1 00:29:22 2024 X-Received: by 10.182.230.168 with SMTP id sz8mr3423385obc.9.1396662295526; Fri, 04 Apr 2014 18:44:55 -0700 (PDT) X-Received: by 10.182.110.167 with SMTP id ib7mr89073obb.5.1396662295382; Fri, 04 Apr 2014 18:44:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no2777038igb.0!news-out.google.com!gi6ni200igc.0!nntp.google.com!l13no3085360iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Apr 2014 18:44:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> Subject: Re: [cross-post]path verification From: KJ Injection-Date: Sat, 05 Apr 2014 01:44:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:2966 On Friday, April 4, 2014 5:53:20 PM UTC-4, alb wrote: >=20 > > And makes me think that things are not implemented in the logic in a=20 > > segregated fashion which could mean that seemingly unrelated=20 > > instructions like 'nop' might depend on logic used by division. >=20 > That is correct. And this is why the need of a set of /through/ clauses= =20 > need to be in place. Imagine the following: >=20 > opcode path multicycle constraint > X a + b + c -through a -through b -through c > Y a + d + e + f -through a -through d -through e -through f > Z q + r + t + a + d ... >=20 > The rest of the constraint definition is the /from/ and /to/ clause=20 > which are simpler since they are the input registers and the output one. >=20 Unless you obtain a deep knowledge of the design, if you try to do what you= described above, you're likely screwed. There's always the chance that it= 's not quite as bad as it appears right now, but there is an equally good c= hance that it is actually worse...and you won't know it until it's too late= and you're shipping product and 'wierd' things are happening when the boar= d warms up or cools down or whatever. > > That's correct. Post route sim really tells you nothing about timing. = =20 > > The only use I've found for that sim can be for finding that something= =20 > > wasn't implemented correctly which then resulted in finding a work=20 > > around and submitting a service request to the software provider. =20 >=20 > you mean it wasn't implemented correctly in the p&r tool? >=20 That's correct. Actually, I had two instances. One was if you passed into= an entity a generic that happened to be a vector, it treated the elements = of the vector as '1 to n', even though the entity definition specifically d= efined them as 'n downto 1'. The other case had to do with not initializin= g the contents of an inferred memory. Using the post-route sim model was conclusive evidence of an improper build= and the cool thing is that the sim really only had to run for a couple nan= oseconds to prove the memory initialization problem; an assertion printing = out the details of the vector comes out simply from starting the simulator. > > My suggestions: >=20 > > 3. This might actually be the best option but I don't know how well=20 > > it really works since I've never tried it. You can buy software that= =20 > > claims to verify that timing constraints are correct [1] > I was wondering if they let us try their tool for a short period of time= =20 > (maybe a couple of weeks), enough to get ourselves out of this painful=20 > situation and maybe convince the management is really a must have tool. >=20 Seems like this would be your best option. Right now, you're caught in the= project management iron triangle: you don't have the right resource (off = in Brazil), you don't have schedule time to modify the design and it sounds= like management might not want to spend the $$ to get the design correct. = The only end result that will have a functional design in this case is to = punt on performance and accept whatever slow speed you can get out of the I= P core by only specifying constraints that you know for absolute fact are c= orrect and stop trying to figure out if this path through this hunk really = can wait a clock or not. Even if you spend the money and the tool happens to guarantee that they wil= l produce valid constraints, there is no guarantee that the end performance= will actually be any better...you will simply know that you've got it prop= erly constrained. You might also want to do some more Google searching for= some other tools that perform this constraint validation. I don't think t= he link I gave you previously is the one I remember from a while back eithe= r in this forum or possibly comp.lang.vhdl so there might be at least one o= ther company to look for to generate valid constraints. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:22 2024 X-Received: by 10.50.73.132 with SMTP id l4mr3662668igv.5.1396663590207; Fri, 04 Apr 2014 19:06:30 -0700 (PDT) X-Received: by 10.182.142.38 with SMTP id rt6mr109obb.10.1396663590025; Fri, 04 Apr 2014 19:06:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no3087690iga.0!news-out.google.com!gi6ni200igc.0!nntp.google.com!l13no3087688iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Apr 2014 19:06:29 -0700 (PDT) In-Reply-To: <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77d6bb14-5b18-4f77-af8f-f793abcccd0c@googlegroups.com> Subject: Re: [cross-post]path verification From: KJ Injection-Date: Sat, 05 Apr 2014 02:06:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2967 On Friday, April 4, 2014 9:44:55 PM UTC-4, KJ wrote: > Even if you spend the money and the tool happens to guarantee that they will > produce valid constraints, there is no guarantee that the end performance > will actually be any better...you will simply know that you've got it > properly constrained. You might also want to do some more Google searching > for some other tools that perform this constraint validation. I don't think > the link I gave you previously is the one I remember from a while back either > in this forum or possibly comp.lang.vhdl so there might be at least one other > company to look for to generate valid constraints. > Here is another company that seems to have a timing constraint verification product http://www.averant.com/products-solidtc.html Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:23 2024 X-Received: by 10.66.139.231 with SMTP id rb7mr8887479pab.33.1396725616244; Sat, 05 Apr 2014 12:20:16 -0700 (PDT) X-Received: by 10.50.59.179 with SMTP id a19mr265577igr.10.1396725616092; Sat, 05 Apr 2014 12:20:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no3154333igb.0!news-out.google.com!gi6ni228igc.0!nntp.google.com!l13no3346708iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Apr 2014 12:20:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.140.40.14; posting-account=tKKUQAoAAABSFlLwwB8ig4AeRm5W6Gbz NNTP-Posting-Host: 14.140.40.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Subject: how to avoidind multisourcing on signal From: yogesh malekar Injection-Date: Sat, 05 Apr 2014 19:20:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2968 How to avoi multisourcing on the signal,and bad synchronois descrption From newsfish@newsfish Thu Aug 1 00:29:23 2024 X-Received: by 10.236.175.66 with SMTP id y42mr10425721yhl.38.1396725784158; Sat, 05 Apr 2014 12:23:04 -0700 (PDT) X-Received: by 10.50.80.10 with SMTP id n10mr265450igx.2.1396725783989; Sat, 05 Apr 2014 12:23:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dc16no108462qab.1!news-out.google.com!gi6ni194igc.0!nntp.google.com!ur14no3155151igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Apr 2014 12:23:03 -0700 (PDT) In-Reply-To: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.140.40.14; posting-account=tKKUQAoAAABSFlLwwB8ig4AeRm5W6Gbz NNTP-Posting-Host: 14.140.40.14 References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <898f8fc4-586b-4e14-9849-59fef44b0f91@googlegroups.com> Subject: how to avoidind multisourcing on signal From: yogesh malekar Injection-Date: Sat, 05 Apr 2014 19:23:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2969 Anybody give me vhdl program for non restoring division algorithm To burn it on cpld working on 4 MHZ frequency From newsfish@newsfish Thu Aug 1 00:29:23 2024 X-Received: by 10.66.139.231 with SMTP id rb7mr8895601pab.33.1396725876345; Sat, 05 Apr 2014 12:24:36 -0700 (PDT) X-Received: by 10.182.119.133 with SMTP id ku5mr133862obb.4.1396725876170; Sat, 05 Apr 2014 12:24:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no3155711igb.0!news-out.google.com!gi6ni194igc.0!nntp.google.com!ur14no3155693igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Apr 2014 12:24:35 -0700 (PDT) In-Reply-To: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: how to avoidind multisourcing on signal From: KJ Injection-Date: Sat, 05 Apr 2014 19:24:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2970 On Saturday, April 5, 2014 3:20:15 PM UTC-4, yogesh malekar wrote: > How to avoi multisourcing on the signal,and bad synchronois descrption Perhaps by asking someone other than you to write the code. From newsfish@newsfish Thu Aug 1 00:29:24 2024 X-Received: by 10.43.18.133 with SMTP id qg5mr12904496icb.13.1396820418444; Sun, 06 Apr 2014 14:40:18 -0700 (PDT) X-Received: by 10.50.143.1 with SMTP id sa1mr410435igb.12.1396820418341; Sun, 06 Apr 2014 14:40:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no3742447iga.0!news-out.google.com!gi6ni194igc.0!nntp.google.com!ur14no3701813igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Apr 2014 14:40:17 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.37.244.164; posting-account=dRhSmgoAAABgGYf0yu8Eg4Q7x1BVxe66 NNTP-Posting-Host: 72.37.244.164 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7fe4843d-15cc-4a6d-91fc-75c6354ab2b9@googlegroups.com> Subject: verilog questions From: sandhya pochiraju Injection-Date: Sun, 06 Apr 2014 21:40:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:2971 Hi All, I have few questions in verilog. please can someone here help me un= derstand this.=20 Let's say, db_count =3D debounce_cnt at 10th positive edge.=20 will "IF" condition in second always block be true at 10th positive edge? or will "IF" condition in second always block be true at 11th positive edge= ? but on 11th positive edge db_count will be set to 0 by first always block= .=20 what is order of operation between "IF" and "Case" ? Though everything is in one always block and non blocking statements are us= ed, "IF" and "Case" are two seperate blocks in themselves. Is the non-block= ing behaviour of statements not confined seperately to "IF" and "Case" bloc= ks? i.e. statements inside "IF" are non-blocking but are they non-blocking = to statements inside "case" and vice versa? Code: `timescale 1 ns / 1 ns module debounce ( //inputs // what value is stored in pbtn_in and switch_in input clk, // clock=09 input [3:0] pbtn_in, // pushbutton inputs input [7:0] switch_in, // slider switch inputs =09 //outputs output reg [3:0] pbtn_db =3D 3'h0, // debounced outputs of pushbuttons= =09 output reg [7:0] swtch_db =3D 8'h0 // debounced outputs of slider switche= s ); parameter simulate =3D 0; // these are two ways to simulate.=20 // simulate is a parameter.=20 // what is the difference in two waits.=20 =09 localparam debounce_cnt =3D simulate ? 22'd5 // debounce clock= when simulating : 22'd4_000_000; // debounce count w= hen running on HW //shift registers used to debounce switches and buttons=09 reg [21:0] db_count =3D 22'h0; //counter for debouncer // 8 switches.=20 // 5 buttons.=20 reg [4:0] shift_pb0 =3D 5'h0, shift_pb1 =3D 5'h0, shift_pb2 =3D 5'h0, shif= t_pb3 =3D 5'h0, shift_pb4 =3D 5'h0; reg [3:0] shift_swtch0 =3D 4'h0, shift_swtch1 =3D 4'h0, shift_swtch2 =3D 4= 'h0, shift_swtch3 =3D 4'h0;=09 reg [3:0] shift_swtch4 =3D 4'h0, shift_swtch5 =3D 4'h0, shift_swtch6 = =3D 4'h0, shift_swtch7 =3D 4'h0; =09 // debounce clock // at positive edge, count is incremented always @(posedge clk) begin=20 if (db_count =3D=3D debounce_cnt) // it is 5 for simulation.=20 db_count <=3D 1'b0; //takes 40mS to reach 4,000,000 else db_count <=3D db_count + 1'b1; end =09 always @(posedge clk)=20 begin // if this always and one is line 51 race condition.=20 // if 51 runs first, then db_count will be set to szero when below conditi= on is true.=20 if (db_count =3D=3D debounce_cnt) begin //sample every 40mS //shift registers for pushbuttons // i am shifting left once and doing a bitwise OR it with 0th bit of pbt= h_in // why // what is the value in pbtn_in shift_pb0 <=3D (shift_pb0 << 1) | pbtn_in[0]; =09 shift_pb1 <=3D (shift_pb1 << 1) | pbtn_in[1]; =09 shift_pb2 <=3D (shift_pb2 << 1) | pbtn_in[2]; =09 shift_pb3 <=3D (shift_pb3 << 1) | pbtn_in[3]; shift_pb4 <=3D (shift_pb4 << 1) | pbtn_in[4];=20 =09 //shift registers for slider switches // i am doing same operation here.=20 // all these happen at same time.=20 // what is the value in switch_in shift_swtch0 <=3D (shift_swtch0 << 1) | switch_in[0]; shift_swtch1 <=3D (shift_swtch1 << 1) | switch_in[1]; shift_swtch2 <=3D (shift_swtch2 << 1) | switch_in[2]; shift_swtch3 <=3D (shift_swtch3 << 1) | switch_in[3]; shift_swtch4 <=3D (shift_swtch4 << 1) | switch_in[4]; shift_swtch5 <=3D (shift_swtch5 << 1) | switch_in[5]; shift_swtch6 <=3D (shift_swtch6 << 1) | switch_in[6]; shift_swtch7 <=3D (shift_swtch7 << 1) | switch_in[7]; end =09 //debounced pushbutton outputs // if first four bits are zero then bit zero is set to 0=20 // if first four bits are one then bit zero is set to 1 case(shift_pb0) 4'b0000: pbtn_db[0] <=3D 0; 4'b1111: pbtn_db[0] <=3D 1; e= ndcase case(shift_pb1) 4'b0000: pbtn_db[1] <=3D 0; 4'b1111: pbtn_db[1] <=3D 1; e= ndcase case(shift_pb2) 4'b0000: pbtn_db[2] <=3D 0; 4'b1111: pbtn_db[2] <=3D 1; e= ndcase case(shift_pb3) 4'b0000: pbtn_db[3] <=3D 0; 4'b1111: pbtn_db[3] <=3D 1; e= ndcase case(shift_pb4) 4'b0000: pbtn_db[4] <=3D 0; 4'b1111: pbtn_db[4] <=3D 1; e= ndcase =09 //debounced slider switch outputs case(shift_swtch0) 4'b0000: swtch_db[0] <=3D 0; 4'b1111: swtch_db[0] <= =3D 1; endcase case(shift_swtch1) 4'b0000: swtch_db[1] <=3D 0; 4'b1111: swtch_db[1] <= =3D 1; endcase case(shift_swtch2) 4'b0000: swtch_db[2] <=3D 0; 4'b1111: swtch_db[2] <= =3D 1; endcase case(shift_swtch3) 4'b0000: swtch_db[3] <=3D 0; 4'b1111: swtch_db[3] <= =3D 1; endcase=09 case(shift_swtch4) 4'b0000: swtch_db[4] <=3D 0; 4'b1111: swtch_db[4] <= =3D 1; endcase case(shift_swtch5) 4'b0000: swtch_db[5] <=3D 0; 4'b1111: swtch_db[5] <= =3D 1; endcase case(shift_swtch6) 4'b0000: swtch_db[6] <=3D 0; 4'b1111: swtch_db[6] <= =3D 1; endcase case(shift_swtch7) 4'b0000: swtch_db[7] <=3D 0; 4'b1111: swtch_db[7] <= =3D 1; endcase end // if and case happen in parallel as it is non blocking statement. right.= =20 // for simulation i am not waiting for as much as i am waiting for synthes= is.=20 endmodule From newsfish@newsfish Thu Aug 1 00:29:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: verilog questions Date: Sun, 06 Apr 2014 19:48:07 -0400 Organization: A noiseless patient Spider Lines: 121 Message-ID: References: <7fe4843d-15cc-4a6d-91fc-75c6354ab2b9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 6 Apr 2014 23:47:44 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="25454"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/UXCLRFoK4AKQlWTOhOcZn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: <7fe4843d-15cc-4a6d-91fc-75c6354ab2b9@googlegroups.com> Cancel-Lock: sha1:SlAsgvxDGlOKWDLwOSn4esWsf1g= Xref: news.eternal-september.org comp.lang.vhdl:2972 comp.lang.verilog:851 Not trying to be a jerk, but have you considered asking in a Verilog group? This is a VHDL group. I'm just sayin'... Tell you what, I've cross posted it for you. :) Rick On 4/6/2014 5:40 PM, sandhya pochiraju wrote: > > Hi All, I have few questions in verilog. please can someone here help me understand this. > > > Let's say, db_count = debounce_cnt at 10th positive edge. > will "IF" condition in second always block be true at 10th positive edge? > > or will "IF" condition in second always block be true at 11th positive edge? but on 11th positive edge db_count will be set to 0 by first always block. > > > what is order of operation between "IF" and "Case" ? > Though everything is in one always block and non blocking statements are used, "IF" and "Case" are two seperate blocks in themselves. Is the non-blocking behaviour of statements not confined seperately to "IF" and "Case" blocks? i.e. statements inside "IF" are non-blocking but are they non-blocking to statements inside "case" and vice versa? > > Code: > > > > `timescale 1 ns / 1 ns > module debounce ( > //inputs > // what value is stored in pbtn_in and switch_in > input clk, // clock > input [3:0] pbtn_in, // pushbutton inputs > input [7:0] switch_in, // slider switch inputs > > //outputs > output reg [3:0] pbtn_db = 3'h0, // debounced outputs of pushbuttons > output reg [7:0] swtch_db = 8'h0 // debounced outputs of slider switches > ); > parameter simulate = 0; > // these are two ways to simulate. > // simulate is a parameter. > // what is the difference in two waits. > > localparam debounce_cnt = simulate ? 22'd5 // debounce clock when simulating > : 22'd4_000_000; // debounce count when running on HW > > //shift registers used to debounce switches and buttons > reg [21:0] db_count = 22'h0; //counter for debouncer > // 8 switches. > // 5 buttons. > reg [4:0] shift_pb0 = 5'h0, shift_pb1 = 5'h0, shift_pb2 = 5'h0, shift_pb3 = 5'h0, shift_pb4 = 5'h0; > reg [3:0] shift_swtch0 = 4'h0, shift_swtch1 = 4'h0, shift_swtch2 = 4'h0, shift_swtch3 = 4'h0; > reg [3:0] shift_swtch4 = 4'h0, shift_swtch5 = 4'h0, shift_swtch6 = 4'h0, shift_swtch7 = 4'h0; > > // debounce clock > // at positive edge, count is incremented > always @(posedge clk) > begin > if (db_count == debounce_cnt) // it is 5 for simulation. > db_count <= 1'b0; //takes 40mS to reach 4,000,000 > else > db_count <= db_count + 1'b1; > end > > always @(posedge clk) > begin > // if this always and one is line 51 race condition. > // if 51 runs first, then db_count will be set to szero when below condition is true. > if (db_count == debounce_cnt) begin //sample every 40mS > //shift registers for pushbuttons > // i am shifting left once and doing a bitwise OR it with 0th bit of pbth_in > // why > // what is the value in pbtn_in > shift_pb0 <= (shift_pb0 << 1) | pbtn_in[0]; > shift_pb1 <= (shift_pb1 << 1) | pbtn_in[1]; > shift_pb2 <= (shift_pb2 << 1) | pbtn_in[2]; > shift_pb3 <= (shift_pb3 << 1) | pbtn_in[3]; > shift_pb4 <= (shift_pb4 << 1) | pbtn_in[4]; > > //shift registers for slider switches > // i am doing same operation here. > // all these happen at same time. > // what is the value in switch_in > shift_swtch0 <= (shift_swtch0 << 1) | switch_in[0]; > shift_swtch1 <= (shift_swtch1 << 1) | switch_in[1]; > shift_swtch2 <= (shift_swtch2 << 1) | switch_in[2]; > shift_swtch3 <= (shift_swtch3 << 1) | switch_in[3]; > shift_swtch4 <= (shift_swtch4 << 1) | switch_in[4]; > shift_swtch5 <= (shift_swtch5 << 1) | switch_in[5]; > shift_swtch6 <= (shift_swtch6 << 1) | switch_in[6]; > shift_swtch7 <= (shift_swtch7 << 1) | switch_in[7]; > end > > //debounced pushbutton outputs > // if first four bits are zero then bit zero is set to 0 > // if first four bits are one then bit zero is set to 1 > case(shift_pb0) 4'b0000: pbtn_db[0] <= 0; 4'b1111: pbtn_db[0] <= 1; endcase > case(shift_pb1) 4'b0000: pbtn_db[1] <= 0; 4'b1111: pbtn_db[1] <= 1; endcase > case(shift_pb2) 4'b0000: pbtn_db[2] <= 0; 4'b1111: pbtn_db[2] <= 1; endcase > case(shift_pb3) 4'b0000: pbtn_db[3] <= 0; 4'b1111: pbtn_db[3] <= 1; endcase > case(shift_pb4) 4'b0000: pbtn_db[4] <= 0; 4'b1111: pbtn_db[4] <= 1; endcase > > //debounced slider switch outputs > case(shift_swtch0) 4'b0000: swtch_db[0] <= 0; 4'b1111: swtch_db[0] <= 1; endcase > case(shift_swtch1) 4'b0000: swtch_db[1] <= 0; 4'b1111: swtch_db[1] <= 1; endcase > case(shift_swtch2) 4'b0000: swtch_db[2] <= 0; 4'b1111: swtch_db[2] <= 1; endcase > case(shift_swtch3) 4'b0000: swtch_db[3] <= 0; 4'b1111: swtch_db[3] <= 1; endcase > case(shift_swtch4) 4'b0000: swtch_db[4] <= 0; 4'b1111: swtch_db[4] <= 1; endcase > case(shift_swtch5) 4'b0000: swtch_db[5] <= 0; 4'b1111: swtch_db[5] <= 1; endcase > case(shift_swtch6) 4'b0000: swtch_db[6] <= 0; 4'b1111: swtch_db[6] <= 1; endcase > case(shift_swtch7) 4'b0000: swtch_db[7] <= 0; 4'b1111: swtch_db[7] <= 1; endcase > end > // if and case happen in parallel as it is non blocking statement. right. > // for simulation i am not waiting for as much as i am waiting for synthesis. > endmodule > -- Rick From newsfish@newsfish Thu Aug 1 00:29:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx30.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> <19e%u.484$%U7.400@fx05.am4> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140406-0, 06/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 68 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396859171 86.29.12.221 (Mon, 07 Apr 2014 08:26:11 UTC) NNTP-Posting-Date: Mon, 07 Apr 2014 08:26:11 UTC Organization: virginmedia.com Date: Mon, 07 Apr 2014 09:26:11 +0100 X-Received-Body-CRC: 2284247576 X-Received-Bytes: 4197 Xref: news.eternal-september.org comp.lang.vhdl:2973 On 03/04/2014 23:21, rickman wrote: Hi Rick, > On 4/3/2014 10:22 AM, HT-Lab wrote:> On 03/04/2014 14:30, KJ wrote: > >> On Thursday, April 3, 2014 8:33:39 AM UTC-4, HT-Lab wrote: > >>>> IMHO a multicycle path delay is a propagation delay specified as > >>>> relative to the clock period. Hence it *does* depend on the clock > >>>> frequency, while the propagation through your gates does not (it > >>>> depends > >>>> on the technology). > >>> > >>> You still have your terminology wrong, here is a SDC example of an > >>> typical MCP constraint: > >>> > >>> set_multicycle_path 2 -from reg_alu* -to reg_mult* > >>> > >>> Notice there is no time, just a natural number of clock cycles. > >> > >> The value of '2' though is computed based on the clock period. Alb > >> already pointed that out earlier in the thread "If your path takes > >> 12.3 ns you would have to set a multicycle constraint of 2 with a > >> 100MHz clock, but 3 with a 200MHz one." > >> > > > > We are taking about different issues here. My argument is that you > > should not exchange a clock constraint for an MCP one, > > I think you are misreading what is intended. It is assumed there is > already a clock timing constraint of 100 MHz. That is for the general > logic in this clock domain. But for a certain section of logic the > output of the logic is not used for some number of clock cycles that > will be determined by the delay through the logic which is expected to > be longer than one clock cycle. > > The OP wants to set this number of clock cycles in the timing > constraints of that special path to verify that the P&R output will work > with the timing he has picked. If the timing fails he has the options > of working to improve the timing in the P&R or changing the logic of the > register enable to allow more clock cycles for this path. > > In no case would he want to change the timing constraint on the clock > since that constraint is set by other aspects of his design goals. > > Do I misunderstand what you are trying to say? > Yes, let me try again. What I am saying is that you should not use an MCP for a path that is not controlled. What Al seems to be doing is to use P&R to extract a path delay, he then chops it up into a number of clock delays and use that to set an MCP constraint. This create a design which will be difficult to maintain. Changing speed grade/device type/synthesis tool/version/settings/P&R settings etc will all make this process pretty painful for the next user. I also believe Al is working on some mission critical design (satellite?) so his current method will definitely fail the CDR. As suggested by others his only option is to modify the design and add e.g. output control to his FP paths, then set an MCP constraint on it and add some assertions to verify it. This should pass the CDR. Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:29:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 7 Apr 2014 08:55:28 GMT Lines: 55 Message-ID: References: X-Trace: individual.net 1YIqq/YQ0y8bBN1IdSEzrw73wCdrZ3rzfukwr/a9QO+WW0SYOE X-Orig-Path: not-for-mail Cancel-Lock: sha1:DdfkSRMS2WBHtgbGipHF0NCviHM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2974 Hi Rick, rickman wrote: [] > > Imagine your path between two registers (A and B) is set by another > > register C. The resulting operation is to be stored in register D. If > > you do not set a /through/ clause you will constraint each path with the > > maximum delay, which is not desirable. > > Ok, so where is the problem with specifying the through parameters if > you know them? The main problem is that I do not know them all and is a PITA to trace them. > I think uncomfortable would be an understatement. There is no other way > to properly and fully verify timing than STA. Either make it work or > find a different way to implement your design is my advice. I share your point, my manager doesn't! Ouch! [] > > The synthesis tool might optimize away (or maybe rename) certain nets > > and you're constraint will not be applicable anymore. > > If the tool optimizes away some part of your design you have problems. I > believe the renaming is done with synonyms so that a constraint should > still apply. You might want to get in touch with support. Who's parts > are you using? If a specified through target can be optimized out it > isn't a very useful feature to have in the STA tool is it? Is not only a matter of optimization, which might happen since a resource might be shared and suddenly a gate does not have the same nets' names anymore. On top of that I'm not quite familiar with synthesis tools name mangling techniques, therefore I cannot be sure the name I use for my /through/ clause will remain constant throughout several synthesis runs. I guess there are other attributes I can set to maintain certain names as they are, but the exercise becomes more and more difficult to maintain. [] > > That is why you'd be better off if you didn't have them [timing > > constraints]! > > I think of it like getting old. It is the worst thing in the world > except for the alternative. Someone said the same about democracy :-) Al p.s.: FYI I guess your Thunderbird 24.4.0 has serious issues with quoting, I'm not use if it might be related to your Win8 or a combination of the two, but your quoting is all screwed up. From newsfish@newsfish Thu Aug 1 00:29:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 7 Apr 2014 09:00:13 GMT Lines: 14 Message-ID: References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> <77d6bb14-5b18-4f77-af8f-f793abcccd0c@googlegroups.com> X-Trace: individual.net Unj03dpTraqwRiONIYHPKQ+YKtzipEoIPNK3tjhnl7gLvn8sox X-Orig-Path: not-for-mail Cancel-Lock: sha1:mhiTVJ4dX4J8KowVxAP8uxVCOzY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2975 Hi Kevin, KJ wrote: [] > Here is another company that seems to have a timing constraint verification product > http://www.averant.com/products-solidtc.html thanks a lot, Hans suggested me this a week or so ago. http://www.fishtail-da.com/ I hope one of them has a trial period. Al From newsfish@newsfish Thu Aug 1 00:29:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 7 Apr 2014 09:00:19 GMT Lines: 61 Message-ID: References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> X-Trace: individual.net Xt0mzOsqomBqPukDeHVjXAwlnrbqjjenMTLvRCh+BbpynsoYR0 X-Orig-Path: not-for-mail Cancel-Lock: sha1:DIujtbf9UJOJWbmdO+tkPCETaXs= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2976 Hi Kevin, KJ wrote: [] >> opcode path multicycle constraint >> X a + b + c -through a -through b -through c >> Y a + d + e + f -through a -through d -through e -through f >> Z q + r + t + a + d ... >> >> The rest of the constraint definition is the /from/ and /to/ clause >> which are simpler since they are the input registers and the output one. >> > > Unless you obtain a deep knowledge of the design, if you try to do > what you described above, you're likely screwed. There's always the > chance that it's not quite as bad as it appears right now, but there > is an equally good chance that it is actually worse...and you won't > know it until it's too late and you're shipping product and 'wierd' > things are happening when the board warms up or cools down or > whatever. I guess I have no choice but trace all the paths. Do port names get completely wiped out when the netlist is generated? I ask because I was thinking about using ports' names for /through/ clauses and I was wondering whether they are kept in some form on the output netlist (I'm using synplify_pro). [] >> > 3. This might actually be the best option but I don't know how well >> > it really works since I've never tried it. You can buy software that >> > claims to verify that timing constraints are correct [1] >> I was wondering if they let us try their tool for a short period of time >> (maybe a couple of weeks), enough to get ourselves out of this painful >> situation and maybe convince the management is really a must have tool. >> > > Seems like this would be your best option. Right now, you're caught > in the project management iron triangle: you don't have the right > resource (off in Brazil), you don't have schedule time to modify the > design and it sounds like management might not want to spend the $$ to > get the design correct. The only end result that will have a > functional design in this case is to punt on performance and accept > whatever slow speed you can get out of the IP core by only specifying > constraints that you know for absolute fact are correct and stop > trying to figure out if this path through this hunk really can wait a > clock or not. Uhm, that would be a show stopper. The 'hunk' limits the speed to 1/5th of the target one and this will compromise system performances beyond an acceptable level. We must constraint the 'hunk' properly. > Even if you spend the money and the tool happens to guarantee that > they will produce valid constraints, there is no guarantee that the > end performance will actually be any better...you will simply know > that you've got it properly constrained. [] A set of multicycle constraints should allow the tool to make the design meet the system clock frequency target and keep the 'hunk' running at a lower pace (through the output enable). Al From newsfish@newsfish Thu Aug 1 00:29:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 7 Apr 2014 09:00:22 GMT Lines: 36 Message-ID: References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> <19e%u.484$%U7.400@fx05.am4> X-Trace: individual.net 5PXuRqkjNU0kvKV5mmUOIA7r3Hua/ytDRKvv/Yy2Ox2v9BZTUk X-Orig-Path: not-for-mail Cancel-Lock: sha1:O/QC1TwsLFjU4gohbwKgtmIAC1A= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2977 Hi Hans, HT-Lab wrote: [] >> The OP wants to set this number of clock cycles in the timing >> constraints of that special path to verify that the P&R output will work >> with the timing he has picked. If the timing fails he has the options >> of working to improve the timing in the P&R or changing the logic of the >> register enable to allow more clock cycles for this path. [] > What I am saying is that you should not use an MCP for a path that is > not controlled. What Al seems to be doing is to use P&R to extract a > path delay, he then chops it up into a number of clock delays and use > that to set an MCP constraint. Thanks for rephrasing it so clearly! > This create a design which will be > difficult to maintain. Changing speed grade/device type/synthesis > tool/version/settings/P&R settings etc will all make this process pretty > painful for the next user. I also believe Al is working on some mission > critical design (satellite?) so his current method will definitely fail > the CDR. I agree with you. This exercise will be needed every time we will change target, clock frequency, etc... We advocated for the design change path, but, as you may know, there might be other factors to consider in the equation for the best choice and only time will say if not changing the design would be the best one (even if rarely it is). > As suggested by others his only option is to modify the design and add > e.g. output control to his FP paths, then set an MCP constraint on it > and add some assertions to verify it. This should pass the CDR. How would the assertions help me in verifying it? From newsfish@newsfish Thu Aug 1 00:29:26 2024 X-Received: by 10.236.141.11 with SMTP id f11mr15445130yhj.54.1396862698971; Mon, 07 Apr 2014 02:24:58 -0700 (PDT) X-Received: by 10.182.44.233 with SMTP id h9mr604obm.41.1396862698803; Mon, 07 Apr 2014 02:24:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!cm18no399444qab.0!news-out.google.com!gi6ni264igc.0!nntp.google.com!ur14no3904103igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Apr 2014 02:24:58 -0700 (PDT) In-Reply-To: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: how to avoidind multisourcing on signal From: Thomas Stanka Injection-Date: Mon, 07 Apr 2014 09:24:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2978 Am Samstag, 5. April 2014 21:20:15 UTC+2 schrieb yogesh malekar: > How to avoi multisourcing on the signal,and bad synchronois descrption The best way is avoid it during code writing. Second best solution is to detect such issues as fast as possible. Multisourcing can be detected during compile of code, if you use no resolved signal types (only std_ulogic or std_ulogic_vector). So if you use only unresolved type you know if code can be simulated, it has no multisourcing at all. For bad synchronous description you could identify all clock domain crosings (CDC) by hand and verify their correct handling. Alternative spend money in license for tools to help in identifying and verifying of CDC. regards Thomas From newsfish@newsfish Thu Aug 1 00:29:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx13.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> <19e%u.484$%U7.400@fx05.am4> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140406-0, 06/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 58 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396865544 86.29.12.221 (Mon, 07 Apr 2014 10:12:24 UTC) NNTP-Posting-Date: Mon, 07 Apr 2014 10:12:24 UTC Organization: virginmedia.com Date: Mon, 07 Apr 2014 11:12:25 +0100 X-Received-Body-CRC: 1193679158 X-Received-Bytes: 3498 Xref: news.eternal-september.org comp.lang.vhdl:2979 On 07/04/2014 10:00, alb wrote: > Hi Hans, > > HT-Lab wrote: > [] >>> The OP wants to set this number of clock cycles in the timing >>> constraints of that special path to verify that the P&R output will work >>> with the timing he has picked. If the timing fails he has the options >>> of working to improve the timing in the P&R or changing the logic of the >>> register enable to allow more clock cycles for this path. > [] > >> What I am saying is that you should not use an MCP for a path that is >> not controlled. What Al seems to be doing is to use P&R to extract a >> path delay, he then chops it up into a number of clock delays and use >> that to set an MCP constraint. > > Thanks for rephrasing it so clearly! > >> This create a design which will be >> difficult to maintain. Changing speed grade/device type/synthesis >> tool/version/settings/P&R settings etc will all make this process pretty >> painful for the next user. I also believe Al is working on some mission >> critical design (satellite?) so his current method will definitely fail >> the CDR. > > I agree with you. This exercise will be needed every time we will change > target, clock frequency, etc... We advocated for the design change path, > but, as you may know, there might be other factors to consider in the > equation for the best choice and only time will say if not changing the > design would be the best one (even if rarely it is). > >> As suggested by others his only option is to modify the design and add >> e.g. output control to his FP paths, then set an MCP constraint on it >> and add some assertions to verify it. This should pass the CDR. > > How would the assertions help me in verifying it? > Hi Al, The assertion is on the control logic of the MCP path. Thus the assertion will fail if data can flow from your input to your output registers in less than the specified number of cycles (your MCP clock value). Look at the Fishtail link I send earlier, you might want to read up on the term sensitization before looking at the example. Good luck with your project, Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:29:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: how to avoidind multisourcing on signal Date: Mon, 07 Apr 2014 10:30:43 -0400 Organization: Alacron, Inc. Lines: 24 Message-ID: References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 7 Apr 2014 14:32:45 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="9431"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190X6h1ZTZIVnJPubTpzGWIUgQKyTNF6vw=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:6aAIVq3cv3YBeXtpOOgJH7Hoe4U= Xref: news.eternal-september.org comp.lang.vhdl:2980 Thomas Stanka wrote: > Am Samstag, 5. April 2014 21:20:15 UTC+2 schrieb yogesh malekar: >> How to avoi multisourcing on the signal,and bad synchronois descrption > > The best way is avoid it during code writing. Second best solution is to detect such issues as fast as possible. > > Multisourcing can be detected during compile of code, if you use no resolved signal types (only std_ulogic or std_ulogic_vector). > So if you use only unresolved type you know if code can be simulated, it has no multisourcing at all. > > For bad synchronous description you could identify all clock domain crosings (CDC) by hand and verify their correct handling. Alternative spend money in license for tools to help in identifying and verifying of CDC. > > regards Thomas "multi-source" happens when you drive (assign) a signal in more than one process. Don't do that for synthesis. "bad synchronous description" is a term used by Xilinx to tell you that your sequential logic does not match a standard flip-flop template. To avoid that use the language templates to see what the synthesis tools expect. For xilinx this is available in the GUI (light bulb icon) as well as in the XST user guide. -- Gabor From newsfish@newsfish Thu Aug 1 00:29:26 2024 X-Received: by 10.66.66.109 with SMTP id e13mr595259pat.1.1396926725812; Mon, 07 Apr 2014 20:12:05 -0700 (PDT) X-Received: by 10.50.25.4 with SMTP id y4mr60256igf.10.1396926725612; Mon, 07 Apr 2014 20:12:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!newsreader4.netcologne.de!news.netcologne.de!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!l13no4208181iga.0!news-out.google.com!gi6ni272igc.0!nntp.google.com!ur14no4334089igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Apr 2014 20:12:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=218.111.12.216; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 218.111.12.216 References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9df171c9-0bba-43a0-aba7-90fe3bec0c98@googlegroups.com> Subject: Re: how to avoidind multisourcing on signal From: Daniel Kho Injection-Date: Tue, 08 Apr 2014 03:12:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3639 X-Received-Body-CRC: 707312435 Xref: news.eternal-september.org comp.lang.vhdl:2981 On Monday, 7 April 2014 22:30:43 UTC+8, Gabor Sz wrote: > Thomas Stanka wrote: >=20 > > Am Samstag, 5. April 2014 21:20:15 UTC+2 schrieb yogesh malekar: >=20 > >> How to avoi multisourcing on the signal,and bad synchronois descrption >=20 > >=20 >=20 > > The best way is avoid it during code writing. Second best solution is t= o detect such issues as fast as possible. >=20 > >=20 >=20 > > Multisourcing can be detected during compile of code, if you use no res= olved signal types (only std_ulogic or std_ulogic_vector). >=20 > > So if you use only unresolved type you know if code can be simulated, i= t has no multisourcing at all. >=20 > >=20 >=20 > > For bad synchronous description you could identify all clock domain cro= sings (CDC) by hand and verify their correct handling. Alternative spend mo= ney in license for tools to help in identifying and verifying of CDC.=20 >=20 > >=20 >=20 > > regards Thomas >=20 >=20 >=20 > "multi-source" happens when you drive (assign) a signal in more than >=20 > one process. Don't do that for synthesis. >=20 >=20 >=20 > "bad synchronous description" is a term used by Xilinx to tell you that >=20 > your sequential logic does not match a standard flip-flop template. To >=20 > avoid that use the language templates to see what the synthesis tools >=20 > expect. For xilinx this is available in the GUI (light bulb icon) as >=20 > well as in the XST user guide. >=20 >=20 >=20 > --=20 >=20 > Gabor Yes, like Gabor said, "multi-source" is a term used when you have multiple = drivers to a signal. If you don't intend to have multiple sources for a sig= nal (which is the case for most designs), I recommend the use of the unreso= lved VHDL types, such as std_ulogic, std_ulogic_vector, or unresolved_unsig= ned. By declaring signals to be unresolved, and if you accidentally drive t= hem from multiple sources, your simulator must give you an error. OTOH, if you use resolved types, your simulator will automatically resolve = the value of the signal as a function of all the input drivers (resolution = function). However, most synthesis tools (those that I know of) don't honour this thou= gh. They still give you an error even for a resolved signal and doesn't aut= omatically resolve the signal based on some function of its inputs. But sim= ulators are very strict in this sense. -daniel From newsfish@newsfish Thu Aug 1 00:29:27 2024 X-Received: by 10.58.22.70 with SMTP id b6mr406124vef.13.1396928676033; Mon, 07 Apr 2014 20:44:36 -0700 (PDT) X-Received: by 10.50.13.97 with SMTP id g1mr633927igc.0.1396928675916; Mon, 07 Apr 2014 20:44:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m5no225315qaj.1!news-out.google.com!gi6ni272igc.0!nntp.google.com!ur14no4341127igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Apr 2014 20:44:35 -0700 (PDT) In-Reply-To: <121818ae-9da8-4d75-a3f7-a92f92bfe92e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=218.111.12.216; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 218.111.12.216 References: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> <121818ae-9da8-4d75-a3f7-a92f92bfe92e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51188dfd-035b-4792-86d1-8068d50bd957@googlegroups.com> Subject: Re: How dofor using generate or loop for this process ? From: Daniel Kho Injection-Date: Tue, 08 Apr 2014 03:44:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3310 X-Received-Body-CRC: 441551736 Xref: news.eternal-september.org comp.lang.vhdl:2982 On Saturday, 5 April 2014 01:07:00 UTC+8, Andy wrote: > It is not clear from the example what is the index range on SelFifo, and = if that range matches the range of DataAvlble. We do know that Selfifo has = 6 bits. DataAvlble has at least 6 bits, indexed between 6 and 1 inclusive, = but we do not know DataAvlble's index range direction. >=20 >=20 >=20 > The loop would only work if SelFifo'range is 6 downto 1. >=20 >=20 >=20 > The following would work if the index diretion of both DataAvlble and Sel= Fifo is "downto", given the correct value for DaOffset: >=20 >=20 >=20 > pSelFifo : process(Clk, SRst)=20 >=20 > constant DaOffset : integer :=3D 1; >=20 > begin=20 >=20 > if SRst =3D '1' then=20 >=20 > SelFifo <=3D (others=3D>'0');=20 >=20 > elsif rising_edge(Clk) then=20 >=20 > SelFifo <=3D (others=3D>'0');=20 >=20 > for i in SelFifo'reverse_range loop -- right to left in SelFifo >=20 > if DataAvlble(i + DaOffset) =3D '1' then=20 >=20 > SelFifo(i) <=3D '1';=20 >=20 > exit; -- prevent multiple bit set, as in original=20 >=20 > end if;=20 >=20 > end loop;=20 >=20 > end if;=20 >=20 > end process;=20 >=20 >=20 >=20 > The sum (i + DaOffset) becomes a constant when synthesis unrolls the loop= . >=20 >=20 >=20 > Andy Something like this might just work (not tested): signal n: positive; ... pSelFifo : process(Clk, SRst) begin if SRst =3D '1' then=20 SelFifo <=3D (others=3D>'0');=20 elsif Clk'event and Clk=3D'1' then if n>6 then SelFifo <=3D (others=3D>'0'); else if DataAvlble(n) then SelFifo <=3D to_unsigned(2**(n-1),6); end if= ; end if; end if;=20 end process; Not sure though if this will synthesise. Probably not, since the expression= (2**(n-1)) is not a constant. However, this can be replaced by a shift-lef= t operation for synthesis. We could try that as well. -daniel From newsfish@newsfish Thu Aug 1 00:29:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: [cross-post][long] svn workflow for fpga development Date: 8 Apr 2014 07:21:22 GMT Lines: 63 Message-ID: References: <99563aff-ed56-4973-8fd3-578761768223@googlegroups.com> X-Trace: individual.net EST2KnSJwcAnSEbLbDB5tQoJlzu4j7ktiHENp28xfk+X8OvYkW X-Orig-Path: not-for-mail Cancel-Lock: sha1:PFfE0Lq9IbFSgbMyNKrGkwahS64= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.arch.fpga:6700 comp.lang.vhdl:2983 Hi Chris, Chris Higgs wrote: [] > In my own experience, I've found it's far easier to lead by example > than battle the internal corporate structure - I soon got tired of > arguing! Leading by example is certainly far more powerful than arguing, I agree. The problem is that in an environment where your hours are counted for each activity you are carrying on it becomes obvious that I should take all these activities back home and do them on my 'spare' time. The good thing is that I find these activities quite amusing and enjoy a lot in building these kind of environment. > If the company is wedded to out-dated version control software I'll > still use git locally. There are often wrappers[1] that make > interfacing easy. I'll run GitLab to provide myself a nice HTTP > code/diff browser etc. If there's no bug-tracker(!!) I'll use GitLab > issues to track things locally. I'll certainly give a shot to git-svn, as far as code/diff browsing, I'm far too used to emacs and I consider html browsing quite cumbersome (no keyboard bindings! How can you live without key bindings!). We do have bugzilla but people are not using it effectively so there's not really a list of bugs, rather a list of 'actions' which are assigned to a specific person. In this way you have no chance to check what bugs other people have and you cannot even contribute to them (I know it sounds pretty silly!). > If the company has no regression, I'll > run a Jenkins server on my box. If tests aren't scripted, I'll spend > some time writing some Makefiles. If the tests aren't self-checking, > I'll gradually add some pass/fail criteria so the tests become useful. > I'll then start plotting graphs for things like simulation coverage, > FPGA resource utilisation etc. using Jenkins. This is my secret plan indeed, but you need to be careful though, you do not want to step on somebody else's foot! Moreover I'm not specifically asked to do so, therefore I need to sneak these activities in the middle of my 'official' ones. > > Unless you're working in an extremely restrictive environment with no > control over your development box, none of this requires sign-off from > the powers that be. You'll find other developers and then management > are suddenly curious to know how you can spot only a few minutes after > they've checked something in that the resource utilisation for their > block has doubled... or how you can say with such confidence that a > certain feature has never been tested in simulation. Once they see > the nice web interface of Jenkins and the pretty graphs, understand > the ease with which you can see what's happening in the repository, > they'll soon be asking for you to centralise your development set-up > so they can all benefit :) At least I managed to install a vbox on my windoz station and now I'm practically behind my fence ;-) > PS apologies for breaking the cross-post again... curse GG news.individual.net charges you 10$ a year... A reasonable price to get rid of GG! From newsfish@newsfish Thu Aug 1 00:29:27 2024 X-Received: by 10.43.14.137 with SMTP id pq9mr10092373icb.12.1397222999461; Fri, 11 Apr 2014 06:29:59 -0700 (PDT) X-Received: by 10.140.90.111 with SMTP id w102mr1130qgd.41.1397222999433; Fri, 11 Apr 2014 06:29:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no5585807iga.0!news-out.google.com!dz10ni6221qab.1!nntp.google.com!m5no863893qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Apr 2014 06:29:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.233.80.250; posting-account=PjyGrQoAAAAh4lKqW0lEgUEckVv3_YxK NNTP-Posting-Host: 41.233.80.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL code error From: Youssef Ahmed Injection-Date: Fri, 11 Apr 2014 13:29:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2984 Hello there, i'm new here so i dont know if this is on topic or should be placed somewhere else. my code is this: "library ieee; use ieee.std_logic_1164.all; package andpackage is component and2 is port (a, b: IN std_logic; c: OUT std_logic); end component and2; end package andpackage; entity circuit2 is port (a, b, x, y: IN std_logic; d: OUT std_logic); end entity circuit2; architecture mixed of circuit2 is for gate: and2 use entity work.and2(and2); signal c,z: std_logic; begin gate: and2 port map (a,b,c); d <= c XOR z; op: process (x,y) is begin z <= x OR y; end process op; end architecture mixed;" i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier "std_logic"." while the 3rd just says "VHDL Compiler exiting", any help would be greatly appreciated, thanks in advance. From newsfish@newsfish Thu Aug 1 00:29:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error Date: 11 Apr 2014 14:11:22 GMT Lines: 21 Message-ID: References: X-Trace: individual.net kAPNU8d57wSnqu92zbU3PQPDgX51JOXh5JUJCAK8BP/XS3axv8 X-Orig-Path: not-for-mail Cancel-Lock: sha1:dkB1wf15xjh0VvZmMe2TV6LpiPY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2985 Hi Youssef, Youssef Ahmed wrote: [] > i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier > "std_logic"." while the 3rd just says "VHDL Compiler exiting", any > help would be greatly appreciated, thanks in advance. the information you are providing is not sufficient to spot the problem. In order to compile the code the compiler should know *where* to look for the ieee library and use the package you are referring to. Do not focus only on the code, try to see if the environment you have is setup properly. If possible, try to compile something you *know* should work (like an example from a project tutorial of your tools [1] or something you borrow from a colleague). Once you are sure your environment is properly setup then you can focus on the code. Al [1] I think long ago I did the exercise for an Orcad project, something like a Chebyshev filter...it failed miserably!! From newsfish@newsfish Thu Aug 1 00:29:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer01.fr7!news.highwinds-media.com!post01.fr7!fx26.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140411-0, 11/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 45 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397226760 86.29.12.221 (Fri, 11 Apr 2014 14:32:40 UTC) NNTP-Posting-Date: Fri, 11 Apr 2014 14:32:40 UTC Organization: virginmedia.com Date: Fri, 11 Apr 2014 15:32:39 +0100 X-Received-Body-CRC: 3128341135 X-Received-Bytes: 2206 Xref: news.eternal-september.org comp.lang.vhdl:2986 On 11/04/2014 14:29, Youssef Ahmed wrote: > Hello there, i'm new here so i dont know if this is on topic or should be placed somewhere else. > > my code is this: > "library ieee; > use ieee.std_logic_1164.all; > > package andpackage is > component and2 is > port (a, b: IN std_logic; > c: OUT std_logic); > end component and2; > end package andpackage; library ieee; use ieee.std_logic_1164.all; use work.andpackage.all; > > entity circuit2 is > port (a, b, x, y: IN std_logic; > d: OUT std_logic); > end entity circuit2; > > architecture mixed of circuit2 is -- for gate: and2 use entity work.and2(and2); > signal c,z: std_logic; > begin > gate: and2 port map (a,b,c); > d <= c XOR z; > op: process (x,y) is > begin > z <= x OR y; > end process op; > end architecture mixed;" > > i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier "std_logic"." while the 3rd just says "VHDL Compiler exiting", any help would be greatly appreciated, thanks in advance. > Hope this help, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:29:28 2024 X-Received: by 10.66.139.9 with SMTP id qu9mr6874912pab.41.1397228909051; Fri, 11 Apr 2014 08:08:29 -0700 (PDT) X-Received: by 10.140.20.75 with SMTP id 69mr47082qgi.17.1397228908993; Fri, 11 Apr 2014 08:08:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!border3.nntp.dca.giganews.com!nntp.giganews.com!l13no5615971iga.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no1879740qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Apr 2014 08:08:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> Subject: Re: VHDL code error From: KJ Injection-Date: Fri, 11 Apr 2014 15:08:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 13 Xref: news.eternal-september.org comp.lang.vhdl:2987 On Friday, April 11, 2014 9:29:59 AM UTC-4, Youssef Ahmed wrote: You need to place the following... library ieee;=20 use ieee.std_logic_1164.all; ...before both the package definition (where you have it now) AND before th= e entity definition. Packages and entities are considered 'primary design = units'. Any libraries you want to include must be listed prior to each one= . The 'architecture' is considered a 'secondary design unit' which does no= t need yet another round of 'library ieee...' because it has been immediate= ly preceded by the primary design unit. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Design toplevel module as schematic? Date: Mon, 14 Apr 2014 09:46:40 +0200 Organization: A noiseless patient Spider Lines: 21 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 14 Apr 2014 07:46:24 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="29540"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+pW7GBrRz6xF9WxxiqQ42q" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 Cancel-Lock: sha1:jiDYLO5W40a+sxvlMPV0esXmLys= Xref: news.eternal-september.org comp.lang.vhdl:2988 Hi everybody, the question above has been come up between a colleague and me. Should the toplevel module be created as schematic plan or written as text in VHDL? I prefer the second one, my colleague the first. The only advantage I see for using schematic coding, is that I have a visual overview of my toplevel modul and I quickly can find which blocks are connected together. On the other side, the development process is much slower because of using the mouse instead of keyboard. I also think that using textfiles are much easier to handle for revision controlling software like git or svn. Maybe someone can give me a few impressions how you handle the toplevel module. Before I started my new job, we worked at CERN on very large designs with hundreds of moduls in a team with about 10 VHDL engineers. We avoided to use graphical coding and this worked excellent, so I don't see any reason, why to change this. Thanks a lot, Tobias From newsfish@newsfish Thu Aug 1 00:29:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 14 Apr 2014 08:56:50 GMT Lines: 50 Message-ID: References: X-Trace: individual.net t/ySa0xM1SUSFpUV1GMA4w49g7Mf1hF6apYBdmR5jD5hfgmsmV X-Orig-Path: not-for-mail Cancel-Lock: sha1:3U9mtreeyYlx8f5RlDp68dkE5aM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2989 Hi Tobias, Tobias Baumann wrote: [] > the question above has been come up between a colleague and me. Should > the toplevel module be created as schematic plan or written as text in VHDL? After discussing with myself for quite some time I tend to avoid using schematics for two main reasons: 1. portability 2. readability No matter which tool you use as schematic entry you will certainly face some portability problem when you have to switch target if the tool chain is different. Even if you generate vhdl out of it, you cannot simply generate a schematic out of vhdl with the same level of care you did your trace routing. Text is written to be read while a schematic is drawn to be looked at. Without going to far in perception psicology, we often overestimate visual representation. On top of it, in most *nix environment you are supported by a wealth of text manipulation tools. How could you live without *grep* or *sed*. > I prefer the second one, my colleague the first. The only advantage I > see for using schematic coding, is that I have a visual overview of my > toplevel modul and I quickly can find which blocks are connected together. use emacs speedbar to see which components are instantiated and if you did a good interface job than there's not such an added value in graphical representation. > On the other side, the development process is much slower because of > using the mouse instead of keyboard. I also think that using textfiles > are much easier to handle for revision controlling software like git or svn. > SVN handles binaries as well, but I guess that portability is more of an issue rather than revision tracking. [] > We avoided to use graphical coding and this worked excellent, so I don't > see any reason, why to change this. If you do not see any reason, why don't you ask what are the reasons to your colleague instead. It may simply be "tradition" and then you can simply forget all your reasonings. Al From newsfish@newsfish Thu Aug 1 00:29:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Mon, 14 Apr 2014 13:05:50 +0200 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 14 Apr 2014 11:05:35 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="11503"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+5vfnTZwErkypyDU5KN/5" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:EQMDpnAtPGj0jyCTYWlVWhL9Paw= Xref: news.eternal-september.org comp.lang.vhdl:2990 Am 14.04.2014 10:56, schrieb alb: > Text is written to be read while a schematic is drawn to be looked at. > Without going to far in perception psicology, we often overestimate > visual representation. I think that too, but there's the problem. Today the project leader came and wanted to see the schematic of my toplevel. So he made some trouble, because he as a none FPGA designer (but with experience in designing ASICs) wants to see a schmeatic to understand. Me as developer want to produce results, so I use textfile. If someone wants a schematic, I draw on a sheet of paper. The discussion ends up with "everybody uses schematic coding for the toplevel and it's silly to use VHDL for the toplevel". I really doubt this statement, so I started this discussion to see how others handle the toplevel. > On top of it, in most *nix environment you are supported by a wealth of text > manipulation tools. How could you live without *grep* or *sed*. > > use emacs speedbar to see which components are instantiated and if you > did a good interface job than there's not such an added value in > graphical representation. > I use Sigasi, which is perfect for me. It helps me to get quickly through a design. But even editors with VHDL highlighting are enough. It depends a bit on the quality of the source code. > If you do not see any reason, why don't you ask what are the reasons to > your colleague instead. It may simply be "tradition" and then you can > simply forget all your reasonings. The argument is, that it is standard for ASICs, so it has to be standard for FPGAs. But I think the real reason is: He wanted to see a schematic and becasue I have none he created an argument which fits his needs. Thanks a lot for sharing your opinion on this topic. From newsfish@newsfish Thu Aug 1 00:29:30 2024 X-Received: by 10.52.29.171 with SMTP id l11mr17305922vdh.0.1397479984989; Mon, 14 Apr 2014 05:53:04 -0700 (PDT) X-Received: by 10.140.26.77 with SMTP id 71mr1260qgu.38.1397479984947; Mon, 14 Apr 2014 05:53:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!cm18no2858986qab.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no2858985qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Apr 2014 05:53:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.65.126.58; posting-account=Eai9nQoAAADWhSIVdc0G4Z9jh8TwVNw0 NNTP-Posting-Host: 80.65.126.58 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <00fe738d-2716-4a33-b7cc-e32a40f4ab63@googlegroups.com> Subject: Re: Design toplevel module as schematic? From: devas Injection-Date: Mon, 14 Apr 2014 12:53:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2991 On Monday, April 14, 2014 9:46:40 AM UTC+2, Tobias Baumann wrote: > Hi everybody, > > > > the question above has been come up between a colleague and me. Should > > the toplevel module be created as schematic plan or written as text in VHDL? > > > > I prefer the second one, my colleague the first. The only advantage I > > see for using schematic coding, is that I have a visual overview of my > > toplevel modul and I quickly can find which blocks are connected together. > > Same discussion in our company. Some designers do not like schematic design (including me) and others like it and are angry when they have to made changes in your text based design. I see advantages of schematic design when you get an existing design but a good design description with some figures about the main path etc. helps a lot. > > On the other side, the development process is much slower because of > > using the mouse instead of keyboard. I also think that using textfiles > > are much easier to handle for revision controlling software like git or svn. > I agree. Text based is faster and easier to use in revision control. > > > Maybe someone can give me a few impressions how you handle the toplevel > > module. Before I started my new job, we worked at CERN on very large > > designs with hundreds of moduls in a team with about 10 VHDL engineers. > > We avoided to use graphical coding and this worked excellent, so I don't > > see any reason, why to change this. > > > > Thanks a lot, > > Tobias From newsfish@newsfish Thu Aug 1 00:29:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 14 Apr 2014 13:21:38 GMT Lines: 39 Message-ID: References: X-Trace: individual.net xnCiqN9Q/4MMvoljEfI8LgNBEFblje5kl128WpEBIKS83RqlU8 X-Orig-Path: not-for-mail Cancel-Lock: sha1:Ky1z4pQStaEVI3LbU7aDJdRaEdU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2992 Hi Tobias, Tobias Baumann wrote: [] >> Text is written to be read while a schematic is drawn to be looked at. >> Without going to far in perception psicology, we often overestimate >> visual representation. > > I think that too, but there's the problem. Today the project leader came > and wanted to see the schematic of my toplevel. So he made some trouble, > because he as a none FPGA designer (but with experience in designing > ASICs) wants to see a schmeatic to understand. Me as developer want to > produce results, so I use textfile. If someone wants a schematic, I draw > on a sheet of paper. The discussion ends up with "everybody uses > schematic coding for the toplevel and it's silly to use VHDL for the > toplevel". I really doubt this statement, so I started this discussion > to see how others handle the toplevel. IIRC Quartus generates top level block level view from your top level code and a quick search 'vhdl to schematic converter' can help you out. Your project leader point might be a valid one since it reflects an habit that is difficult to fight with. You may point out what you *can* do with a text file and how much portable the resulting code might be. But "there's none so deaf as those who will not hear". >> If you do not see any reason, why don't you ask what are the reasons to >> your colleague instead. It may simply be "tradition" and then you can >> simply forget all your reasonings. > > The argument is, that it is standard for ASICs, so it has to be standard > for FPGAs. But I think the real reason is: He wanted to see a schematic > and becasue I have none he created an argument which fits his needs. Assuming he does not have an argument is not going to help you easing the dispute. Try to see if he accepts an automatically generated schematic, this will make everybody happy ;-). HTH. Al From newsfish@newsfish Thu Aug 1 00:29:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!news.astraweb.com!border6.a.newsrouter.astraweb.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx20.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140414-0, 14/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 79 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397492141 86.29.12.221 (Mon, 14 Apr 2014 16:15:41 UTC) NNTP-Posting-Date: Mon, 14 Apr 2014 16:15:41 UTC Organization: virginmedia.com Date: Mon, 14 Apr 2014 17:15:41 +0100 X-Received-Body-CRC: 2616113814 X-Received-Bytes: 4237 Xref: news.eternal-september.org comp.lang.vhdl:2993 On 14/04/2014 08:46, Tobias Baumann wrote: Hi Tobias, > Hi everybody, > > the question above has been come up between a colleague and me. Should > the toplevel module be created as schematic plan or written as text in > VHDL? > > I prefer the second one, my colleague the first. I also prefer schematics. If you take 2 groups of engineers and you show an FSM bubble diagram to the first group and a few pages of RTL to the second, which one do you think will understand the circuit the quickest? I also know that most engineers (myself included) still draw bubble diagram and flow charts in their log book, so why not use a tool to capture that and generate some nice RTL for you. Some engineers like ASM's again this is something which is ideally suited for a graphical tool. > The only advantage I > see for using schematic coding, is that I have a visual overview of my > toplevel modul and I quickly can find which blocks are connected together. Not only that, it can also aid debugging as most of the visual tools allow you to back annotate your simulation results onto the schematics. This makes it very easy to single step through your FSM and see what is happening. Similarly, if you have a block diagram with a number of blocks, when an assertion or breakpoint triggers you can get an immediately overview of all the signals to each block. > > On the other side, the development process is much slower because of > using the mouse instead of keyboard. Not true, I can open a new diagram in my graphical editor, drag a few components from my library, connect the similar names signals with another mouse click and finally press the generate button to create some nicely formatted VHDL or Verilog. > I also think that using textfiles > are much easier to handle for revision controlling software like git or > svn. It is true that AFAIK you can't diff a schematic. > > Maybe someone can give me a few impressions how you handle the toplevel > module. Before I started my new job, we worked at CERN on very large > designs with hundreds of moduls in a team with about 10 VHDL engineers. > We avoided to use graphical coding and this worked excellent, so I don't > see any reason, why to change this. I suspect you have never tried it. If you have a design with hundreds of modules a spreadsheet like entry method might have helped you connect them. When RTL languages came out there was also "a bit" of resistance towards them (me included as I firmly believed my Viewlogic was all I needed to design my FPGA's) and now we can't live without them. Schematic editors are useful addition to an RTL designers tool set. However, the reality is that EDA has a small user base and developing these tools cost a lot of money so not many engineers can effort them and hence their uptake is low. You mentioned in a follow-up that you are using Sigasi, have you noticed they are adding more and more graphical visualisation to their product, I am sure that graphical editing capabilities will come next. As with everything in life, "horses for courses". Regards, Hans. www.ht-lab.com > > Thanks a lot, > Tobias From newsfish@newsfish Thu Aug 1 00:29:30 2024 X-Received: by 10.50.51.68 with SMTP id i4mr2628582igo.5.1397493819348; Mon, 14 Apr 2014 09:43:39 -0700 (PDT) X-Received: by 10.140.50.83 with SMTP id r77mr77849qga.15.1397493819235; Mon, 14 Apr 2014 09:43:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!ur14no8027249igb.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no2924024qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Apr 2014 09:43:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3877de94-f08c-4e02-8f4f-9db26b93ac1b@googlegroups.com> Subject: Re: VHDL code error From: Andy Injection-Date: Mon, 14 Apr 2014 16:43:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2994 As Hans has noted, The entity needs its context defined too. In VHDL, there is no "file scope." Each design unit (entity/architecture/package/package body declaration) in a file includes the context clause (lib..., use... statements) immediately preceding the design unit. However, an architecture inherits the context of its entity, and a package body inherits the context of its package. This often leads many to mistakenly infer that a "file scope" exists for VHDL. Andy From newsfish@newsfish Thu Aug 1 00:29:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Mon, 14 Apr 2014 10:05:48 -0700 Organization: Highland Technology, Inc. Lines: 28 Message-ID: <20140414100548.1b134002@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="fb1f8d326b6b433116d0372735136b8e"; logging-data="28785"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/PxLH7fgSScQ2f5yn/yA+F" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:oDRXMGZBY6q/9MMzL7cgn3YgRJQ= Xref: news.eternal-september.org comp.lang.vhdl:2995 On Mon, 14 Apr 2014 17:15:41 +0100 HT-Lab wrote: > I also know that most engineers (myself included) still draw bubble > diagram and flow charts in their log book, so why not use a tool to > capture that and generate some nice RTL for you. Some engineers like > ASM's again this is something which is ideally suited for a graphical tool. > Actually, I've found that I haven't drawn a straight up bubble diagram in ages, and only very rarely bother with flow charts any more. One major problem with graphical design is that you're tied to the idea that there is a "page size", rather than an infinite 2D plane. That's good, because the infinite plane very quickly explodes in complexity. But when you've got a page of finite size, then for a design above what you can visualize in your head, now you're having to span multiple pages. At that point, the continuous visualization is shot and you're back to having to mentally stitch together text tags. Easier to just write VHDL. Although for the last particularly large flowchart I really really needed I threw everyone else out of the conference room and designed the flow across the entirety of the conference table with 3 colors of Post-Its, tape, and butcher's twine. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:29:31 2024 X-Received: by 10.58.154.228 with SMTP id vr4mr21663714veb.0.1397496245841; Mon, 14 Apr 2014 10:24:05 -0700 (PDT) X-Received: by 10.140.102.136 with SMTP id w8mr112404qge.9.1397496245818; Mon, 14 Apr 2014 10:24:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m5no1944981qaj.1!news-out.google.com!dz10ni7240qab.1!nntp.google.com!m5no1944980qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Apr 2014 10:24:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> Subject: Re: Design toplevel module as schematic? From: Andy Injection-Date: Mon, 14 Apr 2014 17:24:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:2996 When in Rome, do as the Romans do. If your team is expecting a top level sc= hematic, you'll probably have to give it to them, at least until you can de= monstrate alternate means of giving them the "benefits" they currently thin= k they get from a top level schematic.=20 I started out using schematics a long time ago. After initially resisting V= HDL, I embraced it and would NEVER go back! I will not allow developers to use a schematic at any level to generate the= ir RTL. Schematics generate the VHDL code that may "look pretty", but machi= ne-generated VHDL is not maintainable (unless it can modify the schematic p= er RTL code changes), so you have to maintain the schematic, which then rai= ses some other questions that should be evaluated: Is the schematic tool freely distributable (not just the viewer)? Does the schematic provide for generate statements? Does the schematic provide for top-level generics? What about code comments? There are also techniques that can be used to simplify a purely structural = VHDL architecture to provide some of the understandability of a WELL-CRAFTE= D schematic. Use more complex data types than SL & SLV to group related sig= nals together (doues your schematic tool do that?) By the time the user generates symbols for each underlying component/entity= , and places them and connects them, naming each net, in a WELL CRAFTED sch= ematic, they will have spent FAR more time than writing the code. I have ye= t to see a decent "beautifier" for schematics. Plenty exist for VHDL. However, it takes a lot more than a beautifier to create human-understandab= le VHDL. Good coding standards, coding for function rather than netlist, et= c. go a long way. As previously noted, there are good tools for generating graphical document= ation from RTL: Sigasi (my favorite), DVT-Eclipse, Understand (sci-tools) a= nd many synthesis tools.=20 Displaying single-stepped simulation results on a schematic has got to be t= he worst excuse I have ever heard! That sounds like something a marketing m= anager would want to see (or a tool vendor would talk up).=20 Andy From newsfish@newsfish Thu Aug 1 00:29:31 2024 X-Received: by 10.58.7.134 with SMTP id j6mr22169377vea.29.1397512161635; Mon, 14 Apr 2014 14:49:21 -0700 (PDT) X-Received: by 10.50.73.69 with SMTP id j5mr493317igv.14.1397512161382; Mon, 14 Apr 2014 14:49:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cm18no3011862qab.0!news-out.google.com!en3ni100igc.0!nntp.google.com!ur14no8172545igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Apr 2014 14:49:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a04ce67-9ec8-4797-85ef-0087683897e0@googlegroups.com> Subject: Re: Design toplevel module as schematic? From: Dio Gratia Injection-Date: Mon, 14 Apr 2014 21:49:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5507 X-Received-Body-CRC: 3812630094 Xref: news.eternal-september.org comp.lang.vhdl:2997 On Monday, April 14, 2014 7:46:40 PM UTC+12, Tobias Baumann wrote: > Hi everybody, >=20 >=20 >=20 > the question above has been come up between a colleague and me. Should=20 >=20 > the toplevel module be created as schematic plan or written as text in VH= DL? >=20 >=20 >=20 > I prefer the second one, my colleague the first. The only advantage I=20 >=20 > see for using schematic coding, is that I have a visual overview of my=20 >=20 > toplevel modul and I quickly can find which blocks are connected together= . >=20 >=20 >=20 > On the other side, the development process is much slower because of=20 >=20 > using the mouse instead of keyboard. I also think that using textfiles=20 >=20 > are much easier to handle for revision controlling software like git or s= vn. >=20 >=20 >=20 > Maybe someone can give me a few impressions how you handle the toplevel= =20 >=20 > module. Before I started my new job, we worked at CERN on very large=20 >=20 > designs with hundreds of moduls in a team with about 10 VHDL engineers.= =20 >=20 > We avoided to use graphical coding and this worked excellent, so I don't= =20 >=20 > see any reason, why to change this. >=20 >=20 >=20 > Thanks a lot, >=20 > Tobias I once wrote a chip design methodology for implementing ASICs at a large co= rporation. If you look at a chip design process (not that different for an FPGA and an= ASIC) a design specification provides another level of abstraction view of= a design and in general is a superset after implementation of what would g= o in a data sheet. =20 You progress from the most abstract representation to the most detailed (st= ructural based on primitives) implementation. At some point your design sp= ecification is updated with pin numbers and other implementation details. A design specification is intended to represent agreement between all inter= ested parties what is intended to be (and when updated what is actually) bu= ilt. It should contain all the necessary information to interact with the t= arget device at a system or software level. Whether or not there are pictu= res in it (e.g. detailed block diagrams) can be based on whether or not a p= ictorial representation conveys more information than it occludes. Historically the purpose of providing detailed top level information would = be to show drive strengths and areas of buffers, allow annular rings to be = determined and provide a basis along with a gate count for determining die = size, leading to bonding diagrams. All that sort of goes away in FPGAs, wh= ere necessary information is generally not kept in VHDL source files, rathe= r part of a design database dependent on a particular vendor's implementati= on methodology. A design specification can add a one stop shop method of l= ocating the information no matter the implementation method. We do design entry at the behavioral level of abstraction for portability w= hich is historically higher for VHDL than Verilog. Schematic entry is likel= y to prove useless for later incorporating a design specification into an A= SIC should volumes dictate. That level of structural detail requires repli= cation in any event. The only helpful thing might be a hierarchical abstra= ction where the top level does bidirectional to single rail break out. And= that also tends to define what's in a top level detailed block diagram. Note this is implementation detail while VHDL is design entry, optionally w= ith a structural view post synthesis. It's generally not necessary in an F= PGA design flow which provides the same information through other means. In= general you don't design to the structural level instead counting on synth= esis which uses a vendor's established methodology typically not including = a structural schematic top level. Now add to that that some of us have done large pin count chip designs wher= e no matter what you do a top level schematic showing all the pins - potent= ially buffer types, signal name switches and bidirectional to single rail c= onversions becomes nothing but a glorified net list. You could also note that the objective is to build hardware not win argumen= ts. If it likely means extra work for you it ought to be justified by the desig= n process deliverables and you could always argue schedule time. From newsfish@newsfish Thu Aug 1 00:29:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error Date: 15 Apr 2014 07:39:39 GMT Lines: 19 Message-ID: References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> X-Trace: individual.net qSXba9ps9n+quRLTxOn75QLDJp++yZFT9Rhu4WsERSGa3xstd2 X-Orig-Path: not-for-mail Cancel-Lock: sha1:ZhxzjbrESsBloXdI4rVbH8RjjzM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:2998 Hi Kevin, KJ wrote: [] > ...before both the package definition (where you have it now) AND > before the entity definition. Packages and entities are considered > 'primary design units'. Any libraries you want to include must be > listed prior to each one. The 'architecture' is considered a > 'secondary design unit' which does not need yet another round of > 'library ieee...' because it has been immediately preceded by the > primary design unit. I'm so used to have packages and entities in separate files that I guess I forgot about library and use clause scope! But now that we are at it, what is the reason behind such a language 'feature'? I like the idea that secondary units inherit primary units' libraries and use clauses, but scoping those only to the 'first primary unit in a file' seems quite...quirk. From newsfish@newsfish Thu Aug 1 00:29:32 2024 X-Received: by 10.50.43.228 with SMTP id z4mr838005igl.0.1397550138205; Tue, 15 Apr 2014 01:22:18 -0700 (PDT) X-Received: by 10.140.81.166 with SMTP id f35mr11271qgd.8.1397550138173; Tue, 15 Apr 2014 01:22:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no8335284igb.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no3103586qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Apr 2014 01:22:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL code error From: Thomas Stanka Injection-Date: Tue, 15 Apr 2014 08:22:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:2999 Am Dienstag, 15. April 2014 09:39:39 UTC+2 schrieb alb: > I forgot about library and use clause scope! But now that we are at it, > what is the reason behind such a language 'feature'? > > I like the idea that secondary units inherit primary units' libraries > and use clauses, but scoping those only to the 'first primary unit in a > file' seems quite...quirk. Assume your design contains two packages that define the type unsigned (first is the prefered one for your design, second due to IP-usage of bad designed IP). If every primary unit would inherit from all primaries above, you could compile the design if each primary is in an individual file, but not if you combine several primary units in one file. That would be real ....quirk. regards Thomas From newsfish@newsfish Thu Aug 1 00:29:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx27.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> In-Reply-To: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140414-1, 14/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 127 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397555145 86.29.12.221 (Tue, 15 Apr 2014 09:45:45 UTC) NNTP-Posting-Date: Tue, 15 Apr 2014 09:45:45 UTC Organization: virginmedia.com Date: Tue, 15 Apr 2014 10:45:43 +0100 X-Received-Body-CRC: 2829737313 X-Received-Bytes: 6718 Xref: news.eternal-september.org comp.lang.vhdl:3000 Hi Andy, On 14/04/2014 18:24, Andy wrote: > When in Rome, do as the Romans do. If your team is expecting a top level schematic, you'll probably have to give it to them, at least until you can demonstrate alternate means of giving them the "benefits" they currently think they get from a top level schematic. I can see a clear "benefit" if you have to explain your design to somebody not familiar with your design. > > I started out using schematics a long time ago. After initially resisting VHDL, I embraced it and would NEVER go back! The point is that you are not going back, tool and technology evolve and so have graphical design entry tools (although they are actually design entry and management tools to use the proper marketing term, graphics is only a small part of their capabilities). We are not talking about connecting AND/OR gate together, we are talking about parts of the design process which can benefit from schematics. > > I will not allow developers to use a schematic at any level to generate their RTL. Glad I am not working for you ;-) > Schematics generate the VHDL code that may "look pretty", but machine-generated VHDL is not maintainable (unless it can modify the schematic per RTL code changes), With modern design entry tools the sole aim is to generate perfect RTL, the output of the tool is VHDL/Verilog not schematics! The schematic is just a method to help you create your RTL. > so you have to maintain the schematic, No why? I often use my design entry tool to connect some blocks together, generate a testbench framework, or an FSM and then I continue in VHDL, this is quicker and less error prone then doing it manually. > which then raises some other questions that should be evaluated: > > Is the schematic tool freely distributable (not just the viewer)? AFAIK no, most viewers are. > Does the schematic provide for generate statements? Yes. > Does the schematic provide for top-level generics? Of course. > What about code comments? Real man don't use comments.... Clearly you have never looked at a modern (graphical) design entry tool. > > There are also techniques that can be used to simplify a purely structural VHDL architecture to provide some of the understandability of a WELL-CRAFTED schematic. Use more complex data types than SL & SLV to group related signals together (doues your schematic tool do that?) Yes, you can use records. > > By the time the user generates symbols for each underlying component/entity, and places them and connects them, naming each net, in a WELL CRAFTED schematic, they will have spent FAR more time than writing the code. Again, you should really have a look at a modern design entry tool. The symbols are generated automatically, connecting them can be done with a single mouse click. The funny thing is that I now find it very tedious to connect blocks manually, it is much quicker to let the tool do it for me. The same applies to FSM, if somebody doesn't like my n-process FSM, no problem a few mouse clicks and I have an m-process one. > I have yet to see a decent "beautifier" for schematics. yes, don't believe there are any, I have also never seen a tool that can create nice graphics from RTL no matter how expensive they are. > Plenty exist for VHDL. mmmmm, I wouldn't say plenty and the once I looked at all have issues. > > However, it takes a lot more than a beautifier to create human-understandable VHDL. Good coding standards, coding for function rather than netlist, etc. go a long way. I agree and for this reasons most design entry tools will give you a lot of options to generate the code you want, again these tools are designed to generate RTL not schematics. Some of the design entry tool also provide linting capabilities so you can check that your code is adhering to your coding standards. > > As previously noted, there are good tools for generating graphical documentation from RTL: Sigasi (my favorite), DVT-Eclipse, Understand (sci-tools) and many synthesis tools. If you like these tools then you will be amazed what a high-end purposely designed design entry tool can do for you. Unfortunately as I mentioned in my previous post you need a healthy EDA budget to purchase them. > > Displaying single-stepped simulation results on a schematic has got to be the worst excuse I have ever heard! That sounds like something a marketing manager would want to see (or a tool vendor would talk up). So when you use your simulator (assuming Modelsim) do you use the list window or do you look at the waveform window, perhaps the FSM window or dataflow window? If you look at simulator development over the years you will see more and more graphical windows. Mentor's Questa includes a schematic window similar to what you get from a synthesis tool. The point is that graphics may help you debug your code being it by back annotating your simulation results on a block diagram or even animation of your FSM (exists). I am not advocating people should use them, I would just say use whatever works for you. I can understand why somebody might be sceptical but to re-iterate my point, these are tools to help you design your RTL, they are not moving your design into some graphical tools domain from which there is no escape. The output is always nicely formatted, readable, editable RTL as that is what they are designed for. Now back to debugging my SystemC code with printf statements.... Regards, Hans. www.ht-lab.com > > Andy > From newsfish@newsfish Thu Aug 1 00:29:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 15 Apr 2014 10:14:29 GMT Lines: 20 Message-ID: References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> X-Trace: individual.net Ag9ATyPVK+0VPW46vRi2Qg4ZcJXpEMcflYpCN7fNA2lBFRraJp X-Orig-Path: not-for-mail Cancel-Lock: sha1:nAF+108SXrQcw2qUraEop19UapY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3001 Andy wrote: > As previously noted, there are good tools for generating graphical > documentation from RTL: Sigasi (my favorite), DVT-Eclipse, Understand > (sci-tools) and many synthesis tools. there's this interesting tool out there which does not convert vhdl to schematics but does the opposite [1]. Unfortunately the developers do not want to release the code, but among the 'enhancements' they list: - ability to import VHDL or Verilog code for viewing as block-diagram. I find the GUI pretty slick and straight forward but the tool is way too rudimental and it seg. faults quite too often to be usable. Last update of the project page is 2003... :-/ The tool is distributed free of charge. Al [1] http://www.atl.external.lmco.com/projects/rassp2/vgui/index.html From newsfish@newsfish Thu Aug 1 00:29:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: systemC and OSVVM Date: 15 Apr 2014 10:59:30 GMT Lines: 35 Message-ID: References: X-Trace: individual.net AOKDZOtR89PKMETPppATuAPWRB3kC4zeLR/kx3Vws6VEpXjp1p X-Orig-Path: not-for-mail Cancel-Lock: sha1:rH5hXK7RhB7qU9TXhXs5kz8avL4= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.arch.fpga:6777 comp.lang.vhdl:3002 My apologies, I should have really cross-posted this subthread to comp.lang.vhdl as well in the first place. alb wrote: > Hi Hans, > In comp.arch.fpga HT-Lab wrote: > [] >>> I'm considering the possibility to have my model written in SystemC >>> while the testbench written in vhdl, leveraging the benefits of the >>> OSVVM library. >> >> That is unusual, I suspect you are better off using SCV as you might hit >> some mix language interface issues (records are not always >> straightforward on a SC/VHDL interface, use simple structs on SC only). > > There are two motivations behind this choice: > > 1. our system engineer is willing to dig into systemC for architecture > exploration in the first place. We can profit of the model in order to > build our verification environment *soon* in the project. > > 2. our fpga guys are not so much willing to spend time in learning > systemC, while they could feel more confortable with the OSVVM since > they know already the language. > > The first point is a structural element that we are missing in our > design flow. Too often the architecture is based on not so well founded > choices and as the systems grow more complex, there's an increasing need > to get the architecture right at the very beginning. > > The second point is to enhance our current verification flow which is > too often lagging behind. There's an unreasonable perception that going > to the bench soon will reveal problems quicker. If we had a reference > model and a verification environment early in the project I believe we > can shift our mindset and spend less time in testing/debugging the > hardware. From newsfish@newsfish Thu Aug 1 00:29:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error Date: 15 Apr 2014 12:45:26 GMT Lines: 31 Message-ID: References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> X-Trace: individual.net rQY0kyr4Y0yW6xB2L1+P6geYEhpvAZ/QYbF9oUdIiIe5OuHq66 X-Orig-Path: not-for-mail Cancel-Lock: sha1:TkLNGvVC8HWf7pT4LsgvMJC8M68= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3003 Hi Thomas, Thomas Stanka wrote: [] >> I like the idea that secondary units inherit primary units' libraries >> and use clauses, but scoping those only to the 'first primary unit in a >> file' seems quite...quirk. > > Assume your design contains two packages that define the type unsigned > (first is the prefered one for your design, second due to IP-usage of > bad designed IP). > > If every primary unit would inherit from all primaries above, you > could compile the design if each primary is in an individual file, but > not if you combine several primary units in one file. That would be > real ....quirk. I have to assume the offending type definition is not on the entity's ports, otherwise you would need a wrapper around it in order to convert the two unsigned definitions from/to eachother. Now your primary unit has no indication that a different type defintion should be used instead, hiding the subtle /feature/ in its context clause. While I see how in your case a 'file scope' for context clause would not work, I only see troubles in combining primary units in such a case. I still see it as an overhead that for each primary unit I have to have a separate context all of which are most likely the same (library ieee; use ieee.std_logic_1164.all;). Al From newsfish@newsfish Thu Aug 1 00:29:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 15 Apr 2014 12:46:50 GMT Lines: 13 Message-ID: References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> X-Trace: individual.net yMLUvyNjhNTDSQtRZMsgCQCYufU1RRN9zXM9H6srMQGPrgq9Yw X-Orig-Path: not-for-mail Cancel-Lock: sha1:ktDj2EQYbAS6jXvT1JHVz+A4A2U= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3004 Hi Hans, HT-Lab wrote: [] > Now back to debugging my SystemC code with printf statements.... The greatest advantage of 'tracing' (debugging with printf) over other debugging techniques is that you are forced to *read* your code and understand it! We often brag about new tools and the power they have, simply forgetting old ones together with their values ;-) Al From newsfish@newsfish Thu Aug 1 00:29:34 2024 X-Received: by 10.236.188.134 with SMTP id a6mr1078998yhn.11.1397580631720; Tue, 15 Apr 2014 09:50:31 -0700 (PDT) X-Received: by 10.140.91.180 with SMTP id z49mr71255qgd.3.1397580631703; Tue, 15 Apr 2014 09:50:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cm18no3217917qab.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no3217907qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Apr 2014 09:50:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Design toplevel module as schematic? From: Andy Injection-Date: Tue, 15 Apr 2014 16:50:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3501 X-Received-Body-CRC: 1095105221 Xref: news.eternal-september.org comp.lang.vhdl:3005 Hans,=20 Which (single) Graphical Design Entry tool provides all these features you = mention?=20 Several years ago one of our sister sites was using a Mentor graphics tool = ("HDL Designer" or something like that?) but it was very primitive. I have = not looked at it lately... perhaps I should. I am always open to new ways o= f doing things, but only if they are actually better ways! Do you only use the tool as the initial entry for the VHDL, and then mainta= in the design at the vhdl level? If so, how good is that initial schematic = after you've made maintenance modifications to the VHDL? As Dio mentioned above, many organizations believe that a schematic represe= ntation of the top (few) structural level(s) of the design eliminates the n= eed for a Design Specification (including requirements, interface specifica= tions, block diagrams, design constraints etc.) before a single block is pl= aced on a schematic, or a single line of code is written.=20 Schematic diagrams tend to be too detailed to serve as an overview, yet not= detailed enough to dismiss with reviewing/augmenting the code itself, espe= cially if the code is maintained outside the graphical environement.=20 If, on the other hand, the design is always maintained at the graphical lev= el, then you have to keep that tool around for the life of the product (whi= ch, depending on your market, may be decades longer than the tool vendor in= tends to support the tool). If my favorite VHDL editor is no longer available or supported, I can seaml= essly bring the design up in a new editor. I can't tell you how many editor= s I have used over the decades I've been designing FPGAs in VHDL, and none = of them had any problem with even the oldest code I opened in them! I take = that back... a recent new-to-me editor (IDE) tried to tell me I had a bug f= or using a reserved PSL keyword in a non-PSL context. While most IDEs will not automatically generate an acceptable block/state d= iagram (visually unorganized), many will export that diagram in an editable= form (not pixels!) for augmenting documentation.=20 BTW, Who I will work for (or allow to work for me) also has a lot to do wit= h how bad I want my paycheck! Andy From newsfish@newsfish Thu Aug 1 00:29:34 2024 X-Received: by 10.236.109.169 with SMTP id s29mr1124268yhg.43.1397582012005; Tue, 15 Apr 2014 10:13:32 -0700 (PDT) X-Received: by 10.140.97.117 with SMTP id l108mr75999qge.1.1397582011659; Tue, 15 Apr 2014 10:13:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no8557234igb.0!news-out.google.com!en3ni100igc.0!nntp.google.com!ur14no8557231igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Apr 2014 10:13:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2fa9691c-650a-489f-9d0a-413b5ba265bf@googlegroups.com> Subject: Re: VHDL code error From: Andy Injection-Date: Tue, 15 Apr 2014 17:13:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3006 I have seen designs where each file contained a package, an entity and its architecture. The package contained a component declaration corresponding to the entity in that file. The instantiating architecture would use the packages associated with entities it will use, and the packages are guaranteed to be compiled if the entities are compiled. This is probably the cleanest way of keeping component declarations easily usable, yet in sync with their entities, that I have seen (if you have to use components at all.) Including, in the same file, a package with a component declaration that the architecture will/may instantiate (the OP's apparent use case) is less useful. Andy From newsfish@newsfish Thu Aug 1 00:29:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx22.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140415-1, 15/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 58 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397644691 86.29.12.221 (Wed, 16 Apr 2014 10:38:11 UTC) NNTP-Posting-Date: Wed, 16 Apr 2014 10:38:11 UTC Organization: virginmedia.com Date: Wed, 16 Apr 2014 11:38:08 +0100 X-Received-Body-CRC: 3587807789 X-Received-Bytes: 4397 Xref: news.eternal-september.org comp.lang.vhdl:3007 Hi Andy, On 15/04/2014 17:50, Andy wrote: > Hans, > > Which (single) Graphical Design Entry tool provides all these features you mention? > > Several years ago one of our sister sites was using a Mentor graphics tool ("HDL Designer" or something like that?) but it was very primitive. I have not looked at it lately... perhaps I should. I am always open to new ways of doing things, but only if they are actually better ways! Yes, that is the one I am using. Perhaps you looked at it in the old days when it was called Renoir. Nowadays it is a (massive) design entry and management tool, graphics is just a minor part of it. > > Do you only use the tool as the initial entry for the VHDL, and then maintain the design at the vhdl level? I do both, I sometimes use the tool to prototype the structure/testbench and other times I stay within the tool for the duration of the project. I only use graphics for the top level (unless I have lots of components at a lower level), testbench and FSM's. > If so, how good is that initial schematic after you've made maintenance modifications to the VHDL? Unfortunately you can't, you can only have one master (you can however easily switch between a VHDL and schematic version for the same module). > > As Dio mentioned above, many organizations believe that a schematic representation of the top (few) structural level(s) of the design eliminates the need for a Design Specification (including requirements, interface specifications, block diagrams, design constraints etc.) before a single block is placed on a schematic, or a single line of code is written. > Schematic diagrams tend to be too detailed to serve as an overview, yet not detailed enough to dismiss with reviewing/augmenting the code itself, especially if the code is maintained outside the graphical environement. > > If, on the other hand, the design is always maintained at the graphical level, then you have to keep that tool around for the life of the product (which, depending on your market, may be decades longer than the tool vendor intends to support the tool). I agree it is never a good idea to have a design locked to a particular tool although nowadays this is becoming increasingly difficult. But this is not an issue with HDL Designer as the output is always a set of RTL files. > > If my favorite VHDL editor is no longer available or supported, I can seamlessly bring the design up in a new editor. I can't tell you how many editors I have used over the decades I've been designing FPGAs in VHDL, and none of them had any problem with even the oldest code I opened in them! I take that back... a recent new-to-me editor (IDE) tried to tell me I had a bug for using a reserved PSL keyword in a non-PSL context. Same here, my current favourite is notepad++. > > While most IDEs will not automatically generate an acceptable block/state diagram (visually unorganized), many will export that diagram in an editable form (not pixels!) for augmenting documentation. > > BTW, Who I will work for (or allow to work for me) also has a lot to do with how bad I want my paycheck! I understand, Regards, Hans. www.ht-lab.com > > Andy > From newsfish@newsfish Thu Aug 1 00:29:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 17 Apr 2014 03:54:09 -0500 Date: Thu, 17 Apr 2014 09:54:05 +0100 From: MK User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 37 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-J3hp5doHKgg7wHZHUo8GTFag4fpnVyarLSgdTuF4TRf3Y2Q9XtA1WcOD0SYNmvl/kjJZh7qzg57ZLQD!fjwxJwaYgKQ3/0vlJHTiEjZtzNMAJ4ubBgfNyVsn4rj4TD8HUe2TBz2QOdmsuo/Hvz4hF9mnuY/t X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2838 Xref: news.eternal-september.org comp.lang.vhdl:3008 On 14/04/2014 08:46, Tobias Baumann wrote: > Hi everybody, > > the question above has been come up between a colleague and me. Should > the toplevel module be created as schematic plan or written as text in > VHDL? > > I prefer the second one, my colleague the first. The only advantage I > see for using schematic coding, is that I have a visual overview of my > toplevel modul and I quickly can find which blocks are connected together. > > On the other side, the development process is much slower because of > using the mouse instead of keyboard. I also think that using textfiles > are much easier to handle for revision controlling software like git or > svn. > > Maybe someone can give me a few impressions how you handle the toplevel > module. Before I started my new job, we worked at CERN on very large > designs with hundreds of moduls in a team with about 10 VHDL engineers. > We avoided to use graphical coding and this worked excellent, so I don't > see any reason, why to change this. > > Thanks a lot, > Tobias I always use Aldec-HDL's schematic editor for the top level of any VHDL project - it generates perfectly readable VHDL and saves reams of tedious error prone typing, as well as providing a much more understandable high level view of the project. Most of my clients don't use VHDL so showing them 20 pages of top level net-list-like VHDL conveys absolutely nothing. A nice block diagram representation is understood by a far wider audience. Because the top level block diagram is the top level master I know it is up to date and accurate - unlike stuff in note books or other non-linked documents. Michael Kellett From newsfish@newsfish Thu Aug 1 00:29:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Fri, 18 Apr 2014 14:02:50 -0400 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Apr 2014 18:02:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="22013"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX197j5uBfuTSGsytXIgsNIth" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:E5DVokBxmaL51owqflFTRlYGMgc= Xref: news.eternal-september.org comp.lang.vhdl:3009 On 4/14/2014 7:05 AM, Tobias Baumann wrote: > Am 14.04.2014 10:56, schrieb alb: >> Text is written to be read while a schematic is drawn to be looked at. >> Without going to far in perception psicology, we often overestimate >> visual representation. > > I think that too, but there's the problem. Today the project leader came > and wanted to see the schematic of my toplevel. So he made some trouble, > because he as a none FPGA designer (but with experience in designing > ASICs) wants to see a schmeatic to understand. Me as developer want to > produce results, so I use textfile. If someone wants a schematic, I draw > on a sheet of paper. The discussion ends up with "everybody uses > schematic coding for the toplevel and it's silly to use VHDL for the > toplevel". I really doubt this statement, so I started this discussion > to see how others handle the toplevel. I work for myself so I have no boss over me to impose restrictions. But I can "see" a lot better than I can read through all the minutiae of a text file. A picture is worth a kiloword. Still, I never use a top level diagram for HDL. But I do draw a diagram as part of the documentation... sometimes. I used a tool many years ago that represented the requirements decomposition graphically. In the grand scheme of things it didn't work out but mostly because we had no idea how to decompose requirements rather than any limitation of the tool. However I never saw any advantage to the tool either. Manipulating the information graphically was some extra work I think and I never saw much return in the way of verification or other checking our work. :( > I use Sigasi, which is perfect for me. It helps me to get quickly > through a design. But even editors with VHDL highlighting are enough. It > depends a bit on the quality of the source code. Just like your boss is used to diagrams, code bangers are used to text tools. That is preference rather than advantage I think. >> If you do not see any reason, why don't you ask what are the reasons to >> your colleague instead. It may simply be "tradition" and then you can >> simply forget all your reasonings. > > The argument is, that it is standard for ASICs, so it has to be standard > for FPGAs. But I think the real reason is: He wanted to see a schematic > and becasue I have none he created an argument which fits his needs. What? Since when is a top level diagram standard for ASICs? I'd be willing to bet just the opposite is true. ASICs are nearly *all* HDL with no diagrams. -- Rick From newsfish@newsfish Thu Aug 1 00:29:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx26.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140418-0, 18/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 23 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397848536 86.29.12.221 (Fri, 18 Apr 2014 19:15:36 UTC) NNTP-Posting-Date: Fri, 18 Apr 2014 19:15:36 UTC Organization: virginmedia.com Date: Fri, 18 Apr 2014 20:15:32 +0100 X-Received-Body-CRC: 782650341 X-Received-Bytes: 1720 Xref: news.eternal-september.org comp.lang.vhdl:3010 On 18/04/2014 19:02, rickman wrote: .. >> >> The argument is, that it is standard for ASICs, so it has to be standard >> for FPGAs. But I think the real reason is: He wanted to see a schematic >> and becasue I have none he created an argument which fits his needs. > > What? Since when is a top level diagram standard for ASICs? I'd be > willing to bet just the opposite is true. ASICs are nearly *all* HDL > with no diagrams. > I also question that, however, look at some of the comments from an relative old 2004 DeepChip postings: http://www.deepchip.com/items/dac03-07.html looks like graphics are used, Regards, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:29:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Sat, 19 Apr 2014 03:16:40 -0400 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 19 Apr 2014 07:16:19 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="25369"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+GNj49aSd19kwiYNBWMN0q" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:gIrbbxzBSu3IqEOFH7zBniLxXLE= Xref: news.eternal-september.org comp.lang.vhdl:3011 On 4/18/2014 3:15 PM, HT-Lab wrote: > On 18/04/2014 19:02, rickman wrote: > .. >>> >>> The argument is, that it is standard for ASICs, so it has to be standard >>> for FPGAs. But I think the real reason is: He wanted to see a schematic >>> and becasue I have none he created an argument which fits his needs. >> >> What? Since when is a top level diagram standard for ASICs? I'd be >> willing to bet just the opposite is true. ASICs are nearly *all* HDL >> with no diagrams. >> > > I also question that, however, look at some of the comments from an > relative old 2004 DeepChip postings: > > http://www.deepchip.com/items/dac03-07.html > > looks like graphics are used, I don't follow. There are a lot of comments and many were negative regarding the schematic capture. Further, it is not clear which of these are used for FPGA and which are used for ASICs. I see no evidence that drawing schematics is "standard" for designing ASICs. -- Rick From newsfish@newsfish Thu Aug 1 00:29:36 2024 X-Received: by 10.236.181.74 with SMTP id k50mr12032511yhm.46.1397935151643; Sat, 19 Apr 2014 12:19:11 -0700 (PDT) X-Received: by 10.140.95.112 with SMTP id h103mr321702qge.4.1397935151625; Sat, 19 Apr 2014 12:19:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cm18no4366643qab.0!news-out.google.com!dz10ni13939qab.1!nntp.google.com!m5no3374410qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 19 Apr 2014 12:19:11 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.185.0.95; posting-account=ThB-RgoAAACC9oQPd2YxYqTJwmumn6xz NNTP-Posting-Host: 24.185.0.95 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL Synchronizer Function From: genogiapasetti@gmail.com Injection-Date: Sat, 19 Apr 2014 19:19:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1731 X-Received-Body-CRC: 1173287018 Xref: news.eternal-september.org comp.lang.vhdl:3012 Is there a way to write a VHDL synchronizer function that could be called from a section of sequential code as: if sync(clock, a) = '1' then... where "a" is a signal from another clock domain and "clock" is the clock in the present domain? I've tried function sync(clock, in: std_logic) return std_logic is variable med, result: std_logic; begin if clock'event and clock = '1' then med := input; result := med; end if; return result; end sync; The result in the Xilinx simulator is syntactically accepted but is always undefined, no matter how many variations of the above I tried. Is there a technique which preserves the convenience of my approach but works? Geno From newsfish@newsfish Thu Aug 1 00:29:36 2024 X-Received: by 10.67.5.165 with SMTP id cn5mr16121353pad.9.1397941239039; Sat, 19 Apr 2014 14:00:39 -0700 (PDT) X-Received: by 10.50.29.110 with SMTP id j14mr278660igh.5.1397941238688; Sat, 19 Apr 2014 14:00:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no724110igq.0!news-out.google.com!gi6ni537igc.0!nntp.google.com!c1no724108igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 19 Apr 2014 14:00:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5d470a0f-4784-4d2d-8145-a394aaee786b@googlegroups.com> Subject: Re: VHDL Synchronizer Function From: Dio Gratia Injection-Date: Sat, 19 Apr 2014 21:00:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3013 On Sunday, April 20, 2014 7:19:11 AM UTC+12, genogia...@gmail.com wrote: > Is there a way to write a VHDL synchronizer function that could be called= from a section of sequential code as: >=20 >=20 >=20 > if sync(clock, a) =3D '1' then... >=20 >=20 >=20 > where "a" is a signal from another clock domain and "clock" is the clock = in the present domain? >=20 >=20 >=20 > I've tried >=20 >=20 >=20 > function sync(clock, in: std_logic) return std_logic is >=20 > variable med, result: std_logic; >=20 > begin >=20 > if clock'event and clock =3D '1' then >=20 > med :=3D input; >=20 > result :=3D med; >=20 > end if; >=20 > return result; >=20 > end sync; >=20 >=20 >=20 >=20 >=20 > The result in the Xilinx simulator is syntactically accepted but is alway= s undefined, no matter how many variations of the above I tried. >=20 >=20 >=20 > Is there a technique which preserves the convenience of my approach but w= orks? >=20 >=20 >=20 > Geno Local variables in a function are created new each function call. Also not= e your sequential assignments of med and result don't imply a clock delay b= etween them the value of med is updated immediately. While your simulation= might work it doesn't synchronize. You could try a procedure: library ieee; use ieee.std_logic_1164.all; entity foo is end entity; architecture fum of foo is procedure sync ( signal clk: in std_logic; signal a: in std_logic; signal med: inout std_logic; signal result: inout std_logic ) is begin if clk'event and clk =3D '1' then med <=3D a; result <=3D med; end if; end ; =20 signal a: std_logic; signal clk: std_logic :=3D '0'; signal med: std_logic; signal result: std_logic; begin SYNCHRO: sync (clk,a,med,result); EVALUATE: process (result) begin if result =3D '1' then =20 end if; end process; end architecture; Notice this is the equivalent of using a sync component because a procedure= doesn't have a return value, with various restrictions on using signals in= a procedure effectively limiting this to one level of hierarchy. You might as well create a sync component and use and output signal name th= at's descriptive (e.g. a_sync). From newsfish@newsfish Thu Aug 1 00:29:36 2024 X-Received: by 10.182.254.10 with SMTP id ae10mr17318403obd.43.1398025626940; Sun, 20 Apr 2014 13:27:06 -0700 (PDT) X-Received: by 10.50.176.227 with SMTP id cl3mr419965igc.11.1398025626805; Sun, 20 Apr 2014 13:27:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!c1no1231949igq.0!news-out.google.com!gi6ni537igc.0!nntp.google.com!c1no1231948igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 20 Apr 2014 13:27:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL Synchronizer Function From: Dio Gratia Injection-Date: Sun, 20 Apr 2014 20:27:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3014 You could note in your function, besides the formal 'in' in 'clock, in:' be= ing illegal (appears to have been intended to be 'clock, input:'), the form= al 'clock' hasn't been declared as class signal, meaning as class variable = (the default) the expression 'clock'event' is illegal and should result in = an error. From newsfish@newsfish Thu Aug 1 00:29:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error Date: 22 Apr 2014 07:56:36 GMT Lines: 24 Message-ID: References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> <2fa9691c-650a-489f-9d0a-413b5ba265bf@googlegroups.com> X-Trace: individual.net gKq1/xF/x4c2fD8hxWR8MwHR0ZGpeVOWMeCIkGy/wnStD5Jpju X-Orig-Path: not-for-mail Cancel-Lock: sha1:hrLjhdVMg2M/ll+J15/sjfvsEKs= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3015 Hi Andy, Andy wrote: > I have seen designs where each file contained a package, an entity and > its architecture. The package contained a component declaration > corresponding to the entity in that file. > > The instantiating architecture would use the packages associated with > entities it will use, and the packages are guaranteed to be compiled > if the entities are compiled. the main drawback is that you end up with a package for each component, which is less useful as a package in the end. A possibility maybe is to define a 'context' (vhdl-2008) and maintain the list of packages in there. > This is probably the cleanest way of keeping component declarations > easily usable, yet in sync with their entities, that I have seen (if > you have to use components at all.) Another would be to generate a package with component declarations automatically from a list of entities. Emacs has keybindings to copy an entity declaration and paste it as a component, maybe with a little bit of lisp would be possible to generate an entire package with all necessary components in the same way. From newsfish@newsfish Thu Aug 1 00:29:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!backlog4.nntp.dca3.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 22 Apr 2014 03:31:56 -0500 From: rahnahnf Subject: interpolation Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 7d5ec473-520d-4a2b-812b-9c81385a79cd Message-ID: Date: Tue, 22 Apr 2014 03:31:56 -0500 Lines: 4 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-dlwIzbafPNWhcRurUtZr76Jl8JOozGHtNk5ytj+3epBVGTPWNZ9UZ5yudm7jBID8EAevmb0rLr6FjEG!RR9BHtr3PoqYUhSr9lW99VjhzV4ybQm4fqINNrbzc6s3KPKNvApX7D1cqZaXYceWYjwtUs9S27v/!yw== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1045 Xref: news.eternal-september.org comp.lang.vhdl:3016 hi, I need to code the interp2 function in Verilog.anybody have any idea about it? From newsfish@newsfish Thu Aug 1 00:29:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: interpolation Date: 22 Apr 2014 09:37:30 GMT Lines: 8 Message-ID: References: X-Trace: individual.net 26m8NQwKQUzi2EgCo8W9vAYIeHOzqF+ECiM+yqNdwxeI4jJUoA X-Orig-Path: not-for-mail Cancel-Lock: sha1:08zO6H1hXT3vxGgtW1pLsV7BWUU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3017 rahnahnf wrote: > I need to code the interp2 function in Verilog.anybody have any idea > about it? what about asking in the appropriate group? I give you a hint: it ends with 'verilog'. Al From newsfish@newsfish Thu Aug 1 00:29:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx24.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140422-0, 22/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 37 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1398179175 86.29.12.221 (Tue, 22 Apr 2014 15:06:15 UTC) NNTP-Posting-Date: Tue, 22 Apr 2014 15:06:15 UTC Organization: virginmedia.com Date: Tue, 22 Apr 2014 16:06:12 +0100 X-Received-Body-CRC: 980653641 X-Received-Bytes: 2331 Xref: news.eternal-september.org comp.lang.vhdl:3018 On 19/04/2014 08:16, rickman wrote: > On 4/18/2014 3:15 PM, HT-Lab wrote: >> On 18/04/2014 19:02, rickman wrote: >> .. >>>> >>>> The argument is, that it is standard for ASICs, so it has to be >>>> standard >>>> for FPGAs. But I think the real reason is: He wanted to see a schematic >>>> and becasue I have none he created an argument which fits his needs. >>> >>> What? Since when is a top level diagram standard for ASICs? I'd be >>> willing to bet just the opposite is true. ASICs are nearly *all* HDL >>> with no diagrams. >>> >> >> I also question that, however, look at some of the comments from an >> relative old 2004 DeepChip postings: >> >> http://www.deepchip.com/items/dac03-07.html >> >> looks like graphics are used, > > I don't follow. There are a lot of comments and many were negative > regarding the schematic capture. Further, it is not clear which of > these are used for FPGA and which are used for ASICs. > > I see no evidence that drawing schematics is "standard" for designing > ASICs. > That was not the point, I agree that schematics are not standard in the ASIC world, the link was to counter your *all* argument. Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:29:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!rt.uk.eu.org!border4.nntp.ams.giganews.com!backlog4.nntp.ams.giganews.com!border2.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 22 Apr 2014 15:35:19 -0500 Date: Tue, 22 Apr 2014 21:35:19 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <0fOdnQoSvqIaT8vOnZ2dnUVZ8tednZ2d@brightview.co.uk> Lines: 35 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-2JRgKTUhAQjWxfd2XA5gc5bcpjNTexxYd0mtNtQ7KMyjDBkFPgHyzyisMRdfeXE1TNw8NYDYjm2+yDo!2DDjGI9GEsj+hjQxRelp2hky1gFTU7XJk1d0wibbCCIyxldhv4/EqWUujJXACrha2IhLBPZ9K9Zx!6T3lLoqlyqTYKlPBDbIlCyz/ZN0= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2580 Xref: news.eternal-september.org comp.lang.vhdl:3019 On 15/04/14 08:39, alb wrote: > Hi Kevin, > > KJ wrote: > [] >> ...before both the package definition (where you have it now) AND >> before the entity definition. Packages and entities are considered >> 'primary design units'. Any libraries you want to include must be >> listed prior to each one. The 'architecture' is considered a >> 'secondary design unit' which does not need yet another round of >> 'library ieee...' because it has been immediately preceded by the >> primary design unit. > > I'm so used to have packages and entities in separate files that I guess > I forgot about library and use clause scope! But now that we are at it, > what is the reason behind such a language 'feature'? > > I like the idea that secondary units inherit primary units' libraries > and use clauses, but scoping those only to the 'first primary unit in a > file' seems quite...quirk. > I think one answer is (as Microsoft always say in their knowledge base) "this behaviour is by design". I suspect the main reason is to minimise the compilation dependencies for efficiency reasons. In the early days of VHDL, I suspect that compilation time was significant while on modern computers it is not such a problem. regards Alan -- Alan Fitch From newsfish@newsfish Thu Aug 1 00:29:39 2024 X-Received: by 10.182.128.166 with SMTP id np6mr8465115obb.16.1398206888314; Tue, 22 Apr 2014 15:48:08 -0700 (PDT) X-Received: by 10.140.44.75 with SMTP id f69mr108720qga.11.1398206888281; Tue, 22 Apr 2014 15:48:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no9674355iga.0!news-out.google.com!du2ni14151qab.0!nntp.google.com!m5no4228397qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Apr 2014 15:48:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> <2fa9691c-650a-489f-9d0a-413b5ba265bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <57292bfb-6fd1-43f0-8a07-8a65d2cf52d7@googlegroups.com> Subject: Re: VHDL code error From: Andy Injection-Date: Tue, 22 Apr 2014 22:48:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3020 On Tuesday, April 22, 2014 2:56:36 AM UTC-5, alb wrote: > the main drawback is that you end up with a package for each component, w= hich is less useful as a package in the end.=20 Using a package that declares the component, even if it is only one compone= nt, is much easier than repeating (and maintaining!) the component declarat= ion in every architecture that instantiates it. Also, with one package per component declaration, the list of packages used= by a given architecture will be fairly small (only for those components in= stantiated in that architecture.) It also gives the reader a heads-up regar= ding which components are instantiated in the file. If either a common package containing all componentes is used, or a common = context using all the packages is employed, then anytime any one of the pac= kages/components is updated (perhaps due to its corresponding entity being = updated), everything has to be recompiled.=20 On the other hand, compilers (and the computers they run on) have gotten pr= etty fast these days, especially compared to when VHDL was first introduced= (1987)! Andy From newsfish@newsfish Thu Aug 1 00:29:39 2024 X-Received: by 10.236.39.99 with SMTP id c63mr25854222yhb.31.1398289771436; Wed, 23 Apr 2014 14:49:31 -0700 (PDT) X-Received: by 10.182.97.195 with SMTP id ec3mr88485obb.30.1398289771265; Wed, 23 Apr 2014 14:49:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!cm18no5805293qab.0!news-out.google.com!en3ni276igc.0!nntp.google.com!c1no2820385igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 Apr 2014 14:49:31 -0700 (PDT) In-Reply-To: <48ee3cb5$0$6577$9b4e6d93@newsspool4.arcor-online.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.228.40.15; posting-account=Eve5lQoAAADdQ5XZCrU9ZCEsz1ivMYnI NNTP-Posting-Host: 41.228.40.15 References: <48ee3cb5$0$6577$9b4e6d93@newsspool4.arcor-online.net> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2f1b6829-ce57-44bd-a520-3a6d5bb73dd2@googlegroups.com> Subject: Re: Virtex-5 clocking From: salahc4@gmail.com Injection-Date: Wed, 23 Apr 2014 21:49:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3021 Le jeudi 9 octobre 2008 18:18:30 UTC+1, Saul Bernstein a =E9crit=A0: > Hi Folks, >=20 >=20 >=20 > altough brand new I hope someone already made some experience with Virtex= -5.=20 > I just switched from Virtex-4 to Virtex-5 and I must admit that the clock= =20 > managment is... and remains... somewhat unclear to me! >=20 > It's plain to see that the clock management is handled a bit differently= =20 > than Virtex-4. Virtex-5 clocking uses both DCM (digital clock managers)= =20 > technology for delay control and PLL (phased lock loop) technology for lo= wer=20 > jitter clock generation. But what does that mean to me, practically? What= =20 > should I account for when designing a PCB with Virtex-5? Which IOs am I= =20 > supposed to use? >=20 > In Virtex-4 I had Global Clock and Regional Clock Inputs. So far so good.= In=20 > Virtex-5 I have plenty of different clock inputs and it is almost impossi= ble=20 > to arrange for an optimal clock management at the time prior to developin= g=20 > the internal VHDL logic for the FPGA. Basically I'd like to know how to= =20 > connect my global clock sources to the FPGA without catching problems lat= er=20 > in implementing the VHDL and getting confronted with timing errors, etc. >=20 > Same problem - still much worse - with the RocketIO reference clocks! Ple= nty=20 > of clock inputs but. much too confusing! For example I'd like to take one= =20 > reference clock for an arrangement of 10 RocketIOs. No problem with=20 > Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5 for th= e=20 > clocks can only supply 4 RocketIOs at once... as far as I can judge. >=20 >=20 >=20 > Still, I may be wrong! So any help is highly appreciated. >=20 >=20 >=20 > Saul From newsfish@newsfish Thu Aug 1 00:29:39 2024 X-Received: by 10.58.88.136 with SMTP id bg8mr29959006veb.21.1398290010050; Wed, 23 Apr 2014 14:53:30 -0700 (PDT) X-Received: by 10.182.158.167 with SMTP id wv7mr208838obb.29.1398290009673; Wed, 23 Apr 2014 14:53:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m5no4808789qaj.1!news-out.google.com!gi6ni613igc.0!nntp.google.com!l13no10241653iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 Apr 2014 14:53:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.228.40.15; posting-account=Eve5lQoAAADdQ5XZCrU9ZCEsz1ivMYnI NNTP-Posting-Host: 41.228.40.15 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: conv N/A _ with_Virtex5 From: Salah Kortli Injection-Date: Wed, 23 Apr 2014 21:53:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1393 X-Received-Body-CRC: 3301471314 Xref: news.eternal-september.org comp.lang.vhdl:3022 Hello world I just use a low frequency sinusoidal signals, the frequency range of alternative reports will be about 2 Hz. I want to clock the FPGA to manage the reports. I think I need to reduce or divide the frequency of the clock signals to 2 Hz to 1MHz. Then comes the use of Digital / Analog converter DAC. Is it possible to go down to values mHz. Will he links, tutorials, etc ... that guides me to it. cordially From newsfish@newsfish Thu Aug 1 00:29:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Thu, 24 Apr 2014 11:50:52 +0300 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Apr 2014 08:50:57 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4109"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CAQzoGZvIL8iIEt1WspFdAHfqonnWcKw=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:ezZPTw9ts/oerPYxc2DryK+/Ulg= Xref: news.eternal-september.org comp.lang.vhdl:3023 > I also prefer schematics. If you take 2 groups of engineers and you show > an FSM bubble diagram to the first group and a few pages of RTL to the > second, which one do you think will understand the circuit the quickest? I wonder how many people confuse top-level structure from the FSM (behavioural diagram). Might be your tools can generate nice VHDL out of Abstract State Machines. And What it has to do with the question? From newsfish@newsfish Thu Aug 1 00:29:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 24 Apr 2014 09:10:45 GMT Lines: 13 Message-ID: References: X-Trace: individual.net /FFydqM2tiJxYkon3LZ9GAs52j8Nwo5IXSPy5THipYq34UEWzA X-Orig-Path: not-for-mail Cancel-Lock: sha1:y5U7lSiOFRZB4wfwwEEhf05uUZU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3024 Hi valtih1978, valtih1978 wrote: >> I also prefer schematics. If you take 2 groups of engineers and you show >> an FSM bubble diagram to the first group and a few pages of RTL to the >> second, which one do you think will understand the circuit the quickest? > > I wonder how many people confuse top-level structure from the FSM > (behavioural diagram). Might be your tools can generate nice VHDL out of > Abstract State Machines. And What it has to do with the question? To some extent, Hans's point is about conveying information through a graphical mean rather than a listing and have the two means synchronized. IMHO his point of view is not OT. From newsfish@newsfish Thu Aug 1 00:29:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Thu, 24 Apr 2014 15:46:44 +0300 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Apr 2014 12:46:49 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="24272"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19cYM3VfAe05GpFyvm45pk9Aq05wsBPdWg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:080+9iW55LnAqSiXMwJaAzS8R+A= Xref: news.eternal-september.org comp.lang.vhdl:3025 I like to explain students that representation is more structural at the higher levels of abstraction. It is because you start design at the top level. You refine the design by implementing the components (defining their structure). At the bottom level you have the gates. As VHDL designer you know that components do not have the structure at the bottom level. You describe the elementary components by behavioral processes. Now, you understand that the top level is necessarily has known structure. Might be this intuition is taken too far by some bigots but the big picture of the World seems to be really useful in any case. From newsfish@newsfish Thu Aug 1 00:29:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Separate elaboration and parsing Date: Thu, 24 Apr 2014 15:48:39 +0300 Organization: A noiseless patient Spider Lines: 14 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Apr 2014 12:48:43 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="24272"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/w38ntwIDdfa3Uw51yyXlUR0YS0VILdPg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 Cancel-Lock: sha1:hbtV9dFCndGEXfrz7wLGYmX5fhI= Xref: news.eternal-september.org comp.lang.vhdl:3026 It seems that VHDL tools separate parsing from elaboration. However, it seems that some constructions are ambigous at syntax level. For instnance, http://cs.stackexchange.com/questions/24032, target <= prefix(argument) can be treated as either element <= composite_name(10) // selecting an element or int_target <= integer(1.1) // conversion How do the tools handle this case? How do they communicate to the elaborator whether elements should be addressed or conversion function instantiated? From newsfish@newsfish Thu Aug 1 00:29:41 2024 X-Received: by 10.68.180.132 with SMTP id do4mr1840470pbc.4.1398360113263; Thu, 24 Apr 2014 10:21:53 -0700 (PDT) X-Received: by 10.140.97.182 with SMTP id m51mr60079qge.12.1398360113199; Thu, 24 Apr 2014 10:21:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!backlog3.nntp.dca3.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!c1no3143668igq.0!news-out.google.com!dz10ni20896qab.1!nntp.google.com!m5no5038398qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Apr 2014 10:21:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Subject: Re: Separate elaboration and parsing From: KJ Injection-Date: Thu, 24 Apr 2014 17:21:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 37 X-Original-Bytes: 2318 Xref: news.eternal-september.org comp.lang.vhdl:3027 On Thursday, April 24, 2014 8:48:39 AM UTC-4, valtih1978 wrote: > It seems that VHDL tools separate parsing from elaboration. However, it= =20 >=20 > seems that some constructions are ambigous at syntax level. For=20 >=20 > instnance, http://cs.stackexchange.com/questions/24032, target <=3D=20 >=20 > prefix(argument) can be treated as either >=20 >=20 >=20 > element <=3D composite_name(10) // selecting an element >=20 >=20 >=20 > or >=20 >=20 >=20 > int_target <=3D integer(1.1) // conversion >=20 >=20 >=20 > How do the tools handle this case? How do they communicate to the=20 >=20 > elaborator whether elements should be addressed or conversion function=20 >=20 > instantiated? They don't communicate. When the names 'composite_name' and 'integer' come= across, that name must have already been defined. If they are not defined= , you get an error saying that 'composite_name' is unrecognized. If they a= re defined but you are using them incorrectly (for example by passing in an= integer argument to something that is expecting a real) then you will get = an error pointing out what you're doing wrong. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Separate elaboration and parsing Date: Fri, 25 Apr 2014 08:10:12 +0300 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Apr 2014 05:10:16 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4557"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+81ayynIEydQwADUGFvCn9esYLpkf9tmc=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Cancel-Lock: sha1:RSeNiSKyZnbBZLk++Pe+HEWIxo0= Xref: news.eternal-september.org comp.lang.vhdl:3028 On 24.04.2014 20:21, KJ wrote: > They don't communicate. When the names 'composite_name' and > 'integer' come across, that name must have already been defined. If > they are not defined, you get an error saying that 'composite_name' > is unrecognized. If they are defined but you are using them > incorrectly (for example by passing in an integer argument to > something that is expecting a real) then you will get an error > pointing out what you're doing wrong. You basically say that parser does the elaboration (if "The process by which a declaration achieves its effect is called the elaboration of the declaration" is not elaboration then what is elaboration?) for the purpose of mantaining the list of defined objects and, thereby, is not related with elaboration. Try once more. That statement as it is is pure nonsense. From newsfish@newsfish Thu Aug 1 00:29:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!backlog3.nntp.dca3.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 25 Apr 2014 01:29:27 -0500 From: Joe Chisolm Subject: Re: Separate elaboration and parsing Newsgroups: comp.lang.vhdl References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 25 Apr 2014 01:29:27 -0500 Lines: 41 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.195.192.194 X-Trace: sv3-F1CrvK0Ty5pm6rQiA3fi1CcVhGndbazlK/WBxm4zAlYaI5SlvP7D1iEz/r8+xKAc7TbWn+/TQ8tGDQN!8xgVv8wJwwwIwS1fz6yh5ymxyMqC74whjmssBv+voHo5T7uHHr+/Ey+em365fRYoVrQVInSYYTVr!pIXtlPxHtD/svvDHAPEx5qKgMvxuFBPbu6xh X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2857 Xref: news.eternal-september.org comp.lang.vhdl:3029 On Fri, 25 Apr 2014 08:10:12 +0300, valtih1978 wrote: > On 24.04.2014 20:21, KJ wrote: >> They don't communicate. When the names 'composite_name' and 'integer' >> come across, that name must have already been defined. If they are not >> defined, you get an error saying that 'composite_name' is unrecognized. >> If they are defined but you are using them incorrectly (for example by >> passing in an integer argument to something that is expecting a real) >> then you will get an error pointing out what you're doing wrong. > > You basically say that parser does the elaboration (if "The process by > which a declaration achieves its effect is called the elaboration of the > declaration" is not elaboration then what is elaboration?) for the > purpose of mantaining the list of defined objects and, thereby, is not > related with elaboration. Try once more. That statement as it is is pure > nonsense. Kevin is correct and does not need to try once more. The parser will have resolved any ambiguity or will have issued an error. The elaboration has all the necessary information to elaborate the definition (in your phraseology). To keep the syntax similar consider the following FORTRAN code I=C(10) Is "C" a function or array? Or consider IF(IF(10).NE.0) GOTO JAIL And yes, that is legal FORTRAN code (actually it could be IF(IF(10).NE.0)GOTOJAIL). How does the compiler know what "IF" is? The lexer/parser does not know from the BNF. It has to resolve the issue by dealing with the symbol table and then building the correct node or whatever AST type structure you are using. -- Chisolm Republic of Texas From newsfish@newsfish Thu Aug 1 00:29:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Separate elaboration and parsing Date: Fri, 25 Apr 2014 13:37:57 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Apr 2014 10:38:02 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="6622"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX189b8lMS9UcWdl0ej+1Cu/wyj8JH9SuYYU=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:c6ysqjOaZHhXOMmjaOlqQSkSDYA= Xref: news.eternal-september.org comp.lang.vhdl:3030 Why Fortran? Do you know that meaning of the symbol depends on the scope? So, how many tables do you need in VHDL? Do you mean that there is a difference between elaborating the definitions and building all those tables? From newsfish@newsfish Thu Aug 1 00:29:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Separate elaboration and parsing Date: Fri, 25 Apr 2014 15:43:58 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Apr 2014 12:44:03 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="18212"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19IZItDGfB2z6ReYmX8Y/htgdkLwmoPaZk=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:4uH0aOex5rnqqz+mXQ6rfE2F1wQ= Xref: news.eternal-september.org comp.lang.vhdl:3031 Particularly, parser works at per-file basis. Yet, file may refer objects defined in another file (package), which parser have no idea of. Only elaborator is aware of their nature. How do you build your symbol table without elaborating the design? From newsfish@newsfish Thu Aug 1 00:29:43 2024 X-Received: by 10.58.94.232 with SMTP id df8mr4519177veb.23.1398437439089; Fri, 25 Apr 2014 07:50:39 -0700 (PDT) X-Received: by 10.140.51.137 with SMTP id u9mr15222qga.34.1398437439048; Fri, 25 Apr 2014 07:50:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m5no5259036qaj.1!news-out.google.com!du2ni15315qab.0!nntp.google.com!cm18no6256446qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Apr 2014 07:50:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <99c938f7-cbd9-4ff2-b697-20e584e042b1@googlegroups.com> Subject: Re: Separate elaboration and parsing From: KJ Injection-Date: Fri, 25 Apr 2014 14:50:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3032 On Friday, April 25, 2014 8:43:58 AM UTC-4, valtih1978 wrote: > Particularly, parser works at per-file basis. Yet, file may refer > > objects defined in another file (package), which parser have no idea of. > "which parser have no idea of"...That is not correct > Only elaborator is aware of their nature. How do you build your symbol > > table without elaborating the design? - In one word 'library'. - In two questions to guide the reader to the solution 'Where do you think the output of parsing the file ends up?' and 'What do you think then happens with that output?' Hint: The 'one word' will help you on both questions. I would be more helpful, but your misstating what I did say and then your statement to me "That statement as it is is (sic) pure nonsense" when in fact it is correct leads me to make you do some work for yourself. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!backlog4.nntp.dca3.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 25 Apr 2014 12:36:51 -0500 From: Joe Chisolm Subject: Re: Separate elaboration and parsing Newsgroups: comp.lang.vhdl References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 25 Apr 2014 12:36:51 -0500 Lines: 31 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.195.192.194 X-Trace: sv3-pRRVPS9V4V04KnaCi+tDNyXG1YlDXI7Kef5vK8iseQJlpM1E/8SclfVfczk7OhwxYL1sCq4zosDsUYu!/XWl5kLWe5KnSmhz1ii+iAHRX7NZDg589V2q0u63KLjLeF6XAk8MPtxMMOLZ7m1c+DOobki8ytjv!YUrVhzOZZ4MEjxJ/UTVmmjFDCvkAhhlkjtvP X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2434 Xref: news.eternal-september.org comp.lang.vhdl:3033 On Fri, 25 Apr 2014 15:43:58 +0300, valtih1978 wrote: > Particularly, parser works at per-file basis. Yet, file may refer > objects defined in another file (package), which parser have no idea of. > Only elaborator is aware of their nature. How do you build your symbol > table without elaborating the design? Because parsing the language and actually running a sim (or building a final bit stream to program a device) are separate task. The parser takes the language and creates "object code". The "object code" is going to be in your work library or in some other library you "use". The LRM has some rules. The "object code" or other data in the library, has all the necessary information for references by other design units. I have no idea how Xilinx, Altera, or any of the other tools represent and save this data. Consider: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.my_widget_library_pkg.all; This is telling the parser where to find the definition of the symbol "to_integer" or perhaps "my_widget". Take a look at ghdl and see how they do it. -- Chisolm Republic of Texas From newsfish@newsfish Thu Aug 1 00:29:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Separate elaboration and parsing Date: Sat, 26 Apr 2014 09:22:12 +0300 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Apr 2014 06:22:18 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="10606"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Ce1897d5d1tSNugoS93wW7u+M934GNqM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:eRZk/DMlH3g9vuc1RbYX+m5G2dM= Xref: news.eternal-september.org comp.lang.vhdl:3034 > Because parsing the language and actually running a sim (or building > a final bit stream to program a device) are separate task. Thanks for even more nonsense. > The LRM has some rules. The "object code" or LRM says that there is analyzis stage and elaboration, which check the design semantics and bind the objects. Thanks for attributing all that activity to the parser and ignoring any analysis/elaboration that perform on top of it. Since I asked about the difference between parser and elaboration, it makes a great sense to silence any analysis/elaboration and lead astray to the higher level tasks. This should be really convincing. From newsfish@newsfish Thu Aug 1 00:29:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Sat, 26 Apr 2014 03:47:17 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Apr 2014 07:46:49 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="46945bb1625eab38aa80926eba1ef6d5"; logging-data="2324"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/wJ0PDQrEYZeOYM89bLA0C" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:vv+a35bPup+LwnVMAQXp7MNDkjo= Xref: news.eternal-september.org comp.lang.vhdl:3035 On 4/22/2014 11:06 AM, HT-Lab wrote: > On 19/04/2014 08:16, rickman wrote: >> On 4/18/2014 3:15 PM, HT-Lab wrote: >>> On 18/04/2014 19:02, rickman wrote: >>> .. >>>>> >>>>> The argument is, that it is standard for ASICs, so it has to be >>>>> standard >>>>> for FPGAs. But I think the real reason is: He wanted to see a >>>>> schematic >>>>> and becasue I have none he created an argument which fits his needs. >>>> >>>> What? Since when is a top level diagram standard for ASICs? I'd be >>>> willing to bet just the opposite is true. ASICs are nearly *all* HDL >>>> with no diagrams. >>>> >>> >>> I also question that, however, look at some of the comments from an >>> relative old 2004 DeepChip postings: >>> >>> http://www.deepchip.com/items/dac03-07.html >>> >>> looks like graphics are used, >> >> I don't follow. There are a lot of comments and many were negative >> regarding the schematic capture. Further, it is not clear which of >> these are used for FPGA and which are used for ASICs. >> >> I see no evidence that drawing schematics is "standard" for designing >> ASICs. >> > > That was not the point, I agree that schematics are not standard in the > ASIC world, the link was to counter your *all* argument. And that is why I say "nearly" all. :) -- Rick From newsfish@newsfish Thu Aug 1 00:29:44 2024 X-Received: by 10.236.85.131 with SMTP id u3mr6342075yhe.40.1398530323625; Sat, 26 Apr 2014 09:38:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cm18no6541676qab.0!news-out.google.com!dz10ni23331qab.1!nntp.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 26 Apr 2014 11:38:43 -0500 From: Joe Chisolm Subject: Re: Separate elaboration and parsing Newsgroups: comp.lang.vhdl References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) MIME-Version: 1.0 Message-ID: Date: Sat, 26 Apr 2014 11:38:43 -0500 Lines: 25 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.195.192.194 X-Trace: sv3-zIvUBmILdtUBYuXK1etqtF/bz7MKbNYSOEn5o6+4rh3JvkqSEAOfinGcR4cUnkAuxA6I4Q01tV8KXt+!2OWm60cNSPh3sM2K8anAINZ1A/mlEBuw1lpt+ijzDMh94N6oKX/RwnQWENF9dQfC2zOe1kcQoI4N!Z8+WTDqLLRPqej9L1ZL/PlMsB56CM8OXKKLa X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2349 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Received-Bytes: 2655 X-Received-Body-CRC: 1664181927 Xref: news.eternal-september.org comp.lang.vhdl:3036 On Sat, 26 Apr 2014 09:22:12 +0300, valtih1978 wrote: >> Because parsing the language and actually running a sim (or building a >> final bit stream to program a device) are separate task. > > Thanks for even more nonsense. > >> The LRM has some rules. The "object code" or > > LRM says that there is analyzis stage and elaboration, which check the > design semantics and bind the objects. Thanks for attributing all that > activity to the parser and ignoring any analysis/elaboration that > perform on top of it. Since I asked about the difference between parser > and elaboration, it makes a great sense to silence any > analysis/elaboration and lead astray to the higher level tasks. This > should be really convincing. You must be really fun to work with.... What Kevin and I were trying to *help* you with and explain is the way the major players in the industry do this with their tools. Unlike you, these people have had working tool sets for probably longer than you have been on this planet. Bye. I'm done with you. From newsfish@newsfish Thu Aug 1 00:29:44 2024 X-Received: by 10.43.139.66 with SMTP id iv2mr7315303icc.17.1398530771818; Sat, 26 Apr 2014 09:46:11 -0700 (PDT) X-Received: by 10.140.107.35 with SMTP id g32mr304007qgf.2.1398530771775; Sat, 26 Apr 2014 09:46:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no4029090igq.0!news-out.google.com!dz10ni23056qab.1!nntp.google.com!cm18no6543039qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 26 Apr 2014 09:46:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=189.122.242.230; posting-account=u_lMxwoAAAB6CFFgDwMyXRGKYCgzWgkH NNTP-Posting-Host: 189.122.242.230 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Cache Memory From: belchel01@gmail.com Injection-Date: Sat, 26 Apr 2014 16:46:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3037 Did u get it? Em quinta-feira, 1 de dezembro de 2011 18h46min38s UTC-2, rykardu escreveu: > I'm working on a processor model written in vhdl and I'm looking for a > > model for a cache memory written in vhdl. > > > > The architecture of an embedded cache microarchitectureproposed by > > Tannenbaum. This cache must be of type copy back, set associative > > using two sets (2-way), with 64 positions, each set with a capacity to > > store blocks of 4 words of 16 bits. > > > > When a memory read is requested, the cache controller must determine > > whether it is a success or a failure and if the block stored in the > > cache is valid. If a hit, the word address must be supplied to the > > processor. If one fails, the main memory to be accessed, the cache > > should be refreshed and the bit of validity must be activated before > > the word to be supplied to the processor. > > > > When a write memory is requested, the cache controller must > > immediately determine whether it is a success or a failure. If a hit, > > the cache should be updated with the new word. If one fails, the cache > > must be updated with the new block and then the new word must be > > written in the cache. > > > > The replacement policy chooses the set of blocks that used less often. > > Only blocks that have been modified to be written back to main > > memory. > > > > This will need to add a bit of modification, indicating that that > > block was changed while in cache. The cache control is done by the > > microprogram. The main memory to the processor in question is 4K words > > of 16 bits. > > > > So, some components i have built but other not (for copy back, > > data_buffer) etc. > > > > I read here to try the website (www.gaisler.com) but 404. > > > > tks From newsfish@newsfish Thu Aug 1 00:29:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.cs.hut.fi!newsfeed3.funet.fi!newsfeeds.funet.fi!news.utu.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Tue, 29 Apr 2014 16:22:08 +0300 Lines: 44 Message-ID: References: NNTP-Posting-Host: coffee.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1398777728 32624 2001:708:310:3430:213:21ff:fe1b:b396 (29 Apr 2014 13:22:08 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Tue, 29 Apr 2014 13:22:08 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:Hk0jB+8QItyA3nHCLZHXWL/0Yn4= Xref: news.eternal-september.org comp.lang.vhdl:3038 Tobias Baumann writes: > I prefer the second one, my colleague the first. The only advantage I > see for using schematic coding, is that I have a visual overview of my > toplevel modul and I quickly can find which blocks are connected > together. But that kind of overview is usually provided by synthesis tools, no? Quartus does, years ago when I used Precision it did it too. Can't remember off hand if other tools can do that. > Maybe someone can give me a few impressions how you handle the > toplevel module. Once upon a time a coworker created an automated tool to build the toplevel or in fact the whole hierarchy. It operated on a simple config file and some very simple rules for connecting signals. Basically if two modules on the same level had a matching input and output those would be connected together, otherwise the signal would be pushed up in the hierarchy. It was for Verilog though and the IP is owned by Ericsson so not available for general consuption. Too bad really. But automation over tedium is my first choice. These days, as Emacs can copy a VHDL entity and paste it as an instance and signals it's fairly obvious what I prefer as an Emacs user. I had to take a look at an old hybrid schematic / VHDL design recently which was done in MaxPlus and I thought it was a filthy mess and very difficult to figure out what connected where. Of course the readability of a schematic depends on whoever did the schematic. I guess you could obfuscate a VHDL toplevel too if you really wanted to. Some years ago I was in a company where they used I think HDL Designer. It at least generated reasonable VHDL from the visual representation so portability wasn't an issue. OTOH, the GUI drawing part was pretty awful. Autosave with no undo made for a pretty terrible experience. One false move and spend hours fixing the result... Related to this, I'd like to get the top level entity and FPGA pin list from the schematic automagically. I had the pin list part once upon a time and it was great. I wonder how common this is in schematic tools? Recently I wrote a few lines of Python to convert from some kind of pin info from PADS to Quartus pin assignments. Another time years ago some other Mentor schematic tool could produce a UCF file for Xilinx. Very handy as the FPGA in that project had over 1000 pins... From newsfish@newsfish Thu Aug 1 00:29:45 2024 X-Received: by 10.182.104.200 with SMTP id gg8mr368208obb.45.1398812745586; Tue, 29 Apr 2014 16:05:45 -0700 (PDT) X-Received: by 10.182.142.38 with SMTP id rt6mr6698obb.10.1398812745464; Tue, 29 Apr 2014 16:05:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no511734igb.0!news-out.google.com!en3ni366igc.0!nntp.google.com!uq10no511730igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Apr 2014 16:05:45 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.242.131.190; posting-account=z0BiiAoAAABd_vM40LOrWNyVczlX5yAG NNTP-Posting-Host: 24.242.131.190 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> Subject: code question From: sk3ptic@gmail.com Injection-Date: Tue, 29 Apr 2014 23:05:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3039 I want to implement a bitsplit entity but can't figure out how to get it to= work. Basically I get some input of NB_BITS_PER_CLK length and I want to b= e able to select any possible rotation of the bits. Example: Input : 010 Possible outputs depending on tap_sel: 010 100 001 Can also work if tap_sel is std_logic and every time it gets pulsed you get= a different bit arrangement. But this is streaming so it is about selectin= g the appropriate arrangement not doing x rotations. Below is what I came u= p with but sort of stuck. Help would be greatly appreciated entity capture_bitslip is generic ( NB_BITS_PER_CLK : integer :=3D 4 =20 ); port( clk : in std_logic; rst : in std_logic; tap_sel : in std_logic_vector(3 downto 0); -- 2**4 =3D 16 bits_in : in std_logic_vector(NB_BITS-1 downto 0); -- bit unaligned = comming in bits_out : out std_logic_vector(NB_BITS-1 downto 0) -- bit aligned go= ing out ); end capture_bitslip; ---------------------------------------------------------------------------= ---------- -- Architecture declaration ---------------------------------------------------------------------------= ---------- architecture Behavioral of capture_bitslip is ---------------------------------------------------------------------------= ---------- -- CONSTANTS ---------------------------------------------------------------------------= ---------- type register_tbl_type is array (0 to 15) of unsigned(NB_BITS_PER_CLK-1 dow= nto 0); ---------------------------------------------------------------------------= ---------- -- SIGNALS ---------------------------------------------------------------------------= ---------- signal delay_registers : register_tbl_type; signal data_out : std_logic_vector(NB_BITS_PER_CLK-1 downto 0); signal mux_ctrl : std_logic_vector(NB_BITS_PER_CLK-1 downto 0); --2= **5 =3D 32 --*************************************************************************= ********** begin --*************************************************************************= ********** --generate_pattern_table:=20 for X in 0 to NB_BITS_PER_CLK-1 generate pattern_table(X) <=3D unsigned(bit_in) ror X; end generate; bit_out <=3D pattern_table(tap_sel); From newsfish@newsfish Thu Aug 1 00:29:45 2024 X-Received: by 10.58.228.201 with SMTP id sk9mr403077vec.35.1398813144261; Tue, 29 Apr 2014 16:12:24 -0700 (PDT) X-Received: by 10.182.33.4 with SMTP id n4mr6017obi.9.1398813144147; Tue, 29 Apr 2014 16:12:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dc16no108971qab.0!news-out.google.com!en3ni366igc.0!nntp.google.com!uq10no512837igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Apr 2014 16:12:23 -0700 (PDT) In-Reply-To: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.242.131.190; posting-account=z0BiiAoAAABd_vM40LOrWNyVczlX5yAG NNTP-Posting-Host: 24.242.131.190 References: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: code question From: sk3ptic@gmail.com Injection-Date: Tue, 29 Apr 2014 23:12:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3040 ------------------------------------------------------------------------------------- -- Specified libraries ------------------------------------------------------------------------------------- library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------------- -- Entity declaration ------------------------------------------------------------------------------------- entity capture_bitslip is generic ( NB_BITS_PER_CLK : integer := 4 ); port( clk : in std_logic; rst : in std_logic; delay_sel : in std_logic_vector(3 downto 0); -- 2**4 = 16 bits_in : in std_logic_vector(NB_BITS_PER_CLK-1 downto 0); -- bit unaligned comming in bits_out : out std_logic_vector(NB_BITS_PER_CLK-1 downto 0) -- bit aligned going out ); end capture_bitslip; ------------------------------------------------------------------------------------- -- Architecture declaration ------------------------------------------------------------------------------------- architecture Behavioral of capture_bitslip is ------------------------------------------------------------------------------------- -- CONSTANTS ------------------------------------------------------------------------------------- type register_tbl_type is array (0 to 15) of unsigned(NB_BITS_PER_CLK-1 downto 0); ------------------------------------------------------------------------------------- -- SIGNALS ------------------------------------------------------------------------------------- signal delay_registers : register_tbl_type; --*********************************************************************************** begin --*********************************************************************************** generate_pattern_table: for X in 0 to NB_BITS_PER_CLK-1 generate delay_registers(X) <= unsigned(bits_in) ror X; end generate; bits_out <= delay_registers(delay_sel); From newsfish@newsfish Thu Aug 1 00:29:46 2024 X-Received: by 10.50.108.47 with SMTP id hh15mr475836igb.3.1398813561363; Tue, 29 Apr 2014 16:19:21 -0700 (PDT) X-Received: by 10.182.1.202 with SMTP id 10mr4891obo.31.1398813561229; Tue, 29 Apr 2014 16:19:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no514137igb.0!news-out.google.com!en3ni366igc.0!nntp.google.com!uq10no514132igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Apr 2014 16:19:20 -0700 (PDT) In-Reply-To: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.242.131.190; posting-account=z0BiiAoAAABd_vM40LOrWNyVczlX5yAG NNTP-Posting-Host: 24.242.131.190 References: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ee3c29c-34de-438b-8612-12ef14b933ad@googlegroups.com> Subject: Re: code question From: sk3ptic@gmail.com Injection-Date: Tue, 29 Apr 2014 23:19:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3041 Finally came up with this. Is this synthesizable and can anyone think of a better way to do it? generate_pattern_table: for X in 0 to NB_BITS_PER_CLK-1 generate delay_registers(X) <= unsigned(bits_in) ror X; end generate; data <= delay_registers(to_integer(unsigned(delay_sel))); bits_out <= std_logic_vector(data); From newsfish@newsfish Thu Aug 1 00:29:46 2024 X-Received: by 10.182.28.99 with SMTP id a3mr5476581obh.40.1398942743320; Thu, 01 May 2014 04:12:23 -0700 (PDT) X-Received: by 10.140.101.107 with SMTP id t98mr196796qge.5.1398942743251; Thu, 01 May 2014 04:12:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!l13no12469473iga.0!news-out.google.com!dz10ni27706qab.1!nntp.google.com!s7no314334qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 04:12:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.232.223.221; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 85.232.223.221 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Thu, 01 May 2014 11:12:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3042 Hi, I have managed to transmit some character (one after the other) using this code from; http://eewiki.net/pages/viewpage.action?pageId=4096096 I used continuous mode and I got the right characters on MOSI, one after the other, the only thing is that there are 4 clock cycles of high impedance between each 8-bit char. Is this oki? I am planning to interface with MAX1416 ADC. Also, I need to simulate an SPI input coming from the ADC. What is the best way to do it? Shall I use the same method I used for transmitting but this time in the test bench? I am using quartus and ModelSim. thanks From newsfish@newsfish Thu Aug 1 00:29:46 2024 X-Received: by 10.236.66.169 with SMTP id h29mr4855666yhd.34.1398943067377; Thu, 01 May 2014 04:17:47 -0700 (PDT) X-Received: by 10.140.50.83 with SMTP id r77mr46qga.15.1398943067191; Thu, 01 May 2014 04:17:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!backlog4.nntp.dca3.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!s7no314949qap.0!news-out.google.com!dz10ni27706qab.1!nntp.google.com!s7no314945qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 04:17:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.232.223.221; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 85.232.223.221 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <625d4289-c200-478b-9a34-76ff8d1dfb41@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Thu, 01 May 2014 11:17:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 X-Original-Bytes: 1222 Xref: news.eternal-september.org comp.lang.vhdl:3043 https://dl.dropboxusercontent.com/u/34708989/SPI_tx_test.bmp From newsfish@newsfish Thu Aug 1 00:29:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: SPI; simulating an input (rx) Date: Thu, 01 May 2014 09:10:55 -0400 Organization: Alacron, Inc. Lines: 32 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 1 May 2014 13:11:43 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="17959"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/XBF7SuJ/kNaFentJJwXK121AnFfNEev0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:WVN+A55T3JUfpyXCNLhHAwFZgKU= Xref: news.eternal-september.org comp.lang.vhdl:3044 Brandon Spiteri wrote: > Hi, > I have managed to transmit some character (one after the other) using this code from; > > http://eewiki.net/pages/viewpage.action?pageId=4096096 > > I used continuous mode and I got the right characters on MOSI, one after the other, the only thing is that there are 4 clock cycles of high impedance between each 8-bit char. Is this oki? > > I am planning to interface with MAX1416 ADC. > > > Also, I need to simulate an SPI input coming from the ADC. What is the best way to do it? > > Shall I use the same method I used for transmitting but this time in the test bench? > > I am using quartus and ModelSim. > > thanks From your screen-shot, it looks like the high-Z occurs when the receiver is not looking at the data, so it should be OK. On the other hand it might be a good idea to go through your code to see why that's happening. As for simulating data in the opposite direction, there's no reason you can't instantiate a synthesizable module from the testbench to provide stimulus. That assumes of course that the module behaves the way you expect the ADC to behave. Have checked whether Maxim (or whoever makes the ADC) has a simulation model? -- Gabor From newsfish@newsfish Thu Aug 1 00:29:47 2024 X-Received: by 10.236.39.99 with SMTP id c63mr5771284yhb.31.1398963310294; Thu, 01 May 2014 09:55:10 -0700 (PDT) X-Received: by 10.140.94.169 with SMTP id g38mr29508qge.13.1398963310232; Thu, 01 May 2014 09:55:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!s7no385026qap.0!news-out.google.com!du2ni19614qab.0!nntp.google.com!ih12no1422650qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 09:55:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.227.212.2; posting-account=VXDpvQoAAAB9FwBy5EHXKCikwLvVmTDX NNTP-Posting-Host: 88.227.212.2 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <179bb941-0582-42c6-9d53-e68c435b1c5f@googlegroups.com> Subject: Re: how create an 8 bit binary to BCD decoder? From: emirogluengin@gmail.com Injection-Date: Thu, 01 May 2014 16:55:10 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3045 15 May=C4=B1s 2002 =C3=87ar=C5=9Famba 23:07:03 UTC+3 tarihinde Christian ya= zd=C4=B1: > Hello! > I know this newsgroup is specially ybout VHDL. But I am curently working > with Altera's derivation AHDL. > My question isn't quite language related but more general: >=20 > How would you create a decoder which generates BCD-coding from normal 8bi= t > binary coding? > I want to control several 7 segment displays and therefore have to use BC= D > coding. >=20 > I'd be very happy to get any kind of help. > Regards > Chris. From newsfish@newsfish Thu Aug 1 00:29:47 2024 X-Received: by 10.50.136.198 with SMTP id qc6mr1851248igb.4.1398964754323; Thu, 01 May 2014 10:19:14 -0700 (PDT) X-Received: by 10.140.37.148 with SMTP id r20mr234116qgr.0.1398964754255; Thu, 01 May 2014 10:19:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!c1no212075igq.0!news-out.google.com!dz10ni27706qab.1!nntp.google.com!s7no390229qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 10:19:13 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.191.171.253; posting-account=x2hcxAoAAADSdaw31IXuu3z4q8DZR-f9 NNTP-Posting-Host: 2.191.171.253 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: instructor solution manual for Wireless Communications (Andrea Goldsmith) From: meyasm.masoudi@gmail.com Injection-Date: Thu, 01 May 2014 17:19:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3046 hi would you please tell me if you have solution for "wireless communication" by Andrea GoldSmith. From newsfish@newsfish Thu Aug 1 00:29:48 2024 X-Received: by 10.66.233.65 with SMTP id tu1mr6068230pac.35.1398964919535; Thu, 01 May 2014 10:21:59 -0700 (PDT) X-Received: by 10.140.95.112 with SMTP id h103mr231932qge.4.1398964919447; Thu, 01 May 2014 10:21:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!l13no12563420iga.0!news-out.google.com!dz10ni27706qab.1!nntp.google.com!s7no391218qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 10:21:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.191.163.181; posting-account=x2hcxAoAAADSdaw31IXuu3z4q8DZR-f9 NNTP-Posting-Host: 2.191.163.181 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7954a117-8f3b-4d25-8b8f-16ada31a1525@googlegroups.com> Subject: Re: instructor solution manual for Wireless Communications (Andrea Goldsmith) From: meyasm.masoudi@gmail.com Injection-Date: Thu, 01 May 2014 17:21:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3047 hi would you please tell me if you have solution for "wireless communication" by Andrea GoldSmith. From newsfish@newsfish Thu Aug 1 00:29:48 2024 X-Received: by 10.182.186.103 with SMTP id fj7mr13414220obc.9.1399154538788; Sat, 03 May 2014 15:02:18 -0700 (PDT) X-Received: by 10.140.50.83 with SMTP id r77mr1302qga.15.1399154538764; Sat, 03 May 2014 15:02:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no1089421igq.0!news-out.google.com!dz10ni30394qab.1!nntp.google.com!hw13no149173qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 May 2014 15:02:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.11.87.120; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 46.11.87.120 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <82185e7b-b9ef-45a1-b863-68b1d0751049@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Sat, 03 May 2014 22:02:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3048 > > > > From your screen-shot, it looks like the high-Z occurs when the receiver > > is not looking at the data, so it should be OK. On the other hand it > > might be a good idea to go through your code to see why that's > > happening. > > > > As for simulating data in the opposite direction, there's no reason you > > can't instantiate a synthesizable module from the testbench to provide > > stimulus. That assumes of course that the module behaves the way you > > expect the ADC to behave. Have checked whether Maxim (or whoever makes > > the ADC) has a simulation model? > > > > -- > > Gabor Thanks for your reply Gabor, I looked in the datasheet of the ADC but there wasn't much SPI waveforms to check with. Do you have any idea where can I look for a valid waveform example for MAX1416 please? From newsfish@newsfish Thu Aug 1 00:29:48 2024 X-Received: by 10.58.105.105 with SMTP id gl9mr12697759veb.17.1399155480317; Sat, 03 May 2014 15:18:00 -0700 (PDT) X-Received: by 10.182.220.232 with SMTP id pz8mr158657obc.13.1399155479938; Sat, 03 May 2014 15:17:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ih12no256349qab.1!news-out.google.com!gi6ni725igc.0!nntp.google.com!c1no1094917igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 May 2014 15:17:59 -0700 (PDT) In-Reply-To: <82185e7b-b9ef-45a1-b863-68b1d0751049@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <82185e7b-b9ef-45a1-b863-68b1d0751049@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <676744df-2796-4ae0-963f-932eb0ac857e@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: KJ Injection-Date: Sat, 03 May 2014 22:17:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1505 X-Received-Body-CRC: 3893919415 Xref: news.eternal-september.org comp.lang.vhdl:3049 On Saturday, May 3, 2014 6:02:18 PM UTC-4, Brandon Spiteri wrote: > Thanks for your reply Gabor, I looked in the datasheet of the ADC but there > wasn't much SPI waveforms to check with. Do you have any idea where can I look > for a valid waveform example for MAX1416 please? Datasheet, page 23 KJ From newsfish@newsfish Thu Aug 1 00:29:48 2024 X-Received: by 10.43.31.81 with SMTP id sf17mr14988452icb.4.1399288061289; Mon, 05 May 2014 04:07:41 -0700 (PDT) X-Received: by 10.140.51.70 with SMTP id t64mr17388qga.23.1399288061218; Mon, 05 May 2014 04:07:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!c1no1604806igq.0!news-out.google.com!dz10ni30394qab.1!nntp.google.com!hw13no445551qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 May 2014 04:07:40 -0700 (PDT) In-Reply-To: <8opbg4$gl7$1@news1.skynet.be> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.27.69.217; posting-account=66RXwAoAAAASPYbdczIbUgB22XjTHa0z NNTP-Posting-Host: 212.27.69.217 References: <8oilkh$g22$1@soap.pipex.net> <8opbg4$gl7$1@news1.skynet.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8020210a-f957-481c-8088-256effbcb73d@googlegroups.com> Subject: Re: VHDL Syntax Highlighting in MS Visual Studio From: markus.ferringer@gmail.com Injection-Date: Mon, 05 May 2014 11:07:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3050 I realize that this is a rather old thread, but it's still one of the first Google search results, so I think it's worth a note here. On www.vide-software.at (or directly from Visual Studio's Extension Manager) you can download an extension for Visual Studio. It offers syntax & semantic highlighting, code completion, code snippets, enhanced navigation features, etc. etc. It's free for students & teachers, there is a 30-day trial license, and there is a rather cheap private license for non-commercial use. Regards, Markus From newsfish@newsfish Thu Aug 1 00:29:49 2024 X-Received: by 10.236.123.68 with SMTP id u44mr696981yhh.19.1399373552148; Tue, 06 May 2014 03:52:32 -0700 (PDT) X-Received: by 10.182.200.163 with SMTP id jt3mr84229obc.25.1399373551755; Tue, 06 May 2014 03:52:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no686572qab.0!news-out.google.com!qf4ni19igc.0!nntp.google.com!c1no1987803igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 03:52:31 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.177.216.253; posting-account=V5rwAwoAAABbcDl8qd8AM9dp1Lh1besi NNTP-Posting-Host: 122.177.216.253 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> Subject: FFT CALCULATION USING DISTRIBUTIVE ALGORITHM. From: ajit yadav Injection-Date: Tue, 06 May 2014 10:52:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1644 X-Received-Body-CRC: 4019351138 Xref: news.eternal-september.org comp.lang.vhdl:3051 Fast Fourier transform(FFT) is used in digital spectral analysis, filter si= mulations, autocorrelation and pattern recognition applications. The FFT is= based on decomposition and breaking the transform into smaller transforms = and combining them to get the total transform. The FFT reduces the computat= ion time required to compute a discrete Fourier transform and thus improves= speed of computation. The speed of computation can be further enhanced by = the use of distributive Arithmetic (DA) method. DA method is very efficient= in terms of speed and accuracy. pLEASE HELP ME TO WRITE FPGA CODE From newsfish@newsfish Thu Aug 1 00:29:49 2024 X-Received: by 10.236.209.97 with SMTP id r61mr751717yho.33.1399373582047; Tue, 06 May 2014 03:53:02 -0700 (PDT) X-Received: by 10.182.72.228 with SMTP id g4mr265361obv.14.1399373581844; Tue, 06 May 2014 03:53:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no686709qab.0!news-out.google.com!qf4ni19igc.0!nntp.google.com!c1no1987891igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 03:53:01 -0700 (PDT) In-Reply-To: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.177.216.253; posting-account=V5rwAwoAAABbcDl8qd8AM9dp1Lh1besi NNTP-Posting-Host: 122.177.216.253 References: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66413fd0-e4b8-4912-bd14-e101e687c2db@googlegroups.com> Subject: Re: FFT CALCULATION USING DISTRIBUTIVE ALGORITHM. From: ajit yadav Injection-Date: Tue, 06 May 2014 10:53:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1904 X-Received-Body-CRC: 2049408777 Xref: news.eternal-september.org comp.lang.vhdl:3052 On Tuesday, May 6, 2014 4:22:31 PM UTC+5:30, ajit yadav wrote: > Fast Fourier transform(FFT) is used in digital spectral analysis, filter = simulations, autocorrelation and pattern recognition applications. The FFT = is based on decomposition and breaking the transform into smaller transform= s and combining them to get the total transform. The FFT reduces the comput= ation time required to compute a discrete Fourier transform and thus improv= es speed of computation. The speed of computation can be further enhanced b= y the use of distributive Arithmetic (DA) method. DA method is very efficie= nt in terms of speed and accuracy. pLEASE HELP ME WRITE VHDL CODE >=20 >=20 >=20 > pLEASE HELP ME TO WRITE FPGA CODE From newsfish@newsfish Thu Aug 1 00:29:49 2024 X-Received: by 10.50.43.228 with SMTP id z4mr1166525igl.0.1399383682678; Tue, 06 May 2014 06:41:22 -0700 (PDT) X-Received: by 10.140.101.147 with SMTP id u19mr139192qge.10.1399383682650; Tue, 06 May 2014 06:41:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no2055352igq.0!news-out.google.com!dz10ni33449qab.1!nntp.google.com!ih12no836810qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 06:41:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.83; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.83 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: erreur VHDL From: Ayoub Injection-Date: Tue, 06 May 2014 13:41:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3053 Hello! In fact,i have a small problem but I don't understand what I should do here is my code: library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_signed .all ; entity M is port( clk : in std_logic ; rst : in std_logic ; data : in std_ulogic_vector(1 downto 0); CD : in std_logic_vector(3 downto 0); s : out std_logic_vector (1 downto 0)); end entity ; architecture beh of M is signal com :std_logic_vector(3 downto 0); begin code :process(clk,rst) begin if (rst='1') then (others=>'0')<=data; --data<='0' !!! ; (others=>'0')<=CD; --"0000"<=CD ; s <=(others=>'0'); else for i in 0 to 3 loop if (clk'event and clk='1')then --for i in 0 to 3 loop com(i)<= not(CD(i) xor data) ; end if ; end loop ; end if ; end process ; s<=com(i) ; end architecture ; This is my problem : """Error (10476): VHDL error at M.vhd(38): type of identifier "data" does not agree with its usage as "std_ulogic" type""" Thanks in advanced. From newsfish@newsfish Thu Aug 1 00:29:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: erreur VHDL Date: Tue, 06 May 2014 16:44:52 +0200 Organization: A noiseless patient Spider Lines: 7 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 6 May 2014 14:44:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="30411"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18x7evCHuQD+lbEJV+PLItL" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: Cancel-Lock: sha1:MwQC3MzC0yEyyIz1r0uKzYSIbLY= Xref: news.eternal-september.org comp.lang.vhdl:3054 Am 06.05.2014 15:41, schrieb Ayoub: > com(i)<= not(CD(i) xor data) ; Check this line. What type/size has data and compare it with type/size of CD(i). Tobias From newsfish@newsfish Thu Aug 1 00:29:50 2024 X-Received: by 10.182.213.5 with SMTP id no5mr1297069obc.15.1399388526100; Tue, 06 May 2014 08:02:06 -0700 (PDT) X-Received: by 10.140.109.203 with SMTP id l69mr13152qgf.32.1399388526034; Tue, 06 May 2014 08:02:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!r10no1173357igi.0!news-out.google.com!dz10ni33449qab.1!nntp.google.com!ih12no862914qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 08:02:05 -0700 (PDT) In-Reply-To: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5280f381-ab42-4338-924f-3bdb221c32b3@googlegroups.com> Subject: Re: FFT CALCULATION USING DISTRIBUTIVE ALGORITHM. From: KJ Injection-Date: Tue, 06 May 2014 15:02:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3055 On Tuesday, May 6, 2014 6:52:31 AM UTC-4, ajit yadav wrote: > Fast Fourier transform(FFT) is used in digital spectral analysis, filter > pLEASE HELP ME TO WRITE FPGA CODE 1. Post your code so somebody can help. 2. If you have no code, then you should write some and start debugging. When you run across a problem, then go back to step 1. KJ From newsfish@newsfish Thu Aug 1 00:29:50 2024 X-Received: by 10.58.22.166 with SMTP id e6mr1370312vef.6.1399388757267; Tue, 06 May 2014 08:05:57 -0700 (PDT) X-Received: by 10.140.49.234 with SMTP id q97mr53655qga.22.1399388757187; Tue, 06 May 2014 08:05:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no760889qab.0!news-out.google.com!dz10ni33449qab.1!nntp.google.com!ih12no863871qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 08:05:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <41caf9be-1f3d-4e40-9f50-3c3da0bd02a5@googlegroups.com> Subject: Re: erreur VHDL From: KJ Injection-Date: Tue, 06 May 2014 15:05:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3056 On Tuesday, May 6, 2014 9:41:22 AM UTC-4, Ayoub wrote: > com(i)<= not(CD(i) xor data) ; should be com(i)<= not(CD(i) xor std_logic_vector(data)) ; Or compile the file using VHDL-2008 syntax. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!nntp.giganews.com!news.osn.de!diablo2.news.osn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: erreur VHDL Date: Tue, 06 May 2014 17:53:28 +0200 Lines: 95 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net z3MvLpw+IHKWvKmzoHHDFAtQ494riJW6JNEByjcnTqeame4SkH Cancel-Lock: sha1:FdOWKHQyWXS/yHi04zjKHp0F7PY= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:3057 Hi Ayoub, Ayoub wrote: > Hello! > > In fact,i have a small problem but I don't understand what I should do there's a few problems that should cause compilation errors, not only one. > here is my code: > > library ieee ; > use ieee.std_logic_1164.all ; > use ieee.std_logic_signed .all ; Get used to never using ieee.std_logic_signed.all. Use ieee.numeric_std.all instead and use the signed/unsigned types as needed. > > entity M is > port( > clk : in std_logic ; > rst : in std_logic ; > data : in std_ulogic_vector(1 downto 0); > CD : in std_logic_vector(3 downto 0); > s : out std_logic_vector (1 downto 0)); > > end entity ; > > architecture beh of M is > > signal com :std_logic_vector(3 downto 0); > > begin > > code :process(clk,rst) > > begin > > if (rst='1') then > (others=>'0')<=data; This line should cause an error, too. Delete it, it doesn't make sense. (others=>'0') is not a signal you can assign something to. > --data<='0' !!! ; > (others=>'0')<=CD; See above. It looks like you're trying to clear "data" and "CD" here in reset. You cannot do that, since both "data" and "CD" are inputs to your entity, meaning they are generated OUTSIDE of your module; hence you have no way of influencing their values. If you want to clear them, you need to do that in another module that connects to yours or a testbench that instantiates this module and drives its inputs. > --"0000"<=CD ; > s <=(others=>'0'); > else > for i in 0 to 3 loop > > if (clk'event and clk='1')then ... the "for" loop should be outside the clock condition. Otherwise you'd basically have 4 clock conditions. Not sure what simulation and synthesis tools would do with that. It's legal VHDL, but makes no sense in practice. > > --for i in 0 to 3 loop > > com(i)<= not(CD(i) xor data) ; > > end if ; > end loop ; > > end if ; > end process ; > s<=com(i) ; There's another bunch of problems here... - You have two sources for signal "s". It is assigned inside your process and outside of it. When you synthesize this, you'll probably get a "multiple drivers" error. - You use the i-index that is only known inside the process. - com(i) is of length 1, s is of length 2, so the assignment won't work here, anyway... Same applies to "com(i)<= not(CD(i) xor data) ;". Data is of length 2, so you can't xor it with a single bit. I'm surprised the first thing your simulation tool finds is the problem in line 38... I don't know what you are trying to do, so I can't tell you what to do exactly, but first I suggest you get a book on VHDL or read up on the web. You seem to lack basic understanding of the language constructs... HTH, Sean From newsfish@newsfish Thu Aug 1 00:29:51 2024 X-Received: by 10.66.254.101 with SMTP id ah5mr2107442pad.8.1399407095367; Tue, 06 May 2014 13:11:35 -0700 (PDT) X-Received: by 10.140.95.112 with SMTP id h103mr773109qge.4.1399407095281; Tue, 06 May 2014 13:11:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.glorb.com!r10no1302413igi.0!news-out.google.com!dz10ni33693qab.1!nntp.google.com!hw13no861102qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 13:11:35 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.193.64.121; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 46.193.64.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9e163e2c-b05c-4cae-aa4e-14644b9d7765@googlegroups.com> Subject: erreur VHDL 2 From: Ayoub Injection-Date: Tue, 06 May 2014 20:11:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3058 Hi My friends ! there is an option to attach file ?! because I would like to attache the design for more detail but I can't do it !! anybody help me please !! Thank you very much From newsfish@newsfish Thu Aug 1 00:29:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: erreur VHDL 2 Date: 7 May 2014 15:18:26 GMT Lines: 21 Message-ID: References: <9e163e2c-b05c-4cae-aa4e-14644b9d7765@googlegroups.com> X-Trace: individual.net g4KEIi3+hv8S8UVjAx8FigcDuw9lmN62kabAT+pWvmMAy9emP1 X-Orig-Path: not-for-mail Cancel-Lock: sha1:Qpx9Q62WBs1mvld7KB2XVr35Y9I= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3059 Hi Ayoub, In article <9e163e2c-b05c-4cae-aa4e-14644b9d7765@googlegroups.com> you wrote: [] > there is an option to attach file ?! try http://pastebin.com/ You'll get a link you can paste here. There are other websites like that, google is your friend. > because I would like to attache the design for more detail but I can't > do it !! even if most of us are 'friendly' people, I will never open a file from a stranger (and IMHO you shouldn't either). > anybody help me please !! check your keyboard, I guess your exclamation mark key is stuck ;-) HTH, Al From newsfish@newsfish Thu Aug 1 00:29:51 2024 X-Received: by 10.43.67.67 with SMTP id xt3mr4315956icb.23.1399642738669; Fri, 09 May 2014 06:38:58 -0700 (PDT) X-Received: by 10.140.107.35 with SMTP id g32mr215821qgf.2.1399642738638; Fri, 09 May 2014 06:38:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no3656758igq.0!news-out.google.com!dz10ni36309qab.1!nntp.google.com!hw13no1784920qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 May 2014 06:38:58 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Fri, 09 May 2014 13:38:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3060 This cropped up today while writing a testbench. Please look at the followi= ng code - it manages a linked list: type queue is protected procedure add_data(a : unsigned); procedure get_data(a : out unsigned); end protected queue; =20 =20 type queue is protected body type link_t; type link_ptr_t is access link_t; =20 type link_t is record data : unsigned; next_link : link_ptr_t; end record link_t; =20 variable start_of_list : link_ptr_t; =20 procedure add_data(a : unsigned) is variable ptr : link_ptr_t :=3D null; begin ptr :=3D new link_t'( (a, start_of_list) ); start_of_list :=3D ptr; end procedure add_data; =20 =20 procedure get_data(a : out unsigned) is variable ptr : link_ptr_t :=3D null; begin a :=3D start_of_list.data; =20 ptr :=3D start_of_list.next_link; DEALLOCATE(start_of_list); =20 start_of_list :=3D ptr; end procedure get_data; =20 end protected body queue; Ideally, the get_data procedure would actually be a function (as I have don= e in the past) but as the data field in the link_t is unconstrained in the = type, I cannot create a temporary variable to place the data into before re= turning it from the function, as I dont know the length of the data field b= efore pulling it out of the list.=20 Would the above be the best way of doing it, or can some others of you work= out a way a function would work instead? From newsfish@newsfish Thu Aug 1 00:29:52 2024 X-Received: by 10.50.108.47 with SMTP id hh15mr2387202igb.3.1399647465449; Fri, 09 May 2014 07:57:45 -0700 (PDT) X-Received: by 10.182.221.225 with SMTP id qh1mr62037obc.1.1399647465007; Fri, 09 May 2014 07:57:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!c1no3688984igq.0!news-out.google.com!gi6ni790igc.0!nntp.google.com!c1no3688978igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 May 2014 07:57:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: KJ Injection-Date: Fri, 09 May 2014 14:57:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3061 On Friday, May 9, 2014 9:38:58 AM UTC-4, Tricky wrote: > This cropped up today while writing a testbench. Please look at the follo= wing >=20 > Ideally, the get_data procedure would actually be a function (as I have d= one=20 > in the past) but as the data field in the link_t is unconstrained in the= =20 > type, I cannot create a temporary variable to place the data into before= =20 > returning it from the function, as I dont know the length of the data fie= ld=20 > before pulling it out of the list.=20 Actually you do know the length of the data field, it is start_of_list.data= 'length >=20 > Would the above be the best way of doing it, or can some others of you wo= rk=20 > out a way a function would work instead? Below is a function that should be equivalent to your procedure. It compil= es and accomplishes your goal of having a function, but whether it actually= works or not I didn't test. I kind of have my doubts since the 'data' element of your record is not con= strained it's not immediately obvious where you're allocating space for the= actual data element when you go to 'put' the data. I'm guessing that alth= ough it compiles, neither your procedure nor my function will actually run.= But in any case, I believe that what I have posted for the function is th= e equivalent to your procedure. Kevin Jennings impure function get_data2 return unsigned is variable ptr : link_ptr_t :=3D null;=20 variable a: unsigned(start_of_list.data'range); begin=20 a :=3D start_of_list.data;=20 =20 ptr :=3D start_of_list.next_link;=20 DEALLOCATE(start_of_list);=20 =20 start_of_list :=3D ptr;=20 return(a); end function get_data2; From newsfish@newsfish Thu Aug 1 00:29:52 2024 X-Received: by 10.66.252.198 with SMTP id zu6mr2796433pac.25.1399650600056; Fri, 09 May 2014 08:50:00 -0700 (PDT) X-Received: by 10.140.51.231 with SMTP id u94mr19612qga.34.1399650600009; Fri, 09 May 2014 08:50:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no2427178igi.0!news-out.google.com!dz10ni36309qab.1!nntp.google.com!hw13no1819310qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 May 2014 08:49:59 -0700 (PDT) In-Reply-To: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Fri, 09 May 2014 15:50:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3062 This is fine, but if the start_of_list is null, you will get an error from = a null pointer access. In the real code I have a record type instead of just an unsigned. If the s= tart_of_list is null it returns a NULL version of the record type I have as= a constant. I actually worked around the problem by creating a pointer to = the record type, pulling the data off the linked list into the pointer, the= n returning the de-referenced data: impure function get_packet return packet_info_t is variable ptr : packet_ll_ptr_t :=3D null; variable ret : packet_info_ptr_t :=3D null; begin if end_of_list =3D null then=20 ret :=3D new packet_info_t'(NULL_PACKET); =20 else ptr :=3D end_of_list.next_packet; ret :=3D new packet_info_t'( ptr.pi ); =20 DEALLOCATE(end_of_list); end_of_list :=3D ptr; =20 end if; =20 return ret.all; end function get_packet; On Friday, 9 May 2014 15:57:44 UTC+1, KJ wrote: > On Friday, May 9, 2014 9:38:58 AM UTC-4, Tricky wrote: >=20 > > This cropped up today while writing a testbench. Please look at the fol= lowing >=20 >=20 > > Ideally, the get_data procedure would actually be a function (as I have= done=20 >=20 > > in the past) but as the data field in the link_t is unconstrained in th= e=20 >=20 > > type, I cannot create a temporary variable to place the data into befor= e=20 >=20 > > returning it from the function, as I dont know the length of the data f= ield=20 >=20 > > before pulling it out of the list.=20 >=20 >=20 >=20 > Actually you do know the length of the data field, it is start_of_list.da= ta'length >=20 >=20 >=20 > >=20 >=20 > > Would the above be the best way of doing it, or can some others of you = work=20 >=20 > > out a way a function would work instead? >=20 >=20 >=20 > Below is a function that should be equivalent to your procedure. It comp= iles and accomplishes your goal of having a function, but whether it actual= ly works or not I didn't test. >=20 >=20 >=20 > I kind of have my doubts since the 'data' element of your record is not c= onstrained it's not immediately obvious where you're allocating space for t= he actual data element when you go to 'put' the data. I'm guessing that al= though it compiles, neither your procedure nor my function will actually ru= n. But in any case, I believe that what I have posted for the function is = the equivalent to your procedure. >=20 >=20 >=20 > Kevin Jennings >=20 >=20 >=20 > impure function get_data2 return unsigned is >=20 > variable ptr : link_ptr_t :=3D null;=20 >=20 > variable a: unsigned(start_of_list.data'range); >=20 > begin=20 >=20 > a :=3D start_of_list.data;=20 >=20 > =20 >=20 > ptr :=3D start_of_list.next_link;=20 >=20 > DEALLOCATE(start_of_list);=20 >=20 > =20 >=20 > start_of_list :=3D ptr;=20 >=20 > return(a); >=20 > end function get_data2; From newsfish@newsfish Thu Aug 1 00:29:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Writing testbench tools. Suggestions? Date: Fri, 09 May 2014 19:11:08 +0200 Organization: A noiseless patient Spider Lines: 67 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 9 May 2014 17:11:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d50e3f26ee7886ceb9de424a7ed3d9fe"; logging-data="23351"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+4pZz7j90fK8k5FmHP2hHx" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 Cancel-Lock: sha1:jWtfnUP+lcUmiMev5kWm1QL32Js= Xref: news.eternal-september.org comp.lang.vhdl:3063 I am trying to write some helper tools to generate testbench signals. For instance, I have written this data_stream generator: procedure data_stream( signal y : out std_logic; -- Output signal constant data : std_logic_vector; -- Data, e.g. "11110101" constant bit_period : time; -- Duration of each bit constant start_time : time := 0 ns; -- Initial time offset constant def_out : std_logic := 'U') is begin y <= def_out; wait for start_time; for ix in data'left to data'right loop (*) y<=data(ix); wait for bit_period; end loop; y <= def_out; (*) actually I look if data'left < data'right and iterate "to" or "downto" otherwise. (Could probably be improved) Using this procedure, in the test bench I can build: data_stream(slv(1),"0011",1 us, 0 us,'Z'); data_stream(slv(0),"1101",1 us, 5 us,'Z'); Now, I would like to merge each signal onto one. Thanks to the default value of 'Z' this is simple. For instance, in the test bench, this code works fine: join: for i in slv'range generate tot <= slv(i); end generate; y <='U' when tot='Z' else tot; where the 'U' could be changed to whatever makes sense. Now, I would like to have the last lines in a _function_ or _procedure_. Unfortunately, I only have been able to bring this together, which works but looks ugly compared to the 4 lines before: procedure signal_join( signal y : out std_logic; constant slv : std_logic_vector; constant def_out : std_logic := 'U') is variable tot: std_logic; begin tot := 'Z'; join: for i in slv'range loop if slv(i)/='Z' then tot := slv(i); end if; end loop; if tot='Z' then y<=def_out; else y<=tot; end if; end; I would appreciate any suggestion on this. Especially, if I am making big mistakes! Furthermore, I have been unable to find functions that ease the generation of test signals, say to simulate some bursts of an SPI master or whatever, which is why I am writing this stuff. Any pointers on this? Pere From newsfish@newsfish Thu Aug 1 00:29:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: how create an 8 bit binary to BCD decoder? Date: Fri, 09 May 2014 14:33:46 -0400 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <179bb941-0582-42c6-9d53-e68c435b1c5f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Fri, 9 May 2014 18:33:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="1f290bac804f6cd54e3c0a5f7ad6fb70"; logging-data="27599"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xbSvXhlriyM35Y9wkY19U" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <179bb941-0582-42c6-9d53-e68c435b1c5f@googlegroups.com> Cancel-Lock: sha1:DcY48J6CfIxyLbaILsTKC6Oqr+w= Xref: news.eternal-september.org comp.lang.vhdl:3064 On 5/1/2014 12:55 PM, emirogluengin@gmail.com wrote: > 15 Mayıs 2002 Çarşamba 23:07:03 UTC+3 tarihinde Christian yazdı: >> Hello! >> I know this newsgroup is specially ybout VHDL. But I am curently working >> with Altera's derivation AHDL. >> My question isn't quite language related but more general: >> >> How would you create a decoder which generates BCD-coding from normal 8bit >> binary coding? >> I want to control several 7 segment displays and therefore have to use BCD >> coding. >> >> I'd be very happy to get any kind of help. >> Regards >> Chris. I see this message has not been answered so let me try. I remember seeing some fairly elegant ways to convert binary to decimal, but none of them seem to have stuck in my mind. I bet a google search would pull up a few. In your case I think you could do some fairly simple shortcuts which take advantage of the fact that you are only converting an 8 bit sample. With larger numbers it is usually done iteratively, converting one digit at a time, LSB first. -- Rick From newsfish@newsfish Thu Aug 1 00:29:53 2024 X-Received: by 10.182.219.226 with SMTP id pr2mr7921784obc.44.1399714550111; Sat, 10 May 2014 02:35:50 -0700 (PDT) X-Received: by 10.140.49.70 with SMTP id p64mr6483qga.21.1399714550046; Sat, 10 May 2014 02:35:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no2664821igi.0!news-out.google.com!dz10ni36309qab.1!nntp.google.com!hw13no2030936qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 May 2014 02:35:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.23.53.3; posting-account=rOfGEwkAAACFroalPzX-5MFVPhTYgaRI NNTP-Posting-Host: 188.23.53.3 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL to SystemC From: moogyd@yahoo.co.uk Injection-Date: Sat, 10 May 2014 09:35:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3065 Hi, Has anybody successfully used VDHL to SystemC conversion tools. Google returns one or two options, but I'd like to hear from people who have used them. Thanks, Steven From newsfish@newsfish Thu Aug 1 00:29:53 2024 X-Received: by 10.66.230.226 with SMTP id tb2mr6910304pac.41.1399765492083; Sat, 10 May 2014 16:44:52 -0700 (PDT) X-Received: by 10.182.99.199 with SMTP id es7mr101890obb.17.1399765491817; Sat, 10 May 2014 16:44:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no4344999igq.0!news-out.google.com!gi6ni804igc.0!nntp.google.com!c1no4344992igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 May 2014 16:44:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=173.167.190.129; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 173.167.190.129 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> Subject: Writing testbench tools. Suggestions? From: KJ Injection-Date: Sat, 10 May 2014 23:44:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3066 When writing test benches for something that attaches to the top level of a= design, I find it best to simply model the physical part on the actual boa= rd. When you do that, you will start building up a library of part models = that can be reused down the road. The verification of the part model is do= ne by verifying to the data sheet. Your design then gets verified by using= your validated part model. Will lead to less surprises when you power up = your board. Since you mentioned emulating a SPI master you are likely in t= his situation. If writing testbenches for internal modules, you will find it can be produc= tive to standardize on an interface protocol such as Avalon or Wishbone. O= ne benefit will be that testbench writing will be more standardized. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: "Tomas D." Newsgroups: comp.lang.vhdl Subject: Re: VHDL to SystemC Date: Sun, 11 May 2014 13:46:44 +0100 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: Injection-Date: Sun, 11 May 2014 12:46:44 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d1343ad59d23d554448c77c3a5a8e031"; logging-data="11769"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/8+/q6CE5GOo7Jq5YNlLov" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 Cancel-Lock: sha1:puobIwXiz95RZyL8szGlfEdGJ1E= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:3067 wrote in message news:aeddf515-3f70-4b02-9f36-025a8f2b5f78@googlegroups.com... > Hi, > Has anybody successfully used VDHL to SystemC conversion tools. Google > returns one or two options, but I'd like to hear from people who have used > them. > Thanks, > Steven It's like converting foot toe to hands thumb. Do you really want that? From newsfish@newsfish Thu Aug 1 00:29:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx28.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL to SystemC References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140511-0, 11/05/2014), Outbound message X-Antivirus-Status: Clean Lines: 24 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1399827424 86.29.12.221 (Sun, 11 May 2014 16:57:04 UTC) NNTP-Posting-Date: Sun, 11 May 2014 16:57:04 UTC Organization: virginmedia.com Date: Sun, 11 May 2014 17:57:04 +0100 X-Received-Body-CRC: 2817037900 X-Received-Bytes: 2020 Xref: news.eternal-september.org comp.lang.vhdl:3068 On 10/05/2014 10:35, moogyd@yahoo.co.uk wrote: > Hi, > Has anybody successfully used VDHL to SystemC conversion tools. Google returns one or two options, but I'd like to hear from people who have used them. > Thanks, > Steven > Hi Steven, I briefly played with Carbon (http://www.carbondesignsystems.com) and I must say that I was quite impressed. I only tried a few test cases but from what I remember the resulting C++ (with a SystemC top layer) ran much faster than the original VHDL. If you are looking into building a virtual prototype then I would recommend you speak to these guys. If you just want to import some VHDL models to an OSCI environment than you can try my VHDL to SystemC converter as a template generator. However, expect much worse simulation time (3x slower), minimum language support, requirement to fix/tweak the code and on top of that a developer not willing to fix the translator ;-) Good luck, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:29:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: Writing testbench tools. Suggestions? Date: Sun, 11 May 2014 20:08:42 +0200 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 11 May 2014 18:08:44 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="e1ca11cb030fe122572a5bbc5f30875d"; logging-data="19135"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Dj9Az01sL7ykdHDATO9Qkjh08pYGDZz8=" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> Cancel-Lock: sha1:bIwpuWIaWC3nCp5tg1XZKDDLD0A= Xref: news.eternal-september.org comp.lang.vhdl:3069 On 05/11/2014 01:44 AM, KJ wrote: > When writing test benches for something that attaches to the top level of a design, I find it best to simply model the physical part on the actual board. When you do that, you will start building up a library of part models that can be reused down the road. The verification of the part model is done by verifying to the data sheet. Your design then gets verified by using your validated part model. Will lead to less surprises when you power up your board. Since you mentioned emulating a SPI master you are likely in this situation. > > If writing testbenches for internal modules, you will find it can be productive to standardize on an interface protocol such as Avalon or Wishbone. One benefit will be that testbench writing will be more standardized. > > Kevin Jennings > I feel this is exactly what I am doing: My design will talk to an SPI master, hence I am generating the waveforms that the master is expected to give, according to the datasheet. In my post, I included some code that allows me to build an arbitrary burst (usable for clock, data, whatever). The question remains: what is the best way to combine these individual bursts onto a single signal, so that I can model an arbitrary number of occurrences of each stream at arbitrary time points? Pere From newsfish@newsfish Thu Aug 1 00:29:54 2024 X-Received: by 10.43.79.196 with SMTP id zr4mr11606013icb.3.1399860992021; Sun, 11 May 2014 19:16:32 -0700 (PDT) X-Received: by 10.182.191.98 with SMTP id gx2mr1049obc.22.1399860991863; Sun, 11 May 2014 19:16:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no4918763igq.0!news-out.google.com!gi6ni796igc.0!nntp.google.com!r10no3340867igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 May 2014 19:16:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <775dfba4-6e6e-46c3-82ac-9500c6b24fa0@googlegroups.com> Subject: Re: Writing testbench tools. Suggestions? From: KJ Injection-Date: Mon, 12 May 2014 02:16:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3070 On Sunday, May 11, 2014 2:08:42 PM UTC-4, o pere o wrote: > I feel this is exactly what I am doing: My design will talk to an SPI=20 > master, hence I am generating the waveforms that the master is expected= =20 > to give, according to the datasheet.=20 It is not evident in what you posted that there would be any connection wit= h the datasheet at all. Not a very obvious one at least. You don't want t= o make validating the model to be an even bigger task than using the model = to validate your design. >=20 > In my post, I included some code that allows me to build an arbitrary=20 > burst (usable for clock, data, whatever).=20 Not really. Most parts respond to signals from other external parts (i.e. = a processor interface to an FPGA). What you have shown is something where = you give it a list of outputs and you crank them out at some fixed interval= . In effect it is nothing more than this: xyz <=3D '1', '0' after bit_period, '1' after 2*bit_period, '1' after 3*bit= _period ... While use of your procedure would be a better shorthand than the above line= of code, there really isn't much call for the above line of code in the fi= rst place so your shorthand procedure wouldn't have much utility. A SPI master model would instead respond to some higher level control (i.e.= a model for the code running in a processor) and then chunk out the bits a= nd clock as they are specified in the datasheet. So a snippet of the SPI m= aster for a processor with a SPI master might look like this... process begin Spi_Cs_n <=3D '1'; Spi_Sclk <=3D '0'; wait until Spi_Master_Write_This_Out'event; -- Some example of this SPI = master process waiting for something to do Spi_Cs_n <=3D '0'; wait for Spi_Cs_To_Sclk_Time; -- Spec'ed on the datasheet for i in Spi_Data_To_Write'low to Spi_Data_To_Write'high loop Spi_Sclk <=3D '1', '0' after Spi_Clock_Period/2; -- Note: Spi_Clock_= Period could be a signal so you can vary the Spi clock period during the si= m Spi_Mosi <=3D Spi_Data_To_Write(i) after Tco; -- Models the clock = to output delay per the datasheet, in case that ends up mattering wait until Spi_Sclk'falling edge Spi_Sclk; wait for Spi_Clock_Period/2; end loop; Spi_Cs_n <=3D '1'; wait for Spi_Cs_Inactive_To_Spi_Cs_Active_Again; -- Again, likely spec'e= d on datasheet end process; > The question remains: what is=20 > the best way to combine these individual bursts onto a single signal, so= =20 > that I can model an arbitrary number of occurrences of each stream at=20 > arbitrary time points?=20 >=20 I don't have an answer for that question since I don't think it's the right= approach. What physical parts can you think of that would have in their d= atasheet listed something where it shoots out a particular pattern at some = periodic rate? Can you think of more than one part? However, if you create a model of an actual part instead, then you'll find that you don't n= eed to answer your stated question in order to get a working and reaonably realistic model. You might not agree, and that's fine, I'm just putting in= my two cents and giving you an example to consider instead. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:29:55 2024 X-Received: by 10.58.168.137 with SMTP id zw9mr13787495veb.15.1399880108458; Mon, 12 May 2014 00:35:08 -0700 (PDT) X-Received: by 10.140.101.147 with SMTP id u19mr20426qge.10.1399880108432; Mon, 12 May 2014 00:35:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no2640906qab.0!news-out.google.com!dz10ni36309qab.1!nntp.google.com!hw13no2640902qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 May 2014 00:35:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.223.253.45; posting-account=rOfGEwkAAACFroalPzX-5MFVPhTYgaRI NNTP-Posting-Host: 81.223.253.45 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <04f0535a-dbdd-4537-8e72-ec4d86e5aac0@googlegroups.com> Subject: Re: VHDL to SystemC From: moogyd@yahoo.co.uk Injection-Date: Mon, 12 May 2014 07:35:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3071 On Sunday, 11 May 2014 18:57:04 UTC+2, HT-Lab wrote: > On 10/05/2014 10:35, ******yahoo.co.uk wrote: > > > Hi, > > > Has anybody successfully used VDHL to SystemC conversion tools. Google returns one or two options, but I'd like to hear from people who have used them. > > > Thanks, > > > Steven > > > > > Hi Steven, > I briefly played with Carbon (http://www.carbondesignsystems.com) and I > must say that I was quite impressed. I only tried a few test cases but > from what I remember the resulting C++ (with a SystemC top layer) ran > much faster than the original VHDL. If you are looking into building a > virtual prototype then I would recommend you speak to these guys. > If you just want to import some VHDL models to an OSCI environment than > you can try my VHDL to SystemC converter as a template generator. > However, expect much worse simulation time (3x slower), minimum language > support, requirement to fix/tweak the code and on top of that a > developer not willing to fix the translator ;-) > Good luck, > Hans > www.ht-lab.com Hi Hans, you are correct - I am looking to produce a virtual prototype for FW development. The plan is to do initial conversion automatically, and then analyze performance of resulting models, perhaps performing some optimizations where possibly. I'll have a look at you suggestions. Thanks, Steven From newsfish@newsfish Thu Aug 1 00:29:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: how create an 8 bit binary to BCD decoder? Date: Mon, 12 May 2014 08:40:08 -0400 Organization: Alacron, Inc. Lines: 50 Message-ID: References: <179bb941-0582-42c6-9d53-e68c435b1c5f@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 12 May 2014 12:42:04 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="7136"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18VinQY25CTZmbdkffq7mqM9I9At+CbaAk=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:XCw6YU/6037RwczbVfGTNGNC6Lg= Xref: news.eternal-september.org comp.lang.vhdl:3072 rickman wrote: > On 5/1/2014 12:55 PM, emirogluengin@gmail.com wrote: >> 15 Mayıs 2002 Çarşamba 23:07:03 UTC+3 tarihinde Christian yazdı: >>> Hello! >>> I know this newsgroup is specially ybout VHDL. But I am curently working >>> with Altera's derivation AHDL. >>> My question isn't quite language related but more general: >>> >>> How would you create a decoder which generates BCD-coding from normal >>> 8bit >>> binary coding? >>> I want to control several 7 segment displays and therefore have to >>> use BCD >>> coding. >>> >>> I'd be very happy to get any kind of help. >>> Regards >>> Chris. > > I see this message has not been answered so let me try. > > I remember seeing some fairly elegant ways to convert binary to decimal, > but none of them seem to have stuck in my mind. I bet a google search > would pull up a few. > > In your case I think you could do some fairly simple shortcuts which > take advantage of the fact that you are only converting an 8 bit sample. > With larger numbers it is usually done iteratively, converting one > digit at a time, LSB first. > When I had to do this with an 8-bit micro, I made use of the DAA (decimal adjust after addition) instruction. The basic loop was: shift input left into carry add accumulator + carry in to accumulator decimal adjust accumulator The combination of addition and DAA effectively created a BCD adder. Note that the accumulator must be zeroed out before the loop, and you need a loop counter, but that was the basic idea. In an FPGA, I'd probably use a lookup table if there were only 8 bits. I assume that since this information is going to a display, that you have lots of time (many clock cycles) available to get the job done? -- Gabor From newsfish@newsfish Thu Aug 1 00:29:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: Writing testbench tools. Suggestions? Date: Mon, 12 May 2014 19:25:50 +0200 Organization: A noiseless patient Spider Lines: 81 Message-ID: References: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> <775dfba4-6e6e-46c3-82ac-9500c6b24fa0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 12 May 2014 17:25:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d50e3f26ee7886ceb9de424a7ed3d9fe"; logging-data="9449"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18SMU8m3oLlXN9LB73gmMpR" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <775dfba4-6e6e-46c3-82ac-9500c6b24fa0@googlegroups.com> Cancel-Lock: sha1:Qz0xPat16DFt0KIHl7cqRy/VdPU= Xref: news.eternal-september.org comp.lang.vhdl:3073 On 05/12/2014 04:16 AM, KJ wrote: > On Sunday, May 11, 2014 2:08:42 PM UTC-4, o pere o wrote: >> I feel this is exactly what I am doing: My design will talk to an SPI >> master, hence I am generating the waveforms that the master is expected >> to give, according to the datasheet. > > It is not evident in what you posted that there would be any connection with the datasheet at all. Not a very obvious one at least. You don't want to make validating the model to be an even bigger task than using the model to validate your design. > >> >> In my post, I included some code that allows me to build an arbitrary >> burst (usable for clock, data, whatever). > > Not really. Most parts respond to signals from other external parts (i.e. a processor interface to an FPGA). What you have shown is something where you give it a list of outputs and you crank them out at some fixed interval. In effect it is nothing more than this: > > xyz <= '1', '0' after bit_period, '1' after 2*bit_period, '1' after 3*bit_period ... True. A simple helper function for this is exactly the goal that I had in mind. > While use of your procedure would be a better shorthand than the above line of code, there really isn't much call for the above line of code in the first place so your shorthand procedure wouldn't have much utility. Well, I have had the need to generate arbitrary data bursts at arbitrary time positions quite often... Of course, a model for the generator of these bursts gives more information... As always, it is a balance! > A SPI master model would instead respond to some higher level control (i.e. a model for the code running in a processor) and then chunk out the bits and clock as they are specified in the datasheet. So a snippet of the SPI master for a processor with a SPI master might look like this... > > process > begin > Spi_Cs_n <= '1'; > Spi_Sclk <= '0'; > wait until Spi_Master_Write_This_Out'event; -- Some example of this SPI master process waiting for something to do > Spi_Cs_n <= '0'; > wait for Spi_Cs_To_Sclk_Time; -- Spec'ed on the datasheet > for i in Spi_Data_To_Write'low to Spi_Data_To_Write'high loop > Spi_Sclk <= '1', '0' after Spi_Clock_Period/2; -- Note: Spi_Clock_Period could be a signal so you can vary the Spi clock period during the sim > Spi_Mosi <= Spi_Data_To_Write(i) after Tco; -- Models the clock to output delay per the datasheet, in case that ends up mattering > wait until Spi_Sclk'falling edge Spi_Sclk; > wait for Spi_Clock_Period/2; > end loop; > Spi_Cs_n <= '1'; > wait for Spi_Cs_Inactive_To_Spi_Cs_Active_Again; -- Again, likely spec'ed on datasheet > end process; Now I see your point clearer. However, I will still need to to generate the Spi_Master_Write_This_Out'event at an arbitrary time instant. Then I will need to be able to change the data that is being written, depending on the particular data burst. This can be done, and is probably the way to go if you want maximum flexibility. However, if I just need a couple of bursts, my quick-and-dirty approach gives me a suitable waveform without having to go into the SPI details... Of course your approach gives more insight although at a higher initial coding cost. >> The question remains: what is >> the best way to combine these individual bursts onto a single signal, so >> that I can model an arbitrary number of occurrences of each stream at >> arbitrary time points? >> > > I don't have an answer for that question since I don't think it's the right approach. What physical parts can you think of that would have in their datasheet listed something where it shoots out a particular pattern at some periodic rate? Can you think of more than one part? However, if you > create a model of an actual part instead, then you'll find that you don't need to answer your stated question in order to get a working and reaonably > realistic model. You might not agree, and that's fine, I'm just putting in my two cents and giving you an example to consider instead. I really appreciate your inputs and thank you for your time. My effort is just to have something a little more elaborate than the practice of just drawing waveforms in a waveform editor. The SPI example I mentioned is however just one of the inputs of my current design. The other will be a physical IEEE 802.15.4 frame. Here, I am currently able to generate a burst corresponding to some data, following the original idea I posted. Again, a simple combination of individual signals might do the job of simulating a typical transaction. Perhaps I can come up with something similar as the example you posted... Pere From newsfish@newsfish Thu Aug 1 00:29:56 2024 X-Received: by 10.42.236.68 with SMTP id kj4mr14878981icb.6.1399986549796; Tue, 13 May 2014 06:09:09 -0700 (PDT) X-Received: by 10.140.18.194 with SMTP id 60mr28qgf.36.1399986549748; Tue, 13 May 2014 06:09:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no5617034igq.0!news-out.google.com!dz10ni40603qab.1!nntp.google.com!hw13no3018801qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 May 2014 06:09:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9b9bc77a-b6d4-41a7-a18f-e9d405b8864f@googlegroups.com> Subject: Help code VHDL From: Ayoub Injection-Date: Tue, 13 May 2014 13:09:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3074 hi everybody ! I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data and the result would be S . Can you help me correcting this code : library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Premier is port( clk:in std_logic ; rst:in std_logic ; data:in std_logic ; CD :in std_logic_vector(3 downto 0); S :out std_logic ); end entity ; architecture beh of Premier is signal i :integer range 0 to 3; signal iCD :std_logic_vector(3 downto 0); signal idata:std_logic ; begin code:process(clk,rst) begin if(rst='1') then S<='0'; i<=0; idata<=data ; iCD <=CD ; else if(clk'event and clk='1')then if(CD(0)='0')then iCD(3 downto 0)<="1111"; else iCD(3 downto 0)<="0001"; end if ; if(CD(1)='0') then iCD(3 downto 0)<="1111"; else iCD(3 downto 0)<="0001"; end if ; if(CD(2)='0') then iCD(3 downto 0)<="1111"; else iCD(3 downto 0)<="0001"; end if ; if(CD(3)='0') then iCD(3 downto 0)<="1111"; else iCD(3 downto 0)<="0001"; end if ; S<=not(iCD(i) xor (idata)); i<= i+1; if i=3 then idata<= data ; end if ; end if ; end if ; end process ; end architecture ; Thank you ! From newsfish@newsfish Thu Aug 1 00:29:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.stack.nl!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: Help code VHDL Date: Tue, 13 May 2014 08:28:12 -0700 Organization: Aioe.org NNTP Server Lines: 20 Message-ID: References: <9b9bc77a-b6d4-41a7-a18f-e9d405b8864f@googlegroups.com> NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3075 On 5/13/2014 6:09 AM, Ayoub wrote: > I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data > and the result would be S . According to my interpretation of the stated requirements, this pseudo code should work: func([in] CD, [in] data, [out] S) if CD == 0 S = -1 else if CD == 1 S = 1 else S = CD + data func end No registers or clocking are needed. It is basic combinatorial logic. JJS From newsfish@newsfish Thu Aug 1 00:29:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!newsfeed.xs4all.nl!newsfeed3a.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 11:30:25 +0200 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 65 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1400059825 dreader35.news.xs4all.nl 27153 puiterl/195.242.97.150:51618 Xref: news.eternal-september.org comp.lang.vhdl:3076 Tricky wrote: > This is fine, but if the start_of_list is null, you will get an error from > a null pointer access. > > In the real code I have a record type instead of just an unsigned. If the > start_of_list is null it returns a NULL version of the record type I have > as a constant. I actually worked around the problem by creating a pointer > to the record type, pulling the data off the linked list into the pointer, > then returning the de-referenced data: > > impure function get_packet return packet_info_t is > variable ptr : packet_ll_ptr_t := null; > variable ret : packet_info_ptr_t := null; > begin > if end_of_list = null then > ret := new packet_info_t'(NULL_PACKET); > > else > ptr := end_of_list.next_packet; > ret := new packet_info_t'( ptr.pi ); > > DEALLOCATE(end_of_list); > end_of_list := ptr; > > end if; > > return ret.all; > end function get_packet; You create a memory leak in this way, so don't do it this way. Every time get_packet is called, a packet is allocated, never deallocated and the pointer to it (ret) is lost upon exiting the function. VHDL does not know the concept of garbage collection, so this is a memory leak. To verify this, put the get_packet in a loop, endless, or a lot of times (increasing it tenfold with each run) and observe the memory usage of your machine. Or, in case of the endless loop, watch the simulator crash (and/or see you machine getting irresponsive). To get around the unconstrained issue, I would put the code in a package. Put a generic on that package, specifying the width of the data. Or better still, put the datatype in the generic of the package! When instantiating the package, you specify the datatype. In that way you can use your queue for any data type. Check out the book "VHDL-2008, just the new stuff" by Peter Ashenden and Jim Lewis. It is all described there, in the first chapter. One more thing: when declaring a variable of an access type, it is not necessary to initialize it to null. The initial value of variables and signals automatically is "the most left value" of the type of the variable or signal. For natural it is 0, for boolean false, for enumeration types the first member, for access types it is null. People sometimes complain that VHDL is overly verbose, but at the same time they type needless things... ;-) -- Paul Uiterlinden www.aimvalley.nl From newsfish@newsfish Thu Aug 1 00:29:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed3.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Writing testbench tools. Suggestions? Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 11:41:19 +0200 References: Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 17 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1400060479 dreader35.news.xs4all.nl 27127 puiterl/195.242.97.150:51653 Xref: news.eternal-september.org comp.lang.vhdl:3077 o pere o wrote: > I am trying to write some helper tools to generate testbench signals. [snip] > > I would appreciate any suggestion on this. Especially, if I am making > big mistakes! Furthermore, I have been unable to find functions that > ease the generation of test signals, say to simulate some bursts of an > SPI master or whatever, which is why I am writing this stuff. Any > pointers on this? I would suggest reading a book like "Writing Testbenches" by Janick Bergeron and look at the client/server model suggested there. -- Paul Uiterlinden www.aimvalley.nl From newsfish@newsfish Thu Aug 1 00:29:57 2024 X-Received: by 10.58.22.70 with SMTP id b6mr1983067vef.13.1400083072217; Wed, 14 May 2014 08:57:52 -0700 (PDT) X-Received: by 10.140.106.67 with SMTP id d61mr7695qgf.41.1400083072077; Wed, 14 May 2014 08:57:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!c1no6539701igq.0!news-out.google.com!qf4ni926igc.0!nntp.google.com!c1no6539679igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 08:57:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.83; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.83 References: <9b9bc77a-b6d4-41a7-a18f-e9d405b8864f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help code VHDL From: Ayoub Injection-Date: Wed, 14 May 2014 15:57:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3078 On Tuesday, May 13, 2014 5:28:12 PM UTC+2, John Speth wrote: > On 5/13/2014 6:09 AM, Ayoub wrote: > > > I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data > > > and the result would be S . > > > > According to my interpretation of the stated requirements, this pseudo > > code should work: > > > > func([in] CD, [in] data, [out] S) > > if CD == 0 > > S = -1 > > else if CD == 1 > > S = 1 > > else > > S = CD + data > > func end > > > > No registers or clocking are needed. It is basic combinatorial logic. > > > > JJS Thank you very much ^^ From newsfish@newsfish Thu Aug 1 00:29:57 2024 X-Received: by 10.66.138.17 with SMTP id qm17mr1962938pab.34.1400083162968; Wed, 14 May 2014 08:59:22 -0700 (PDT) X-Received: by 10.50.62.6 with SMTP id u6mr142061igr.15.1400083162833; Wed, 14 May 2014 08:59:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no6540688igq.0!news-out.google.com!qf4ni1019igc.0!nntp.google.com!r10no4491818igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 08:59:22 -0700 (PDT) In-Reply-To: <1da53656-f7dd-4825-8334-6179605e9e5c@k39g2000hsf.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=118.71.10.236; posting-account=3tUCQgoAAACv9-0KuHrdfl7c9q886ho5 NNTP-Posting-Host: 118.71.10.236 References: <1da53656-f7dd-4825-8334-6179605e9e5c@k39g2000hsf.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <488e4fec-54b3-4c4e-bccc-de3dee012ba2@googlegroups.com> Subject: Re: ASIC gate count estimation From: toanbkfet@gmail.com Injection-Date: Wed, 14 May 2014 15:59:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3079 hello you have document speak of count gate nand 2 ?? if you have ?? can you spent document that?? From newsfish@newsfish Thu Aug 1 00:29:58 2024 X-Received: by 10.236.125.6 with SMTP id y6mr2706550yhh.3.1400106603563; Wed, 14 May 2014 15:30:03 -0700 (PDT) X-Received: by 10.140.91.245 with SMTP id z108mr81170qgd.16.1400106603353; Wed, 14 May 2014 15:30:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no6836851igq.0!news-out.google.com!qf4ni926igc.0!nntp.google.com!c1no6836843igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 15:30:03 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.193.64.121; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 46.193.64.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> Subject: Array VHDL From: Ayoub Injection-Date: Wed, 14 May 2014 22:30:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3080 Hi everybody ! I have a small problemIo want to do a not xor for 4 input of 4 bit with input data 1 bit to have a 4 bit output using a table of input here is my code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cdm is port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic ; CD : in std_logic_vector(15 downto 0) ; S : out std_logic(3 downto 0 ); end entity ; architecture beh of cdm is signal i :integer range 0 to 3 ; signal idata :std_logic ; begin code :process(clk,rst) begin if(rst='1')then S<='0'; i<=0 ; idata<=data ; else if(clk'event and clk='1')then type tab is array(3 downto 0)of std_logic_vector ???? ?? S<=not(CD(i) xor (idata)); i<= i+1 ; if i=3 then idata<=data ; end if ; end if ; end if ; end process ; end architecture ; Thank you in advance for your answer !! From newsfish@newsfish Thu Aug 1 00:29:58 2024 X-Received: by 10.224.72.66 with SMTP id l2mr4372505qaj.8.1400162011586; Thu, 15 May 2014 06:53:31 -0700 (PDT) X-Received: by 10.140.92.82 with SMTP id a76mr195636qge.1.1400162011477; Thu, 15 May 2014 06:53:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!c1no7294129igq.0!news-out.google.com!qf4ni1806igc.0!nntp.google.com!c1no7294123igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 May 2014 06:53:31 -0700 (PDT) In-Reply-To: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 References: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Array VHDL From: Ayoub Injection-Date: Thu, 15 May 2014 13:53:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3081 On Thursday, May 15, 2014 12:30:03 AM UTC+2, Ayoub wrote: > Hi everybody ! > > > > I have a small problemIo want to do a not xor for 4 input of 4 bit with input data > > 1 bit to have a 4 bit output using a table of input > > > > here is my code: > > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.numeric_std.all; > > > > entity cdm is > > port ( > > clk : in std_logic ; > > rst : in std_logic ; > > data: in std_logic ; > > CD : in std_logic_vector(15 downto 0) ; > > S : out std_logic(3 downto 0 ); > > end entity ; > > > > architecture beh of cdm is > > > > signal i :integer range 0 to 3 ; > > signal idata :std_logic ; > > begin > > code :process(clk,rst) > > begin > > if(rst='1')then > > S<='0'; > > i<=0 ; > > idata<=data ; > > else > > if(clk'event and clk='1')then > > > > type tab is array(3 downto 0)of std_logic_vector > > ???? > > ?? > > > > S<=not(CD(i) xor (idata)); > > i<= i+1 ; > > if i=3 then > > idata<=data ; > > end if ; > > end if ; > > end if ; > > end process ; > > end architecture ; > > > > Thank you in advance for your answer !! Are You Here ? From newsfish@newsfish Thu Aug 1 00:29:58 2024 X-Received: by 10.182.24.5 with SMTP id q5mr5020525obf.23.1400162152721; Thu, 15 May 2014 06:55:52 -0700 (PDT) X-Received: by 10.140.95.141 with SMTP id i13mr200450qge.3.1400162152583; Thu, 15 May 2014 06:55:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no4951375igi.0!news-out.google.com!qf4ni1806igc.0!nntp.google.com!c1no7295972igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 May 2014 06:55:52 -0700 (PDT) In-Reply-To: <488e4fec-54b3-4c4e-bccc-de3dee012ba2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.84.30.178; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 2.84.30.178 References: <1da53656-f7dd-4825-8334-6179605e9e5c@k39g2000hsf.googlegroups.com> <488e4fec-54b3-4c4e-bccc-de3dee012ba2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4707a363-9a89-4fa6-b87b-98e9d840cd81@googlegroups.com> Subject: Re: ASIC gate count estimation From: Nikolaos Kavvadias Injection-Date: Thu, 15 May 2014 13:55:52 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: base64 Xref: news.eternal-september.org comp.lang.vhdl:3082 VGhpcyBpcyBhIDYteWVhciBvbGQgdGhyZWFkLCBubyBtdWNoIHBvaW50IGluIGFkZGluZyBuZXcg cG9zdHMuDQoNCs6kzrcgzqTOtc+EzqzPgc+EzrcsIDE0IM6czrHOkM6/z4UgMjAxNCA2OjU5OjIy IM68Ls68LiBVVEMrMywgzr8gz4fPgc6uz4PPhM63z4IgdG9hbi4uLkBnbWFpbC5jb20gzq3Os8+B zrHPiM61Og0KPiBoZWxsbyB5b3UgaGF2ZSBkb2N1bWVudCBzcGVhayBvZiBjb3VudCBnYXRlIG5h bmQgMiA/Pw0KPiANCj4gIA0KPiANCj4gaWYgeW91IGhhdmUgPz8gY2FuIHlvdSBzcGVudCBkb2N1 bWVudCB0aGF0Pz8NCg0K From newsfish@newsfish Thu Aug 1 00:29:58 2024 X-Received: by 10.182.28.136 with SMTP id b8mr12438698obh.19.1400366368606; Sat, 17 May 2014 15:39:28 -0700 (PDT) X-Received: by 10.140.101.147 with SMTP id u19mr3597qge.10.1400366368486; Sat, 17 May 2014 15:39:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no611398igb.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no9295251igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 May 2014 15:39:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.100.228; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.100.228 References: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Array VHDL From: Nikolaos Kavvadias Injection-Date: Sat, 17 May 2014 22:39:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3083 Hi I am here. I would happily provide help. > > I have a small problemIo want to do a not xor for 4 input of 4 bit with input data My consulting services are better explained here: www.nkavvadias.com Best regards N > > > > > > 1 bit to have a 4 bit output using a table of input > > > > > > > > > > > > here is my code: > > > > > > > > > > > > library ieee; > > > > > > use ieee.std_logic_1164.all; > > > > > > use ieee.numeric_std.all; > > > > > > > > > > > > entity cdm is > > > > > > port ( > > > > > > clk : in std_logic ; > > > > > > rst : in std_logic ; > > > > > > data: in std_logic ; > > > > > > CD : in std_logic_vector(15 downto 0) ; > > > > > > S : out std_logic(3 downto 0 ); > > > > > > end entity ; > > > > > > > > > > > > architecture beh of cdm is > > > > > > > > > > > > signal i :integer range 0 to 3 ; > > > > > > signal idata :std_logic ; > > > > > > begin > > > > > > code :process(clk,rst) > > > > > > begin > > > > > > if(rst='1')then > > > > > > S<='0'; > > > > > > i<=0 ; > > > > > > idata<=data ; > > > > > > else > > > > > > if(clk'event and clk='1')then > > > > > > > > > > > > type tab is array(3 downto 0)of std_logic_vector > > > > > > ???? > > > > > > ?? > > > > > > > > > > > > S<=not(CD(i) xor (idata)); > > > > > > i<= i+1 ; > > > > > > if i=3 then > > > > > > idata<=data ; > > > > > > end if ; > > > > > > end if ; > > > > > > end if ; > > > > > > end process ; > > > > > > end architecture ; > > > > > > > > > > > > Thank you in advance for your answer !! > > > > Are You Here ? From newsfish@newsfish Thu Aug 1 00:29:59 2024 X-Received: by 10.58.29.14 with SMTP id f14mr3284072veh.32.1400485748942; Mon, 19 May 2014 00:49:08 -0700 (PDT) X-Received: by 10.140.104.202 with SMTP id a68mr16334qgf.30.1400485748686; Mon, 19 May 2014 00:49:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hl10no1126436igb.0!news-out.google.com!qf4ni2875igc.0!nntp.google.com!hl10no1126435igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 00:49:08 -0700 (PDT) In-Reply-To: <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Mon, 19 May 2014 07:49:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3084 > > You create a memory leak in this way, so don't do it this way. > The memory leak is a concern, but this is best way around my problem. I cannot put the type in a package, because the the packet length is variable at run time. The whole point is the packet generator generates variable length packets for the UUT to handle. So even the package generics do not help here. Because of this, I do not know the length of the packet until it is pulled out of the queue, so I cannot create a temporary variable ----- Actually, I just thought, it wouldnt be very hard just to access the length of the packet on the end of the queue to return the length to create the temporary variable, so it is not a pointer. From newsfish@newsfish Thu Aug 1 00:29:59 2024 X-Received: by 10.50.119.164 with SMTP id kv4mr5597159igb.3.1400486295410; Mon, 19 May 2014 00:58:15 -0700 (PDT) X-Received: by 10.140.91.245 with SMTP id z108mr19122qgd.16.1400486295316; Mon, 19 May 2014 00:58:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no10275261igq.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10275254igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 00:58:15 -0700 (PDT) In-Reply-To: <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Mon, 19 May 2014 07:58:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3085 So all I needed was an extra function to check if the end of queue was already null, or just return the length: ------------------------------------------------------------------ --Removes a packet from the FIFO Queue ------------------------------------------------------------------ impure function get_packet return packet_info_t is impure function get_payload_len return integer is begin if end_of_queue = null then return 0; else return end_of_queue.payload'length; end if; end function get_payload_len; variable ptr : packet_ll_ptr_t := null; variable ret : packet_info_t( payload(0 to get_payload_len-1)); begin if end_of_list = null then ret := NULL_PACKET; else ret := end_of_list.pi; ptr := end_of_list.next_packet; DEALLOCATE(end_of_list); end_of_list := ptr; ------------------------------------------------------------------------------------------- --The list has been emptied, so to prevent a null pointer reference, reset the start of --list too to prevent a dangling pointer ------------------------------------------------------------------------------------------- if end_of_list = null then start_of_list := null; end if; end if; return ret; end function get_packet; From newsfish@newsfish Thu Aug 1 00:29:59 2024 X-Received: by 10.66.157.138 with SMTP id wm10mr1714577pab.23.1400486526825; Mon, 19 May 2014 01:02:06 -0700 (PDT) X-Received: by 10.140.95.141 with SMTP id i13mr642953qge.3.1400486526710; Mon, 19 May 2014 01:02:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no1130904igb.0!news-out.google.com!qf4ni2875igc.0!nntp.google.com!hl10no1130889igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 01:02:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Mon, 19 May 2014 08:02:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3086 Doh must remember to syntax check first! ------------------------------------------------------------------ --Removes a packet from the FIFO Queue ------------------------------------------------------------------ impure function get_packet return packet_info_t is impure function get_payload_len return integer is begin if end_of_list= null then return 0; else return end_of_list.pi.payload'length; end if; end function get_payload_len; variable ptr : packet_ll_ptr_t := null; variable ret : packet_info_t( payload(0 to get_payload_len-1)); begin if end_of_list = null then ret := NULL_PACKET; else ret := end_of_list.pi; ptr := end_of_list.next_packet; DEALLOCATE(end_of_list); end_of_list := ptr; ------------------------------------------------------------------------------------------- --The list has been emptied, so to prevent a null pointer reference, reset the start of --list too to prevent a dangling pointer ------------------------------------------------------------------------------------------- if end_of_list = null then start_of_list := null; end if; end if; return ret; end function get_packet; From newsfish@newsfish Thu Aug 1 00:29:59 2024 X-Received: by 10.66.66.35 with SMTP id c3mr13613228pat.7.1400489588941; Mon, 19 May 2014 01:53:08 -0700 (PDT) X-Received: by 10.140.44.75 with SMTP id f69mr25274qga.11.1400489588783; Mon, 19 May 2014 01:53:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hl10no1147329igb.0!news-out.google.com!qf4ni2875igc.0!nntp.google.com!hl10no1147326igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 01:53:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: demande plz From: Ayoub Injection-Date: Mon, 19 May 2014 08:53:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3087 Hi ! How are you ? Do you have an example of demodulation bpsk in vhdl ?! thank you in advance for your answer. From newsfish@newsfish Thu Aug 1 00:30:00 2024 X-Received: by 10.68.216.230 with SMTP id ot6mr16110437pbc.3.1400496776508; Mon, 19 May 2014 03:52:56 -0700 (PDT) X-Received: by 10.140.92.227 with SMTP id b90mr31901qge.25.1400496776345; Mon, 19 May 2014 03:52:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!c1no10382977igq.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10382970igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 03:52:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.100.228; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.100.228 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <368ec752-043a-40f4-8dea-56cb9bbe3c03@googlegroups.com> Subject: Re: demande plz From: Nikolaos Kavvadias Injection-Date: Mon, 19 May 2014 10:52:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3088 Hi, I don't have one at hand, but I could develop one. From newsfish@newsfish Thu Aug 1 00:30:00 2024 X-Received: by 10.236.137.50 with SMTP id x38mr15323391yhi.9.1400497346056; Mon, 19 May 2014 04:02:26 -0700 (PDT) X-Received: by 10.140.101.111 with SMTP id t102mr637935qge.5.1400497345943; Mon, 19 May 2014 04:02:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no1195822igb.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10389931igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 04:02:25 -0700 (PDT) In-Reply-To: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Array VHDL From: Tricky Injection-Date: Mon, 19 May 2014 11:02:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3089 Well, for a start, you need to make S a std_logic_vector then you probably want a for loop around the xor A good tutorial will help. Or just pay nikolaos a small fortune On Wednesday, 14 May 2014 23:30:03 UTC+1, Ayoub wrote: > Hi everybody ! > > > > I have a small problemIo want to do a not xor for 4 input of 4 bit with input data > > 1 bit to have a 4 bit output using a table of input > > > > here is my code: > > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.numeric_std.all; > > > > entity cdm is > > port ( > > clk : in std_logic ; > > rst : in std_logic ; > > data: in std_logic ; > > CD : in std_logic_vector(15 downto 0) ; > > S : out std_logic(3 downto 0 ); > > end entity ; > > > > architecture beh of cdm is > > > > signal i :integer range 0 to 3 ; > > signal idata :std_logic ; > > begin > > code :process(clk,rst) > > begin > > if(rst='1')then > > S<='0'; > > i<=0 ; > > idata<=data ; > > else > > if(clk'event and clk='1')then > > > > type tab is array(3 downto 0)of std_logic_vector > > ???? > > ?? > > > > S<=not(CD(i) xor (idata)); > > i<= i+1 ; > > if i=3 then > > idata<=data ; > > end if ; > > end if ; > > end if ; > > end process ; > > end architecture ; > > > > Thank you in advance for your answer !! From newsfish@newsfish Thu Aug 1 00:30:00 2024 X-Received: by 10.236.141.11 with SMTP id f11mr2804198yhj.54.1400507832733; Mon, 19 May 2014 06:57:12 -0700 (PDT) X-Received: by 10.182.247.2 with SMTP id ya2mr21116obc.20.1400507832445; Mon, 19 May 2014 06:57:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!proxad.net!feeder1-2.proxad.net!209.85.213.215.MISMATCH!hl10no1266723igb.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10507571igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 06:57:12 -0700 (PDT) In-Reply-To: <368ec752-043a-40f4-8dea-56cb9bbe3c03@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 References: <368ec752-043a-40f4-8dea-56cb9bbe3c03@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: demande plz From: Ayoub Injection-Date: Mon, 19 May 2014 13:57:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3090 On Monday, May 19, 2014 12:52:56 PM UTC+2, Nikolaos Kavvadias wrote: > Hi, I don't have one at hand, but I could develop one. Hi , Good ;I go to see ; because I want to have just an idea Knowing that I want to make the bpsk demodulating . Thank you . From newsfish@newsfish Thu Aug 1 00:30:00 2024 X-Received: by 10.182.213.37 with SMTP id np5mr16785439obc.36.1400511329552; Mon, 19 May 2014 07:55:29 -0700 (PDT) X-Received: by 10.140.38.199 with SMTP id t65mr56699qgt.17.1400511329426; Mon, 19 May 2014 07:55:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no10551281igq.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10551279igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 07:55:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4157474d-c812-40f3-967f-7a85f9e1acac@googlegroups.com> Subject: Array of Modulation BPSK From: Ayoub Injection-Date: Mon, 19 May 2014 14:55:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3091 Hi everybody ! I want to add(xor) data with CD in shape array and the result would be S Can you help me correcting this code : """" library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cdm is --generic ( -- width : natural :=4); port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic ; odata: out std_logic ; CD : in std_logic_vector(15 downto 0) ; isis :out integer range 0 to 15 ; S : inout std_logic_vector(3 downto 0 )); end entity ; architecture beh of cdm is type tab is array(3 downto 0)of std_logic_vector(15 downto 0); signal i :integer range 0 to 15 ; signal idata :std_logic ; signal itab :tab ; begin code :process(clk,rst) begin if(rst='1')then itab(i)<="0000" ; else if(clk'event and clk='1')then S(i)<=(CD(i) xor (data)); i<= i+1 ; if i=15 then idata<=data ; end if ; end if ; end if ; end process ; isis<=i; odata<=idata ; end architecture ; "" Thank you in advance for your answer !!!^^ From newsfish@newsfish Thu Aug 1 00:30:01 2024 X-Received: by 10.66.231.68 with SMTP id te4mr17570381pac.29.1400606376096; Tue, 20 May 2014 10:19:36 -0700 (PDT) X-Received: by 10.140.97.119 with SMTP id l110mr44175qge.21.1400606375918; Tue, 20 May 2014 10:19:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl10no1790742igb.0!news-out.google.com!qf4ni5721igc.0!nntp.google.com!c1no11385206igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 May 2014 10:19:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.203.78.247; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 87.203.78.247 References: <368ec752-043a-40f4-8dea-56cb9bbe3c03@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ca57374-1fdc-4b37-8b14-e787e5c3939a@googlegroups.com> Subject: Re: demande plz From: Nikolaos Kavvadias Injection-Date: Tue, 20 May 2014 17:19:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3092 Dear Ayoub, > > Hi, I don't have one at hand, but I could develop one. > > Good ;I go to see ; > because I want to have just an idea I mean that I *could* develop one, given a specific precondition. Best regards Nikolaos Kavvadias http://www.nkavvadias.com > > > > Knowing that I want to make the bpsk demodulating . > > > > Thank you . From newsfish@newsfish Thu Aug 1 00:30:01 2024 X-Received: by 10.66.216.161 with SMTP id or1mr24465213pac.38.1400687640819; Wed, 21 May 2014 08:54:00 -0700 (PDT) X-Received: by 10.140.80.5 with SMTP id b5mr59225qgd.20.1400687640700; Wed, 21 May 2014 08:54:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no12920273igq.0!news-out.google.com!qf4ni5721igc.0!nntp.google.com!c1no12920262igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 May 2014 08:54:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <679614bb-e568-418b-868c-2860a9889866@googlegroups.com> Subject: code vhdl From: Ayoub Injection-Date: Wed, 21 May 2014 15:54:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3093 Hi guys ! Can you help me correcting this code : library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cdma_testbipo is port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic ; odata: out std_logic ; type Re is array(0 to 3)of integer range 0 to 15; signal CD: Re ; isis :out integer range 0 to 3 ; S :out integer range -8 to 7 ); end entity ; architecture beh of cdma_testbipo is type RAM is array (0 to 3) of integer range -8 to 7; signal i :integer range 0 to 3 ; signal code : RAM; signal idata :std_logic ; begin code(0)<=CD(15 downto 12); code(1)<=CD(11 downto 8) ; code(2)<=CD(7 downto 4) ; code(3)<=CD(3 downto 0) ; bpsk :process(clk,rst) begin if(rst='1')then i<= 0; else if(clk'event and clk='1')then i<=i+1 ; if(idata='0') then s<=-code(i); else s<=code(i); end if; if(i=3) then idata<=data; end if; end if ; end if ; end process ; isis<=i; odata<=idata ; end architecture ; I think my problem is near :" type Re is array(0 to 3)of integer range 0 to 15; signal CD: Re ; "" Error : ""Error (10500): VHDL syntax error at cdma_testbipo.vhd(12) near text "type"; expecting an identifier ("type" is a reserved keyword), or "constant", or "file", or "signal", or "variable" "" Thank you :! From newsfish@newsfish Thu Aug 1 00:30:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: code vhdl Date: Wed, 21 May 2014 09:31:33 -0700 Organization: Highland Technology, Inc. Lines: 94 Message-ID: <20140521093133.2ce99a1c@rg.highlandtechnology.com> References: <679614bb-e568-418b-868c-2860a9889866@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="fb1f8d326b6b433116d0372735136b8e"; logging-data="15492"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/nIo+HsQvrZx55ZXPXICxb" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:GWlMRpkkgPSv4I+4V9THKqqny8w= Xref: news.eternal-september.org comp.lang.vhdl:3094 On Wed, 21 May 2014 08:54:00 -0700 (PDT) Ayoub wrote: > Hi guys ! > > > Can you help me correcting this code : > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity cdma_testbipo is > > port ( > clk : in std_logic ; > rst : in std_logic ; > data: in std_logic ; > odata: out std_logic ; > type Re is array(0 to 3)of integer range 0 to 15; > signal CD: Re ; > isis :out integer range 0 to 3 ; > S :out integer range -8 to 7 ); > end entity ; > > architecture beh of cdma_testbipo is > > type RAM is array (0 to 3) of integer range -8 to 7; > signal i :integer range 0 to 3 ; > signal code : RAM; > signal idata :std_logic ; > > begin > > code(0)<=CD(15 downto 12); > code(1)<=CD(11 downto 8) ; > code(2)<=CD(7 downto 4) ; > code(3)<=CD(3 downto 0) ; > bpsk :process(clk,rst) > begin > if(rst='1')then > i<= 0; > else > if(clk'event and clk='1')then > > i<=i+1 ; > if(idata='0') then > s<=-code(i); > else > s<=code(i); > end if; > > if(i=3) then > idata<=data; > end if; > > end if ; > end if ; > end process ; > isis<=i; > > odata<=idata ; > end architecture ; > > > I think my problem is near :" type Re is array(0 to 3)of integer range 0 to 15; > signal CD: Re ; "" > > Error : ""Error (10500): VHDL syntax error at cdma_testbipo.vhd(12) near text "type"; expecting an identifier ("type" is a reserved keyword), or "constant", or "file", or "signal", or "variable" "" > > Thank you :! A) You can't declare a type inside of a port list. A type that you need to in in a port list should be in a separate package. B) "clk'event and clk == '1'" is ancient style. You weren't even born yet when they added the rising_edge() function to the standard library. For the love of god use it. C) Whatever it is you're trying to do with "CD" and "code" is so tangled and full of misunderstandings of the language that I can't even begin to guess what it is you think it SHOULD accomplish. But an unresolved signal, such as an integer, can only have one driver. It can be in a process, or in a freefloating statement (which is just a shorthand for a process), but you can't do it in both. D) Pertinent to C, your code is entirely devoid of documentation. Therefore, not only won't you know what you're doing, but no one will know what you're doing. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:30:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: Writing testbench tools. Suggestions? Date: Thu, 22 May 2014 10:35:00 +0200 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 22 May 2014 08:35:00 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d50e3f26ee7886ceb9de424a7ed3d9fe"; logging-data="15307"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/SR4SrkfLODXSNNCKQa5fJ" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> Cancel-Lock: sha1:RQUH0zUR2y7cOEAA9204VXfzwtg= Xref: news.eternal-september.org comp.lang.vhdl:3095 On 05/14/2014 11:41 AM, Paul Uiterlinden wrote: > o pere o wrote: > >> I am trying to write some helper tools to generate testbench signals. > [snip] >> >> I would appreciate any suggestion on this. Especially, if I am making >> big mistakes! Furthermore, I have been unable to find functions that >> ease the generation of test signals, say to simulate some bursts of an >> SPI master or whatever, which is why I am writing this stuff. Any >> pointers on this? > > I would suggest reading a book like "Writing Testbenches" by Janick Bergeron > and look at the client/server model suggested there. Thanks for this pointer. I just had the opportunity to have a quick look at this book and it looks *very* promising. OTOH, I just keep wondering why there is so little material on this subject out there... Especially considering that a lot of the development effort is spent here -Janick Bargeron even puts figures into this in the book's preface: reportedly, 60% to 80% of the design effort goes into verification... Pere From newsfish@newsfish Thu Aug 1 00:30:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx33.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: PSHDL Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140521-1, 21/05/2014), Outbound message X-Antivirus-Status: Clean Lines: 14 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1400767856 86.29.12.221 (Thu, 22 May 2014 14:10:56 UTC) NNTP-Posting-Date: Thu, 22 May 2014 14:10:56 UTC Organization: virginmedia.com Date: Thu, 22 May 2014 15:10:54 +0100 X-Received-Body-CRC: 304460096 X-Received-Bytes: 1168 Xref: news.eternal-september.org comp.lang.vhdl:3096 For those that haven't seen it: http://pshdl.org/ Here is some more info on the project: http://www.youtube.com/watch?v=nTg6f6NGbZg Looks like good effort to me although I would have preferred if he used VHDL rather than developing a new language, nevertheless he gets some kudos from me. Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:30:02 2024 X-Received: by 10.236.19.7 with SMTP id m7mr12282350yhm.35.1400774587817; Thu, 22 May 2014 09:03:07 -0700 (PDT) X-Received: by 10.140.37.148 with SMTP id r20mr1149418qgr.0.1400774587663; Thu, 22 May 2014 09:03:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hl10no3513040igb.0!news-out.google.com!qf4ni5721igc.0!nntp.google.com!c1no13738487igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 May 2014 09:03:07 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Demodulator bpsk From: Ayoub Injection-Date: Thu, 22 May 2014 16:03:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3097 Hi guys ! Do you have in idea about demodulator bpsk in VHDL ! I'm not sure where to begin . Thank you in advance for your reponse From newsfish@newsfish Thu Aug 1 00:30:03 2024 X-Received: by 10.67.30.197 with SMTP id kg5mr456196pad.36.1400798163563; Thu, 22 May 2014 15:36:03 -0700 (PDT) X-Received: by 10.140.37.148 with SMTP id r20mr12830qgr.0.1400798163428; Thu, 22 May 2014 15:36:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no14215208igq.0!news-out.google.com!qf4ni5721igc.0!nntp.google.com!c1no14215199igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 May 2014 15:36:03 -0700 (PDT) In-Reply-To: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6c70ab1d-7153-4a0c-8032-7101b2344cb8@googlegroups.com> Subject: Re: Writing testbench tools. Suggestions? From: Andy Injection-Date: Thu, 22 May 2014 22:36:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3098 On Wednesday, May 14, 2014 4:41:19 AM UTC-5, Paul Uiterlinden wrote: > I would suggest reading a book like "Writing Testbenches" by Janick Berge= ron and look at the client/server model suggested there. -- Paul Uiterlinde= n www.aimvalley.nl Excellent book recommendation! However, the second edition was revised to c= over more SystemVerilog, at the expense of VHDL/Verilog. The first edition = (light blue cover, rather than red for the 2nd edition) is just VHDL & veri= log, and more appropriate if you are working on VHDL testbenches. Jim Lewis/Synthworks has an excellent advanced VHDL verification class, and= his freely available Open Source VHDL Verification Methodology (OSVVM.org)= is a huge step in the right direction. Other than being a very satisfied s= tudent, I have no connection with Synthworks.=20 The use of protected types/methods is extremely powerful for testbenches (t= oo bad they are not synthesizeable yet). The constrained randomization and = coverage packages in OSVVM provide great examples to illustrate some of the= uses of protected types. Andy From newsfish@newsfish Thu Aug 1 00:30:03 2024 X-Received: by 10.236.140.42 with SMTP id d30mr15198813yhj.2.1401252681180; Tue, 27 May 2014 21:51:21 -0700 (PDT) X-Received: by 10.50.61.170 with SMTP id q10mr335543igr.16.1401252681088; Tue, 27 May 2014 21:51:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no18799926igq.0!news-out.google.com!gi6ni15574igc.0!nntp.google.com!hl10no6598309igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 May 2014 21:51:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=196.1.105.91; posting-account=LIltwAoAAABu4LbjMvWqcvikTJr4Qyzo NNTP-Posting-Host: 196.1.105.91 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4f8a4204-46e0-4132-b207-34fb8ef1f4cc@googlegroups.com> Subject: Parallel load register 4 bit without using instantiation From: chirag.nitb@gmail.com Injection-Date: Wed, 28 May 2014 04:51:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3099 Need to design a 4 bit register with parallel loading using D flip flop . I= wrote the following code in xilinx but the simulation shows an undefined s= tate and the code does not work if the initial values of the out put are se= t to zero . Please help correcting the code=20 Here is the code=20 ---------------------------------------------------------------------------= ------- -- Company:=20 -- Engineer:=20 --=20 -- Create Date: 14:06:13 05/27/2014=20 -- Design Name:=20 -- Module Name: code - Behavioral=20 -- Project Name:=20 -- Target Devices:=20 -- Tool versions:=20 -- Description:=20 -- -- Dependencies:=20 -- -- Revision:=20 -- Revision 0.01 - File Created -- Additional Comments:=20 -- ---------------------------------------------------------------------------= ------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity code is Port ( din : in STD_LOGIC_VECTOR (3 downto 0); dout :inout STD_LOGIC_VECTOR (3 downto 0):=3D"0000"; rd,clk,rst : in STD_LOGIC); end code; architecture registerdesign of code is signal wr: STD_LOGIC; signal OPA_0, OPA_1, OPA_2, OPA_3: STD_LOGIC; signal OPB_0, OPB_1, OPB_2, OPB_3: STD_LOGIC; signal FOP_0, FOP_1, FOP_2, FOP_3: STD_LOGIC; begin wr <=3D not(rd); OPA_0 <=3D rd and dout(0); OPA_1 <=3D rd and dout(1); OPA_2 <=3D rd and dout(2); OPA_3 <=3D rd and dout(3); OPB_0 <=3D wr and din(0); OPB_1 <=3D wr and din(1); OPB_2 <=3D wr and din(2); OPB_3 <=3D wr and din(3); FOP_0 <=3D OPA_0 or OPB_0; FOP_1 <=3D OPA_1 or OPB_1; FOP_2 <=3D OPA_2 or OPB_2; FOP_3 <=3D OPA_3 or OPB_3; process(clk,rst) begin if (rst=3D'1')then dout <=3D"0000"; =09 else=20 if(clk'event and clk=3D'1')then dout(0)<=3D FOP_0; dout(1)<=3D FOP_1; dout(2)<=3D FOP_2; dout(3)<=3D FOP_3; end if; =20 end if; end process; end registerdesign; From newsfish@newsfish Thu Aug 1 00:30:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Parallel load register 4 bit without using instantiation Date: Wed, 28 May 2014 02:40:55 -0400 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: <4f8a4204-46e0-4132-b207-34fb8ef1f4cc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 May 2014 06:40:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="6601"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/D2who6uYQlLjweETF/B4P" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <4f8a4204-46e0-4132-b207-34fb8ef1f4cc@googlegroups.com> Cancel-Lock: sha1:h3jTP0iY5Amqm5JrVFegn2BeoTI= Xref: news.eternal-september.org comp.lang.vhdl:3100 On 5/28/2014 12:51 AM, chirag.nitb@gmail.com wrote: > Need to design a 4 bit register with parallel loading using D flip flop . I wrote the following code in xilinx but the simulation shows an undefined state and the code does not work if the initial values of the out put are set to zero . Please help correcting the code > > > Here is the code > > ---------------------------------------------------------------------------------- > -- Company: > -- Engineer: > lol, the -- at the beginning of a line in your code made the newsreader think it was the start of the signature. Your code will only reset the FFs if rst is equal to '1'. Do you set rst = '1' in your simulation? I don't see anything wrong with the code for the register. I would recommend that you use rising_edge(clk) rather than the clk'event, etc. but that won't cause a failure. Also, the use of these libraries is *not* recommended... use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Use numeric_std instead. If you want to know more about these recommendations, do some google searches and come back if you still have questions. -- Rick From newsfish@newsfish Thu Aug 1 00:30:04 2024 X-Received: by 10.58.234.164 with SMTP id uf4mr15602573vec.13.1401262639110; Wed, 28 May 2014 00:37:19 -0700 (PDT) X-Received: by 10.140.27.244 with SMTP id 107mr14136qgx.18.1401262638990; Wed, 28 May 2014 00:37:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl10no6638442igb.0!news-out.google.com!gi6ni15574igc.0!nntp.google.com!hl10no6638434igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 May 2014 00:37:18 -0700 (PDT) In-Reply-To: <3667EF03.D7CFC73@techno.forem.be> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.13.72.195; posting-account=YN8QFwoAAABAPoRKu1qtT_1G9FlRfdVL NNTP-Posting-Host: 129.13.72.195 References: <3667EF03.D7CFC73@techno.forem.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> Subject: Re: GPS and DCF-77, synchronised clock From: suhas sajjan Injection-Date: Wed, 28 May 2014 07:37:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3101 On Friday, 4 December 1998 09:00:00 UTC+1, Georges wrote: > Hello, > > I'm looking for vhdl programs for decoding the GPS signal or the DCF-77 > signal (an AM signal at 77.5kHz emitted in Frankfurt used for > synchronisation). > I want to do a synchronised clock on an IC, I need any information on > this subject. > Thank you for your attention. > > Gaetan Brichet > Student at the University of Liege - Belgium > brichet@stud.montefiore.ulg.ac.be Hi George, Do you have any idea regarding this project.I am doing the same and i m in need of VHDL for decoding dcf77 time signal and display it on a nixie tube which is like a 8 segment dispaly? Regards, Suhas Sajjan From newsfish@newsfish Thu Aug 1 00:30:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: GPS and DCF-77, synchronised clock Date: Wed, 28 May 2014 04:01:08 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <3667EF03.D7CFC73@techno.forem.be> <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 May 2014 08:01:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="4133"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19nfZDQDmkK5CyRh74VZq/J" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> Cancel-Lock: sha1:5V2zUVnYnK/3SluRO284AtupBLQ= Xref: news.eternal-september.org comp.lang.vhdl:3102 On 5/28/2014 3:37 AM, suhas sajjan wrote: > On Friday, 4 December 1998 09:00:00 UTC+1, Georges wrote: >> Hello, >> >> I'm looking for vhdl programs for decoding the GPS signal or the DCF-77 >> signal (an AM signal at 77.5kHz emitted in Frankfurt used for >> synchronisation). >> I want to do a synchronised clock on an IC, I need any information on >> this subject. >> Thank you for your attention. >> >> Gaetan Brichet >> Student at the University of Liege - Belgium >> brichet@stud.montefiore.ulg.ac.be > > Hi George, > > Do you have any idea regarding this project.I am doing the same and i m in need of VHDL for decoding dcf77 time signal and display it on a nixie tube which is like a 8 segment dispaly? I have not looked at DCF-77 in detail, but I believe it is very similar to the time code transmitted by NIST in the US which I am familiar with. I have designed a decoder/encoder for the IRIG-B signal which is again very similar. I can't share any of the code, but I can offer you some advice in how to proceed. You might want to be aware of two things. One is that there are commercial chips which do exactly this. I believe they are complete receivers needing only passive devices to form the antenna. The one I am thinking of decodes the US and German signals as well as the related Japanese signal. So why reinvent the wheel? Is this a project for a class rather than development of a product? btw, GPS will be a much harder task than the simple audio time codes. -- Rick From newsfish@newsfish Thu Aug 1 00:30:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.tele2net.at!news.panservice.it!feed.xsnews.nl!border02.ams.xsnews.nl!feeder01.ams.xsnews.nl!abuse.newsxs.nl!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: GPS and DCF-77, synchronised clock References: <3667EF03.D7CFC73@techno.forem.be> <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: X-Complaints-To: abuse@newsxs.nl Organization: Newsxs Date: Wed, 28 May 2014 10:11:24 +0200 Lines: 35 X-Upload: Secured through NewsXS SSL NNTP-Posting-Date: Wed, 28 May 2014 10:11:24 +0200 Xref: news.eternal-september.org comp.lang.vhdl:3103 In comp.lang.vhdl, suhas sajjan wrote: > On Friday, 4 December 1998 09:00:00 UTC+1, Georges wrote: >> Hello, >> >> I'm looking for vhdl programs for decoding the GPS signal or the DCF-77 >> signal (an AM signal at 77.5kHz emitted in Frankfurt used for >> synchronisation). >> I want to do a synchronised clock on an IC, I need any information on >> this subject. >> Thank you for your attention. >> >> Gaetan Brichet >> Student at the University of Liege - Belgium >> brichet@stud.montefiore.ulg.ac.be > > Hi George, > > Do you have any idea regarding this project.I am doing the same and i m in need of VHDL for decoding dcf77 time signal and display it on a nixie tube which is like a 8 segment dispaly? > > Regards, > Suhas Sajjan I hope he has finished his study project after 15 1/2 years! For information about DCF77, start reading here: http://en.wikipedia.org/wiki/DCF77 Also have a look at the external links. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) "I found out why my car was humming. It had forgotten the words." From newsfish@newsfish Thu Aug 1 00:30:04 2024 X-Received: by 10.58.218.232 with SMTP id pj8mr15727417vec.3.1401268800049; Wed, 28 May 2014 02:20:00 -0700 (PDT) X-Received: by 10.140.104.52 with SMTP id z49mr22418qge.12.1401268799941; Wed, 28 May 2014 02:19:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!c1no18941173igq.0!news-out.google.com!qf4ni13600igc.0!nntp.google.com!c1no18941170igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 May 2014 02:19:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.73.199.96; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 85.73.199.96 References: <3667EF03.D7CFC73@techno.forem.be> <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54430c68-0161-4182-9b8e-2c586e9a88e0@googlegroups.com> Subject: Re: GPS and DCF-77, synchronised clock From: Nikolaos Kavvadias Injection-Date: Wed, 28 May 2014 09:19:59 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3104 Hi Suhan and all, around 2012 I had implemented both a DCF77 and an MSF decoder in RTL-style = VHDL. (for the UK and German signals) The design had been put to work with success on a specific lab facility. I think there is no such open-source core, so it possible that you might be= interested. Best regards Nikolaos Kavvadias http://www.nkavvadias.com =CE=A4=CE=B7 =CE=A4=CE=B5=CF=84=CE=AC=CF=81=CF=84=CE=B7, 28 =CE=9C=CE=B1=CE= =90=CE=BF=CF=85 2014 11:11:24 =CF=80.=CE=BC. UTC+3, =CE=BF =CF=87=CF=81=CE= =AE=CF=83=CF=84=CE=B7=CF=82 Stef =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > In comp.lang.vhdl, >=20 > suhas sajjan wrote: >=20 > > On Friday, 4 December 1998 09:00:00 UTC+1, Georges wrote: >=20 > >> Hello, >=20 > >>=20 >=20 > >> I'm looking for vhdl programs for decoding the GPS signal or the DCF-7= 7 >=20 > >> signal (an AM signal at 77.5kHz emitted in Frankfurt used for >=20 > >> synchronisation). >=20 > >> I want to do a synchronised clock on an IC, I need any information on >=20 > >> this subject. >=20 > >> Thank you for your attention. >=20 > >>=20 >=20 > >> Gaetan Brichet >=20 > >> Student at the University of Liege - Belgium >=20 > >> brichet@stud.montefiore.ulg.ac.be >=20 > > >=20 > > Hi George, >=20 > > >=20 > > Do you have any idea regarding this project.I am doing the same and i m= in need of VHDL for decoding dcf77 time signal and display it on a nixie t= ube which is like a 8 segment dispaly? >=20 > > >=20 > > Regards, >=20 > > Suhas Sajjan >=20 >=20 >=20 > I hope he has finished his study project after 15 1/2 years! >=20 >=20 >=20 > For information about DCF77, start reading here: >=20 > http://en.wikipedia.org/wiki/DCF77 >=20 > Also have a look at the external links. >=20 >=20 >=20 >=20 >=20 >=20 >=20 > --=20 >=20 > Stef (remove caps, dashes and .invalid from e-mail address to reply by= mail) >=20 >=20 >=20 > "I found out why my car was humming. It had forgotten the words." Hi, From newsfish@newsfish Thu Aug 1 00:30:05 2024 X-Received: by 10.43.31.81 with SMTP id sf17mr1347437icb.4.1401319890567; Wed, 28 May 2014 16:31:30 -0700 (PDT) X-Received: by 10.140.107.35 with SMTP id g32mr68560qgf.2.1401319890477; Wed, 28 May 2014 16:31:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no7040758igb.0!news-out.google.com!qf4ni13600igc.0!nntp.google.com!c1no19521600igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 May 2014 16:31:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.11.82.92; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 46.11.82.92 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Wed, 28 May 2014 23:31:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3105 Hi, thanks a lot for the help, I managed to understand a lot and perform some simulations with success. I followed the flow chart and got the correct sequences on the logic analyser for the transmission (MOSI) Now I have this dilemma on how to amalgamate the DRDY pin of the ADC mentioned: http://datasheets.maximintegrated.com/en/ds/MAX1415-MAX1416.pdf page. 29 is the flow chart with the SPI code found here: https://www.eewiki.net/display/LOGIC/Serial+Peripheral+Interface+(SPI)+Master+(VHDL) If I understand correctly, this is used mainly when reading from MISO. Is it a good idea to use DRDY as an enable for SCLK in order to wait for the data to be ready? Or is there a better way? thanks On Thursday, 1 May 2014 13:12:23 UTC+2, Brandon Spiteri wrote: > Hi, > > I have managed to transmit some character (one after the other) using this code from; > > > > http://eewiki.net/pages/viewpage.action?pageId=4096096 > > > > I used continuous mode and I got the right characters on MOSI, one after the other, the only thing is that there are 4 clock cycles of high impedance between each 8-bit char. Is this oki? > > > > I am planning to interface with MAX1416 ADC. > > > > > > Also, I need to simulate an SPI input coming from the ADC. What is the best way to do it? > > > > Shall I use the same method I used for transmitting but this time in the test bench? > > > > I am using quartus and ModelSim. > > > > thanks From newsfish@newsfish Thu Aug 1 00:30:05 2024 X-Received: by 10.42.206.77 with SMTP id ft13mr1559816icb.22.1401326773956; Wed, 28 May 2014 18:26:13 -0700 (PDT) X-Received: by 10.182.63.7 with SMTP id c7mr1411obs.28.1401326773631; Wed, 28 May 2014 18:26:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hl10no7068214igb.0!news-out.google.com!qf4ni17234igc.0!nntp.google.com!c1no19574040igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 May 2014 18:26:13 -0700 (PDT) In-Reply-To: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <101eea39-688c-48cf-8d5f-2881712bd4f0@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: KJ Injection-Date: Thu, 29 May 2014 01:26:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3106 I would suggest that you use DRDY as an input to the 'user logic' that drives the SPI controller. It should not be used to directly modify SCLK, that defeats the purpose of re-using an existing design. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:05 2024 X-Received: by 10.182.22.133 with SMTP id d5mr2466931obf.27.1401352567583; Thu, 29 May 2014 01:36:07 -0700 (PDT) X-Received: by 10.140.38.199 with SMTP id t65mr13458qgt.17.1401352567476; Thu, 29 May 2014 01:36:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no19791027igq.0!news-out.google.com!qf4ni17234igc.0!nntp.google.com!c1no19791021igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 01:36:07 -0700 (PDT) In-Reply-To: <101eea39-688c-48cf-8d5f-2881712bd4f0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.11.82.92; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 46.11.82.92 References: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> <101eea39-688c-48cf-8d5f-2881712bd4f0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <692f46df-8211-46b4-89ac-4c2b6e2c2f45@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Thu, 29 May 2014 08:36:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3107 thanks for the fast reply. What do you think of this modification of spi.vhdl with DRDY ? WHEN execute => busy <= '1'; --set busy signal ss_n(slave) <= '0'; --set proper slave select output --system clock to sclk ratio is met IF(count = clk_ratio) THEN count <= 1; --reset system-to-spi clock counter assert_data <= NOT assert_data; --switch transmit/receive indicator IF(clk_toggles = d_width*2 + 1) THEN -- (==17) clk_toggles <= 0; --reset spi clock toggles counter ELSE clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter END IF; --spi clock toggle needed IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN sclk <= NOT sclk; --toggle spi clock END IF; --receive spi clock toggle IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0' AND DRDY = '0') THEN rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit END IF; --transmit spi clock toggle IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN mosi <= tx_buffer(d_width-1); --clock out data bit tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer END IF; --last data receive, but continue IF(clk_toggles = last_bit_rx AND cont = '1' AND DRDY = '0') THEN tx_buffer <= tx_data; --reload transmit buffer clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter continue <= '1'; --set continue flag END IF; --normal end of transaction, but continue IF(continue = '1') THEN continue <= '0'; --clear continue flag busy <= '0'; --clock out signal that first receive data is ready rx_data <= rx_buffer; --clock out received data to output port END IF; --end of transaction IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN busy <= '0'; --clock out not busy signal ss_n <= (OTHERS => '1'); --set all slave selects high mosi <= 'Z'; --set mosi output high impedance rx_data <= rx_buffer; --clock out received data to output port state <= ready; --return to ready state ELSE --not end of transaction state <= execute; --remain in execute state END IF; ELSE --system clock to sclk ratio not met count <= count + 1; --increment counter state <= execute; --remain in execute state END IF; On Thursday, 29 May 2014 03:26:13 UTC+2, KJ wrote: > I would suggest that you use DRDY as an input to the 'user logic' that drives the SPI controller. It should not be used to directly modify SCLK, that defeats the purpose of re-using an existing design. > > > > Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:06 2024 X-Received: by 10.182.109.231 with SMTP id hv7mr3557236obb.2.1401381393299; Thu, 29 May 2014 09:36:33 -0700 (PDT) X-Received: by 10.140.96.41 with SMTP id j38mr180091qge.8.1401381393040; Thu, 29 May 2014 09:36:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no7376417igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no20116983igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 09:36:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.193.64.121; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 46.193.64.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> Subject: Multiplication VHDL From: Ayoub Injection-Date: Thu, 29 May 2014 16:36:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3108 Hi, I have problems with my vhdl code.=20 can you help me plz=20 This is the code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity correla is port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic_vector(11 downto 0) ; code: in std_logic_vector(15 downto 0 ) ; =20 Q :out std_logic_vector(17 downto 0) ) ; end entity ; architecture arch of correla is =20 =20 type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ; signal CD : RAM; signal temp :integer range 0 to 15; =20 signal idata :std_logic_vector(11 downto 0) ; signal sum :integer range 0 to 16 ; signal AB :integer range 0 to 17 ; =20 begin =20 CD(0)<=3D(code(15 downto 12)); CD(1)<=3D(code(11 downto 8)) ; CD(2)<=3D(code(7 downto 4 )); CD(3)<=3D(code(3 downto 0)); =20 =E9talement:process(clk,rst) =20 begin=20 if(rst=3D'1') then=20 Q <=3D(others=3D>'0'); =20 temp<=3D0; AB <=3D0; =20 else=20 if(clk'event and clk =3D'1') then=20 sum<=3D0; =20 for i in 0 to 3 loop=20 temp(i)<=3Dto_integer(data(i)*CD(i)) ; sum(i)<=3Dsum(i) +temp(i) ; i<=3D i+1 ; if(i=3D3) then=20 idata<=3Ddata; end if; end loop ; =20 AB<=3Dsum ; Q<=3Dstd_logic_vector(AB) ; =20 =20 =20 end if ; end if ; =20 =20 =20 =20 end process ; end architecture ;=20 Thanks a lot=20 From newsfish@newsfish Thu Aug 1 00:30:06 2024 X-Received: by 10.236.144.136 with SMTP id n8mr3641983yhj.22.1401396954096; Thu, 29 May 2014 13:55:54 -0700 (PDT) X-Received: by 10.50.142.104 with SMTP id rv8mr571847igb.13.1401396953962; Thu, 29 May 2014 13:55:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl10no7492176igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no20289757igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 13:55:53 -0700 (PDT) In-Reply-To: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Multiplication VHDL From: Jim Lewis Injection-Date: Thu, 29 May 2014 20:55:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3109 Ayoub It looks like you are doing a college exercise. Multiplication is nothing more than Y <= A * B ; If you need some help with that or with pipelining, see the papers, "VHDL Math tricks of the Trade" and "Coding a 40 x 40 Multipler" at http://www.synthworks.com/papers/index.htm Best Regards, Jim From newsfish@newsfish Thu Aug 1 00:30:06 2024 X-Received: by 10.236.19.7 with SMTP id m7mr2603506yhm.35.1401397359296; Thu, 29 May 2014 14:02:39 -0700 (PDT) X-Received: by 10.50.25.4 with SMTP id y4mr283914igf.10.1401397359157; Thu, 29 May 2014 14:02:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl10no7495252igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no20294035igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 14:02:38 -0700 (PDT) In-Reply-To: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <61b9f7fe-3db5-46a1-93a6-9a78bb9f3e24@googlegroups.com> Subject: Re: Multiplication VHDL From: Jim Lewis Injection-Date: Thu, 29 May 2014 21:02:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3110 Ayoub The objects temp, data, and sum are not arrays. If you did not intend to index these and instead you intended the scalar value to update between iterations of your for loop, then they will need to be variables. Best Regards, Jim From newsfish@newsfish Thu Aug 1 00:30:06 2024 X-Received: by 10.182.58.71 with SMTP id o7mr5046963obq.3.1401413802942; Thu, 29 May 2014 18:36:42 -0700 (PDT) X-Received: by 10.182.137.129 with SMTP id qi1mr981obb.37.1401413802765; Thu, 29 May 2014 18:36:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no7569982igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no20426640igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 18:36:42 -0700 (PDT) In-Reply-To: <692f46df-8211-46b4-89ac-4c2b6e2c2f45@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> <101eea39-688c-48cf-8d5f-2881712bd4f0@googlegroups.com> <692f46df-8211-46b4-89ac-4c2b6e2c2f45@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <11d5751f-8830-4cea-bf43-2ca28b7ac699@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: KJ Injection-Date: Fri, 30 May 2014 01:36:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3111 On Thursday, May 29, 2014 4:36:07 AM UTC-4, Brandon Spiteri wrote: > thanks for the fast reply. What do you think of this modification of spi.= vhdl=20 > with DRDY ? >=20 I think=20 - You completely ignored my suggestion to use DRDY as an input to the 'user= logic' that drives the SPI controller. - Assuming you started from known working SPI controller code, you've hobbl= ed it at best to make it into something that will only work under very spec= ial circumstances. Had you followed my suggestion, your new code would be generating the follo= wing outputs from a 'User_Logic' entity: - Enable, Addr and Tx_Data. How these are generated could be made to be a = function of Drdy. - You would likely have to only define constants for the following outputs:= cpol, cpha, cont and clk_div. The 'User_Logic' entity would then be connected to the 'Spi_Master' entity.= Then as you think of other requirements you would modify 'User_Logic' som= e more until everything is working properly. Some modifications like: - What should you do if DRDY never comes back? You have no timeout, probab= ly a hard reset is the only escape - Do you really want every SPI operation to depend on DRDY? The basic idea is that if you have some known working code for some widget,= and you modify it, you're more likely to break it then to improve it if yo= u didn't write it yourself in the first place. Instead, you should present= an interface to the widget (i.e. the entity) that encourages one to use th= e widget, not modify the widget. The SPI_Master interface looks like it pr= esented a simple address/data interface with handshaking that would be fair= ly easy to understand then simply use. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:07 2024 X-Received: by 10.236.99.7 with SMTP id w7mr7133984yhf.4.1401501207243; Fri, 30 May 2014 18:53:27 -0700 (PDT) X-Received: by 10.50.73.98 with SMTP id k2mr28779igv.0.1401501207145; Fri, 30 May 2014 18:53:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no8064879igb.0!news-out.google.com!gi6ni17440igc.0!nntp.google.com!hl10no8064871igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 May 2014 18:53:26 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=205.175.97.117; posting-account=IgXoAQkAAABjWBXMvqT0qPYUz09IMzj4 NNTP-Posting-Host: 205.175.97.117 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Subject: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? From: kaiyutony@gmail.com Injection-Date: Sat, 31 May 2014 01:53:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3112 Any Help Will Be Appreciated! I wrote this module in order to keep track of the score (<=3D 99) for a gam= e written in verilog and runs on a LED Array. I want it to be able to maint= ain a max score. When the current count is greater than maxcount, the maxco= unt will be equal to the current count, else it keeps its value. The Problem is, I do not know why the maxcount changes its value whenever c= ount changes (It cannot keep its value when count is less, but instead beco= me less along with the count) Is there any logical error? Or is there any Verilog Error that I missed? Thank you very much! module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, h= ex2); input Clock, Reset; input signed [3:0] pt_0, pt_1, pt_2, pt_3; output [6:0] hex1, hex0, hex3, hex2; wire signed [6:0] count; wire signed [6:0] maxcount; score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount= ); display(count, maxcount, hex1, hex0, hex3, hex2); endmodule=20 module display (count, maxcount, hex1, hex0, hex3, hex2); input [6:0] count, maxcount; output [6:0] hex1, hex0, hex3, hex2; wire [4:0] unit, unit_m; wire [4:0] tens, tens_m; assign unit =3D count % 10; assign tens =3D count / 10; assign unit_m =3D count % 10; assign tens_m =3D count / 10; seg7 ud (unit, hex0); seg7 td (tens, hex1); seg7 umd (unit_m, hex2); seg7 tmd (tens_m, hex3); endmodule=20 module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount)= ; input Clock, Reset; //input signed [3:0] sum; input [3:0] pt_0, pt_1, pt_2, pt_3; parameter signed [3:0] no_point =3D 4'b0000, plus_one =3D 4'b0001, plus= _two =3D 4'b0010, neg_two =3D 4'b1110; //input zero, negative, carry, overflow; output signed [6:0] count, maxcount; reg signed [6:0] count, maxcount; ////wire PS; //reg NS; always @(posedge Clock) if (Reset) begin count <=3D 7'b0; maxcount <=3D 7'b0; end else begin if (count > maxcount) begin maxcount <=3D count; end=20 if (pt_0 =3D=3D neg_two) begin if (count < 2) begin count <=3D 7'b0; end else begin count <=3D count - 2; end end else begin count <=3D count + pt_0; if (count > 7'b100010) begin count <=3D 7'b0; end end if (pt_1 =3D=3D neg_two) begin if (count < 2) begin count <=3D 7'b0; end else begin count <=3D count - 2; end end else begin count <=3D count + pt_1; if (count > 7'b100010) begin count <=3D 7'b0; end end if (pt_2 =3D=3D neg_two) begin if (count < 2) begin count <=3D 7'b0; end else begin count <=3D count - 2; end end else begin count <=3D count + pt_2; if (count > 7'b100010) begin count <=3D 7'b0; end end if (pt_3 =3D=3D neg_two) begin if (count < 2) begin count <=3D 7'b0; end else begin count <=3D count - 2; end end else begin count <=3D count + pt_3; if (count > 7'b100010) begin count <=3D 7'b0; end end end endmodule From newsfish@newsfish Thu Aug 1 00:30:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? Date: Sat, 31 May 2014 01:39:52 -0400 Organization: A noiseless patient Spider Lines: 135 Message-ID: References: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 31 May 2014 05:39:54 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="31857"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18MF956QYhRry/O/elFbX9p" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Cancel-Lock: sha1:dQJRdAwi/mvQMILWrYg2KEeUUbc= Xref: news.eternal-september.org comp.lang.vhdl:3113 I'm not an expert in Verilog, but I don't see anything obvious in the code. I do see two possible issues. One is that maxcount is passed into display, but not used for anything. Are unit_m and tens_m supposed to be updated from maxcount? Is that where you are checking the value of maxcount? The other is that maxcount is declared as both an output and a reg. In VHDL that does not work. Is that ok in Verilog? Rick On 5/30/2014 9:53 PM, kaiyutony@gmail.com wrote: > Any Help Will Be Appreciated! > > I wrote this module in order to keep track of the score (<= 99) for a game written in verilog and runs on a LED Array. I want it to be able to maintain a max score. When the current count is greater than maxcount, the maxcount will be equal to the current count, else it keeps its value. > > The Problem is, I do not know why the maxcount changes its value whenever count changes (It cannot keep its value when count is less, but instead become less along with the count) > > Is there any logical error? Or is there any Verilog Error that I missed? > > Thank you very much! > > module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2); > input Clock, Reset; > input signed [3:0] pt_0, pt_1, pt_2, pt_3; > output [6:0] hex1, hex0, hex3, hex2; > > wire signed [6:0] count; > wire signed [6:0] maxcount; > score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount); > > display(count, maxcount, hex1, hex0, hex3, hex2); > > endmodule > > module display (count, maxcount, hex1, hex0, hex3, hex2); > input [6:0] count, maxcount; > output [6:0] hex1, hex0, hex3, hex2; > > wire [4:0] unit, unit_m; > wire [4:0] tens, tens_m; > > assign unit = count % 10; > assign tens = count / 10; > > assign unit_m = count % 10; > assign tens_m = count / 10; > > seg7 ud (unit, hex0); > seg7 td (tens, hex1); > seg7 umd (unit_m, hex2); > seg7 tmd (tens_m, hex3); > > > endmodule > > module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount); > input Clock, Reset; > //input signed [3:0] sum; > input [3:0] pt_0, pt_1, pt_2, pt_3; > parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110; > //input zero, negative, carry, overflow; > > output signed [6:0] count, maxcount; > reg signed [6:0] count, maxcount; > > ////wire PS; > //reg NS; > > always @(posedge Clock) > if (Reset) begin > count <= 7'b0; > maxcount <= 7'b0; > end else begin > if (count > maxcount) begin > maxcount <= count; > end > if (pt_0 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_0; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_1 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_1; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_2 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_2; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_3 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_3; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > end > endmodule > -- Rick From newsfish@newsfish Thu Aug 1 00:30:07 2024 X-Received: by 10.43.56.134 with SMTP id wc6mr1147167icb.17.1401614608028; Sun, 01 Jun 2014 02:23:28 -0700 (PDT) X-Received: by 10.50.110.42 with SMTP id hx10mr190770igb.0.1401614607897; Sun, 01 Jun 2014 02:23:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!hl10no8390627igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no21799673igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Jun 2014 02:23:27 -0700 (PDT) In-Reply-To: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? From: Dio Gratia Injection-Date: Sun, 01 Jun 2014 09:23:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3114 Perhaps you could try in comp.lang.verilog. VHDL stands for VHSIC Hardware Design Language, not Verilog Hardware Design Language. The former is typically referred to as VHDL, while the latter is sometimes referred to as Verilog HDL, or just Verilog. From newsfish@newsfish Thu Aug 1 00:30:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp4-2.free.fr!not-for-mail Date: Sun, 01 Jun 2014 21:49:51 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Multiplication VHDL References: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> In-Reply-To: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 26 Message-ID: <538b83e0$0$2176$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 01 Jun 2014 21:49:52 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1401652192 news-2.free.fr 2176 88.185.146.198:1167 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3115 Le 29/05/2014 18:36, Ayoub a crit : > Hi, > > I have problems with my vhdl code. Maybe if you described the problems you have we'd be able to help you. > code: in std_logic_vector(15 downto 0 ) ; ... > type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ; > signal CD : RAM; ... > CD(0)<=(code(15 downto 12)); > CD(1)<=(code(11 downto 8)) ; > CD(2)<=(code(7 downto 4 )); > CD(3)<=(code(3 downto 0)); Now here we have a problem. RAM is defined as an array of 4 16-bits std_logic_vector, and you try to assign 4 bits to each of these 16-bits element. I haven't looked any further but this must be fixed. Nicolas From newsfish@newsfish Thu Aug 1 00:30:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? Date: Sun, 01 Jun 2014 21:12:42 -0400 Organization: A noiseless patient Spider Lines: 133 Message-ID: References: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 2 Jun 2014 01:12:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="42d31eb8e7ba6748611c57063fee3e99"; logging-data="19157"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GA+CmKg7yhtGH6QNnPyaW" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Cancel-Lock: sha1:lYVpN+bv3tSIfXRfiVcC7ib4UXA= Xref: news.eternal-september.org comp.lang.vhdl:3116 comp.lang.verilog:891 On 5/30/2014 9:53 PM, kaiyutony@gmail.com wrote: > Any Help Will Be Appreciated! > > I wrote this module in order to keep track of the score (<= 99) for a game written in verilog and runs on a LED Array. I want it to be able to maintain a max score. When the current count is greater than maxcount, the maxcount will be equal to the current count, else it keeps its value. > > The Problem is, I do not know why the maxcount changes its value whenever count changes (It cannot keep its value when count is less, but instead become less along with the count) > > Is there any logical error? Or is there any Verilog Error that I missed? > > Thank you very much! > > module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2); > input Clock, Reset; > input signed [3:0] pt_0, pt_1, pt_2, pt_3; > output [6:0] hex1, hex0, hex3, hex2; > > wire signed [6:0] count; > wire signed [6:0] maxcount; > score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount); > > display(count, maxcount, hex1, hex0, hex3, hex2); > > endmodule > > module display (count, maxcount, hex1, hex0, hex3, hex2); > input [6:0] count, maxcount; > output [6:0] hex1, hex0, hex3, hex2; > > wire [4:0] unit, unit_m; > wire [4:0] tens, tens_m; > > assign unit = count % 10; > assign tens = count / 10; > > assign unit_m = count % 10; > assign tens_m = count / 10; > > seg7 ud (unit, hex0); > seg7 td (tens, hex1); > seg7 umd (unit_m, hex2); > seg7 tmd (tens_m, hex3); > > > endmodule > > module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount); > input Clock, Reset; > //input signed [3:0] sum; > input [3:0] pt_0, pt_1, pt_2, pt_3; > parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110; > //input zero, negative, carry, overflow; > > output signed [6:0] count, maxcount; > reg signed [6:0] count, maxcount; > > ////wire PS; > //reg NS; > > always @(posedge Clock) > if (Reset) begin > count <= 7'b0; > maxcount <= 7'b0; > end else begin > if (count > maxcount) begin > maxcount <= count; > end > if (pt_0 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_0; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_1 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_1; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_2 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_2; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_3 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_3; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > end > endmodule > There's nothing obvious to me. Is it failing in behavioral simulation or only in hardware (you did simulate, right)? I've had issues with signed arithmetic in Verilog, but in this case count and maxcount have the same type, so I don't see an issue with the logic. Could there be a problem with synchronization to the clock? All inputs need to be synchronous to the clock, especially Reset. Obviously a Reset pulse could cause maxcount to go down. -- Gabor From newsfish@newsfish Thu Aug 1 00:30:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? Date: Sun, 01 Jun 2014 21:31:44 -0400 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 2 Jun 2014 01:31:45 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="24127"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IT2Adf85hKw2Y3DTLj7cn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: Cancel-Lock: sha1:g2yB77jqp6UXERDgu+rT525b9ng= Xref: news.eternal-september.org comp.lang.vhdl:3117 comp.lang.verilog:892 On 6/1/2014 9:12 PM, Gabor wrote: > assign unit_m = count % 10; > assign tens_m = count / 10; I think the problem are these lines. He didn't say how he was checking the result, but I bet it was by looking at the display of unit_m and tens_m. I bet we never hear back from him... -- Rick From newsfish@newsfish Thu Aug 1 00:30:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Re: Verilog or VLDL? Date: Wed, 04 Jun 2014 20:58:26 -0400 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <02bb614c-9866-4fea-a4fa-d321bbdd5605@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 5 Jun 2014 00:58:25 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="3081"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+gwkfWlvaBePvZ+uBWyq2Y" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <02bb614c-9866-4fea-a4fa-d321bbdd5605@googlegroups.com> Cancel-Lock: sha1:5pgByiPdrKjMFlcHEjBNhhB518c= Xref: news.eternal-september.org comp.lang.verilog:894 comp.lang.vhdl:3118 On 6/4/2014 5:06 PM, dhruvin bhadani wrote: > helooo sir, > > i am intrested in VLSI as a carrer, and i dont know with what should i start, with verilog? or VLHD? and i also dont knw any computer language much , i know basic C and little bit of core JAVA, hoping for your positive response I would recommend that you be fluent in both HDLs. In particular know how the problems and shortcomings of each language. Neither is hard to learn, but finding the problems each one creates is not so easy. VHDL has a steeper learning curve, but I think Verilog is harder to learn it's issues. I'm cross posting so you can get feedback from both groups. I hope all replies are to this branch of the thread. -- Rick From newsfish@newsfish Thu Aug 1 00:30:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder2.news.elisa.fi!uutiset.elisa.fi!7564ea0f!not-for-mail From: Kim Enkovaara User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Re: Verilog or VLDL? References: <02bb614c-9866-4fea-a4fa-d321bbdd5605@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 30 Message-ID: <4FTjv.43606$SH2.32503@uutiset.elisa.fi> Date: Thu, 05 Jun 2014 08:57:21 +0300 NNTP-Posting-Host: 138.111.130.175 X-Complaints-To: newsmaster@saunalahti.com X-Trace: uutiset.elisa.fi 1401947840 138.111.130.175 (Thu, 05 Jun 2014 08:57:20 EEST) NNTP-Posting-Date: Thu, 05 Jun 2014 08:57:20 EEST Organization: Elisa Customer Xref: news.eternal-september.org comp.lang.verilog:895 comp.lang.vhdl:3119 On 5.6.2014 3:58, rickman wrote: > On 6/4/2014 5:06 PM, dhruvin bhadani wrote: >> helooo sir, >> >> i am intrested in VLSI as a carrer, and i dont know with what should i >> start, with verilog? or VLHD? and i also dont knw any computer >> language much , i know basic C and little bit of core JAVA, hoping for >> your positive response > > I would recommend that you be fluent in both HDLs. In particular know > how the problems and shortcomings of each language. Neither is hard to > learn, but finding the problems each one creates is not so easy. VHDL > has a steeper learning curve, but I think Verilog is harder to learn > it's issues. > > I'm cross posting so you can get feedback from both groups. I hope all > replies are to this branch of the thread. I agree that both languages are important. I have not seen for a long time design that would not have both languages (verilog/sv + vhdl) but I'm on the Europe side of the pond ;) The language is quite minor part of the design, more important is to understand what logic the RTL generates. For real ASIC stuff etc. schematic level understanding is also quite important (getting netlist simulations to work, metal fixes, tinkering at gate level for last timings etc.). If you understand digital design and its principles the language is just a way to express those ideas. --Kim From newsfish@newsfish Thu Aug 1 00:30:09 2024 X-Received: by 10.224.12.14 with SMTP id v14mr23485177qav.8.1401980492871; Thu, 05 Jun 2014 08:01:32 -0700 (PDT) X-Received: by 10.182.153.200 with SMTP id vi8mr198824obb.23.1401980492719; Thu, 05 Jun 2014 08:01:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no1716372qaq.1!news-out.google.com!gi6ni19621igc.0!nntp.google.com!h18no751659igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Jun 2014 08:01:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=209.118.190.4; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 209.118.190.4 References: <02bb614c-9866-4fea-a4fa-d321bbdd5605@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0dfe98b8-291f-4aa7-8499-7bc1e2949add@googlegroups.com> Subject: Re: Verilog or VLDL? From: Jim Lewis Injection-Date: Thu, 05 Jun 2014 15:01:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1370 X-Received-Body-CRC: 310395520 Xref: news.eternal-september.org comp.lang.vhdl:3120 Hi, If you know where you want to work and who you are interested in working for, look at what they currently use, if you can ask them if they plan on changing. Then learn that. While it is nice to be general, I would put my first focus on a job you want. Jim From newsfish@newsfish Thu Aug 1 00:30:10 2024 X-Received: by 10.50.18.20 with SMTP id s20mr4206178igd.3.1402096351165; Fri, 06 Jun 2014 16:12:31 -0700 (PDT) X-Received: by 10.140.38.199 with SMTP id t65mr61401qgt.17.1402096351122; Fri, 06 Jun 2014 16:12:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!h18no1011744igc.0!news-out.google.com!k18ni6553qav.1!nntp.google.com!hw13no5064918qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Jun 2014 16:12:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.99.164.46; posting-account=sAdkPAoAAACGN9LhffdAv3Mpxzde2fYO NNTP-Posting-Host: 188.99.164.46 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Job - Promotion - 2D/3D Bildverarbeitug - FPGA From: sim2a2z@googlemail.com Injection-Date: Fri, 06 Jun 2014 23:12:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3121 Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Am Institut f=FCr Parallele und Verteilte Systeme der Universit=E4t Stuttga= rt ist ab sofort eine Stelle f=FCr wiss. Mitarbeiter / wiss. Mitarbeiterin = Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf= dem folgenden Gebiet: Echtzeit-Bildverarbeitung zur schnellen messtechnischen=20 2D/3D Erfassung aufsteigender Blasen Voraussetzung ist ein =FCberdurchschnittlicher Abschluss in einem Studium d= er Informatik, Elektrotechnik, Physik oder einem verwandten Gebiet. Vertief= te Kenntnisse im Bereich FPGA-Entwurf oder der Technischen Informatik sind = von Vorteil. Wir bieten eine attraktive Arbeitsumgebung im internationalen = Umfeld mit einem hervorragend ausgestatteten Arbeitsplatz.=20 Anstellung und Verg=FCtung erfolgen nach TV-L, Verg. Gr. 13. Die Forschungs= t=E4tigkeit bietet die M=F6glichkeit zur Promotion. Die Universit=E4t Stuttgart m=F6chte den Anteil der Frauen im wissenschaftl= ichen Bereich erh=F6hen und ist deshalb an Bewerbungen von Frauen besonders= interessiert. Schwerbehinderte werden bei gleicher Eignung vorrangig einge= stellt. Bitte schicken Sie Ihre Bewerbung in elektronischer Form an: applic= ation-pas@ipvs.uni-stuttgart.de Professor Dr.-Ing. Sven Simon Universit=E4t Stuttgart Institut f=FCr Parallele und Verteilte Systeme Abteilung Parallele Systeme Universit=E4tsstr. 38 70569 Stuttgart Tel.: +49-711-685-88450 Email: application-pas@ipvs.uni-stuttgart.de From newsfish@newsfish Thu Aug 1 00:30:10 2024 X-Received: by 10.236.202.143 with SMTP id d15mr74753yho.18.1402133987396; Sat, 07 Jun 2014 02:39:47 -0700 (PDT) X-Received: by 10.140.91.245 with SMTP id z108mr356qgd.16.1402133987328; Sat, 07 Jun 2014 02:39:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.albasani.net!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!j5no2068238qaq.1!news-out.google.com!k18ni6554qav.1!nntp.google.com!j5no2068237qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Jun 2014 02:39:47 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.112.194.42; posting-account=-bKUXwoAAABskFGI8l3tcZRKpFmG6DfT NNTP-Posting-Host: 80.112.194.42 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Ethernet Switch on Configurable Logic now available From: Logixa Injection-Date: Sat, 07 Jun 2014 09:39:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3122 Now available from our Opencores.org repository a highly configurable Ethernet Switch for FPGA implementations. Check http://opencores.org/project,esoc for more details. From newsfish@newsfish Thu Aug 1 00:30:10 2024 X-Received: by 10.236.24.196 with SMTP id x44mr191201yhx.15.1402734899497; Sat, 14 Jun 2014 01:34:59 -0700 (PDT) X-Received: by 10.140.48.101 with SMTP id n92mr3935qga.15.1402734899409; Sat, 14 Jun 2014 01:34:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no1162980qae.1!news-out.google.com!q9ni6501qaj.0!nntp.google.com!w8no1418054qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 14 Jun 2014 01:34:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4cd2212d-9782-46a2-aba2-92ce84be32a5@googlegroups.com> Subject: Hash 256 function From: niv Injection-Date: Sat, 14 Jun 2014 08:34:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1660 X-Received-Body-CRC: 522616185 Xref: news.eternal-september.org comp.lang.vhdl:3123 Trying to build a standard HASh256 function based on some web articles I've read. Generally it takes 64 steps per message slice, & I have a sample printout-out of the 8 intermediate register (a to h) values for the 64 steps for the simple (hex) message X"61626380" I don't get the expected intermediate value(s). I thought the8 regs were initialised to '0's, then apply the first 16 words with the K(i) constant, then the remaining 48 words from the message expander. Finally, the 8 regs are then added to the 8 pre-initialised Hash regs (H0 to H7) I thought the first a reg value would just be thesum of K(0) & the first message word, but it isn't. Anyone tell me where I'm going wrong please? From newsfish@newsfish Thu Aug 1 00:30:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: VHDL 2008/ PSL Verification: Book Recommendation Date: Tue, 17 Jun 2014 15:56:29 +0200 Organization: A noiseless patient Spider Lines: 20 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 17 Jun 2014 13:55:11 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="12312"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18tHFopkWocnbYyMLbGSeOB" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 Cancel-Lock: sha1:SHiFRFoh+rVG8qhjR1xXgq9zPK0= Xref: news.eternal-september.org comp.lang.vhdl:3125 Hi, I'm trying to improve my verification processes for VHDL designs and IP cores with VHDL 2008 and PSL. Therefore I used "The designers guide to VHDL - Third Edition" (Peter J. Ashenden). Now I want to go further and need some more specific literature. Maybe someone has a hint which book is recommendable to buy? There are two references in the Ashenden book: [1] A Practical Introduction to PSL, C. Eisner and D. Fisman, 2006 [2] Assertion-Based Design, H. D. Foster et al, 2003 Are there any other good books on the market you can suggest? Thanks a lot! Best regards Tobias From newsfish@newsfish Thu Aug 1 00:30:11 2024 X-Received: by 10.43.65.4 with SMTP id xk4mr7605435icb.12.1403029515631; Tue, 17 Jun 2014 11:25:15 -0700 (PDT) X-Received: by 10.140.47.15 with SMTP id l15mr489096qga.5.1403029515594; Tue, 17 Jun 2014 11:25:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!a13no6735706igq.0!news-out.google.com!q9ni6501qaj.0!nntp.google.com!w8no4853742qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 17 Jun 2014 11:25:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.32.177.252; posting-account=zwwrhQoAAABkSgLoXR0QdgJVC-UJXTHy NNTP-Posting-Host: 185.32.177.252 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> Subject: Help needed debugging high impedance on RAM read From: David Kaplan Injection-Date: Tue, 17 Jun 2014 18:25:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3126 Hi I'm having an issue with a cpu that I'm building and no matter what I try, I can't seem to resolve it (so any help would greatly be appreciated): Basically, when I issue a POP instruction, my processor will read from RAM at the stack pointer address (minus 1). However, the value does not appear on the tristate data bus (it remains in hi-Z); even though it seems to be successfully read from RAM. You can see the issue in the simulation screenie: https://www.dropbox.com/s/s9ctbcpqilzzqmc/pop1.bmp At 110ns mmu1/ram_data is '11111111', however mem_data remains hi-Z (and therefore r0 is hi-Z). The code is at: https://github.com/DepletionMode/cupcake/blob/master/cpu/cpu.vhd https://github.com/DepletionMode/cupcake/blob/master/cpu/mmu.vhd https://github.com/DepletionMode/cupcake/blob/master/cpu/simpleram.vhd Apologies for the quality of the code; VHDL isn't my thing (I'm learning I guess.. :)) Thanks in advance! :) From newsfish@newsfish Thu Aug 1 00:30:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!lightspeed!lightspeed.eweka.nl!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf04.am4!fx30.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008/ PSL Verification: Book Recommendation References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140617-1, 17/06/2014), Outbound message X-Antivirus-Status: Clean Lines: 39 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1403086029 86.29.12.221 (Wed, 18 Jun 2014 10:07:09 UTC) NNTP-Posting-Date: Wed, 18 Jun 2014 10:07:09 UTC Organization: virginmedia.com Date: Wed, 18 Jun 2014 11:07:06 +0100 X-Received-Body-CRC: 2580723100 X-Received-Bytes: 2429 Xref: news.eternal-september.org comp.lang.vhdl:3127 On 17/06/2014 14:56, Tobias Baumann wrote: > Hi, > > I'm trying to improve my verification processes for VHDL designs and IP > cores with VHDL 2008 and PSL. Therefore I used "The designers guide to > VHDL - Third Edition" (Peter J. Ashenden). Now I want to go further and > need some more specific literature. > > Maybe someone has a hint which book is recommendable to buy? There are > two references in the Ashenden book: > > [1] A Practical Introduction to PSL, C. Eisner and D. Fisman, 2006 > [2] Assertion-Based Design, H. D. Foster et al, 2003 > > Are there any other good books on the market you can suggest? > > Thanks a lot! > > Best regards > Tobias > Hi Tobias, I have Ben Cohen's book which is OKish but I only started to appreciate PSL (or I hope I do) after going onto a PSL course. I know they are not particular cheap but it will get you up to speed in just a few days. There is no problem learning PSL (or SVA) from a book but there are certain constructs like multiple clocks which you really need to have explained (multiple times in my case) by an expert. I would suggest you look into sequences and the cover directive first so that you can impress your boss with some quick functional coverage, then ask for about a training budget.....;-) Good luck, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:30:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008/ PSL Verification: Book Recommendation Date: Wed, 18 Jun 2014 16:09:42 +0200 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 18 Jun 2014 14:08:25 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="6294"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18GTuDwAXK9q3J0OKSs92LL" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:08VaXDCOXK8oJyqMrOTn/mfaC/s= Xref: news.eternal-september.org comp.lang.vhdl:3128 Am 18.06.2014 12:07, schrieb HT-Lab: > I have Ben Cohen's book which is OKish but I only started to appreciate > PSL (or I hope I do) after going onto a PSL course. I know they are not > particular cheap but it will get you up to speed in just a few days. > There is no problem learning PSL (or SVA) from a book but there are > certain constructs like multiple clocks which you really need to have > explained (multiple times in my case) by an expert. > > I would suggest you look into sequences and the cover directive first so > that you can impress your boss with some quick functional coverage, then > ask for about a training budget.....;-) > Hello Hans, thank you for sharing your experiences. I think if I want to visit a PSL course, my boss would let me go. But honestly, I'm a person who needs to learn autodidactically, at least the basics. If I have a good basic knowledge, then it makes sense to go deeper with courses. So maybe the Ben Cohen book is a good start. If not - 60$ is not the world :) Thanks a lot, Tobias From newsfish@newsfish Thu Aug 1 00:30:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!newsfeed2.funet.fi!newsfeeds.funet.fi!news.utu.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Help needed debugging high impedance on RAM read Date: Wed, 18 Jun 2014 17:23:23 +0300 Lines: 20 Message-ID: References: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> NNTP-Posting-Host: coffee.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1403101409 16272 2001:708:310:3430:213:21ff:fe1b:b396 (18 Jun 2014 14:23:29 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Wed, 18 Jun 2014 14:23:29 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:WjZmg2q8TFv1At+lxt0ohLmAbA0= Xref: news.eternal-september.org comp.lang.vhdl:3129 David Kaplan writes: > Basically, when I issue a POP instruction, my processor will read from RAM at the stack pointer address (minus 1). However, the value does not appear on the tristate data bus (it remains in hi-Z); even though it seems to be successfully read from RAM. > > You can see the issue in the simulation screenie: > > https://www.dropbox.com/s/s9ctbcpqilzzqmc/pop1.bmp > > At 110ns mmu1/ram_data is '11111111', however mem_data remains hi-Z (and therefore r0 is hi-Z). Well, with a (very) quick look, your mem_data control requires zero in mem_wr and mem_en but you have zero only in mem_en so mem_data remains Z. So I guess your tristating isn't really correct then? Do you really need this and do you really need both enable and write enable for RAM? > Apologies for the quality of the code; VHDL isn't my thing (I'm learning I guess.. :)) It seems a little odd with the white space and I hate it when people wrap their if conditions in useless brackets. Oh, I also like active low signals to end in _n but maybe that's just my preference. From newsfish@newsfish Thu Aug 1 00:30:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Help needed debugging high impedance on RAM read Date: Wed, 18 Jun 2014 18:16:00 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 18 Jun 2014 22:16:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="17210"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199MkvuYDhTPJREdWGDiEvs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> Cancel-Lock: sha1:YKmiMMpZucH/PExhuXFTg+gS2Fg= Xref: news.eternal-september.org comp.lang.vhdl:3130 On 6/17/2014 2:25 PM, David Kaplan wrote: > Hi > > I'm having an issue with a cpu that I'm building and no matter what I try, I can't seem to resolve it (so any help would greatly be appreciated): > > Basically, when I issue a POP instruction, my processor will read from RAM at the stack pointer address (minus 1). However, the value does not appear on the tristate data bus (it remains in hi-Z); even though it seems to be successfully read from RAM. > > You can see the issue in the simulation screenie: > > https://www.dropbox.com/s/s9ctbcpqilzzqmc/pop1.bmp > > At 110ns mmu1/ram_data is '11111111', however mem_data remains hi-Z (and therefore r0 is hi-Z). > > The code is at: > > https://github.com/DepletionMode/cupcake/blob/master/cpu/cpu.vhd > https://github.com/DepletionMode/cupcake/blob/master/cpu/mmu.vhd > https://github.com/DepletionMode/cupcake/blob/master/cpu/simpleram.vhd > > Apologies for the quality of the code; VHDL isn't my thing (I'm learning I guess.. :)) > > Thanks in advance! :) Try looking at your write enable inside the ram module. I think the sense is reversed somewhere. Also, in the read process of the MMU is purely combinatorial, but you have not completely specified all the cases in the IFs and CASE statements. That generate latches where they are not intended. An easy way to fix this is to include a single assignment outside of all the conditional code that sets a default. data_out <= 0x"ff"; -- Rick From newsfish@newsfish Thu Aug 1 00:30:13 2024 X-Received: by 10.236.19.7 with SMTP id m7mr688662yhm.35.1403137261874; Wed, 18 Jun 2014 17:21:01 -0700 (PDT) X-Received: by 10.50.17.100 with SMTP id n4mr33908igd.3.1403137261678; Wed, 18 Jun 2014 17:21:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no6156371qac.0!news-out.google.com!qf4ni6igc.0!nntp.google.com!hn18no309285igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Jun 2014 17:21:01 -0700 (PDT) In-Reply-To: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4bd8deff-9b7b-4964-ad42-e8951b8b8b32@googlegroups.com> Subject: Re: Help needed debugging high impedance on RAM read From: Dio Gratia Injection-Date: Thu, 19 Jun 2014 00:21:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3238 X-Received-Body-CRC: 3968116736 Xref: news.eternal-september.org comp.lang.vhdl:3131 On Wednesday, June 18, 2014 6:25:15 AM UTC+12, David Kaplan wrote: > At 110ns mmu1/ram_data is '11111111', however mem_data remains hi-Z (and = therefore r0 is hi-Z). >=20 The read process in mmu has ram_data on the right hand side of a conditiona= l signal assignment statement but ram_data isn't in the sensitivity list. What happens if the ram_data goes valid (non-'Z') in the next delta cycle f= ollowing some combination of events on n_wr, n_en and addr? You'll have as= signed data_out to the ram_data (others =3D> 'Z'). Until another transacti= on on n_wr, n_en or addr data_out will remain all 'Z's. Try putting ram_data in the sensitivity list. (This is speculation. It's t= oo much work to write an mmu test bench to test the hypothesis. The operat= ive delay would be the delta delay assigning ram_we - else '0'.) I also notice that simple_ram_tb_1 transitions the address while the ram en= able and write are both true, in general a no-no in an asynchronous RAM (de= spite the presence of a clock in the test bench). The reason for this is b= ecause you can have different propagation times for address signals and cou= ld corrupt RAM contents. The issue wouldn't show up in a zero time single = dimension array type representation simulation. It also says at some point you should be concerned with ram_we to ram_addr = delay as well as ram_addr to ram_we delay (t=3D85ns to t=3D90ns in your BMP= ). Perhaps you could 'form' the write enable? Also because the write occurs in 5 ns, you might consider using a synchrono= us RAM which would cure any potential issues anyway. Trying to find or crea= te two other clock phases to form both edges of ram_we could be tough in an= FPGA at that speed and I'd suspect an FPGA vendor would point you at a syn= chronous RAM. You'd be highly dependent on routing to get the holdovers wo= rking. (In other words a 200 MHz internal RAM may not be a simple RAM). Or is the clock rate a polite fiction at this point? I didn't see any actu= al specs on your web site. From newsfish@newsfish Thu Aug 1 00:30:13 2024 X-Received: by 10.182.226.166 with SMTP id rt6mr817814obc.47.1403137579503; Wed, 18 Jun 2014 17:26:19 -0700 (PDT) X-Received: by 10.50.60.7 with SMTP id d7mr44683igr.10.1403137579316; Wed, 18 Jun 2014 17:26:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!r2no4384454igi.0!news-out.google.com!gf2ni1igb.0!nntp.google.com!r2no4384440igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Jun 2014 17:26:18 -0700 (PDT) In-Reply-To: <4bd8deff-9b7b-4964-ad42-e8951b8b8b32@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> <4bd8deff-9b7b-4964-ad42-e8951b8b8b32@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54569bd1-9e32-4fac-b00f-53e2d7729491@googlegroups.com> Subject: Re: Help needed debugging high impedance on RAM read From: Dio Gratia Injection-Date: Thu, 19 Jun 2014 00:26:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3132 On Thursday, June 19, 2014 12:21:01 PM UTC+12, Dio Gratia wrote: > Try putting ram_data in the sensitivity list. (This is speculation. It's too much work to write an mmu test bench to test the hypothesis. The operative delay would be the delta delay assigning ram_we - else '0'.) And I see you already implemented the sensitivity list change: https://github.com/DepletionMode/cupcake/commit/e836c96016e253fd6d44d73d629fdf46ab794405 From newsfish@newsfish Thu Aug 1 00:30:13 2024 X-Received: by 10.236.35.5 with SMTP id t5mr2684149yha.9.1403196872376; Thu, 19 Jun 2014 09:54:32 -0700 (PDT) X-Received: by 10.50.103.104 with SMTP id fv8mr151630igb.2.1403196872192; Thu, 19 Jun 2014 09:54:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!xlned.com!feeder1.xlned.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.85.216.88.MISMATCH!i13no6469754qae.1!news-out.google.com!gf2ni6igb.0!nntp.google.com!hn18no1198530igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Jun 2014 09:54:31 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.195; posting-account=8_pC6AoAAACWbtLE3A_sMKwe3ztVOfyh NNTP-Posting-Host: 119.235.52.195 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9d89d4a0-97fa-4aca-be09-bab6300c7b60@googlegroups.com> Subject: Graphic Design Company in Chennai From: pmptraining66@gmail.com Injection-Date: Thu, 19 Jun 2014 16:54:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3133 Postlor Interactive is the best Graphic Design Company in Chennai, India specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com/ From newsfish@newsfish Thu Aug 1 00:30:14 2024 X-Received: by 10.58.67.129 with SMTP id n1mr1712656vet.35.1403280788819; Fri, 20 Jun 2014 09:13:08 -0700 (PDT) X-Received: by 10.140.95.176 with SMTP id i45mr79539qge.10.1403280788800; Fri, 20 Jun 2014 09:13:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no7287602qae.1!news-out.google.com!a8ni10892qaq.1!nntp.google.com!w8no7541345qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Jun 2014 09:13:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=149.156.64.122; posting-account=tsG57AoAAAD-1jped8Dtw3E8dJDyinwH NNTP-Posting-Host: 149.156.64.122 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0788f3e7-44bb-483c-aafe-4bc8f29a7864@googlegroups.com> Subject: Simple counter in verilog (Lattice MachXO2 7000H) From: krzysztof.pelczar@gmail.com Injection-Date: Fri, 20 Jun 2014 16:13:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2122 X-Received-Body-CRC: 3310269923 Xref: news.eternal-september.org comp.lang.vhdl:3134 Hi, I am working on a simple multi-channel pulse counter. The pulses counted ar= e infrequent (up to 100 kHz), and slow (at least 1 us), coming form a compa= rator. In total I have 20 parallel channels (identical). Every 0.5 s I read= out the counters and reset them to 0 using SPI. The counter code is simple, contained in a module: ... reg [17:0] counter_ripple_high; always @(posedge slow_gate, posedge reset) begin : b1 /*synopsys resource r0: map_to_module =3D "DW01_inc", implementation =3D "csa", ops =3D "inc1";*/ if (reset) counter_ripple_high <=3D 18'b0; else counter_ripple_high <=3D counter_ripple_high + 1'b1; // synopsys label in= c1 end assign counter =3D counter_ripple_high; ... Some channels (not more than 3 out of 20) count two times the input frequen= cy. How is it possible? One channel is not counting properly at all. I woul= d expect the latter to be obviously caused by the speed of arithmetic logic= , but the former..? I am looking forward for your opinions. Regards, Krzysztof From newsfish@newsfish Thu Aug 1 00:30:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Simple counter in verilog (Lattice MachXO2 7000H) Date: Fri, 20 Jun 2014 13:13:41 -0400 Organization: Alacron, Inc. Lines: 3 Message-ID: References: <0788f3e7-44bb-483c-aafe-4bc8f29a7864@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 20 Jun 2014 17:15:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="30419"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/H7JYMQfavQxQVbcOSgNSAfMFOWKNXctE=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <0788f3e7-44bb-483c-aafe-4bc8f29a7864@googlegroups.com> Cancel-Lock: sha1:mdl7orSZKPvZzaTmLSiQPTEC6TE= Xref: news.eternal-september.org comp.lang.vhdl:3135 Cross-posted. See thread in comp.lang.verilog From newsfish@newsfish Thu Aug 1 00:30:14 2024 X-Received: by 10.42.229.194 with SMTP id jj2mr3777660icb.18.1403699143249; Wed, 25 Jun 2014 05:25:43 -0700 (PDT) X-Received: by 10.50.112.36 with SMTP id in4mr207525igb.7.1403699143128; Wed, 25 Jun 2014 05:25:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no9372447igb.0!news-out.google.com!gf2ni11igb.0!nntp.google.com!hn18no10704372igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Jun 2014 05:25:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=198.182.52.26; posting-account=DmMQNwoAAAAW6z46wNj7BIBvw750QZWq NNTP-Posting-Host: 198.182.52.26 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5cfdcb37-07e0-4960-aeb7-1dce7e9ace7d@googlegroups.com> Subject: Predefined Attributes From: NK Injection-Date: Wed, 25 Jun 2014 12:25:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3136 IS 'element a Predefined Attributes similar to 'Range ? From newsfish@newsfish Thu Aug 1 00:30:15 2024 X-Received: by 10.66.144.228 with SMTP id sp4mr6760737pab.5.1403750836918; Wed, 25 Jun 2014 19:47:16 -0700 (PDT) X-Received: by 10.140.50.131 with SMTP id s3mr73547qga.7.1403750836867; Wed, 25 Jun 2014 19:47:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!hn18no12114173igb.0!news-out.google.com!q9ni968qaj.0!nntp.google.com!i13no754758qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Jun 2014 19:47:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Why does it use shared variable? From: fl Injection-Date: Thu, 26 Jun 2014 02:47:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3137 Hi, When I learn Modelsim, I find that there is shared variable in its single port memory example. Every architecture of sp_syn_ram has its SHARED VARIABLE mem : mem_type; I do not see one mem variable accessed by other process signals. I only copy two architectures below of the four similar structures. Do you think what purpose it uses shared variable here? Thanks, ......................... ARCHITECTURE constrainedintarch OF sp_syn_ram IS SUBTYPE constrained_int is integer range 0 to 2**data_width-1; TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; SHARED VARIABLE mem : mem_type; BEGIN ASSERT data_width <= 32 REPORT "### Illegal data width detected" SEVERITY failure; control_proc : PROCESS (inclk, outclk) VARIABLE inner_addr : integer; VARIABLE outer_addr : integer; BEGIN IF (inclk'event AND inclk = '1') THEN IF (we = '1') THEN mem(to_integer(addr)) := to_integer(unsigned(data_in)); END IF; END IF; IF (outclk'event AND outclk = '1') THEN data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); END IF; END PROCESS; END constrainedintarch; ARCHITECTURE \3D\ OF sp_syn_ram IS TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer; SHARED VARIABLE mem : mem_type; BEGIN control_proc : PROCESS (inclk, outclk) VARIABLE inner_addr : integer; VARIABLE outer_addr : integer; BEGIN IF (inclk'event AND inclk = '1') THEN inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); IF (we = '1') THEN mem(outer_addr, inner_addr) := to_integer(unsigned(data_in)); END IF; END IF; IF (outclk'event AND outclk = '1') THEN inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length)); END IF; END PROCESS; END \3D\; From newsfish@newsfish Thu Aug 1 00:30:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? Date: Thu, 26 Jun 2014 09:59:09 -0400 Organization: Alacron, Inc. Lines: 80 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 26 Jun 2014 14:02:56 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="5925"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Ic5C+o0JBXQFDObr+oj/Mo1cv3hD0fQQ=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:hmSgi4DCvRAtV3Rn44Lt8oQocFQ= Xref: news.eternal-september.org comp.lang.vhdl:3138 fl wrote: > Hi, > When I learn Modelsim, I find that there is shared variable in its single port > memory example. Every architecture of sp_syn_ram has its > SHARED VARIABLE mem : mem_type; > > I do not see one mem variable accessed by other process signals. > > I only copy two architectures below of the four similar structures. > > Do you think what purpose it uses shared variable here? > > Thanks, > > > > ......................... > ARCHITECTURE constrainedintarch OF sp_syn_ram IS > > SUBTYPE constrained_int is integer range 0 to 2**data_width-1; > TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; > SHARED VARIABLE mem : mem_type; > > BEGIN > > ASSERT data_width <= 32 > REPORT "### Illegal data width detected" > SEVERITY failure; > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > IF (we = '1') THEN > mem(to_integer(addr)) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); > END IF; > END PROCESS; > > END constrainedintarch; > > > ARCHITECTURE \3D\ OF sp_syn_ram IS > > TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer; > SHARED VARIABLE mem : mem_type; > > BEGIN > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > IF (we = '1') THEN > mem(outer_addr, inner_addr) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length)); > END IF; > END PROCESS; > > END \3D\; Just a guess, perhaps the one-port memory example was chopped down from a two-port memory example? -- Gabor From newsfish@newsfish Thu Aug 1 00:30:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx02.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140626-1, 26/06/2014), Outbound message X-Antivirus-Status: Clean Lines: 85 Message-ID: <54Xqv.464124$Mx1.439821@fx02.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1403796865 86.29.12.221 (Thu, 26 Jun 2014 15:34:25 UTC) NNTP-Posting-Date: Thu, 26 Jun 2014 15:34:25 UTC Organization: virginmedia.com Date: Thu, 26 Jun 2014 16:34:24 +0100 X-Received-Body-CRC: 4133677316 X-Received-Bytes: 3746 Xref: news.eternal-september.org comp.lang.vhdl:3139 On 26/06/2014 03:47, fl wrote: > Hi, > When I learn Modelsim, I find that there is shared variable in its single port > memory example. Every architecture of sp_syn_ram has its > SHARED VARIABLE mem : mem_type; > > I do not see one mem variable accessed by other process signals. There are 2 different clocks, one for reading and one for writing used in the same process. Run the simulation and check the result, next change the shared variable to a signal and see what happens, Good luck, Hans. www.ht-lab.com > > I only copy two architectures below of the four similar structures. > > Do you think what purpose it uses shared variable here? > > Thanks, > > > > ......................... > ARCHITECTURE constrainedintarch OF sp_syn_ram IS > > SUBTYPE constrained_int is integer range 0 to 2**data_width-1; > TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; > SHARED VARIABLE mem : mem_type; > > BEGIN > > ASSERT data_width <= 32 > REPORT "### Illegal data width detected" > SEVERITY failure; > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > IF (we = '1') THEN > mem(to_integer(addr)) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); > END IF; > END PROCESS; > > END constrainedintarch; > > > ARCHITECTURE \3D\ OF sp_syn_ram IS > > TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer; > SHARED VARIABLE mem : mem_type; > > BEGIN > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > IF (we = '1') THEN > mem(outer_addr, inner_addr) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length)); > END IF; > END PROCESS; > > END \3D\; > From newsfish@newsfish Thu Aug 1 00:30:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx07.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Predefined Attributes References: <5cfdcb37-07e0-4960-aeb7-1dce7e9ace7d@googlegroups.com> In-Reply-To: <5cfdcb37-07e0-4960-aeb7-1dce7e9ace7d@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140626-1, 26/06/2014), Outbound message X-Antivirus-Status: Clean Lines: 13 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1403798119 86.29.12.221 (Thu, 26 Jun 2014 15:55:19 UTC) NNTP-Posting-Date: Thu, 26 Jun 2014 15:55:19 UTC Organization: virginmedia.com Date: Thu, 26 Jun 2014 16:55:18 +0100 X-Received-Body-CRC: 2350826076 X-Received-Bytes: 1228 Xref: news.eternal-september.org comp.lang.vhdl:3140 On 25/06/2014 13:25, NK wrote: > IS 'element a Predefined Attributes similar to 'Range ? > Yes, see: http://stackoverflow.com/questions/21907520/get-range-attribute-of-array-subtype-in-vhdl Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:30:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? Date: Thu, 26 Jun 2014 14:58:20 -0400 Organization: Alacron, Inc. Lines: 100 Message-ID: References: <54Xqv.464124$Mx1.439821@fx02.am4> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 26 Jun 2014 19:02:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="15643"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18dT7cNEuRwHOEA2VR/OOnvcNinKdEJE8g=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <54Xqv.464124$Mx1.439821@fx02.am4> Cancel-Lock: sha1:nF0a7WNEJitOCoL2SFlnC4A5kqs= Xref: news.eternal-september.org comp.lang.vhdl:3141 HT-Lab wrote: > On 26/06/2014 03:47, fl wrote: >> Hi, >> When I learn Modelsim, I find that there is shared variable in its >> single port >> memory example. Every architecture of sp_syn_ram has its >> SHARED VARIABLE mem : mem_type; >> >> I do not see one mem variable accessed by other process signals. > > There are 2 different clocks, one for reading and one for writing used > in the same process. Run the simulation and check the result, next > change the shared variable to a signal and see what happens, > > Good luck, > Hans. > www.ht-lab.com > >> >> I only copy two architectures below of the four similar structures. >> >> Do you think what purpose it uses shared variable here? >> >> Thanks, >> >> >> >> ......................... >> ARCHITECTURE constrainedintarch OF sp_syn_ram IS >> >> SUBTYPE constrained_int is integer range 0 to 2**data_width-1; >> TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; >> SHARED VARIABLE mem : mem_type; >> >> BEGIN >> >> ASSERT data_width <= 32 >> REPORT "### Illegal data width detected" >> SEVERITY failure; >> >> control_proc : PROCESS (inclk, outclk) >> VARIABLE inner_addr : integer; >> VARIABLE outer_addr : integer; >> BEGIN >> IF (inclk'event AND inclk = '1') THEN >> IF (we = '1') THEN >> mem(to_integer(addr)) := to_integer(unsigned(data_in)); >> END IF; >> END IF; >> >> IF (outclk'event AND outclk = '1') THEN >> data_out <= >> std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); >> END IF; >> END PROCESS; >> >> END constrainedintarch; >> >> >> ARCHITECTURE \3D\ OF sp_syn_ram IS >> >> TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF >> integer; >> SHARED VARIABLE mem : mem_type; >> >> BEGIN >> >> control_proc : PROCESS (inclk, outclk) >> VARIABLE inner_addr : integer; >> VARIABLE outer_addr : integer; >> BEGIN >> IF (inclk'event AND inclk = '1') THEN >> inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); >> outer_addr := to_integer(addr(addr_width-1 DOWNTO >> addr_width-2)); >> IF (we = '1') THEN >> mem(outer_addr, inner_addr) := >> to_integer(unsigned(data_in)); >> END IF; >> END IF; >> >> IF (outclk'event AND outclk = '1') THEN >> inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); >> outer_addr := to_integer(addr(addr_width-1 DOWNTO >> addr_width-2)); >> data_out <= std_logic_vector(to_unsigned(mem(outer_addr, >> inner_addr), data_out'length)); >> END IF; >> END PROCESS; >> >> END \3D\; >> > I think the question was about sharing, rather than whether this should be a signal. i.e. if it's only used in one process, why does the variable "mem" need to be shared? -- Gabor From newsfish@newsfish Thu Aug 1 00:30:16 2024 X-Received: by 10.58.209.227 with SMTP id mp3mr8993642vec.29.1403809504269; Thu, 26 Jun 2014 12:05:04 -0700 (PDT) X-Received: by 10.182.143.4 with SMTP id sa4mr22075obb.38.1403809504003; Thu, 26 Jun 2014 12:05:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!i13no1255782qae.1!news-out.google.com!gf2ni200igb.0!nntp.google.com!hn18no13500196igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Jun 2014 12:05:03 -0700 (PDT) In-Reply-To: <54Xqv.464124$Mx1.439821@fx02.am4> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <54Xqv.464124$Mx1.439821@fx02.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why does it use shared variable? From: Andy Injection-Date: Thu, 26 Jun 2014 19:05:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3142 On Thursday, June 26, 2014 10:34:24 AM UTC-5, HT-Lab wrote: > There are 2 different clocks, one for reading and one for writing used in the same process. Run the simulation and check the result, next change the shared variable to a signal and see what happens, Good luck, Hans. I think the OP was referring to changing the shared variable to a local variable declared in the process, not to a signal. A local variable would behave exactly the same as the shared variable in this context. Using a shared variable, IINM, allows the memory content to be accessed with a hierarchical reference, say in a testbench, etc. Local variables do not allow that (yet). Andy From newsfish@newsfish Thu Aug 1 00:30:17 2024 X-Received: by 10.43.151.207 with SMTP id kt15mr9434746icc.15.1403831523616; Thu, 26 Jun 2014 18:12:03 -0700 (PDT) X-Received: by 10.182.220.133 with SMTP id pw5mr228obc.30.1403831523389; Thu, 26 Jun 2014 18:12:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!hn18no13954106igb.0!news-out.google.com!gf2ni202igb.0!nntp.google.com!uq10no12626108igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Jun 2014 18:12:02 -0700 (PDT) In-Reply-To: <54Xqv.464124$Mx1.439821@fx02.am4> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.21.248.204; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 72.21.248.204 References: <54Xqv.464124$Mx1.439821@fx02.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ba338ef-d2ee-4b80-8e96-0710c9297590@googlegroups.com> Subject: Re: Why does it use shared variable? From: KJ Injection-Date: Fri, 27 Jun 2014 01:12:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3143 Unless the two clocks are actually the same clock, there should be no difference when using variables or signals in the posted code...but as noted by others signal vs variable did not appear to be the point of the OP. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!talisker.lacave.net!lacave.net!feeder.erje.net!eu.feeder.erje.net!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx05.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? References: <54Xqv.464124$Mx1.439821@fx02.am4> <0ba338ef-d2ee-4b80-8e96-0710c9297590@googlegroups.com> In-Reply-To: <0ba338ef-d2ee-4b80-8e96-0710c9297590@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140626-2, 26/06/2014), Outbound message X-Antivirus-Status: Clean Lines: 15 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1403858680 86.29.12.221 (Fri, 27 Jun 2014 08:44:40 UTC) NNTP-Posting-Date: Fri, 27 Jun 2014 08:44:40 UTC Organization: virginmedia.com Date: Fri, 27 Jun 2014 09:44:36 +0100 X-Received-Body-CRC: 1217973053 X-Received-Bytes: 1573 Xref: news.eternal-september.org comp.lang.vhdl:3144 On 27/06/2014 02:12, KJ wrote: > Unless the two clocks are actually the same clock, there should be no difference when using variables or signals in the posted code...but as noted by others signal vs variable did not appear to be the point of the OP. > > Kevin Jennings > you are all correct, I misread the OP's question. A shared variable in this case is not required and a local process variable should behave the same. Regards, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:30:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Markus Michel Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? Date: Sun, 29 Jun 2014 21:00:59 +0200 Organization: A noiseless patient Spider Lines: 82 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 29 Jun 2014 19:00:59 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="931432146a9ecb6d48ecc33a58ac477b"; logging-data="9274"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+GnViaUaXwp1BlgQw5E8hB" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:f9tADhSMfeBCAK7ti4tEB/ckStA= Xref: news.eternal-september.org comp.lang.vhdl:3145 Am 26.06.2014 04:47, schrieb fl: > Hi, > When I learn Modelsim, I find that there is shared variable in its single port > memory example. Every architecture of sp_syn_ram has its > SHARED VARIABLE mem : mem_type; > > I do not see one mem variable accessed by other process signals. > > I only copy two architectures below of the four similar structures. > > Do you think what purpose it uses shared variable here? > > Thanks, > > > > ......................... > ARCHITECTURE constrainedintarch OF sp_syn_ram IS > > SUBTYPE constrained_int is integer range 0 to 2**data_width-1; > TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; > SHARED VARIABLE mem : mem_type; > > BEGIN > > ASSERT data_width <= 32 > REPORT "### Illegal data width detected" > SEVERITY failure; > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > IF (we = '1') THEN > mem(to_integer(addr)) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); > END IF; > END PROCESS; > > END constrainedintarch; > > > ARCHITECTURE \3D\ OF sp_syn_ram IS > > TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer; > SHARED VARIABLE mem : mem_type; > > BEGIN > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > IF (we = '1') THEN > mem(outer_addr, inner_addr) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length)); > END IF; > END PROCESS; > > END \3D\; > signals have attributes which the simulator must maintain. (shared) variables do not. This makes simulation (much) faster. Like signals, shared variables can be used for communication between processes. Regards, Markus From newsfish@newsfish Thu Aug 1 00:30:17 2024 X-Received: by 10.236.92.69 with SMTP id i45mr6483448yhf.20.1404314238780; Wed, 02 Jul 2014 08:17:18 -0700 (PDT) X-Received: by 10.182.128.131 with SMTP id no3mr112276obb.9.1404314238667; Wed, 02 Jul 2014 08:17:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no5256365qac.0!news-out.google.com!gf2ni2855igb.0!nntp.google.com!uq10no863908igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Jul 2014 08:17:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=120.56.167.175; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 120.56.167.175 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> Subject: Synthesis issues in Merkle Hellman Knapsack Cryptosystems From: Gandalf Injection-Date: Wed, 02 Jul 2014 15:17:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2316 X-Received-Body-CRC: 2245080976 Xref: news.eternal-september.org comp.lang.vhdl:3146 Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained a r= andom number generator but I'm stuck on the Transmitter part. I've written = this code : entity Knapsack_Tx is port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic; data:std_logic_vector;cip:out std_logic_vector(7 downto 0)); end Knapsack_Tx; =20 architecture Encipher of Knapsack_Tx is type rndnum is array(7 downto 0) of std_logic; type easy is array(7 downto 0) of std_logic; --type index is array (0 to 7) of integer; function elf(rnum:rndnum) return easy is=20 variable knap1:easy; variable i: integer :=3D 0; variable rnum1 : rndnum :=3Drnum; variable int1, int2 :integer :=3D0; begin =09 int1:=3D to_integer(rnum1(i-1)); int2:=3D to_integer(rnum1(i)); for i in 0 to 7 loop if int1 <=3D int2 then knap1(i) :=3D rnum1(i); end if; end loop; return knap1; end function elf; begin end architecture Encipher; The rnum1 variable is an array which is used to store the random values obt= ained from the RNG. The code is obviously incomplete but essentially it rev= olves around this. Check Syntax reveals that to_integer is not recognised. = If anyone can help it would be nice :) From newsfish@newsfish Thu Aug 1 00:30:18 2024 X-Received: by 10.182.125.4 with SMTP id mm4mr30678198obb.49.1404316766464; Wed, 02 Jul 2014 08:59:26 -0700 (PDT) X-Received: by 10.182.165.36 with SMTP id yv4mr111815obb.18.1404316766360; Wed, 02 Jul 2014 08:59:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hn18no1961282igb.0!news-out.google.com!gf2ni2855igb.0!nntp.google.com!uq10no878470igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Jul 2014 08:59:26 -0700 (PDT) In-Reply-To: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=166.20.224.10; posting-account=Hhan4goAAAC6R91Dbv381087p9kjKRkY NNTP-Posting-Host: 166.20.224.10 References: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> Subject: Re: Synthesis issues in Merkle Hellman Knapsack Cryptosystems From: Russell Merrick Injection-Date: Wed, 02 Jul 2014 15:59:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3147 On Wednesday, July 2, 2014 11:17:18 AM UTC-4, Gandalf wrote: > Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained a= random number generator but I'm stuck on the Transmitter part. I've writte= n this code : >=20 > entity Knapsack_Tx is >=20 > port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic; >=20 > data:std_logic_vector;cip:out std_logic_vector(7 downto 0)); >=20 > end Knapsack_Tx; =20 >=20 >=20 >=20 >=20 >=20 > architecture Encipher of Knapsack_Tx is >=20 >=20 >=20 > type rndnum is array(7 downto 0) of std_logic; >=20 > type easy is array(7 downto 0) of std_logic; >=20 > --type index is array (0 to 7) of integer; >=20 >=20 >=20 >=20 >=20 >=20 >=20 >=20 >=20 > function elf(rnum:rndnum) return easy is=20 >=20 >=20 >=20 > variable knap1:easy; >=20 > variable i: integer :=3D 0; >=20 > variable rnum1 : rndnum :=3Drnum; >=20 > variable int1, int2 :integer :=3D0; >=20 >=20 >=20 > begin >=20 > =09 >=20 > int1:=3D to_integer(rnum1(i-1)); >=20 > int2:=3D to_integer(rnum1(i)); >=20 >=20 >=20 > for i in 0 to 7 loop >=20 > if int1 <=3D int2 then >=20 > knap1(i) :=3D rnum1(i); >=20 > end if; >=20 > end loop; >=20 >=20 >=20 > return knap1; >=20 >=20 >=20 > end function elf; >=20 >=20 >=20 > begin >=20 >=20 >=20 >=20 >=20 > end architecture Encipher; >=20 >=20 >=20 > The rnum1 variable is an array which is used to store the random values o= btained from the RNG. The code is obviously incomplete but essentially it r= evolves around this. Check Syntax reveals that to_integer is not recognised= . If anyone can help it would be nice :) First of all, why are you creating an array of std_logic? Just use a std_l= ogic_vector. You should be including std_logic_1164 package file. =20 Once that's complete, use the numeric_std package file for your math. =20 Your conversion will be: output <=3D to_integer(unsigned(input_slv)); Read more about how to convert std_logic_vector to integer and why using st= d_logic_arith is a bad idea. http://www.nandland.com/vhdl/tips/tip-convert= -numeric-std-logic-vector-to-integer.html From newsfish@newsfish Thu Aug 1 00:30:18 2024 X-Received: by 10.52.121.13 with SMTP id lg13mr1127570vdb.8.1404363591943; Wed, 02 Jul 2014 21:59:51 -0700 (PDT) X-Received: by 10.50.25.168 with SMTP id d8mr782569igg.1.1404363591691; Wed, 02 Jul 2014 21:59:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no5448372qae.1!news-out.google.com!bp9ni2742igb.0!nntp.google.com!uq10no1106094igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Jul 2014 21:59:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=121.1.60.114; posting-account=SpxwwwoAAAAuxDZPgTWiDB6veugmX1-d NNTP-Posting-Host: 121.1.60.114 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: MEGAWIZARD PLUG IN From: edgedetection fpga Injection-Date: Thu, 03 Jul 2014 04:59:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1112 X-Received-Body-CRC: 553425998 Xref: news.eternal-september.org comp.lang.vhdl:3148 what is the default adder of addition in megawizard plugin??? like ripple carry,. or can we modify it to assign what kind of adder will be used? From newsfish@newsfish Thu Aug 1 00:30:18 2024 X-Received: by 10.43.94.71 with SMTP id bx7mr4072974icc.2.1404365301082; Wed, 02 Jul 2014 22:28:21 -0700 (PDT) X-Received: by 10.50.45.67 with SMTP id k3mr412257igm.1.1404365300989; Wed, 02 Jul 2014 22:28:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hn18no2331330igb.0!news-out.google.com!bp9ni2742igb.0!nntp.google.com!uq10no1111777igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Jul 2014 22:28:20 -0700 (PDT) In-Reply-To: <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.27.8.45; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 103.27.8.45 References: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <04208bb3-7e0e-4a47-892d-b5aa4a5a63fe@googlegroups.com> Subject: Re: Synthesis issues in Merkle Hellman Knapsack Cryptosystems From: Gandalf Injection-Date: Thu, 03 Jul 2014 05:28:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3149 On Wednesday, July 2, 2014 9:29:26 PM UTC+5:30, Russell wrote: > On Wednesday, July 2, 2014 11:17:18 AM UTC-4, Gandalf wrote: >=20 > > Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained= a random number generator but I'm stuck on the Transmitter part. I've writ= ten this code : >=20 > >=20 >=20 > > entity Knapsack_Tx is >=20 > >=20 >=20 > > port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic; >=20 > >=20 >=20 > > data:std_logic_vector;cip:out std_logic_vector(7 downto 0)); >=20 > >=20 >=20 > > end Knapsack_Tx; =20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > architecture Encipher of Knapsack_Tx is >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > type rndnum is array(7 downto 0) of std_logic; >=20 > >=20 >=20 > > type easy is array(7 downto 0) of std_logic; >=20 > >=20 >=20 > > --type index is array (0 to 7) of integer; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > function elf(rnum:rndnum) return easy is=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > variable knap1:easy; >=20 > >=20 >=20 > > variable i: integer :=3D 0; >=20 > >=20 >=20 > > variable rnum1 : rndnum :=3Drnum; >=20 > >=20 >=20 > > variable int1, int2 :integer :=3D0; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > begin >=20 > >=20 >=20 > > =09 >=20 > >=20 >=20 > > int1:=3D to_integer(rnum1(i-1)); >=20 > >=20 >=20 > > int2:=3D to_integer(rnum1(i)); >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > for i in 0 to 7 loop >=20 > >=20 >=20 > > if int1 <=3D int2 then >=20 > >=20 >=20 > > knap1(i) :=3D rnum1(i); >=20 > >=20 >=20 > > end if; >=20 > >=20 >=20 > > end loop; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > return knap1; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > end function elf; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > begin >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > end architecture Encipher; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > The rnum1 variable is an array which is used to store the random values= obtained from the RNG. The code is obviously incomplete but essentially it= revolves around this. Check Syntax reveals that to_integer is not recognis= ed. If anyone can help it would be nice :) >=20 >=20 >=20 > First of all, why are you creating an array of std_logic? Just use a std= _logic_vector. You should be including std_logic_1164 package file. =20 >=20 >=20 >=20 > Once that's complete, use the numeric_std package file for your math. =20 >=20 > Your conversion will be: >=20 > output <=3D to_integer(unsigned(input_slv)); >=20 >=20 >=20 > Read more about how to convert std_logic_vector to integer and why using = std_logic_arith is a bad idea. http://www.nandland.com/vhdl/tips/tip-conve= rt-numeric-std-logic-vector-to-integer.html Hey Thanks, But I need several random numbers in my array so that a private= key may be derived. The module is connected to a random number generator w= hich generates a std_logic_vector of 8 bits. From newsfish@newsfish Thu Aug 1 00:30:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Synthesis issues in Merkle Hellman Knapsack Cryptosystems Date: Thu, 03 Jul 2014 12:05:01 +0200 Lines: 34 Message-ID: References: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> <04208bb3-7e0e-4a47-892d-b5aa4a5a63fe@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net LxT2vKBrOIKGekwvAlSdpwJqXi+hxIGcZtlJLlkkcE9iL0AVba Cancel-Lock: sha1:01DcR94p/A5+AmGLPE36pq4XaGA= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <04208bb3-7e0e-4a47-892d-b5aa4a5a63fe@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:3150 Gandalf wrote: > Hey Thanks, But I need several random numbers in my array so that a > private key may be derived. The module is connected to a random > number generator which generates a std_logic_vector of 8 bits. Then you need an array of std_logic_vectors, not an array of std_logic. Right now what you're doing here: int1:= to_integer(rnum1(i-1)); ... is accessing a single bit in a std_logic_vector. Not sure how useful it is to convert a single bit to an integer. I suppose you expect rnum1(i-1) to be a random number of 8 bits length instead? You probably want to declare "rndnum" and "easy" as arrays of std_logic_vectors(7 downto 0) to be able to store incoming rnum values or something. I have no idea about the algorithm, so I'm guessing here... Besides, a std_logic or a std_logic_vector is not a numerical value, it's a bit or a collection of bits. That's why you cannot convert it to integer. You either have to declare the elements of your rnum1 array as some sort of numerical value (for example unsigned(7 downto 0)) or you have to cast before trying to convert: int1:= to_integer(unsigned(rnum1(i-1))); (or maybe signed, depending on what values that random number generator delivers). The whole conversion doesn't make a whole lot of sense if what you're converting is a single it, though. HTH, Sean From newsfish@newsfish Thu Aug 1 00:30:19 2024 X-Received: by 10.66.185.9 with SMTP id ey9mr2717551pac.26.1404402594447; Thu, 03 Jul 2014 08:49:54 -0700 (PDT) X-Received: by 10.50.43.227 with SMTP id z3mr247600igl.11.1404402594161; Thu, 03 Jul 2014 08:49:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-01.inet.qwest.net!news.glorb.com!hn18no2585868igb.0!news-out.google.com!bp9ni2743igb.0!nntp.google.com!hn18no2585865igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Jul 2014 08:49:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.206; posting-account=7MoFvwoAAABDSlSivIE9GEbIeBJFr7-i NNTP-Posting-Host: 119.235.52.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f168893-4680-4ea8-a1b1-7aa7d0ddd5fb@googlegroups.com> Subject: Graphic Design Company in Chennai From: chkumar357@gmail.com Injection-Date: Thu, 03 Jul 2014 15:49:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3151 Postlor Interactive is the best Graphic Design Company in ChennaiIndia specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com From newsfish@newsfish Thu Aug 1 00:30:19 2024 X-Received: by 10.182.70.74 with SMTP id k10mr4879863obu.34.1404457783543; Fri, 04 Jul 2014 00:09:43 -0700 (PDT) X-Received: by 10.50.138.133 with SMTP id qq5mr1132605igb.4.1404457783393; Fri, 04 Jul 2014 00:09:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hn18no2819401igb.0!news-out.google.com!bp9ni2745igb.0!nntp.google.com!hn18no2819383igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Jul 2014 00:09:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.27.8.45; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 103.27.8.45 References: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> <04208bb3-7e0e-4a47-892d-b5aa4a5a63fe@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Synthesis issues in Merkle Hellman Knapsack Cryptosystems From: Gandalf Injection-Date: Fri, 04 Jul 2014 07:09:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3152 On Thursday, July 3, 2014 3:35:01 PM UTC+5:30, Sean Durkin wrote: > Gandalf wrote: > > > > > Hey Thanks, But I need several random numbers in my array so that a > > > private key may be derived. The module is connected to a random > > > number generator which generates a std_logic_vector of 8 bits. > > > > Then you need an array of std_logic_vectors, not an array of std_logic. > > > > Right now what you're doing here: > > > > int1:= to_integer(rnum1(i-1)); > > > > ... is accessing a single bit in a std_logic_vector. Not sure how useful > > it is to convert a single bit to an integer. I suppose you expect > > rnum1(i-1) to be a random number of 8 bits length instead? > > > > You probably want to declare "rndnum" and "easy" as arrays of > > std_logic_vectors(7 downto 0) to be able to store incoming rnum values > > or something. I have no idea about the algorithm, so I'm guessing here... > > > > Besides, a std_logic or a std_logic_vector is not a numerical value, > > it's a bit or a collection of bits. That's why you cannot convert it to > > integer. You either have to declare the elements of your rnum1 array as > > some sort of numerical value (for example unsigned(7 downto 0)) or you > > have to cast before trying to convert: > > > > int1:= to_integer(unsigned(rnum1(i-1))); > > > > (or maybe signed, depending on what values that random number generator > > delivers). The whole conversion doesn't make a whole lot of sense if > > what you're converting is a single it, though. > > > > HTH, > > Sean Hey Sean, that was pretty helpful! I'll try to do the things you mentioned. From newsfish@newsfish Thu Aug 1 00:30:20 2024 X-Received: by 10.236.136.231 with SMTP id w67mr6502481yhi.37.1404532881414; Fri, 04 Jul 2014 21:01:21 -0700 (PDT) X-Received: by 10.50.45.67 with SMTP id k3mr618641igm.1.1404532881180; Fri, 04 Jul 2014 21:01:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i13no6083670qae.1!news-out.google.com!bp9ni2744igb.0!nntp.google.com!uq10no1700170igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Jul 2014 21:01:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.206; posting-account=7MoFvwoAAABDSlSivIE9GEbIeBJFr7-i NNTP-Posting-Host: 119.235.52.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <076a62ef-f79a-453b-8982-68960e8b0e7a@googlegroups.com> Subject: Graphic Design Company in Chennai From: chkumar357@gmail.com Injection-Date: Sat, 05 Jul 2014 04:01:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3153 Postlor Interactive is the best Graphic Design Company in ChennaiIndia specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com From newsfish@newsfish Thu Aug 1 00:30:20 2024 X-Received: by 10.43.58.137 with SMTP id wk9mr13345433icb.10.1404667173780; Sun, 06 Jul 2014 10:19:33 -0700 (PDT) X-Received: by 10.50.2.73 with SMTP id 9mr679962igs.13.1404667173652; Sun, 06 Jul 2014 10:19:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hn18no4100713igb.0!news-out.google.com!bp9ni2747igb.0!nntp.google.com!hn18no4100709igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Jul 2014 10:19:33 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.206; posting-account=7MoFvwoAAABDSlSivIE9GEbIeBJFr7-i NNTP-Posting-Host: 119.235.52.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9ce2d2ca-9f27-42d9-b68d-68e0c1418d51@googlegroups.com> Subject: Graphic Design Company in Chennai From: chkumar357@gmail.com Injection-Date: Sun, 06 Jul 2014 17:19:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3154 Postlor Interactive is the best Graphic Design Company in ChennaiIndia specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com From newsfish@newsfish Thu Aug 1 00:30:20 2024 X-Received: by 10.66.182.130 with SMTP id ee2mr9252737pac.37.1405007011167; Thu, 10 Jul 2014 08:43:31 -0700 (PDT) X-Received: by 10.182.28.71 with SMTP id z7mr154028obg.16.1405007010966; Thu, 10 Jul 2014 08:43:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!r10no645937igi.0!news-out.google.com!gf2ni5igb.0!nntp.google.com!hn18no249931igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Jul 2014 08:43:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.206; posting-account=7MoFvwoAAABDSlSivIE9GEbIeBJFr7-i NNTP-Posting-Host: 119.235.52.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9cc79afa-c26e-44e7-aa13-384112177062@googlegroups.com> Subject: Graphic Design Company in Chennai From: chkumar357@gmail.com Injection-Date: Thu, 10 Jul 2014 15:43:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3155 Postlor Interactive is the best Graphic Design Company in ChennaiIndia specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com From newsfish@newsfish Thu Aug 1 00:30:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: scoreboards, checkers and golden models Date: 11 Jul 2014 14:40:42 GMT Lines: 60 Message-ID: X-Trace: individual.net GwT11v8mP7510TZ86fIvXgwKeePl0/v1Z6+jVD9wZAHZnjnqtz X-Orig-Path: not-for-mail Cancel-Lock: sha1:oezWN/ttBBVUaE7FwPKd+J4sPMo= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3156 Hi everyone, I'm designing a verification environment for our fpga designs which essentially allows to incrementally test the whole system without the need to break the verification effort in several block level testcases which are often not reusable and too often not sufficiently debugged either. In order to perform CI (continuous integration) it would be better to have in place selfchecking testbenches which run autonomously and regularly (each build or each nth build). When talking about a selfchecking testbench I've often heard about a 'golden model' against which we compare our results and here I'd like to explain why I do not clearly see the reason for it. In a 'verification plan' I have to match the 'requirements specification', therefore I need to check that a) I've covered all requirements and b) the criteria specified as a requirement is met. Taking one example I'm currently working with: /The time between the SYNC assertion and the REF assertion shall be less than 5 microseconds/ My selfchecking testbench needs to have a coverage model to verify that my transactions a) do generate a transaction of the SYNC signal and b) the corresponding REF signal has arrived withing the 5 microseconds. So in my mind I consider a scoreboard as a mechanism to 'store' transactions out of which I fill my coverage model, while a checker is a mechanism which goes through each transaction and verify that the requirement is met. In the above example I may imagine to have my bfm which generates the SYNC and samples the REF signal, storing the 'transaction' as a data structure, possibly containing the 'time interval' between the two events. The transaction is stored in the scoreboard which fills a sort of coverage db while in the meantime the checker may, asynchronously, examine the transaction and raise a flag pass/failed. If all what I said does make sense to, at least some of, you then could someone explain me where is the need for a 'golden model' in this context? Isn't the requirement specification sufficient to fill our needs? Remaining in the hypothesis that I did understand something of what I said, when it is time to do the 'verification report', how do we bind the pass/failed criteria to the coverage db? I hinted the possibility for the checker to be completely out of sync w.r.t. the coverage db. On a side note, if any has some source code for scoreboards and checkers, whose willing to share as a reference for this discussion I'd appreciate. Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Thu Aug 1 00:30:21 2024 X-Received: by 10.52.121.13 with SMTP id lg13mr22993419vdb.8.1405094940221; Fri, 11 Jul 2014 09:09:00 -0700 (PDT) X-Received: by 10.182.250.195 with SMTP id ze3mr20094obc.34.1405094939947; Fri, 11 Jul 2014 09:08:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no100526igc.0!news-out.google.com!gf2ni6igb.0!nntp.google.com!r10no1044532igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Jul 2014 09:08:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <00510750-5d33-424d-bc8e-cbf51e284519@googlegroups.com> Subject: Re: scoreboards, checkers and golden models From: KJ Injection-Date: Fri, 11 Jul 2014 16:08:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2673 X-Received-Body-CRC: 1542455812 Xref: news.eternal-september.org comp.lang.vhdl:3157 On Friday, July 11, 2014 10:40:42 AM UTC-4, alb wrote: > If all what I said does make sense to, at least some of, you then could= =20 > someone explain me where is the need for a 'golden model' in this=20 > context? Isn't the requirement specification sufficient to fill our=20 > needs?=20 In your case, it appears that your 'golden model' implementation happens wi= th "I may imagine to have my bfm which generates the SYNC and samples the R= EF signal, storing the 'transaction' as a data structure, possibly containi= ng the 'time interval' between the two events". Since you do not appear to be performing any function on the data then simp= ly making sure that what goes in, comes out at the appropriate time is suff= icient, but that then is your golden model. Your design may be translating= between interfaces or other such useful things, but if at the end of the d= ay you're simply moving data from a source to a destination with the expect= ation that everything sent gets received, then the golden model for that wo= uld be to take whatever is sent and post that to the expected output queue. Now consider a case where the input data gets operated on to produce the ou= tput. The specification might say something like "JPEG compression" where = what comes out is radically different than what went in. Now you have to a= ctually compute what the expected output is and you have to use a known goo= d model for producing that golden output so you have to question the source= of that model. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:21 2024 X-Received: by 10.50.126.9 with SMTP id mu9mr1364436igb.6.1405097712442; Fri, 11 Jul 2014 09:55:12 -0700 (PDT) X-Received: by 10.50.12.70 with SMTP id w6mr121876igb.9.1405097712262; Fri, 11 Jul 2014 09:55:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!r10no1059830igi.0!news-out.google.com!gf2ni6igb.0!nntp.google.com!r10no1059817igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Jul 2014 09:55:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> Subject: Re: scoreboards, checkers and golden models From: Jim Lewis Injection-Date: Fri, 11 Jul 2014 16:55:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3223 X-Received-Body-CRC: 2205373041 Xref: news.eternal-september.org comp.lang.vhdl:3158 Hi Al,=20 The first problem is that the terminology is evolving and means different t= hings to different people. One good source of terminology is the book, "Co= mprehensive Functional Verification". =20 A "golden model" or reference model answers the question, how do I predict = what is going on in the system. Some designs need them, some don't. A scoreboard is simply a means for correlating transactions into a DUT with= responses. =20 A checker simply provides a means for collecting outputs of a design and va= lidating functionality of a design. =20 A checker may operate alone or in conjunction with a reference model and/or= a scoreboard. For example, if Sync and Ref are simple std_logic values (i= e: =3D '1'), for every Sync there is a Ref, and there is no additional Sync= until the first Ref is received, then a checker model can validate this al= l by itself.=20 OTOH, if Sync and Ref are actually transaction values (such as Integer) and= the Ref value depends not only on Sync, but also on prior transactions, th= en it would be appropriate to use a reference model. If Ref depends only = on Sync, then again the checker model can validate it alone. Also if the system allows for pipelining of Sync and Ref, meaning, multiple= Sync transactions may be received before a Ref response, then you will nee= d a scoreboard. The scoreboard would store both the expected Ref value (if= not just a '1') and the time at which it must occur by (ie: Sync Time + 5 = us). This is a great example as it also demonstrates that a scoreboard mus= t support more than just simple "=3D" comparisons - in this case, the actua= l time value of receiving Ref must be less than or equal the expected time. BTW, the scoreboard model that we discuss and comes with SynthWorks' VHDL T= estbenches and Verification class, handles both inorder and out of order tr= ansaction responses, and also, supports parametrization so that it can hand= le cases like the last one described above (less than equal to comparisons = or more complex "ad hoc"). Cheers, Jim From newsfish@newsfish Thu Aug 1 00:30:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models Date: 12 Jul 2014 21:49:01 GMT Lines: 80 Message-ID: References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> X-Trace: individual.net 09iViCiIv8r5VbTb3yQ1agSNTSWLKxtWqqo+48wcanRmOElOw8 X-Orig-Path: not-for-mail Cancel-Lock: sha1:LAVQycCJYL8DslZcQWV8RKbOI9Q= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3159 Hi Jim, Jim Lewis wrote: > The first problem is that the terminology is evolving and means > different things to different people. One good source of terminology > is the book, "Comprehensive Functional Verification". I went through it once...maybe it's time to go through it once again ;-) > A "golden model" or reference model answers the question, how do I > predict what is going on in the system. Some designs need them, some > don't. A golden model, as defined, does not need to be part of a test. Indeed it needs to be part of the 'test report', where you go through your collected data and check for each test if you passed or fail. > A scoreboard is simply a means for correlating transactions into a DUT > with responses. That is an extremely nice definition. A sort of a 'dictionary' where for each transaction there's a reply. Such a definition imply the need to be able to associate a reply to a transaction, no matter the order of the replies and or transactions. > A checker simply provides a means for collecting outputs of a design > and validating functionality of a design. As defined, I see this step as separate element in my verification effort, that not necessarily lives in the same moment of the result collections. Is like if I first pick up the mushrooms and only then select the good from the bad ones. > A checker may operate alone or in conjunction with a reference model > and/or a scoreboard. For example, if Sync and Ref are simple > std_logic values (ie: = '1'), for every Sync there is a Ref, and there > is no additional Sync until the first Ref is received, then a checker > model can validate this all by itself. > OTOH, if Sync and Ref are actually transaction values (such as > Integer) and the Ref value depends not only on Sync, but also on prior > transactions, then it would be appropriate to use a reference model. > If Ref depends only on Sync, then again the checker model can validate > it alone. If Ref 'depends' on multiple Sync, than the real 'transaction' is that multitude of Sync it is required to generate that Ref. Indeed there's always a one-to-one relation between an input transaction and an output one (unless the system is undeterministic and its output is not predictable only from the inputs and its state). At this point the transaction itself is made out of multiple packets (or events), which need to be stored in a suitable structure in the scoreboard. > > Also if the system allows for pipelining of Sync and Ref, meaning, > multiple Sync transactions may be received before a Ref response, then > you will need a scoreboard. The scoreboard would store both the > expected Ref value (if not just a '1') and the time at which it must > occur by (ie: Sync Time + 5 us). This is a great example as it also > demonstrates that a scoreboard must support more than just simple "=" > comparisons - in this case, the actual time value of receiving Ref > must be less than or equal the expected time. I would rather remove the checking from the scoreboard and leave it to the checker (possibly outside the simulation itself), in order to keep the scoreboard logic as simple as possible. > BTW, the scoreboard model that we discuss and comes with SynthWorks' > VHDL Testbenches and Verification class, handles both inorder and out > of order transaction responses, and also, supports parametrization so > that it can handle cases like the last one described above (less than > equal to comparisons or more complex "ad hoc"). If the scoreboard stores information in a file, a python dictionary would be a very simple and powerful structure to handle out of order transactions since it's a keyed list. That is why I'm actually thinking about separating the two tasks. As for the class...one day, I hope! ;-) From newsfish@newsfish Thu Aug 1 00:30:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models Date: 12 Jul 2014 21:49:16 GMT Lines: 49 Message-ID: References: <00510750-5d33-424d-bc8e-cbf51e284519@googlegroups.com> X-Trace: individual.net DigmiLW4kVBZIaNa8y6QTQa3JvLhnppptMy0WIc81jWetP+X0t X-Orig-Path: not-for-mail Cancel-Lock: sha1:UQgg1CZmLACEygSDnq3y5w5kIB8= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3160 Hi Kevin, KJ wrote: >> If all what I said does make sense to, at least some of, you then could >> someone explain me where is the need for a 'golden model' in this >> context? Isn't the requirement specification sufficient to fill our >> needs? > Now consider a case where the input data gets operated on to produce > the output. The specification might say something like "JPEG > compression" where what comes out is radically different than what > went in. Now you have to actually compute what the expected output is > and you have to use a known good model for producing that golden > output so you have to question the source of that model. Ok, I think I didn't pick the right example and therefore I failed to see the need of a 'complex' model and indeed, as you said, I was using a model anyway. And I'm also not particularly smart either since we do have more complex examples that would need a reference model, but I guess I was too fast in discarding its need. So the checker would need to *know* what to expect for a particular transaction and rise a flag if the test fails or pass. But, while I see some benefits in having a 'protocol checker' embedded in the testbench in order to /validate/ the transactions, I have some issues in understanding why would I need the checker with a golden model to be also embedded in my testbench. Wouldn't it be easier to record transactions, say on a file, and then post-process it? Unless the stimulus has to adapt to the checker status, I don't see a particular benefit in venturing with complex models in either vhdl or any other language in a mixed language simulation (too much money and too many quirks). A post-processing phase instead could be easily handled with any high-level language and has the advantage that does not need any co-simulation environment to deal with. Moreover it decouples completely the model from the test, the output could be compared with simple tools and you keep the freedom to write your reference in what suits best for the application. While I see the benefit of a model when I need to emulate the hardware/software environment *around* my DUT, I fail to see its use in verifying the DUT behavior. But, as already proved by my shortsightedness in the OP, I may miss again the bigger picture. From newsfish@newsfish Thu Aug 1 00:30:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Concurrent assignments vs. assignments inside a process Date: Sun, 13 Jul 2014 11:13:58 +0200 Lines: 23 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net 6Fq8QpZzZ34N343KnHYKlgMmapxuD0p0oxGR9CTE1vadhmtYhA Cancel-Lock: sha1:G54Axb9z88ISGbF1ROPrHFF4mVk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 Xref: news.eternal-september.org comp.lang.vhdl:3161 Hi *, I'm sure one of you can clear this up: During debugging recently I discovered a bug in a module of mine: I had assigned a signal inside of a clocked process, but had also assigned it elsewhere concurrently (before writing the process, I had assigned it a different signal). Now, the result in simulation is as expected: the concurrent assignment usually "wins", with occasional 'X' in simulation. But what is unexpected to me is that the synthesis tools did not complain about this. I would have expected a "multiple drivers" error/warning or something similar. Why isn't there any? I always thought that a concurrent signal assignment is more or less just a less verbose version of a process with the right-hand-side signals in the sensitivity list. So basically what I had was assignments to the same signal from two different processes (one sequential one combinatorial), which should cause multiple drivers warnings. What would the hardware really do in that case, anyway? Sean From newsfish@newsfish Thu Aug 1 00:30:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Sun, 13 Jul 2014 20:38:47 -0400 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 14 Jul 2014 00:38:56 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="131d71abdca206f852e85f753b3a8167"; logging-data="24886"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18LG/7nUZ3qFLlXvz2c8JO7" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:/4PGSqv9r4UMtp40A2Jur3jupFE= Xref: news.eternal-september.org comp.lang.vhdl:3162 On 7/13/2014 5:13 AM, Sean Durkin wrote: > Hi *, > > I'm sure one of you can clear this up: > > During debugging recently I discovered a bug in a module of mine: I had > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). > > Now, the result in simulation is as expected: the concurrent assignment > usually "wins", with occasional 'X' in simulation. > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" > error/warning or something similar. Why isn't there any? > > I always thought that a concurrent signal assignment is more or less > just a less verbose version of a process with the right-hand-side > signals in the sensitivity list. So basically what I had was assignments > to the same signal from two different processes (one sequential one > combinatorial), which should cause multiple drivers warnings. What would > the hardware really do in that case, anyway? I would agree with what you about a concurrent statement being a shorthand version of a combinational process. I would have expected a multiple driver warning too. There may be something odd going on because one is clocked and the other combinational. But I expect this is a bug in any case. -- Rick From newsfish@newsfish Thu Aug 1 00:30:23 2024 X-Received: by 10.42.222.198 with SMTP id ih6mr8243484icb.18.1405299377129; Sun, 13 Jul 2014 17:56:17 -0700 (PDT) X-Received: by 10.182.225.162 with SMTP id rl2mr31194obc.13.1405299377001; Sun, 13 Jul 2014 17:56:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!h18no1173207igc.0!news-out.google.com!bp9ni7igb.0!nntp.google.com!h18no1173202igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 13 Jul 2014 17:56:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Question about driver, variable? From: fl Injection-Date: Mon, 14 Jul 2014 00:56:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3163 Hi, On VHDL books, it says that each signal having an assignment has a driver. I have a question about variable. Has a variable a driver? Please clarify the concept for me. Thanks, From newsfish@newsfish Thu Aug 1 00:30:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: 14 Jul 2014 06:31:46 GMT Lines: 50 Message-ID: References: X-Trace: individual.net 7gd2Xi3FROhd1FQVqtyTZARWvxMbhfpI6BaewaEE01OCH15lgr X-Orig-Path: not-for-mail Cancel-Lock: sha1:MlwvpNgBk6oZxL9LvxWId66oDzY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3164 Hi Sean, Sean Durkin wrote: [] > During debugging recently I discovered a bug in a module of mine: I had > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). I'm assuming your signal is of a resolved type, say std_logic or std_logic_vector. These types *can* have multiple drivers since they have a resolution function to resolve the conflict. Nevertheless I would not recommend resolved types for synthesis unless strictly necessary (bus), they may hide nasty bugs. > Now, the result in simulation is as expected: the concurrent assignment > usually "wins", with occasional 'X' in simulation. > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" > error/warning or something similar. Why isn't there any? An unresolved signal cannot be synthesized because the synthesis tool does not have a way to know what would be the output driving the signal for a specific configuration of its drivers. A resolved signal allows you to have multiple sources driving the signal and it would be up to the designer to make sure the result is what it is expected (think of a bus). > I always thought that a concurrent signal assignment is more or less > just a less verbose version of a process with the right-hand-side > signals in the sensitivity list. I would rather think they are two different language constructs, each with its own characteristics. You can infer a register with a concurrent assignment, but not a latch. Which one you use is a matter of style, as long as it matches your desired behavior. > So basically what I had was assignments > to the same signal from two different processes (one sequential one > combinatorial), which should cause multiple drivers warnings. What would > the hardware really do in that case, anyway? If I were you I'd program the device and see what happens (if the target is a ram/flash based device). Otherwise you can always simulate the postsynth results and verify it through your testbench (which you should anyhow). I'm not sure what the hardware will do when the signal is 'U' or 'X' Al From newsfish@newsfish Thu Aug 1 00:30:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Mon, 14 Jul 2014 11:55:51 +0200 Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net BwnzxdNoqZwSUzmVDyqBBQsUqjs+BpZcOOdjw644WuAKR/PVRz Cancel-Lock: sha1:yrAJp9iCfKJuOV5vzafCTtTlHPA= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:3165 alb wrote: > A resolved signal allows you to have multiple sources driving the signal > and it would be up to the designer to make sure the result is what it is > expected (think of a bus). Then why does the synthesis tool ALWAYS issue a "multiple drivers" error when a (resolved!) signal is being driven from two processes? It just doesn't if one of the assignments is concurrent and not inside a process. - signal driven from two processes -> "multiple drivers" error - signal driven from one process and a concurrent assignment -> nothing The signal might be resolved, but to 'X'. How is that going to help a synthesis tool decide what to do? It's not, and that's why I had expected it to complain. >> I always thought that a concurrent signal assignment is more or less >> just a less verbose version of a process with the right-hand-side >> signals in the sensitivity list. > I would rather think they are two different language constructs, each > with its own characteristics. You can infer a register with a concurrent > assignment, but not a latch. Which one you use is a matter of style, as > long as it matches your desired behavior. I looked it up in Ashenden's "Designer's Guide": "Concurrent signal assignment statements are equivalent to sequential signal assignments contained in process statements." So that doesn't really help explain anything here, unfortunately. I'm sure there's something more specific in the LRM... > If I were you I'd program the device and see what happens (if the target > is a ram/flash based device). Of course I did that already. The concurrent assignment wins. The question is: why? > I'm not sure what the hardware will do when the signal is 'U' or 'X' Neither am I, and that is really the question here. With 'U' I would assume it just sets everything to '0', because at least in Xilinx FPGAs everything's initialized to '0' as a default. So that is more or less "well-defined" and "logical" behaviour. If undriven, default to '0' (or even optimize away). Not so much for 'X', don't know how the decision process works there. If I had the time right now, I'd try using an unresolved signal to see if that makes any difference in synthesis. Greetings, Sean From newsfish@newsfish Thu Aug 1 00:30:24 2024 X-Received: by 10.70.43.77 with SMTP id u13mr7411028pdl.0.1405331790862; Mon, 14 Jul 2014 02:56:30 -0700 (PDT) X-Received: by 10.182.236.10 with SMTP id uq10mr10948obc.18.1405331790606; Mon, 14 Jul 2014 02:56:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no1305414igc.0!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no486512igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 02:56:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: Thomas Stanka Injection-Date: Mon, 14 Jul 2014 09:56:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2975 X-Received-Body-CRC: 785147415 Xref: news.eternal-september.org comp.lang.vhdl:3166 Am Sonntag, 13. Juli 2014 11:13:58 UTC+2 schrieb Sean Durkin: > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" > error/warning or something similar. Why isn't there any? I would expect Warning, no Error. In fact this is legal and the resulting h= ardware is legal, but very likely to do real bad things, as each time you s= ee an X in simulation, your HW might have a bus conflict with shortcut from= power supply to ground. Therefore it is good idea to use std_ulogic instea= d of std_logic to detect those errors in compile phase of your design. > I always thought that a concurrent signal assignment is more or less > just a less verbose version of a process with the right-hand-side You are right, if you remove the "or less" :). A concurrent signal is a pro= cess with right hand side as sensitivity list. > combinatorial), which should cause multiple drivers warnings. What would= =20 > the hardware really do in that case, anyway? Depending on technology and synthesis tool, you have a bus with multiple dr= iver=20 directly or through some wired-or constructs. A bus with multiple driver is= considered legal for technologies with internal tristate buffer, but it is= up to you(the designer) to ensure no condition of the bus can occure that = damages the device permanently. Therefore be carefule with the "try and err= or" suggestion of alb. While a lot of technologies and synthesis tools will= come up with a solution that is harmless for the device, there is no guara= ntee of such in general. regards Thomas From newsfish@newsfish Thu Aug 1 00:30:24 2024 X-Received: by 10.43.70.132 with SMTP id yg4mr9278667icb.30.1405338170307; Mon, 14 Jul 2014 04:42:50 -0700 (PDT) X-Received: by 10.182.66.131 with SMTP id f3mr12143obt.25.1405338170207; Mon, 14 Jul 2014 04:42:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no1344864igc.0!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no506754igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 04:42:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <853610dc-bb2c-4fee-b65f-13fc75f33d3d@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: KJ Injection-Date: Mon, 14 Jul 2014 11:42:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3167 On Sunday, July 13, 2014 5:13:58 AM UTC-4, Sean Durkin wrote: >=20 > During debugging recently I discovered a bug in a module of mine: I had > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). > Now, the result in simulation is as expected: the concurrent assignment > usually "wins", with occasional 'X' in simulation. > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" >=20 > error/warning or something similar. Why isn't there any? >=20 You should submit a ticket to the synthesis vendor. Without the code or kn= owing which tool you're using nobody here can help unless they happen to ha= ve run across the exact same problem. But you are correct, you should get = a multiple drivers error on this. A way to catch this sooner (i.e. while you're still in simulation mode) is = to use std_ulogic rather than std_logic. That way you'll have the error re= ported to you either when you first compile the file or when the simulation= starts up. There is no reason to use std_logic in an FPGA design except at the top lev= el for signals such as a data bus that are driven by multiple sources. FPG= As do not allow for this internally, so there is no reason to use std_logic= , use the proper type, std_ulogic/std_ulogic_vector. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:24 2024 X-Received: by 10.66.182.130 with SMTP id ee2mr7918288pac.37.1405338461999; Mon, 14 Jul 2014 04:47:41 -0700 (PDT) X-Received: by 10.182.249.108 with SMTP id yt12mr13491obc.17.1405338461886; Mon, 14 Jul 2014 04:47:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no1346943igc.0!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no507678igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 04:47:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: KJ Injection-Date: Mon, 14 Jul 2014 11:47:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2311 X-Received-Body-CRC: 3072080712 Xref: news.eternal-september.org comp.lang.vhdl:3168 On Monday, July 14, 2014 2:31:46 AM UTC-4, alb wrote: > > I'm assuming your signal is of a resolved type, say std_logic or > std_logic_vector. These types *can* have multiple drivers since they > have a resolution function to resolve the conflict. Nevertheless I would > not recommend resolved types for synthesis unless strictly necessary > (bus), they may hide nasty bugs. > There are no nasty bugs to be hidden. Multiple drivers of a signal no longer exist in FPGAs with the exception of I/O pins. > > An unresolved signal cannot be synthesized because the synthesis tool > does not have a way to know what would be the output driving the signal > for a specific configuration of its drivers. > This makes absolutely no sense. All of the signals inside an FPGA come from exactly one driver. That is basically the definition of unresolved (i.e std_ulogic, std_ulogic_vector). > > A resolved signal allows you to have multiple sources driving the signal > and it would be up to the designer to make sure the result is what it is > expected (think of a bus). > Just don't think of using it in an FPGA design except on the I/O pins. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:24 2024 X-Received: by 10.236.159.198 with SMTP id s46mr6652739yhk.17.1405338816090; Mon, 14 Jul 2014 04:53:36 -0700 (PDT) X-Received: by 10.182.29.38 with SMTP id g6mr89360obh.12.1405338815984; Mon, 14 Jul 2014 04:53:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v10no383514qac.1!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no508955igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 04:53:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <26ef915d-f0c0-46d3-8b48-934a3d6c8873@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: KJ Injection-Date: Mon, 14 Jul 2014 11:53:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1981 X-Received-Body-CRC: 2091072233 Xref: news.eternal-september.org comp.lang.vhdl:3169 On Monday, July 14, 2014 5:56:30 AM UTC-4, Thomas Stanka wrote: > I would expect Warning, no Error. In fact this is legal and the resulting > hardware is legal, No, it would be an error, not a warning. If a synthesis tool actually allows two drivers to be connected, there is a bug in the synthesis tool. Since by design they do not, the following that you wrote is completely wrong... > but very likely to do real bad things, as each time you see > an X in simulation, your HW might have a bus conflict with shortcut from power > supply to ground But the following is sound advice. All internal FPGA signals should be std_ulogic / std_ulogic_vector. > Therefore it is good idea to use std_ulogic instead of > std_logic to detect those errors in compile phase of your design. > Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models Date: Mon, 14 Jul 2014 14:59:30 +0100 Organization: TRW Conekt Lines: 18 Message-ID: References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain X-Trace: individual.net YLHcnKGRcrGG+LoGA36/dgt+r4meiwkvB+VcHZJn6oEiYGx08= Cancel-Lock: sha1:Rl++mP1LSfPmHxRcdChNHQPWo9Q= sha1:QvvShGNPQPL7CTkvJoSKUODaV2A= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:3170 al.basili@gmail.com (alb) writes: > I would rather remove the checking from the scoreboard and leave it to > the checker (possibly outside the simulation itself), in order to keep > the scoreboard logic as simple as possible. One reason to keep the checker inside the simulation is to make sure you fail as soon as possible. You don't want to have to wait for the simulation to finish after many hours only to find that the error could have been flagged only minutes into the test! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Thu Aug 1 00:30:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Mon, 14 Jul 2014 17:20:05 +0200 Lines: 60 Message-ID: References: <853610dc-bb2c-4fee-b65f-13fc75f33d3d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net GM/DyZvFttDGN6ASct8ocAMpfgHbB9B69GywpPl/OeABy9NJLI Cancel-Lock: sha1:91HGIDFZhihNVOkHBSESnc/lpsU= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <853610dc-bb2c-4fee-b65f-13fc75f33d3d@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:3171 Hi KJ, KJ wrote: > You should submit a ticket to the synthesis vendor. Without the code > or knowing which tool you're using nobody here can help unless they > happen to have run across the exact same problem. But you are > correct, you should get a multiple drivers error on this. That's what I wanted to know. It's not that I didn't find the bug or anything, my testbench caught it quickly (although not as quickly as it would have when using std_ulogic), it's that I didn't understand the synth tool's reaction, or better non-reaction. This was just one of those occasions where you do a tiny adjustment shortly before going to a meeting, start up a simulation-run before leaving and then decide that the probability of it working now is so high that you might just start synthesis as well to save some time. When I came back it turned out simulation had failed but synthesis had completed successfully, without as much as a warning message in the logfiles. (FWIW, this was Xilinx Vivado synthesis, and there's no easy way anymore to submit tickets unless you're a big customer. You always have to go through your FAE, who was hopelessly overloaded before being responsibly for accepting tickets in addition to all his other duties. So before going through him I at least want to make sure that I'm not just misunderstanding things and this is all perfectly expected behaviour. The only alternative is to post in their user forums and hope someone feels responsible.) > There is no reason to use std_logic in an FPGA design except at the > top level for signals such as a data bus that are driven by multiple > sources. FPGAs do not allow for this internally, so there is no > reason to use std_logic, use the proper type, > std_ulogic/std_ulogic_vector. You are of course right. But someone should tell Xilinx... Almost every IP-Core, every example design, every code snippet or template they provide uses std_logic(_vector) exclusively. In fact, what I was doing was to drive an IP-Core-FIFO control signal, and of course they use std_logic as the type for all ports, not std_ulogic, so I hooked it up to a std_logic as well instead of using std_ulogic (which probably would have caught it right at the start of simulation). Just for some of their hardmacros, they provide component declarations with some (not all) ports being of type std_ulogic(_vector), the rest is std_logic. Because of this, trying to enforce usage of std_ulogic usually results in type casting madness whenever Xilinx-stuff is involved (or is there some elegant, less verbose way to solve this?). This seems to be easier, less-verbose in VHDL-2008 (it seems that e.g. connecting a core's std_logic_vector output port to a std_ulogic_vector signal is now accepted; compiling with VHDL-2002 I get a type mismatch error in ModelSim), but that's not yet supported in most synthesis tools so I can't really use it. Greetings, Sean From newsfish@newsfish Thu Aug 1 00:30:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Mon, 14 Jul 2014 11:30:44 -0400 Organization: Alacron, Inc. Lines: 24 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 14 Jul 2014 15:32:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="7710"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wv4fcObUV6BciwHoJs64dO3S6JXBg+zo=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:gaQHCqaPPbIaxXq19QIhvJbVO1E= Xref: news.eternal-september.org comp.lang.vhdl:3172 Sean Durkin wrote: [snip] >> If I were you I'd program the device and see what happens (if the target >> is a ram/flash based device). > Of course I did that already. The concurrent assignment wins. The > question is: why? > This is only a guess, but if a truly concurrent assignment is continuous - i.e. doesn't really depend on inputs changing, but acts like a wire to constantly update the output. One of these constantly updated drivers would "win" against any other procedural driver because the output of the process would only affect the net for a zero time period (say one delta delay for simulation) after the process runs. Again it's only a guess, and I agree that synthesis should complain about multiple drivers rather than going ahead and letting the concurrent assignment "win." -- Gabor From newsfish@newsfish Thu Aug 1 00:30:26 2024 X-Received: by 10.182.19.138 with SMTP id f10mr784047obe.25.1405354351034; Mon, 14 Jul 2014 09:12:31 -0700 (PDT) X-Received: by 10.182.104.226 with SMTP id gh2mr14896obb.37.1405354350895; Mon, 14 Jul 2014 09:12:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no574821igc.0!news-out.google.com!bp9ni28igb.0!nntp.google.com!h18no1453108igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 09:12:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46008d37-d320-41be-bdb1-48d42ec2a28d@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: Andy Injection-Date: Mon, 14 Jul 2014 16:12:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3173 Multiple driver warnings in synthesis are usually triggered by multiple ass= ignments without any 'Z' values being conditionally driven.=20 If both of your assignments conditionally drive data or 'Z' onto the signal= , then some synthesis tools will handle converting the multiple tri-state s= ignals to muxed data, and if that signal is for chip-level IO, synthesis wi= ll handle the output enable control (for the implied TS buffer in the IOB). Depending on the synthesis tool and what options are set, some synthesis to= ols will convert internal tri-state "busses" into multiplexers, etc. genera= ting an output for single net. Some will even split up bi-directional tri-s= tate busses, and replace them with multiplexers, etc. I don't necessarily r= ecommend using this feature. Otherwise, I'm not sure what your problem might be. Andy From newsfish@newsfish Thu Aug 1 00:30:26 2024 X-Received: by 10.182.95.40 with SMTP id dh8mr8596166obb.5.1405355186187; Mon, 14 Jul 2014 09:26:26 -0700 (PDT) X-Received: by 10.182.153.200 with SMTP id vi8mr27054obb.23.1405355186054; Mon, 14 Jul 2014 09:26:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no1459887igc.0!news-out.google.com!bp9ni28igb.0!nntp.google.com!h18no1459881igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 09:26:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <05910271-f443-42f2-a961-7218a99a8f49@googlegroups.com> Subject: Re: Question about driver, variable? From: Andy Injection-Date: Mon, 14 Jul 2014 16:26:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3174 No, variables do not have a sense of time or scheduled updates, so they do = not have "drivers" like signals do.=20 Note that unless the variable is shared, only one process can update and re= ad it anyway. The variable contents are updated immediately upon execution of an assignme= nt statement for that variable. The value persists as long as the variable = persists (which, in a process, is for the duration of the simulation), unti= l it is updated by a subsequently executed assignment.=20 The persistence of a variable's values, in synthesis, can imply either a wi= re or storage (latch or register), depending on the context of updates and = accesses to the value. Andy From newsfish@newsfish Thu Aug 1 00:30:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models Date: 15 Jul 2014 06:15:09 GMT Lines: 32 Message-ID: References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> X-Trace: individual.net 6Sbba8je0SKFbLt9Epa+sAJajqhjZF2n2BKUugAlxitn2XAKL9 X-Orig-Path: not-for-mail Cancel-Lock: sha1:9CGj6gbu5IMFPEhbonRuk1Rhk/U= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3175 Hi Martin, Martin Thompson wrote: [] >> I would rather remove the checking from the scoreboard and leave it to >> the checker (possibly outside the simulation itself), in order to keep >> the scoreboard logic as simple as possible. > > One reason to keep the checker inside the simulation is to make sure you > fail as soon as possible. You don't want to have to wait for the > simulation to finish after many hours only to find that the error could > have been flagged only minutes into the test! True, I believe though that running many hours simulation is not really necessary and often you can break it up in several testcases. Unless you need many hours to 'configure' properly the DUT for a specific test, you could generally think that a test case is a finite and relatively small number of transactions. If you are thinking about Constrained Randomization, you can always break the verification in several simulation runs by merging the coverage collected on the way. The real issue is that modelling is not extremely straight forward with vhdl and you immediately find yourself in a mixed language simulation environment which requires expensive licenses. I found for instance that python is extremely powerful at producing relatively accurate models with very small efforts. The issue is how to embed a python model into a vhdl based testbench? I've recently heard about 'cocotb', maybe I should give it a try, but I've read it has problems with Modelsim/Questa, which is the simulator we are using. From newsfish@newsfish Thu Aug 1 00:30:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: 15 Jul 2014 06:35:40 GMT Lines: 56 Message-ID: References: X-Trace: individual.net z/qndFymWCiTRxOlncNeUQMZn1dIOnB8IJkhnzQauAVL/l7k/h X-Orig-Path: not-for-mail Cancel-Lock: sha1:m+LbKXo9EPWDlQy8M9EmxPV2kq0= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3176 Hi Kevin, KJ wrote: > On Monday, July 14, 2014 2:31:46 AM UTC-4, alb wrote: >> >> I'm assuming your signal is of a resolved type, say std_logic or >> std_logic_vector. These types *can* have multiple drivers since they >> have a resolution function to resolve the conflict. Nevertheless I would >> not recommend resolved types for synthesis unless strictly necessary >> (bus), they may hide nasty bugs. >> > There are no nasty bugs to be hidden. Multiple drivers of a signal no > longer exist in FPGAs with the exception of I/O pins. I was referring to the fact that the OP didn't realize about the multiple drivers issue during simulation therefore hiding a 'bug' for a long time before being uncovered. >> An unresolved signal cannot be synthesized because the synthesis tool >> does not have a way to know what would be the output driving the signal >> for a specific configuration of its drivers. >> > This makes absolutely no sense. All of the signals inside an FPGA > come from exactly one driver. That is basically the definition of > unresolved (i.e std_ulogic, std_ulogic_vector). Oops, you are right! It didn't make sense at all! I wanted to say that an unresolved type signal driven by multiple drivers cannot be implemented because the tool does not have a way to know what to drive when a conflict arise. Using resolved signals internally to an FPGA is not necessarily bad though. There's an interesting AN from B.Cohen (klabs.org/richcontent/software_content/vhdl/force_errors.pdf) which is using user defined resolution functions to inject errors onto a signal. Interestingly enough you could use a configuration to wrap your architecture with the extra component for error injection *only* during verification and removing it when performing synthesis. A very useful usecase is when you need to verify an EDAC. >> A resolved signal allows you to have multiple sources driving the signal >> and it would be up to the designer to make sure the result is what it is >> expected (think of a bus). >> > > Just don't think of using it in an FPGA design except on the I/O pins. I've often used resolved signals inside FPGAs to describe tristated busses with multiple drivers, I find the syntax much more readable. Synplify Pro AE has always been relatively useful to understand the code and implement the necessary muxes, it is also documented in their language guideline. Al From newsfish@newsfish Thu Aug 1 00:30:27 2024 X-Received: by 10.70.24.163 with SMTP id v3mr4715807pdf.8.1405429710079; Tue, 15 Jul 2014 06:08:30 -0700 (PDT) X-Received: by 10.182.128.131 with SMTP id no3mr147785obb.9.1405429709960; Tue, 15 Jul 2014 06:08:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!h18no904686igc.0!news-out.google.com!bp9ni210igb.0!nntp.google.com!h18no1941736igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Jul 2014 06:08:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: Andy Injection-Date: Tue, 15 Jul 2014 13:08:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3177 On Tuesday, July 15, 2014 1:35:40 AM UTC-5, alb wrote: > Interestingly enough you could use a configuration to wrap your architect= ure with the extra component for error injection *only* during verification= and removing it when performing synthesis. A very useful usecase is when y= ou need to verify an EDAC.=20 You don't even need to use a configuration (which then requires component d= eclarations and instantiations from the top, all the way down to the module= of interest) to try this. If your EDAC module is instantiated as an entity, WITHOUT an architecture s= pecification (e.g. rtl), then, after you compile all your RTL into the simu= lator, compile a wrapper architecture for your EDAC module. Inside that wra= pper, you re-instantiate the module again, but WITH the architecture specif= ication (rtl). Then you can do anything you want between the module and the= rest of the design, inside that wrapper architecture. You can modify/monit= or interface signals, insert funnctional coverage (OSVVM), and even use hie= rarchical references to check on signals inside EDAC (like covering the EDA= C's FSM state signal). Andy From newsfish@newsfish Thu Aug 1 00:30:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: 15 Jul 2014 19:47:48 GMT Lines: 36 Message-ID: References: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> X-Trace: individual.net pGvwMAcVrXpV0hp58Xxj8QofTc98UnlEx/kcNdMJglVF6dOI+3 X-Orig-Path: not-for-mail Cancel-Lock: sha1:2VbZgwPU/UivLygl3Mt4IewC9gg= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3178 Hi Andy, Andy wrote: >> Interestingly enough you could use a configuration to wrap your >> architecture with the extra component for error injection *only* >> during verification and removing it when performing synthesis. A very >> useful usecase is when you need to verify an EDAC. [] > If your EDAC module is instantiated as an entity, WITHOUT an > architecture specification (e.g. rtl), then, after you compile all > your RTL into the simulator, compile a wrapper architecture for your > EDAC module. Inside that wrapper, you re-instantiate the module again, > but WITH the architecture specification (rtl). So you are suggesting to have the entity and architecture on separate files, compile all of them and compile *last* the wrapper with the component instantiated. You are leveraging the fact the last 'object' compiled for that entity's architecture is the wrapper one therefore would be the one used for the sim. In synthesis though you would certainly not compile the wrapper and have only the rtl architecture. What about post-synth sims then? Do you perform the same amount of testing you do for your verification? (it seems not so). > Then you can do > anything you want between the module and the rest of the design, > inside that wrapper architecture. You can modify/monitor interface > signals, insert funnctional coverage (OSVVM), and even use > hierarchical references to check on signals inside EDAC (like covering > the EDAC's FSM state signal). I'm trying to convince my team to work with OSVVM and leverage these capabilities, unfortunately not everyone is onboard and sometimes the we are entrenched behind beliefs which are extremely wrong and hopelessly misleading (sob). From newsfish@newsfish Thu Aug 1 00:30:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: coverage collection Date: 15 Jul 2014 20:25:27 GMT Lines: 64 Message-ID: X-Trace: individual.net F2tvlesWJNDzkrw2oTF3xwyTkudDkQwWHfvQ8wVcB4r58RzNmR X-Orig-Path: not-for-mail Cancel-Lock: sha1:GT7SA2qs16Ogp04ikJmShP+gP+0= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3179 Hi everyone, this morning a member of the verification team found a bug in a testbench which lead to think we were testing a particular feature of the design while we were not (that's bad)! Likely enough the feature did fail at system level and we are now busy fixing it (that's good). We are too smart to perform any functional coverage collection and therefore rely on the fact that our direct tests are actually testing what they are supposed to do. Everyone seems pretty confortable with this situation while I'm not really. My argument against the current organization is that if we do not 'collect' our functional coverage we cannot know when and if we are done. Even though some boss believes that code coverage is all you need (and hopefully most of us know that that's not the case!), when I try to argument the need of a functional coverage collection I start to wander: wait a minute, what if our coverage model is not correct. What if we believe we are done just because we are doing functional coverage verification and we 'measure' that function A has been exercised. What if we 'believe' we have done a test against function A, happily recording the transaction which was supposedly defined to test it, while in reality the transaction got sidetracked by a stupid bug which did not cause the function A to be tested at all? I recently followed a recorded webinar on OSVVM at Aldec, by J.Lewis, and I found it very interesting, especially when he talked about Intelligent Coverage but then something stroke me, let's see this snippet of code [1]: -- from the presentation, available to registered users. while not ACov.IsCovered loop (Reg1, Reg2) := Acov.RandCovPoint; -- randomize uncovered bins DoAluOp(Trec, Reg1, Reg2); -- do transaction Acov.Icover((Reg1, Reg2)); -- mark it covered end loop; In the above snippet the real transaction is DoAluOp, which is supposed to do something with registers Reg[12], but we mark the bin as covered even though there's no real feedback from the transaction result. We are measuring coverage, we generate a transaction, but where did it ended? how can we be sure that we really tested what we believed? Isn't this the very same situation my colleague met this morning? On top of that, how can we collect coverage when using direct testing? Al [1] I hope Jim does not get upset for having used a snippet from his presentation :-/ -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Thu Aug 1 00:30:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: OSVVM vs UVM/OVM w.r.t. processor resources Date: 15 Jul 2014 20:47:17 GMT Lines: 31 Message-ID: X-Trace: individual.net 2IeofNaSHdvCbg6SZRT6pAj7AImCKf55isvTjwyQfGDL53BuF1 X-Orig-Path: not-for-mail Cancel-Lock: sha1:brXM850KkhT+/wq6x5Cb8JbGkcI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3180 Hi everyone, while trying to convince someone to have a look at the OSVVM package I got told that vhdl-2008 cannot be as efficient as SystemVerilog or SystemC in handling processor resources therefore a bench with UVM/OVM is certainly far more efficient [1] than one with OSVVM. Not knowing what are the performances of UVM/OVM I couldn't certainly argue against it, but is it really the case? I know about the Intelligent Coverage in OSVVM is o(log(N)) more efficient than its companion Constrained Random in SV, but what about memory allocation for instance? Or task switching? SystemC is certainly very flexible being derived from C++, but is that factor so important in simulation? What about the synchronization messages between the two simulation cores (if that is how they are called)? Any comment is appreciated, Al [1] we talk only about processor's resources here, nothing related to ease of adoption of the package, licenses cost and features set. -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Thu Aug 1 00:30:28 2024 X-Received: by 10.236.92.69 with SMTP id i45mr11712390yhf.20.1405477821870; Tue, 15 Jul 2014 19:30:21 -0700 (PDT) X-Received: by 10.182.61.9 with SMTP id l9mr189618obr.1.1405477821634; Tue, 15 Jul 2014 19:30:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j15no1003218qaq.0!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no1202716igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Jul 2014 19:30:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8b4cb4f2-5149-40cb-af32-fdca33ff9f4b@googlegroups.com> Subject: Re: coverage collection From: KJ Injection-Date: Wed, 16 Jul 2014 02:30:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3181 On Tuesday, July 15, 2014 4:25:27 PM UTC-4, alb wrote: > this morning a member of the verification team found a bug in a=20 > testbench which lead to think we were testing a particular feature of=20 > the design while we were not (that's bad)!=20 No, actually that's good. If your verification team does not find bugs, th= en most likely they are not trying or the design is very mature and only su= bject to relatively minor changes. > Likely enough the feature did=20 > fail at system level and we are now busy fixing it (that's good).=20 Yes it is > My argument against the current organization is that if we do not=20 > 'collect' our functional coverage we cannot know when and if we are done.= =20 That is typically the case. There aren't a whole lot of real world designs= where everything gets specified exactly enough and the test cases get defi= ned exactly enough so that you can get an a priori view that you can then t= rack to completion. > Even though some boss believes that code coverage is all you need (and=20 > hopefully most of us know that that's not the case!), when I try to=20 > argument the need of a functional coverage collection I start to wander:= =20 > wait a minute, what if our coverage model is not correct. What if we=20 > believe we are done just because we are doing functional coverage=20 > verification and we 'measure' that function A has been exercised. What=20 > if we 'believe' we have done a test against function A, happily=20 > recording the transaction which was supposedly defined to test it, while= =20 > in reality the transaction got sidetracked by a stupid bug which did not= =20 > cause the function A to be tested at all?=20 What you described seems to me to have nothing to do with functional covera= ge. Instead it sounds like the checking was not quite robust enough. The intended test was performed (albeit incorrectly), but the checker did n= ot catch that the correct response to the intended test did not occur. Sou= nds to me that there were two errors, not one as you reported. The checker= should first be upgraded to detect and report the incorrect (or lack of) r= esponse to the test as it was originally written. Then the stimulus should= be updated to perform the intended test. > =20 > -- from the presentation, available to registered users.=20 >=20 > while not ACov.IsCovered loop=20 >=20 > (Reg1, Reg2) :=3D Acov.RandCovPoint; -- randomize uncovered bins=20 > DoAluOp(Trec, Reg1, Reg2); -- do transaction=20 > Acov.Icover((Reg1, Reg2)); -- mark it covered=20 >=20 > end loop;=20 >=20 > =20 > In the above snippet the real transaction is DoAluOp, which is supposed= =20 > to do something with registers Reg[12], but we mark the bin as covered=20 > even though there's no real feedback from the transaction result.=20 Not sure about your point here. Are you saying - It is not possible to check that Reg[12] responded properly? - Reg1 and Reg2 were used where Reg[12] should have been used? The answer to the first scenario is that will never be the case unless Reg[= 12] controls nothing. There should be a verifiable response to everything.= Getting that response might be rather involved but if it is intended to d= o something then it can be verified in theory. Sometimes those tests need = to be performed at a unit level if the system level test is impossibly long= to run. In that case, one would have to verify at the system level on act= ual hardware rather than in simulation. The answer to the second scenario is that right now you have some additiona= l checking of Reg1 and Reg2 that you had not really intended (but it's ther= e now and works) and you need to add some more code to test Reg12. This ju= st means the testbench needs some more work. If you're thinking that havin= g a bug in a testbench is somehow worse than a bug in the design than you a= re a bit shortsighted. You should view every line of code written equally.= A given line of code is just as likely to be wrong no matter where it is = located. > We are measuring coverage, we generate a transaction, but where did it=20 > ended? how can we be sure that we really tested what we believed? Isn't= =20 > this the very same situation my colleague met this morning?=20 The short answer is that in most situations is that you can't be sure. Som= e niches of designs might be able to be provably correct but most will not.= That's not to say that you shouldn't be using good testing and design tec= hniques, but don't expect those techniques to be implemented flawlessly. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: coverage collection Date: 16 Jul 2014 07:54:32 GMT Lines: 120 Message-ID: References: <8b4cb4f2-5149-40cb-af32-fdca33ff9f4b@googlegroups.com> X-Trace: individual.net cWhePI8v3CYh3OgHXiVPwgtTC/HUuVE6yoaVckX3EPdJydmV77 X-Orig-Path: not-for-mail Cancel-Lock: sha1:CmfSyph9zGhDpIGbJ8s4PlcftWI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3182 Hi Kevin, KJ wrote: > On Tuesday, July 15, 2014 4:25:27 PM UTC-4, alb wrote: >> this morning a member of the verification team found a bug in a >> testbench which lead to think we were testing a particular feature of >> the design while we were not (that's bad)! > > No, actually that's good. If your verification team does not find > bugs, then most likely they are not trying or the design is very > mature and only subject to relatively minor changes. Indeed, I was focused on the 'half empty' glass... ;-) >> Even though some boss believes that code coverage is all you need (and >> hopefully most of us know that that's not the case!), when I try to >> argument the need of a functional coverage collection I start to wander: >> wait a minute, what if our coverage model is not correct. What if we >> believe we are done just because we are doing functional coverage >> verification and we 'measure' that function A has been exercised. What >> if we 'believe' we have done a test against function A, happily >> recording the transaction which was supposedly defined to test it, while >> in reality the transaction got sidetracked by a stupid bug which did not >> cause the function A to be tested at all? [] > The intended test was performed (albeit incorrectly), but the checker > did not catch that the correct response to the intended test did not > occur. Sounds to me that there were two errors, not one as you > reported. The checker should first be upgraded to detect and report > the incorrect (or lack of) response to the test as it was originally > written. Then the stimulus should be updated to perform the intended > test. Yes, you are right. There was a combination of two errors, one in the stimulus and one in the checker. None of them were spotted in time and only 'luck' helped us out. We were actually lucky that the issue came out at system level, but I'd like to understand why not earlier and what can we do to improve this situation. >> >> -- from the presentation, available to registered users. >> >> while not ACov.IsCovered loop >> >> (Reg1, Reg2) := Acov.RandCovPoint; -- randomize uncovered bins >> DoAluOp(Trec, Reg1, Reg2); -- do transaction >> Acov.Icover((Reg1, Reg2)); -- mark it covered >> >> end loop; >> >> >> In the above snippet the real transaction is DoAluOp, which is supposed >> to do something with registers Reg[12], but we mark the bin as covered >> even though there's no real feedback from the transaction result. > > Not sure about your point here. Are you saying > - It is not possible to check that Reg[12] responded properly? In the above example we assume that injecting Reg1 and Reg2 we are covering the intended case, *assuming* DoAluOp does what is supposed to do. > - Reg1 and Reg2 were used where Reg[12] should have been used? negative. My regexp notation for Reg1 and Reg2 was a bad choice that lead confusion. There's no Reg[12], only Reg1 and Reg2. > The answer to the first scenario is that will never be the case unless > Reg[12] controls nothing. There should be a verifiable response to > everything. That's is what it *should*, but here it was not the case. Is it a matter of code review? plan? report? model? > Getting that response might be rather involved but if it > is intended to do something then it can be verified in theory. Assume we inject Reg1 and Reg2 in order to have a Reg3=0 (I'm oversimplifying here). It is possible that Reg1 and Reg2 did not operate at all on Reg3, but for some reason the value of Reg3 is still correct. I realize the example is a bit too stupid to be representative but the point is still valid. The functional coverage should aim at generating the /condition/ *and* /measuring/ that something *did* happen (like a transition in Reg3 from one value to another). [] > If you're thinking that having a bug in a testbench is somehow worse > than a bug in the design than you are a bit shortsighted. You should > view every line of code written equally. A given line of code is just > as likely to be wrong no matter where it is located. It was not my intention to make you believe that I consider a testbench bug worse than a design one. All bugs are born equal, they only become severe if they have time to grow unnoticed. >> We are measuring coverage, we generate a transaction, but where did it >> ended? how can we be sure that we really tested what we believed? Isn't >> this the very same situation my colleague met this morning? > > The short answer is that in most situations is that you can't be sure. What I'm saying is that if a state of your sistem is controllable and observable there *must* be a way to A) define the inputs to control it to a particular value and B) observe that value happen. If we 'collect' only the fact that we have covered A) does not necessarily mean that B) is covered as well. > Some niches of designs might be able to be provably correct but most > will not. That's not to say that you shouldn't be using good testing > and design techniques, but don't expect those techniques to be > implemented flawlessly. My point here is not to point fingers on a wrong implementation, bugs are most likely there and will be there even if the final product behaves 'correctly'. My point is about trying to define a methodology which allows to anticipate these issues early in the development/verification cycle. From newsfish@newsfish Thu Aug 1 00:30:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx19.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: coverage collection References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140715-1, 15/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 49 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405499944 86.29.12.221 (Wed, 16 Jul 2014 08:39:04 UTC) NNTP-Posting-Date: Wed, 16 Jul 2014 08:39:04 UTC Organization: virginmedia.com Date: Wed, 16 Jul 2014 09:39:02 +0100 X-Received-Body-CRC: 132118099 X-Received-Bytes: 2648 Xref: news.eternal-september.org comp.lang.vhdl:3183 On 15/07/2014 21:25, alb wrote: Hi Al, .. > > I recently followed a recorded webinar on OSVVM at Aldec, by J.Lewis, > and I found it very interesting, especially when he talked about > Intelligent Coverage but then something stroke me, let's see this > snippet of code [1]: > > > -- from the presentation, available to registered users. > > while not ACov.IsCovered loop > > (Reg1, Reg2) := Acov.RandCovPoint; -- randomize uncovered bins > DoAluOp(Trec, Reg1, Reg2); -- do transaction > Acov.Icover((Reg1, Reg2)); -- mark it covered > > end loop; > > > > In the above snippet the real transaction is DoAluOp, which is supposed > to do something with registers Reg[12], but we mark the bin as covered > even though there's no real feedback from the transaction result. > > We are measuring coverage, we generate a transaction, but where did it > ended? how can we be sure that we really tested what we believed? Isn't > this the very same situation my colleague met this morning? > Coverage (not code) is only measuring that we have applied all the required and corner test cases, is not concerned with checking correct behaviour. So you are right in the above code snipped there must be another module that checks the ALU operations. In most cases Coverage Based Verification and Assertion Based Verification goes hand in hand. > On top of that, how can we collect coverage when using direct testing? Simply use an assertion, PSL is IMHO the easiest as it support sequences but you can also use OVL or write a simple FSM that confirms the sequence. Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:30:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx06.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: OSVVM vs UVM/OVM w.r.t. processor resources References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140715-1, 15/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 52 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405502382 86.29.12.221 (Wed, 16 Jul 2014 09:19:42 UTC) NNTP-Posting-Date: Wed, 16 Jul 2014 09:19:42 UTC Organization: virginmedia.com Date: Wed, 16 Jul 2014 10:19:40 +0100 X-Received-Body-CRC: 1380895920 X-Received-Bytes: 3271 Xref: news.eternal-september.org comp.lang.vhdl:3184 Hi Al, On 15/07/2014 21:47, alb wrote: > Hi everyone, > > while trying to convince someone to have a look at the OSVVM package I > got told that vhdl-2008 cannot be as efficient as SystemVerilog or > SystemC in handling processor resources therefore a bench with UVM/OVM > is certainly far more efficient [1] than one with OSVVM. It is true that (SystemVerilog/SystemC) can run faster than VHDL, however, I suspect the difference will be too small to be concerned about unless you are running a regression test for several days. You also have to ask yourself the question, would you swap language and verification environment just to get a few extra % of performance? Wouldn't it be more cost effective to improve your code (Modelsim has a nice code/memory profiler) or just get a faster PC. > > Not knowing what are the performances of UVM/OVM I couldn't certainly > argue against it, but is it really the case? I suspect that UVM(SV) will be quite fast (and faster in the future unless another acronym is invented) for the simple reason that this is where EDA vendors are spending their R&D budget on. However, the UVM/OVM is IMHO hugely complex and a total overkill for the fast majority of us. Unless you are working on a huge xxM gate ASIC design, have a large verification team or have lots of re-usable/verification IP I would forget about the UVM (or OVM/VVM). > > I know about the Intelligent Coverage in OSVVM is o(log(N)) more > efficient than its companion Constrained Random in SV, but what about > memory allocation for instance? Or task switching? > > SystemC is certainly very flexible being derived from C++, but is that > factor so important in simulation? What about the synchronization > messages between the two simulation cores (if that is how they are > called)? Yes, I believe that you are right that dual language simulation is not as efficient as a single language one as the simulator has to handle 2 simulation kernels. For SystemC and VHDL the overhead is probably not that great as they are both based on the same scheduler model, however, (System)Verilog is quite different (has a lot more scheduler stages). Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:30:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx13.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process References: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> In-Reply-To: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140715-1, 15/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 19 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405503957 86.29.12.221 (Wed, 16 Jul 2014 09:45:57 UTC) NNTP-Posting-Date: Wed, 16 Jul 2014 09:45:57 UTC Organization: virginmedia.com Date: Wed, 16 Jul 2014 10:45:55 +0100 X-Received-Body-CRC: 1061429652 X-Received-Bytes: 2634 Xref: news.eternal-september.org comp.lang.vhdl:3185 On 15/07/2014 14:08, Andy wrote: > On Tuesday, July 15, 2014 1:35:40 AM UTC-5, alb wrote: >> Interestingly enough you could use a configuration to wrap your architecture with the extra component for error injection *only* during verification and removing it when performing synthesis. A very useful usecase is when you need to verify an EDAC. > > You don't even need to use a configuration (which then requires component declarations and instantiations from the top, all the way down to the module of interest) to try this. > > If your EDAC module is instantiated as an entity, WITHOUT an architecture specification (e.g. rtl), then, after you compile all your RTL into the simulator, compile a wrapper architecture for your EDAC module. Inside that wrapper, you re-instantiate the module again, but WITH the architecture specification (rtl). Then you can do anything you want between the module and the rest of the design, inside that wrapper architecture. You can modify/monitor interface signals, insert funnctional coverage (OSVVM), and even use hierarchical references to check on signals inside EDAC (like covering the EDAC's FSM state signal). > > Andy > Or to make life even easier just use a bit of Tcl to force some errors in your EDAC code, this is how I tested my EDAC many many years ago. You only have to learn 3 Modelsim Tcl commands, "force/noforce", "when" and "examine". Regards, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:30:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: 16 Jul 2014 13:30:19 GMT Lines: 28 Message-ID: References: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> X-Trace: individual.net qZ+e+LCFOxvFg2GgtgWxNQlD6bnezD7lBOP7eCiMKoOXLalHcZ X-Orig-Path: not-for-mail Cancel-Lock: sha1:3URJzh28fM/nBLghRFDm1ny+rcI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3186 Hi Hans, HT-Lab wrote: [] >> If your EDAC module is instantiated as an entity, WITHOUT an >> architecture specification (e.g. rtl), then, after you compile all >> your RTL into the simulator, compile a wrapper architecture for your >> EDAC module. Inside that wrapper, you re-instantiate the module >> again, but WITH the architecture specification (rtl). Then you can do >> anything you want between the module and the rest of the design, >> inside that wrapper architecture. You can modify/monitor interface >> signals, insert funnctional coverage (OSVVM), and even use >> hierarchical references to check on signals inside EDAC (like >> covering the EDAC's FSM state signal). >> > Or to make life even easier just use a bit of Tcl to force some errors > in your EDAC code, this is how I tested my EDAC many many years ago. You > only have to learn 3 Modelsim Tcl commands, "force/noforce", "when" and > "examine". The issue with your suggestion is that is not portable and will depend on the tcl implementation of your simulator. On top of this what Andy proposed is much more than just force some values; he is suggesting to implement coverage collection and/or protocol checkers or the likes. Indeed you may be capable to embed, within the wrapper, a verification IP to your module that allows you to perform much more than just forcing signals. From newsfish@newsfish Thu Aug 1 00:30:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx16.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: coverage collection References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140716-0, 16/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 44 Message-ID: <64wxv.226799$xk2.102762@fx16.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405521282 86.29.12.221 (Wed, 16 Jul 2014 14:34:42 UTC) NNTP-Posting-Date: Wed, 16 Jul 2014 14:34:42 UTC Organization: virginmedia.com Date: Wed, 16 Jul 2014 15:34:41 +0100 X-Received-Body-CRC: 3974387229 X-Received-Bytes: 2433 Xref: news.eternal-september.org comp.lang.vhdl:3187 On 16/07/2014 09:39, HT-Lab wrote: > On 15/07/2014 21:25, alb wrote: > Hi Al, > .. >> >> I recently followed a recorded webinar on OSVVM at Aldec, by J.Lewis, >> and I found it very interesting, especially when he talked about >> Intelligent Coverage but then something stroke me, let's see this >> snippet of code [1]: >> >> >> -- from the presentation, available to registered users. >> >> while not ACov.IsCovered loop >> >> (Reg1, Reg2) := Acov.RandCovPoint; -- randomize uncovered bins >> DoAluOp(Trec, Reg1, Reg2); -- do transaction >> Acov.Icover((Reg1, Reg2)); -- mark it covered >> >> end loop; >> >> >> >> In the above snippet the real transaction is DoAluOp, which is supposed >> to do something with registers Reg[12], but we mark the bin as covered >> even though there's no real feedback from the transaction result. >> >> We are measuring coverage, we generate a transaction, but where did it >> ended? how can we be sure that we really tested what we believed? Isn't >> this the very same situation my colleague met this morning? >> > > Coverage (not code) is only measuring that we have applied all the > required and corner test cases, is not concerned with checking correct > behaviour. Sorry it should read "is not normally concerned with", obviously you can use coverage to check behaviour. Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:30:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Question about driver, variable? Date: Wed, 16 Jul 2014 18:34:06 +0100 Organization: TRW Conekt Lines: 23 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain X-Trace: individual.net xCqVzOHQZ0ELyWzGzyVu4AgbTAmCvyvUFdB9alUHeKQxHd8R0= Cancel-Lock: sha1:Ywwmh7a9AV2u0tWE/gPTjQFzE3g= sha1:cNFe0+5/X+0txYp2aKHKMCJ92YY= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:3188 fl writes: > Hi, > > On VHDL books, it says that each signal having an assignment has a driver. I > have a question about variable. Has a variable a driver? > Please clarify the concept for me. > No, a variable does not have a driver. Variables can only be changed within a process (unlike signals which can be changed - driven - from multiple processes) and the order in which assignment happen within that process define what the value of a variable is at any particular instant during the flow of execution. HTH, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Thu Aug 1 00:30:31 2024 X-Received: by 10.42.37.71 with SMTP id x7mr18371977icd.4.1405579353497; Wed, 16 Jul 2014 23:42:33 -0700 (PDT) X-Received: by 10.50.88.9 with SMTP id bc9mr434145igb.14.1405579353382; Wed, 16 Jul 2014 23:42:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no2925646igc.0!news-out.google.com!gf2ni864igb.0!nntp.google.com!h18no1546659igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Jul 2014 23:42:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <565bc83c-554b-47b6-bb27-4afcfa69404c@googlegroups.com> Subject: Re: coverage collection From: Jim Lewis Injection-Date: Thu, 17 Jul 2014 06:42:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3189 Hi Al, I think the need for functional coverage revolves around complexity. As co= mplexity increases, the need for functional coverage increases. The need f= or it also increases as the design goes through revision cycles. As we go = to new chips, they have bigger memory resources. We may decide to leverage= this and increase FIFO size. We re-run the old directed testbench and it = passes, however, did we validate that the testbench still hits the boundary= conditions - some may, some may not. =20 Code coverage measures execution of lines of code. However, if the item we= need to make sure happens is not in the code, then we need functional cove= rage (both of the examples from the presentation require functional coverag= e). =20 Code coverage works well for code that only runs once per clock cycle. OTO= H, it is optimistic for combinational logic coded in a process with a sensi= tivity list. This process runs on delta cycles and may run multiple times = during a given clock cycle - as a result, it may report you have covered so= mething that you did not.=20 While code coverage works great for software, it seems some put too much co= nfidence in it without understanding its limitations. > > while not ACov.IsCovered loop > (Reg1, Reg2) :=3D Acov.RandCovPoint; -- randomize uncovered bins > DoAluOp(Trec, Reg1, Reg2); -- do transaction > Acov.Icover((Reg1, Reg2)); -- mark it covered > end loop; > >=20 >=20 > In the above snippet the real transaction is DoAluOp, which is supposed= =20 > to do something with registers Reg[12], but we mark the bin as covered=20 > even though there's no real feedback from the transaction result. The example in the presentation is somewhat simplified. You have valid abo= ut concerns whether the input vectors are really applied or not. More form= ally you could (and perhaps should) have a input monitor that watches the i= nterface and collects the functional coverage - hard to show that on one sl= ide :). It would definitely reduce the risk. It is in some ways extra wor= k and the value it delivers will depend on the situation. =20 The value of a separate monitor will depend some on complexity. If I issue= a DoAluOp transaction, can I validate it in such a way that I am confident= that it always does what the transaction implies? For the ALU or even a U= ART transmitter - these are fairly simple and I should be able to validate = the testbench model well enough. =20 The value of a separate monitor will also depend on the response checking m= ethdology. For example, as KJ suggested, sometimes while doing result chec= king we also validate that the correct stimulus was applied. For example, = with UART or Ethernet traffic, I send a transaction, I put the expected val= ue into the scoreboard, and then when the RX side receives the transaction = and checks it via the scoreboard. In this case, the monitor is not adding = significant value since I am validating it on the receive side of the inter= face anyway. =20 OTOH, for the ALU logic, my testbench may simultaneously apply the inputs t= o the DUT and a behavioral math model. In this case, the response checker = is not going to me anything about what inputs were applied. However, in th= is case, DoAluOp may almost be trivial to write. If I were doing a safety critical design, I would require a separate monito= r process or model all of the time, just to add to the confidence level of = the testing. =20 > [1] I hope Jim does not get upset for having used a snippet from his=20 > presentation :-/ Certainly permitted. Especially when it promotes good discussion. Cheers, Jim From newsfish@newsfish Thu Aug 1 00:30:31 2024 X-Received: by 10.236.123.68 with SMTP id u44mr15763371yhh.19.1405595925588; Thu, 17 Jul 2014 04:18:45 -0700 (PDT) X-Received: by 10.182.91.37 with SMTP id cb5mr275796obb.0.1405595925479; Thu, 17 Jul 2014 04:18:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j15no1200251qaq.0!news-out.google.com!bp9ni940igb.0!nntp.google.com!h18no1609355igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Jul 2014 04:18:45 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> Subject: Re: scoreboards, checkers and golden models From: Chris Higgs Injection-Date: Thu, 17 Jul 2014 11:18:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2246 X-Received-Body-CRC: 1857038375 Xref: news.eternal-september.org comp.lang.vhdl:3190 On Tuesday, July 15, 2014 7:15:09 AM UTC+1, alb wrote: > I found for instance that python is extremely powerful at producing > relatively accurate models with very small efforts. The issue is how to > embed a python model into a vhdl based testbench? I've recently heard > about 'cocotb', maybe I should give it a try, but I've read it has > problems with Modelsim/Questa, which is the simulator we are using. The problem with Modelsim/Questa is that Mentor have yet to implement the full VHDL-2008 standard, specifically the VHPI C API, which Cocotb uses to communicate with VHDL simulations. If you have a mixed-language simulator license you can wrap the toplevel in Verilog wrapper, allowing Cocotb to use VPI to access the simulator. The only other alternative is implementing an FLI layer for Cocotb, which due to the rather limited functionality offered by FLI is non-trivial. You could also open a ticket with Mentor to demonstrate that there is demand for VHPI. Thanks, Chris From newsfish@newsfish Thu Aug 1 00:30:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!lightspeed!lightspeed.eweka.nl!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx24.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> In-Reply-To: <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140717-0, 17/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 44 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405602128 86.29.12.221 (Thu, 17 Jul 2014 13:02:08 UTC) NNTP-Posting-Date: Thu, 17 Jul 2014 13:02:08 UTC Organization: virginmedia.com Date: Thu, 17 Jul 2014 14:02:07 +0100 X-Received-Body-CRC: 3051967956 X-Received-Bytes: 3196 Xref: news.eternal-september.org comp.lang.vhdl:3191 On 17/07/2014 12:18, Chris Higgs wrote: > On Tuesday, July 15, 2014 7:15:09 AM UTC+1, alb wrote: >> I found for instance that python is extremely powerful at producing >> relatively accurate models with very small efforts. The issue is how to >> embed a python model into a vhdl based testbench? I've recently heard >> about 'cocotb', maybe I should give it a try, but I've read it has >> problems with Modelsim/Questa, which is the simulator we are using. > > The problem with Modelsim/Questa is that Mentor have yet to implement the full VHDL-2008 standard, specifically the VHPI C API, which Cocotb uses to communicate with VHDL simulations. > > If you have a mixed-language simulator license you can wrap the toplevel in Verilog wrapper, allowing Cocotb to use VPI to access the simulator. > > The only other alternative is implementing an FLI layer for Cocotb, which due to the rather limited functionality offered by FLI is non-trivial. FLI has "rather limited functionality", hum? what do you base that on? IMHO the FLI give you more functionality than you can shake a stick at. As per Aldec's presentation last week nobody is willing to pay Potential Ventures to port the code to the FLI, this is purely a financial issue and definitely not a technical one. During the Q&A session they mentioned that the FLI didn't have the right functionality to create processes in memory and creates signals to trigger on them, this is basic(core) FLI stuff! // Get pointer to port signal ip->signala = mti_FindPort(ports, "signala"); // Create a process in memory proc = mti_CreateProcess("myprocess", eval_int, ip); // Create sensitivity mti_Sensitize(proc, ip->signala, MTI_EVENT); Regards, Hans. www.ht-lab.com > > You could also open a ticket with Mentor to demonstrate that there is demand for VHPI. > > Thanks, > > Chris > From newsfish@newsfish Thu Aug 1 00:30:31 2024 X-Received: by 10.236.62.165 with SMTP id y25mr16748146yhc.26.1405618614973; Thu, 17 Jul 2014 10:36:54 -0700 (PDT) X-Received: by 10.182.104.226 with SMTP id gh2mr21982obb.37.1405618614858; Thu, 17 Jul 2014 10:36:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v10no1182383qac.1!news-out.google.com!bp9ni941igb.0!nntp.google.com!h18no3186620igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Jul 2014 10:36:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.0.40.221; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 82.0.40.221 References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3ba0ac73-564a-44c4-b7a6-893ea92d665d@googlegroups.com> Subject: Re: scoreboards, checkers and golden models From: Chris Higgs Injection-Date: Thu, 17 Jul 2014 17:36:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3655 X-Received-Body-CRC: 2969806915 Xref: news.eternal-september.org comp.lang.vhdl:3192 On Thursday, July 17, 2014 2:02:07 PM UTC+1, HT-Lab wrote: > FLI has "rather limited functionality", hum? what do you base that on? > IMHO the FLI give you more functionality than you can shake a stick at. It's likely that FLI provides all the required functionality, it's just more awkward to use than VPI or VHPI. Creating and tracking a process in order to generate a callback is one example of the inconvenience, although that in itself is minor. However if you look at the GPI layer we also need to create callbacks for various phases in the simulation scheduler loop. While with FLI it's possible to set a process priority referring to the scheduler phase, it's still not obvious how you might simply register a callback for entering a given phase, since you'd have to sensitise a process to *something*. Ensuring that Cocotb interacts correctly with the simulation scheduling loop was a major challenge and it doesn't look like FLI makes this any easier. > As per Aldec's presentation last week nobody is willing to pay Potential > Ventures to port the code to the FLI, this is purely a financial issue > and definitely not a technical one. During the Q&A session they > mentioned that the FLI didn't have the right functionality to create > processes in memory and creates signals to trigger on them, this is > basic(core) FLI stuff! I'm glad you listened to the presentation. I have to take issue with this statement though as this is actually the opposite of what I said. I appreciate that the sound quality of the recording is not great but if you listen from 41:55 you'll hear the following: > I believe it would be possible to create processes using FLI and trigger > them on signals, which is effectively the functionality we need. But you're correct that it's more a question of incentive - it's very likely that whatever technical issues arise are solvable. It's still a non-trivial task. The most biggest obstacle is that it's not possible to gain access to an FLI simulator without paying Mentor actual cash in not insignificant amounts. If somebody would like to contribute a license to enable us to develop an FLI interface I'm sure it would happen... or better yet if you have the skills and access to FLI contribute some code! Thanks, Chris From newsfish@newsfish Thu Aug 1 00:30:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx21.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> <3ba0ac73-564a-44c4-b7a6-893ea92d665d@googlegroups.com> In-Reply-To: <3ba0ac73-564a-44c4-b7a6-893ea92d665d@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140718-0, 18/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 95 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405677049 86.29.12.221 (Fri, 18 Jul 2014 09:50:49 UTC) NNTP-Posting-Date: Fri, 18 Jul 2014 09:50:49 UTC Organization: virginmedia.com Date: Fri, 18 Jul 2014 10:50:46 +0100 X-Received-Body-CRC: 2404468501 X-Received-Bytes: 4911 Xref: news.eternal-september.org comp.lang.vhdl:3193 Hi Chris, On 17/07/2014 18:36, Chris Higgs wrote: > On Thursday, July 17, 2014 2:02:07 PM UTC+1, HT-Lab wrote: >> FLI has "rather limited functionality", hum? what do you base that on? >> IMHO the FLI give you more functionality than you can shake a stick at. > > It's likely that FLI provides all the required functionality, it's just > more awkward to use than VPI or VHPI. Its all in the eye of the beholder. > > Creating and tracking a process in order to generate a callback is one > example of the inconvenience, although that in itself is minor. However > if you look at the GPI layer we also need to create callbacks for various > phases in the simulation scheduler loop. While with FLI it's possible to > set a process priority referring to the scheduler phase, it's still not > obvious how you might simply register a callback for entering a given > phase, I must admit I didn't check the GPI layer but I would expect the mti_CreateProcessWithPriority function to do the trick (which is the FLI function I assume you are referring to). If you look at the example of this function in the reference manual you will see it includes callbacks for different scheduler regions. >since you'd have to sensitise a process to *something*. I am not sure what you mean, do you need to activate the process other than by sensitivity signals? Perhaps mti_schedulewakeup is what you are after. > > Ensuring that Cocotb interacts correctly with the simulation scheduling > loop was a major challenge and it doesn't look like FLI makes this any > easier. > > >> As per Aldec's presentation last week nobody is willing to pay Potential >> Ventures to port the code to the FLI, this is purely a financial issue >> and definitely not a technical one. During the Q&A session they >> mentioned that the FLI didn't have the right functionality to create >> processes in memory and creates signals to trigger on them, this is >> basic(core) FLI stuff! > > I'm glad you listened to the presentation. I have to take issue with this > statement though as this is actually the opposite of what I said. > > I appreciate that the sound quality of the recording is not great but if you > listen from 41:55 you'll hear the following: > >> I believe it would be possible to create processes using FLI and trigger >> them on signals, which is effectively the functionality we need. I downloaded the recording and yes you are correct, my memory is not what it used to be. > > But you're correct that it's more a question of incentive - it's very likely > that whatever technical issues arise are solvable. It's still a non-trivial > task. Yes, I can imagine this is not an easy task. However, given the popularity of VHDL and Modelsim I assume this is high on your todo list. > > The most biggest obstacle is that it's not possible to gain access to > an FLI simulator without paying Mentor actual cash in not insignificant > amounts. Yes Modelsim (DE) is not particular low-cost, however, as with most large corporations it is "just" a question of finding the right person. If somebody would like to contribute a license to enable us to > develop an FLI interface I'm sure it would happen... or better yet if you > have the skills and access to FLI contribute some code! Looks like an interesting challenge, unfortunately my brain is already overloaded with to many languages and there is no more room not even for a powerful language like Python. Good luck, Regards, Hans. www.ht-lab.com > > Thanks, > > Chris > From newsfish@newsfish Thu Aug 1 00:30:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Martin Trummer Newsgroups: comp.lang.vhdl Subject: Optimize VHDL snippet for area Date: Thu, 24 Jul 2014 12:15:38 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: mx05.eternal-september.org; posting-host="4b81f6907e2ae697561d06650f07d4c6"; logging-data="17293"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX194enfzViRQanDg3fmoJsn0" User-Agent: Unison/2.1.9 Cancel-Lock: sha1:x5DDx2zCtULl6G/dWeMFxyAzWFU= Xref: news.eternal-september.org comp.lang.vhdl:3194 Hi, Having following VHDL snippet. This masks put bits from an input at a certain position if mask_ctrl > 0 then for i in 0 to DWITH-1 loop if i < mask_ctrl then next_data(i) <= data(i); mask_data(i) <= alu_out(i); else next_data(i) <= '0'; mask_data(i) <= '0'; end if; end loop; end if; next_data is an input for a FF, mask_data is a combinatorical output. Are possibilities to optimize this behavior with respect to chip area? Thanks! Best regards M. T. From newsfish@newsfish Thu Aug 1 00:30:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Optimize VHDL snippet for area Date: Thu, 24 Jul 2014 14:52:48 -0400 Organization: Alacron, Inc. Lines: 40 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Jul 2014 18:53:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="13215"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/StqS26pWmV4ZWy6J+Lr7PP0z2EJrO4eY=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:13wCRbTKVNlPNZbOduPJYRqEm34= Xref: news.eternal-september.org comp.lang.vhdl:3195 Martin Trummer wrote: > Hi, > > Having following VHDL snippet. This masks put bits from an input at a > certain position > > if mask_ctrl > 0 then > for i in 0 to DWITH-1 loop > if i < mask_ctrl then > next_data(i) <= data(i); > mask_data(i) <= alu_out(i); > else > next_data(i) <= '0'; > mask_data(i) <= '0'; > end if; > end loop; > end if; > > next_data is an input for a FF, mask_data is a combinatorical output. > Are possibilities to optimize this behavior with respect to chip area? > > Thanks! > > Best regards > M. T. > You say "mask_data is a combinatorical output," but I don't see any assignment to it if mask_ctrl is not > 0. That could create a latche unless you have a default assignment outside the code you posted. As for optimization, I would think a good synthesizer could give you a pretty optimal result. However you also didn't mention what architecture you're trying to build this in (FPGA, ASIC...) so there may be something you could do to help the optimization. However it's likely that even if you changed the code, for example by not using a loop, that the synthesis output wouldn't change. -- Gabor From newsfish@newsfish Thu Aug 1 00:30:33 2024 X-Received: by 10.50.85.42 with SMTP id e10mr10464478igz.0.1406232200561; Thu, 24 Jul 2014 13:03:20 -0700 (PDT) X-Received: by 10.182.191.39 with SMTP id gv7mr90555obc.10.1406232200350; Thu, 24 Jul 2014 13:03:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no4021917igc.0!news-out.google.com!eg1ni0igc.0!nntp.google.com!h18no4021914igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Jul 2014 13:03:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45ec9210-49d0-4182-89cd-639aa9b3bf6a@googlegroups.com> Subject: Re: OSVVM vs UVM/OVM w.r.t. processor resources From: Andy Injection-Date: Thu, 24 Jul 2014 20:03:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3196 Most of the simulation performance difference between vhdl and verilog/SV is due to the data types used by VHDL (SLV, etc.), how much memory they consume, etc. But most good testbenches minimize the use of slv/unsigned/etc. and use variables, integers and booleans as much as possible. That narrows the performance gap between VHDL and Verilog/SV tremendously. Thankfully, OSVVM supports integer coverage and randomization natively, so it should be more comparable to SV/UVM (especially if the DUT is in VHDL), and even faster if intelligent coverage is used. Alas, I have no benchmarking to back any of this up. YMMV, Closed Course Professional Driver, do not try this at home, void where prohibited by law, etc. Andy From newsfish@newsfish Thu Aug 1 00:30:33 2024 X-Received: by 10.236.129.2 with SMTP id g2mr4875506yhi.2.1406233002256; Thu, 24 Jul 2014 13:16:42 -0700 (PDT) X-Received: by 10.182.2.107 with SMTP id 11mr3849obt.41.1406233001980; Thu, 24 Jul 2014 13:16:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j15no2389091qaq.0!news-out.google.com!eg1ni2igc.0!nntp.google.com!h18no6966541igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Jul 2014 13:16:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: Andy Injection-Date: Thu, 24 Jul 2014 20:16:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1969 X-Received-Body-CRC: 2934864748 Xref: news.eternal-september.org comp.lang.vhdl:3197 Yes, that's it in a nutshell (wrapper architectures). Doing anything except black box testing on the gate level model generally t= akes lots of work, and is not often portable between gate level and RTL ver= ification. What wrapper architectures (and other similar techniques using configuratio= ns) are best at is observing internal interfaces and making sure they are o= perating per spec, sometimes including inserting errors to see how the rest= of the system responds. This often has more to do with ensuring a robust, = maintainable implementation rather than just a functional implementation. Andy From newsfish@newsfish Thu Aug 1 00:30:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Marc Jenkins Newsgroups: comp.lang.vhdl Subject: Wired Or in VHDL Date: Fri, 25 Jul 2014 11:58:07 +0200 Organization: A noiseless patient Spider Lines: 10 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: mx05.eternal-september.org; posting-host="4b81f6907e2ae697561d06650f07d4c6"; logging-data="28758"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19EyHPbYRkWqjSAclsBiCe4" User-Agent: Unison/2.1.9 Cancel-Lock: sha1:vo/oFa4DW+jm7Ov+1LEvbPOgT9U= Xref: news.eternal-september.org comp.lang.vhdl:3198 Hello folks, Verilog supports the net type "wor" to implement a wired or logic. Is something similar possible in VHDL? Target plattform is an ASIC. Thanks, Marc From newsfish@newsfish Thu Aug 1 00:30:34 2024 X-Received: by 10.50.80.111 with SMTP id q15mr2351191igx.0.1406298802103; Fri, 25 Jul 2014 07:33:22 -0700 (PDT) X-Received: by 10.140.101.120 with SMTP id t111mr5084qge.39.1406298802031; Fri, 25 Jul 2014 07:33:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no7407976igc.0!news-out.google.com!j6ni12934qas.0!nntp.google.com!v10no2465439qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Jul 2014 07:33:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: KJ Injection-Date: Fri, 25 Jul 2014 14:33:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3199 On Friday, July 25, 2014 5:58:07 AM UTC-4, Marc Jenkins wrote: > Hello folks, > Verilog supports the net type "wor" to implement a wired or logic. > Is something similar possible in VHDL? > > Target plattform is an ASIC. Wired-or simply means that there are multiple drivers on a net. In VHDL land, the std_logic that nearly everybody uses for every signal definition can have multiple drivers. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 13:42:47 -0400 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Jul 2014 17:43:00 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="31530"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18tVrtEJzebBxyRpoN8TPVR" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:r85bmNn1p+AEZZ2UeM7W60gS1+I= Xref: news.eternal-september.org comp.lang.vhdl:3200 On 7/25/2014 5:58 AM, Marc Jenkins wrote: > Hello folks, > > Verilog supports the net type "wor" to implement a wired or logic. > Is something similar possible in VHDL? > > Target plattform is an ASIC. The question is why would you want that? To use a wired or you would need to have open collector (or open drain) outputs with a pull up resistor. Compared to just adding an OR gate this is a very slow method or very power hungry, take your pick. Do you really plan to use a wired or? Or do you expect this to be replaced with a real gate and are using it as shorthand? -- Rick From newsfish@newsfish Thu Aug 1 00:30:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 18:41:21 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 33 Message-ID: References: Injection-Date: Fri, 25 Jul 2014 18:41:21 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="17814"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ka7vUjrZcSTj4POku33w9" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:1nNpglZaN1zZxhEimUxNg1DMAqE= Xref: news.eternal-september.org comp.lang.vhdl:3201 In article , rickman wrote: >On 7/25/2014 5:58 AM, Marc Jenkins wrote: >> Hello folks, >> >> Verilog supports the net type "wor" to implement a wired or logic. >> Is something similar possible in VHDL? >> >> Target plattform is an ASIC. > >The question is why would you want that? To use a wired or you would >need to have open collector (or open drain) outputs with a pull up >resistor. Compared to just adding an OR gate this is a very slow method >or very power hungry, take your pick. > >Do you really plan to use a wired or? Or do you expect this to be >replaced with a real gate and are using it as shorthand? Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net to a logical 'or' gate. It's perfectly synthesizable, and quite useful. We've been using this construct for over 10 years on our Xilinx FPGAs on our CPU register bus. The returned read data (for when the CPU is issuing a read) is collected on a "wor" bus. All the slaves drive 0 when NOT addressed. When addressed, and issued a read, the one slave drives the actual read data on the bus. Works a charm, and greatly simplifies our code. Regards, Mark From newsfish@newsfish Thu Aug 1 00:30:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 16:30:18 -0400 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Jul 2014 20:30:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="6549"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/H5Q63tVdsdtyTjOuhB9tp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:JTBTHEPTrQg7ctgi/uIL1mNDQP4= Xref: news.eternal-september.org comp.lang.vhdl:3202 On 7/25/2014 2:41 PM, Mark Curry wrote: > In article , rickman wrote: >> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>> Hello folks, >>> >>> Verilog supports the net type "wor" to implement a wired or logic. >>> Is something similar possible in VHDL? >>> >>> Target plattform is an ASIC. >> >> The question is why would you want that? To use a wired or you would >> need to have open collector (or open drain) outputs with a pull up >> resistor. Compared to just adding an OR gate this is a very slow method >> or very power hungry, take your pick. >> >> Do you really plan to use a wired or? Or do you expect this to be >> replaced with a real gate and are using it as shorthand? > > Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net > to a logical 'or' gate. It's perfectly synthesizable, and quite useful. > > We've been using this construct for over 10 years on our Xilinx FPGAs > on our CPU register bus. The returned read data (for when the CPU > is issuing a read) is collected on a "wor" bus. All the slaves > drive 0 when NOT addressed. When addressed, and issued a read, the > one slave drives the actual read data on the bus. > > Works a charm, and greatly simplifies our code. Synthesizable yes, useful...? -- Rick From newsfish@newsfish Thu Aug 1 00:30:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 21:56:58 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 45 Message-ID: References: Injection-Date: Fri, 25 Jul 2014 21:56:58 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="6504"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX191ctctT6G5DQFpb4Ki/eQ5" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:xoEjeIHKwGoAlU0QPMYd14YN2I4= Xref: news.eternal-september.org comp.lang.vhdl:3203 In article , rickman wrote: >On 7/25/2014 2:41 PM, Mark Curry wrote: >> In article , rickman wrote: >>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>>> Hello folks, >>>> >>>> Verilog supports the net type "wor" to implement a wired or logic. >>>> Is something similar possible in VHDL? >>>> >>>> Target plattform is an ASIC. >>> >>> The question is why would you want that? To use a wired or you would >>> need to have open collector (or open drain) outputs with a pull up >>> resistor. Compared to just adding an OR gate this is a very slow method >>> or very power hungry, take your pick. >>> >>> Do you really plan to use a wired or? Or do you expect this to be >>> replaced with a real gate and are using it as shorthand? >> >> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net >> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. >> >> We've been using this construct for over 10 years on our Xilinx FPGAs >> on our CPU register bus. The returned read data (for when the CPU >> is issuing a read) is collected on a "wor" bus. All the slaves >> drive 0 when NOT addressed. When addressed, and issued a read, the >> one slave drives the actual read data on the bus. >> >> Works a charm, and greatly simplifies our code. > >Synthesizable yes, useful...? Very useful. We've got a much cleaner, reusable structure setup for register configuration. There's nothing to do to add/subtract (sometimes via the setting of a parameter) more registers on the bus. It just works. It's a bit hard to describe in a small example. But we've got significant code size reduction using this structure. Some were uncomfortable at first with the "multi-driver" implications, or collision problems. But we've found that neither are a problem at all. Regards, Mark From newsfish@newsfish Thu Aug 1 00:30:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 19:04:23 -0400 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Jul 2014 23:04:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="378"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18UUoAd0+mBMzg3AB5IFExs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:kFsGmO4vLLUxVF5+zqLzhMnq5jU= Xref: news.eternal-september.org comp.lang.vhdl:3204 On 7/25/2014 5:56 PM, Mark Curry wrote: > In article , rickman wrote: >> On 7/25/2014 2:41 PM, Mark Curry wrote: >>> In article , rickman wrote: >>>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>>>> Hello folks, >>>>> >>>>> Verilog supports the net type "wor" to implement a wired or logic. >>>>> Is something similar possible in VHDL? >>>>> >>>>> Target plattform is an ASIC. >>>> >>>> The question is why would you want that? To use a wired or you would >>>> need to have open collector (or open drain) outputs with a pull up >>>> resistor. Compared to just adding an OR gate this is a very slow method >>>> or very power hungry, take your pick. >>>> >>>> Do you really plan to use a wired or? Or do you expect this to be >>>> replaced with a real gate and are using it as shorthand? >>> >>> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net >>> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. >>> >>> We've been using this construct for over 10 years on our Xilinx FPGAs >>> on our CPU register bus. The returned read data (for when the CPU >>> is issuing a read) is collected on a "wor" bus. All the slaves >>> drive 0 when NOT addressed. When addressed, and issued a read, the >>> one slave drives the actual read data on the bus. >>> >>> Works a charm, and greatly simplifies our code. >> >> Synthesizable yes, useful...? > > Very useful. We've got a much cleaner, reusable structure setup for > register configuration. There's nothing to do to add/subtract (sometimes > via the setting of a parameter) more registers on the bus. It just works. > > It's a bit hard to describe in a small example. But we've got significant > code size reduction using this structure. Some were uncomfortable at first > with the "multi-driver" implications, or collision problems. But we've found > that neither are a problem at all. No need for examples. I understand perfectly what you are describing. But this is a construct that is in some respects the equivalent of a global variable and creates issues for verifying code depending on your methods. If it works for you then great. :) -- Rick From newsfish@newsfish Thu Aug 1 00:30:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Sat, 26 Jul 2014 00:06:23 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 67 Message-ID: References: Injection-Date: Sat, 26 Jul 2014 00:06:23 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="18744"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/opioylKF+vDkBg2s/l4Sz" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:45I5dPeOO4kQQpNAkt0Jf+NhgXY= Xref: news.eternal-september.org comp.lang.vhdl:3205 In article , rickman wrote: >On 7/25/2014 5:56 PM, Mark Curry wrote: >> In article , rickman wrote: >>> On 7/25/2014 2:41 PM, Mark Curry wrote: >>>> In article , rickman wrote: >>>>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>>>>> Hello folks, >>>>>> >>>>>> Verilog supports the net type "wor" to implement a wired or logic. >>>>>> Is something similar possible in VHDL? >>>>>> >>>>>> Target plattform is an ASIC. >>>>> >>>>> The question is why would you want that? To use a wired or you would >>>>> need to have open collector (or open drain) outputs with a pull up >>>>> resistor. Compared to just adding an OR gate this is a very slow method >>>>> or very power hungry, take your pick. >>>>> >>>>> Do you really plan to use a wired or? Or do you expect this to be >>>>> replaced with a real gate and are using it as shorthand? >>>> >>>> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net >>>> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. >>>> >>>> We've been using this construct for over 10 years on our Xilinx FPGAs >>>> on our CPU register bus. The returned read data (for when the CPU >>>> is issuing a read) is collected on a "wor" bus. All the slaves >>>> drive 0 when NOT addressed. When addressed, and issued a read, the >>>> one slave drives the actual read data on the bus. >>>> >>>> Works a charm, and greatly simplifies our code. >>> >>> Synthesizable yes, useful...? >> >> Very useful. We've got a much cleaner, reusable structure setup for >> register configuration. There's nothing to do to add/subtract (sometimes >> via the setting of a parameter) more registers on the bus. It just works. >> >> It's a bit hard to describe in a small example. But we've got significant >> code size reduction using this structure. Some were uncomfortable at first >> with the "multi-driver" implications, or collision problems. But we've found >> that neither are a problem at all. > >No need for examples. I understand perfectly what you are describing. >But this is a construct that is in some respects the equivalent of a >global variable and creates issues for verifying code depending on your >methods. If it works for you then great. :) Rickman, I was among those that cast a suspicious eye on the construct when I first saw it. But it really works fine and is NOT comparable to a global variable at all IMHO. I think of it as the same mux as others do by hand to mux the readdata back - just broken up. i.e. think of the readmux as a sum of products: y = ( sel0 & in0 ) | ( sel1 & in1 ) | ( sel2 & in2 ) | ... Where we force the slave modules themselves to do the "AND" masking. Then the 'OR' is taken care of automatically with the 'wor' multi-driver. There's really no verification issues that we have with using this. It's very straightforward. --Mark From newsfish@newsfish Thu Aug 1 00:30:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 22:15:54 -0400 Organization: A noiseless patient Spider Lines: 97 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Jul 2014 02:16:06 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25268"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ser5+mHtbw6lSsLdyt1/L" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:bnqDTPLZZ7urr9S2C+Cs9PB5DWA= Xref: news.eternal-september.org comp.lang.vhdl:3206 On 7/25/2014 8:06 PM, Mark Curry wrote: > In article , rickman wrote: >> On 7/25/2014 5:56 PM, Mark Curry wrote: >>> In article , rickman wrote: >>>> On 7/25/2014 2:41 PM, Mark Curry wrote: >>>>> In article , rickman wrote: >>>>>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>>>>>> Hello folks, >>>>>>> >>>>>>> Verilog supports the net type "wor" to implement a wired or logic. >>>>>>> Is something similar possible in VHDL? >>>>>>> >>>>>>> Target plattform is an ASIC. >>>>>> >>>>>> The question is why would you want that? To use a wired or you would >>>>>> need to have open collector (or open drain) outputs with a pull up >>>>>> resistor. Compared to just adding an OR gate this is a very slow method >>>>>> or very power hungry, take your pick. >>>>>> >>>>>> Do you really plan to use a wired or? Or do you expect this to be >>>>>> replaced with a real gate and are using it as shorthand? >>>>> >>>>> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net >>>>> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. >>>>> >>>>> We've been using this construct for over 10 years on our Xilinx FPGAs >>>>> on our CPU register bus. The returned read data (for when the CPU >>>>> is issuing a read) is collected on a "wor" bus. All the slaves >>>>> drive 0 when NOT addressed. When addressed, and issued a read, the >>>>> one slave drives the actual read data on the bus. >>>>> >>>>> Works a charm, and greatly simplifies our code. >>>> >>>> Synthesizable yes, useful...? >>> >>> Very useful. We've got a much cleaner, reusable structure setup for >>> register configuration. There's nothing to do to add/subtract (sometimes >>> via the setting of a parameter) more registers on the bus. It just works. >>> >>> It's a bit hard to describe in a small example. But we've got significant >>> code size reduction using this structure. Some were uncomfortable at first >>> with the "multi-driver" implications, or collision problems. But we've found >>> that neither are a problem at all. >> >> No need for examples. I understand perfectly what you are describing. >> But this is a construct that is in some respects the equivalent of a >> global variable and creates issues for verifying code depending on your >> methods. If it works for you then great. :) > > Rickman, > > I was among those that cast a suspicious eye on the construct when I > first saw it. But it really works fine and is NOT comparable to > a global variable at all IMHO. > > I think of it as the same mux as others do by hand to > mux the readdata back - just broken up. i.e. think > of the readmux as a sum of products: > y = ( sel0 & in0 ) | ( sel1 & in1 ) | ( sel2 & in2 ) | ... > > Where we force the slave modules themselves to do the "AND" masking. > Then the 'OR' is taken care of automatically with the 'wor' multi-driver. > > There's really no verification issues that we have with using this. > It's very straightforward. I might not understand this correctly since I am much more the VHDL programmer (where the wire or is seldom used, in fact, can that be done?) than a Verilog programmer... So there is one net with multiple drivers. When *any* of the drivers outputs a 1 the net is a 1, hence the wire or name. So if you have a 1 on the net when you aren't expecting a 1, how do you identify the driver unless you look at the inputs to all the drivers in all the different modules? To me that is a problem and is one of the reasons why buses like this are a PITA to debug in real hardware. This is commonly referred to as "hanging" the bus. By using an explicit mux the only signal that can drive the output of the mux is the signal that is selected at that moment. Look at the select lines, look at the corresponding input and continue to trace back from there. This is not an insurmountable problem. As I said this is commonly used in real hardware, just not inside chips very often. You say it makes the code easier to read, I think it splits the logic for a simple mux across multiple modules and makes it harder to debug. Consider a software technique of encapsulating decisions and functions. The wire or is the opposite of that since the mux logic is spread across modules. Different horses for different courses. :) -- Rick From newsfish@newsfish Thu Aug 1 00:30:36 2024 X-Received: by 10.42.10.66 with SMTP id p2mr9742545icp.28.1406353679611; Fri, 25 Jul 2014 22:47:59 -0700 (PDT) X-Received: by 10.50.50.205 with SMTP id e13mr234118igo.17.1406353679524; Fri, 25 Jul 2014 22:47:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no4548340igc.0!news-out.google.com!px9ni0igc.0!nntp.google.com!h18no7789787igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Jul 2014 22:47:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e816e99-8bce-40b2-99e8-bacfed6b5e47@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: Dio Gratia Injection-Date: Sat, 26 Jul 2014 05:47:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3207 On Monday, July 14, 2014 6:31:46 PM UTC+12, alb wrote: > > I would rather think they are two different language constructs, each > with its own characteristics. You can infer a register with a concurrent > assignment, but not a latch. Which one you use is a matter of style, as > long as it matches your desired behavior. >From IEEE Std 1076.6-2004 6.2.1.2 Level-sensitive storage from concurrent signal assignment A level-sensitive storage element shall be modeled for a signal that is assigned in a concurrent signal assignment statement that can be mapped to a process that adheres to the rules in 6.2.1.1. Example 1: LEV_SENS_7: Q <= '0' when RESET ='1' else -- This is identical D when ENABLE; -- to LEV_SENS_1 in 6.2.1.1, Example 2: LEV_SENS_8: With ENABLE select Q <= D when '1', Q when others; -- Identical to LEV_SENS_2 in 6.2.1.1, -- and models combinational logic. Example 3: LEV_SENS_9: with ENABLE select Q <= D when '1', unaffected when others; (There's more). From newsfish@newsfish Thu Aug 1 00:30:37 2024 X-Received: by 10.43.85.201 with SMTP id ap9mr6646536icc.11.1406742465013; Wed, 30 Jul 2014 10:47:45 -0700 (PDT) X-Received: by 10.140.93.181 with SMTP id d50mr71366qge.0.1406742464883; Wed, 30 Jul 2014 10:47:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no6544330igc.0!news-out.google.com!px9ni176igc.0!nntp.google.com!h18no10628324igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Jul 2014 10:47:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> Subject: Could you explain "BUT NOT signal_declaration" in this tutorial? From: fl Injection-Date: Wed, 30 Jul 2014 17:47:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3208 Hi, I learn concurrent clause from this link: http://www.csee.umbc.edu/portal/help/VHDL/concurrent.html I do not understand "BUT NOT signal_declaration", see below please. Could you explain what it intends to say? Thanks, process_declarative_items are any of: subprogram declaration subprogram body type declaration subtype declaration constant, object declaration variable, object declaration file, object declaration alias declaration attribute declaration attribute specification use clause group template declaration group declaration BUT NOT signal_declaration, all signals must be declared outside the process. sig1 <= sig2 and sig3; -- considered here as a sequential statement -- sig1 is set outside the process upon exit or wait From newsfish@newsfish Thu Aug 1 00:30:37 2024 X-Received: by 10.42.119.82 with SMTP id a18mr7074737icr.19.1406748445801; Wed, 30 Jul 2014 12:27:25 -0700 (PDT) X-Received: by 10.182.108.165 with SMTP id hl5mr23016obb.27.1406748445613; Wed, 30 Jul 2014 12:27:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no6607370igc.0!news-out.google.com!px9ni176igc.0!nntp.google.com!h18no10705995igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Jul 2014 12:27:24 -0700 (PDT) In-Reply-To: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1cecf7c0-7e73-46d0-aa9f-46c034f727dc@googlegroups.com> Subject: Re: Could you explain "BUT NOT signal_declaration" in this tutorial? From: Jim Lewis Injection-Date: Wed, 30 Jul 2014 19:27:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3209 It simply notes that signal declarations are not allowed in a process. Instead for most applications you declare them in the architecture. >From the perspective of a process with a sensitivity list that is intended to create combinatorial logic, this makes sense. However, from the perspective of a process with a wait statement (used frequently in testbenches), perhaps not. From newsfish@newsfish Thu Aug 1 00:30:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx02.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: Could you explain "BUT NOT signal_declaration" in this tutorial? Newsgroups: comp.lang.vhdl References: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 17 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1406749346 62.49.20.82 (Wed, 30 Jul 2014 19:42:26 UTC) NNTP-Posting-Date: Wed, 30 Jul 2014 19:42:26 UTC Date: Wed, 30 Jul 2014 19:42:26 GMT X-Received-Body-CRC: 1375691008 X-Received-Bytes: 1259 Xref: news.eternal-september.org comp.lang.vhdl:3210 On Wed, 30 Jul 2014 10:47:44 -0700, fl wrote: > Hi, > > I learn concurrent clause from this link: > > http://www.csee.umbc.edu/portal/help/VHDL/concurrent.html > > I do not understand "BUT NOT signal_declaration", see below please. > Could you explain what it intends to say? > Simply put, signals are the means of communicating between processes. So declaring a signal within a process, visible only within that process, doesn't make a lot of sense. - Brian From newsfish@newsfish Thu Aug 1 00:30:37 2024 X-Received: by 10.68.137.99 with SMTP id qh3mr2724332pbb.2.1406751837175; Wed, 30 Jul 2014 13:23:57 -0700 (PDT) X-Received: by 10.140.100.182 with SMTP id s51mr25473qge.29.1406751837118; Wed, 30 Jul 2014 13:23:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no10741146igc.0!news-out.google.com!b3ni3606qac.1!nntp.google.com!j15no3492446qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Jul 2014 13:23:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 References: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Could you explain "BUT NOT signal_declaration" in this tutorial? From: fl Injection-Date: Wed, 30 Jul 2014 20:23:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3211 On Wednesday, July 30, 2014 3:42:26 PM UTC-4, Brian Drummond wrote: > On Wed, 30 Jul 2014 10:47:44 -0700, fl wrote: > > I do not understand "BUT NOT signal_declaration", see below please. > > Could you explain what it intends to say? > > > Simply put, signals are the means of communicating between processes. So > declaring a signal within a process, visible only within that process, > doesn't make a lot of sense. > > - Brian Thanks. I am clear about the signal declaration. For "BUT NOT", it is a typo for "BUT NOTE"? Or something else? From newsfish@newsfish Thu Aug 1 00:30:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Could you explain "BUT NOT signal_declaration" in this tutorial? Date: Wed, 30 Jul 2014 21:41:13 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 01:41:31 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="27666"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19bE4cgWT9A2zeWIYnXOpdx" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:UCD3dsW341zAyS634UHJjSbKKn8= Xref: news.eternal-september.org comp.lang.vhdl:3212 On 7/30/2014 4:23 PM, fl wrote: > On Wednesday, July 30, 2014 3:42:26 PM UTC-4, Brian Drummond wrote: >> On Wed, 30 Jul 2014 10:47:44 -0700, fl wrote: >>> I do not understand "BUT NOT signal_declaration", see below please. >>> Could you explain what it intends to say? >>> >> Simply put, signals are the means of communicating between processes. So >> declaring a signal within a process, visible only within that process, >> doesn't make a lot of sense. >> >> - Brian > > Thanks. I am clear about the signal declaration. > For "BUT NOT", it is a typo for "BUT NOTE"? Or something else? It is just English, not part of the formal language for VHDL. process_declarative_items may be any of this list, but not a signal_declaration. -- Rick From newsfish@newsfish Thu Aug 1 00:30:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Thu, 31 Jul 2014 15:28:28 +0200 Lines: 42 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net og3QS8FN70CHeWOD+UDYfAf2o2SC48xZ81HHhhFcm5pT21zTNu Cancel-Lock: sha1:V5fmKBnVSAHWMIjIdFckLuQDghQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:3213 In case anyone's still interested: This gets even worse in Vivado. Not even driving a std_ulogic from two different places causes an error or warning during synthesis... The best you can do is to receive a critical warning, but only under certain circumstances (as it turns out, it makes a difference if one of the drivers drives a constant value or not, for whatever reason...). I've reported it to Xilinx, but as of now they don't believe me that this is a problem: http://tinyurl.com/lkzgsgj I'll be on vacation for awhile now, maybe the problem will have magically disappeared when I'm back... Am 13.07.2014 um 11:13 schrieb Sean Durkin: > Hi *, > > I'm sure one of you can clear this up: > > During debugging recently I discovered a bug in a module of mine: I had > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). > > Now, the result in simulation is as expected: the concurrent assignment > usually "wins", with occasional 'X' in simulation. > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" > error/warning or something similar. Why isn't there any? > > I always thought that a concurrent signal assignment is more or less > just a less verbose version of a process with the right-hand-side > signals in the sensitivity list. So basically what I had was assignments > to the same signal from two different processes (one sequential one > combinatorial), which should cause multiple drivers warnings. What would > the hardware really do in that case, anyway? > > Sean > From newsfish@newsfish Thu Aug 1 00:30:38 2024 X-Received: by 10.42.188.84 with SMTP id cz20mr14361505icb.1.1406831063925; Thu, 31 Jul 2014 11:24:23 -0700 (PDT) X-Received: by 10.50.138.69 with SMTP id qo5mr8718igb.7.1406831063799; Thu, 31 Jul 2014 11:24:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no7213366igc.0!news-out.google.com!px9ni1igc.0!nntp.google.com!h18no7213356igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 11:24:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 18:24:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3214 On Thursday, 31 July 2014 21:28:28 UTC+8, Sean Durkin wrote: > In case anyone's still interested: >=20 >=20 >=20 > This gets even worse in Vivado. Not even driving a std_ulogic from two >=20 > different places causes an error or warning during synthesis... The best >=20 > you can do is to receive a critical warning, but only under certain >=20 > circumstances (as it turns out, it makes a difference if one of the >=20 > drivers drives a constant value or not, for whatever reason...). >=20 >=20 >=20 > I've reported it to Xilinx, but as of now they don't believe me that >=20 > this is a problem: >=20 >=20 >=20 > http://tinyurl.com/lkzgsgj >=20 >=20 >=20 > I'll be on vacation for awhile now, maybe the problem will have >=20 > magically disappeared when I'm back... >=20 I've had a similar problem with Altera before, but in my case it had to do = with Quartus optimising away the signals when they aren't used in the desig= n (e.g. not read by another signal, or not used as an output, etc.). Quartus has the bad habit of optimising away (reducing) multiple drivers to= an unresolved net, BEFORE checking that the net is unresolved and it has m= ultiple drivers (and therefore should give an error). I'm not sure if this = changed for the latest version. For those interested, you can try the follo= wing code and see if Quartus incorrectly optimises away the design without = giving any errors: entity test is port(a0,a1:in std_ulogic; q0:out std_ulogic); end entity test; architecture shouldErrorAndNotOptimise of test is signal q1:std_ulogic; begin q0<=3Da0; -- wire synthesised from a0 to q0. correct behaviour. q1<=3Da1; -- assignment to an internal net. q1<=3Da0; -- multiple assignment to an unresolved net. -- should report error here. =20 --q0<=3Da1; -- if this line is enabled, Quartus correctly=20 -- gives an error on multiple drivers driving q0. end architecture shouldErrorAndNotOptimise; I wrote this from memory, and have not tested this code on the latest Quart= us. But yes, I did have these problems before when using the tool. The reas= on why Quartus errored out for q0 and not q1 was because q0 was "used" - it= was the output of the design, while q1 was an internal signal that got opt= imised away. Anyway, I still perceive this as a bug in Quartus, as the code= is incorrect as per my understanding of the LRM. Quartus should have throw= n me an error, as ModelSim correctly did. Now, to the topic about having multiple drivers to a RESOLVED net. Altera has partial support for resolution functions (which is good), but th= ere are still problems with the feature. Having multiple drivers on a resol= ved net is fine; simulation tools usually resolve to an 'X' (or whatever th= e resolution function resolves to) and this will be correctly displayed in = the simulator. For synthesis tools however, I believe they should give eith= er a Warning or a Critical Warning, but should not give an error. At least = warn us that they are multiple drivers to a resolved signal. Both Altera an= d Xilinx choke at this. For Altera, I think resolved types only work correctly when a custom resolu= tion function is used - when you try to have multiple drivers to a signal o= f a predefined resolved type (such as std_logic / std_logic_vector), you wo= uld, incorrectly, be puked by Quartus with an error. The tool should have i= nvoked the predefined resolution function and automatically resolve the mul= tiple drivers, while also giving us a Critical Warning. Again, I'm not sure= if this behaviour changed for the latest version - last I tried this was a= t least a couple of years back. Anyway, I have supported your claim in Xilinx's forum. For those who really= need this, do rally your support. -dan From newsfish@newsfish Thu Aug 1 00:30:39 2024 X-Received: by 10.236.26.206 with SMTP id c54mr39798yha.44.1406832830910; Thu, 31 Jul 2014 11:53:50 -0700 (PDT) X-Received: by 10.50.41.103 with SMTP id e7mr14475igl.8.1406832830555; Thu, 31 Jul 2014 11:53:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v10no3578058qac.1!news-out.google.com!px9ni1igc.0!nntp.google.com!h18no7231513igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 11:53:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 18:53:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 7378 X-Received-Body-CRC: 292099030 Xref: news.eternal-september.org comp.lang.vhdl:3215 On Saturday, 26 July 2014 10:15:54 UTC+8, rickman wrote: > On 7/25/2014 8:06 PM, Mark Curry wrote: > > > In article , rickman wrote: > > >> On 7/25/2014 5:56 PM, Mark Curry wrote: > > >>> In article , rickman wrote: > > >>>> On 7/25/2014 2:41 PM, Mark Curry wrote: > > >>>>> In article , rickman wrote: > > >>>>>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: > > >>>>>>> Hello folks, > > >>>>>>> > > >>>>>>> Verilog supports the net type "wor" to implement a wired or logic. > > >>>>>>> Is something similar possible in VHDL? > > >>>>>>> > > >>>>>>> Target plattform is an ASIC. > > >>>>>> > > >>>>>> The question is why would you want that? To use a wired or you would > > >>>>>> need to have open collector (or open drain) outputs with a pull up > > >>>>>> resistor. Compared to just adding an OR gate this is a very slow method > > >>>>>> or very power hungry, take your pick. > > >>>>>> > > >>>>>> Do you really plan to use a wired or? Or do you expect this to be > > >>>>>> replaced with a real gate and are using it as shorthand? > > >>>>> > > >>>>> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net > > >>>>> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. > > >>>>> > > >>>>> We've been using this construct for over 10 years on our Xilinx FPGAs > > >>>>> on our CPU register bus. The returned read data (for when the CPU > > >>>>> is issuing a read) is collected on a "wor" bus. All the slaves > > >>>>> drive 0 when NOT addressed. When addressed, and issued a read, the > > >>>>> one slave drives the actual read data on the bus. > > >>>>> > > >>>>> Works a charm, and greatly simplifies our code. > > >>>> > > >>>> Synthesizable yes, useful...? > > >>> > > >>> Very useful. We've got a much cleaner, reusable structure setup for > > >>> register configuration. There's nothing to do to add/subtract (sometimes > > >>> via the setting of a parameter) more registers on the bus. It just works. > > >>> > > >>> It's a bit hard to describe in a small example. But we've got significant > > >>> code size reduction using this structure. Some were uncomfortable at first > > >>> with the "multi-driver" implications, or collision problems. But we've found > > >>> that neither are a problem at all. > > >> > > >> No need for examples. I understand perfectly what you are describing. > > >> But this is a construct that is in some respects the equivalent of a > > >> global variable and creates issues for verifying code depending on your > > >> methods. If it works for you then great. :) > > > > > > Rickman, > > > > > > I was among those that cast a suspicious eye on the construct when I > > > first saw it. But it really works fine and is NOT comparable to > > > a global variable at all IMHO. > > > > > > I think of it as the same mux as others do by hand to > > > mux the readdata back - just broken up. i.e. think > > > of the readmux as a sum of products: > > > y = ( sel0 & in0 ) | ( sel1 & in1 ) | ( sel2 & in2 ) | ... > > > > > > Where we force the slave modules themselves to do the "AND" masking. > > > Then the 'OR' is taken care of automatically with the 'wor' multi-driver. > > > > > > There's really no verification issues that we have with using this. > > > It's very straightforward. > > > > I might not understand this correctly since I am much more the VHDL > > programmer (where the wire or is seldom used, in fact, can that be > > done?) than a Verilog programmer... So there is one net with multiple > > drivers. When *any* of the drivers outputs a 1 the net is a 1, hence > > the wire or name. > > > > So if you have a 1 on the net when you aren't expecting a 1, how do you > > identify the driver unless you look at the inputs to all the drivers in > > all the different modules? To me that is a problem and is one of the > > reasons why buses like this are a PITA to debug in real hardware. This > > is commonly referred to as "hanging" the bus. > > > > By using an explicit mux the only signal that can drive the output of > > the mux is the signal that is selected at that moment. Look at the > > select lines, look at the corresponding input and continue to trace back > > from there. > > > > This is not an insurmountable problem. As I said this is commonly used > > in real hardware, just not inside chips very often. You say it makes > > the code easier to read, I think it splits the logic for a simple mux > > across multiple modules and makes it harder to debug. > > > > Consider a software technique of encapsulating decisions and functions. > > The wire or is the opposite of that since the mux logic is spread > > across modules. > > > > Different horses for different courses. :) > > > > -- > > > > Rick Haven't tried resolution functions on Xilinx. But from the sound of it, I believe your 'wor' can be easily done with a custom resolution function in VHDL: entity test is port(d0,d1:in std_ulogic; q:out resolved_wor std_ulogic); end entity test; architecture rtl of test is begin q<=d0; q<=d1; end architecture rtl; Not sure if Vivado supports this though. With a bit of hacking, you can get Quartus to support this. Last I know, Quartus chokes on custom resolved ports, so you need to declare an internal signal that uses the custom resolution function: signal s:resolved_wor std_ulogic; and treat s as having multiple drivers from d0 and d1. Then drive the output q from the internal resolved signal s. You can write custom resolution functions to resolve outputs on OR, AND, or anything you want. We prefer not to have special keywords like wor, wand, etc. that clutter our language. :) These things can be easily written as custom functions by the designer. -dan From newsfish@newsfish Thu Aug 1 00:30:39 2024 X-Received: by 10.236.78.70 with SMTP id f46mr294697yhe.24.1406840158960; Thu, 31 Jul 2014 13:55:58 -0700 (PDT) X-Received: by 10.50.138.70 with SMTP id qo6mr11217igb.0.1406840158675; Thu, 31 Jul 2014 13:55:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j15no3665502qaq.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11583727igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 13:55:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 20:55:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3216 On Thursday, 24 July 2014 18:15:38 UTC+8, Martin Trummer wrote: > Hi, >=20 >=20 >=20 > Having following VHDL snippet. This masks put bits from an input at a=20 >=20 > certain position >=20 >=20 >=20 > if mask_ctrl > 0 then >=20 > for i in 0 to DWITH-1 loop >=20 > if i < mask_ctrl then >=20 > next_data(i) <=3D data(i); >=20 > mask_data(i) <=3D alu_out(i); >=20 > else >=20 > next_data(i) <=3D '0'; >=20 > mask_data(i) <=3D '0'; >=20 > end if; >=20 > end loop; >=20 > end if; >=20 >=20 >=20 > next_data is an input for a FF, mask_data is a combinatorical output.=20 >=20 > Are possibilities to optimize this behavior with respect to chip area? >=20 >=20 >=20 > Thanks! >=20 >=20 >=20 > Best regards >=20 > M. T. Guessing from your post on what you're trying to do, why not create a mask = variable and assign it accordingly based upon the condition you want? Your = condition "if i'1', others=3D>'0'); =20 next_data(DWIDTH-1 downto 0)<=3Ddata(DWIDTH-1 downto 0) and mask; mask_data(DWIDTH-1 downto 0)<=3Dalu_out(DWIDTH-1 downto 0) and mask; end process; -- Daniel | www.tauhop.com ~eats, drinks, sleeps, and breathes VHDL From newsfish@newsfish Thu Aug 1 00:30:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 20:58:39 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 50 Message-ID: References: Injection-Date: Thu, 31 Jul 2014 20:58:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="15168"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+a4H0CE18RbjdWOGhM3+Ia" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:j+eM//VW9AG3Bs6Ft6TkKLXcWcQ= Xref: news.eternal-september.org comp.lang.vhdl:3217 In article , Daniel Kho wrote: > >Haven't tried resolution functions on Xilinx. But from the sound of it, I >believe your 'wor' can be easily done with a custom resolution function in > VHDL: > >entity test is port(d0,d1:in std_ulogic; q:out resolved_wor std_ulogic); >end entity test; > >architecture rtl of test is begin > q<=d0; > q<=d1; >end architecture rtl; > >Not sure if Vivado supports this though. With a bit of hacking, you can get >Quartus to support this. Last I know, Quartus chokes on custom resolved ports, >so you need to declare an internal signal >that uses the custom resolution function: > signal s:resolved_wor std_ulogic; > >and treat s as having multiple drivers from d0 and d1. Then drive the output >q from the internal resolved signal s. > >You can write custom resolution functions to resolve outputs on OR, AND, or >anything you want. We prefer not to have special keywords like wor, wand, etc. >that clutter our language. :) These things >can be easily written as custom functions by the designer. Dan, I'm not a VHDL person - can you detail more? How's the custom resolution function written? I.e. How's it support the variable number of inputs to the function? i.e. I want the 'resolved_wor' to resolve a variable number of drivers on the net. There's only one net. The net may driven locally, or thru a connection to a sub-entity's output port. Can I do this with VHDL, using custom resolution functions? Xilinx is dragging their feet supporting wor's in verilog thru Vivado. They've always supported it in ISE at least since ISE 6.xx, probably forever. If I can give them a VHDL example too, it might help. Thanks, Mark From newsfish@newsfish Thu Aug 1 00:30:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Optimize VHDL snippet for area Date: Thu, 31 Jul 2014 17:14:19 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 21:14:34 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22313"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19/edm6RM3Yl5E8dyBEfNrM" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:DAgAZzCy/U1BiI3e/1AL+aRPSzg= Xref: news.eternal-september.org comp.lang.vhdl:3218 On 7/24/2014 6:15 AM, Martin Trummer wrote: > Hi, > > Having following VHDL snippet. This masks put bits from an input at a > certain position > > if mask_ctrl > 0 then > for i in 0 to DWITH-1 loop > if i < mask_ctrl then > next_data(i) <= data(i); > mask_data(i) <= alu_out(i); > else > next_data(i) <= '0'; > mask_data(i) <= '0'; > end if; > end loop; > end if; > > next_data is an input for a FF, mask_data is a combinatorical output. > Are possibilities to optimize this behavior with respect to chip area? Trying to outsmart the compiler is hard to do. The only way I have found to do this is to design my own hardware and then code to describe that hardware. Others have pointed out the mistakes in your code that need to be addressed. I would suggest that you drop your thinking back to logic design 101 and draw a diagram of how you think the circuit should work. Then think of how this would best be implemented in your technology and only then think about how to describe it in the HDL to get what you want. A key point is to know what the source of mask_ctrl is. Is this a configuration register? Why is it encoded rather than specifying the mask directly?.... that would be the lowest chip area I think.... no area at all other than the mask logic itself. -- Rick From newsfish@newsfish Thu Aug 1 00:30:40 2024 X-Received: by 10.42.39.140 with SMTP id h12mr1002346ice.9.1406842161422; Thu, 31 Jul 2014 14:29:21 -0700 (PDT) X-Received: by 10.50.222.41 with SMTP id qj9mr23826igc.1.1406842161303; Thu, 31 Jul 2014 14:29:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11602241igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11602235igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 14:29:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9f1da2de-0517-4853-8ed8-2f8ca2c3d237@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 21:29:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3219 On Friday, 1 August 2014 05:14:19 UTC+8, rickman wrote: > > A key point is to know what the source of mask_ctrl is. Is this a > > configuration register? Why is it encoded rather than specifying the > > mask directly?.... that would be the lowest chip area I think.... no > > area at all other than the mask logic itself. > Exactly. I believe all the OP wants is just to mask the inputs. It should synthesise to all wires (from I/P to O/P) for the masked bits, and for the rest of the output bits - tied to ground. -- Daniel | www.tauhop.com ~eats, drinks, sleeps, and breathes VHDL From newsfish@newsfish Thu Aug 1 00:30:40 2024 X-Received: by 10.42.94.69 with SMTP id a5mr1014464icn.29.1406842687601; Thu, 31 Jul 2014 14:38:07 -0700 (PDT) X-Received: by 10.50.39.16 with SMTP id l16mr15684igk.7.1406842687506; Thu, 31 Jul 2014 14:38:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11605703igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11605698igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 14:38:06 -0700 (PDT) In-Reply-To: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45ab2df7-ca44-4c9f-a219-18818d92d074@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 21:38:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3220 On Friday, 1 August 2014 04:55:57 UTC+8, Daniel Kho wrote: > process(all) is > > variable mask:std_ulogic_vector(DWIDTH-1 downto 0); > > begin > > mask:=(0 to mask_ctrl-1=>'1', others=>'0'); > > > > next_data(DWIDTH-1 downto 0)<=data(DWIDTH-1 downto 0) and mask; > > mask_data(DWIDTH-1 downto 0)<=alu_out(DWIDTH-1 downto 0) and mask; > > end process; > > > > -- > > Daniel | www.tauhop.com > > ~eats, drinks, sleeps, and breathes VHDL Since the ranges are all the same, we can simplify this to: process(all) is variable mask:std_ulogic_vector(DWIDTH-1 downto 0); begin mask:=(0 to mask_ctrl-1=>'1', others=>'0'); next_data<=data and mask; mask_data<=alu_out and mask; end process; -- Daniel | www.tauhop.com ~eats, drinks, sleeps, and breathes VHDL From newsfish@newsfish Thu Aug 1 00:30:40 2024 X-Received: by 10.42.62.73 with SMTP id x9mr1181765ich.15.1406844269095; Thu, 31 Jul 2014 15:04:29 -0700 (PDT) X-Received: by 10.50.18.50 with SMTP id t18mr19816igd.10.1406844268925; Thu, 31 Jul 2014 15:04:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11617632igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11617621igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 15:04:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4a9a5bcb-8b89-4656-b201-6c712f92a573@googlegroups.com> Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 22:04:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3221 On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: > Dan, > > > > I'm not a VHDL person - can you detail more? How's the custom resolution > > function written? I.e. How's it support the variable number of inputs to > > the function? > > > > i.e. I want the 'resolved_wor' to resolve a variable number of drivers on the > > net. There's only one net. The net may driven locally, or thru a connection > > to a sub-entity's output port. > > > > Can I do this with VHDL, using custom resolution functions? > > > > Xilinx is dragging their feet supporting wor's in verilog thru Vivado. They've > > always supported it in ISE at least since ISE 6.xx, probably forever. > > If I can give them a VHDL example too, it might help. > > > > Thanks, > > > > Mark Hi Mark, There are some pretty good references on designing your own custom resolution functions in VHDL. I just did a search and found this: http://vhdl.renerta.com/source/vhd00058.htm There are also predefined (standard) resolution functions within the standard VHDL packages, and anyone can read them. An example of resolved_or (or resolved_wor in my previous post): function resolved_or(s:std_ulogic_vector) return std_logic is variable result:std_ulogic:='0'; begin for i in s'range loop result:=result or s(i); end loop; return result; end function resolved_or; These custom functions may be defined within an architecture (before the BEGIN), or within a VHDL package. -dan From newsfish@newsfish Thu Aug 1 00:30:41 2024 X-Received: by 10.43.70.132 with SMTP id yg4mr1304886icb.30.1406845424319; Thu, 31 Jul 2014 15:23:44 -0700 (PDT) X-Received: by 10.50.79.201 with SMTP id l9mr21072igx.5.1406845424230; Thu, 31 Jul 2014 15:23:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11626780igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11626769igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 15:23:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 22:23:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3222 On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: > I'm not a VHDL person - can you detail more? How's the custom resolution= =20 > function written? I.e. How's it support the variable number of inputs to > the function? >=20 Sorry for the multiple posting. Posted too quickly without reading your ent= ire question. :| A resolution function accepts as argument, a vector (or array) of the signa= l you wish to have multiple drivers on. Say for example you have a signal (= or output) net q as in my previous example, that you wish to have multiple = sources driving it. q is of an unresolved type std_ulogic, but you can appl= y the resolution function "resolved_wor" to resolve q to a deterministic va= lue from multiple sources driving it. q:out resolved_wor std_ulogic; To write a resolution function for q, you create one that accepts a vector = of std_ulogic (we can use the predefined std_ulogic_vector), and this array= contains all the multiple drivers that would be driving q. The resolution = function can then be written to resolve the output based on any resolution = logic you want. This can be a simple OR or AND, or can as complex as need b= e. The output (return value) of a resolution function must therefore be of = a resolved type (such as std_logic). function resolved_wor(s:std_ulogic_vector) return std_logic is begin ... end function resolved_wor; -dan From newsfish@newsfish Thu Aug 1 00:30:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Optimize VHDL snippet for area Date: Thu, 31 Jul 2014 19:17:23 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <9f1da2de-0517-4853-8ed8-2f8ca2c3d237@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 23:17:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3882"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18TIZIL/kT3VcRoyZBS1cEr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <9f1da2de-0517-4853-8ed8-2f8ca2c3d237@googlegroups.com> Cancel-Lock: sha1:UFYUzjnZhjvz0Oe53vfc7eDazyI= Xref: news.eternal-september.org comp.lang.vhdl:3223 On 7/31/2014 5:29 PM, Daniel Kho wrote: > On Friday, 1 August 2014 05:14:19 UTC+8, rickman wrote: >> >> A key point is to know what the source of mask_ctrl is. Is this a >> >> configuration register? Why is it encoded rather than specifying the >> >> mask directly?.... that would be the lowest chip area I think.... no >> >> area at all other than the mask logic itself. >> > > Exactly. I believe all the OP wants is just to mask the inputs. It should synthesise to all wires (from I/P to O/P) for the masked bits, and for the rest of the output bits - tied to ground. That would only be true if the mask value is constant. I assume it's a control register setting and can be changed from an encoded value 0, 1, 2, 3,... to a mask value 0...0000, 0...0001, 0...0011, 0...0111,... If the mask value changes depending on a real time logic function, then he will need to design the decoder too. If optimization is truly important (this is not a hugely large circuit after all) I bet I can beat the standard decoder design. -- Rick From newsfish@newsfish Thu Aug 1 00:30:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 23:18:47 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 65 Message-ID: References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> Injection-Date: Thu, 31 Jul 2014 23:18:47 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="4215"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+PRP4yQsGrzqW5OlpipAEl" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:MMPF0LjxEtl0vFADUZE80JbMJbk= Xref: news.eternal-september.org comp.lang.vhdl:3224 In article <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com>, Daniel Kho wrote: >On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: > >> I'm not a VHDL person - can you detail more? How's the custom resolution >> function written? I.e. How's it support the variable number of inputs to >> the function? >> > >Sorry for the multiple posting. Posted too quickly without reading >your entire question. :| > >A resolution function accepts as argument, a vector (or array) of >the signal you wish to have multiple drivers on. Say for example >you have a signal (or output) net q as in my previous example, that >you wish to have multiple sources driving it. q is of an unresolved >type std_ulogic, but you can apply the resolution function >"resolved_wor" to resolve q to a deterministic value from multiple >sources driving it. > q:out resolved_wor std_ulogic; > >To write a resolution function for q, you create one that accepts a >vector of std_ulogic (we can use the predefined std_ulogic_vector), >and this array contains all the multiple drivers that would be >driving q. The resolution function can then be written to resolve the >output based on any resolution logic you want. This can be a simple OR >or AND, or can as complex as need be. The output (return >value) of a resolution function must therefore be of a resolved type >(such as std_logic). > > function resolved_wor(s:std_ulogic_vector) return std_logic is begin > ... > end function resolved_wor; > Yeah - doesn't solve my problem. There's no "std_ulogic_vector" for the input to the function. There's only *ONE* net. The one net with multiple (resolved type) drivers on it. I don't see how this is "custom resolution function" is different than any other function? (Again, I'm not VHDL person). What I'm trying to do (verilog speak, sorry): cpu_reg cpu_reg1 ( `BUS_CONNECT, .data_o( reg1_val ) ); cpu_reg cpu_reg2 ( `BUS_CONNECT, .data_o( reg2_val ) ); cpu_reg cpu_reg3 ( `BUS_CONNECT, .data_o( reg3_val ) ); ... The `BUS_CONNECT is simple a verilog macro (probably a structure (record?) in VHDL) that hooks up the CPU bus interface. All the read data, is a wor net. Theres only one "read_data" net (an output of this entity) on BUS_CONNECT. (Think of it as 1 bit to make the testcase easier). "read_data" is 'wor' resolved for the multiple drivers on it. Generics/etc will conditionally compile in/out many cpu_regs. So I don't know how many drivers "read_data" has apriori. Nor could I easily define the width of the "std_ulogic_vector" input to your function. --Mark From newsfish@newsfish Thu Aug 1 00:30:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 19:23:38 -0400 Organization: A noiseless patient Spider Lines: 68 Message-ID: References: <4a9a5bcb-8b89-4656-b201-6c712f92a573@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 23:23:54 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="5825"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Et4cA8l5IBunRTES7rsQV" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <4a9a5bcb-8b89-4656-b201-6c712f92a573@googlegroups.com> Cancel-Lock: sha1:YwXr601GhDT6aPZoeOl4NIKyoEc= Xref: news.eternal-september.org comp.lang.vhdl:3225 On 7/31/2014 6:04 PM, Daniel Kho wrote: > On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: >> Dan, >> >> >> >> I'm not a VHDL person - can you detail more? How's the custom resolution >> >> function written? I.e. How's it support the variable number of inputs to >> >> the function? >> >> >> >> i.e. I want the 'resolved_wor' to resolve a variable number of drivers on the >> >> net. There's only one net. The net may driven locally, or thru a connection >> >> to a sub-entity's output port. >> >> >> >> Can I do this with VHDL, using custom resolution functions? >> >> >> >> Xilinx is dragging their feet supporting wor's in verilog thru Vivado. They've >> >> always supported it in ISE at least since ISE 6.xx, probably forever. >> >> If I can give them a VHDL example too, it might help. >> >> >> >> Thanks, >> >> >> >> Mark > > Hi Mark, > There are some pretty good references on designing your own custom resolution functions in VHDL. I just did a search and found this: > http://vhdl.renerta.com/source/vhd00058.htm > > There are also predefined (standard) resolution functions within the standard VHDL packages, and anyone can read them. > > An example of resolved_or (or resolved_wor in my previous post): > > function resolved_or(s:std_ulogic_vector) return std_logic is > variable result:std_ulogic:='0'; > begin > for i in s'range loop > result:=result or s(i); > end loop; > return result; > end function resolved_or; > > These custom functions may be defined within an architecture (before the BEGIN), or within a VHDL package. The resolved_or function you posted does not implement a wired or. The type used is just std_ulogic and the assignment is result := result or s(i); This is the or of all the bits in a bus. -- Rick From newsfish@newsfish Thu Aug 1 00:30:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 16:39:58 -0700 Organization: Highland Technology, Inc. Lines: 32 Message-ID: <20140731163958.633a719e@rg.highlandtechnology.com> References: <4a9a5bcb-8b89-4656-b201-6c712f92a573@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="e25680cee057b0c034ced785d61acc50"; logging-data="18671"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/cgu/nDN34f2alz2eGRDJf" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:k4j+5APXLpUPlOj46t/VDxjHRlw= Xref: news.eternal-september.org comp.lang.vhdl:3226 On Thu, 31 Jul 2014 19:23:38 -0400 rickman wrote: > On 7/31/2014 6:04 PM, Daniel Kho wrote: > > On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: > > > > An example of resolved_or (or resolved_wor in my previous post): > > > > function resolved_or(s:std_ulogic_vector) return std_logic is > > variable result:std_ulogic:='0'; > > begin > > for i in s'range loop > > result:=result or s(i); > > end loop; > > return result; > > end function resolved_or; > > > > These custom functions may be defined within an architecture (before the BEGIN), or within a VHDL package. > > The resolved_or function you posted does not implement a wired or. The > type used is just std_ulogic and the assignment is > result := result or s(i); > > This is the or of all the bits in a bus. > Which, when used as a resolution function, makes the signal equal to the OR of all its drivers, i.e. a wired OR. Doesn't it? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:30:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 19:42:08 -0400 Organization: A noiseless patient Spider Lines: 74 Message-ID: References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 23:42:24 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="11750"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19DPSWd8I6FMC2846aR1P8U" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:SHbTwAuGj4nDPgCJkR+h3sx+INE= Xref: news.eternal-september.org comp.lang.vhdl:3227 On 7/31/2014 7:18 PM, Mark Curry wrote: > In article <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com>, > Daniel Kho wrote: >> On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: >> >>> I'm not a VHDL person - can you detail more? How's the custom resolution >>> function written? I.e. How's it support the variable number of inputs to >>> the function? >>> >> >> Sorry for the multiple posting. Posted too quickly without reading >> your entire question. :| >> >> A resolution function accepts as argument, a vector (or array) of >> the signal you wish to have multiple drivers on. Say for example >> you have a signal (or output) net q as in my previous example, that >> you wish to have multiple sources driving it. q is of an unresolved >> type std_ulogic, but you can apply the resolution function >> "resolved_wor" to resolve q to a deterministic value from multiple >> sources driving it. >> q:out resolved_wor std_ulogic; >> >> To write a resolution function for q, you create one that accepts a >> vector of std_ulogic (we can use the predefined std_ulogic_vector), >> and this array contains all the multiple drivers that would be >> driving q. The resolution function can then be written to resolve the >> output based on any resolution logic you want. This can be a simple OR >> or AND, or can as complex as need be. The output (return >> value) of a resolution function must therefore be of a resolved type >> (such as std_logic). >> >> function resolved_wor(s:std_ulogic_vector) return std_logic is begin >> ... >> end function resolved_wor; >> > > Yeah - doesn't solve my problem. There's no "std_ulogic_vector" for the > input to the function. There's only *ONE* net. The one net with multiple > (resolved type) drivers on it. > > I don't see how this is "custom resolution function" is different > than any other function? (Again, I'm not VHDL person). > > What I'm trying to do (verilog speak, sorry): > cpu_reg cpu_reg1 ( `BUS_CONNECT, .data_o( reg1_val ) ); > > cpu_reg cpu_reg2 ( `BUS_CONNECT, .data_o( reg2_val ) ); > > cpu_reg cpu_reg3 ( `BUS_CONNECT, .data_o( reg3_val ) ); > .... > > The `BUS_CONNECT is simple a verilog macro (probably a structure (record?) > in VHDL) that hooks up the CPU bus interface. All the read data, is a > wor net. > > Theres only one "read_data" net (an output of this entity) on BUS_CONNECT. > (Think of it as 1 bit to make the testcase easier). "read_data" is 'wor' > resolved for the multiple drivers on it. > > Generics/etc will conditionally compile in/out many cpu_regs. So I don't > know how many drivers "read_data" has apriori. Nor could I easily define > the width of the "std_ulogic_vector" input to your function. I think I see where Daniel is coming from. Try reading this link. I guess the function resolved_wor gets applied to your multiple drivers when you declare the signal q:out resolved_wor std_ulogic; http://vhdl.renerta.com/mobile/source/vhd00058.htm So disregard my prior post..... :( -- Rick From newsfish@newsfish Thu Aug 1 00:30:42 2024 X-Received: by 10.42.82.79 with SMTP id c15mr1861202icl.7.1406851799967; Thu, 31 Jul 2014 17:09:59 -0700 (PDT) X-Received: by 10.50.138.69 with SMTP id qo5mr31243igb.7.1406851799799; Thu, 31 Jul 2014 17:09:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11664868igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11664865igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 17:09:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: Dio Gratia Injection-Date: Fri, 01 Aug 2014 00:09:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3228 On Friday, August 1, 2014 1:28:28 AM UTC+12, Sean Durkin wrote: > In case anyone's still interested: > > This gets even worse in Vivado. Not even driving a std_ulogic from two > different places causes an error or warning during synthesis... The best > you can do is to receive a critical warning, but only under certain > circumstances (as it turns out, it makes a difference if one of the > drivers drives a constant value or not, for whatever reason...). > > I've reported it to Xilinx, but as of now they don't believe me that > this is a problem: > > http://tinyurl.com/lkzgsgj > Your test case you provided to Xilinx demonstrates your issue admirably. There's actually support for Xilinx's position in the now withdrawn 1076.6-2004, Section 5, Verification methodology: "... The process of verifying synthesis results using simulation consists of applying equivalent inputs to both the original model and synthesized model and then comparing their outputs to ensure that they are equivalent. Equivalent in this context means that a synthesis tool shall produce a circuit that is equivalent at the input, output, and bidirectional ports of the model. ..." This issue here is that shall is directive. See 1.3 Terminology: "The word shall indicates mandatory requirements strictly to be followed in order to conform to the standard and from which no deviation is permitted (shall equals is required to)." And note that synthesis only deals with a subset of VHDL: See 1.1 Scope: " This standard defines a subset of very high-speed integrated circuit hardware description language (VHDL) that ensures portability of VHDL descriptions between register transfer level synthesis tools. Synthesis tools may be compliant and yet have features beyond those required by this standard. This standard defines how the semantics of VHDL shall be used, for example, to model level-sensitive and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be sup- ported for interoperability. Use of this standard should minimize the potential for functional simulation mismatches between models before they are synthesized and after they are synthesized." There is no requirement that a synthesis tool provide a valid synthesis output for an invalid model. See the title page: "... The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors." There are only two errors defined in 1076.6, 6.3 Three-state logic and busses and 7.1 Attributes. The one on three-state logic pivots on guarded assignment. And your test case is invalid, you can't have multiple drivers for unresolved types. And back to 5. Verification methodology: "... The input stimulus shall comply with the following criteria: a) Input data does not contain metalogical or high-impedance values. b) Input data may only contain 'H' and 'L' on inputs that are converted to '1' and '0', respectively." There's no requirement that any metavalue on internal_sig be evaluated for matching behavior in top. Resolution can be ignored. The underlying issue here is that your model is invalid and your asking Xilinx detect errors where they've never been required to and historically (prior to reconfigurable FPGAs) it would have been imprudent to synthesize and implement hardware based on an invalid model. The cost implications would have demanded you simulate first where the invalid model would be filtered out. When Daniel also mentions similar issues with a second synthesis vendor the message here is that you need an RTL synthesis standard, and that if resurrected 1076.6 might be updated to require further error detection. Until then you have no leverage. And any standard on synthesis would represent a consensus between vendors (the same ones you're collectively complaining about.) From newsfish@newsfish Thu Aug 1 00:30:43 2024 X-Received: by 10.42.188.84 with SMTP id cz20mr4056295icb.1.1406875020865; Thu, 31 Jul 2014 23:37:00 -0700 (PDT) X-Received: by 10.50.134.3 with SMTP id pg3mr72145igb.4.1406875020685; Thu, 31 Jul 2014 23:37:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11792489igc.0!news-out.google.com!px9ni585igc.0!nntp.google.com!h18no7383964igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 23:37:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5dd43b00-79f3-47ef-abea-82faeafeffa1@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: Daniel Kho Injection-Date: Fri, 01 Aug 2014 06:37:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3229 On Friday, 1 August 2014 08:09:58 UTC+8, Dio Gratia wrote: > The underlying issue here is that your model is invalid and your asking X= ilinx >=20 > detect errors where they've never been required to and historically (prio= r to >=20 > reconfigurable FPGAs) it would have been imprudent to synthesize and impl= ement >=20 > hardware based on an invalid model. The cost implications would have dema= nded >=20 > you simulate first where the invalid model would be filtered out. >=20 >=20 >=20 > When Daniel also mentions similar issues with a second synthesis vendor t= he >=20 > message here is that you need an RTL synthesis standard, and that if >=20 > resurrected 1076.6 might be updated to require further error detection. >=20 >=20 >=20 > Until then you have no leverage. And any standard on synthesis would repr= esent >=20 > a consensus between vendors (the same ones you're collectively complainin= g >=20 > about.) While 1076.6 may not have described about signal resolutions and driving va= lues, the main standard P1076-2008 specifies this very clearly: ------------------------------------------------------- Section 6.4.2.3 Signal declarations [scroll down to Pg. 69] ... A signal may have one or more sources. For a signal of a scalar type, each = source is either a driver (see 14.7.2) or an out, inout, buffer, or linkage= port of a component instance or of a block statement with which the signal= is associated. For a signal of a composite type, each composite source is = a collection of scalar sources, one for each scalar subelement of the signa= l. It is an error if, after the elaboration of a description, a signal has = multiple sources and it is not a resolved signal. It is also an error if, a= fter the elaboration of a description, a resolved signal has more sources t= han the number of elements in the index range of the type of the formal par= ameter of the resolution function associated with the resolved signal. ------------------------------------------------------- It specifically mentions "It is an error if, after the elaboration of a des= cription, a signal has multiple sources and it is not a resolved signal." Therefore, as per my understanding of the LRM, we actually do have some lev= erage when trying to press vendors to actually comply to the standard. We s= hould (and could) tell them that their tools are not compliant to the stand= ard until they get this fixed. IMHO, wrong code stays wrong, and it would b= e wrong for vendors to not give any errors, or worse, optimise away the inc= orrect design. -- Daniel | www.tauhop.com ~eats, drinks, sleeps, and breathes VHDL From newsfish@newsfish Thu Aug 1 00:30:43 2024 X-Received: by 10.43.153.196 with SMTP id lb4mr4529407icc.2.1406877880874; Fri, 01 Aug 2014 00:24:40 -0700 (PDT) X-Received: by 10.50.61.145 with SMTP id p17mr76502igr.16.1406877880764; Fri, 01 Aug 2014 00:24:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11808710igc.0!news-out.google.com!px9ni585igc.0!nntp.google.com!h18no7394636igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 1 Aug 2014 00:24:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Fri, 01 Aug 2014 07:24:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3230 On Friday, 1 August 2014 07:18:47 UTC+8, Mark Curry wrote: > Yeah - doesn't solve my problem. There's no "std_ulogic_vector" for the >=20 > input to the function. There's only *ONE* net. The one net with multip= le=20 >=20 > (resolved type) drivers on it. >=20 Yes, the 'q' in my previous example is also a single net, with multiple dri= vers driving it. > What I'm trying to do (verilog speak, sorry): >=20 > cpu_reg cpu_reg1 ( `BUS_CONNECT, .data_o( reg1_val ) ); > cpu_reg cpu_reg2 ( `BUS_CONNECT, .data_o( reg2_val ) ); > cpu_reg cpu_reg3 ( `BUS_CONNECT, .data_o( reg3_val ) ); >=20 > ... >=20 > The `BUS_CONNECT is simple a verilog macro (probably a structure (record?= ) > in VHDL) that hooks up the CPU bus interface. All the read data, is a= =20 > wor net.=20 >=20 Don't really understand this Verilog code, sorry. Is that within an @always= block? So are those transactions? > Generics/etc will conditionally compile in/out many cpu_regs. So I don't= =20 > know how many drivers "read_data" has apriori. Nor could I easily define > the width of the "std_ulogic_vector" input to your function. As long as you leave the vector width unconstrained in your resolution func= tion, you don't need to specify how many drivers there are. Upon elaboratio= n of your design, the resolution function takes in the vector of all multip= le drivers - it finds all the multiple driving nets, and groups them into a= n array automatically. The size of the array is automatically calculated up= on elaboration. It's all done behind the scenes for you. -dan From newsfish@newsfish Thu Aug 1 00:30:43 2024 X-Received: by 10.42.207.146 with SMTP id fy18mr6982810icb.12.1406904917430; Fri, 01 Aug 2014 07:55:17 -0700 (PDT) X-Received: by 10.182.4.1 with SMTP id g1mr32084obg.3.1406904917276; Fri, 01 Aug 2014 07:55:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-01.inet.qwest.net!news.glorb.com!h18no7546043igc.0!news-out.google.com!px9ni585igc.0!nntp.google.com!h18no7546011igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 1 Aug 2014 07:55:16 -0700 (PDT) In-Reply-To: <45ab2df7-ca44-4c9f-a219-18818d92d074@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> <45ab2df7-ca44-4c9f-a219-18818d92d074@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8de054de-16f1-4a41-b28b-3e2cd0c4fab0@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Andy Injection-Date: Fri, 01 Aug 2014 14:55:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3231 IINM, Kho's solution will not compile. When "others" is used in an index expression, any accompanying indices/ranges must be locally static. This is because the value of "others" must be staticly determinable during compilation (unit analysis), before elaboration or exeution. Andy From newsfish@newsfish Thu Aug 1 00:30:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 1 Aug 2014 17:47:30 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 46 Message-ID: References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> Injection-Date: Fri, 1 Aug 2014 17:47:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="9275"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/5sdEacbONe8sNZKjZYfFf" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:TDTwon6VeqRL/10BdfQA/EMCxEs= Xref: news.eternal-september.org comp.lang.vhdl:3232 In article <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com>, Daniel Kho wrote: >On Friday, 1 August 2014 07:18:47 UTC+8, Mark Curry wrote: >> Yeah - doesn't solve my problem. There's no "std_ulogic_vector" for the >> >> input to the function. There's only *ONE* net. The one net with multiple >> >> (resolved type) drivers on it. >> > >Yes, the 'q' in my previous example is also a single net, with multiple >drivers driving it. > > >> What I'm trying to do (verilog speak, sorry): >> >> cpu_reg cpu_reg1 ( `BUS_CONNECT, .data_o( reg1_val ) ); >> cpu_reg cpu_reg2 ( `BUS_CONNECT, .data_o( reg2_val ) ); >> cpu_reg cpu_reg3 ( `BUS_CONNECT, .data_o( reg3_val ) ); >> >> ... >> >> The `BUS_CONNECT is simple a verilog macro (probably a structure (record?) >> in VHDL) that hooks up the CPU bus interface. All the read data, is a >> wor net. >> > >Don't really understand this Verilog code, sorry. Is that within an >@always block? So are those transactions? Sorry, should have been more clear. Those are all just instaciations. The "multiple driver" read_data is all within `BUS_CONNNECT. To expand it (leaving some connections out to synplify): wor rddata_o; cpu_reg cpu_reg1 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); cpu_reg cpu_reg2 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); cpu_reg cpu_reg3 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); rddata_o has multiple drivers. I want them resolved like a verilog 'wor', but in VHDL. I'm having trouble figuring out how to tie the VHDL "resolution function" "resolved_wor" to the single net "rddata_o". "rddata_o" is both the input, and output of the function... How do I hook it up? --Mark From newsfish@newsfish Thu Aug 1 00:30:43 2024 X-Received: by 10.43.85.201 with SMTP id ap9mr12000671icc.11.1406954710894; Fri, 01 Aug 2014 21:45:10 -0700 (PDT) X-Received: by 10.50.29.13 with SMTP id f13mr238719igh.15.1406954710755; Fri, 01 Aug 2014 21:45:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no12349478igc.0!news-out.google.com!px9ni585igc.0!nntp.google.com!h18no7750143igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 1 Aug 2014 21:45:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f3c515b-99a7-41dc-9261-111534779be7@googlegroups.com> Subject: Re: Wired Or in VHDL From: Dio Gratia Injection-Date: Sat, 02 Aug 2014 04:45:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3233 On Saturday, August 2, 2014 5:47:30 AM UTC+12, Mark Curry wrote: > rddata_o has multiple drivers. I want them resolved like a verilog 'wor'= , but=20 > in VHDL. I'm having trouble figuring out how to tie the VHDL "resolution= function" "resolved_wor"=20 > to the single net "rddata_o". "rddata_o" is both the input, and output o= f the function... > How do I hook it up? You specify a resolution function to use in a subtype indication declaring = signals. The simulator provides an array type of the base type of the sign= al having a value for every driver on the net and calls the function inter= nally. A resolution function has one argument, an array vector and returns a resul= t that is of the same base type. This is from package std_logic_1164 for std_logic: type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC; ------------------------------------------------------------------- =20 -- resolution function ------------------------------------------------------------------- =20 constant resolution_table : stdlogic_table :=3D ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | =20 -- --------------------------------------------------------- ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | ('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 | ('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 | ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z | ('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W | ('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L | ('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - | ); function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is variable result : STD_ULOGIC :=3D 'Z'; -- weakest state default begin -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. if (s'length =3D 1) then return s(s'low); else for i in s'range loop result :=3D resolution_table(result, s(i)); end loop; end if; return result; end function resolved; Additionally if you were to look at the truth table for wor and trior in th= e 1064 (Verilog) standard you'd find that wor works identically to using th= e std_ulogic subtype X01Z (which is also resolved, using the same resolutio= n function shown above). Further package std_logic_1164 provides To_X01Z conversion functions that c= an be used to pre-filter std_logic and std_logic_vector values to X01Z valu= es. They are conversion functions (1 input, a return value from a pure fun= ction) and functions are expressions ( can be used for example in port map = associations) and the result is base type compatible with std_logic. If you only ever assign 'X', '0', '1' or 'Z' to a standard logic value And= you provide a default value that is one of those four values you don't nee= d to do anything to get the same effect as using wor in Verilog. =20 The To_X01Z functions can be used to filter MVL9 signal values ('U','X','0'= , '1', 'Z', 'W', 'L','H', '-') to 'X', '0', '1', 'Z' when assignment is out= of your control. VHDL's std_logic_1164 package already provides the functionality you're aft= er. From newsfish@newsfish Thu Aug 1 00:30:44 2024 X-Received: by 10.42.235.132 with SMTP id kg4mr13716068icb.22.1406968835831; Sat, 02 Aug 2014 01:40:35 -0700 (PDT) X-Received: by 10.50.4.6 with SMTP id g6mr264075igg.4.1406968835711; Sat, 02 Aug 2014 01:40:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no12426060igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no12426057igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 2 Aug 2014 01:40:35 -0700 (PDT) In-Reply-To: <8de054de-16f1-4a41-b28b-3e2cd0c4fab0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.113; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.113 References: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> <45ab2df7-ca44-4c9f-a219-18818d92d074@googlegroups.com> <8de054de-16f1-4a41-b28b-3e2cd0c4fab0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <809f5d70-0c39-4704-8066-a2c1244d688a@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Daniel Kho Injection-Date: Sat, 02 Aug 2014 08:40:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3234 On Friday, 1 August 2014 22:55:16 UTC+8, Andy wrote: > IINM, Kho's solution will not compile. When "others" is used in an index expression, any accompanying indices/ranges must be locally static. > > > > This is because the value of "others" must be staticly determinable during compilation (unit analysis), before elaboration or exeution. > > > > Andy Yes, like what Rick has said as well. If mask_ctrl were a register, my example won't work. However, if it was a constant (as I originally assumed), my example would compile. Anyway, it's still unclear what mask_ctrl is for. If mask_ctrl were some register, then I believe 'mask' can be changed accordingly depending upon what the value of mask_ctrl is. This will probably be where the bulk of the logic is. Perhaps the OP needs something like this (assuming mask_ctrl is a register): architecture rtl of masker is signal mask:std_ulogic_vector(data'range); signal i:natural range data'range; begin /* Use a clocked process to set mask values. This saves you timing problems later (if you were to use a purely combinatorial process, e.g. a for-loop). */ process(reset,clk) is begin if reset then i<=0; ready<=false; mask<=(others=>'0'); elsif rising_edge(clk) then if i Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.113; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.113 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> <6f3c515b-99a7-41dc-9261-111534779be7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Sat, 02 Aug 2014 09:21:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3235 On Saturday, 2 August 2014 12:45:10 UTC+8, Dio Gratia wrote: > Additionally if you were to look at the truth table for wor and trior in the 1064 (Verilog) standard you'd find that wor works identically to using the std_ulogic subtype X01Z (which is also resolved, using the same resolution function shown above). > Sorry, does the Verilog wor resolve '0' and '1' to an 'X'? Or will it be resolved to a '1'? -dan From newsfish@newsfish Thu Aug 1 00:30:44 2024 X-Received: by 10.42.38.15 with SMTP id a15mr9978018ice.30.1407019671630; Sat, 02 Aug 2014 15:47:51 -0700 (PDT) X-Received: by 10.50.134.3 with SMTP id pg3mr338165igb.4.1407019671543; Sat, 02 Aug 2014 15:47:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no12792318igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no12792309igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 2 Aug 2014 15:47:50 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> <6f3c515b-99a7-41dc-9261-111534779be7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8d2e7da7-f731-4499-a61a-7d724b8f43ba@googlegroups.com> Subject: Re: Wired Or in VHDL From: Dio Gratia Injection-Date: Sat, 02 Aug 2014 22:47:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3236 On Saturday, August 2, 2014 9:21:37 PM UTC+12, Daniel Kho wrote: > Sorry, does the Verilog wor resolve '0' and '1' to an 'X'? Or will it be resolved to a '1'? Opps! Wrong table, Dan is right. My bad. 4-4 from 1364-2005: wor/trior 0 1 x z 0 0 1 x 0 1 1 1 1 1 x x 1 x x z 0 1 x z std_logic matches 4-2, wire/tri. Which says yes a different resolution function for wor, and begs the question of who can synthesize logic from single rail transfer gate models in VHDL. A demo case for penance: library ieee; use ieee.std_logic_1164.all; package wor_stuff is type wortrior is ('X', '0', '1', 'Z'); type wortrior_vector is array (natural range <>) of wortrior; function wor_trior (s: wortrior_vector) return wortrior; subtype wor is wor_trior wortrior; type wor_vector is array (natural range <>) of wor; function wor_image(inp: wor_vector) return string; end package; package body wor_stuff is type wor_table is array (wortrior, wortrior) of wortrior; constant resolution_table : wor_table := ( -- -------------------------------- -- | X 0 1 Z | | -- -------------------------------- ('X', 'X', '1', 'X'), -- | X | ('X', '0', '1', '0'), -- | 0 | ('1', '1', '1', '1'), -- | 1 | ('X', '0', '1', 'Z') -- | Z | ); function wor_trior ( s: wortrior_vector ) return wortrior is variable result: wortrior := 'Z'; begin if (s'length = 1) then return (s(s'low)); else for i in s'range loop result := resolution_table(result, s(i)); end loop; end if; return result; end wor_trior; function wor_image(inp: wor_vector) return string is variable image_str: string (1 to inp'length); alias input_str: wor_vector (1 to inp'length) is inp; begin for i in input_str'range loop image_str(i) := character'VALUE(wortrior'IMAGE(input_str(i))); end loop; return image_str; end; end package body; library ieee; use ieee.std_logic_1164.all; use work.wor_stuff.all; entity cpu_reg_dummy is generic ( value: wor_vector(3 downto 0) := (others => 'Z') ); port ( rddata_o: out wor_vector(3 downto 0) ); end entity; architecture foo of cpu_reg_dummy is begin rddata_o <= value after 0.5 ns; end architecture; library ieee; use ieee.std_logic_1164.all; use work.wor_stuff.all; entity foo is end entity; architecture fum of foo is component cpu_reg_dummy generic ( value: wor_vector(3 downto 0) := (others => 'Z') ); port ( rddata_o: out wor_vector(3 downto 0) ); end component; signal rddata_o: wor_vector (3 downto 0); begin CPU_REG1: cpu_reg_dummy generic map (value => "0000") port map (rddata_o => rddata_o); CPU_REG2: cpu_reg_dummy generic map (value => "1001") port map (rddata_o => rddata_o); CPU_REG3: cpu_reg_dummy generic map (value => "ZZZZ") port map (rddata_o => rddata_o); CPU_REG4: cpu_reg_dummy generic map (value => "ZZZX") port map (rddata_o => rddata_o); WHAT: process begin wait for 0.6 ns; report "rddata_o = " & wor_image(rddata_o); wait; end process; end architecture; Which analyzes, elaborates and simulates the test case foowith the following assertion output: ** Note: 600ps+0: Report Note: rddata_o = 1001 Process :foo:what File wor.vhdl, Line 113 (and yes the resolution function wor_trior is shamelessly derived from package std_logic_1164's resolution function). From newsfish@newsfish Thu Aug 1 00:30:45 2024 X-Received: by 10.42.62.73 with SMTP id x9mr26259020ich.15.1407078468848; Sun, 03 Aug 2014 08:07:48 -0700 (PDT) X-Received: by 10.50.41.103 with SMTP id e7mr426433igl.8.1407078468758; Sun, 03 Aug 2014 08:07:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no13198488igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no13198479igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 3 Aug 2014 08:07:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.12; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.12 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Sun, 03 Aug 2014 15:07:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3237 On Saturday, 2 August 2014 01:47:30 UTC+8, Mark Curry wrote: > Sorry, should have been more clear. Those are all just instaciations. > > The "multiple driver" read_data is all within `BUS_CONNNECT. > > To expand it (leaving some connections out to synplify): > > > > wor rddata_o; > > cpu_reg cpu_reg1 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); > > cpu_reg cpu_reg2 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); > > cpu_reg cpu_reg3 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); > > > > rddata_o has multiple drivers. I want them resolved like a verilog 'wor', but > > in VHDL. I'm having trouble figuring out how to tie the VHDL "resolution function" "resolved_wor" > > to the single net "rddata_o". "rddata_o" is both the input, and output of the function... > > How do I hook it up? > > > > --Mark architecture rtl of test is signal rddata_o:resolved_wor std_ulogic; /* declare the other internal non-resolved signals here (addr_i, cs_i, wrdata_i, rwn_i). */ begin cpu_reg1: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); cpu_reg2: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); cpu_reg3: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); end architecture rtl; Here all the 3 entity instances (cpu_reg1, cpu_reg2, cpu_reg3) will be driving the single resolved wire "rddata_o". The resolved_wor resolution function will be used to resolve the multiple drivers. Of course, you can have more instances driving the net, without needing to specify the array width (or the number of drivers) into the resolution function, provided your function does not constrain the input argument's width. To write the resolution function 'resolved_wor', you can use the examples Dio or I provided earlier. Just place it within a VHDL package, and remember to add a library-use clause to 'import' this package into your design. -dan From newsfish@newsfish Thu Aug 1 00:30:45 2024 X-Received: by 10.42.212.207 with SMTP id gt15mr17688395icb.31.1407126799966; Sun, 03 Aug 2014 21:33:19 -0700 (PDT) X-Received: by 10.50.4.6 with SMTP id g6mr491715igg.4.1407126799839; Sun, 03 Aug 2014 21:33:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no13517454igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no13517453igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 3 Aug 2014 21:33:19 -0700 (PDT) In-Reply-To: <8d2e7da7-f731-4499-a61a-7d724b8f43ba@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> <6f3c515b-99a7-41dc-9261-111534779be7@googlegroups.com> <8d2e7da7-f731-4499-a61a-7d724b8f43ba@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: Dio Gratia Injection-Date: Mon, 04 Aug 2014 04:33:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3238 VHDL2008 also has this neat feature the Jim and Peter call Resolved Element= s in 3.2 of their book VHDL2008 Just the New Stuff. If you were to look th= rough previous versions of the standard you'd find it's new, although parts= those standards imply you can do it while otherwise explicitly not allowin= g it. The idea is that you can specify the resolution function to use on elements= of a composite types subtype declaration. Previously if I provided a resolution indication on a composite type: signal rddata_o: rddata_o_resolv std_logic_vector (rddata_o_range); The resolution function would have to be of the signal's type in this case = std_logic_vector (and it can be, because a composite type resolution functi= on will replace any element resolution). =20 So they've added a feature to the language to allow you to specify element = resolution: signal rddata_o: (wor_trior) std_logic_vector (rddata_o_range); And this works for records two, where you'd specify multiple resolution fun= ction names inside the parentheses. Resolution is subtype bound and every declaration of a signal is a subtype = declaration. So, historically why this is important can be demonstrated by writing a VHD= L design specification compatible with a previous edition of the spec. This is the previous demonstration re-written to specify a resolution funct= ion for a std_logic_vector array subtype: library ieee; use ieee.std_logic_1164.all; package wor_std is subtype rddata_o_range is integer range 3 downto 0; type rddata_o_array is array (natural range <>) of std_logic_vector(rdd= ata_o_range); =20 function rddata_o_resolv (s: rddata_o_array) return std_logic_vector; = =20 =20 function wor_trior (s: std_logic_vector) return std_logic; function slv_image(inp: std_logic_vector) return string; end package; package body wor_std is =20 type wor_table is array (X01Z, X01Z) of std_ulogic; constant resolution_table : wor_table :=3D ( -- -------------------------------- -- | X 0 1 Z | | =20 -- -------------------------------- ('X', 'X', '1', 'X'), -- | X | ('X', '0', '1', '0'), -- | 0 | ('1', '1', '1', '1'), -- | 1 | ('X', '0', '1', 'Z') -- | Z | ); =20 function wor_trior ( s: std_logic_vector ) return std_logic is variable result: std_logic :=3D 'Z';=20 begin if (s'length =3D 1) then return (To_X01Z(s(s'low))); else for i in s'range loop result :=3D resolution_table(result, To_X01Z(s(i))); end loop; end if; return result; end wor_trior; =20 function rddata_o_resolv (s: rddata_o_array) return std_logic_vector is variable wor: std_logic_vector (s'range); variable result: std_logic_vector (rddata_o_range); begin for i in result'range loop for j in s'range loop wor(j) :=3D s(j)(i); end loop; report "wor =3D " & slv_image(wor); result(i) :=3D wor_trior(wor); end loop; return result; end function; =20 function slv_image(inp: std_logic_vector) return string is variable image_str: string (1 to inp'length); alias input_str: std_logic_vector (1 to inp'length) is inp; begin for i in input_str'range loop image_str(i) :=3D character'VALUE(std_ulogic'IMAGE(input_str(i)= )); end loop; return image_str; end; =20 end package body; library ieee; use ieee.std_logic_1164.all; use work.wor_std.all; entity cpu_reg_dummy is generic ( value: std_logic_vector(3 downto 0) :=3D (others =3D> 'Z') ); port ( rddata_o: out std_logic_vector(3 downto 0) ); end entity; architecture foo of cpu_reg_dummy is=20 =20 begin rddata_o <=3D value after 0.5 ns; end architecture; library ieee; use ieee.std_logic_1164.all; use work.wor_std.all; entity foe is end entity; architecture fum of foe is =20 component cpu_reg_dummy generic ( value: std_logic_vector(rddata_o_range) :=3D (others =3D> = 'Z') ); port ( rddata_o: out std_logic_vector(rddata_o_range) ); end component; =20 signal rddata_o: rddata_o_resolv std_logic_vector (rddata_o_range); -- signal rddata_o: (wor_trior) std_logic_vector (rddata_o_range); -- = -2008 =20 begin =20 CPU_REG1: cpu_reg_dummy generic map (value =3D> "0000") port map (rddata_o =3D> rddata_o); CPU_REG2: cpu_reg_dummy generic map (value =3D> "1001") port map (rddata_o =3D> rddata_o); CPU_REG3: cpu_reg_dummy generic map (value =3D> "ZZZZ") port map (rddata_o =3D> rddata_o); =20 CPU_REG4: cpu_reg_dummy generic map (value =3D> "ZZZX") port map (rddata_o =3D> rddata_o); =20 WHAT: process begin wait for 0.6 ns; report "rddata_o =3D " & slv_image(rddata_o); wait; end process; end architecture; The really harsh part of using a tool complying to an earlier standard is f= or the resolution function rddata_o_resolv we can't specify an array type w= ith a unconstrained element type, which means for the demo the index range = of rddata_o has been fixed where everything can see it in the package wor_s= td. =20 This gives you an idea what a simulator does, assembling arrays of each ele= ment and resolving those.=20 wor_std.vhdl:50:13:@500ps:(report note): wor =3D 01zz wor_std.vhdl:50:13:@500ps:(report note): wor =3D 00zz wor_std.vhdl:50:13:@500ps:(report note): wor =3D 00zz wor_std.vhdl:50:13:@500ps:(report note): wor =3D 01zx wor_std.vhdl:126:9:@600ps:(report note): rddata_o =3D 1001 And the line 50 reports are in the resolution function and taking those val= ues vertically we see values written out by the cpu_reg_dummy instantiation= s. Take horizontally the wor_trior resolution of those tells us what each of t= he index values for rdata_o is going to be. You can also note that those logical operators for std_ulogic related types= use table look up to speed things up. From newsfish@newsfish Thu Aug 1 00:30:45 2024 X-Received: by 10.66.66.3 with SMTP id b3mr3499864pat.6.1407167781459; Mon, 04 Aug 2014 08:56:21 -0700 (PDT) X-Received: by 10.140.105.200 with SMTP id c66mr312031qgf.4.1407167781410; Mon, 04 Aug 2014 08:56:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no8702978igc.0!news-out.google.com!b3ni5434qac.1!nntp.google.com!v10no4325991qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 08:56:21 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Help for function calling From: fl Injection-Date: Mon, 04 Aug 2014 15:56:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3239 Hi, I want to program a CRC project originating from a past discussion: function crc_shift -- Mike Treseler -- parallel data version (constant X_load : in unsigned; constant D_vec : in unsigned ; constant Poly : in unsigned := x"3223") --Poly_16_12_5) return unsigned is variable X_out : unsigned(X_load'range); begin X_out := X_load; for I in D_vec'range loop -- call serial version for each bit X_out := crc_shift(X_out, D_vec(I), Poly); end loop; return X_out; end function crc_shift; end package body crc_package; library IEEE; use IEEE.std_logic_1164.all; use WORK.crc_package.all; entity tb is end tb; architecture structural of bit8_adder is signal internal_carry : std_logic; signal sum1: std_logic_vector(15 downto 0); begin sum1 <= crc_shift(x"3322", x"1111", x"3223"); end; The code has an error when compiling: ** Error: C:\Users\Jeff\crc_ccitt.vhd(100): No feasible entries for subprogram "crc_shift". I am new to VHDL, especially to function. Could you help me on what is wrong with my code? Thanks. From newsfish@newsfish Thu Aug 1 00:30:46 2024 X-Received: by 10.68.209.130 with SMTP id mm2mr9397088pbc.3.1407169167925; Mon, 04 Aug 2014 09:19:27 -0700 (PDT) X-Received: by 10.140.36.198 with SMTP id p64mr39065qgp.10.1407169167877; Mon, 04 Aug 2014 09:19:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no13830407igc.0!news-out.google.com!b3ni5434qac.1!nntp.google.com!v10no4329910qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 09:19:27 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> Subject: Re: Help for function calling From: fl Injection-Date: Mon, 04 Aug 2014 16:19:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 5308 X-Received-Body-CRC: 1127044844 Xref: news.eternal-september.org comp.lang.vhdl:3240 On Monday, August 4, 2014 11:56:21 AM UTC-4, fl wrote: > Hi, > I guess that there are two overloading crc_shift function in previous post causing error. Then I explicitly define two crc_shift(0) function inside the package. It has a new error: ** Error: C:\Users\Jeff\crc_ccitt.vhd(15): (vcom-1115) Subtype indication found where type mark is required. Could anybody help me on what is wrong? Thanks, library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package crc_package is function crc_shift -- Mike Treseler -- parallel data version (constant X_load : in unsigned (15 downto 0); constant D_vec : in unsigned (15 downto 0); constant Poly : in unsigned := x"3223") --Poly_16_12_5) return unsigned (15 downto 0); end package crc_package; package body crc_package is function crc_shift0 -- Mike Treseler -- serial data version, see overload for parallel data below -- Purpose : Single bit shift for a CRC register using any polynomial. -- Inputs : X_load : Current CRC vector. -- D_bit : Data to shift into CRC vector. -- Poly : CRC polynomial. Default is Frame Relay. -- -- Outputs : CRC vector after CRC shift. ( constant X_load : in unsigned; -- register start value constant D_bit : in std_ulogic := '0'; -- input bit constant Poly : in unsigned := x"3223" --Poly_16_12_5 -- poly bits ) return unsigned is variable X_out : unsigned(X_load'range); -- CRC register begin ---------------------------------------------------------------------- -- we assume that X and Poly are in downto format -- to match the textbook definition of LSFR -- and to match the CCITT FCS bit assigments -- for frame relay, note that X(15) becomes the lsb of octet n-2 -- and that X(7 ) becomes the lsb of octet n-1 ---------------------------------------------------------------------- -- Procedure: Left shift a '0' into the current X0 -- and the previous X(14) into the current X15 etc. -- if the original X15 is '1' or the data is '1' -- but not both, then invert the poly bit locations ---------------------------------------------------------------------- -- Sample Invocation: -- crc_shift( "0001000100010001", '1')); -- SLL 0010001000100010 -- shift the variable -- D (not X15) [ ! ! !] -- invert poly locations? -- expect("shift1 0011001000000011"); -- expected result ---------------------------------------------------------------------- assert X_load'length = Poly'length report "crc_shift: Vectors X_load and Poly must be of equal length." severity error; X_out := X_load sll 1; if (X_load(X_load'left) xor D_bit) = '1' then X_out := X_out xor Poly; end if; return unsigned(X_out); -- returns each shift end function crc_shift0; ----------------------------------------------- function crc_shift -- Mike Treseler -- parallel data version (constant X_load : in unsigned (15 downto 0); constant D_vec : in unsigned (15 downto 0); constant Poly : in unsigned := x"3223") --Poly_16_12_5) return unsigned is variable X_out : unsigned(X_load'range); begin X_out := X_load; for I in D_vec'range loop -- call serial version for each bit X_out := crc_shift0(X_out, D_vec(I), Poly); end loop; return X_out; end function crc_shift; end package body crc_package; library IEEE; use IEEE.std_logic_1164.all; use WORK.crc_package.all; entity tb is end tb; architecture structural of tb is signal internal_carry : std_logic; signal sum1: unsigned (15 downto 0); begin sum1 <= crc_shift(x"3322", x"1111", x"3223"); end; From newsfish@newsfish Thu Aug 1 00:30:46 2024 X-Received: by 10.68.222.194 with SMTP id qo2mr10001030pbc.6.1407182082475; Mon, 04 Aug 2014 12:54:42 -0700 (PDT) X-Received: by 10.140.27.102 with SMTP id 93mr41713qgw.23.1407182082403; Mon, 04 Aug 2014 12:54:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h18no13956234igc.0!news-out.google.com!b3ni5434qac.1!nntp.google.com!v10no4373984qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 12:54:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <79e0ac75-a108-424c-b982-41bd68ad1082@googlegroups.com> Subject: How to understand the different CRC formats? From: fl Injection-Date: Mon, 04 Aug 2014 19:54:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3241 Hi, I read a post on this forum about CRC: https://groups.google.com/forum/#!searchin/comp.lang.vhdl/crc/comp.lang.vhdl/GL1irJS6WrA/FiBxmFXal24J I can run this routine through simulation. In the same time, my Matlab can generate the same results with CCITT (x^16+x^12+x^5+1). The initial generator states are all '0'. When the message bits are 0x80000, the checksum is 0x1B98. When I check website: http://www.lammertbies.nl/comm/info/crc-calculation.html There are several kinds of CCITT, such as xModem, 0xFFFF etc. I have tried different kinds of initial states, byte order etc., but no one can generate the same results of the simulation program and Matlab result. Could you tell me what format can result in the differences? Second, the original code is very good. I know some FPGA vendors sell CRC IP. I would like to know what advantage of their design comparing to the Mike Treseler's code? Thanks, From newsfish@newsfish Thu Aug 1 00:30:46 2024 X-Received: by 10.182.125.37 with SMTP id mn5mr10651719obb.49.1407183883615; Mon, 04 Aug 2014 13:24:43 -0700 (PDT) X-Received: by 10.140.23.163 with SMTP id 32mr65170qgp.8.1407183883548; Mon, 04 Aug 2014 13:24:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h18no8813963igc.0!news-out.google.com!b3ni5177qac.1!nntp.google.com!j15no4447193qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 13:24:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help for function calling From: KJ Injection-Date: Mon, 04 Aug 2014 20:24:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3242 On Monday, August 4, 2014 11:56:21 AM UTC-4, fl wrote: > I am new to VHDL, especially to function. Could you help me on what is wrong > with my code? You declared sum1 as a std_logic_vector, not an unsigned. The crc_shift function returns unsigned. Change this... signal sum1: std_logic_vector(15 downto 0); To this... signal sum1: unsigned(15 downto 0); Kevin Jennings From newsfish@newsfish Thu Aug 1 00:30:46 2024 X-Received: by 10.236.26.206 with SMTP id c54mr527014yha.44.1407207890007; Mon, 04 Aug 2014 20:04:50 -0700 (PDT) X-Received: by 10.50.67.98 with SMTP id m2mr671465igt.15.1407207889730; Mon, 04 Aug 2014 20:04:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j15no4508381qaq.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no14144011igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 20:04:49 -0700 (PDT) In-Reply-To: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <59711d1d-e1f2-4cdc-917e-d1a7f339226a@googlegroups.com> Subject: Re: Help for function calling From: Dio Gratia Injection-Date: Tue, 05 Aug 2014 03:04:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3243 On Tuesday, August 5, 2014 4:19:27 AM UTC+12, fl wrote: > On Monday, August 4, 2014 11:56:21 AM UTC-4, fl wrote: > > > Hi, > > > I guess that there are two overloading crc_shift function in previous post > causing error. Then I explicitly define two crc_shift(0) function inside the > package. It has a new error: > > > ** Error: C:\Users\Jeff\crc_ccitt.vhd(15): > (vcom-1115) Subtype indication found where type mark is required. > You could consider posting code with line numbers. I believe this is line 15: return unsigned (15 downto 0); And a different error message may help: ghdl -a crc_shft.vhdl crc_shft.vhdl:47:25: index constraint not allowed here ghdl: compilation error subprogram_specification ::= procedure designator [ ( formal_parameter_list ) ] | [ pure | impure ] function designator [ ( formal_parameter_list ) ] return type_mark type_mark ::= type_name | subtype_name Notice the lack of subtype indication associated with the return type_mark. It should be: return unsigned ; -- (15 downto 0); It also doesn't match the function's subprogram specification in the package body. There are other problems with entity tb. You're missing a use statement for package ieee.numeric_std.all for the type declaration unsigned. After which your code analyzes, elaborates and runs. With a little added monitoring: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.crc_package.all; entity tb is end tb; architecture structural of tb is signal internal_carry : std_logic; signal sum1: unsigned (15 downto 0); function unsigned_image(inp: unsigned) return string is variable image_str: string (1 to inp'length); alias input_str: unsigned (1 to inp'length) is inp; begin for i in input_str'range loop image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i))); end loop; return image_str; end; begin sum1 <= crc_shift(x"3322", x"1111", x"3223"); MONITOR: process begin wait for 1 ns; report "sum1 = " & unsigned_image(sum1); wait; end process; end architecture; gives: crc_shft.vhdl:114:9:@1ns:(report note): sum1 = 1011100111100000 Which is x"B9E0" From newsfish@newsfish Thu Aug 1 00:30:47 2024 X-Received: by 10.68.209.130 with SMTP id mm2mr2314772pbc.3.1407252372344; Tue, 05 Aug 2014 08:26:12 -0700 (PDT) X-Received: by 10.50.41.103 with SMTP id e7mr771582igl.8.1407252372098; Tue, 05 Aug 2014 08:26:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no14460598igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no14460593igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Aug 2014 08:26:11 -0700 (PDT) In-Reply-To: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.148.96; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.148.96 References: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help for function calling From: Daniel Kho Injection-Date: Tue, 05 Aug 2014 15:26:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3244 On Tuesday, 5 August 2014 00:19:27 UTC+8, fl wrote: > package crc_package is=20 > function crc_shift > -- Mike Treseler > -- parallel data version > (constant X_load : in unsigned (15 downto 0); > constant D_vec : in unsigned (15 downto 0); > constant Poly : in unsigned :=3D x"3223") --Poly_16_12_5) > return unsigned (15 downto 0); > end package crc_package;=20 >=20 > package body crc_package is=20 > function crc_shift0=20 ... Just adding to what others have said. You need to declare the function crc_= shift0 at the package declarative area as well, since you have that functio= n in the package body and intend to use it. package crc_package is function crc_shift(...) return unsigned; function crc_shift0(...) return unsigned; end package crc_package; Make sure the subprogram "signature" is the same for both the declarative r= egion and the body. E.g. if you declared your subprogram to return an 'unsi= gned(15 downto 0)', then to be consistent, you should use the same return t= ype in your subprogram specification (the one in the package body). -dan From newsfish@newsfish Thu Aug 1 00:30:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Tue, 5 Aug 2014 17:01:19 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 70 Message-ID: References: <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> Injection-Date: Tue, 5 Aug 2014 17:01:19 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="22846"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+hFnhCJ9+5ni49IJjdjciZ" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:iHXOH2YyGUJNkDyGmBLlGxmjPWU= Xref: news.eternal-september.org comp.lang.vhdl:3245 In article , Daniel Kho wrote: >On Saturday, 2 August 2014 01:47:30 UTC+8, Mark Curry wrote: >> Sorry, should have been more clear. Those are all just instaciations. >> >> The "multiple driver" read_data is all within `BUS_CONNNECT. >> >> To expand it (leaving some connections out to synplify): >> >> >> >> wor rddata_o; >> >> cpu_reg cpu_reg1 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); >> >> cpu_reg cpu_reg2 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); >> >> cpu_reg cpu_reg3 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); >> >> >> >> rddata_o has multiple drivers. I want them resolved like a verilog 'wor', but >> >> in VHDL. I'm having trouble figuring out how to tie the VHDL "resolution function" "resolved_wor" >> >> to the single net "rddata_o". "rddata_o" is both the input, and output of the function... >> >> How do I hook it up? >> >> >> >> --Mark > > >architecture rtl of test is > signal rddata_o:resolved_wor std_ulogic; > > /* declare the other internal non-resolved signals here (addr_i, > cs_i, wrdata_i, rwn_i). > */ > >begin > cpu_reg1: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); > > cpu_reg2: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); > > cpu_reg3: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); > >end architecture rtl; > >Here all the 3 entity instances (cpu_reg1, cpu_reg2, cpu_reg3) will be driving the single resolved wire "rddata_o". The resolved_wor resolution function will be used to resolve the multiple drivers. > >Of course, you can have more instances driving the net, without needing to specify the array width (or the number of drivers) into the resolution function, provided your function does not constrain >the input argument's width. > >To write the resolution function 'resolved_wor', you can use the examples Dio or I provided earlier. Just place it within a VHDL package, and remember to add a library-use clause to 'import' this >package into your design. Dan, and all. Thanks for the detailied example (and having the patience to beat its use thru my thick skull). That is indeed a useful tool in the language. I'm going to play around with this when I get some time, and see what the tool support is like. Thanks, Mark From newsfish@newsfish Thu Aug 1 00:30:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: How to understand the different CRC formats? Date: Tue, 5 Aug 2014 18:53:05 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 51 Message-ID: References: <79e0ac75-a108-424c-b982-41bd68ad1082@googlegroups.com> Injection-Date: Tue, 5 Aug 2014 18:53:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="10668"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19rwWFVB+0lAXsR9hbYgtYv" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:HmziE1AscXkIXA6PoTHsSma39aU= Xref: news.eternal-september.org comp.lang.vhdl:3246 In article <79e0ac75-a108-424c-b982-41bd68ad1082@googlegroups.com>, fl wrote: >Hi, > >I read a post on this forum about CRC: >https://groups.google.com/forum/#!searchin/comp.lang.vhdl/crc/comp.lang.vhdl/GL1irJS6WrA/FiBxmFXal24J > >I can run this routine through simulation. In the same time, my Matlab can generate the same results with CCITT (x^16+x^12+x^5+1). The initial generator >states are all '0'. When the message bits are 0x80000, the checksum is 0x1B98. > >When I check website: > >http://www.lammertbies.nl/comm/info/crc-calculation.html > >There are several kinds of CCITT, such as xModem, 0xFFFF etc. I have tried >different kinds of initial states, byte order etc., but no one can generate >the same results of the simulation program and Matlab result. Could you tell me >what format can result in the differences? > > > >Second, the original code is very good. I know some FPGA vendors sell CRC IP. >I would like to know what advantage of their design comparing to the Mike >Treseler's code? Not specifically answering your questions but... My favorite paper on CRCs is here: http://www.ross.net/crc/download/crc_v3.txt It's old (1993) - but entire valid today. It describes, pretty much every way you can do a CRC. Ross describes CRCs in general, with examples. Then lists a way of fully specifying any CRC. Many standard examples (like CCITT) are included. Take an hour or so and read this paper. If you're looking at this from a hardware angle (which I think you are, as you're asking this question in a VHDL newsgroup), then you can STOP READING after section 8. Past this part of the paper Ross begins to describe how CRC's are efficiently done in SW. YOU DON'T NEED TO KNOW this first time. CRC's in HW are really simple. Don't let the SW "Table-Driven Implementations" cloud your head right now. Just focus on the first part of the paper. Regards, Mark From newsfish@newsfish Thu Aug 1 00:30:48 2024 X-Received: by 10.182.34.130 with SMTP id z2mr3408726obi.3.1407272498543; Tue, 05 Aug 2014 14:01:38 -0700 (PDT) X-Received: by 10.140.32.227 with SMTP id h90mr50097qgh.26.1407272498518; Tue, 05 Aug 2014 14:01:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no9249580igc.0!news-out.google.com!b3ni5434qac.1!nntp.google.com!v10no4612788qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Aug 2014 14:01:38 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> Subject: How to model an internal state in a function (or a procedure)? From: fl Injection-Date: Tue, 05 Aug 2014 21:01:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3247 Hi, After I get helps from several on-line groups, I can calculate a CRC with a VHDL project. The problem now is that I can get the 16-bit checksum in one time calculation. Some real FPGA implementations use 8-bit. Thus, I guess that it needs two clocks to get a 16-bit CRC checksum. My code originates from a function call, which is a combination logic (no register), from on-line post. When I modify it to get 8-bit one time for a 16-bit CRC checksum, I find that I have to store the internal states for the next iterative CRC calculation (Is this right?) The function call seems not work in this way (It only output the result, not the internal states). The CRC problem is just like an integer division. I have to store the residue and the new divisor (dividend is polynomial, constant in this case). It looks like the residue must have attribute of 'in' and 'out'. In both function and procedure, parameters can be set to 'in', 'out' or 'inout'. I am new to VHDL function/procedure. They do not look like easy. Could you express your idea to help me? Thanks, From newsfish@newsfish Thu Aug 1 00:30:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to model an internal state in a function (or a procedure)? Date: Tue, 05 Aug 2014 17:26:19 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Aug 2014 21:26:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="19574"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/vK64IzZfBr11Qwjoxoy0i" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> Cancel-Lock: sha1:1M9KC3kvyAQcQWoBzmh39lgS7HM= Xref: news.eternal-september.org comp.lang.vhdl:3248 On 8/5/2014 5:01 PM, fl wrote: > Hi, > > After I get helps from several on-line groups, I can calculate a CRC with a VHDL > project. The problem now is that I can get the 16-bit checksum in one time > calculation. Some real FPGA implementations use 8-bit. Thus, I guess that it needs > two clocks to get a 16-bit CRC checksum. My code originates from a function call, > which is a combination logic (no register), from on-line post. When I modify it to > get 8-bit one time for a 16-bit CRC checksum, I find that I have to store the > internal states for the next iterative CRC calculation (Is this right?) > The function call seems not work in this way (It only output the result, not the > internal states). The CRC problem is just like an integer division. I have to > store the residue and the new divisor (dividend is polynomial, constant in this > case). It looks like the residue must have attribute of 'in' and 'out'. In both > function and procedure, parameters can be set to 'in', 'out' or 'inout'. > > I am new to VHDL function/procedure. They do not look like easy. Could you express > your idea to help me? Thanks, Are you new to HDL in general? HDL means Hardware Description Language. There are no small number of designers who use HDL as a language and don't bother considering what hardware will be produced which can work perfectly well. In this case I think looking at what hardware you wish to produce will do you wonders. A CRC is not a complex function. It is just a register and a few exclusive or gates (XOR). The only trick is knowing what to connect to what with the XOR gates. Your function can be written to describe the XOR gates and be purely combinatorial. Then you can connect it to your inputs and a register and Bob's your uncle! Try starting with a very simple CRC that you have example data for testing. It will be much easier to see what is happening. -- Rick From newsfish@newsfish Thu Aug 1 00:30:48 2024 X-Received: by 10.50.103.66 with SMTP id fu2mr1838056igb.7.1407284665451; Tue, 05 Aug 2014 17:24:25 -0700 (PDT) X-Received: by 10.50.66.135 with SMTP id f7mr224941igt.3.1407284665366; Tue, 05 Aug 2014 17:24:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no9297839igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no14729262igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Aug 2014 17:24:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help for function calling From: Dio Gratia Injection-Date: Wed, 06 Aug 2014 00:24:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3249 On Wednesday, August 6, 2014 3:26:11 AM UTC+12, Daniel Kho wrote: > Just adding to what others have said. You need to declare the function > crc_shift0 at the package declarative area as well, since you have that function > in the package body and intend to use it. Err, no, not necessarily. A declaration in a package declaration makes the function visible through a use statement. (i.e. use work.package.all;) while the function is directly visible in the package body by through the function's subprogram body. The effect of not having the function declared in the package declaration is to make it private (only visible) to the package body. You can find examples for both locally visible functions and declarations in package std_logic_1164's body. IEEE Std 1076-2008, 4.3 Subprogram bodies, para 8: "The declaration of a subprogram is optional. In the absence of such a declaration, the subprogram specification of the subprogram body acts as the declaration. For each subprogram declaration, there shall be a corresponding body. If both a declaration and a body are given, the subprogram specification of the body shall lexically conform (see 4.10) to the subprogram specification of the declaration. Furthermore, both the declaration and the body shall occur immediately within the same declarative region (see 12.1)." Which also tells us a function declaration within the package body has to match the function body. 4.7 Package declarations, para 1: "A package declaration defines the interface to a package. The scope of a declaration within a package can be extended to other design units or to other parts of the design unit containing the package declaration." 12.4 Use clauses, para 1 - 3: "A use clause achieves direct visibility of declarations that are visible by selection. use_clause ::= use selected_name { , selected_name } ; Each selected name in a use clause identifies one or more declarations that will potentially become directly visible. If the suffix of the selected name is a simple name other than a type mark, or is a character literal or operator symbol, then the selected name identifies only the declaration(s) of that simple name, character literal, or operator symbol contained within the package or library denoted by the prefix of the selected name." 12.4 para 3: "If the suffix is the reserved word all, then the selected name identifies all declarations that are contained within the package or library denoted by the prefix of the selected name." (Which tells us that .all at the end of a use clause makes all the declarations in a package visible.) 12.3 Visibility, para 2, excerpted: "For each identifier and at each place in the text, the visibility rules determine a set of declarations (with this identifier) that define the possible meanings of an occurrence of the identifier. A declaration is said to be visible at a given place in the text when, according to the visibility rules, the declaration defines a possible meaning of this occurrence. ..." In this specific case crc_shift0 isn't visible outside crc_package, and the case presented by fi only shows it called from function crc_shift inside the crc_package body where it is visible. It only has to be declared in the crc_package declaration if it is required to be visible externally. > Make sure the subprogram "signature" is the same for both the declarative region > and the body. E.g. if you declared your subprogram to return an 'unsigned(15 > downto 0)', then to be consistent, you should use the same return type in your > subprogram specification (the one in the package body). And a return type declaration in a function declaration may not contain a subtype indication, the previously quoted EBNF in another comment is normative. Both of these and require extensive reading of the standard (and is the more difficult in the -2008 version of the standard) or can be demonstrated by simple experimentation. Those of us who don't trust tools to be right do both. The VHDL language standard is large enough those of us trying to make authoritative statements tend to keep it to hand. It's too big to keep in your head (short term memory is the first to go), which is why over time tool error messages improve. (And if I hadn't checked yesterday before a previous comment I might not have raised the issues, I too saw there was no declaration in the package and checked why. I had a tool complain about a subtype indication on the function return, but also noted fi had corrected it when presenting the entire package.) From newsfish@newsfish Thu Aug 1 00:30:48 2024 X-Received: by 10.66.66.196 with SMTP id h4mr6326010pat.22.1407346084150; Wed, 06 Aug 2014 10:28:04 -0700 (PDT) X-Received: by 10.140.19.213 with SMTP id 79mr225463qgh.5.1407346084057; Wed, 06 Aug 2014 10:28:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no9564679igc.0!news-out.google.com!b3ni5177qac.1!nntp.google.com!j15no5051844qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 6 Aug 2014 10:28:03 -0700 (PDT) In-Reply-To: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d552a7c-d128-46ab-beb5-a61053b3eedb@googlegroups.com> Subject: Re: How to model an internal state in a function (or a procedure)? From: Andy Injection-Date: Wed, 06 Aug 2014 17:28:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3250 I use a procedure with an inout variable parameter for the CRC value, and an in parameter for the data to be CRC'd (bit, byte, word, block, etc.) Just initialize the crc variable once, and then call the procecure with (data, crc) each time you get new data, and it will update the crc variable each time. Because it can be written to accept an entire block of data (unconstrained array of bytes), such a procedure can be very useful in testbenches too. Andy From newsfish@newsfish Thu Aug 1 00:30:49 2024 X-Received: by 10.224.169.20 with SMTP id w20mr8659673qay.4.1407402152625; Thu, 07 Aug 2014 02:02:32 -0700 (PDT) X-Received: by 10.50.134.3 with SMTP id pg3mr220211igb.4.1407402152409; Thu, 07 Aug 2014 02:02:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j15no5250987qaq.0!news-out.google.com!eg1ni559igc.0!nntp.google.com!h18no15482919igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 Aug 2014 02:02:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.108; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.108 References: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8ba6d987-c0dc-482e-ad6d-a9b95290a9b6@googlegroups.com> Subject: Re: Help for function calling From: Daniel Kho Injection-Date: Thu, 07 Aug 2014 09:02:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2984 X-Received-Body-CRC: 658536411 Xref: news.eternal-september.org comp.lang.vhdl:3251 On Wednesday, 6 August 2014 08:24:24 UTC+8, Dio Gratia wrote: > On Wednesday, August 6, 2014 3:26:11 AM UTC+12, Daniel Kho wrote: >=20 >=20 >=20 > > Just adding to what others have said. You need to declare the function >=20 > > crc_shift0 at the package declarative area as well, since you have that= function >=20 > > in the package body and intend to use it. >=20 >=20 >=20 > Err, no, not necessarily. A declaration in a package declaration makes th= e >=20 > function visible through a use statement. (i.e. use work.package.all;) wh= ile the >=20 > function is directly visible in the package body by through the function'= s >=20 > subprogram body. The effect of not having the function declared in the pa= ckage >=20 > declaration is to make it private (only visible) to the package body. You= can find >=20 > examples for both locally visible functions and declarations in package >=20 > std_logic_1164's body. Yes, I agree. However, I was not speaking strictly from the LRM - instead I= was speaking based on the OP's intention. From what I guess, the OP intend= s to use the subprogram outside of the package body (i.e. probably use it i= n a real design, whose entity-architecture is probably in another file). Defining a subprogram within the package body but not in the package declar= ative part will not give you any errors (IINM), but that makes the subprogr= am private to the package body (as what you've mentioned) and you can't use= the subprogram outside of the package. I think the intent of the OP is eventually to be able to use the subprogram= outside of the package body. -dan From newsfish@newsfish Thu Aug 1 00:30:49 2024 X-Received: by 10.236.125.33 with SMTP id y21mr7885471yhh.20.1407584567466; Sat, 09 Aug 2014 04:42:47 -0700 (PDT) X-Received: by 10.50.97.74 with SMTP id dy10mr238180igb.1.1407584567329; Sat, 09 Aug 2014 04:42:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!j15no5737236qaq.0!news-out.google.com!px9ni588igc.0!nntp.google.com!h18no16810525igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Aug 2014 04:42:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=27.116.16.2; posting-account=8oA8ZwoAAAC66CVHtm8hS6fyjFuhccs0 NNTP-Posting-Host: 27.116.16.2 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <508fbfc8-9bc6-4a95-ad91-2ed290c02ac2@googlegroups.com> Subject: isc books From: vaasuisc@gmail.com Injection-Date: Sat, 09 Aug 2014 11:42:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: news.eternal-september.org comp.lang.vhdl:3252 Are you looking for best isc books, then central books online is a best online book store where you can find all types of text books and competitive books. http://www.centralbooksonline.com/categories/School-Books-ISC/cid-CU00113788.aspx From newsfish@newsfish Thu Aug 1 00:30:49 2024 X-Received: by 10.66.66.46 with SMTP id c14mr3053682pat.21.1407865021622; Tue, 12 Aug 2014 10:37:01 -0700 (PDT) X-Received: by 10.140.36.66 with SMTP id o60mr28032qgo.28.1407865021515; Tue, 12 Aug 2014 10:37:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no12181193igc.0!news-out.google.com!j6ni43193qas.0!nntp.google.com!v10no6524370qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Aug 2014 10:37:01 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.35.35.35 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Combinatorial logic causing delta impulse From: "V." Injection-Date: Tue, 12 Aug 2014 17:37:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3253 I have sig1 and sig2 that are both driven by a synchronous process. I have a line of combinatorial logic that simply checks that both are high: out <= sig1 and sig2. In my ModelSim simulation, at the moment of the falling edge of sig1 and rising edge of sig2, I see the "out" signal pulse high just for only one delta delay cycle. I assume there's a moment in time while sig1 is falling and sig2 is rising that the simulator thinks they are both high? I am not sure if this only exists in simulation environment or will it propagate to my real world implementation? How can I prevent it in simulation? Thanks for your guidance. Regards, V. From newsfish@newsfish Thu Aug 1 00:30:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Combinatorial logic causing delta impulse Date: Tue, 12 Aug 2014 17:53:30 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 34 Message-ID: References: Injection-Date: Tue, 12 Aug 2014 17:53:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="7935"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+EUUTwYinmlq1h8zMrA6lW" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:G8m1xg56QUT9VFwegYT3/91GGoU= Xref: news.eternal-september.org comp.lang.vhdl:3254 In article , V. wrote: >I have sig1 and sig2 that are both driven by a synchronous process. > >I have a line of combinatorial logic that simply checks that both are high: > >out <= sig1 and sig2. > >In my ModelSim simulation, at the moment of the falling edge of sig1 and >rising edge of sig2, I see the "out" signal pulse high just for only one >delta delay cycle. > >I assume there's a moment in time while sig1 is falling and sig2 is rising >that the simulator thinks they are both high? > >I am not sure if this only exists in simulation environment or will it >propagate to my real world implementation? How can I prevent it in simulation? Think it through more V, as it'll happen in the real world. The signals "sig1" and "sig2" are never going to have exactly matched delays. So of course in the real world perhaps "sig1" rises just a few moments before "sig2" falls. What do you get? - a glitch. Do you care? Not if you've followed proper synchronous design principles. You registers up the "out" signal one period later after everything's settled. As to the sim - again, do you care? It's a reprsentative model of what could happen in the real circuit. It's ok, no need to "prevent it in simulation". Regards, Mark From newsfish@newsfish Thu Aug 1 00:30:50 2024 X-Received: by 10.42.188.84 with SMTP id cz20mr900337icb.1.1407881550572; Tue, 12 Aug 2014 15:12:30 -0700 (PDT) X-Received: by 10.51.18.100 with SMTP id gl4mr49013igd.6.1407881550443; Tue, 12 Aug 2014 15:12:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no19143979igc.0!news-out.google.com!px9ni620igc.0!nntp.google.com!h18no12303560igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Aug 2014 15:12:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <016d4ba9-e0cc-4201-896f-76f9ea5d12d9@googlegroups.com> Subject: Re: Combinatorial logic causing delta impulse From: Dio Gratia Injection-Date: Tue, 12 Aug 2014 22:12:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3410 X-Received-Body-CRC: 1291961352 Xref: news.eternal-september.org comp.lang.vhdl:3255 On Wednesday, August 13, 2014 5:37:01 AM UTC+12, V. wrote: > > How can I prevent it in simulation? >=20 As Mark notes it can occur in the real world. However if you never use a v= ulnerable combinatorial product as a latch enable or clock it has no meanin= g other than difference in propagation times of the inputs in delta cycles = to the expression and you can prevent it simulation. That difference in p= ropagation time can match differences in gate delays, travel times or risin= g/falling edge times in actual hardware. You could also note that in a zero timed model it tells you one of your syn= chronous processes is either using a delta delayed clock or already has a c= ombinatorial expression on a sequential storage element's output. To prevent a delta cycle impulse from propagating look to signal assignment= : signal_assignment_statement ::=3D [ label : ] target <=3D [ delay_mechanism ] waveform ; delay_mechanism ::=3D transport | [ reject time_expression ] inertial target ::=3D name | aggregate waveform ::=3D waveform_element { , waveform_element } | unaffected Where you'd use inertial impulse rejection with a time expression set to th= e smallest unit of the resolution limit selected primary or secondary time = unit (without setting the resolution limit that would be 1 fs, the default = resolution limit set to femto-second). The idea here is to prevent an impu= lse rejection interval of 0 which happens to match a delta cycle delay. Such a signal assignment should have the delay mechanism ignored by synthes= is. A rule of thumb should be to never rely on inertial rejection to insure pro= per operation of a model. =20 I recall issues we had in the late '70s and early '80s with silicon being t= oo fast, sub nanosecond gate delays in 74LSXX MSI from Japanese vendors and= AMD having DRAM with almost zero holdover on Data Out from CAS invalid. M= ixing things with different propagation delays can result in unforeseen com= plications.=20 The same sort of effects can occur on silicon devices, and the same synchro= nous design rules are used as cures. From newsfish@newsfish Thu Aug 1 00:30:50 2024 X-Received: by 10.182.60.36 with SMTP id e4mr27180350obr.3.1408547089854; Wed, 20 Aug 2014 08:04:49 -0700 (PDT) X-Received: by 10.140.98.243 with SMTP id o106mr17334qge.17.1408547089784; Wed, 20 Aug 2014 08:04:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!r2no3552010igi.0!news-out.google.com!q8ni661qal.1!nntp.google.com!m5no1395486qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Aug 2014 08:04:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <33ec8e85-78e5-4a05-9326-47012f4f94a0@googlegroups.com> Subject: VHDL 2008 - how to declare 2nd dimension for array where 1st dimension is already constrained? From: Tricky Injection-Date: Wed, 20 Aug 2014 15:04:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3256 so I have this type definition: type slv_array4_t is array(0 to 3) of std_logic_vector; but when I try this: signal some_thing : slv_array4_t(7 downto 0); I get this error from VCOM: ERROR: In array constraint at depth 1 the array slv_array4_t has already been constrained. I get the same error when I try signal some_thing : slv_array4_t(0 to 3)(7 downto 0); It has no problem compiling the type delcaration. So whats the correct syntax for this? or should both dimension be unconstrained (and vcom should flag it?) From newsfish@newsfish Thu Aug 1 00:30:50 2024 X-Received: by 10.52.174.178 with SMTP id bt18mr9443982vdc.1.1408548651691; Wed, 20 Aug 2014 08:30:51 -0700 (PDT) X-Received: by 10.140.21.175 with SMTP id 44mr35609qgl.14.1408548651656; Wed, 20 Aug 2014 08:30:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i13no1402351qae.1!news-out.google.com!j6ni3084qas.0!nntp.google.com!i13no1402350qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Aug 2014 08:30:51 -0700 (PDT) In-Reply-To: <33ec8e85-78e5-4a05-9326-47012f4f94a0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <33ec8e85-78e5-4a05-9326-47012f4f94a0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 - how to declare 2nd dimension for array where 1st dimension is already constrained? From: Tricky Injection-Date: Wed, 20 Aug 2014 15:30:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3257 On Wednesday, 20 August 2014 16:04:49 UTC+1, Tricky wrote: > so I have this type definition: > > > > type slv_array4_t is array(0 to 3) of std_logic_vector; > > > > but when I try this: > > > > signal some_thing : slv_array4_t(7 downto 0); > > > > I get this error from VCOM: > > > > ERROR: In array constraint at depth 1 the array slv_array4_t has already been constrained. > > > > I get the same error when I try > > > > signal some_thing : slv_array4_t(0 to 3)(7 downto 0); > > > > It has no problem compiling the type delcaration. > > > > So whats the correct syntax for this? or should both dimension be unconstrained (and vcom should flag it?) Sorry to bother you all - some light reading (2008 LRM) showed me it should be: signal some_thing : slv_array4_t(open)(7 downto 0); From newsfish@newsfish Thu Aug 1 00:30:51 2024 X-Received: by 10.236.126.103 with SMTP id a67mr7557216yhi.4.1408800718596; Sat, 23 Aug 2014 06:31:58 -0700 (PDT) X-Received: by 10.50.85.7 with SMTP id d7mr109056igz.9.1408800718456; Sat, 23 Aug 2014 06:31:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no2203006qae.1!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no5576841igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Aug 2014 06:31:58 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.129.65.105; posting-account=gZGhxwoAAACah1cEfYemoWcb8yVumWC_ NNTP-Posting-Host: 150.129.65.105 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Undefined Symbol error 3312 and 1209 From: Gaurav Agarwal Injection-Date: Sat, 23 Aug 2014 13:31:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1660 X-Received-Body-CRC: 2376887552 Xref: news.eternal-september.org comp.lang.vhdl:3258 Please help me out with this code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity comple2 is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : out STD_LOGIC_VECTOR (3 downto 0)); end comple2; architecture Behavioral of comple2 is signal D : out STD_LOGIC_VECTOR (3 downto 0); begin D <= (not a); b <= D + "0001"; end Behavioral; i am getting this error ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'. ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block) From newsfish@newsfish Thu Aug 1 00:30:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 Date: Sat, 23 Aug 2014 12:24:18 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 23 Aug 2014 16:24:23 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="20995"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+2TsQEo1HAU5gnLoMHzohq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:EAmcnzrVH+/Zeh40LjxOvbxeNCY= Xref: news.eternal-september.org comp.lang.vhdl:3259 On 8/23/2014 9:31 AM, Gaurav Agarwal wrote: > Please help me out with this code > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > library UNISIM; > use UNISIM.VComponents.all; > > entity comple2 is > Port ( a : in STD_LOGIC_VECTOR (3 downto 0); > b : out STD_LOGIC_VECTOR (3 downto 0)); > end comple2; > > architecture Behavioral of comple2 is > signal D : out STD_LOGIC_VECTOR (3 downto 0); > > begin > > D <= (not a); > b <= D + "0001"; > > end Behavioral; > > > i am getting this error > ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'. > ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block) > Your signal declaration should not include the keyword "out". -- Rick From newsfish@newsfish Thu Aug 1 00:30:51 2024 X-Received: by 10.52.174.178 with SMTP id bt18mr7774817vdc.1.1408812476429; Sat, 23 Aug 2014 09:47:56 -0700 (PDT) X-Received: by 10.50.114.69 with SMTP id je5mr126151igb.1.1408812476326; Sat, 23 Aug 2014 09:47:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m5no2248829qaj.0!news-out.google.com!ef6ni1igb.0!nntp.google.com!uq10no3976915igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Aug 2014 09:47:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.129.65.105; posting-account=gZGhxwoAAACah1cEfYemoWcb8yVumWC_ NNTP-Posting-Host: 150.129.65.105 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45d893a5-5c7f-45da-94bb-62ee1b964bec@googlegroups.com> Subject: Re: Undefined Symbol error 3312 and 1209 From: Gaurav Agarwal Injection-Date: Sat, 23 Aug 2014 16:47:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2244 X-Received-Body-CRC: 2451801752 Xref: news.eternal-september.org comp.lang.vhdl:3260 On Saturday, 23 August 2014 19:01:58 UTC+5:30, Gaurav Agarwal wrote: > Please help me out with this code > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.NUMERIC_STD.ALL; > > library UNISIM; > > use UNISIM.VComponents.all; > > > > entity comple2 is > > Port ( a : in STD_LOGIC_VECTOR (3 downto 0); > > b : out STD_LOGIC_VECTOR (3 downto 0)); > > end comple2; > > > > architecture Behavioral of comple2 is > > signal D : out STD_LOGIC_VECTOR (3 downto 0); > > > > begin > > > > D <= (not a); > > b <= D + "0001"; > > > > end Behavioral; > > > > > > i am getting this error > > ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'. > > ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block) if i remove out keyword then its showing an error ERROR:HDLParsers:808 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. + can not have such operands in this context. line 43 is the operation on port b From newsfish@newsfish Thu Aug 1 00:30:52 2024 X-Received: by 10.182.246.70 with SMTP id xu6mr8145072obc.31.1408817966474; Sat, 23 Aug 2014 11:19:26 -0700 (PDT) X-Received: by 10.50.57.71 with SMTP id g7mr131589igq.13.1408817966380; Sat, 23 Aug 2014 11:19:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no4018166igb.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no5741111igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Aug 2014 11:19:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.129.65.105; posting-account=gZGhxwoAAACah1cEfYemoWcb8yVumWC_ NNTP-Posting-Host: 150.129.65.105 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Undefined Symbol error 3312 and 1209 From: Gaurav Agarwal Injection-Date: Sat, 23 Aug 2014 18:19:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3261 On Saturday, 23 August 2014 19:01:58 UTC+5:30, Gaurav Agarwal wrote: > Please help me out with this code > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.NUMERIC_STD.ALL; > > library UNISIM; > > use UNISIM.VComponents.all; > > > > entity comple2 is > > Port ( a : in STD_LOGIC_VECTOR (3 downto 0); > > b : out STD_LOGIC_VECTOR (3 downto 0)); > > end comple2; > > > > architecture Behavioral of comple2 is > > signal D : out STD_LOGIC_VECTOR (3 downto 0); > > > > begin > > > > D <= (not a); > > b <= D + "0001"; > > > > end Behavioral; > > > > > > i am getting this error > > ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'. > > ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block) lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked! From newsfish@newsfish Thu Aug 1 00:30:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!fdn.fr!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed3-a.proxad.net!nnrp4-1.free.fr!not-for-mail Date: Sat, 23 Aug 2014 23:27:52 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 11 Message-ID: <53f90758$0$2007$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 23 Aug 2014 23:27:52 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1408829272 news-1.free.fr 2007 88.185.146.198:2427 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3262 Le 23/08/2014 20:19, Gaurav Agarwal a crit : > lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked! Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. Learn how to use the numeric_std package instead. Declare your ports and signal as unsigned instead of std_logic_vector, you will even be able to write "b <= d + 1;" Nicolas From newsfish@newsfish Thu Aug 1 00:30:52 2024 X-Received: by 10.182.28.102 with SMTP id a6mr9371273obh.44.1408840057963; Sat, 23 Aug 2014 17:27:37 -0700 (PDT) X-Received: by 10.140.105.52 with SMTP id b49mr260653qgf.3.1408840057864; Sat, 23 Aug 2014 17:27:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!r2no5921908igi.0!news-out.google.com!j6ni7969qas.0!nntp.google.com!i13no2345261qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Aug 2014 17:27:37 -0700 (PDT) In-Reply-To: <53f90758$0$2007$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <53f90758$0$2007$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Undefined Symbol error 3312 and 1209 From: Andy Injection-Date: Sun, 24 Aug 2014 00:27:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3263 On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote: > Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned. Then you can perform unsigned arithmetic on SLVs (with SLV or naturals), using an OFFICIAL package, rather than the synopsys-developed non-standard packages. Andy From newsfish@newsfish Thu Aug 1 00:30:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed4-a.proxad.net!nnrp1-2.free.fr!not-for-mail Date: Mon, 25 Aug 2014 00:33:12 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 References: <53f90758$0$2007$426a74cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 12 Message-ID: <53fa6828$0$2066$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Aug 2014 00:33:12 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1408919592 news-3.free.fr 2066 88.185.146.198:2482 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3264 Le 24/08/2014 02:27, Andy a crit : > On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote: >> Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. > > Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned. Then you can perform unsigned arithmetic on SLVs (with SLV or naturals), using an OFFICIAL package, rather than the synopsys-developed non-standard packages. Oh no no no no no no (shakes head) Well, technically yes you could but as a fierce advocate of strong typing, I can not support this heresy ;o) Nicolas From newsfish@newsfish Thu Aug 1 00:30:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 Date: Sun, 24 Aug 2014 18:59:51 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <53f90758$0$2007$426a74cc@news.free.fr> <53fa6828$0$2066$426a74cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Sun, 24 Aug 2014 22:59:57 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="11656"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+SFnOBZwEqs+sCk9/rnQhp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <53fa6828$0$2066$426a74cc@news.free.fr> Cancel-Lock: sha1:9T/MsTxmyxVIlzbBTrf8FdEtkJk= Xref: news.eternal-september.org comp.lang.vhdl:3265 On 8/24/2014 6:33 PM, Nicolas Matringe wrote: > Le 24/08/2014 02:27, Andy a crit : >> On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote: >>> Terrible mistake. Thou shalt not use the std_logic_* arithmetic >>> packages. >> >> Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned. >> Then you can perform unsigned arithmetic on SLVs (with SLV or >> naturals), using an OFFICIAL package, rather than the >> synopsys-developed non-standard packages. > > Oh no no no no no no (shakes head) > Well, technically yes you could but as a fierce advocate of strong > typing, I can not support this heresy ;o) Is there some advantage to such strong typing? I think the active word in "strong typing" is "typing". There is far too much of it in VHDL. I'm happy with a few very clear, well defined *short* cuts. Actually these short cuts don't have anything to do with strong typing. The library simply defines an operator which uses the appropriate types on its inputs and output. What's wrong with that? -- Rick From newsfish@newsfish Thu Aug 1 00:30:53 2024 X-Received: by 10.66.122.101 with SMTP id lr5mr14614898pab.19.1408982076204; Mon, 25 Aug 2014 08:54:36 -0700 (PDT) X-Received: by 10.50.29.13 with SMTP id f13mr380957igh.15.1408982076101; Mon, 25 Aug 2014 08:54:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no4870071igb.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no7010298igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 25 Aug 2014 08:54:35 -0700 (PDT) In-Reply-To: <53f90758$0$2007$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.129.65.105; posting-account=gZGhxwoAAACah1cEfYemoWcb8yVumWC_ NNTP-Posting-Host: 150.129.65.105 References: <53f90758$0$2007$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> Subject: Re: Undefined Symbol error 3312 and 1209 From: Gaurav Agarwal Injection-Date: Mon, 25 Aug 2014 15:54:36 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3266 On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote: > Le 23/08/2014 20:19, Gaurav Agarwal a =EF=BF=BDcrit : >=20 >=20 >=20 > > lol! i removed the keyword out and then used the package STD_LOGIC_UNSI= GNED.ALL and it worked! >=20 >=20 >=20 > Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. >=20 > Learn how to use the numeric_std package instead. Declare your ports and= =20 >=20 > signal as unsigned instead of std_logic_vector, you will even be able to= =20 >=20 > write "b <=3D d + 1;" >=20 >=20 >=20 > Nicolas can you please give the exact code using the numeric_std package? From newsfish@newsfish Thu Aug 1 00:30:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!dedibox.gegeweb.org!gegeweb.eu!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp5-1.free.fr!not-for-mail Date: Mon, 25 Aug 2014 21:40:48 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 References: <53f90758$0$2007$426a74cc@news.free.fr> <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> In-Reply-To: <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 37 Message-ID: <53fb9140$0$2224$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Aug 2014 21:40:48 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1408995648 news-3.free.fr 2224 88.185.146.198:4379 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3267 Le 25/08/2014 17:54, Gaurav Agarwal a écrit : > On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote: >> Le 23/08/2014 20:19, Gaurav Agarwal a �crit : >>> lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked! >> >> Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. >> Learn how to use the numeric_std package instead. Declare your ports and >> signal as unsigned instead of std_logic_vector, you will even be able to >> write "b <= d + 1;" > can you please give the exact code using the numeric_std package? I can library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity comple2 is Port ( a : in unsigned (3 downto 0); b : out unsigned (3 downto 0)); end comple2; architecture Behavioral of comple2 is signal D : out unsigned (3 downto 0); begin D <= (not a); b <= D + 1; end Behavioral; Just as I said, use unsigned instead of std_logic_vector. There's no need to use the intermediate signal D, you can do it all in a single expression, BTW. Nicolas From newsfish@newsfish Thu Aug 1 00:30:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 Date: Mon, 25 Aug 2014 16:42:09 -0400 Organization: A noiseless patient Spider Lines: 46 Message-ID: References: <53f90758$0$2007$426a74cc@news.free.fr> <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> <53fb9140$0$2224$426a74cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 25 Aug 2014 20:42:15 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="29248"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18gpQNOrhRcaskYxF/rQskb" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <53fb9140$0$2224$426a74cc@news.free.fr> Cancel-Lock: sha1:iYKfmE65w8XoEmd63PxuzQGwFEo= Xref: news.eternal-september.org comp.lang.vhdl:3268 On 8/25/2014 3:40 PM, Nicolas Matringe wrote: > Le 25/08/2014 17:54, Gaurav Agarwal a écrit : >> On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote: >>> Le 23/08/2014 20:19, Gaurav Agarwal a �crit : >>>> lol! i removed the keyword out and then used the package >>>> STD_LOGIC_UNSIGNED.ALL and it worked! >>> >>> Terrible mistake. Thou shalt not use the std_logic_* arithmetic >>> packages. >>> Learn how to use the numeric_std package instead. Declare your ports and >>> signal as unsigned instead of std_logic_vector, you will even be able to >>> write "b <= d + 1;" >> can you please give the exact code using the numeric_std package? > > I can > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > library UNISIM; > use UNISIM.VComponents.all; > > entity comple2 is > Port ( a : in unsigned (3 downto 0); > b : out unsigned (3 downto 0)); > end comple2; > > architecture Behavioral of comple2 is > signal D : out unsigned (3 downto 0); > begin > D <= (not a); > b <= D + 1; > end Behavioral; > > Just as I said, use unsigned instead of std_logic_vector. > > There's no need to use the intermediate signal D, you can do it all in a > single expression, BTW. > > Nicolas You used "out" in your signal declaration for D. Was that intentional? -- Rick From newsfish@newsfish Thu Aug 1 00:30:55 2024 X-Received: by 10.42.188.84 with SMTP id cz20mr20661589icb.1.1409053255974; Tue, 26 Aug 2014 04:40:55 -0700 (PDT) X-Received: by 10.182.131.166 with SMTP id on6mr10097obb.24.1409053255845; Tue, 26 Aug 2014 04:40:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no5245789igb.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no7599374igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Aug 2014 04:40:55 -0700 (PDT) In-Reply-To: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.21.194.1; posting-account=l6FnUwoAAAA4GdhVUFXsD7A1E1w5GF9Z NNTP-Posting-Host: 125.21.194.1 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d5d93f3-e32f-476b-a086-66abb97e5b12@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: JK Injection-Date: Tue, 26 Aug 2014 11:40:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3269 http://en.wikipedia.org/wiki/Linear_feedback_shift_register#Galois_LFSRs From newsfish@newsfish Thu Aug 1 00:30:55 2024 X-Received: by 10.66.119.174 with SMTP id kv14mr19002109pab.23.1409077367443; Tue, 26 Aug 2014 11:22:47 -0700 (PDT) X-Received: by 10.50.79.201 with SMTP id l9mr594112igx.5.1409077367297; Tue, 26 Aug 2014 11:22:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!uq10no5432791igb.0!news-out.google.com!ef6ni1igb.0!nntp.google.com!uq10no5432790igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Aug 2014 11:22:46 -0700 (PDT) In-Reply-To: <3d5d93f3-e32f-476b-a086-66abb97e5b12@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.148.186; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.148.186 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> <3d5d93f3-e32f-476b-a086-66abb97e5b12@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How can I design Galois field 2^m multiplier. From: Daniel Kho Injection-Date: Tue, 26 Aug 2014 18:22:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3270 There's a Galois LFSR project in OpenCores: http://www.opencores.org/project,galois_lfsr It's a simple design, which gives you the ability to "configure" the taps of the LFSR easily. The design will automatically generate the LFSR structure with all the XOR gates accordingly based on the taps you chose (see user.vhdl). E.g.: tapVector:boolean_vector:=( 0|1|2|8=>true, 7 downto 3=>false ) Disclosure: I'm the author of the project, so may have a bias towards it. From newsfish@newsfish Thu Aug 1 00:30:55 2024 X-Received: by 10.68.216.231 with SMTP id ot7mr21588648pbc.2.1409138755587; Wed, 27 Aug 2014 04:25:55 -0700 (PDT) X-Received: by 10.50.57.71 with SMTP id g7mr706164igq.13.1409138755430; Wed, 27 Aug 2014 04:25:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r2no8315107igi.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no8315101igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Aug 2014 04:25:54 -0700 (PDT) In-Reply-To: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <606f6d0f-1a3e-47a8-b6fa-99664bd8cc59@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: Dio Gratia Injection-Date: Wed, 27 Aug 2014 11:25:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3271 On Saturday, June 22, 2013 4:10:25 AM UTC+12, lkp wrote: > Any suggestion will be helpful. There's a gate level representation of a GF(2M) parallel Galois Field multipler in expired patent US 4,918,638, which you can find by googling. In theory a person having ordinary skill in the art is capable of implementing the claimed invention found in a patent. The gate level representation should make it fairly easy to translate into a behavioral representation in VHDL. It looks like it could synthesis pretty compactly as long as you kept it in one process. From newsfish@newsfish Thu Aug 1 00:30:56 2024 X-Received: by 10.182.110.130 with SMTP id ia2mr23827229obb.42.1409162625127; Wed, 27 Aug 2014 11:03:45 -0700 (PDT) X-Received: by 10.50.50.97 with SMTP id b1mr113204igo.9.1409162624985; Wed, 27 Aug 2014 11:03:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!uq10no5924068igb.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no8558825igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Aug 2014 11:03:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=98.154.38.111; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 98.154.38.111 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <05210d57-2fcc-4177-a328-e408ce00358a@googlegroups.com> Subject: Where can I find the limitations on length of a paper and number of its graphs and other information of JACM From: Weng Tianxiang Injection-Date: Wed, 27 Aug 2014 18:03:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3272 Hi, I am preparing to deliver my first paper to Journal of ACM. I downloaded the format file from http://www.acm.org/publications/word_style/V2-ACM-SMALL-AUGUST-2012.zip through http://www.acm.org/publications/word_style/word-style-toc/ But I cannot find the limitations on length of a paper and number of its graphs and other information, for example, fees for reviewing and publishing. Help please. Weng From newsfish@newsfish Thu Aug 1 00:30:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!dedibox.gegeweb.org!gegeweb.eu!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp3-2.free.fr!not-for-mail Date: Wed, 27 Aug 2014 21:21:10 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 References: <53f90758$0$2007$426a74cc@news.free.fr> <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> <53fb9140$0$2224$426a74cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 9 Message-ID: <53fe2fa6$0$5102$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 27 Aug 2014 21:21:10 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1409167270 news-2.free.fr 5102 88.185.146.198:1772 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3273 Le 25/08/2014 22:42, rickman a crit : > You used "out" in your signal declaration for D. Was that intentional? Oops sorry no, I just copy-pasted the orignal code and replaced the types, I forgot to fix this. Nicolas From newsfish@newsfish Thu Aug 1 00:30:56 2024 X-Received: by 10.236.118.195 with SMTP id l43mr11772237yhh.52.1409212391102; Thu, 28 Aug 2014 00:53:11 -0700 (PDT) X-Received: by 10.140.37.39 with SMTP id q36mr13345qgq.10.1409212391022; Thu, 28 Aug 2014 00:53:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i13no3785414qae.1!news-out.google.com!q8ni3qal.1!nntp.google.com!i13no3785412qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Aug 2014 00:53:10 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.182.238.172; posting-account=DanITAoAAADZRQ3INvxcdLr4w4QwYv0X NNTP-Posting-Host: 88.182.238.172 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> Subject: [VHDL Documentation tool] First release of pyVhdl2Sch From: Laurent Cabaret Injection-Date: Thu, 28 Aug 2014 07:53:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 12 Xref: news.eternal-september.org comp.lang.vhdl:3274 Hi, just a message to annouce the first release of a python based documentatiion tool. pyVhdl2Sch is a documentation generator tool. It takes VHDL files (.vhd) as entry and generates a pdf schematic for each input file. pyVhdl2Sch is based on Python and is a rewrite of the QT/Latex based Vhdl2Sch. More details here : https://github.com/LaurentCabaret/pyVhdl2Sch Feel free to criticize/cheers/participate/... Laurent From newsfish@newsfish Thu Aug 1 00:30:57 2024 X-Received: by 10.50.136.166 with SMTP id qb6mr7943749igb.5.1412340242402; Fri, 03 Oct 2014 05:44:02 -0700 (PDT) X-Received: by 10.140.40.85 with SMTP id w79mr553qgw.38.1412340242322; Fri, 03 Oct 2014 05:44:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no1110224igc.0!news-out.google.com!i10ni60qaf.0!nntp.google.com!s7no282918qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Oct 2014 05:44:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.59.43.213; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 195.59.43.213 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e3b5c9f-38da-4d94-bf82-d75e6f11eba7@googlegroups.com> Subject: clear "endfile" flag? From: niv Injection-Date: Fri, 03 Oct 2014 12:44:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3275 I have a TBench that reads a file in a loop: i.e. while not endfile(my_file) ... ... However, later in the TBench, I need to read the file again, but it obviously see that the file has reached the end. How do I clear the endfile status please? Regards, Niv. From newsfish@newsfish Thu Aug 1 00:30:57 2024 X-Received: by 10.66.191.233 with SMTP id hb9mr5053766pac.4.1412340616476; Fri, 03 Oct 2014 05:50:16 -0700 (PDT) X-Received: by 10.140.29.230 with SMTP id b93mr14098qgb.4.1412340616088; Fri, 03 Oct 2014 05:50:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!uq10no3222145igb.0!news-out.google.com!i10ni60qaf.0!nntp.google.com!s7no283304qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Oct 2014 05:50:16 -0700 (PDT) In-Reply-To: <3e3b5c9f-38da-4d94-bf82-d75e6f11eba7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.59.43.213; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 195.59.43.213 References: <3e3b5c9f-38da-4d94-bf82-d75e6f11eba7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <57acbcb9-82f8-4db4-ae9e-f7e5730664f4@googlegroups.com> Subject: Re: clear "endfile" flag? From: niv Injection-Date: Fri, 03 Oct 2014 12:50:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1565 X-Received-Body-CRC: 4029614542 Xref: news.eternal-september.org comp.lang.vhdl:3276 On Friday, 3 October 2014 13:44:05 UTC+1, niv wrote: > I have a TBench that reads a file in a loop: > > > > i.e. while not endfile(my_file) > > > > ... > > ... > > > > However, later in the TBench, I need to read the file again, but it obviously see that the file has reached the end. > > > > How do I clear the endfile status please? > > > > Regards, Niv. Is it as simple as: endfile(my_file) <= FALSE; ??? Regards, Niv. From newsfish@newsfish Thu Aug 1 00:30:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx20.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PSL help please References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> <7741882d-b5b7-4636-80b4-ff7746f7de28@googlegroups.com> <939fe762-14c5-4730-aa09-b7d7fb0f702d@googlegroups.com> In-Reply-To: <939fe762-14c5-4730-aa09-b7d7fb0f702d@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 141003-0, 03/10/2014), Outbound message X-Antivirus-Status: Clean Lines: 23 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1412340780 86.17.210.161 (Fri, 03 Oct 2014 12:53:00 UTC) NNTP-Posting-Date: Fri, 03 Oct 2014 12:53:00 UTC Organization: virginmedia.com Date: Fri, 03 Oct 2014 13:52:56 +0100 X-Received-Body-CRC: 3168006914 X-Received-Bytes: 1767 Xref: news.eternal-september.org comp.lang.vhdl:3277 Hi Andy, On 30/09/2014 18:54, Andy wrote: > IMHO, plain old procedural VHDL with assertion statements is so much easier to write and debug... well.... perhaps, it all depends on the complexity of the assertion. You can write very simple PSL assertions and if you are already using OVL then the jump to PSL is not that difficult. The problem with PSL is that it requires an expensive license and hence not many engineers get access to it. > Are you using PSL to support Formal Analysis? Perhaps in the future when formal tools become more affordable, Regards, Hans. www.ht-lab.com > > Andy > From newsfish@newsfish Thu Aug 1 00:30:58 2024 X-Received: by 10.43.137.2 with SMTP id im2mr9568059icc.22.1412347734990; Fri, 03 Oct 2014 07:48:54 -0700 (PDT) X-Received: by 10.140.109.203 with SMTP id l69mr4967qgf.27.1412347734813; Fri, 03 Oct 2014 07:48:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no3285361igb.0!news-out.google.com!q8ni41qal.1!nntp.google.com!dc16no408955qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Oct 2014 07:48:54 -0700 (PDT) In-Reply-To: <57acbcb9-82f8-4db4-ae9e-f7e5730664f4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.188.153.114; posting-account=kPb-OQoAAABrjfR10Xor0FEhs2Rpst_8 NNTP-Posting-Host: 86.188.153.114 References: <3e3b5c9f-38da-4d94-bf82-d75e6f11eba7@googlegroups.com> <57acbcb9-82f8-4db4-ae9e-f7e5730664f4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0eafded7-b1a8-44f5-a622-fe22ff953046@googlegroups.com> Subject: Re: clear "endfile" flag? From: graham.p.ward@googlemail.com Injection-Date: Fri, 03 Oct 2014 14:48:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3278 I suggest that you close and re-open the file. From newsfish@newsfish Thu Aug 1 00:30:58 2024 X-Received: by 10.182.191.36 with SMTP id gv4mr6681832obc.50.1412372471832; Fri, 03 Oct 2014 14:41:11 -0700 (PDT) X-Received: by 10.140.20.246 with SMTP id 109mr34682qgj.0.1412372471683; Fri, 03 Oct 2014 14:41:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no1316399igc.0!news-out.google.com!q8ni41qal.1!nntp.google.com!dc16no462357qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Oct 2014 14:41:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> <7741882d-b5b7-4636-80b4-ff7746f7de28@googlegroups.com> <939fe762-14c5-4730-aa09-b7d7fb0f702d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <118dc6d0-4c1f-4185-834e-3d78cca2741e@googlegroups.com> Subject: Re: PSL help please From: Andy Injection-Date: Fri, 03 Oct 2014 21:41:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3279 Define "very simple" for real-world applications. If you mean "very short and cryptic," I agree completely. Andy From newsfish@newsfish Thu Aug 1 00:30:58 2024 X-Received: by 10.66.142.167 with SMTP id rx7mr4961284pab.12.1412614746405; Mon, 06 Oct 2014 09:59:06 -0700 (PDT) X-Received: by 10.50.57.11 with SMTP id e11mr143283igq.6.1412614746292; Mon, 06 Oct 2014 09:59:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no5010962igb.0!news-out.google.com!bc9ni17237igb.0!nntp.google.com!h18no2183592igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 6 Oct 2014 09:59:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.150.45; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.150.45 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL-2008 to -93 converter for synthesis From: Daniel Kho Injection-Date: Mon, 06 Oct 2014 16:59:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3280 Dear all, Recently I have built a small tool that eventually aims to give people the = ability to code synthesisable designs in VHDL-2008. The new P1076-2008 stan= dard has a whole bunch of new features that allow us to all write simple an= d concise designs. Many of us (me included) wouldn't want to go back to wri= ting '93 code if we hadn't needed to. Unfortunately, current synthesis supp= ort for VHDL-2008 is still lacking in many EDA tools. I like to change that, and hopefully many of you like to see better languag= e support in tools as well. An alpha version of the tool can be found here: http://www.tauhop.com (informational) http://www.tauhop.com/#!hls (the tool) Feel free to use it and test its features, currently limited to uninstantia= ted packages, generic packages, and generic types in packages. From the man= y requests I see in forums, I have decided that this is the area with which= I should focus on right now: VHDL-2008's enhanced generics, before moving = on to other features. Please let me know if there are any other specific '2008 features you like = me to spend some time on, and I will surely consider them to be added into = my roadmap. As many of you would understand, this effort is not trivial, and it does co= nsume a significant amount of my time per week. At this time, you may use t= he service for free on www.tauhop.com/#!hls but I request your kind support= in helping me bring food to the table, so I can continue working towards b= uilding something useful that all of you can use. There are a number of options you can help me financially. The webpage give= s you some options, but I also accept any arbitrary sum that you feel comfo= rtable with. Just write to me (daniel.kho tauhop.com) so we can work t= his out. One more thing. If you feel you could help me market this product, please g= et in touch as well. You will have a good share of the revenue you help gen= erate. Best regards, Daniel Kho Tauhop Solutions From newsfish@newsfish Thu Aug 1 00:30:59 2024 X-Received: by 10.50.134.137 with SMTP id pk9mr3022503igb.0.1412703367973; Tue, 07 Oct 2014 10:36:07 -0700 (PDT) X-Received: by 10.140.38.177 with SMTP id t46mr24907qgt.21.1412703367731; Tue, 07 Oct 2014 10:36:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no5894014igb.0!news-out.google.com!bc9ni17237igb.0!nntp.google.com!h18no2808292igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Oct 2014 10:36:07 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.176.51.135; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 46.176.51.135 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <98cd33e9-e9ec-4445-bce8-0cc0c802d62f@googlegroups.com> Subject: [RFC] METATOR - A look into processor synthesis From: Nikolaos Kavvadias Injection-Date: Tue, 07 Oct 2014 17:36:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3281 These last few months, I have been slowly moving back to my main interests,= EDA tools (as a developer and as a user), FPGA application engineering, an= d last but not least processor design. After a 5-year hiatus I have started= revamping (and modernizing) my own environment, developed as an outcome of= my PhD work on application-specific instruction-set processors (ASIPs). Th= e flow was based on SUIF/Machine-SUIF (compiler), SALTO (assembly-level tra= nsformations) and ArchC (architecture description language for producing bi= nary tools and simulators). It was a highly-successful flow that allowed me= (along with my custom instruction generator YARDstick) to explore configur= ations and extensions of processors with seconds or minutes. I have been thinking about what's next. We have tools to assist the designe= r (the processor design engineer per se) to speedup his/her development. St= ill, the processor must be designed explicitly. What would go beyond the st= ate-of-the-art is not to have to design the golden model of the processor a= t all. What I am proposing is an application-specific processor synthesis tool tha= t goes beyond the state-of-the-art. A model generator for producing the hig= h-level description of the processor, based only on application analysis an= d user-defined constraints. And for the fun of it, let's codename it METATO= R, because I tend to watch too much Supernatural these days, and METATOR (m= essenger) is a possible meaning for METATRON, an angelic being from the Apo= crypha with a human past. So think of METATOR as an upgrade (spiritual or n= ot) to the current status of both academic and commercial ASIP design tools= . 1. The Context, the Problem and its Solution ASIPs are tuned for cost-effective execution of targeted application sets. = An ASIP design flow involves profiling, architecture exploration, generatio= n and selection of functionalities and synthesis of the corresponding hardw= are while enabling the user taking certain decisions. The state-of-the-art in ASIP synthesis includes commercial efforts from Syn= opsys which has accumulated three relevant portfolios: the ARC configurable= processor cores, Processor Designer (previously LISATek) and the IP Design= er nML-based tools (previously Target Compiler Technologies); ASIPmeister b= y ASIP Solutions (site down?), Lissom/CodAL by Codasip, and the academic TC= E and NISC toolsets. Apologies if I have missed any other ASIP technology p= rovider! The key differentiation point of METATOR against existing approaches is tha= t ASIP synthesis should not require the explicit definition of a processor = model by a human developer. The solution implies the development of a novel= scheme for the extraction of a common denominator architectural model from= a given set of user applications (accounting for high-level constraints an= d requirements) that are intended to be executed on the generated processor= by the means of graph similarity extraction. From this automatically gener= ated model, an RTL description, verification IP and a programming toolchain= would be produced as part of an automated targeting process, in like "meta= -": a generated model generating models!. 2. Conceptual ASIP Synthesis Flow METATOR would accept as input the so-called algorithmic soup (narrow set of= applications) and generate the ADL (Architecture Description Language) des= cription of the processor. My first aim would be for ArchC but this could a= lso expand to the dominant ADLs, LISA 2.0 and nML. METATOR would rely upon HercuLeS high-level synthesis technology and the YA= RDstick profiling and custom instruction generation environment. In the pas= t, YARDstick has been used for generating custom instructions (CIs) for Byo= RISC (Build Your Own RISC) soft-core processors. ByoRISC is a configurable = in-order RISC design, allowing the execution of multiple-input, multiple-ou= tput custom instructions and achieving higher performance than typical VLIW= architectures. CIs for ByoRISC where generated by YARDstick, which purpose= is to perform application analysis on targeted codes, identify application= hotspots, extract custom instructions and evaluate their potential impact = on code performance for ByoRISC. = 3. Conclusion To sum this up, METATOR is a mind experiment in ASIP synthesis technology. = It automatically generates a full-fledged processor and toolchain merely fr= om its usage intent, expressed as indicative targeted application sets. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Thu Aug 1 00:30:59 2024 X-Received: by 10.182.241.2 with SMTP id we2mr8208162obc.38.1413585942945; Fri, 17 Oct 2014 15:45:42 -0700 (PDT) X-Received: by 10.140.100.150 with SMTP id s22mr1132qge.34.1413585942797; Fri, 17 Oct 2014 15:45:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!uq10no12765333igb.0!news-out.google.com!i10ni93qaf.0!nntp.google.com!s7no3497027qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 17 Oct 2014 15:45:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=178.61.0.144; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 178.61.0.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Handel-C to (VHDL or Verilog or EDIF) From: ahmedablak0@gmail.com Injection-Date: Fri, 17 Oct 2014 22:45:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3282 hi, I am trying to generate VHDL or Verlog or EDIF from Handel-C. I always end with an empty (VHDL,Verilog,EDIF) files. Any one faced this issue before ?? and how to solve it ?? Thanks From newsfish@newsfish Thu Aug 1 00:30:59 2024 X-Received: by 10.182.246.3 with SMTP id xs3mr15970231obc.13.1413747236242; Sun, 19 Oct 2014 12:33:56 -0700 (PDT) X-Received: by 10.140.84.21 with SMTP id k21mr3633qgd.6.1413747236093; Sun, 19 Oct 2014 12:33:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!uq10no13823324igb.0!news-out.google.com!i10ni95qaf.0!nntp.google.com!s7no3874903qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 19 Oct 2014 12:33:55 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.103.204.115; posting-account=YmCAXAoAAABbHW0Ist1dYHuAZjNjssNb NNTP-Posting-Host: 213.103.204.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3745da2c-651e-4ca0-8e37-6e1ef6d976f5@googlegroups.com> Subject: NFA FSM From: mohitkumar39@gmail.com Injection-Date: Sun, 19 Oct 2014 19:33:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3283 Hi Guys! I am trying to code the following sequential re-coder/scrambler FSM in VHDL. 000 -> 110 001 -> 101 010 -> 111 011 -> 110 100 -> 010 101 -> 011 110 -> 010 111 -> 000 I understand this is an NFA and must be converted to DFA before implementing. I was able to convert into a DFA, but I am not sure how to assign the output for the merged states. Help on this would be appreciated. From newsfish@newsfish Thu Aug 1 00:31:00 2024 X-Received: by 10.52.165.165 with SMTP id yz5mr21588153vdb.4.1413878038432; Tue, 21 Oct 2014 00:53:58 -0700 (PDT) X-Received: by 10.140.101.227 with SMTP id u90mr3498qge.18.1413878038371; Tue, 21 Oct 2014 00:53:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!dc16no4340068qab.1!news-out.google.com!u5ni9qab.1!nntp.google.com!cm18no6693qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Oct 2014 00:53:58 -0700 (PDT) In-Reply-To: <3745da2c-651e-4ca0-8e37-6e1ef6d976f5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <3745da2c-651e-4ca0-8e37-6e1ef6d976f5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c6ee22d-643f-4dd5-8aab-29e457e503d8@googlegroups.com> Subject: Re: NFA FSM From: Thomas Stanka Injection-Date: Tue, 21 Oct 2014 07:53:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1911 X-Received-Body-CRC: 1938165863 Xref: news.eternal-september.org comp.lang.vhdl:3284 Am Sonntag, 19. Oktober 2014 21:33:58 UTC+2 schrieb mohitk...@gmail.com: > I am trying to code the following sequential re-coder/scrambler FSM in VH= DL. [..] > I understand this is an NFA and must be converted to DFA before implement= ing.=20 Why? Please explain on which details of the function you see the nondetermi= nstic behavior. In fact you have several possibilities, but I would use for the simple func= tion above a lookup table. If you consider the input as unsigned you could = just say that 0 =3D> 110, 1 =3D> 101 and so on, the conversion is than just= a lookup. Ofc you could also try to use karnaugh map to reduce the lookup = youself, but I'm sure for 3 bit input your sythesis tool will find best sol= ution. regards Thomas From newsfish@newsfish Thu Aug 1 00:31:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: NFA FSM Date: Tue, 21 Oct 2014 10:20:06 +0200 Organization: A noiseless patient Spider Lines: 6 Message-ID: References: <3745da2c-651e-4ca0-8e37-6e1ef6d976f5@googlegroups.com> <7c6ee22d-643f-4dd5-8aab-29e457e503d8@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 21 Oct 2014 08:17:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="6858"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19B0NMBgiWLntdfXJjwT3U9" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 In-Reply-To: <7c6ee22d-643f-4dd5-8aab-29e457e503d8@googlegroups.com> Cancel-Lock: sha1:KjGrH84NvtRfVECtNxutUI9q71o= Xref: news.eternal-september.org comp.lang.vhdl:3285 I also would implement it as a LUT. But input 100 and 110 has the same output. I think one of both should be 001 on output. Then it seems a bit like Gray Counter, going backward. Best regards, Tobias From newsfish@newsfish Thu Aug 1 00:31:00 2024 X-Received: by 10.43.155.13 with SMTP id lg13mr9487976icc.31.1413899229635; Tue, 21 Oct 2014 06:47:09 -0700 (PDT) X-Received: by 10.182.72.161 with SMTP id e1mr1154obv.41.1413899229421; Tue, 21 Oct 2014 06:47:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!enother.net!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!uq10no14931085igb.0!news-out.google.com!bc9ni31795igb.0!nntp.google.com!h18no8367675igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Oct 2014 06:47:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.91.171.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Subject: Simulation behavior for TestBench and UUT From: "V." Injection-Date: Tue, 21 Oct 2014 13:47:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1592 X-Received-Body-CRC: 2021999428 Xref: news.eternal-september.org comp.lang.vhdl:3286 At the top test bench level, I have something like this: PROCESS(clk, rst) BEGIN IF (rst = '1') THEN mytmp <= '1'; ELSIF RISING_EDGE(clk) THEN IF (busy = '1') THEN mytmp <= '0'; END IF; END IF; END PROCESS; At the top level, mytmp signal goes low on the same rising edge as my clock. -- I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. I am sure I am missing something very elementary here, could someone help me out? Thanks. From newsfish@newsfish Thu Aug 1 00:31:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Simulation behavior for TestBench and UUT Date: Tue, 21 Oct 2014 10:05:11 -0400 Organization: Alacron, Inc. Lines: 34 Message-ID: References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 21 Oct 2014 14:05:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="17244"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+eaQy+0sYIBl+7ZyGPqgW2ZISLCiMzVB0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Cancel-Lock: sha1:61QaVcoxLQvehfIWGOXRw5edyOk= Xref: news.eternal-september.org comp.lang.vhdl:3287 V. wrote: > At the top test bench level, I have something like this: > > PROCESS(clk, rst) > BEGIN > IF (rst = '1') THEN > mytmp <= '1'; > ELSIF RISING_EDGE(clk) THEN > IF (busy = '1') THEN > mytmp <= '0'; > END IF; > END IF; > END PROCESS; > > At the top level, mytmp signal goes low on the same rising edge as my clock. > > -- > > I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. > > I am sure I am missing something very elementary here, could someone help me out? > > > Thanks. You say "the same rising edge as my clock" which doesn't say anything to me. Do you mean that in the test bench there is no delay from the assertion of "busy" to "mytmp" going low? How is busy driven in the test bench? How is it driven in the UUT? My guess is that one has a simple time-based driver and the other gets it (after a delta delay) from an edge-triggered process. -- Gabor From newsfish@newsfish Thu Aug 1 00:31:01 2024 X-Received: by 10.70.131.230 with SMTP id op6mr22482819pdb.4.1413902788810; Tue, 21 Oct 2014 07:46:28 -0700 (PDT) X-Received: by 10.182.215.136 with SMTP id oi8mr182883obc.0.1413902788617; Tue, 21 Oct 2014 07:46:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no14965608igb.0!news-out.google.com!bc9ni31795igb.0!nntp.google.com!h18no8387665igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Oct 2014 07:46:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.31.106.34 References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Simulation behavior for TestBench and UUT From: "V." Injection-Date: Tue, 21 Oct 2014 14:46:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3288 On Tuesday, October 21, 2014 9:05:29 AM UTC-5, Gabor Sz wrote: > V. wrote: > > > At the top test bench level, I have something like this: > > > > > > PROCESS(clk, rst) > > > BEGIN > > > IF (rst = '1') THEN > > > mytmp <= '1'; > > > ELSIF RISING_EDGE(clk) THEN > > > IF (busy = '1') THEN > > > mytmp <= '0'; > > > END IF; > > > END IF; > > > END PROCESS; > > > > > > At the top level, mytmp signal goes low on the same rising edge as my clock. > > > > > > -- > > > > > > I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. > > > > > > I am sure I am missing something very elementary here, could someone help me out? > > > > > > > > > Thanks. > > > > You say "the same rising edge as my clock" which doesn't say anything > > to me. Do you mean that in the test bench there is no delay from the > > assertion of "busy" to "mytmp" going low? How is busy driven in the > > test bench? How is it driven in the UUT? My guess is that one has > > a simple time-based driver and the other gets it (after a delta delay) > > from an edge-triggered process. > > > > -- > > Gabor On Tuesday, October 21, 2014 9:05:29 AM UTC-5, Gabor Sz wrote: > V. wrote: > > > At the top test bench level, I have something like this: > > > > > > PROCESS(clk, rst) > > > BEGIN > > > IF (rst = '1') THEN > > > mytmp <= '1'; > > > ELSIF RISING_EDGE(clk) THEN > > > IF (busy = '1') THEN > > > mytmp <= '0'; > > > END IF; > > > END IF; > > > END PROCESS; > > > > > > At the top level, mytmp signal goes low on the same rising edge as my clock. > > > > > > -- > > > > > > I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. > > > > > > I am sure I am missing something very elementary here, could someone help me out? > > > > > > > > > Thanks. > > > > You say "the same rising edge as my clock" which doesn't say anything > > to me. Do you mean that in the test bench there is no delay from the > > assertion of "busy" to "mytmp" going low? How is busy driven in the > > test bench? How is it driven in the UUT? My guess is that one has > > a simple time-based driver and the other gets it (after a delta delay) > > from an edge-triggered process. > > > > -- > > Gabor On Tuesday, October 21, 2014 9:05:29 AM UTC-5, Gabor Sz wrote: > V. wrote: > > > At the top test bench level, I have something like this: > > > > > > PROCESS(clk, rst) > > > BEGIN > > > IF (rst = '1') THEN > > > mytmp <= '1'; > > > ELSIF RISING_EDGE(clk) THEN > > > IF (busy = '1') THEN > > > mytmp <= '0'; > > > END IF; > > > END IF; > > > END PROCESS; > > > > > > At the top level, mytmp signal goes low on the same rising edge as my clock. > > > > > > -- > > > > > > I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. > > > > > > I am sure I am missing something very elementary here, could someone help me out? > > > > > > > > > Thanks. > > > > You say "the same rising edge as my clock" which doesn't say anything > > to me. Do you mean that in the test bench there is no delay from the > > assertion of "busy" to "mytmp" going low? How is busy driven in the > > test bench? How is it driven in the UUT? My guess is that one has > > a simple time-based driver and the other gets it (after a delta delay) > > from an edge-triggered process. > > > > -- > > Gabor Sorry , I had meant to say: "At the top level, mytmp signal goes low on the same rising edge as busy". As you say, there is no delay from the assertion of "busy" to "mytmp" going low. --- Busy is generated by UUT (via clocked process), and sent out as an output to the testbench. It is essentially the same signal. The clk signal is also generated internally by UUT, and sent out to testbench. I'm using Modelsim as my simulator if it makes a difference. From newsfish@newsfish Thu Aug 1 00:31:01 2024 X-Received: by 10.236.61.132 with SMTP id w4mr25475377yhc.2.1413943523620; Tue, 21 Oct 2014 19:05:23 -0700 (PDT) X-Received: by 10.182.215.229 with SMTP id ol5mr204389obc.3.1413943523520; Tue, 21 Oct 2014 19:05:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!cm18no216712qab.0!news-out.google.com!ks2ni146igb.0!nntp.google.com!uq10no15312304igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Oct 2014 19:05:13 -0700 (PDT) In-Reply-To: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <113be19a-7e95-4c09-a7fa-90fad11f98ae@googlegroups.com> Subject: Re: Simulation behavior for TestBench and UUT From: KJ Injection-Date: Wed, 22 Oct 2014 02:05:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 47 Xref: news.eternal-september.org comp.lang.vhdl:3289 On Tuesday, October 21, 2014 9:47:11 AM UTC-4, V. wrote: > At the top test bench level, I have something like this:=20 >=20 > PROCESS(clk, rst) > BEGIN > IF (rst =3D '1') THEN > mytmp <=3D '1'; =20 > ELSIF RISING_EDGE(clk) THEN > IF (busy =3D '1') THEN > mytmp <=3D '0'; > END IF; > END IF; > END PROCESS; >=20 > At the top level, mytmp signal goes low on the same rising edge as my clo= ck.=20 >=20 >=20 > I then repeat this code within my UUT (still instantiated by same testben= ch),=20 > but now mytmp signal goes low on the following rising edge clock after bu= sy=20 > is asserted. >=20 > I am sure I am missing something very elementary here, could someone help= me out?=20 >=20 What you're missing is that when your testbench code hits the line 'IF (bus= y =3D '1') THEN...' the rising edge of the clock has already occurred and t= he subsequent assignment to 'mytmp' will not occur until one simulation del= ta after the rising edge of the clock. Now consider the UUT. If 'mytmp' d= oes not change until after the rising edge of the clock then really it won'= t be looked at again until the NEXT rising edge. In order to see this more= clearly, simply change the assignment to 'mytmp' to include some non-zero = delay like this 'mytmp <=3D '0' after 2 ns;'. Your testbench and UUT will = respond identically based on what you described.=20 But before you go thinking that you somehow need to curse simulation deltas= realize that what you're describing in the code you posted is a form of a = flip flop where 'busy' is an input. The 'D' input to a flip flop always sw= itches on the previous clock cycle relative to the 'Q' output of that flip = flop. There is nothing inherently wrong here unless the protocol of your s= ignals is that 'mytmp' should occur on the same clock cycle as 'busy'. If = that's the case, then 'mytmp' should be a concurrent statement, not inside = a clocked process. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:31:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: [cross-post] verification vs design Followup-To: comp.arch.fpga Date: 22 Oct 2014 08:10:37 GMT Lines: 34 Message-ID: X-Trace: individual.net 2XO2ltchnXz1RFBrYx/grg8DQHnpZ2hiO0OTygcNILUQVsm2Dn Keywords: verification,fpga X-Orig-Path: not-for-mail Cancel-Lock: sha1:8Zrf5EACgS4/1/1nRIUq/urigJM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.arch.fpga:7358 comp.lang.vhdl:3290 Hi everyone, I've recently had to argue why it is not 'sane' to budget 500 hours of development against 200 of verification. If you ask the FPGA developer he'd say a factor of 2/3 has to be considered for verification w.r.t. design (that I tend to agree to). I'd like to give some grounds to those estimates and I asked the fpga group leader to compare among several completed projects what is this ratio. We are usually collecting lots of data on the amount and type of work we do every day and this data can be used to verify the verification effort w.r.t. the design effort. His counter argument is that it is difficult to compare projects due to their peculiarity, implying that there's very little that we can learn from the past (that I obviously do not buy!). As of your knowledge is there any source of - trusted - data that I can point at? Is there really a ratio that can be 'generally' applied? Any comment/opinion/pointer is appreciated. Al p.s.: this thread is intentially crossposted to comp.lang.vhdl and comp.arch.fpga. Please use the followup-to field in order to avoid breaking the thread. -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Thu Aug 1 00:31:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Simulation behavior for TestBench and UUT Date: Wed, 22 Oct 2014 09:50:14 -0400 Organization: Alacron, Inc. Lines: 22 Message-ID: References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 22 Oct 2014 13:50:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="29896"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/2TExtqMjuR3ElJNhdEJOXQbXB0sQgbGY=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:oLAFnhypG4Bq17/SesnKOs8/QKY= Xref: news.eternal-september.org comp.lang.vhdl:3291 V. wrote: > > Sorry , I had meant to say: > "At the top level, mytmp signal goes low on the same rising edge as busy". > > As you say, there is no delay from the assertion of "busy" to "mytmp" going low. > > --- > > Busy is generated by UUT (via clocked process), and sent out as an output to the testbench. It is essentially the same signal. > > The clk signal is also generated internally by UUT, and sent out to testbench. I'm using Modelsim as my simulator if it makes a difference. Then you need to see how the UUT generates the clock going back to the test bench. If the clock and the busy signal are generated at the same time, then you have in effect a race condition. If your UUT is supposed to drive this (in real hardware) to another device that requires setup and hold time with respect to the generated clock, you need to fix your design that there is some real delay in the busy output. -- Gabor From newsfish@newsfish Thu Aug 1 00:31:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed2-b.proxad.net!nnrp4-2.free.fr!not-for-mail Date: Thu, 23 Oct 2014 00:31:07 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Simulation behavior for TestBench and UUT References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 13 Message-ID: <54483023$0$2335$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 23 Oct 2014 00:30:59 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1414017059 news-3.free.fr 2335 88.185.146.198:1091 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3292 Le 21/10/2014 16:46, V. a écrit : [loads of snipped useless lines] > > Sorry , I had meant to say: > "At the top level, mytmp signal goes low on the same rising edge as busy". > > As you say, there is no delay from the assertion of "busy" to "mytmp" going low. Did you really need to quote the whole thread (with added blank lines, courtesy of this piece of sh*t that's Google groups) just to add these three lines ? Nicolas From newsfish@newsfish Thu Aug 1 00:31:03 2024 X-Received: by 10.50.111.170 with SMTP id ij10mr8012793igb.1.1414179189793; Fri, 24 Oct 2014 12:33:09 -0700 (PDT) X-Received: by 10.182.22.13 with SMTP id z13mr70486obe.5.1414179189565; Fri, 24 Oct 2014 12:33:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!uq10no16983661igb.0!news-out.google.com!ks2ni1344igb.0!nntp.google.com!uq10no16983659igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Oct 2014 12:33:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.15.159.241; posting-account=7508ugoAAAD0yBZ9X0HzJ1jhCKp4TH7N NNTP-Posting-Host: 129.15.159.241 References: <5dd17323.0204142133.2ac6e113@posting.google.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: unsigned to bit_vector From: lesya.borowska@noaa.gov Injection-Date: Fri, 24 Oct 2014 19:33:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2545 X-Received-Body-CRC: 4222427127 Xref: news.eternal-september.org comp.lang.vhdl:3293 On Friday, April 19, 2002 6:40:44 AM UTC-5, Renaud Pacalet wrote: > chak a =E9crit : >=20 > > hi every body, > > could any body suggest me how to convert unsigned to bit > > vector...... and bitvector to unsigned with an exmaple.i will be > > very thank full thanx in advance > > chakri >=20 > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.NUMERIC_STD.all; > ... > signal BV: BIT_VECTOR(15 downto 0); > signal UV: UNSIGNED(1 to 16); > ... > BV <=3D TO_BITVECTOR(STD_ULOGIC_VECTOR(UV)); > UV <=3D UNSIGNED(TO_STDULOGICVECTOR(BV)); >=20 > As suggested by Egbert the FAQ is a good starting point if you want > to understand all this. >=20 > Regards. > --=20 > Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13 > Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pacalet@enst.fr > ###### Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ ###### Dear Renaud, I also need to convert unsigned to bit vector...... and bit vector to unsig= ned. Unfortunately, I need to use USE ieee.numeric_bit.all;=20 When I add=20 use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;=20 my program gives me an error (vcom-1078) Identifier "unsigned" is not direc= tly visible. Do you know any other way to unsigned to bit vector...... and bit vector to= unsigned using USE ieee.numeric_bit.all; Thanks! Have a nice evening, Lesya From newsfish@newsfish Thu Aug 1 00:31:03 2024 X-Received: by 10.68.135.99 with SMTP id pr3mr9566228pbb.9.1414191304897; Fri, 24 Oct 2014 15:55:04 -0700 (PDT) X-Received: by 10.50.136.197 with SMTP id qc5mr86642igb.6.1414191304770; Fri, 24 Oct 2014 15:55:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no17071711igb.0!news-out.google.com!rp1ni2654igb.0!nntp.google.com!h18no9644641igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Oct 2014 15:55:04 -0700 (PDT) In-Reply-To: <5dd17323.0204142133.2ac6e113@posting.google.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <5dd17323.0204142133.2ac6e113@posting.google.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: unsigned to bit_vector From: diogratia@gmail.com Injection-Date: Fri, 24 Oct 2014 22:55:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3294 On Monday, April 15, 2002 5:33:16 PM UTC+12, chak wrote: > hi every body, > could any body suggest me how to convert unsigned to bit vector...... > and bitvector to unsigned with an exmaple.i will be very thank full > thanx in advance > chakri With a context clause consisting of=20 library ieee; use ieee.numeric_bit.all; The conversion between the unsigned type declared in numeric_bit and bit_ve= ctor can be accomplished explicit type conversion between closely related t= ypes: entity foo is end entity; architecture fum of foo is signal unsigned_vector: unsigned (7 downto 0):=3D "11001010"; signal bit_val: bit_vector (7 downto 0); begin bit_val <=3D bit_vector(unsigned_vector); end architecture; unsigned is defined as an array natural range of type bit in package numeri= c_bit while bit_vector is defined as an array natural range of type bit in = package standard. This makes the two types closely related, both arrays wi= th the same element type, dimensionality and index type. This context clause and associated entity/architecture pair analyzes, elabo= rates and simulates. Conversion to unsigned is also accomplished by explicit type conversion: architecture fie of foo is signal unsigned_vector: unsigned (7 downto 0):=3D "11001010"; signal bit_val: bit_vector (7 downto 0); signal un_signed: unsigned (7 downto 0); begin bit_val <=3D bit_vector(unsigned_vector); un_signed <=3D unsigned(bit_val); end architecture; And this also analyzes, elaborates and simulates, differing from the previo= us architecture by doing conversion between unsigned and bit_vector and bit= _vector and unsigned. So as you can see from the rest of the answers you can see there is confusi= on on which declared unsigned to which you're referring. In those cases where you need to express a VHDL design specification with b= oth unsigned type declarations visible you could partition by visibility. F= or instance you could specify use clauses as process declarative items in a= process statement's process declarative part. You'd communicate between th= e two processes via signals declared from types visible in both declarative= regions. For example one process statement can have a use clause=20 use ieee.numeric_std.all; and use ieee.numeric_std.unsigned. While another process statement can have= =20 =20 use ieee.numeric_bit.all; and use ieee.numeric_bit.unsigned. You'd communicate between the two processes using signals whose types are v= isible to both declarations (e.g. bit_vector, std_logic_vector). Any unsign= ed types would be variables declared as process declarative items. You could also use selected names: library ieee; use ieee.numeric_bit.all; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fuu is end entity; architecture fee of fuu is signal unsigned_vector: ieee.numeric_bit.unsigned (7 downto 0) :=3D "11001010"; signal bit_val: bit_vector (7 downto 0); signal un_signed: ieee.numeric_bit.unsigned (7 downto 0); signal unsigned_slv: ieee.numeric_std.unsigned (7 downto 0); signal bit_unsigned: ieee.numeric_bit.unsigned (7 downto 0); begin bit_val <=3D bit_vector(unsigned_vector); un_signed <=3D ieee.numeric_bit.unsigned(bit_val); unsigned_slv <=3D ieee.numeric_std.unsigned(to_stdlogicvector(bit_val))= ; bit_unsigned <=3D ieee.numeric_bit.unsigned( to_bitvector(std_logic_vector(unsigned_slv)) ); end architecture; Selected names overcome the issue of ambiguity with two types named unsigne= d. (And this example also analyzes, elaborates and simulates) From newsfish@newsfish Thu Aug 1 00:31:03 2024 X-Received: by 10.52.188.67 with SMTP id fy3mr22305240vdc.5.1414439959900; Mon, 27 Oct 2014 12:59:19 -0700 (PDT) X-Received: by 10.50.43.233 with SMTP id z9mr265569igl.5.1414439959747; Mon, 27 Oct 2014 12:59:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no995138qap.0!news-out.google.com!ks2ni4879igb.0!nntp.google.com!h15no388278igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 27 Oct 2014 12:59:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.150.156; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.150.156 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> Subject: Finally some VHDL-2008 support in Xilinx Vivado From: Daniel Kho Injection-Date: Mon, 27 Oct 2014 19:59:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 5 Xref: news.eternal-september.org comp.lang.vhdl:3295 Just received word that Xilinx has implemented some features of VHDL-2008 in their Vivado tool. Some of you guys may be interested to try these new compiler features. I am sure to be trying them out: http://www.xilinx.com/support/answers/62005.html Cheers, dan From newsfish@newsfish Thu Aug 1 00:31:04 2024 X-Received: by 10.67.4.3 with SMTP id ca3mr8901322pad.23.1414614834251; Wed, 29 Oct 2014 13:33:54 -0700 (PDT) X-Received: by 10.182.79.104 with SMTP id i8mr33119obx.21.1414614834147; Wed, 29 Oct 2014 13:33:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no1542692igi.0!news-out.google.com!ks2ni6272igb.0!nntp.google.com!r10no1542686igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Oct 2014 13:33:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: An unconstrained array problem From: Weng Tianxiang Injection-Date: Wed, 29 Oct 2014 20:33:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3296 I have a problem with how to deal with an unconstrained array. Here is the code snippet: Package A_package is constant DATA_OUT_WIDTH : positive := 8; -- data out width type OUT_DATA_ARRAY is array(natural range <>) of unsigned(DATA_OUT_WIDTH-1 downto 0); end A_package; -- B_module would be used as a VHDL system module shared by all designers entity B_module is generic ( MULTIPLE : positive := 1) port ( ... D_I : in OUT_DATA_ARRAY(MULTIPLE-1 downto 0); ... ); end B_module; architecture B of B_module is ... end B; If B_module is for use for one person or one company, there is no problem with VHDL-2002, what to do for a user to use B_module is to change DATA_OUT_WIDTH's value in A_package to meet his new width requirement for B_module. Now B_package is designed for all designers with VHDL and B_package is expected to be included into any VHDL system library. Problem comes! User cannot change DATA_OUT_WIDTH for OUT_DATA_ARRAY. What I want to do is: -- C_module would be used as a VHDL system module shared by all designers entity C_module is generic ( MULTIPLE : positive := 1; DATA_OUT_WIDTH : positive := 8; type OUT_DATA_ARRAY is array(natural range <>) of unsigned(DATA_OUT_WIDTH-1 downto 0)) port ( ... D_I : in OUT_DATA_ARRAY(MULTIPLE-1 downto 0); ... ); end C_module; In other words,if new type definition can be introduced into generic, each time C_module is used, OUT_DATA_ARRAY can be any type a user wants. I think it is the easiest way to deal with unconstrained array while it complies with current VHDL grammar style. Two helps are needed: 1. For VHDL-2002, is there any method to resolve the problem? 2. For VHDL-2008, is there any method to resolve the problem as I suggested in C_module? Thank you. Weng From newsfish@newsfish Thu Aug 1 00:31:04 2024 X-Received: by 10.236.61.69 with SMTP id v45mr4499462yhc.57.1414628676532; Wed, 29 Oct 2014 17:24:36 -0700 (PDT) X-Received: by 10.51.16.65 with SMTP id fu1mr244899igd.10.1414628676288; Wed, 29 Oct 2014 17:24:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed0.kamp.net!newsfeed.kamp.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.112.MISMATCH!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!s7no1496512qap.0!news-out.google.com!ks2ni4879igb.0!nntp.google.com!h15no1857537igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Oct 2014 17:24:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <34fb902e-40fc-47b3-a776-ef8400a63a17@googlegroups.com> Subject: Re: An unconstrained array problem From: Jim Lewis Injection-Date: Thu, 30 Oct 2014 00:24:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1487 X-Received-Body-CRC: 3249745530 Xref: news.eternal-september.org comp.lang.vhdl:3297 Hi Weng, VHDL-2008 allows arrays to have unconstrained elements. Hence, you could have a package that defines type std_logic_matrix is array (natural range <>) of std_logic_vector ; And then constrain both dimensions in a signal or port: signal A : std_logic_matrix(5 downto 0)(7 downto 0) ; It is a VHDL-2008 feature, so synthesis vendor support may vary. Jim From newsfish@newsfish Thu Aug 1 00:31:04 2024 X-Received: by 10.50.43.228 with SMTP id z4mr22961180igl.4.1414631069227; Wed, 29 Oct 2014 18:04:29 -0700 (PDT) X-Received: by 10.50.118.9 with SMTP id ki9mr245955igb.16.1414631068924; Wed, 29 Oct 2014 18:04:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1872853igd.0!news-out.google.com!ks2ni4879igb.0!nntp.google.com!h15no1872850igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Oct 2014 18:04:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <67a4efa8-9a75-4a41-8d73-ed67b8e11b92@googlegroups.com> Subject: Re: An unconstrained array problem From: Weng Tianxiang Injection-Date: Thu, 30 Oct 2014 01:04:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3298 Hi Jim, I haven't heard you for a long time. I hope to give you some new ideas in near future. Your comments are excellent and appreciated. Thank you. Weng From newsfish@newsfish Thu Aug 1 00:31:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Paul Colin de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: Finally some VHDL-2008 support in Xilinx Vivado Date: Fri, 31 Oct 2014 20:25:53 +0100 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx02.eternal-september.org; posting-host="1269e88b772369679a1c60bd0bac220f"; logging-data="26902"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+HOli8JKOdni8Qwor1ejJTY6lRle9yArDWGclaaBR87g==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> Cancel-Lock: sha1:V5WkN84HvioCcoKEWg5mDbEBpGE= X-X-Sender: gloster@anapnea.net Xref: news.eternal-september.org comp.lang.vhdl:3299 On 27th October 2014, Daniel Kho sent: |---------------------------------------------------------------------| |"Just received word that Xilinx has implemented some features of | |VHDL-2008 in their Vivado tool. Some of you guys may be interested to| |try these new compiler features. | | | |I am sure to be trying them out: | | http://www.xilinx.com/support/answers/62005.html | | | |Cheers, dan" | |---------------------------------------------------------------------| I would like to thank Dan for the good work he has been doing for standardizing VHDL. Cheers, Paul Colin From newsfish@newsfish Thu Aug 1 00:31:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: LRM: Double-block instantiations Date: Sun, 02 Nov 2014 11:14:39 +0200 Organization: A noiseless patient Spider Lines: 44 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 2 Nov 2014 09:14:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="2749"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18fIhq3z7gv3JFGDdB3JVCsQcwyJcRAjoY=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 Cancel-Lock: sha1:EVl4vuFModEpvQfb0Ij7Emkhh04= Xref: news.eternal-september.org comp.lang.vhdl:3300 Specification says "A component instantiation is equivalent to a pair of nested block statements that couple the block hierarchy in the containing design unit to a unique copy of the block hierarchy contained in another design unit (i.e., the subcomponent). The outer block represents the component instantiation statement; the inner block represents the design entity to which the instance is bound. Each is defined by a block statement." You do not understand what is the issue unless first time look at the example entity X is port (P1, P2: inout BIT); constant Delay: TIME := 1 ms; begin ... end entity X; architecture Y of X is begin ... end architecture Y; Spec then specifies that instantiation C: entity Work.X (Y) port map (P1 => S1, P2 => S2); is identical to C: block -- Instance block. begin X: block -- Design entity block. port (P1, P2: inout BIT); -- Entity interface ports. port map (P1 => S1, P2 => S2); constant Delay: TIME := 1 ms; -- Entity declarative item. begin ... end block X; end block C; I wonder, what is the purpose of doing that and why everybody, eg. Modelsim, behave as there is only one block? For instant, I always used to refer C.P1 instead of C.X.P1 in whatever tool I use as if there is only one hierarchical block. From newsfish@newsfish Thu Aug 1 00:31:05 2024 X-Received: by 10.182.33.162 with SMTP id s2mr25642104obi.17.1414923932338; Sun, 02 Nov 2014 02:25:32 -0800 (PST) X-Received: by 10.140.17.69 with SMTP id 63mr2024qgc.10.1414923932156; Sun, 02 Nov 2014 02:25:32 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4009452igd.0!news-out.google.com!u5ni19qab.1!nntp.google.com!i13no688834qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 2 Nov 2014 02:25:32 -0800 (PST) In-Reply-To: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.7.99.227; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 91.7.99.227 References: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c5523ff-d1a0-495b-abea-a41e4fa465db@googlegroups.com> Subject: Re: Finally some VHDL-2008 support in Xilinx Vivado From: capossio.leonardo@gmail.com Injection-Date: Sun, 02 Nov 2014 10:25:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3301 El lunes, 27 de octubre de 2014 20:59:21 UTC+1, Daniel Kho escribi=F3: > Just received word that Xilinx has implemented some features of VHDL-2008= in their Vivado tool. Some of you guys may be interested to try these new = compiler features. >=20 > I am sure to be trying them out: > http://www.xilinx.com/support/answers/62005.html >=20 > Cheers, dan Finally unconstrained element types. But it is still too early to use it in= any real design. Wish this was available two years ago. From newsfish@newsfish Thu Aug 1 00:31:06 2024 X-Received: by 10.224.156.69 with SMTP id v5mr225639qaw.1.1415041827866; Mon, 03 Nov 2014 11:10:27 -0800 (PST) X-Received: by 10.140.20.175 with SMTP id 44mr728195qgj.4.1415041827814; Mon, 03 Nov 2014 11:10:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!u7no2163561qaz.1!news-out.google.com!u5ni17qab.1!nntp.google.com!u7no2163560qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Nov 2014 11:10:27 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=31.214.45.148; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 31.214.45.148 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72206553-9d01-48e2-9d47-07d9eecd780f@googlegroups.com> Subject: Quartus II TCL or command line From: AA Injection-Date: Mon, 03 Nov 2014 19:10:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3302 Hi, how can I add vhdl files to quartus II project using TCL, or command line??? so far I can create project using Quartus_sh --tcl_eval, but I didn't find any tcl command to add a vhdl file to the project. Thank you, From newsfish@newsfish Thu Aug 1 00:31:06 2024 X-Received: by 10.66.222.135 with SMTP id qm7mr40040560pac.20.1415132400135; Tue, 04 Nov 2014 12:20:00 -0800 (PST) X-Received: by 10.50.20.198 with SMTP id p6mr306743ige.10.1415132399161; Tue, 04 Nov 2014 12:19:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no3878107igi.0!news-out.google.com!ks2ni7567igb.0!nntp.google.com!r10no3878087igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Nov 2014 12:19:58 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Subject: An English sentence? From: Weng Tianxiang Injection-Date: Tue, 04 Nov 2014 20:19:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3303 Hi, I am writing a paper now. I am not sure which English sentence is right in VHDL: signal A : std_logic; ... A <= '1'; 1. set A to '1'; -- I am now using. 2. set A equal to '1'; 3. set '1' to A; Thank you. Weng From newsfish@newsfish Thu Aug 1 00:31:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!news.astraweb.com!border5.a.newsrouter.astraweb.com!border2.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 04 Nov 2014 18:06:50 -0600 Date: Wed, 05 Nov 2014 00:06:50 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: An English sentence? References: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> In-Reply-To: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-ID: Lines: 33 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-9rPBO5n7j8ZZz2cZmnoqbRXS3vVkZQ2nHnnEanPK4xYmIPzIUN8GmttpuwlDcjDNP66WwmYrmH7AmW+!oT2Xm72vIMq6TBKvgtHXozu6WO6glC61SBVlsx2vuFNzmpd4iOQH9iesTdOVzVbidgaKdagq+EQ0!EFEOaeDI0h2URIbEMkdlBI8kNQ== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1675 Xref: news.eternal-september.org comp.lang.vhdl:3304 On 04/11/14 20:19, Weng Tianxiang wrote: > Hi, > > I am writing a paper now. I am not sure which English sentence is right in VHDL: > > signal A : std_logic; > > ... > > A <= '1'; > > 1. set A to '1'; -- I am now using. > 2. set A equal to '1'; > 3. set '1' to A; > > Thank you. > > Weng > Set A to '1' is fine, but I would probably say assign '1' to A or assign the value '1' to A simply because it is referred to as signal assignment in the standard, regards Alan -- Alan Fitch From newsfish@newsfish Thu Aug 1 00:31:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: An English sentence? Date: Wed, 05 Nov 2014 15:50:29 +0200 Organization: An impatient and LOUD arachnid Lines: 12 Message-ID: References: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Injection-Info: mx02.eternal-september.org; posting-host="e5afc5bc4c110b3af5789ef5c59a038f"; logging-data="24749"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1958TlQlkNHa103I5V/JR6I" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:mwQdvLl0gVT/ZDOiIShdX8a6NwY= sha1:MkB6LgtonqFETxN+Bw9nlYidEaM= Xref: news.eternal-september.org comp.lang.vhdl:3305 Alan Fitch writes: > Set A to '1' is fine, but I would probably say > > assign '1' to A > or > assign the value '1' to A > > simply because it is referred to as signal assignment in the standard, OTOH, if the paper discusses generated hardware rather than pure VHDL, then I'd prefer set. From newsfish@newsfish Thu Aug 1 00:31:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: An English sentence? Date: Wed, 05 Nov 2014 13:49:03 -0500 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Nov 2014 18:49:27 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14303"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/gpMPrUTFQT+rVgY2IEYfz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:YTeV313XA9Oinj4EQpigdmItDTc= Xref: news.eternal-september.org comp.lang.vhdl:3307 On 11/5/2014 8:50 AM, Anssi Saari wrote: > Alan Fitch writes: > >> Set A to '1' is fine, but I would probably say >> >> assign '1' to A >> or >> assign the value '1' to A >> >> simply because it is referred to as signal assignment in the standard, > > OTOH, if the paper discusses generated hardware rather than pure VHDL, > then I'd prefer set. I agree with both of you. -- Rick From newsfish@newsfish Thu Aug 1 00:31:07 2024 X-Received: by 10.68.212.169 with SMTP id nl9mr655098pbc.0.1415230039765; Wed, 05 Nov 2014 15:27:19 -0800 (PST) X-Received: by 10.50.4.36 with SMTP id h4mr387082igh.1.1415230039648; Wed, 05 Nov 2014 15:27:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!h15no6487452igd.0!news-out.google.com!c9ni6259igv.0!nntp.google.com!h15no6487442igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Nov 2014 15:27:18 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=220.255.96.166; posting-account=dAcMTAoAAAAThaIUTdpeJSARKG5Mzqlp NNTP-Posting-Host: 220.255.96.166 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Subject: VHDl - A little help please From: Kai Injection-Date: Wed, 05 Nov 2014 23:27:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3308 A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that implements such a system. Compile and verify the functionality of the program with appropriate test cases. How do I write the statement for this ? If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented I am able to write this in C and C++ programming but how do i that in VHDL? From newsfish@newsfish Thu Aug 1 00:31:08 2024 X-Received: by 10.182.120.8 with SMTP id ky8mr936212obb.14.1415234674794; Wed, 05 Nov 2014 16:44:34 -0800 (PST) X-Received: by 10.50.152.100 with SMTP id ux4mr453871igb.6.1415234674579; Wed, 05 Nov 2014 16:44:34 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no6517766igd.0!news-out.google.com!c9ni6262igv.0!nntp.google.com!r10no4401566igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Nov 2014 16:44:33 -0800 (PST) In-Reply-To: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: An English sentence? From: Weng Tianxiang Injection-Date: Thu, 06 Nov 2014 00:44:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 25 Xref: news.eternal-september.org comp.lang.vhdl:3309 On Tuesday, November 4, 2014 12:20:02 PM UTC-8, Weng Tianxiang wrote: > Hi, > > I am writing a paper now. I am not sure which English sentence is right in VHDL: > > signal A : std_logic; > > ... > > A <= '1'; > > 1. set A to '1'; -- I am now using. > 2. set A equal to '1'; > 3. set '1' to A; > > Thank you. > > Weng Alan, Anssi and rick, I am very glad that three of you gave my reply. I would like to do a great change in my paper to use "assign '1' to A". Thank you very much. Weng From newsfish@newsfish Thu Aug 1 00:31:08 2024 X-Received: by 10.70.61.33 with SMTP id m1mr1438170pdr.0.1415242579097; Wed, 05 Nov 2014 18:56:19 -0800 (PST) X-Received: by 10.140.94.212 with SMTP id g78mr25642qge.0.1415242578816; Wed, 05 Nov 2014 18:56:18 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6563431igd.0!news-out.google.com!u5ni26qab.1!nntp.google.com!u7no2739867qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Nov 2014 18:56:18 -0800 (PST) In-Reply-To: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <919c067a-74a8-43b2-91bb-64df7e866ab5@googlegroups.com> Subject: Re: VHDl - A little help please From: KJ Injection-Date: Thu, 06 Nov 2014 02:56:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3310 On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote: > A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input > CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When > COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase > further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that > implements such a system. Compile and verify the functionality of the program with appropriate > test cases. > > How do I write the statement for this ? > If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented > > I am able to write this in C and C++ programming but how do i that in VHDL? Post your code in C and then I'm sure someone will translate it into VHDL Kevin Jennings From newsfish@newsfish Thu Aug 1 00:31:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDl - A little help please Date: Wed, 05 Nov 2014 22:52:37 -0500 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 6 Nov 2014 03:53:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="26423"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/TM1cQQojdWG5b5Bzo4kXT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Cancel-Lock: sha1:v8/gL95+KoR5WDg3gpQtHgUhwMY= Xref: news.eternal-september.org comp.lang.vhdl:3311 On 11/5/2014 6:27 PM, Kai wrote: > A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input > CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When > COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase > further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that > implements such a system. Compile and verify the functionality of the program with appropriate > test cases. > > How do I write the statement for this ? > If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented > > I am able to write this in C and C++ programming but how do i that in VHDL? I'm old school. I think in terms of the logic. So I design the logic in my head as I go along and code the VHDL to describe the hardware. After all, HDL stands for hardware description language. Can you picture the logic you would need to implement the above requirements? -- Rick From newsfish@newsfish Thu Aug 1 00:31:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDl - A little help please Date: 6 Nov 2014 08:52:52 GMT Lines: 42 Message-ID: References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> X-Trace: individual.net I32pxh3iL+o7OaoRP6mfqAruF1RjrufuBPY5Fcn1daEEsco/8n X-Orig-Path: not-for-mail Cancel-Lock: sha1:HkU3pi7OhaZP3vqm9d82VsR5QBI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3312 Hi Kai, Kai wrote: > A system has a 3-bit input D_IN which is read in at every positive > going edge of a clock input CLK. If the current D_IN is greater than > the previous D_IN by at least 2, a 3-bit output COUNT is incremented. > If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When > COUNT reaches 6, the system will assert an output ALARM and the COUNT > will not increase further, till it is reset by giving 0s at D_IN for 3 > consecutive cycles. Write a VHDL program that implements such a > system. Compile and verify the functionality of the program with > appropriate test cases. First of all I'd suggest you post with an editor that limits the amount of columns to 78 chars since it eases the reading and increases the likelihood to get an answer. Forget about VHDL and think about the logic. Breakdown your 'specification' in semantic pieces: there are registers and combinatorial elements and you may easily spot them. COUNT is incremented when D_IN is greater than previous by 2 so you need to store the previous and the current value in order to compare them and trigger the condition for COUNT to increase. COUNT is another register since it needs to store information between events. You need to count how many times you have the condition that D_IN is 0 (here you go another counter). Once you have the elements you only need to put them together. I leave this up to you since you are learning VHDL and you should make an effort to get it done (no free lunch in here!). If you have problems with your implementation than post the code and I'm sure you'll find some help. Al p.s.: tell your professor that the specification is not clear and there's room for misunderstanding on the ALARM signal since it is not stated whether can be asynchronous or should be registerd and there's no condition for ALARM to be deasserted. You'll find out in your career that most of the issues are traced back in unclear specification of the interfaces! From newsfish@newsfish Thu Aug 1 00:31:09 2024 X-Received: by 10.42.194.204 with SMTP id dz12mr10339364icb.16.1415289358897; Thu, 06 Nov 2014 07:55:58 -0800 (PST) X-Received: by 10.140.21.49 with SMTP id 46mr16712qgk.30.1415289358762; Thu, 06 Nov 2014 07:55:58 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no4749167igi.0!news-out.google.com!u5ni27qab.1!nntp.google.com!i13no1729557qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Nov 2014 07:55:58 -0800 (PST) In-Reply-To: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=216.16.247.154; posting-account=uTTtcgoAAABPqu7825DzTx7-FRSU6_LI NNTP-Posting-Host: 216.16.247.154 References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13f665bd-aa4e-4c2e-82d9-053af49ba9c1@googlegroups.com> Subject: Re: VHDl - A little help please From: Anton Gunman Injection-Date: Thu, 06 Nov 2014 15:55:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3313 On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote: > A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input > CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When > COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase > further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that > implements such a system. Compile and verify the functionality of the program with appropriate > test cases. > > How do I write the statement for this ? > If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented > > I am able to write this in C and C++ programming but how do i that in VHDL? Hello, The code below was NOT TESTED, so it might have some errors. The purpose is just to demonstrate a way of implementing the requirements (I hope I understood them correctly). You will still need to write a nice testbench to test some of the cases :) Cheers, Anton. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_module is port ( clk : in std_logic; reset : in std_logic; din_i : in std_logic_vector(2 downto 0); count_o : out std_logic_vector(2 downto 0); alarm_o : out std_logic); end my_module; architecture rtl of my_module is -- Note: you can replace these '1d, 2d' with an array signal din_1d : std_logic_vector(2 downto 0) := (others => '0'); signal din_2d : std_logic_vector(2 downto 0) := (others => '0'); signal count : unsigned(2 downto 0) := (others => '0'); signal inc_count : std_logic := '0'; signal rst_count : std_logic := '0'; signal alarm : std_logic := '0'; begin -- rtl --------------------------------------------------------------------------- -- Delay pipes, used to save the previous value(s) --------------------------------------------------------------------------- delay_pipes : process (clk) begin if rising_edge(clk) then if reset = '1' then din_1d <= (others => '0'); din_2d <= (others => '0'); else din_1d <= unsigned(din_i); din_2d <= din_1d; end if; end if; end process delay_pipes; --------------------------------------------------------------------------- -- Count 'increment' -- * Check that current value is > than previous (to avoid wraparound) -- * Check that the difference is >= 2 -- Count and alarm 'reset' -- * Check that the data is zero for 3 consecutive clock cycles. --------------------------------------------------------------------------- inc_count <= '1' when (unsigned(din_i) > d) and ((unsigned(din_i) - din_1d) >= 2) else '0'; rst_count <= '1' when (din_i = "000" and din_1d = "000" and din_2d = "000") else '0'; counter : process (clk) begin if rising_edge(clk) then if reset = '1' then count <= (others => '0'); alarm <= '0'; else if rst_count = '1' then -- Reset the count and the alarm count <= (others => '0'); alarm <= '0'; elsif inc_count = '1' then if count < 6 then -- Saturate count at 6 count <= count + 1; else -- Set the alarm if count >= 6 alarm <= '1'; end if; end if; end if; end if; end process counter; count_o <= std_logic_vector(count); alarm_o <= alarm; end rtl; From newsfish@newsfish Thu Aug 1 00:31:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDl - A little help please Date: Thu, 06 Nov 2014 13:48:54 -0500 Organization: A noiseless patient Spider Lines: 115 Message-ID: References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> <13f665bd-aa4e-4c2e-82d9-053af49ba9c1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 6 Nov 2014 18:49:16 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="16786"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+C0o4EVQRf8CYUyuBcKBxn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <13f665bd-aa4e-4c2e-82d9-053af49ba9c1@googlegroups.com> Cancel-Lock: sha1:Xir77kwfJs94ecD5cRekXTyfhwY= Xref: news.eternal-september.org comp.lang.vhdl:3314 On 11/6/2014 10:55 AM, Anton Gunman wrote: > On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote: >> A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input >> CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output >> COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When >> COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase >> further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that >> implements such a system. Compile and verify the functionality of the program with appropriate >> test cases. >> >> How do I write the statement for this ? >> If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output >> COUNT is incremented >> >> I am able to write this in C and C++ programming but how do i that in VHDL? > > Hello, > > The code below was NOT TESTED, so it might have some errors. > The purpose is just to demonstrate a way of implementing the requirements (I hope I understood them correctly). > > You will still need to write a nice testbench to test some of the cases :) > > Cheers, > Anton. > > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity my_module is > port ( > clk : in std_logic; > reset : in std_logic; > din_i : in std_logic_vector(2 downto 0); > count_o : out std_logic_vector(2 downto 0); > alarm_o : out std_logic); > end my_module; > > architecture rtl of my_module is > -- Note: you can replace these '1d, 2d' with an array > signal din_1d : std_logic_vector(2 downto 0) := (others => '0'); > signal din_2d : std_logic_vector(2 downto 0) := (others => '0'); > signal count : unsigned(2 downto 0) := (others => '0'); > signal inc_count : std_logic := '0'; > signal rst_count : std_logic := '0'; > signal alarm : std_logic := '0'; > > begin -- rtl > > --------------------------------------------------------------------------- > -- Delay pipes, used to save the previous value(s) > --------------------------------------------------------------------------- > delay_pipes : process (clk) > begin > if rising_edge(clk) then > if reset = '1' then > din_1d <= (others => '0'); > din_2d <= (others => '0'); > else > din_1d <= unsigned(din_i); > din_2d <= din_1d; > end if; > end if; > end process delay_pipes; > > --------------------------------------------------------------------------- > -- Count 'increment' > -- * Check that current value is > than previous (to avoid wraparound) > -- * Check that the difference is >= 2 > -- Count and alarm 'reset' > -- * Check that the data is zero for 3 consecutive clock cycles. > --------------------------------------------------------------------------- > inc_count <= '1' when (unsigned(din_i) > d) and > ((unsigned(din_i) - din_1d) >= 2) else '0'; > rst_count <= '1' when (din_i = "000" and din_1d = "000" and > din_2d = "000") else '0'; > > counter : process (clk) > begin > if rising_edge(clk) then > if reset = '1' then > count <= (others => '0'); > alarm <= '0'; > else > if rst_count = '1' then > -- Reset the count and the alarm > count <= (others => '0'); > alarm <= '0'; > elsif inc_count = '1' then > if count < 6 then > -- Saturate count at 6 > count <= count + 1; > else > -- Set the alarm if count >= 6 > alarm <= '1'; > end if; > > end if; > end if; > end if; > end process counter; > > count_o <= std_logic_vector(count); > alarm_o <= alarm; > > end rtl; You do realize you are doing his homework, right? Or it may even be a test. -- Rick From newsfish@newsfish Thu Aug 1 00:31:10 2024 X-Received: by 10.52.138.175 with SMTP id qr15mr6890762vdb.4.1415328137002; Thu, 06 Nov 2014 18:42:17 -0800 (PST) X-Received: by 10.50.77.6 with SMTP id o6mr7878igw.8.1415328136850; Thu, 06 Nov 2014 18:42:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i13no1849235qae.0!news-out.google.com!ks2ni13482igb.0!nntp.google.com!h15no7253795igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Nov 2014 18:42:16 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=49.156.53.254; posting-account=tKNq2QoAAADH5KHs7Y-Di-cjhMZRhRlv NNTP-Posting-Host: 49.156.53.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2326e3ef-907a-41d5-881d-756ced5009dd@googlegroups.com> Subject: Floating point in VHDL From: Dai Tran Van Injection-Date: Fri, 07 Nov 2014 02:42:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:3315 Hi everyone. I working with foating point, and i have problem with multipile maxtrix, vetor in foating.. this i's my project to go out shool on time. help me. From newsfish@newsfish Thu Aug 1 00:31:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Quartus II TCL or command line Date: Fri, 07 Nov 2014 06:20:47 +0100 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <72206553-9d01-48e2-9d47-07d9eecd780f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 7 Nov 2014 05:20:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="dcece3cc2db339bbea1130eb9b01bab7"; logging-data="8772"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hSYgzZ9X80ncNlHrkWSXB" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <72206553-9d01-48e2-9d47-07d9eecd780f@googlegroups.com> Cancel-Lock: sha1:FmMv39WpRMQK6lF69gp+2e+yTO0= Xref: news.eternal-september.org comp.lang.vhdl:3316 > how can I add vhdl files to quartus II project using TCL, or command line??? > > so far I can create project using Quartus_sh --tcl_eval, but I didn't find any tcl command to add a vhdl file to the project. Does "quartus_sh --qhelp" print all avalible commands? Synplify and Vivado knows the "add_file" commad. Bart Fox From newsfish@newsfish Thu Aug 1 00:31:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Quartus II TCL or command line Date: Fri, 07 Nov 2014 14:58:00 +0200 Organization: An impatient and LOUD arachnid Lines: 13 Message-ID: References: <72206553-9d01-48e2-9d47-07d9eecd780f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Injection-Info: mx02.eternal-september.org; posting-host="e5afc5bc4c110b3af5789ef5c59a038f"; logging-data="30701"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18J+CgkNOGZpfQhmt5XagA9" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:9TZ6g1AJ/NNkArlF+eh9fWcFggQ= sha1:iARI0bZkNCPJeef92FQ0QmDKzRg= Xref: news.eternal-september.org comp.lang.vhdl:3317 AA writes: > Hi, > how can I add vhdl files to quartus II project using TCL, or command line??? > > so far I can create project using Quartus_sh --tcl_eval, but I didn't find any tcl command to add a vhdl file to the project. > > Thank you, It's the same non-intuitive command you probably already have in your .qsf files, like this: set_global_assignment -name VHDL_FILE whatever.vhdl From newsfish@newsfish Thu Aug 1 00:31:11 2024 X-Received: by 10.182.120.99 with SMTP id lb3mr49181613obb.10.1415978963029; Fri, 14 Nov 2014 07:29:23 -0800 (PST) X-Received: by 10.140.93.199 with SMTP id d65mr7946qge.20.1415978963003; Fri, 14 Nov 2014 07:29:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!r10no2710542igi.0!news-out.google.com!m4ni192qag.1!nntp.google.com!u7no1650465qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Nov 2014 07:29:22 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.178.158.89; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.178.158.89 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Compile OK but simulation fails From: Marios Barlas Injection-Date: Fri, 14 Nov 2014 15:29:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3105 X-Received-Body-CRC: 2274314540 Xref: news.eternal-september.org comp.lang.vhdl:3318 Hello every1, I am new to VHDL just working on my first code. I am trying to realize an sqrt(x) function in a sequential wax and simulate it with Modelsim. My code looks like this : use ieee.numeric_std.ALL; entity sqroot is generic (constant NBITS : natural := 8); --design implementation port ( signal arg : in std_logic_vector(NBITS-1 downto 0); signal roundup : in std_logic := '0'; --determine if roundup is done or not signal sqroot : out std_logic_vector(NBITS/2 downto 0)); end entity sqroot; architecture rtl of sqroot is use ieee.std_logic_1164.all; use ieee.numeric_std.ALL; --Internal signal definitions signal delta : unsigned(NBITS-1 downto 0) := (0 => '1', others => '0'); begin process( arg, roundup ) --Internal variable definitions variable delta_int : integer := 1; variable sqroot_int : integer :=0; variable res_int : integer := to_integer(unsigned(arg)); begin delta <= delta sll (NBITS-2); -- shifted // temp = delta^(NBITS-2) delta_int := to_integer(delta); while (delta_int >= 1) loop if ( (sqroot_int + delta_int) <= res_int ) then res_int := res_int -(sqroot_int + delta_int); sqroot_int := sqroot_int + 2*delta_int; end if; sqroot_int := sqroot_int/2; delta_int := delta_int/4; end loop; if ( (roundup = '1') and (res_int > sqroot_int) ) then sqroot_int := sqroot_int + 1; end if; sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); end process; end architecture rtl; I end up with an error on the sqroot line right before the end : sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); fatal error simulation terminated. I don't really understand what that error is associated to. Any1 has a hint ? Thanks in advance Mario From newsfish@newsfish Thu Aug 1 00:31:11 2024 X-Received: by 10.68.125.134 with SMTP id mq6mr19314832pbb.7.1415996577857; Fri, 14 Nov 2014 12:22:57 -0800 (PST) X-Received: by 10.140.37.83 with SMTP id q77mr70547qgq.7.1415996577808; Fri, 14 Nov 2014 12:22:57 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no325638igd.0!news-out.google.com!m4ni192qag.1!nntp.google.com!u7no1714181qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Nov 2014 12:22:57 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.178.158.89; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.178.158.89 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: problem with sll operator From: Marios Barlas Injection-Date: Fri, 14 Nov 2014 20:22:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3319 Hello, I am facing a pretty wierd error as regards an operation which is pretty cr= utial for my code.=20 I am trying to do a left shift operation on an unsigned vector. My NBITS is= defined generically as natural and my delta vector is unsigned. All compil= es well but when i=E0m doing the simulation my delta_shifted receives X val= ues. for me that seems to suggest that the sll operation is not performed. = Any1 has an idea as to where the problem could be ? library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.ALL;=20 entity sqroot_comb is generic (constant NBITS : natural :=3D 8); --design implementation port ( signal arg : in std_logic_vector(NBITS-1 downto 0); signal roundup : in std_logic :=3D '0'; --determine if roundup is done = or not signal sqroot : out std_logic_vector(NBITS/2 downto 0)); end entity sqroot_comb; =20 architecture rtl of sqroot_comb is use ieee.std_logic_1164.all; use ieee.numeric_std.ALL;=20 =20 --Internal signal definitions signal delta : unsigned(NBITS-1 downto 0);=20 signal delta_shifted : unsigned(NBITS-1 downto 0);=20 signal delta_shifted_prev : unsigned(NBITS-1 downto 0); signal res : unsigned(NBITS-1 downto 0); signal res_prev : unsigned(NBITS-1 downto 0); signal sqroot_temp_prev : unsigned(NBITS-1 downto 0); signal sqroot_temp : unsigned(NBITS-1 downto 0); =20 --Signal Assignments =20 =20 begin =20 =20 delta <=3D to_unsigned(2**(NBITS-2),delta'length); sqroot_temp <=3D to_unsigned(0,delta'length); sqroot_temp_prev <=3D to_unsigned(0,delta'length); delta_shifted_prev <=3D to_unsigned(0,delta'length); res_prev <=3D to_unsigned(0,delta'length); =20 delta_shifted <=3D (delta sll NBITS-2); -- shifted // temp =3D delta^(N= BITS-2) =20 res <=3D unsigned(arg);=20 =20 process( arg, roundup ) =20 --Internal variable definitions --variable delta_int : integer :=3D 1; --variable sqroot_int : integer :=3D0; --variable res_int : integer :=3D to_integer(unsigned(arg)); =20 begin=20 for i in 0 to 2*NBITS-1 loop if (delta_shifted >=3D 1) then if ( (sqroot_temp + delta_shifted) <=3D res ) then res <=3D res -(sqroot_temp + delta_shifted); sqroot_temp <=3D sqroot_temp + 2*delta_shifted; else sqroot_temp <=3D sqroot_temp_prev; res <=3D res_prev; delta_shifted <=3D delta_shifted_prev; end if; end if; =20 sqroot_temp <=3D sqroot_temp/2; delta_shifted <=3D delta_shifted/4; =20 --Update previous values of sqroot and residual sqroot_temp_prev <=3D sqroot_temp; res_prev <=3D res; =20 end loop; =20 if ( (roundup =3D '1') and (res > sqroot_temp) ) then sqroot_temp <=3D sqroot_temp + 1; else=20 sqroot_temp <=3D sqroot_temp_prev; end if; =20 =20 sqroot <=3D std_logic_vector(resize( sqroot_temp,sqroot'length ))= ; =20 end process;=20 =20 end architecture rtl; From newsfish@newsfish Thu Aug 1 00:31:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator Date: Fri, 14 Nov 2014 15:42:18 -0500 Organization: Alacron, Inc. Lines: 92 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Fri, 14 Nov 2014 20:43:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="27712"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18lbMnyTqNtrMP24ECkOZ5kp0yOOCRSGj0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:pBVlHIrpvz9XR/t5JIzDIBU/wRM= Xref: news.eternal-september.org comp.lang.vhdl:3320 Marios Barlas wrote: > Hello, > > I am facing a pretty wierd error as regards an operation which is pretty crutial for my code. > > I am trying to do a left shift operation on an unsigned vector. My NBITS is defined generically as natural and my delta vector is unsigned. All compiles well but when im doing the simulation my delta_shifted receives X values. for me that seems to suggest that the sll operation is not performed. Any1 has an idea as to where the problem could be ? > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.ALL; > > entity sqroot_comb is > generic (constant NBITS : natural := 8); --design implementation > port ( > signal arg : in std_logic_vector(NBITS-1 downto 0); > signal roundup : in std_logic := '0'; --determine if roundup is done or not > signal sqroot : out std_logic_vector(NBITS/2 downto 0)); > end entity sqroot_comb; > > architecture rtl of sqroot_comb is > use ieee.std_logic_1164.all; > use ieee.numeric_std.ALL; > > --Internal signal definitions > signal delta : unsigned(NBITS-1 downto 0); > signal delta_shifted : unsigned(NBITS-1 downto 0); > signal delta_shifted_prev : unsigned(NBITS-1 downto 0); > signal res : unsigned(NBITS-1 downto 0); > signal res_prev : unsigned(NBITS-1 downto 0); > signal sqroot_temp_prev : unsigned(NBITS-1 downto 0); > signal sqroot_temp : unsigned(NBITS-1 downto 0); > > --Signal Assignments > > begin > > delta <= to_unsigned(2**(NBITS-2),delta'length); > sqroot_temp <= to_unsigned(0,delta'length); > sqroot_temp_prev <= to_unsigned(0,delta'length); > delta_shifted_prev <= to_unsigned(0,delta'length); > res_prev <= to_unsigned(0,delta'length); > > delta_shifted <= (delta sll NBITS-2); -- shifted // temp = delta^(NBITS-2) > res <= unsigned(arg); > > process( arg, roundup ) > > --Internal variable definitions > --variable delta_int : integer := 1; > --variable sqroot_int : integer :=0; > --variable res_int : integer := to_integer(unsigned(arg)); > > begin > > for i in 0 to 2*NBITS-1 loop > if (delta_shifted >= 1) then > if ( (sqroot_temp + delta_shifted) <= res ) then > res <= res -(sqroot_temp + delta_shifted); > sqroot_temp <= sqroot_temp + 2*delta_shifted; > else > sqroot_temp <= sqroot_temp_prev; > res <= res_prev; > delta_shifted <= delta_shifted_prev; > end if; > end if; > > sqroot_temp <= sqroot_temp/2; > delta_shifted <= delta_shifted/4; > > --Update previous values of sqroot and residual > sqroot_temp_prev <= sqroot_temp; > res_prev <= res; > > end loop; > > if ( (roundup = '1') and (res > sqroot_temp) ) then > sqroot_temp <= sqroot_temp + 1; > else > sqroot_temp <= sqroot_temp_prev; > end if; > > sqroot <= std_logic_vector(resize( sqroot_temp,sqroot'length )); > > end process; > > end architecture rtl; The first thing I noticed is that delta_shifted doesn't have enough bits to represent the shifted value. Maybe that has something to do with it? -- Gabor From newsfish@newsfish Thu Aug 1 00:31:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed4-a.proxad.net!nnrp1-2.free.fr!not-for-mail Date: Fri, 14 Nov 2014 22:43:20 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator References: In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 15 Message-ID: <54667774$0$2070$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 14 Nov 2014 22:43:16 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1416001396 news-4.free.fr 2070 88.185.146.198:1164 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3321 Hello Le 14/11/2014 21:22, Marios Barlas a écrit : > Hello, > > I am facing a pretty wierd error as regards an operation which is pretty crutial for my code. > > I am trying to do a left shift operation on an unsigned vector. My NBITS is defined generically as natural and my delta vector is unsigned. All compiles well but when iàm doing the simulation my delta_shifted receives X values. for me that seems to suggest that the sll operation is not performed. Any1 has an idea as to where the problem could be ? You have a conflict on delta_shifted. You have a concurrent assignment (6th assignment after the architecture's "begin") and you assign values to it in the process. You're from a computer programming background, aren't you ? Nicolas From newsfish@newsfish Thu Aug 1 00:31:12 2024 X-Received: by 10.236.98.71 with SMTP id u47mr51581430yhf.30.1416004825937; Fri, 14 Nov 2014 14:40:25 -0800 (PST) X-Received: by 10.140.102.117 with SMTP id v108mr36038qge.36.1416004825909; Fri, 14 Nov 2014 14:40:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i13no1739899qae.0!news-out.google.com!m4ni193qag.1!nntp.google.com!u7no1739321qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Nov 2014 14:40:25 -0800 (PST) In-Reply-To: <54667774$0$2070$426a34cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.254.155; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.179.254.155 References: <54667774$0$2070$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: problem with sll operator From: Marios Barlas Injection-Date: Fri, 14 Nov 2014 22:40:25 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3322 =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, 14 =CE= =9D=CE=BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:43:19 =CE=BC.= =CE=BC. UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicolas Ma= tringe =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > Hello >=20 > Le 14/11/2014 21:22, Marios Barlas a =C3=A9crit : > > Hello, > > > > I am facing a pretty wierd error as regards an operation which is prett= y crutial for my code. > > > > I am trying to do a left shift operation on an unsigned vector. My NBIT= S is defined generically as natural and my delta vector is unsigned. All co= mpiles well but when i=C3=A0m doing the simulation my delta_shifted receive= s X values. for me that seems to suggest that the sll operation is not perf= ormed. Any1 has an idea as to where the problem could be ? >=20 > You have a conflict on delta_shifted. You have a concurrent assignment=20 > (6th assignment after the architecture's "begin") and you assign values= =20 > to it in the process. > You're from a computer programming background, aren't you ? >=20 > Nicolas Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a 2 y= ears master's in nanotechnology the last semester of which is in microelect= ronics. As a result us stupid physics people lack a good deal of background= that others have for granted. This is my first bit of code in VHDL. Apolog= izing for my ignorance in advance, I am guessing you are referring to=20 delta_shifted <=3D delta sll NBITS-1 but this is exactly what I would like to do, shift the bits of my vector re= presentation to the left. I was under the impression that sll would basical= ly shift the bits to the left adding zeros on the right-most columns. Also = the comment above seems logical, I probably need more bits so that I won't = lose information, right ? From newsfish@newsfish Thu Aug 1 00:31:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator Date: Sat, 15 Nov 2014 11:59:22 +0000 (UTC) Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <54667774$0$2070$426a34cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 15 Nov 2014 11:59:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="19791"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/K2JAHOdrhKEo+Y2Wq+k76q9ETMJA48Ck=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:mFCmf/CYao+KyQWRxo2jhmkMaO4= Xref: news.eternal-september.org comp.lang.vhdl:3323 On Fri, 14 Nov 2014 14:40:25 -0800, Marios Barlas wrote: > Τη Παρασκευή, 14 Νοεμβρίου 2014 10:43:19 μ.μ. UTC+1, ο χρήστης Nicolas > Matringe έγραψε: >> Hello >> >> Le 14/11/2014 21:22, Marios Barlas a écrit : >> > Hello, >> > >> > but when iàm doing the simulation my >> > delta_shifted receives X values. >> You have a conflict on delta_shifted. You have a concurrent assignment >> (6th assignment after the architecture's "begin") and you assign values >> to it in the process. > Apologizing for my ignorance in advance, I am guessing you are > referring to > > delta_shifted <= delta sll NBITS-1 > > but this is exactly what I would like to do, shift the bits of my vector > representation to the left. No, you missed Nicolas' point. You have created two pieces of circuitry driving delta_shifted - one is the process, the other is the concurrent statement delta_shifted <= (delta sll NBITS-2); -- shifted // temp = These two circuits have their outputs short circuited to each other, and that short circuit creates the Xes, not the shift operation itself. The usual solution is to decide which circuit should be permitted to drive delta_shifted, and eliminate the other. (Usually, keep the process, and move the other statement to an appropriate part of the process.) - Brian From newsfish@newsfish Thu Aug 1 00:31:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Compile OK but simulation fails Date: Sat, 15 Nov 2014 12:03:39 +0000 (UTC) Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 15 Nov 2014 12:03:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="19791"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+7JFAmtTHe6Yy92Ia7azW10sSbg8NAlvc=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:++44N+ZJeo9pUvB3wLiACl8+McI= Xref: news.eternal-september.org comp.lang.vhdl:3324 On Fri, 14 Nov 2014 07:29:22 -0800, Marios Barlas wrote: > Hello every1, > > I am new to VHDL just working on my first code. I am trying to realize > an sqrt(x) function in a sequential wax and simulate it with Modelsim. > > My code looks like this : > > use ieee.numeric_std.ALL; > > entity sqroot is > generic (constant NBITS : natural := 8); --design implementation port > ( > signal sqroot : out std_logic_vector(NBITS/2 downto 0)); > end entity sqroot; > > I end up with an error on the sqroot line right before the end : > > sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); You have probably already solved this, but for completeness : there is both an entity and signal with the same name sqroot, so some expressions like sqroot'length may be ambiguous... - Brian From newsfish@newsfish Thu Aug 1 00:31:13 2024 X-Received: by 10.224.120.71 with SMTP id c7mr56100686qar.4.1416068296989; Sat, 15 Nov 2014 08:18:16 -0800 (PST) X-Received: by 10.140.37.83 with SMTP id q77mr849qgq.7.1416068296945; Sat, 15 Nov 2014 08:18:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w8no24792qac.0!news-out.google.com!w7ni0qay.0!nntp.google.com!w8no24789qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 15 Nov 2014 08:18:16 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.183.75; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.179.183.75 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9041a195-e199-4756-8890-21612a7244bc@googlegroups.com> Subject: Re: Compile OK but simulation fails From: Marios Barlas Injection-Date: Sat, 15 Nov 2014 16:18:16 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3325 =CE=A4=CE=B7 =CE=A3=CE=AC=CE=B2=CE=B2=CE=B1=CF=84=CE=BF, 15 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 1:03:52 =CE=BC.=CE=BC. UTC+1, = =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Brian Drummond =CE=AD=CE= =B3=CF=81=CE=B1=CF=88=CE=B5: > On Fri, 14 Nov 2014 07:29:22 -0800, Marios Barlas wrote: >=20 > > Hello every1, > >=20 > > I am new to VHDL just working on my first code. I am trying to realize > > an sqrt(x) function in a sequential wax and simulate it with Modelsim. > >=20 > > My code looks like this : > >=20 > > use ieee.numeric_std.ALL; > >=20 > > entity sqroot is > > generic (constant NBITS : natural :=3D 8); --design implementation p= ort > > ( > > signal sqroot : out std_logic_vector(NBITS/2 downto 0)); > > end entity sqroot; > > =20 >=20 > > I end up with an error on the sqroot line right before the end : > >=20 > > sqroot <=3D std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); >=20 > You have probably already solved this, but for completeness : there is=20 > both an entity and signal with the same name sqroot, so some expressions= =20 > like sqroot'length may be ambiguous... >=20 > - Brian Thanks for the answer Brian! Yes I resolved it, I'm sorry for the stupid qu= estions of a rookie but newsgroups are in my opinion the best way to ask ex= perienced people.=20 With appreciation, Marios Barlas From newsfish@newsfish Thu Aug 1 00:31:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp1-1.free.fr!not-for-mail Date: Sat, 15 Nov 2014 22:50:11 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator References: <54667774$0$2070$426a34cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 28 Message-ID: <5467ca8f$0$2908$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 15 Nov 2014 22:50:07 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1416088207 news-1.free.fr 2908 88.185.146.198:1201 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3326 Le 14/11/2014 23:40, Marios Barlas a écrit : > Τη Παρασκευή, 14 Νοεμβρίου 2014 10:43:19 μ.μ. UTC+1, ο χρήστης Nicolas Matringe έγραψε: [...] >> You're from a computer programming background, aren't you ? > Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a 2 years master's in nanotechnology the last semester of which is in microelectronics. As a result us stupid physics people lack a good deal of background that others have for granted. This is my first bit of code in VHDL. Sorry for my wrong guess, then. You wrote your VHDL like you'd write a program in C for example. It doesn't work like that. VHDL is a description language, not a programming language. It is like a schematics, except it is in text form. Concurrent expressions (i.e. that are outside of processes) are independent blocks in your schematics. This also means that their order in the code doesn't matter at all. As Brian explained, concurrently assigning something to a signal is like connecting the output of a logic function to this signal. Concurrently assigning several times to the same signal is connecting several outputs together. You usually don't want to do that (this causes your Xs in simulation) You seem to assume your code is executed from top to bottom. It is not. It is not even executed, since VHDL is not a programming language. What you want is a block that takes a number and, after several iterations, outputs its square root, am I right ? So you want to initialize some internal signals or variables then step by step compute the square root and finally output the result. So you need some simple sequencer (a counter will do), and a clock to make it run. Nicolas From newsfish@newsfish Thu Aug 1 00:31:13 2024 X-Received: by 10.67.16.99 with SMTP id fv3mr58170592pad.5.1416091090619; Sat, 15 Nov 2014 14:38:10 -0800 (PST) X-Received: by 10.50.36.9 with SMTP id m9mr138570igj.2.1416091090503; Sat, 15 Nov 2014 14:38:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no907991igd.0!news-out.google.com!ks2ni20433igb.0!nntp.google.com!r10no3153126igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 15 Nov 2014 14:38:10 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8d5e24fd-79a6-4a17-a78e-e8dd872b721a@googlegroups.com> Subject: Re: Compile OK but simulation fails From: diogratia@gmail.com Injection-Date: Sat, 15 Nov 2014 22:38:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3327 On Saturday, November 15, 2014 4:29:26 AM UTC+13, Marios Barlas wrote: > My code looks like this : > > use ieee.numeric_std.ALL; > > > I end up with an error on the sqroot line right before the end : > > sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); The to_unsigned function found in package numeric_std expects a natural. Passing it a negative value would be erroneous. function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is variable RESULT: UNSIGNED(SIZE-1 downto 0); variable I_VAL: NATURAL := ARG; The variable I_VAL (and RESULT) are dynamically elaborated. Assigning a negative ARG would fail. The signature for TO_UNSIGNED allows an integer (a natural is a constrained integer, a subtype of the type integer). That would speak to a an algorithm implementation issue. You might consider adding an integer signal to receive sq_root_int, and comment out the above statement so you can see what's going on. It might help for others to know what your input was for the failed case (arg, roundup). From newsfish@newsfish Thu Aug 1 00:31:14 2024 X-Received: by 10.68.228.164 with SMTP id sj4mr32653568pbc.8.1416131081280; Sun, 16 Nov 2014 01:44:41 -0800 (PST) X-Received: by 10.140.37.83 with SMTP id q77mr1723qgq.7.1416131081021; Sun, 16 Nov 2014 01:44:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1135444igd.0!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no173043qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 01:44:40 -0800 (PST) In-Reply-To: <5467ca8f$0$2908$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.254.48; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.179.254.48 References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> Subject: Re: problem with sll operator From: Marios Barlas Injection-Date: Sun, 16 Nov 2014 09:44:41 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3328 =CE=A4=CE=B7 =CE=A3=CE=AC=CE=B2=CE=B2=CE=B1=CF=84=CE=BF, 15 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:50:10 =CE=BC.=CE=BC. UTC+1,= =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicolas Matringe =CE=AD= =CE=B3=CF=81=CE=B1=CF=88=CE=B5: > Le 14/11/2014 23:40, Marios Barlas a =C3=A9crit : > > =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, 14= =CE=9D=CE=BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:43:19 =CE= =BC.=CE=BC. UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicola= s Matringe =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > [...] > >> You're from a computer programming background, aren't you ? > > Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a= 2 years master's in nanotechnology the last semester of which is in microe= lectronics. As a result us stupid physics people lack a good deal of backgr= ound that others have for granted. This is my first bit of code in VHDL. >=20 > Sorry for my wrong guess, then. You wrote your VHDL like you'd write a=20 > program in C for example. It doesn't work like that. >=20 > VHDL is a description language, not a programming language. It is like a= =20 > schematics, except it is in text form. Concurrent expressions (i.e. that= =20 > are outside of processes) are independent blocks in your schematics.=20 > This also means that their order in the code doesn't matter at all. > As Brian explained, concurrently assigning something to a signal is like= =20 > connecting the output of a logic function to this signal. Concurrently=20 > assigning several times to the same signal is connecting several outputs= =20 > together. You usually don't want to do that (this causes your Xs in=20 > simulation) > You seem to assume your code is executed from top to bottom. It is not.= =20 > It is not even executed, since VHDL is not a programming language. What= =20 > you want is a block that takes a number and, after several iterations,=20 > outputs its square root, am I right ? So you want to initialize some=20 > internal signals or variables then step by step compute the square root= =20 > and finally output the result. So you need some simple sequencer (a=20 > counter will do), and a clock to make it run. >=20 > Nicolas Thanks for the reply Nicolas. Finally I wrote my code in dataflow using sta= ges and it works perfectly. But I'll write it again with a process and cloc= k! thanks for your feedback ! From newsfish@newsfish Thu Aug 1 00:31:14 2024 X-Received: by 10.52.76.227 with SMTP id n3mr61852216vdw.9.1416153107365; Sun, 16 Nov 2014 07:51:47 -0800 (PST) X-Received: by 10.140.17.69 with SMTP id 63mr4283qgc.10.1416153107305; Sun, 16 Nov 2014 07:51:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!u7no2077365qaz.1!news-out.google.com!m4ni197qag.1!nntp.google.com!u7no2077363qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 07:51:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.178.158.91; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.178.158.91 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Subject: Warning interpretation ? From: Marios Barlas Injection-Date: Sun, 16 Nov 2014 15:51:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2215 X-Received-Body-CRC: 2205117604 Xref: news.eternal-september.org comp.lang.vhdl:3329 Hello, I am getting a warning on my code like : # ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE # Time: 0 ns Iteration: 0 Region: /sqroot_comb_tb/DUV/STAGES(3) # ** Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE ********************************************* # ** Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE # Time: 0 ns Iteration: 4 Region: /sqroot_comb_tb/DUV/STAGES(3) My code implements the calculation of an integer square root in 4 stages in dataflow. It doesn't seem to have a negative effect on the computation or on the synthesis phase. I am using Modelsim for coding/simulation and Synopsis for synthesis. I suspect it comes from the fact that I introduce an array of vectors like this : type r_size is array (0 to NBITS/2) of unsigned(NBITS-1 downto 0); signal sqroot2 : r_size; signal delta : r_size; signal res : r_size; and I initialize only the 1st element res(0) <= unsigned(arg); with my input vector. In the algorithm however I have an assignment like : res(i+1) <= res(i); Can I circumvent the problem or should I just leave it like that? Thanks in advance! Marios Barlas From newsfish@newsfish Thu Aug 1 00:31:14 2024 X-Received: by 10.182.230.200 with SMTP id ta8mr65704819obc.11.1416167105143; Sun, 16 Nov 2014 11:45:05 -0800 (PST) X-Received: by 10.50.124.8 with SMTP id me8mr222554igb.3.1416167105011; Sun, 16 Nov 2014 11:45:05 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no155528igb.0!news-out.google.com!c9ni14081igv.0!nntp.google.com!h15no1451458igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 11:45:04 -0800 (PST) In-Reply-To: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5081dfd4-567a-47d5-91cc-be542b8370ba@googlegroups.com> Subject: Re: Warning interpretation ? From: Jim Lewis Injection-Date: Sun, 16 Nov 2014 19:45:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3330 Hi Marios, At startup all std_logic family has a 'U' by default. When the math functions, such as relationals (>=, <=, ...) see a 'U' (or string of them), they return FALSE. As long as this is happening before your circuit becomes active, it is ok. If it is happening later in simulation, you need to research why it is getting a 'U'. Cheers, Jim From newsfish@newsfish Thu Aug 1 00:31:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator Date: Sun, 16 Nov 2014 14:59:36 -0500 Organization: A noiseless patient Spider Lines: 51 Message-ID: References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Sun, 16 Nov 2014 19:59:58 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25157"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+m+Onem7AXRIY0+K/QMMsg" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> Cancel-Lock: sha1:oSWcbyWbegjVw6AmDrRr4Jv9/s0= Xref: news.eternal-september.org comp.lang.vhdl:3331 On 11/16/2014 4:44 AM, Marios Barlas wrote: > Τη Σάββατο, 15 Νοεμβρίου 2014 10:50:10 μ.μ. UTC+1, ο χρήστης Nicolas Matringe έγραψε: >> Le 14/11/2014 23:40, Marios Barlas a écrit : >>> Τη Παρασκευή, 14 Νοεμβρίου 2014 10:43:19 μ.μ. UTC+1, ο χρήστης Nicolas Matringe έγραψε: >> [...] >>>> You're from a computer programming background, aren't you ? >>> Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a 2 years master's in nanotechnology the last semester of which is in microelectronics. As a result us stupid physics people lack a good deal of background that others have for granted. This is my first bit of code in VHDL. >> >> Sorry for my wrong guess, then. You wrote your VHDL like you'd write a >> program in C for example. It doesn't work like that. >> >> VHDL is a description language, not a programming language. It is like a >> schematics, except it is in text form. Concurrent expressions (i.e. that >> are outside of processes) are independent blocks in your schematics. >> This also means that their order in the code doesn't matter at all. >> As Brian explained, concurrently assigning something to a signal is like >> connecting the output of a logic function to this signal. Concurrently >> assigning several times to the same signal is connecting several outputs >> together. You usually don't want to do that (this causes your Xs in >> simulation) >> You seem to assume your code is executed from top to bottom. It is not. >> It is not even executed, since VHDL is not a programming language. What >> you want is a block that takes a number and, after several iterations, >> outputs its square root, am I right ? So you want to initialize some >> internal signals or variables then step by step compute the square root >> and finally output the result. So you need some simple sequencer (a >> counter will do), and a clock to make it run. >> >> Nicolas > > Thanks for the reply Nicolas. Finally I wrote my code in dataflow using stages and it works perfectly. But I'll write it again with a process and clock! thanks for your feedback ! I'm curious about the course where you are learning VHDL. I remember about a million years ago when I was in college that I took a my first computer programming course. It was one part of six in a lab course in chemistry. I believe it was just two weeks. I now know they were doing their students a huge disservice by giving them such a limited amount of training and then releasing them into the world to write their own programs. I'm wondering if you are learning VHDL in a similar manner. VHDL is not a terrible language to learn, but any HDL is a bit different from computer programming in that they are inherently parallel rather than sequential. Computer programming languages come naturally because they are sequential reading the same as a recipe. HLDs are describing the functionality of hardware with it working in parallel. So there are different rules to it than you may be used to in software. -- Rick From newsfish@newsfish Thu Aug 1 00:31:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: Sun, 16 Nov 2014 15:08:23 -0500 Organization: A noiseless patient Spider Lines: 53 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 16 Nov 2014 20:08:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="27671"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zI/QB4CY9V8UYJl+B8AeV" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Cancel-Lock: sha1:oWYyXDKsE/iZ3wsfVkPmiPCS1HU= Xref: news.eternal-september.org comp.lang.vhdl:3332 On 11/16/2014 10:51 AM, Marios Barlas wrote: > Hello, > > I am getting a warning on my code like : > # ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE > # Time: 0 ns Iteration: 0 Region: /sqroot_comb_tb/DUV/STAGES(3) > # ** Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE > > ********************************************* > # ** Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE > # Time: 0 ns Iteration: 4 Region: /sqroot_comb_tb/DUV/STAGES(3) > > My code implements the calculation of an integer square root in 4 stages in dataflow. It doesn't seem to have a negative effect on the computation or on the synthesis phase. I am using Modelsim for coding/simulation and Synopsis for synthesis. > > I suspect it comes from the fact that I introduce an array of vectors like this : > type r_size is array (0 to NBITS/2) of unsigned(NBITS-1 downto 0); > signal sqroot2 : r_size; > signal delta : r_size; > signal res : r_size; > > and I initialize only the 1st element > > res(0) <= unsigned(arg); > > with my input vector. > > In the algorithm however I have an assignment like : > > res(i+1) <= res(i); > > Can I circumvent the problem or should I just leave it like that? This is like exploring the cold dusty areas of my mind. The problems you are having are ones I had a long time ago and have learned to simply step around. lol If I remember correctly, this warning is because the comparison operators >= and <= are seeing an input which is not all '1's and '0's (and possibly 'H's and 'L's). While it is not likely of consequence at time 0 you can easily code around it by making sure your signals and variables are initialized. Your assignment res(i+1) <= res(i); is fine assuming you start with an initialized value. It is the comparisons that are biting you. I recommend that you fix your code to get rid of warnings. Otherwise you become inured to them and eventually they will cause you to miss a valid warning that you need to pay attention to. Just initialize the full array to something that isn't a letter... ;) -- Rick From newsfish@newsfish Thu Aug 1 00:31:15 2024 X-Received: by 10.66.246.109 with SMTP id xv13mr62886936pac.15.1416171374476; Sun, 16 Nov 2014 12:56:14 -0800 (PST) X-Received: by 10.140.101.227 with SMTP id u90mr1425qge.18.1416171374426; Sun, 16 Nov 2014 12:56:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1493598igd.0!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no304804qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 12:56:14 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.70.30.51; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 195.70.30.51 References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: problem with sll operator From: Marios Barlas Injection-Date: Sun, 16 Nov 2014 20:56:14 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3333 =CE=A4=CE=B7 =CE=9A=CF=85=CF=81=CE=B9=CE=B1=CE=BA=CE=AE, 16 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 9:00:12 =CE=BC.=CE=BC. UTC+1, = =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 rickman =CE=AD=CE=B3=CF= =81=CE=B1=CF=88=CE=B5: > On 11/16/2014 4:44 AM, Marios Barlas wrote: > > =CE=A4=CE=B7 =CE=A3=CE=AC=CE=B2=CE=B2=CE=B1=CF=84=CE=BF, 15 =CE=9D=CE= =BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:50:10 =CE=BC.=CE=BC. = UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicolas Matringe = =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > >> Le 14/11/2014 23:40, Marios Barlas a =C3=A9crit : > >>> =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, = 14 =CE=9D=CE=BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:43:19 =CE= =BC.=CE=BC. UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicola= s Matringe =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > >> [...] > >>>> You're from a computer programming background, aren't you ? > >>> Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing= a 2 years master's in nanotechnology the last semester of which is in micr= oelectronics. As a result us stupid physics people lack a good deal of back= ground that others have for granted. This is my first bit of code in VHDL. > >> > >> Sorry for my wrong guess, then. You wrote your VHDL like you'd write a > >> program in C for example. It doesn't work like that. > >> > >> VHDL is a description language, not a programming language. It is like= a > >> schematics, except it is in text form. Concurrent expressions (i.e. th= at > >> are outside of processes) are independent blocks in your schematics. > >> This also means that their order in the code doesn't matter at all. > >> As Brian explained, concurrently assigning something to a signal is li= ke > >> connecting the output of a logic function to this signal. Concurrently > >> assigning several times to the same signal is connecting several outpu= ts > >> together. You usually don't want to do that (this causes your Xs in > >> simulation) > >> You seem to assume your code is executed from top to bottom. It is not= . > >> It is not even executed, since VHDL is not a programming language. Wha= t > >> you want is a block that takes a number and, after several iterations, > >> outputs its square root, am I right ? So you want to initialize some > >> internal signals or variables then step by step compute the square roo= t > >> and finally output the result. So you need some simple sequencer (a > >> counter will do), and a clock to make it run. > >> > >> Nicolas > > > > Thanks for the reply Nicolas. Finally I wrote my code in dataflow using= stages and it works perfectly. But I'll write it again with a process and = clock! thanks for your feedback ! >=20 > I'm curious about the course where you are learning VHDL. I remember=20 > about a million years ago when I was in college that I took a my first=20 > computer programming course. It was one part of six in a lab course in= =20 > chemistry. I believe it was just two weeks. I now know they were doing= =20 > their students a huge disservice by giving them such a limited amount of= =20 > training and then releasing them into the world to write their own=20 > programs. >=20 > I'm wondering if you are learning VHDL in a similar manner. VHDL is not= =20 > a terrible language to learn, but any HDL is a bit different from=20 > computer programming in that they are inherently parallel rather than=20 > sequential. Computer programming languages come naturally because they= =20 > are sequential reading the same as a recipe. HLDs are describing the=20 > functionality of hardware with it working in parallel. So there are=20 > different rules to it than you may be used to in software. >=20 > --=20 >=20 > Rick The program I'm following is called "master Nanotech". It's a bit unorthodo= x in the sense that it's mainly 1 year of applied physics / SC technology i= n master's level and 6 months in pure electronics. Now we are having two co= urses on VHDL one which is theoretical + small exercises like the one you s= aw above and then a lab which is split in 3 parts ( Full custom design in += layout in digital and analog electronics and semi-custom design in VHDL + = place and route in Synopsis. ) The problem is that the courses take for gra= nted some background in electronics and this is something lacking to ppl li= ke me that come from applied physics. So, even if you are comfortable with = programming wrapping your mind around parallel execution is somewhat alien = in the beginning. From newsfish@newsfish Thu Aug 1 00:31:16 2024 X-Received: by 10.66.190.229 with SMTP id gt5mr60362057pac.39.1416171375721; Sun, 16 Nov 2014 12:56:15 -0800 (PST) X-Received: by 10.140.41.147 with SMTP id z19mr1230388qgz.1.1416171375670; Sun, 16 Nov 2014 12:56:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1493614igd.0!news-out.google.com!m4ni197qag.1!nntp.google.com!u7no2139455qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 12:56:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.70.30.51; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 195.70.30.51 References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4dcad4a2-6e44-435c-bb23-9f37f58addbf@googlegroups.com> Subject: Re: problem with sll operator From: Marios Barlas Injection-Date: Sun, 16 Nov 2014 20:56:15 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3334 =CE=A4=CE=B7 =CE=9A=CF=85=CF=81=CE=B9=CE=B1=CE=BA=CE=AE, 16 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 9:00:12 =CE=BC.=CE=BC. UTC+1, = =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 rickman =CE=AD=CE=B3=CF= =81=CE=B1=CF=88=CE=B5: > On 11/16/2014 4:44 AM, Marios Barlas wrote: > > =CE=A4=CE=B7 =CE=A3=CE=AC=CE=B2=CE=B2=CE=B1=CF=84=CE=BF, 15 =CE=9D=CE= =BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:50:10 =CE=BC.=CE=BC. = UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicolas Matringe = =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > >> Le 14/11/2014 23:40, Marios Barlas a =C3=A9crit : > >>> =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, = 14 =CE=9D=CE=BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:43:19 =CE= =BC.=CE=BC. UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicola= s Matringe =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > >> [...] > >>>> You're from a computer programming background, aren't you ? > >>> Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing= a 2 years master's in nanotechnology the last semester of which is in micr= oelectronics. As a result us stupid physics people lack a good deal of back= ground that others have for granted. This is my first bit of code in VHDL. > >> > >> Sorry for my wrong guess, then. You wrote your VHDL like you'd write a > >> program in C for example. It doesn't work like that. > >> > >> VHDL is a description language, not a programming language. It is like= a > >> schematics, except it is in text form. Concurrent expressions (i.e. th= at > >> are outside of processes) are independent blocks in your schematics. > >> This also means that their order in the code doesn't matter at all. > >> As Brian explained, concurrently assigning something to a signal is li= ke > >> connecting the output of a logic function to this signal. Concurrently > >> assigning several times to the same signal is connecting several outpu= ts > >> together. You usually don't want to do that (this causes your Xs in > >> simulation) > >> You seem to assume your code is executed from top to bottom. It is not= . > >> It is not even executed, since VHDL is not a programming language. Wha= t > >> you want is a block that takes a number and, after several iterations, > >> outputs its square root, am I right ? So you want to initialize some > >> internal signals or variables then step by step compute the square roo= t > >> and finally output the result. So you need some simple sequencer (a > >> counter will do), and a clock to make it run. > >> > >> Nicolas > > > > Thanks for the reply Nicolas. Finally I wrote my code in dataflow using= stages and it works perfectly. But I'll write it again with a process and = clock! thanks for your feedback ! >=20 > I'm curious about the course where you are learning VHDL. I remember=20 > about a million years ago when I was in college that I took a my first=20 > computer programming course. It was one part of six in a lab course in= =20 > chemistry. I believe it was just two weeks. I now know they were doing= =20 > their students a huge disservice by giving them such a limited amount of= =20 > training and then releasing them into the world to write their own=20 > programs. >=20 > I'm wondering if you are learning VHDL in a similar manner. VHDL is not= =20 > a terrible language to learn, but any HDL is a bit different from=20 > computer programming in that they are inherently parallel rather than=20 > sequential. Computer programming languages come naturally because they= =20 > are sequential reading the same as a recipe. HLDs are describing the=20 > functionality of hardware with it working in parallel. So there are=20 > different rules to it than you may be used to in software. >=20 > --=20 >=20 > Rick The program I'm following is called "master Nanotech". It's a bit unorthodo= x in the sense that it's mainly 1 year of applied physics / SC technology i= n master's level and 6 months in pure electronics. Now we are having two co= urses on VHDL one which is theoretical + small exercises like the one you s= aw above and then a lab which is split in 3 parts ( Full custom design in += layout in digital and analog electronics and semi-custom design in VHDL + = place and route in Synopsis. ) The problem is that the courses take for gra= nted some background in electronics and this is something lacking to ppl li= ke me that come from applied physics. So, even if you are comfortable with = programming wrapping your mind around parallel execution is somewhat alien = in the beginning. From newsfish@newsfish Thu Aug 1 00:31:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator Date: Sun, 16 Nov 2014 20:53:42 -0500 Organization: A noiseless patient Spider Lines: 73 Message-ID: References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> <4dcad4a2-6e44-435c-bb23-9f37f58addbf@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 17 Nov 2014 01:54:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="30258"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19X1dhupNd3CupXkd7QTe1o" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <4dcad4a2-6e44-435c-bb23-9f37f58addbf@googlegroups.com> Cancel-Lock: sha1:3Yr1oG04waK8uV2j/1euQE6jOKs= Xref: news.eternal-september.org comp.lang.vhdl:3335 On 11/16/2014 3:56 PM, Marios Barlas wrote: > Τη Κυριακή, 16 Νοεμβρίου 2014 9:00:12 μ.μ. UTC+1, ο χρήστης rickman έγραψε: >> On 11/16/2014 4:44 AM, Marios Barlas wrote: >>> Τη Σάββατο, 15 Νοεμβρίου 2014 10:50:10 μ.μ. UTC+1, ο χρήστης Nicolas Matringe έγραψε: >>>> Le 14/11/2014 23:40, Marios Barlas a écrit : >>>>> Τη Παρασκευή, 14 Νοεμβρίου 2014 10:43:19 μ.μ. UTC+1, ο χρήστης Nicolas Matringe έγραψε: >>>> [...] >>>>>> You're from a computer programming background, aren't you ? >>>>> Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a 2 years master's in nanotechnology the last semester of which is in microelectronics. As a result us stupid physics people lack a good deal of background that others have for granted. This is my first bit of code in VHDL. >>>> >>>> Sorry for my wrong guess, then. You wrote your VHDL like you'd write a >>>> program in C for example. It doesn't work like that. >>>> >>>> VHDL is a description language, not a programming language. It is like a >>>> schematics, except it is in text form. Concurrent expressions (i.e. that >>>> are outside of processes) are independent blocks in your schematics. >>>> This also means that their order in the code doesn't matter at all. >>>> As Brian explained, concurrently assigning something to a signal is like >>>> connecting the output of a logic function to this signal. Concurrently >>>> assigning several times to the same signal is connecting several outputs >>>> together. You usually don't want to do that (this causes your Xs in >>>> simulation) >>>> You seem to assume your code is executed from top to bottom. It is not.. >>>> It is not even executed, since VHDL is not a programming language. What >>>> you want is a block that takes a number and, after several iterations, >>>> outputs its square root, am I right ? So you want to initialize some >>>> internal signals or variables then step by step compute the square root >>>> and finally output the result. So you need some simple sequencer (a >>>> counter will do), and a clock to make it run. >>>> >>>> Nicolas >>> >>> Thanks for the reply Nicolas. Finally I wrote my code in dataflow using stages and it works perfectly. But I'll write it again with a process and clock! thanks for your feedback ! >> >> I'm curious about the course where you are learning VHDL. I remember >> about a million years ago when I was in college that I took a my first >> computer programming course. It was one part of six in a lab course in >> chemistry. I believe it was just two weeks. I now know they were doing >> their students a huge disservice by giving them such a limited amount of >> training and then releasing them into the world to write their own >> programs. >> >> I'm wondering if you are learning VHDL in a similar manner. VHDL is not >> a terrible language to learn, but any HDL is a bit different from >> computer programming in that they are inherently parallel rather than >> sequential. Computer programming languages come naturally because they >> are sequential reading the same as a recipe. HLDs are describing the >> functionality of hardware with it working in parallel. So there are >> different rules to it than you may be used to in software. >> >> -- >> >> Rick > > The program I'm following is called "master Nanotech". It's a bit unorthodox in the sense that it's mainly 1 year of applied physics / SC technology in master's level and 6 months in pure electronics. Now we are having two courses on VHDL one which is theoretical + small exercises like the one you saw above and then a lab which is split in 3 parts ( Full custom design in + layout in digital and analog electronics and semi-custom design in VHDL + place and route in Synopsis. ) The problem is that the courses take for granted some background in electronics and this is something lacking to ppl like me that come from applied physics. So, even if you are comfortable with programming wrapping your mind around parallel execution is somewhat alien in the beginning. When I learned VHDL I wasn't "comfortable" with the parallel nature of it. I had been programming in conventional languages for a number of years. However, I was familiar with logic design and once it was explained to me how the HDL mapped to logic it helped a lot. I always think of my design in terms of the hardware and then code that hardware in the HDL. In your theoretical course they should have taught you that a signal can not be assigned in more than one process without a resolution function. In theory std_logic is resolved, so it is not an error to have multiple drivers. But unless you are describing a tristated bus it is not synthesizable and tristated buses are not used very often. So they give you a warning. Try this with std_ulogic and you will get an error. -- Rick From newsfish@newsfish Thu Aug 1 00:31:16 2024 X-Received: by 10.236.1.37 with SMTP id 25mr58271181yhc.25.1416235050126; Mon, 17 Nov 2014 06:37:30 -0800 (PST) X-Received: by 10.140.34.14 with SMTP id k14mr28834qgk.8.1416235050111; Mon, 17 Nov 2014 06:37:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!u7no2320466qaz.1!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no485733qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 06:37:30 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> Subject: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Mon, 17 Nov 2014 14:37:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3336 So Im messing arround with VHDL - Ive created a package that contains a lin= ked list with a generic type. There is one issue I cant seem to work out in my head - is it possible crea= te a generic that defaults to the initial value of the generic type? At the= moment, when the there are no values in the list, the "get_item" function = will return the default value of the generic type - so I want to give the p= ackage a "null_value" generic, so it is easy to detect a null return (ie an= empty list). package ll_test_pkg is generic ( type data_t; =20 null_value : data_t :=3D ; ); =20 type link_list_t is protected =20 procedure add_item( i : data_t ); =20 impure function get_item return data_t; =20 end protected link_list_t; =20 end package ll_test_pkg; I could just force the user to explicitly specify the null_value when insta= ntiating the package, but it would be nicer (for me) if it defaulted to the= initial value of data_t. I could also make the get_item a procedure that outputs a data_t and an emp= ty_list boolean, but I wondered if the above was possible? From newsfish@newsfish Thu Aug 1 00:31:17 2024 X-Received: by 10.182.165.104 with SMTP id yx8mr65606501obb.15.1416237026044; Mon, 17 Nov 2014 07:10:26 -0800 (PST) X-Received: by 10.140.82.106 with SMTP id g97mr9451qgd.27.1416237026015; Mon, 17 Nov 2014 07:10:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no477679igb.0!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no493046qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 07:10:24 -0800 (PST) In-Reply-To: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: KJ Injection-Date: Mon, 17 Nov 2014 15:10:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3337 On Monday, November 17, 2014 9:37:31 AM UTC-5, Tricky wrote: > I could just force the user to explicitly specify the null_value when instantiating the package, but it would be nicer (for me) if it defaulted to the initial value of data_t. > I'm not sure what you mean by the 'initial value of data_t', but inside your function, if you declare a variable that is eventually the one to be returned, that variable will get initialized to the leftmost value of the type. Example: function get_item return std_logic is variable RetVal: std_logic; -- RetVal will initialize to 'U' because it is the leftmost value in the definition of std_logic begin return(RetVal); end function get_item; Kevin Jennings From newsfish@newsfish Thu Aug 1 00:31:17 2024 X-Received: by 10.66.231.100 with SMTP id tf4mr56890088pac.48.1416241719993; Mon, 17 Nov 2014 08:28:39 -0800 (PST) X-Received: by 10.140.87.71 with SMTP id q65mr12158qgd.39.1416241719944; Mon, 17 Nov 2014 08:28:39 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no509222igb.0!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no510272qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 08:28:39 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Mon, 17 Nov 2014 16:28:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3338 On Monday, 17 November 2014 15:10:28 UTC, KJ wrote: > On Monday, November 17, 2014 9:37:31 AM UTC-5, Tricky wrote: > > I could just force the user to explicitly specify the null_value when i= nstantiating the package, but it would be nicer (for me) if it defaulted to= the initial value of data_t. > >=20 >=20 > I'm not sure what you mean by the 'initial value of data_t', but inside y= our function, if you declare a variable that is eventually the one to be re= turned, that variable will get initialized to the leftmost value of the typ= e. >=20 > Example: >=20 > function get_item return std_logic is > variable RetVal: std_logic; -- RetVal will initialize to 'U' because i= t is the leftmost value in the definition of std_logic > begin > return(RetVal); > end function get_item; >=20 > Kevin Jennings Well yes, that is what I already have. But I want the possibility of the us= er specifying the null_value, which needs to be done on the generics. I can= leave it without a default value, but that forces the user to explicitly s= pecify the null_return, even if it is the initial value, for every package = instantiation. From newsfish@newsfish Thu Aug 1 00:31:17 2024 X-Received: by 10.52.228.4 with SMTP id se4mr70885361vdc.7.1416285958729; Mon, 17 Nov 2014 20:45:58 -0800 (PST) X-Received: by 10.182.121.161 with SMTP id ll1mr1436obb.27.1416285958290; Mon, 17 Nov 2014 20:45:58 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no136908qap.1!news-out.google.com!ks2ni22429igb.0!nntp.google.com!uq10no709066igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 20:45:58 -0800 (PST) In-Reply-To: <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Andy Injection-Date: Tue, 18 Nov 2014 04:45:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:3339 if data_t is always scalar, then use data_t'left as the initializer for null_value: null_value : data_t := data_t'left; If data_t can be scalar, array or record type, you may be outa luck... Andy From newsfish@newsfish Thu Aug 1 00:31:18 2024 X-Received: by 10.236.32.204 with SMTP id o52mr71944439yha.53.1416287700472; Mon, 17 Nov 2014 21:15:00 -0800 (PST) X-Received: by 10.182.28.10 with SMTP id x10mr70267obg.11.1416287700355; Mon, 17 Nov 2014 21:15:00 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no633733qac.0!news-out.google.com!c9ni14081igv.0!nntp.google.com!h15no2399917igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 21:14:59 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> <4dcad4a2-6e44-435c-bb23-9f37f58addbf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <101864e2-b23f-467d-a84c-129811ea9313@googlegroups.com> Subject: Re: problem with sll operator From: Andy Injection-Date: Tue, 18 Nov 2014 05:15:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2820 X-Received-Body-CRC: 1456568327 Xref: news.eternal-september.org comp.lang.vhdl:3340 There's a very fine line between what a parallelizing compiler can do for S= W, and what a synthesis tool does for HDL. Both understand how to transform= sequential statements into parallel threads based on dependency. Once you understand the HDL behavior (not the template) that synthesizes to= registers vs combinatorial logic, then you are free to code your HDL at th= e behavioral level, on a clock-cycle by clock-cycle basis, and let the synt= hesis tool worry about the HW. If the synthesis results won't run with a fa= st enough clock, then (and only then) start thinking/coding at a lower leve= l. Often the "cure" for slow HW is to do something more often, not less oft= en. In SW we are taught not to perform a task if it is not needed. In HW, w= e learn to perform the task all the time, and only use the results if we ne= ed to. That takes less logic (and ns) than the decision whether to do the t= ask or not. In practice, this is nothing more than reducing dependency, whi= ch aids in parallelizing. I have always thought VHDL should be taught using variables first (use sign= als only for inter-process communication), so the student can fully underst= and what constitutes the behavior of a register, or storage of any kind (la= tches, ram, etc.) Once you fully understand that, you can reliably use stor= age, or avoid unwanted storage. Andy From newsfish@newsfish Thu Aug 1 00:31:18 2024 X-Received: by 10.67.14.232 with SMTP id fj8mr17480112pad.16.1416393601020; Wed, 19 Nov 2014 02:40:01 -0800 (PST) X-Received: by 10.140.27.214 with SMTP id 80mr11908qgx.23.1416393600862; Wed, 19 Nov 2014 02:40:00 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3522532igd.0!news-out.google.com!c9ni18079igv.0!nntp.google.com!w8no759316qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 02:40:00 -0800 (PST) In-Reply-To: <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.255.5.90; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 146.255.5.90 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Wed, 19 Nov 2014 10:40:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3341 On Tuesday, 18 November 2014 04:46:00 UTC, Andy wrote: > if data_t is always scalar, then use data_t'left as the initializer for null_value: > > null_value : data_t := data_t'left; > > If data_t can be scalar, array or record type, you may be outa luck... > > Andy Yup, I suspect outta luck - as the whole point is it could be any data type. You cant even use 'left as you dont know at that point what type of type it is. From newsfish@newsfish Thu Aug 1 00:31:18 2024 X-Received: by 10.182.58.105 with SMTP id p9mr53779170obq.25.1416396295176; Wed, 19 Nov 2014 03:24:55 -0800 (PST) X-Received: by 10.140.20.175 with SMTP id 44mr1525325qgj.4.1416396295029; Wed, 19 Nov 2014 03:24:55 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no1406024igb.0!news-out.google.com!ks2ni24749igb.0!nntp.google.com!s7no275312qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 03:24:54 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.179.200; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.179.179.200 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> Subject: Speeding up computations in sequential algorithm From: Marios Barlas Injection-Date: Wed, 19 Nov 2014 11:24:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3342 Dear all, I'm trying to figure out how to speed up my computation on the following al= gorithm: Following my previous post, I wrote a code that implements an FSMD of 3 sta= tes calculating the square root of a number according to a clock. All is wo= rking fine, but i'lm trying to figure out if I can make it more efficient b= y making more calculations on the same clock cycle.=20 I have a process and in this a case statement with me FSMD states. Since I = can't use the for...generate command inside the process I tried to use some= buffer variables like this :=20 res_buff <=3D (res_c-(root_c + delta_c)) when (((root_c + = delta_c) <=3D res_c) ) else res_c; root_buff <=3D shift_right(root_c + shift_left(delta_c,1),1) = when ((root_c + delta_c) <=3D res_c) else=20 shift_right(root_c,1); delta_buff <=3D shift_right(delta_c,2); -- Parallelization=20 res_next <=3D (res_buff-(root_buff + delta_buff)) when (((ro= ot_buff + delta_buff) <=3D res_buff) ) else res_buff; root_next <=3D shift_right(root_buff + shift_left(delta_buff,= 1),1) when ((root_buff + delta_buff) <=3D res_buff) else=20 shift_right(root_buff,1); delta_next <=3D shift_right(delta_buff,2); but it seems to mess up my results. From the little I know I think this is = pipelining but I'm not sure how to infer this logic in VHDL. Anyone could g= ive me an idea? Thanks in Advance, Marios Barlas From newsfish@newsfish Thu Aug 1 00:31:19 2024 X-Received: by 10.66.142.106 with SMTP id rv10mr79268799pab.21.1416396752239; Wed, 19 Nov 2014 03:32:32 -0800 (PST) X-Received: by 10.140.41.11 with SMTP id y11mr16199qgy.16.1416396752075; Wed, 19 Nov 2014 03:32:32 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3548735igd.0!news-out.google.com!ks2ni24749igb.0!nntp.google.com!s7no277160qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 03:32:32 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.182.238.172; posting-account=DanITAoAAADZRQ3INvxcdLr4w4QwYv0X NNTP-Posting-Host: 88.182.238.172 References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch From: Laurent Cabaret Injection-Date: Wed, 19 Nov 2014 11:32:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3343 Le samedi 30 ao=FBt 2014 18:08:34 UTC+2, Bart Fox a =E9crit=A0: > > pyVhdl2Sch is a documentation generator tool. It takes VHDL files (.vhd= ) as entry and generates a pdf schematic for each input file. > With a little fiddeling on MacOS X (with Macports) it run on my Mac too. >=20 > Nice work! >=20 > I did some changes to support signed/unsigned and std_ulogic as data type= s: >=20 > /pyVhdl2Sch$ git diff > diff --git a/file_manager/vhdl_reader.py b/file_manager/vhdl_reader.py > index f9576ca..9933442 100644 > --- a/file_manager/vhdl_reader.py > +++ b/file_manager/vhdl_reader.py > @@ -99,10 +99,10 @@ class Vhdl_reader: > if wire_type =3D=3D "integer": > nb_wires =3D 32 > else: > - if wire_type =3D=3D "std_logic": > + if wire_type =3D=3D "std_logic" or wire_type =3D=3D "std_ulo= gic": > nb_wires =3D 1 > else: > - if wire_type =3D=3D "std_logic_vector": > + if wire_type =3D=3D "std_logic_vector" or wire_type =3D= =3D=20 > "std_ulogic_vector" or wire_type =3D=3D "signed" or wire_type =3D=3D "uns= igned": > bus_direction =3D real_words[5].lower() > bus_description =3D text.split("(")[1].split(")")[0= ] > if bus_direction =3D=3D "downto": > diff --git a/pyV2S.py b/pyV2S.py > index 8cccdf0..ced8fd6 100755 > --- a/pyV2S.py > +++ b/pyV2S.py > @@ -1,4 +1,4 @@ > -#!/usr/bin/python > +#!/usr/bin/env python > # -*- coding: utf-8 -*- >=20 >=20 >=20 > Maybe you can enhance the skript to use the data type instead the number= =20 > of wires for unknown data types? > I use a lot of vhdl-recods defined in packages in my projects, so the=20 > number of wires is difficult to determine. >=20 > regards, > Bart Hi, I inserted your interesting message as an issue in the github space. I think i solved it. Many Thanks, Laurent From newsfish@newsfish Thu Aug 1 00:31:19 2024 X-Received: by 10.182.234.108 with SMTP id ud12mr79436300obc.0.1416397241957; Wed, 19 Nov 2014 03:40:41 -0800 (PST) X-Received: by 10.140.41.147 with SMTP id z19mr1550661qgz.1.1416397241813; Wed, 19 Nov 2014 03:40:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no1410662igb.0!news-out.google.com!c9ni18079igv.0!nntp.google.com!w8no773281qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 03:40:41 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.182.238.172; posting-account=DanITAoAAADZRQ3INvxcdLr4w4QwYv0X NNTP-Posting-Host: 88.182.238.172 References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94d990e4-54d5-408d-bbea-a97856766f4a@googlegroups.com> Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch From: Laurent Cabaret Injection-Date: Wed, 19 Nov 2014 11:40:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3344 Hi,=20 I inserted your interesting message as an issue in the github space. here is the current state of his resolution : - Signals are now allowed in port definition - Still working on resolution functions! - cairocffi embed all fonts (even standard ones) so Jura seems to be smalle= r than times or helvetica. - Not sure to understand the kicad part - pyVhdl2Sch now support pdf/svg/ps/png output Many Thanks,=20 Laurent=20 =20 Le samedi 30 ao=FBt 2014 22:15:52 UTC+2, Dio Gratia a =E9crit=A0: > On Thursday, August 28, 2014 7:53:10 PM UTC+12, Laurent Cabaret wrote: >=20 > > pyVhdl2Sch is a documentation generator tool.=20 > >=20 > > Feel free to criticize/cheers/participate/... >=20 > I noticed your tool doesn't accept the optional keyword signal in an inte= rface signal declaration on the port. >=20 > interface_signal_declaration ::=3D > [ signal ] identifier_list : [ mode ] subtype_indication [ bus ] [ = :=3D static_expression ] >=20 > "Ports of any mode are also signals." As you can see the mode is optional= and defaults to mode in. >=20 > Also a subtype indication can be more than a name and an index range: >=20 > subtype_indication ::=3D > [ resolution_indication ] type_mark [ constraint ] >=20 > resolution_indication ::=3D > resolution_function_name | ( element_resolution ) >=20 > element_resolution ::=3D array_element_resolution | record_resolution=20 >=20 > array_element_resolution ::=3D resolution_indication >=20 > record_resolution ::=3D record_element_resolution { , record_element_reso= lution }=20 >=20 > record_element_resolution ::=3D record_element_simple_name resolution_ind= ication >=20 > (These are from IEEE Std 1076-2008). A port signal can be a record, too. >=20 > A resolution indication can appear wherever there is a driver. This is v= alid VHDL code: >=20 > library ieee; > use ieee.std_logic_1164.all; >=20 > package a_pkg is >=20 > function x_res (to_resolve: std_logic_vector) return std_ulogic; >=20 > end a_pkg; >=20 > package body a_pkg is >=20 > function x_res (to_resolve: std_logic_vector) return std_ulogic is > variable r: std_ulogic; > begin > r :=3D 'Z'; > for i in to_resolve'range loop > r :=3D r or to_resolve(i); > end loop; > return r; > end function x_res; >=20 > end a_pkg; >=20 > library ieee; > use ieee.std_logic_1164.all; > use work.a_pkg.all; >=20 > entity foo is > port ( > signal a: in std_logic; > signal b: in std_logic; > signal c: in std_logic; > signal p: out x_res std_logic > ); > end entity; >=20 > architecture fum of foo is > =20 > begin=20 > p <=3D a; > p <=3D b; > p <=3D c; > end architecture; >=20 > As you can see there's a resolution function declared and because it's no= t an array type or a record type there are no parentheses for an array elem= ent resolution function. A record can have a resolution function for each = record element, while there's only one for an array type. >=20 > I've written schematic symbol generators several times over the years wha= t your program does isn't a surprise, the geometry familiar. =20 >=20 > That you discard the subtype indication (index range) limits the use to b= lock diagrams (for documentation). There's at least one PDF based schematic= package out there (Kicad). It'd likely require your own PDF code generati= on to make symbols for it. >=20 > A three signal port entity generated a 10KB PDF file, you're own PDF code= generation could possibly reduce that should you be able to live with a st= andard embedded font. The issue here is eventually swamping a word process= or by including embedded PDF files accumulating in size. Open Office/Libre = Office can slow down with a relatively few large image files, It's the redr= aw times. >=20 > We used to do a lot of PostScript code for this kind of stuff back in the= day, PDF can be on par and schematic symbols are about as hard as printing= overlays on bank checks. You could do PostScript and rely on conversion t= o PDF. From newsfish@newsfish Thu Aug 1 00:31:19 2024 X-Received: by 10.52.253.102 with SMTP id zz6mr39485285vdc.1.1416459026278; Wed, 19 Nov 2014 20:50:26 -0800 (PST) X-Received: by 10.182.213.36 with SMTP id np4mr242925obc.4.1416459026085; Wed, 19 Nov 2014 20:50:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no518239qap.1!news-out.google.com!w7ni66qay.0!nntp.google.com!h15no4069690igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 20:50:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Andy Injection-Date: Thu, 20 Nov 2014 04:50:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:3345 You could provide a procedure to set the null value. Until/unless the user calls the procedure, use the default value of data_t. You could also implement a lockout to prevent using the set_null_value() procedure after add_item() has been called. Andy From newsfish@newsfish Thu Aug 1 00:31:19 2024 X-Received: by 10.182.234.108 with SMTP id ud12mr85262269obc.0.1416483224817; Thu, 20 Nov 2014 03:33:44 -0800 (PST) X-Received: by 10.140.36.231 with SMTP id p94mr7637qgp.13.1416483224785; Thu, 20 Nov 2014 03:33:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4272028igd.0!news-out.google.com!w7ni49qay.0!nntp.google.com!s7no588938qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Nov 2014 03:33:44 -0800 (PST) In-Reply-To: <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <618a2d08-80c0-4b77-8068-db37295a51d8@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Thu, 20 Nov 2014 11:33:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3346 On Thursday, 20 November 2014 04:50:28 UTC, Andy wrote: > You could provide a procedure to set the null value. Until/unless the user calls the procedure, use the default value of data_t. You could also implement a lockout to prevent using the set_null_value() procedure after add_item() has been called. > > Andy This is all a bit proof of concept anyway at the moment - but these are good ideas. Linked lists have often featured in my testbenches, so having a linked list in a package would mean I wouldnt have to essentially do a copy/paste into every new testbench that uses different storage types. Looking forward to it :) From newsfish@newsfish Thu Aug 1 00:31:20 2024 X-Received: by 10.66.161.40 with SMTP id xp8mr579385pab.33.1416483596162; Thu, 20 Nov 2014 03:39:56 -0800 (PST) X-Received: by 10.140.21.49 with SMTP id 46mr3210qgk.30.1416483596108; Thu, 20 Nov 2014 03:39:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no1860493igb.0!news-out.google.com!w7ni50qay.0!nntp.google.com!w8no1083940qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Nov 2014 03:39:55 -0800 (PST) In-Reply-To: <618a2d08-80c0-4b77-8068-db37295a51d8@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> <618a2d08-80c0-4b77-8068-db37295a51d8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9d17a65e-ba88-4d0e-a69b-b4a21cb56f8e@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Thu, 20 Nov 2014 11:39:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3347 One thing that is going to infuriate me though is the protected type limitations: Cannot have arrays of protected types. Cannot have function/procedure arguments that are access types (or records that contain access types) in protected type member functions. So I may have to move away from protected types to define the linked list in the package, and just store the linked list in the package itself, as you can now define variables in a package if the package is local to a process/function/procedure. From newsfish@newsfish Thu Aug 1 00:31:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Speeding up computations in sequential algorithm Date: Thu, 20 Nov 2014 13:21:30 +0000 (UTC) Organization: A noiseless patient Spider Lines: 36 Message-ID: References: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 20 Nov 2014 13:21:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="11272"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1963e7t3xkFL4WBauqFp3kUf+DqkQMZ1Ek=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:vzTBY22E0W9gK3pykHN3gFCZ7a8= Xref: news.eternal-september.org comp.lang.vhdl:3348 On Wed, 19 Nov 2014 03:24:54 -0800, Marios Barlas wrote: > Dear all, > > I'm trying to figure out how to speed up my computation on the following > algorithm: ... > I have a process and in this a case statement with me FSMD states. Since > I can't use the for...generate command inside the process I tried to use > some buffer variables like this : ... > but it seems to mess up my results. From the little I know I think this > is pipelining but I'm not sure how to infer this logic in VHDL. Anyone > could give me an idea? The first stage is to have a clear idea what you want to happen in each cycle of the pipeline - I find it helps to name signals appropriately and to organise the pipelined process into its logical stages. Here's a simple example of a badly pipelined design (WARNING : I am not recommending this practice!) http://vhdlguru.blogspot.com/2011/01/what-is-pipelining-explanation- with.html and my approach to cleaning it up, in response to a StackExchange question on this topic. http://stackoverflow.com/questions/14765205/how-can-i-speed-up-my-math- operations-in-vhdl/14777458#14777458 These may help get you started - Brian From newsfish@newsfish Thu Aug 1 00:31:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Speeding up computations in sequential algorithm Date: Thu, 20 Nov 2014 11:30:43 -0500 Organization: A noiseless patient Spider Lines: 95 Message-ID: References: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 20 Nov 2014 16:31:08 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="8f56c4083975a6c8d296f9d83087445c"; logging-data="27183"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+BMSicG3uG0YbD4XDZJBLR" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> Cancel-Lock: sha1:qDgcGE3CaP8SAUufkZIZTF88QP0= Xref: news.eternal-september.org comp.lang.vhdl:3349 On 11/19/2014 6:24 AM, Marios Barlas wrote: > Dear all, > > I'm trying to figure out how to speed up my computation on the following algorithm: > > Following my previous post, I wrote a code that implements an FSMD of 3 states calculating the square root of a number according to a clock. All is working fine, but i'lm trying to figure out if I can make it more efficient by making more calculations on the same clock cycle. > > I have a process and in this a case statement with me FSMD states. Since I can't use the for...generate command inside the process I tried to use some buffer variables like this : > > > > res_buff <= (res_c-(root_c + delta_c)) when (((root_c + delta_c) <= res_c) ) else > res_c; > root_buff <= shift_right(root_c + shift_left(delta_c,1),1) when ((root_c + delta_c) <= res_c) else > shift_right(root_c,1); > delta_buff <= shift_right(delta_c,2); > -- Parallelization > res_next <= (res_buff-(root_buff + delta_buff)) when (((root_buff + delta_buff) <= res_buff) ) else > res_buff; > root_next <= shift_right(root_buff + shift_left(delta_buff,1),1) when ((root_buff + delta_buff) <= res_buff) else > shift_right(root_buff,1); > delta_next <= shift_right(delta_buff,2); > > but it seems to mess up my results. From the little I know I think this is pipelining but I'm not sure how to infer this logic in VHDL. Anyone could give me an idea? > > Thanks in Advance, > Marios Barlas To start with, I don't know what an FSMD is. Is this like an FSM (Finite State Machine)? I can't comment on the correctness of your code because I don't know what it is supposed to do. You are only showing part of your work. Should we assume this is inside a clocked process? I am guessing yes since you talk about pipelining and clocks. In that case, each of the signal assignment statements above will generate registers. The assignment to res_buff looks like it only includes signals from outside the process. The assignment to root_buff looks the same so this will run in parallel without depending on the assignment to res_buff. The assignment to delta_buff is the same. So all three of these are running at the same point in the pipeline. The assignment to res_next depends on all three of the above, so it would be in the second stage of the pipeline. Same for root_next and delta_next. So all three of these signals are in the second stage of the pipeline and will produce results with the same cycle timing. This is a two stage pipeline producing a result every clock cycle with a two clock cycle latency. There are some things you can do to improve the efficiency of this algorithm. The expression root_c + delta_c is used more than once, but will likely produce multiple adders coded this way. This sum is subtracted from res_c as well as compared to res_c. This can share the same logic if coded to do so. This is where variables can be used. Variables in a clocked process will not generate registers if they are assigned before they are used. So you could do this... sum_c := root_c + delta_c; diff_c := res_c - sum_c; res_buff <= res_c when diff_c < 0 else diff_c; This provides the tools a better chance at using just two adders (or subtractor - same thing) and using the carry out from the second one to control the mux selecting the input to res_buff. In addition the same variables can be used to control the assignment for root_buff since it uses the same comparison, again saving logic and likely improving the speed at least a little. If you want to speed this up further, you can pipeline the above two variable assignments as signal assignments giving two more stages to your pipeline. You will need to delay the use of root_c and delta_c in the assignment to root_buff to keep them at the same delay. Likewise for delta_buff so all three x_buff results are ready at the same time. You can use all the same methods to improve the assignments to res_next, root_next and delta_next. If you are not familiar with variable assignments, they work like variables in a regular C program completing their assignments as they are executed while signal assignments are not completed until the process stops. Using a variable in a clocked process gets you the current value while using a signal inside the process gets you the old value no matter what. I hope this helps some. -- Rick From newsfish@newsfish Thu Aug 1 00:31:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch Date: 21 Nov 2014 11:12:21 GMT Lines: 38 Message-ID: References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> X-Trace: individual.net D9Of1pxqo5+ZNUYj2YzEpgqG00uVK6P6Z7k2Z3lmQQYqBtH4+g X-Orig-Path: not-for-mail Cancel-Lock: sha1:vwfo4MClRc5j3HZkmlx3sOvNGmY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3350 Hi Laurent, Laurent Cabaret wrote: [] > pyVhdl2Sch is a documentation generator tool. It takes VHDL files > (.vhd) as entry and generates a pdf schematic for each input file. tried and got this: Warning - a special port type is used or your entity is not well formated. by default I used your type name as a wire name Here is the official supported type list : - integer - natural - positive - signed - std_logic - std_logic_vector - std_ulogic - unsigned Traceback (most recent call last): File "./pyV2S.py", line 30, in reader = Vhdl_reader(filename, options) File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 31, in __init__ self.parse_entity_part() File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 141, in parse_entity_part self.extract_wire(raw_line) File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 166, in extract_wire wire_type = vhdl_wire_words[3].lower() IndexError: list index out of range The vhdl synthesizes correctly and all ports are std_logic[_vector]. I'm actually very motivated for introducing these tools for documentation purposes, especially considering the possibility to include it in a LaTeX document. Al From newsfish@newsfish Thu Aug 1 00:31:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch Date: 21 Nov 2014 11:14:57 GMT Lines: 22 Message-ID: References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> X-Trace: individual.net /BsLZiNLxQhuSUnCdmOUxwOlvCXUL2aUoBEIb5mvOs0P14yhTo X-Orig-Path: not-for-mail Cancel-Lock: sha1:uVuVfHO/yF6dEDigFQZ6DNGEz+4= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3351 Hi Laurent, Laurent Cabaret wrote: [] > pyVhdl2Sch is a documentation generator tool. It takes VHDL files > (.vhd) as entry and generates a pdf schematic for each input file. Additionally this is what I get on the example provided in the repo: debian@debian:pyVhdl2Sch-master$ ./pyV2S.py tb_None.vhd Traceback (most recent call last): File "./pyV2S.py", line 30, in reader = Vhdl_reader(filename, options) File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 30, in __init__ self.parse_vhdl_file() File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 118, in parse_vhdl_file if real_words[locate_end + 1] == self.entity.name: IndexError: list index out of range Am I missing something? Al From newsfish@newsfish Thu Aug 1 00:31:21 2024 X-Received: by 10.236.26.200 with SMTP id c48mr6703774yha.46.1416612388520; Fri, 21 Nov 2014 15:26:28 -0800 (PST) X-Received: by 10.140.94.150 with SMTP id g22mr134243qge.0.1416612388496; Fri, 21 Nov 2014 15:26:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!w8no1470194qac.0!news-out.google.com!w7ni319qay.0!nntp.google.com!s7no976089qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Nov 2014 15:26:28 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.55.56.197; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 5.55.56.197 References: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8610158a-7e65-43a0-b1a3-601e5da566a1@googlegroups.com> Subject: Re: Speeding up computations in sequential algorithm From: Nikolaos Kavvadias Injection-Date: Fri, 21 Nov 2014 23:26:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 82 Xref: news.eternal-september.org comp.lang.vhdl:3352 Dear Marios and rickman, > > @rickman: An FSMD (Finite-State Machine with Datapath) is a microarchitectural paradi= gm for implementing non-programmable/hardwired processors with their contro= l unit and datapath combined/merged. Essentially, the datapath actions are = embedded within the actual next state and output logic decoder of your RTL = FSM description (if you view it this way). I have a published work on FSMDs: http://cdn.intechweb.org/pdfs/29207.pdf w= hile my high-level synthesis tool, HercuLeS ( http://www.nkavvadias.com/her= cules/ ) produces such FSMDs. A manual for HercuLeS is here: http://www.nka= vvadias.com/hercules-reference-manual/hercules-refman.pdf. I have based my version of FSMDs to Prof. Gajski's and Pong P. Chu's work, = mostly on some of their books and published papers. I had rented a couple o= f Gajski's books from the local library [I was a lecturer at the time, now = I ain't but still can drive 2km to closest higher education library and ren= t various works] and have actually bought two of P.P. Chu's works; the RTL = Hardware Design using VHDL book is brilliant. Further, Gajski's work on Spe= cC and the classic TRs (technical reports) from his group were at some poin= t night (by the bed) and day (by the desk) readings... I believe Vivado HLS (aka AutoESL/xPilot) and the others do the same thing,= with one key difference on how the actual RTL FSMD code is presented. Thei= r datapath code is implemented with concurrent assignments and there are lo= ts of control and status signals going in and out of the next state logic d= ecoder. On the contrary I prefer datapath actions embedded within state dec= oding; produces a little slower and fatter (sic) hardware overall, but the = user's intention in the RTL is much more clear and it is to grasp and follo= w. > > @Marios: > > I'm trying to figure out how to speed up my computation on the followin= g algorithm: I know this might not be an scientifically appropriate proposal from my sid= e, but do you have a plain software description of the algorithm? E.g. when= I was enumerating topological sorts I started from Knuth's pseudocode, the= n coded an ANSI/ISO C version, then modified it for HLS with HercuLeS, and = voila: a meaningless hardware version for the code as well :) > > Following my previous post, I wrote a code that implements an FSMD of 3= =20 > > states calculating the square root of a number according to a clock. Al= l is=20 > > working fine, but i'm trying to figure out if I can make it more effici= ent by > > making more calculations on the same clock cycle. Having an FSMD with only 3 states for a square-rooting algorithm seems coun= ter-intuitive, unless one of the states is a multi-cycle state or a "multi-= state". Or you are doing a lot of operation chaining within a single state. Try to follow basic principles from Pong P. Chu: 1) Have a _reg and _next version for each register as declared signals in V= HDL code. 2) In each state, read the _reg's and assign the _next's. 3) Donnot reassign the same _next version of a register within a single FSM= D state. 4) You can totally avoid variables from your code. Not all tools provide eq= ually mature support for synthesizing code with variables. 5) Operation chaining is possible but requires that you write _next version= s and read them in the same state. Then these are plain wires and donnot im= plement registers. Again, you can peruse the same _next version more than o= nce in the same state. I had developed an ingenious technique for automatically modifying a VHDL F= SMD code for adding controlled operation chaining; I was about to patent it= but spared on the money of course. My technique just uses a lexer and to r= ead more about it, see chapter III.E of this work: http://www.nkavvadias.co= m/publications/kavvadias_asap12_cr.pdf There are also newer works on HercuLeS like: http://www.nkavvadias.com/publ= ications/hercules-pci13.pdf and a journal paper accepted for publication. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Thu Aug 1 00:31:22 2024 X-Received: by 10.236.16.194 with SMTP id h42mr9263541yhh.13.1416657533780; Sat, 22 Nov 2014 03:58:53 -0800 (PST) X-Received: by 10.140.81.169 with SMTP id f38mr177737qgd.3.1416657533764; Sat, 22 Nov 2014 03:58:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!w8no1554244qac.0!news-out.google.com!w7ni50qay.0!nntp.google.com!w8no1554240qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 22 Nov 2014 03:58:53 -0800 (PST) In-Reply-To: <8610158a-7e65-43a0-b1a3-601e5da566a1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.55.56.197; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 5.55.56.197 References: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> <8610158a-7e65-43a0-b1a3-601e5da566a1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7633f1d6-72fe-4d9b-aafd-a2a96f3e3dc5@googlegroups.com> Subject: Re: Speeding up computations in sequential algorithm From: Nikolaos Kavvadias Injection-Date: Sat, 22 Nov 2014 11:58:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 8 Xref: news.eternal-september.org comp.lang.vhdl:3353 > 5) Operation chaining is possible but requires that you write _next versions and read them in the same state. Then these are plain wires and donnot implement registers. Again, you can peruse the same _next version more than once in the same state. Of course I meant that you cannot peruse **for writing** the same _next version more than once in the same state! I just needed to clarify this. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Thu Aug 1 00:31:22 2024 X-Received: by 10.42.194.204 with SMTP id dz12mr39012883icb.16.1416954209790; Tue, 25 Nov 2014 14:23:29 -0800 (PST) X-Received: by 10.50.114.134 with SMTP id jg6mr298532igb.13.1416954208932; Tue, 25 Nov 2014 14:23:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7681515igd.0!news-out.google.com!c9ni23798igv.0!nntp.google.com!h15no422878igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Nov 2014 14:23:28 -0800 (PST) In-Reply-To: <9d17a65e-ba88-4d0e-a69b-b4a21cb56f8e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> <618a2d08-80c0-4b77-8068-db37295a51d8@googlegroups.com> <9d17a65e-ba88-4d0e-a69b-b4a21cb56f8e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <43261795-7850-4358-bf20-e947dfa8d2d1@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Jim Lewis Injection-Date: Tue, 25 Nov 2014 22:23:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3354 In my generic linked list/scoreboard, pop when the list is empty is an assert failure. OTOH, if you are looking to return type'left, why not just declare a local variable: impure function pop return data_t is variable result : data_t ; -- defaults to left most value of type begin if not empty then result := top.value ; -- get -- remove top cell from list return result ; else report "FIFO_PKG: POP called when list empty" severity failure ; return result ; -- type'left by default end if ; end function pop ; I have the following already on the VHDL-201X list. Do you have any more? Cannot have arrays of protected types. Cannot have function/procedure arguments that are access types (or records that contain access types) in protected type member functions. Drop me a line as I have a package that you may like. From newsfish@newsfish Thu Aug 1 00:31:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: VHDL 2008: Can I use conditional_expressions as an initialiser for a constant? Newsgroups: comp.lang.vhdl User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 26 Nov 2014 11:21:15 GMT Lines: 66 Message-ID: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 2c4443a3.news.astraweb.com X-Trace: DXC=YlQQ`H0Snca1m]JSMD?cjjL?0kYOcDh@jSBc;\8ijUdkYRP3^H]h_dfAgmHV5@Nh Xref: news.eternal-september.org comp.lang.vhdl:3355 Hi, I'm trying to do something equivalent to the following: generic g : boolean; ... constant c : some_type := expression1 when g else expression2; This is something I want to do a lot in both synthesisable and non- synthesisable designs. Usually I end up writing an 8 line function to do something that I ought be able to do in a single line. For example, in Verilog 2001 I would write this as localparam c = g ? expression1 : expression2; (Questions below) I found this in the '08 standard: [§ 6.4.2.2] constant_declaration ::= constant identifier_list : subtype_indication [ := expression ] ; [§ 9.1] expression ::= condition_operator primary | logical_expression [§ 9.1] primary ::= name | literal | aggregate | function_call | qualified_expression | type_conversion | allocator | ( expression ) Unfortunately, "expression" doesn't ever lead to "conditional_expressions". [§ 10.5.3] conditional_expressions ::= expression when condition { else expression when condition } [ else expression ] Questions: Q1: Am I reading the standard correctly and we can't (in 2008) use conditional expressions in constant initialisers? Q2: Is there some simple and effective way of doing what I'm trying to do? Q3: If not, how do we go about fixing this? Thanks, Allan From newsfish@newsfish Thu Aug 1 00:31:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.albasani.net!.POSTED!not-for-mail From: Mathias Weierganz Newsgroups: comp.lang.vhdl Subject: Xilinx ISE14: Problems with Sythesize Date: Wed, 26 Nov 2014 13:20:51 +0100 Organization: albasani.net Lines: 24 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.albasani.net xzta6jGovNTUmf+T8xqXsu/dRd9dkLx6EPI4Usf1/EqFNZCILgUrTPU4u/Kv7unWR5/FgC0qUQGJDFpQF82CR7UgwwgPT+xohv5wBr2+TbzJZf9tWCcY1zhb/CBYY0+v NNTP-Posting-Date: Wed, 26 Nov 2014 12:20:51 +0000 (UTC) Injection-Info: news.albasani.net; logging-data="DOcd1ftLa4HeTD0s/qDe53ApTLP0dRANsJXWORpGYdaxB1QDxV3v7S96/BbZ/LWRX99OklXo2jmdbkDfxNfJdRn1kNz+7fj60qDXvg5e+IIzzvW51OFpmlCEPHuNeNUP"; mail-complaints-to="abuse@albasani.net" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 Cancel-Lock: sha1:7Tk6VV8xvCz3+/ozxvuyVga/1ZE= Xref: news.eternal-september.org comp.lang.vhdl:3356 I am using Xilinx ISE14.7 I have a project for Spartan6 which I can compile without problems. Now I try to compile it for a Virtex 5 and I run into problems already at the synthesis level. The first problem was easy to fix: The synthesis don't like the concatenation operator "&" in the instantiation bloc. But is there an easy solution for my second problem? The synthesis don't want to see this construct: databus_i => (others => '0'), and give me this error message: ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in unconstrained array aggregate. Let me say it again: I can compile the same project for Spartan-6 without any problems. Any hints? Thanks Mathias From newsfish@newsfish Thu Aug 1 00:31:23 2024 X-Received: by 10.182.111.164 with SMTP id ij4mr29995344obb.26.1417006272388; Wed, 26 Nov 2014 04:51:12 -0800 (PST) X-Received: by 10.140.81.169 with SMTP id f38mr586843qgd.3.1417006272352; Wed, 26 Nov 2014 04:51:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7965634igd.0!news-out.google.com!m4ni578qag.1!nntp.google.com!s7no1994171qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 04:51:12 -0800 (PST) In-Reply-To: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008: Can I use conditional_expressions as an initialiser for a constant? From: KJ Injection-Date: Wed, 26 Nov 2014 12:51:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3357 On Wednesday, November 26, 2014 6:21:16 AM UTC-5, Allan Herriman wrote: > Hi, >=20 > I'm trying to do something equivalent to the following: >=20 > generic g : boolean; > ... > constant c : some_type :=3D expression1 when g else expression2; >=20 >=20 > Q3: If not, how do we go about fixing this? >=20 >=20 Write a function that takes as input the condition and the two expressions = and returns the result. I called mine 'sel' (since 'select' is already a r= eserved keyword). Overload it for all of the basic types that you would us= e for an expression as well as for std_ulogic and boolean for the condition= . Works just fine for any version VHDL. function sel(Cond: BOOLEAN; If_True, If_False: integer) return integer; function sel(Cond: BOOLEAN; If_True, If_False: real) return real; function sel(Cond: BOOLEAN; If_True, If_False: time) return time; function sel(Cond: BOOLEAN; If_True, If_False: BOOLEAN) return BOOLEAN; function sel(Cond: BOOLEAN; If_True, If_False: arr_integer) return arr_= integer; function sel(Cond: BOOLEAN; If_True, If_False: arr_natural) return arr_= natural; function sel(Cond: BOOLEAN; If_True, If_False: arr_real) return arr_rea= l; function sel(Cond: BOOLEAN; If_True, If_False: arr_time) return arr_tim= e; function sel(Cond: BOOLEAN; If_True, If_False: std_ulogic) return std_u= logic; function sel(Cond: BOOLEAN; If_True, If_False: std_ulogic_vector) retur= n std_ulogic_vector; function sel(Cond: BOOLEAN; If_True, If_False: std_logic_vector) return= std_logic_vector; function sel(Cond: BOOLEAN; If_True, If_False: signed) return signed; function sel(Cond: BOOLEAN; If_True, If_False: unsigned) return unsigne= d; function sel(Cond: BOOLEAN; If_True, If_False: STRING) return STRING; function sel(Cond: BOOLEAN; If_True, If_False: Character) return Charac= ter; Then the usage is simply: constant c : some_type :=3D sel(g, expression1, expression2); Or for the more wordy constant c : some_type :=3D sel(Cond =3D> g, If_True =3D> expression1, If_F= alse =3D> expression2); Kevin Jennings From newsfish@newsfish Thu Aug 1 00:31:23 2024 X-Received: by 10.66.219.135 with SMTP id po7mr33035036pac.9.1417025296168; Wed, 26 Nov 2014 10:08:16 -0800 (PST) X-Received: by 10.182.216.202 with SMTP id os10mr25132obc.8.1417025295978; Wed, 26 Nov 2014 10:08:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no8115957igd.0!news-out.google.com!d20ni730igz.0!nntp.google.com!h15no704959igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 10:08:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2ecf2fab-174a-4654-970b-8779c82c17a5@googlegroups.com> Subject: Re: Xilinx ISE14: Problems with Sythesize From: Andy Injection-Date: Wed, 26 Nov 2014 18:08:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1516 X-Received-Body-CRC: 3595982537 Xref: news.eternal-september.org comp.lang.vhdl:3358 There are a lot of things that are non-compliant VHDL that are accepted by synthesis tools. And a lot of compliant VHDL is not accepted by synthesis tools either. Have you tried a simulator? They often have better error messages. Is the port formal of an unconstrained type (i.e. takes its size from that of the associated actual)? If so, there is no pre-defined port-width from which "others" can be determined, and vise versa. Andy From newsfish@newsfish Thu Aug 1 00:31:24 2024 X-Received: by 10.66.248.8 with SMTP id yi8mr32184430pac.26.1417025508772; Wed, 26 Nov 2014 10:11:48 -0800 (PST) X-Received: by 10.182.233.134 with SMTP id tw6mr166296obc.2.1417025508614; Wed, 26 Nov 2014 10:11:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no8117709igd.0!news-out.google.com!d20ni730igz.0!nntp.google.com!h15no706268igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 10:11:48 -0800 (PST) In-Reply-To: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <08e8e804-f755-4665-b4d0-3a32624466ca@googlegroups.com> Subject: Re: VHDL 2008: Can I use conditional_expressions as an initialiser for a constant? From: Andy Injection-Date: Wed, 26 Nov 2014 18:11:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1346 X-Received-Body-CRC: 1298250791 Xref: news.eternal-september.org comp.lang.vhdl:3359 There is no such thing in vhdl as "conditional expressions", only "conditional assignments". Since your statement is not an assignment statement, but a declaration statement, your code is non-compliant. Andy From newsfish@newsfish Thu Aug 1 00:31:24 2024 X-Received: by 10.70.19.201 with SMTP id h9mr31743341pde.3.1417027832824; Wed, 26 Nov 2014 10:50:32 -0800 (PST) X-Received: by 10.50.61.135 with SMTP id p7mr377293igr.9.1417027832719; Wed, 26 Nov 2014 10:50:32 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no722277igd.0!news-out.google.com!d20ni740igz.0!nntp.google.com!h15no8139262igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 10:50:32 -0800 (PST) In-Reply-To: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008: Can I use conditional_expressions as an initialiser for a constant? From: Jim Lewis Injection-Date: Wed, 26 Nov 2014 18:50:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3360 Hi Allan, I worked on it for the VHDL-2008 phase. It is an interesting problem as to= how to add it as an expression given that signals assignments already have= existing conditional_waveforms. Also one of the members wanted to change = the else to a "," (in the name of conciseness) in the conditional assignmen= t. In the end that caused ambiguity which killed it. =20 During the LRM editing phase, I got busy with other items (had to work so I= could eat), and did not notice that the force statement required a separat= e BNF production that defined conditional_expression. Wish I had noticed a= s given that it was done there, it is very obvious to support that in at le= ast an initialization scenario as you asked for. =20 It is on the list again: =20 http://www.eda.org/twiki/bin/view.cgi/P1076/ConditionalExpressions I added a fail safe so that if the main proposal fails that we at least add= it to initialize constants, signals, and variables. Which seems to be a t= rivial addition at this point. =20 We are at the point where we are ranking proposals and welcome input from m= embers of the VHDL community - no one want to add and/or implement features= that are not wanted by the general community. Jim From newsfish@newsfish Thu Aug 1 00:31:24 2024 X-Received: by 10.182.65.232 with SMTP id a8mr33253210obt.5.1417028142084; Wed, 26 Nov 2014 10:55:42 -0800 (PST) X-Received: by 10.50.134.135 with SMTP id pk7mr375666igb.6.1417028141915; Wed, 26 Nov 2014 10:55:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no8141732igd.0!news-out.google.com!d20ni740igz.0!nntp.google.com!h15no8141725igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 10:55:41 -0800 (PST) In-Reply-To: <2326e3ef-907a-41d5-881d-756ced5009dd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <2326e3ef-907a-41d5-881d-756ced5009dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81079b61-a7b4-416b-a5f5-853d957fe904@googlegroups.com> Subject: Re: Floating point in VHDL From: Jim Lewis Injection-Date: Wed, 26 Nov 2014 18:55:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1627 X-Received-Body-CRC: 1768142744 Xref: news.eternal-september.org comp.lang.vhdl:3361 On Thursday, November 6, 2014 6:42:18 PM UTC-8, Dai Tran Van wrote: > Hi everyone. > I working with foating point, and i have problem with multipile maxtrix, vetor in foating.. > this i's my project to go out shool on time. help me. What have you done so far? VHDL-2008 added packages for floating point math. There is a tutorial on this part on my website at: http://www.synthworks.com/papers/index.htm If you look around some, you may find some packages that use this package that do what you want - they exist. From newsfish@newsfish Thu Aug 1 00:31:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Xilinx ISE14: Problems with Sythesize Date: Wed, 26 Nov 2014 14:23:11 -0500 Organization: Alacron, Inc. Lines: 38 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 26 Nov 2014 19:23:26 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="31024"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1958AGA5CNxhl9psk2gPwsGr2Gn3M0ha9g=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:BGx88lku/Vw796tuy/fZaC6TRo0= Xref: news.eternal-september.org comp.lang.vhdl:3362 Mathias Weierganz wrote: > I am using Xilinx ISE14.7 > I have a project for Spartan6 which I can compile without problems. Now > I try to compile it for a Virtex 5 and I run into problems already at > the synthesis level. > > The first problem was easy to fix: The synthesis don't like the > concatenation operator "&" in the instantiation bloc. > > But is there an easy solution for my second problem? The synthesis > don't want to see this construct: > databus_i => (others => '0'), > and give me this error message: > ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in > unconstrained array aggregate. > > Let me say it again: I can compile the same project for Spartan-6 > without any problems. > > > Any hints? > > Thanks > > Mathias Xilinx tools use a different front-end to synthesize 6-series and newer FPGA's by default. If your code works with the new front- end, you can try to use it on older parts. In the XST command line add the option: -use_new_parser yes If you use the Navigator GUI, you can apply this option under "Other XST Command Line Options" in the synthesis properties. -- Gabor From newsfish@newsfish Thu Aug 1 00:31:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 26 Nov 2014 16:12:59 -0600 From: mazharchattha88 Subject: Re: VHDL code for Turbo Codes Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 9490c5c1-517d-4461-a749-5b3102ed76bc References: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> Message-ID: Date: Wed, 26 Nov 2014 16:12:59 -0600 Lines: 6 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ssFfz3o5rhCRbopQZRCiHlc269IHZlgRbr0OMX9GEOssgbzgdyzpTD47unp0ahTqXsvXrfL69VnC7E1!FJndndIWObo1ZhNpGIaKpGCS4dO/PWHXE1xZGxwO8mUGy4qsQEAYewtjDK0f8zOiNoan2wT0wUbh!WKc= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1072 Xref: news.eternal-september.org comp.lang.vhdl:3363 hi i cant open this website for turbo code can u send me again From newsfish@newsfish Thu Aug 1 00:31:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.albasani.net!.POSTED!not-for-mail From: Mathias Weierganz Newsgroups: comp.lang.vhdl Subject: Re: Xilinx ISE14: Problems with Sythesize Date: Thu, 27 Nov 2014 09:40:37 +0100 Organization: albasani.net Lines: 19 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.albasani.net cVUnQQPBxhqpSCBM8tQK3+RW8+7ty96JBqkNSWZaacdiXXj0zd+KA4dN0/jdiwuAyUUWxecq0gDlquuCu0iWKTX8n4UQhS/rdKsUVWTCjcz/0UVTu4y7v45NfQct3zTQ NNTP-Posting-Date: Thu, 27 Nov 2014 08:40:37 +0000 (UTC) Injection-Info: news.albasani.net; logging-data="dZM1fkeRvpU4VugxlML3yk5X4VBak+gAjzdNTTLw9xzStNpyW9kPonUin3fiPUdHdid1MfLnysJKZMefyW0ycfO6XSmUQkvevgGVPzjg0EpNby0HDJKeP6OYdlbKG4KI"; mail-complaints-to="abuse@albasani.net" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:jelC626IdD4MCNOt/0uIYxqVnFc= Xref: news.eternal-september.org comp.lang.vhdl:3364 Am 26.11.2014 20:23, schrieb GaborSzakacs: > > Xilinx tools use a different front-end to synthesize 6-series and > newer FPGA's by default. If your code works with the new front- > end, you can try to use it on older parts. In the XST command > line add the option: > > -use_new_parser yes > > If you use the Navigator GUI, you can apply this option under > "Other XST Command Line Options" in the synthesis properties. > This works fine for me. Many thanks for this hint. Mathias From newsfish@newsfish Thu Aug 1 00:31:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Xilinx ISE14: Problems with Sythesize Date: Thu, 27 Nov 2014 11:26:55 +0000 (UTC) Organization: A noiseless patient Spider Lines: 15 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 27 Nov 2014 11:26:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="26475"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19OO3pYn2sU1/w9TetWPUL9XxlL6cJnx5k=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:v91n64F/2LPKx9k8fatygKVU9pc= Xref: news.eternal-september.org comp.lang.vhdl:3365 On Wed, 26 Nov 2014 13:20:51 +0100, Mathias Weierganz wrote: > But is there an easy solution for my second problem? The synthesis don't > want to see this construct: > databus_i => (others => '0'), > and give me this error message: > ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in > unconstrained array aggregate. Easily solved by constraining the array aggregate: databus_i => (databus_i'range => '0'), making the code more portable -- Brian From newsfish@newsfish Thu Aug 1 00:31:26 2024 X-Received: by 10.182.92.163 with SMTP id cn3mr5267392obb.49.1417141790936; Thu, 27 Nov 2014 18:29:50 -0800 (PST) X-Received: by 10.140.108.5 with SMTP id i5mr952qgf.11.1417141790863; Thu, 27 Nov 2014 18:29:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no9014412igd.0!news-out.google.com!m4ni576qag.1!nntp.google.com!w8no2895006qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Nov 2014 18:29:50 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Subject: Question pertaining to a project From: JB Injection-Date: Fri, 28 Nov 2014 02:29:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1648 X-Received-Body-CRC: 2822916710 Xref: news.eternal-september.org comp.lang.vhdl:3366 http://goo.gl/ZgNnK4 Above is the VHDL code I've attached relating to a small "Baseball Scoreboard" project. I'm fairly new to VHDL (~2 months) so bare with me when it comes to common practices (real world type stuff). I'm trying to code this now so, for instance, when the baseball count is 3-BALLS and 1-STRIKE and when the next pitch is thrown is a BALL then both the balls and strikes get reset back to "000" and "00". The code attached is working but without this feature. I've tried numerous things without any luck. The reset on the top-level is for a "hits" button. When a hit is produced this button resets the count (currently working). Thank you in advanced. From newsfish@newsfish Thu Aug 1 00:31:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Question pertaining to a project Date: Thu, 27 Nov 2014 22:27:23 -0500 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 28 Nov 2014 03:27:17 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="83a31ac2c505da17ce863bed0f607c5d"; logging-data="29976"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18k5+aG0oWCrqwoMBHCx2Id" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Cancel-Lock: sha1:yq0TM7kcNRgrmkJnDcTQJVrSZgE= Xref: news.eternal-september.org comp.lang.vhdl:3367 On 11/27/2014 9:29 PM, JB wrote: > http://goo.gl/ZgNnK4 > > Above is the VHDL code I've attached relating to a small "Baseball Scoreboard" project. I'm fairly new to VHDL (~2 months) so bare with me when it comes to common practices (real world type stuff). > > I'm trying to code this now so, for instance, when the baseball count is 3-BALLS and 1-STRIKE and when the next pitch is thrown is a BALL then both the balls and strikes get reset back to "000" and "00". > > The code attached is working but without this feature. I've tried numerous things without any luck. The reset on the top-level is for a "hits" button. When a hit is produced this button resets the count (currently working). > > Thank you in advanced. > The problem I see is that you are using the "button press" for each outcome as a clock. In real world applications, this has issues due to switch bouncing. However, supposing you had a "bounceless" button, you still get into trouble because you now *need* two processes (as you currently have) in order to use these two "clocks" but at the same time you can't assign balls (or strikes) in *both* of these processes, at least for synthesizable code. It might be possible to generate two signals when strike or ball happen on full count, and use each signal as an asynchronous reset to the other process. However this can get a bit messy. The usual way to handle this sort of problem is to use a free-running clock to sample the buttons. Then your state logic can all be in the same process driven by that clock's rising edge. You would use shift registers to synchronize and delay each button press and use bits from these shift registers to detect edges of the button synchronous to the clock. Now with one process, you can set or clear any number of signals on any button event (as detected by looking at the S/R bits). -- Gabor From newsfish@newsfish Thu Aug 1 00:31:27 2024 X-Received: by 10.52.1.103 with SMTP id 7mr40296873vdl.6.1417148476285; Thu, 27 Nov 2014 20:21:16 -0800 (PST) X-Received: by 10.140.41.147 with SMTP id z19mr729199qgz.1.1417148476206; Thu, 27 Nov 2014 20:21:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!s7no2411513qap.1!news-out.google.com!m4ni576qag.1!nntp.google.com!w8no2905056qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Nov 2014 20:21:16 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <653b4f7e-b556-48e0-bcab-fc7ecef4334e@googlegroups.com> Subject: Re: Question pertaining to a project From: JB Injection-Date: Fri, 28 Nov 2014 04:21:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1605 X-Received-Body-CRC: 3168534803 Xref: news.eternal-september.org comp.lang.vhdl:3368 This is funny you mention the "button press" as the clock because I know it's not the right method. I actually used a clock input and had changed it based on a friend's input, but knew it looked funny. Also, the fact I could not use both signal in my processes was another big issue and something I figured would have to be changed. Well, thank you very much Gabor. Glad I actually came to some solution (and had the same thoughts as you). I will implement what you suggested. Thanks again! From newsfish@newsfish Thu Aug 1 00:31:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: 28 Nov 2014 09:01:15 GMT Lines: 26 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> X-Trace: individual.net OjhmjEPXTg1rusa5h6CxWgMQ0m5tlmngyW4QroBkTloDPfew45 X-Orig-Path: not-for-mail Cancel-Lock: sha1:AfCEFoW2mM6vv4u5L8fx/oqKoUg= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3369 Hi Rick, rickman wrote: [] > I recommend that you fix your code to get rid of warnings. Otherwise > you become inured to them and eventually they will cause you to miss a > valid warning that you need to pay attention to. Just initialize the > full array to something that isn't a letter... ;) This is a sound suggestion, but I won't initialize those objects in the vhdl code since is error prone (you may suddenly forget to reset an added object and still get valid data). I usually get around this with the following lines in my .do file: set StdArithNoWarnings 1 set NumericStdNoWarnings 1 run 0 ns; set StdArithNoWarnings 0 set NumericStdNoWarnings 0 run -all HTH, Al From newsfish@newsfish Thu Aug 1 00:31:27 2024 X-Received: by 10.42.103.76 with SMTP id l12mr752661ico.8.1417172069952; Fri, 28 Nov 2014 02:54:29 -0800 (PST) X-Received: by 10.140.82.106 with SMTP id g97mr4937qgd.27.1417172069861; Fri, 28 Nov 2014 02:54:29 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no9207703igd.0!news-out.google.com!m4ni576qag.1!nntp.google.com!w8no2969339qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 02:54:29 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 78.154.109.115 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question pertaining to a project From: "colin_toogood@yahoo.com" Injection-Date: Fri, 28 Nov 2014 10:54:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3370 Makes a change from a traffic light controller. For full marks you need to read up on metastability, your simulator will always work but real D types can't cope with the button being pressed exactly when the clock edge occurs. Colin From newsfish@newsfish Thu Aug 1 00:31:28 2024 X-Received: by 10.182.245.162 with SMTP id xp2mr41498216obc.8.1417188283151; Fri, 28 Nov 2014 07:24:43 -0800 (PST) X-Received: by 10.140.38.197 with SMTP id t63mr4657qgt.31.1417188283126; Fri, 28 Nov 2014 07:24:43 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no9351314igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no2535997qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 07:24:43 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.176.197.14; posting-account=JQXykgoAAAB5c7UjCcMIJQGNoGxD60UO NNTP-Posting-Host: 88.176.197.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <70180598-daea-412f-b539-875d10ffbc3a@googlegroups.com> Subject: Generate find a good solution From: Olivier Dir Injection-Date: Fri, 28 Nov 2014 15:24:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3371 I have this process, pState : process(Clk) begin if Clk'event and Clk='1' then if SRst = '1' then State <= ST_IDLE; else case State is when ST_IDLE => if DspTrfAvb = '1' then State <= ST_TRF2DSP; elsif DataAbleRam(1) = '1' then State <= ST_WDATA1; elsif DataAbleRam(2) = '1' then State <= ST_WDATA2; elsif DataAbleRam(3) = '1' then State <= ST_WDATA3; elsif DataAbleRam(4) = '1' then State <= ST_WDATA4; elsif DataAbleRam(5) = '1' then State <= ST_WDATA5; elsif DataAbleRam(6) = '1' then State <= ST_WDATA6; elsif DataAbleRam(7) = '1' then State <= ST_WDATA7; elsif DataAbleRam(8) = '1' then State <= ST_WDATA8; else State <= ST_IDLE; end if; when ST_WDATA1 => if RdDataInRamRd(1) = '1' then State <= ST_DATA1; else State <= ST_WDATA1; end if; when ST_DATA1 => if DataAbleRamRd(1) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA1; end if; when ST_WDATA2 => if RdDataInRamRd(2) = '1' then State <= ST_DATA2; else State <= ST_WDATA2; end if; when ST_DATA2 => if DataAbleRamRd(2) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA2; end if; when ST_WDATA3 => if RdDataInRamRd(3) = '1' then State <= ST_DATA3; else State <= ST_WDATA3; end if; when ST_DATA3 => if DataAbleRamRd(3) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA3; end if; when ST_WDATA4 => if RdDataInRamRd(4) = '1' then State <= ST_DATA4; else State <= ST_WDATA4; end if; when ST_DATA4 => if DataAbleRamRd(4) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA4; end if; when ST_WDATA5 => if RdDataInRamRd(5) = '1' then State <= ST_DATA5; else State <= ST_WDATA5; end if; when ST_DATA5 => if DataAbleRamRd(5) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA5; end if; when ST_WDATA6 => if RdDataInRamRd(6) = '1' then State <= ST_DATA6; else State <= ST_WDATA6; end if; when ST_DATA6 => if DataAbleRamRd(6) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA6; end if; when ST_WDATA7 => if RdDataInRamRd(7) = '1' then State <= ST_DATA7; else State <= ST_WDATA7; end if; when ST_DATA7 => if DataAbleRamRd(7) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA7; end if; when ST_WDATA8 => if RdDataInRamRd(8) = '1' then State <= ST_DATA8; else State <= ST_WDATA8; end if; when ST_DATA8 => if DataAbleRamRd(8) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA8; end if; ---- end case; end if; end if; end process; what is the best syntax ? thank for advance Olivier From newsfish@newsfish Thu Aug 1 00:31:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: Fri, 28 Nov 2014 10:43:35 -0500 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 28 Nov 2014 15:43:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="1528"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jIT4vvd7IPRcSVUhiW63G" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:aYUBy0Km3ZvajUimtaKItcmMk/U= Xref: news.eternal-september.org comp.lang.vhdl:3372 On 11/28/2014 4:01 AM, alb wrote: > Hi Rick, > > rickman wrote: > [] >> I recommend that you fix your code to get rid of warnings. Otherwise >> you become inured to them and eventually they will cause you to miss a >> valid warning that you need to pay attention to. Just initialize the >> full array to something that isn't a letter... ;) > > This is a sound suggestion, but I won't initialize those objects in the > vhdl code since is error prone (you may suddenly forget to reset an > added object and still get valid data). I don't understand. If you forget to reset a signal, how will that create a problem? The type of warning the OP is talking about happens because the signal is *not* initialized and is a useful flag for that condition. It is not assured to catch all uninitialized signals, but how is intentionally not initializing them better? > I usually get around this with the following lines in my .do file: > > set StdArithNoWarnings 1 > set NumericStdNoWarnings 1 > run 0 ns; > set StdArithNoWarnings 0 > set NumericStdNoWarnings 0 > > run -all > > HTH, > > Al > -- Rick From newsfish@newsfish Thu Aug 1 00:31:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Generate find a good solution Date: Fri, 28 Nov 2014 10:45:44 -0500 Organization: A noiseless patient Spider Lines: 152 Message-ID: References: <70180598-daea-412f-b539-875d10ffbc3a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 28 Nov 2014 15:45:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="83a31ac2c505da17ce863bed0f607c5d"; logging-data="3001"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+FSusdbLVRqBceze5uo6pf" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 In-Reply-To: <70180598-daea-412f-b539-875d10ffbc3a@googlegroups.com> Cancel-Lock: sha1:wWQqF4so5s7PtuY/S9NSDXmd9Tc= Xref: news.eternal-september.org comp.lang.vhdl:3373 On 11/28/2014 10:24 AM, Olivier Dir wrote: > I have this process, > pState : process(Clk) > begin > if Clk'event and Clk='1' then > if SRst = '1' then > State <= ST_IDLE; > else > case State is > when ST_IDLE => > if DspTrfAvb = '1' then > State <= ST_TRF2DSP; > elsif DataAbleRam(1) = '1' then > State <= ST_WDATA1; > elsif DataAbleRam(2) = '1' then > State <= ST_WDATA2; > elsif DataAbleRam(3) = '1' then > State <= ST_WDATA3; > elsif DataAbleRam(4) = '1' then > State <= ST_WDATA4; > elsif DataAbleRam(5) = '1' then > State <= ST_WDATA5; > elsif DataAbleRam(6) = '1' then > State <= ST_WDATA6; > elsif DataAbleRam(7) = '1' then > State <= ST_WDATA7; > elsif DataAbleRam(8) = '1' then > State <= ST_WDATA8; > else > State <= ST_IDLE; > end if; > when ST_WDATA1 => > if RdDataInRamRd(1) = '1' then > State <= ST_DATA1; > else > State <= ST_WDATA1; > end if; > when ST_DATA1 => > if DataAbleRamRd(1) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA1; > end if; > when ST_WDATA2 => > if RdDataInRamRd(2) = '1' then > State <= ST_DATA2; > else > State <= ST_WDATA2; > end if; > when ST_DATA2 => > if DataAbleRamRd(2) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA2; > end if; > when ST_WDATA3 => > if RdDataInRamRd(3) = '1' then > State <= ST_DATA3; > else > State <= ST_WDATA3; > end if; > when ST_DATA3 => > if DataAbleRamRd(3) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA3; > end if; > when ST_WDATA4 => > if RdDataInRamRd(4) = '1' then > State <= ST_DATA4; > else > State <= ST_WDATA4; > end if; > when ST_DATA4 => > if DataAbleRamRd(4) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA4; > end if; > when ST_WDATA5 => > if RdDataInRamRd(5) = '1' then > State <= ST_DATA5; > else > State <= ST_WDATA5; > end if; > when ST_DATA5 => > if DataAbleRamRd(5) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA5; > end if; > when ST_WDATA6 => > if RdDataInRamRd(6) = '1' then > State <= ST_DATA6; > else > State <= ST_WDATA6; > end if; > when ST_DATA6 => > if DataAbleRamRd(6) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA6; > end if; > when ST_WDATA7 => > if RdDataInRamRd(7) = '1' then > State <= ST_DATA7; > else > State <= ST_WDATA7; > end if; > when ST_DATA7 => > if DataAbleRamRd(7) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA7; > end if; > when ST_WDATA8 => > if RdDataInRamRd(8) = '1' then > State <= ST_DATA8; > else > State <= ST_WDATA8; > end if; > when ST_DATA8 => > if DataAbleRamRd(8) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA8; > end if; > ---- > end case; > end if; > end if; > end process; > > what is the best syntax ? > > thank for advance > Olivier > Not clear what you're asking. The only thing I notice is that your process has a lot of unnecessary else clauses that assign the state to its current value. This same action is implied by leaving out the else clause, and doing so makes the whole thing shorter, and in my opinion easier to read. The only other observation is that even if you have fully used all cases, it is often better to pick one and use "default" instead of the case name. Some synthesizers have an easier time to optimize code this way. -- Gabor From newsfish@newsfish Thu Aug 1 00:31:29 2024 X-Received: by 10.42.246.66 with SMTP id lx2mr18881122icb.0.1417206881365; Fri, 28 Nov 2014 12:34:41 -0800 (PST) X-Received: by 10.140.104.145 with SMTP id a17mr2373qgf.16.1417206881294; Fri, 28 Nov 2014 12:34:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no9528493igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no2610805qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 12:34:41 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question pertaining to a project From: JB Injection-Date: Fri, 28 Nov 2014 20:34:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3374 @Gabor I'm kind of stumped on this one. I understand the shift register approach b= ut don't see how I can get the correct outputs of "01" "11" and "001" "011"= "111". Whenever I place a '1' on the button press in put I get a constant = change of outputs either "00" "10" "11" "00" even if the button is not pres= sed. Hmm.. From newsfish@newsfish Thu Aug 1 00:31:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Question pertaining to a project Date: Fri, 28 Nov 2014 21:23:18 -0500 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 29 Nov 2014 02:23:14 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="83a31ac2c505da17ce863bed0f607c5d"; logging-data="13588"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18SapKHwoUWWqfIbw8GsDEN" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 In-Reply-To: Cancel-Lock: sha1:D5vKksCepMxCVzpWNokgftM/0mU= Xref: news.eternal-september.org comp.lang.vhdl:3375 On 11/28/2014 3:34 PM, JB wrote: > @Gabor > > I'm kind of stumped on this one. I understand the shift register approach but don't see how I can get the correct outputs of "01" "11" and "001" "011" "111". Whenever I place a '1' on the button press in put I get a constant change of outputs either "00" "10" "11" "00" even if the button is not pressed. Hmm.. > OK, I have to say I have no idea what you're asking here. I looked back at your code and you haven't updated the paste.org page. So without seeing what you have now I really can't comment or help. By the way, you can always paste the VHDL code (at least the interesting bits) right into your post here instead of using an ad-sponsored site. After all VHDL is just text... -- Gabor From newsfish@newsfish Thu Aug 1 00:31:29 2024 X-Received: by 10.67.22.35 with SMTP id hp3mr13940655pad.11.1417231977527; Fri, 28 Nov 2014 19:32:57 -0800 (PST) X-Received: by 10.140.41.147 with SMTP id z19mr798713qgz.1.1417231977478; Fri, 28 Nov 2014 19:32:57 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no9704271igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no2689922qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 19:32:57 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> Subject: Re: Question pertaining to a project From: JB Injection-Date: Sat, 29 Nov 2014 03:32:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3376 --So this does exactly what I want it too without the feature I described to you prior. I was having a hard time implementing the shift registers. Here, I have the case statements but everything is now within one process block. My idea was something like: if tempstrikes <="11" then tempballs<="000"; type of thing, in order to clear the balls count if another strike is thrown and causes an out. But, it's not going to work based on the other assignments within the case statements. library IEEE; use ieee.std_logic_1164.all; entity Baseball_New is port (button_strikes : in std_logic; button_balls : in std_logic; clk : in std_logic; reset : in std_logic; led_strikes : out std_logic_vector (1 downto 0); led_balls : out std_logic_vector (2 downto 0) ); end entity; architecture Baseball_New_arch of Baseball_New is signal tempstrikes : std_logic_vector (1 downto 0); signal tempballs : std_logic_vector (2 downto 0); begin process (clk) begin if reset='1' then tempstrikes <="00"; elsif clk'EVENT AND clk = '1' AND button_strikes ='1' then case ( tempstrikes) is when "00" => tempstrikes <="01"; when "01" => tempstrikes <="11"; when "10" => tempstrikes <="00"; when "11" => tempstrikes<="00"; when others => tempstrikes <="00"; end case; end if; end process; led_strikes <= tempstrikes; process (clk) is begin if reset='1' then tempballs<="000"; elsif clk'EVENT AND clk='1' AND button_balls ='1' then case (tempballs) is when "000" => tempballs <="001"; when "001" => tempballs <="011"; when "010" => tempballs <="000"; when "011" => tempballs<="111"; when others => tempballs <= "000"; end case; end if; end process; led_balls<=tempballs; end Baseball_New_arch; From newsfish@newsfish Thu Aug 1 00:31:29 2024 X-Received: by 10.50.88.10 with SMTP id bc10mr40014453igb.5.1417232318855; Fri, 28 Nov 2014 19:38:38 -0800 (PST) X-Received: by 10.140.84.21 with SMTP id k21mr31qgd.6.1417232318775; Fri, 28 Nov 2014 19:38:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no9706029igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no2690897qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 19:38:38 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question pertaining to a project From: JB Injection-Date: Sat, 29 Nov 2014 03:38:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3377 **Nevermind, this still has two processes. My apologies. From newsfish@newsfish Thu Aug 1 00:31:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question pertaining to a project Date: Fri, 28 Nov 2014 23:34:36 -0500 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 29 Nov 2014 04:34:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="4568"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+DhP4bYjY3yD0hRowXfzxZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:fqHA6dcu489pQtpMat3Lksy1m3c= Xref: news.eternal-september.org comp.lang.vhdl:3378 On 11/28/2014 10:38 PM, JB wrote: > **Nevermind, this still has two processes. My apologies. You need to change the sensitivity list to include reset. process (clk, reset) Also, if you want to post your code here, you should remove the tabs and replace with spaces. I believe you code is using something less than 8 spaces per tab while posting tabs here defaults to 8. -- Rick From newsfish@newsfish Thu Aug 1 00:31:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: 29 Nov 2014 23:31:52 GMT Lines: 45 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> X-Trace: individual.net XMYyK1BBx0YkgwPh6Qdh+wzEoNP6JKbJkr50U9Xd0e3WB+tcbo X-Orig-Path: not-for-mail Cancel-Lock: sha1:UxzeiRPXoMCqt7JyCBH6QeOBFxo= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3379 Hi Rick, rickman wrote: [] >> This is a sound suggestion, but I won't initialize those objects in the >> vhdl code since is error prone (you may suddenly forget to reset an >> added object and still get valid data). > > I don't understand. If you forget to reset a signal, how will that > create a problem? The type of warning the OP is talking about happens > because the signal is *not* initialized and is a useful flag for that > condition. It is not assured to catch all uninitialized signals, but > how is intentionally not initializing them better? assume the following code: signal a: std_logic_vector := x"0123"; signal b: std_logic_vector := x"4567"; ... process (rst, clk) begin if rst = '1' then a <= '0000'; elsif rising_edge(clk) then -- do something comparing a and b end if; end process; The code above 'depends' on the initialization in the signals declaration and your simulation may differ from the behavior after synthesis, unless your target (and the toolchain) supports explicit initializations. My suggestion is to properly *reset* every register in your logic because this is how you control what is going to happen when your fpga will be doing *after* reset. You can safely disregard all signal initializations and handle those warnings at time 0 with the workaround posted. Al From newsfish@newsfish Thu Aug 1 00:31:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: Sat, 29 Nov 2014 20:29:50 -0500 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 30 Nov 2014 01:30:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25046"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+PO+peMpk8rn095LMHRsgI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:71zssctNc/+CkT6qTe28dOJTEWg= Xref: news.eternal-september.org comp.lang.vhdl:3380 On 11/29/2014 6:31 PM, alb wrote: > Hi Rick, > > rickman wrote: > [] >>> This is a sound suggestion, but I won't initialize those objects in the >>> vhdl code since is error prone (you may suddenly forget to reset an >>> added object and still get valid data). >> >> I don't understand. If you forget to reset a signal, how will that >> create a problem? The type of warning the OP is talking about happens >> because the signal is *not* initialized and is a useful flag for that >> condition. It is not assured to catch all uninitialized signals, but >> how is intentionally not initializing them better? > > assume the following code: > > > signal a: std_logic_vector := x"0123"; > signal b: std_logic_vector := x"4567"; > > .... > > process (rst, clk) > begin > if rst = '1' then > a <= '0000'; > elsif rising_edge(clk) then > -- do something comparing a and b > end if; > end process; > > > > The code above 'depends' on the initialization in the signals > declaration and your simulation may differ from the behavior after > synthesis, unless your target (and the toolchain) supports explicit > initializations. > > My suggestion is to properly *reset* every register in your logic > because this is how you control what is going to happen when your fpga > will be doing *after* reset. You can safely disregard all signal > initializations and handle those warnings at time 0 with the workaround > posted. If resetting a signal in your design is a requirement, it should have a way of verifying that it was reset. Every requirement should be verified. I would do that in the test bench. -- Rick From newsfish@newsfish Thu Aug 1 00:31:31 2024 X-Received: by 10.68.180.101 with SMTP id dn5mr2012770pbc.5.1417509046536; Tue, 02 Dec 2014 00:30:46 -0800 (PST) X-Received: by 10.50.30.202 with SMTP id u10mr35200igh.6.1417509046431; Tue, 02 Dec 2014 00:30:46 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no11810325igd.0!news-out.google.com!d20ni1426igz.0!nntp.google.com!h15no11810324igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 00:30:45 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.136.155.8; posting-account=5T8syQoAAADGHYRHO4dd1KbX_Ht4gcuF NNTP-Posting-Host: 175.136.155.8 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5471aa4c-ccf3-463d-a560-d48aa43207d5@googlegroups.com> Subject: Local Controller for latch From: Mohd Zulkarnain Jaranee Injection-Date: Tue, 02 Dec 2014 08:30:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3381 Hi, I want to make a controller which will enable the latch.=20 As you can seen on my code below, the signal en will take the output from w= AND x to enable the latch. After that, w and x will fetch the en. For exam= ple, initially, let say the w and x values start at 1, the en will become 1= and cause the latch to fetch data from data_in to data_out. After that, en= will become the input of w and x and cause the latch to disable. However, = the circuit didn't work when I tested it using altera university waveform p= rogram. The data_out didnt take the value of data_in. I can't figure out wh= at is the problem still I'm new in VHDL. Hope you can assist/advice me on t= his :) Sorry for my bad english. library ieee; use ieee.std_logic_1164.all; entity gasp_ctrl is port( w,x : inout std_logic; --! bidirectional wire data_in : in std_logic; --! Data In when latch is enable data_out: out std_logic -- ); end gasp_ctrl; architecture ctrl of gasp_ctrl is signal en, ww, xx : std_logic; =09 begin en <=3D w and x; ------=20 ww <=3D en; xx <=3D not en; w <=3D ww; x <=3D xx; =09 -------- Latch ------ process(en) begin if(en =3D '1') then data_out <=3D data_in; end if; end process; end gasp_ctrl; From newsfish@newsfish Thu Aug 1 00:31:31 2024 X-Received: by 10.66.231.100 with SMTP id tf4mr60257300pac.48.1417513258924; Tue, 02 Dec 2014 01:40:58 -0800 (PST) X-Received: by 10.140.108.5 with SMTP id i5mr19217qgf.11.1417513258608; Tue, 02 Dec 2014 01:40:58 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3474772igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no3548752qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 01:40:58 -0800 (PST) In-Reply-To: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 References: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <29367b80-c99e-4872-883b-8f381472ba48@googlegroups.com> Subject: Re: VHDL code for Turbo Codes From: Muhammad Injection-Date: Tue, 02 Dec 2014 09:40:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3382 Hi kwaj, i need vhdl code for turbo codes .can u give me this.. i will be very thankful to you. best regards From newsfish@newsfish Thu Aug 1 00:31:31 2024 X-Received: by 10.182.43.170 with SMTP id x10mr59171125obl.15.1417513289625; Tue, 02 Dec 2014 01:41:29 -0800 (PST) X-Received: by 10.140.48.69 with SMTP id n63mr1446qga.21.1417513289559; Tue, 02 Dec 2014 01:41:29 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!h15no11844332igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no3548799qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 01:41:29 -0800 (PST) In-Reply-To: <1105965927.803887.86760@f14g2000cwb.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 References: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> <1105965927.803887.86760@f14g2000cwb.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL code for Turbo Codes From: Muhammad Injection-Date: Tue, 02 Dec 2014 09:41:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3383 Hi zinga i need vhdl code for turbo codes .can u give me this.. i will be very thankful to you. best regards From newsfish@newsfish Thu Aug 1 00:31:32 2024 X-Received: by 10.42.197.134 with SMTP id ek6mr2355345icb.6.1417513305153; Tue, 02 Dec 2014 01:41:45 -0800 (PST) X-Received: by 10.140.33.229 with SMTP id j92mr110551qgj.7.1417513305085; Tue, 02 Dec 2014 01:41:45 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no11844429igd.0!news-out.google.com!m4ni576qag.1!nntp.google.com!w8no4042618qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 01:41:44 -0800 (PST) In-Reply-To: <91ca356bf018d3c2ea1e0c445b417d18@localhost.talkaboutprogramming.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 References: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> <91ca356bf018d3c2ea1e0c445b417d18@localhost.talkaboutprogramming.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL code for Turbo Codes From: Muhammad Injection-Date: Tue, 02 Dec 2014 09:41:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3384 Hi i need vhdl code for turbo codes .can u give me this.. i will be very thankful to you. best regards From newsfish@newsfish Thu Aug 1 00:31:32 2024 X-Received: by 10.70.44.161 with SMTP id f1mr33638081pdm.7.1417513452238; Tue, 02 Dec 2014 01:44:12 -0800 (PST) X-Received: by 10.182.241.135 with SMTP id wi7mr3356obc.29.1417513452059; Tue, 02 Dec 2014 01:44:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!h15no11845056igd.0!news-out.google.com!d20ni730igz.0!nntp.google.com!h15no3475217igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 01:44:11 -0800 (PST) In-Reply-To: <1fb8ce7b.0201071408.2aeed3e7@posting.google.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 References: <1fb8ce7b.0201071408.2aeed3e7@posting.google.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <74509e7f-214b-4eb7-ad79-9cdf201c3b09@googlegroups.com> Subject: Re: Looking for links to interleaver design for Turbo codes. From: Muhammad Injection-Date: Tue, 02 Dec 2014 09:44:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3385 On Monday, January 7, 2002 11:08:40 PM UTC+1, pacific ocean wrote: > Looking for links to interleaver design for Turbo codes. > > THX > Fredj hi, i need the code for interleaver can u give me plz.. thanks From newsfish@newsfish Thu Aug 1 00:31:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Local Controller for latch Date: Tue, 02 Dec 2014 04:51:04 -0500 Organization: A noiseless patient Spider Lines: 62 Message-ID: References: <5471aa4c-ccf3-463d-a560-d48aa43207d5@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 2 Dec 2014 09:51:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="5273"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+X59y627vMdGZL5OHERHS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <5471aa4c-ccf3-463d-a560-d48aa43207d5@googlegroups.com> Cancel-Lock: sha1:tNQ608Kt9+EKkRW7jEQf9q3hx10= Xref: news.eternal-september.org comp.lang.vhdl:3386 On 12/2/2014 3:30 AM, Mohd Zulkarnain Jaranee wrote: > Hi, I want to make a controller which will enable the latch. > > As you can seen on my code below, the signal en will take the output from w AND x to enable the latch. After that, w and x will fetch the en. For example, initially, let say the w and x values start at 1, the en will become 1 and cause the latch to fetch data from data_in to data_out. After that, en will become the input of w and x and cause the latch to disable. However, the circuit didn't work when I tested it using altera university waveform program. The data_out didnt take the value of data_in. I can't figure out what is the problem still I'm new in VHDL. Hope you can assist/advice me on this :) Sorry for my bad english. > > library ieee; > use ieee.std_logic_1164.all; > entity gasp_ctrl is > port( > w,x : inout std_logic; --! bidirectional wire > data_in : in std_logic; --! Data In when latch is enable > data_out: out std_logic -- > ); > end gasp_ctrl; > > architecture ctrl of gasp_ctrl is > signal en, ww, xx : std_logic; > > begin > en <= w and x; ------ > ww <= en; > xx <= not en; > w <= ww; > x <= xx; > > > -------- Latch ------ > process(en) > begin > if(en = '1') then > data_out <= data_in; > end if; > end process; > end gasp_ctrl; You have some fundamental misunderstandings of how logic and HTML work. I can identify two errors without trying. The really big one is that you seem to want X and W to be inputs, but also assign them in your code. Which are they, internal signals or inputs? Defining them as inout in your port doesn't make this synthesizeable. The next error is creating a feedback loop in the concurrent statements. By assigning values to X and W that depend on X and W you are creating unintentional latches. Do this. This is a simple circuit. Try drawing a logic schematic of what you think this should produce in the FPGA. Use AND and NOT functions and show what it should be. Finally, did you synthesize this or just load it into a chip and try running it? I'm surprised the tools didn't complain about this code. I guess maybe it just gave you warnings which you didn't pay attention to. Oh, there's a third error. You need to add data_in to your sensitivity list in the process... I don't think the simulation will work correctly without it. -- Rick From newsfish@newsfish Thu Aug 1 00:31:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Looking for links to interleaver design for Turbo codes. Date: Tue, 2 Dec 2014 12:45:03 +0000 (UTC) Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <1fb8ce7b.0201071408.2aeed3e7@posting.google.com> <74509e7f-214b-4eb7-ad79-9cdf201c3b09@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 2 Dec 2014 12:45:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="7679"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+2rWK9gbGDpj7j/aHPKONSYPVXolpyHiQ=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:XN5g22paiQvPBwsdZ7KytpM3eyU= Xref: news.eternal-september.org comp.lang.vhdl:3387 On Tue, 02 Dec 2014 01:44:11 -0800, Muhammad wrote: > On Monday, January 7, 2002 11:08:40 PM UTC+1, pacific ocean wrote: >> Looking for links to interleaver design for Turbo codes. >> >> THX Fredj > > hi, > i need the code for interleaver can u give me plz.. > > thanks Well he's had 12 years to finish the assignment so maybe he'll give you teh codez. Good luck! From newsfish@newsfish Thu Aug 1 00:31:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: VHDL 2008 support in Modelsim? Date: Fri, 05 Dec 2014 14:48:03 +0200 Organization: An impatient and LOUD arachnid Lines: 35 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Injection-Info: mx02.eternal-september.org; posting-host="0d8432157885fb838356cc0832d33c8c"; logging-data="20586"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/k1vA4NoG0ax1Ut+7AwIkx" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:a4JYldoQu7RAXHYPh7ijxVwzuc8= sha1:Mlib5uZEurxo/OsnOSRoJ0QRRVc= Xref: news.eternal-september.org comp.lang.vhdl:3388 Is Modelsim still not implementing VHDL 2008? I have some code with the "new" if ... generate with else branch but Modelsim 10.1e doesn't seem to support that. Or is it just that the Altera's Starter Edition doesn't support that? I don't have a Modelsim PE or SE installed right now... I tried case in generate as well but it didn't work any better. Example code, vcom -2008 says ** Error: generate_prob.vhdl(20): near "else": syntax error (line 20 is the else generate line.) LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity dummy is generic ( some_boolean_generic : boolean := false); port( clk : in std_logic; reset_n : in std_logic; dout : out std_logic ); end dummy; architecture dummy_arch of dummy is begin some_label: if some_boolean_generic = false generate dout <= '0'; else generate dout <= '1'; end generate some_label; end dummy_arch; From newsfish@newsfish Thu Aug 1 00:31:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 support in Modelsim? Date: Fri, 05 Dec 2014 07:58:10 -0500 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 5 Dec 2014 12:57:52 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="26753"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18bbg16YLUGd+UiAW9n2lio" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:TzXowgniWHuomjGIV6hVFRPezAg= Xref: news.eternal-september.org comp.lang.vhdl:3389 I don't know specifically about Modelsim, but in many tools the VHDL 2008 features have to be turned on in the options. Try nosing around to see if you can find that. Rick On 12/5/2014 7:48 AM, Anssi Saari wrote: > > Is Modelsim still not implementing VHDL 2008? I have some code with the > "new" if ... generate with else branch but Modelsim 10.1e doesn't seem > to support that. Or is it just that the Altera's Starter Edition doesn't > support that? I don't have a Modelsim PE or SE installed right now... I > tried case in generate as well but it didn't work any better. > > Example code, vcom -2008 says > ** Error: generate_prob.vhdl(20): near "else": syntax error > (line 20 is the else generate line.) > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > > entity dummy is > generic ( > some_boolean_generic : boolean := false); > port( > clk : in std_logic; > reset_n : in std_logic; > dout : out std_logic > ); > end dummy; > > architecture dummy_arch of dummy is > > begin > > some_label: if some_boolean_generic = false generate > dout <= '0'; > else generate > dout <= '1'; > end generate some_label; > > end dummy_arch; > -- Rick From newsfish@newsfish Thu Aug 1 00:31:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf04.am4!fx45.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 support in Modelsim? References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 141204-1, 04/12/2014), Outbound message X-Antivirus-Status: Clean Lines: 50 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1417789453 86.17.210.161 (Fri, 05 Dec 2014 14:24:13 UTC) NNTP-Posting-Date: Fri, 05 Dec 2014 14:24:13 UTC Organization: virginmedia.com Date: Fri, 05 Dec 2014 14:24:10 +0000 X-Received-Body-CRC: 2076097356 X-Received-Bytes: 2238 Xref: news.eternal-september.org comp.lang.vhdl:3390 On 05/12/2014 12:48, Anssi Saari wrote: > > Is Modelsim still not implementing VHDL 2008? I have some code with the > "new" if ... generate with else branch but Modelsim 10.1e doesn't seem > to support that. Or is it just that the Altera's Starter Edition doesn't > support that? I don't have a Modelsim PE or SE installed right now... I > tried case in generate as well but it didn't work any better. Modelsim 10.1e was released in June of 2013. Your code compiled OK in the latest 10.3d release. Modelsim SE is an obsolete product and replaced by Questa core. Regards, Hans www.ht-lab.com > > Example code, vcom -2008 says > ** Error: generate_prob.vhdl(20): near "else": syntax error > (line 20 is the else generate line.) > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > > entity dummy is > generic ( > some_boolean_generic : boolean := false); > port( > clk : in std_logic; > reset_n : in std_logic; > dout : out std_logic > ); > end dummy; > > architecture dummy_arch of dummy is > > begin > > some_label: if some_boolean_generic = false generate > dout <= '0'; > else generate > dout <= '1'; > end generate some_label; > > end dummy_arch; > From newsfish@newsfish Thu Aug 1 00:31:34 2024 X-Received: by 10.224.125.195 with SMTP id z3mr15143464qar.0.1417790813755; Fri, 05 Dec 2014 06:46:53 -0800 (PST) X-Received: by 10.140.18.178 with SMTP id 47mr31153qgf.9.1417790813695; Fri, 05 Dec 2014 06:46:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no4797805qac.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no4306138qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Dec 2014 06:46:53 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:630:340:100b:0:0:f:97dc; posting-account=2g_UWgoAAADr5MhVMVTej8gzC_urYh2K NNTP-Posting-Host: 2001:630:340:100b:0:0:f:97dc User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <65a5299f-ca90-4542-8932-d10d29addcb7@googlegroups.com> Subject: Design and Implementation of a PS/2 Receiver From: steverowedder@googlemail.com Injection-Date: Fri, 05 Dec 2014 14:46:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1472 X-Received-Body-CRC: 4086034508 Xref: news.eternal-september.org comp.lang.vhdl:3391 Hi There, Currently I have been set this project, I am really struggling with how to get going with it. If anyone can assist I would be greatly appreciated. It was a year since I have completed any work in VHDL. If anyone can assist we have been provided with PS2_DISPLAY.vhd, PS2_EXP.ucf, utils.vhd, VHDL_Template_entity.vhd, VHDL_Template_TB.vhd All files are below any help is greatly appreciated! Please assist, thanks in advance. Regards From newsfish@newsfish Thu Aug 1 00:31:34 2024 X-Received: by 10.182.87.39 with SMTP id u7mr15294608obz.4.1417790842769; Fri, 05 Dec 2014 06:47:22 -0800 (PST) X-Received: by 10.140.32.74 with SMTP id g68mr11658qgg.22.1417790842740; Fri, 05 Dec 2014 06:47:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no4807074igd.0!news-out.google.com!n9ni21qai.0!nntp.google.com!w8no4797826qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Dec 2014 06:47:22 -0800 (PST) In-Reply-To: <65a5299f-ca90-4542-8932-d10d29addcb7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:630:340:100b:0:0:f:97dc; posting-account=2g_UWgoAAADr5MhVMVTej8gzC_urYh2K NNTP-Posting-Host: 2001:630:340:100b:0:0:f:97dc References: <65a5299f-ca90-4542-8932-d10d29addcb7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Design and Implementation of a PS/2 Receiver From: steverowedder@googlemail.com Injection-Date: Fri, 05 Dec 2014 14:47:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 15 Xref: news.eternal-september.org comp.lang.vhdl:3392 On Friday, December 5, 2014 2:46:55 PM UTC, stever...@googlemail.com wrote: > Hi There, > > Currently I have been set this project, I am really struggling with how to get going with it. If anyone can assist I would be greatly appreciated. > > It was a year since I have completed any work in VHDL. > > If anyone can assist we have been provided with PS2_DISPLAY.vhd, PS2_EXP.ucf, utils.vhd, VHDL_Template_entity.vhd, VHDL_Template_TB.vhd > > All files are below any help is greatly appreciated! > > Please assist, thanks in advance. > > Regards Please ask for files and I can provide them From newsfish@newsfish Thu Aug 1 00:31:34 2024 X-Received: by 10.182.89.136 with SMTP id bo8mr15868034obb.7.1417793059644; Fri, 05 Dec 2014 07:24:19 -0800 (PST) X-Received: by 10.140.82.106 with SMTP id g97mr14781qgd.27.1417793059579; Fri, 05 Dec 2014 07:24:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no13818971igd.0!news-out.google.com!n9ni21qai.0!nntp.google.com!w8no4809154qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Dec 2014 07:24:19 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.55.108.200; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 5.55.108.200 References: <65a5299f-ca90-4542-8932-d10d29addcb7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Design and Implementation of a PS/2 Receiver From: Nikolaos Kavvadias Injection-Date: Fri, 05 Dec 2014 15:24:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1447 X-Received-Body-CRC: 1967781131 Xref: news.eternal-september.org comp.lang.vhdl:3393 Hi, can you set the context? 1) Which board do you target? (it's a Xilinx one since you use .ucf parlance) 2) Sharing the starting files will help. To sum this up, I can help you. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Thu Aug 1 00:31:35 2024 X-Received: by 10.236.4.106 with SMTP id 70mr20633640yhi.33.1417886784966; Sat, 06 Dec 2014 09:26:24 -0800 (PST) X-Received: by 10.140.17.82 with SMTP id 76mr424763qgc.5.1417886784909; Sat, 06 Dec 2014 09:26:24 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no4564444qap.1!news-out.google.com!n9ni21qai.0!nntp.google.com!w8no5056142qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Dec 2014 09:26:24 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.231.168.41; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 37.231.168.41 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> Subject: Throughput under Quartus II From: AA Injection-Date: Sat, 06 Dec 2014 17:26:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 3 Xref: news.eternal-september.org comp.lang.vhdl:3394 hi, How to calculate the throughput in Mbps of the design under Quartus II ? Thank you, From newsfish@newsfish Thu Aug 1 00:31:35 2024 X-Received: by 10.42.246.66 with SMTP id lx2mr26862614icb.0.1417915759083; Sat, 06 Dec 2014 17:29:19 -0800 (PST) X-Received: by 10.140.81.169 with SMTP id f38mr485677qgd.3.1417915759010; Sat, 06 Dec 2014 17:29:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no14661457igd.0!news-out.google.com!n9ni21qai.0!nntp.google.com!w8no5139620qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Dec 2014 17:29:18 -0800 (PST) In-Reply-To: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8f92d3d3-2611-46df-8e36-44203df3f68a@googlegroups.com> Subject: Re: Throughput under Quartus II From: KJ Injection-Date: Sun, 07 Dec 2014 01:29:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 8 Xref: news.eternal-september.org comp.lang.vhdl:3395 On Saturday, December 6, 2014 12:26:26 PM UTC-5, AA wrote: > hi, > How to calculate the throughput in Mbps of the design under Quartus II ? > > Thank you, Quartus does not calculate Mbps. Use a spreadsheet. KJ From newsfish@newsfish Thu Aug 1 00:31:35 2024 X-Received: by 10.236.1.37 with SMTP id 25mr24322332yhc.25.1417961944349; Sun, 07 Dec 2014 06:19:04 -0800 (PST) X-Received: by 10.140.108.5 with SMTP id i5mr5908qgf.11.1417961944291; Sun, 07 Dec 2014 06:19:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!w8no5236413qac.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no4744906qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Dec 2014 06:19:04 -0800 (PST) In-Reply-To: <8f92d3d3-2611-46df-8e36-44203df3f68a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.132.244.204; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 213.132.244.204 References: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> <8f92d3d3-2611-46df-8e36-44203df3f68a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0af828dc-255c-4798-ba33-0a0abf5cdb5f@googlegroups.com> Subject: Re: Throughput under Quartus II From: AA Injection-Date: Sun, 07 Dec 2014 14:19:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 12 Xref: news.eternal-september.org comp.lang.vhdl:3396 On Sunday, December 7, 2014 4:29:20 AM UTC+3, KJ wrote: > On Saturday, December 6, 2014 12:26:26 PM UTC-5, AA wrote: > > hi, > > How to calculate the throughput in Mbps of the design under Quartus II ? > > > > Thank you, > > Quartus does not calculate Mbps. Use a spreadsheet. > > KJ What do you mean by spreadsheet? May you please give me some details? From newsfish@newsfish Thu Aug 1 00:31:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!backlog3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 07 Dec 2014 08:24:51 -0600 From: "Andy Bartlett" Newsgroups: comp.lang.vhdl References: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> Subject: Re: Throughput under Quartus II Date: Sun, 7 Dec 2014 14:24:33 -0000 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 Message-ID: Lines: 19 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-bVE4DSsD6TxvCfPA5aA075zryITftJjpAy0HN93H0UNyosCxgrw1KL3C6PnPhuVXKAq53E/XL3Kt6Rc!ElMqr0RLZ/ByTCPzBZnMIWTbx8GNlOy4pTiTTAYUWPgzz7t9Pz0hf5Vt1NEaXF70s/7z9/YawfPR!FiMQqERgWmluPMCEpMO7O+Z5OKw= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1716 Xref: news.eternal-september.org comp.lang.vhdl:3397 "AA" wrote in message news:1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com... > hi, > How to calculate the throughput in Mbps of the design under Quartus II ? > > Thank you, Use the TimeQuest timing analyzer. This will give you the maximum internal clock rate you can run your design at. It will calculate the longest register-register prop. delay and include register setup and hold times. You can also get it to list all the internal props. starting at the longest of you want to sift through manually. As usual, RTFM. Andy From newsfish@newsfish Thu Aug 1 00:31:36 2024 X-Received: by 10.236.207.136 with SMTP id n8mr27517760yho.5.1417977181952; Sun, 07 Dec 2014 10:33:01 -0800 (PST) X-Received: by 10.50.79.197 with SMTP id l5mr173767igx.17.1417977181744; Sun, 07 Dec 2014 10:33:01 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!w8no5289385qac.0!news-out.google.com!jh1ni6649igb.0!nntp.google.com!h15no15058834igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Dec 2014 10:33:01 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.42.153.228; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 119.42.153.228 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: What could be a complete redesign of a microprocessor if one wrote it in VHDL From: Gandalf Injection-Date: Sun, 07 Dec 2014 18:33:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:3398 I was studying VHDL, when this thought struck me. What features do you think a new microprocessor written in VHDL must possess? If this is the wrong place to ask, kindly redirect me to the relevant group if possible. -Gandalf From newsfish@newsfish Thu Aug 1 00:31:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL Date: Sun, 07 Dec 2014 17:19:09 -0500 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 7 Dec 2014 22:18:49 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="24681"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ZDtfTDH8hfYG8C7W0gzHa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:f+/oWkZs161chuaKL8SL2USCPs4= Xref: news.eternal-september.org comp.lang.vhdl:3399 On 12/7/2014 1:33 PM, Gandalf wrote: > I was studying VHDL, when this thought struck me. What features do you think a new microprocessor written in VHDL must possess? If this is the wrong place to ask, kindly redirect me to the relevant group if possible. If you want to know what features to include in a processor design, pick a processor suitable for the job you want to do and use those. :) Before you consider rolling your own processor, take a look at the others out there. There are around 1000 of them so far. -- Rick From newsfish@newsfish Thu Aug 1 00:31:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Dave Higton Newsgroups: comp.lang.vhdl Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL Date: Sun, 07 Dec 2014 22:24:01 GMT Organization: Home Lines: 12 Message-ID: <76087c7254.DaveMeUK@my.inbox.com> References: X-Trace: individual.net KuyaAsU/Ot10+4pFCL7QEwPlXkZWKK2xk+AmIKUr1x9Y7pXMA= X-Orig-Path: my.inbox.com%DaveMeUK Cancel-Lock: sha1:GaQLf/RkzY209v0g771r5HOYi9k= User-Agent: Messenger-Pro/7.06 (MsgServe/7.06) (RISC-OS/5.20) NewsHound/v1.52-32 Xref: news.eternal-september.org comp.lang.vhdl:3400 In message Gandalf wrote: > I was studying VHDL, when this thought struck me. What features do you > think a new microprocessor written in VHDL must possess? If this is the > wrong place to ask, kindly redirect me to the relevant group if possible. Your question makes no sense at all. VHDL is a means to implement whatever features you wish. It has no limitations that would cause you to reduce the feature set. Dave From newsfish@newsfish Thu Aug 1 00:31:37 2024 X-Received: by 10.236.231.180 with SMTP id l50mr27615781yhq.4.1418006548132; Sun, 07 Dec 2014 18:42:28 -0800 (PST) X-Received: by 10.50.111.130 with SMTP id ii2mr187891igb.16.1418006547948; Sun, 07 Dec 2014 18:42:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!s7no4875999qap.1!news-out.google.com!jh1ni6649igb.0!nntp.google.com!h15no15265283igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Dec 2014 18:42:27 -0800 (PST) In-Reply-To: <76087c7254.DaveMeUK@my.inbox.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.42.153.228; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 119.42.153.228 References: <76087c7254.DaveMeUK@my.inbox.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45bec985-5545-4671-9310-6b522e4b5884@googlegroups.com> Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL From: Gandalf Injection-Date: Mon, 08 Dec 2014 02:42:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2018 X-Received-Body-CRC: 2965408117 Xref: news.eternal-september.org comp.lang.vhdl:3401 On Monday, December 8, 2014 3:54:11 AM UTC+5:30, Dave Higton wrote: > In message > Gandalf wrote: > > > I was studying VHDL, when this thought struck me. What features do you > > think a new microprocessor written in VHDL must possess? If this is the > > wrong place to ask, kindly redirect me to the relevant group if possible. > > Your question makes no sense at all. VHDL is a means to implement > whatever features you wish. It has no limitations that would cause > you to reduce the feature set. > > Dave Let me rephrase it- If you were to build a microprocessor today which is geared towards microcomputing platforms, what low level feature you would implement in addition to the standard PC,ALU, FPU etc. From newsfish@newsfish Thu Aug 1 00:31:37 2024 X-Received: by 10.236.26.5 with SMTP id b5mr26456353yha.15.1418006618619; Sun, 07 Dec 2014 18:43:38 -0800 (PST) X-Received: by 10.50.43.166 with SMTP id x6mr189404igl.5.1418006618429; Sun, 07 Dec 2014 18:43:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no5367479qac.0!news-out.google.com!jh1ni6649igb.0!nntp.google.com!h15no15265511igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Dec 2014 18:43:37 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.42.153.228; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 119.42.153.228 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL From: Gandalf Injection-Date: Mon, 08 Dec 2014 02:43:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1930 X-Received-Body-CRC: 2495878504 Xref: news.eternal-september.org comp.lang.vhdl:3402 On Monday, December 8, 2014 3:49:08 AM UTC+5:30, rickman wrote: > On 12/7/2014 1:33 PM, Gandalf wrote: > > I was studying VHDL, when this thought struck me. What features do you think a new microprocessor written in VHDL must possess? If this is the wrong place to ask, kindly redirect me to the relevant group if possible. > > If you want to know what features to include in a processor design, pick > a processor suitable for the job you want to do and use those. :) > > Before you consider rolling your own processor, take a look at the > others out there. There are around 1000 of them so far. > > -- > > Rick Hey thanks Rick, I already went through the MIPS documentation and the ARM documentation. Could you suggest me some more? From newsfish@newsfish Thu Aug 1 00:31:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL Date: Sun, 07 Dec 2014 23:25:43 -0500 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 8 Dec 2014 04:25:24 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="24198"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hRVjne98BaYhLImzPu/MD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:0Pqb3Ldd0EJOualkZq60NqzLFBw= Xref: news.eternal-september.org comp.lang.vhdl:3403 On 12/7/2014 9:43 PM, Gandalf wrote: > On Monday, December 8, 2014 3:49:08 AM UTC+5:30, rickman wrote: >> On 12/7/2014 1:33 PM, Gandalf wrote: >>> I was studying VHDL, when this thought struck me. What features do you think a new microprocessor written in VHDL must possess? If this is the wrong place to ask, kindly redirect me to the relevant group if possible. >> >> If you want to know what features to include in a processor design, pick >> a processor suitable for the job you want to do and use those. :) >> >> Before you consider rolling your own processor, take a look at the >> others out there. There are around 1000 of them so far. >> >> -- >> >> Rick > > Hey thanks Rick, > I already went through the MIPS documentation and the ARM documentation. Could you suggest me some more? I meant that home grown CPU designs. If you are serious about this the question is "why"? I've been down this path myself designing some number of iterations of MISC type processors. In the end it was educational, but only moderately useful. The smallest practical processor I've seen is the picoBlaze from Xilinx, but it is not HDL, but rather done with Xilinx primitives. So in that sense my CPU was the smallest I have seen that wasn't also dog slow, but not by much. There are lots of CPUs of a wide range of sizes all designed with different goals in mind. The question is, what is your goal? -- Rick From newsfish@newsfish Thu Aug 1 00:31:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: vhdl code review Date: 8 Dec 2014 09:01:08 GMT Lines: 36 Message-ID: X-Trace: individual.net bCHgHHldyqfNEQ7QZSk3TAoSxWPWEjTrGVMTrvcyDFGitTUByX X-Orig-Path: not-for-mail Cancel-Lock: sha1:11/8n+V1qDMhOJofc70Lgfj8g0o= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3404 Hi everyone, inspired by a nice read (the art of designing embedded systems - Jack Ganssle) I've started wondering what's the best way to perform code reviews for vhdl. Our projects are on the scale of ~100 KLOC (including testbenches) and if the number of lines reviewed per hour presented in the book is correct (150) it will mean that we will need to spend ~85 days in code reviews (considering a day made out of 8 working hours)! Considering that best practices mandate 4 people per review (moderator, reader. recorder, author), only review would cost one and a half man/year! Am I missing something? In order to make reviews effective how can we organize them? I've also seen a presentation on klabs.org which talked about reviewing the netlist as well, since that is what ultimately goes in the hardware. This will complexify the process enormously, to the point where no one single manager would be on board. Any insight on this subject? If you happen to know any material (articles/books/presentations) which is worth reading I'll be happy to have a look. Thanks a lot, Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Thu Aug 1 00:31:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx39.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 141208-0, 08/12/2014), Outbound message X-Antivirus-Status: Clean Lines: 49 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1418031960 86.17.210.161 (Mon, 08 Dec 2014 09:46:00 UTC) NNTP-Posting-Date: Mon, 08 Dec 2014 09:46:00 UTC Organization: virginmedia.com Date: Mon, 08 Dec 2014 09:45:59 +0000 X-Received-Body-CRC: 2706193000 X-Received-Bytes: 2603 Xref: news.eternal-september.org comp.lang.vhdl:3405 Hi Al, On 08/12/2014 09:01, alb wrote: > Hi everyone, > > inspired by a nice read (the art of designing embedded systems - Jack > Ganssle) I've started wondering what's the best way to perform code > reviews for vhdl. > > Our projects are on the scale of ~100 KLOC (including testbenches) and > if the number of lines reviewed per hour presented in the book is > correct (150) it will mean that we will need to spend ~85 days in code > reviews (considering a day made out of 8 working hours)! > > Considering that best practices mandate 4 people per review (moderator, > reader. recorder, author), only review would cost one and a half > man/year! > > Am I missing something? In order to make reviews effective how can we > organize them? > > I've also seen a presentation on klabs.org which talked about reviewing > the netlist as well, since that is what ultimately goes in the hardware. > This will complexify the process enormously, to the point where no one > single manager would be on board. > > Any insight on this subject? If you happen to know any material > (articles/books/presentations) which is worth reading I'll be happy to > have a look. > > Thanks a lot, > > Al I would suggest you look into linting tools as this is the only way to handle large amount of code. There are some really nice ones like Mentor's Design Checker, Atrenta's Spyclass, Aldec's Alint etc. Unfortunately these tools are not cheap but they are quit powerful and compared to the "old days" they do both static and dynamic linting (running synthesis in the background). Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:31:39 2024 X-Received: by 10.66.190.198 with SMTP id gs6mr29202357pac.4.1418044510027; Mon, 08 Dec 2014 05:15:10 -0800 (PST) X-Received: by 10.140.94.150 with SMTP id g22mr629115qge.0.1418044509978; Mon, 08 Dec 2014 05:15:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no5942362igd.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no4961893qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Dec 2014 05:15:09 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7a005a45-c7a9-4443-a991-4471da18c678@googlegroups.com> Subject: Re: vhdl code review From: Chris Higgs Injection-Date: Mon, 08 Dec 2014 13:15:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3406 On Monday, December 8, 2014 9:01:11 AM UTC, alb wrote: > inspired by a nice read (the art of designing embedded systems - Jack > Ganssle) I've started wondering what's the best way to perform code > reviews for vhdl. Great! It seems to have taken a while for code review to catch on for RTL development but done correctly you should find it beneficial. > Our projects are on the scale of ~100 KLOC (including testbenches) and > if the number of lines reviewed per hour presented in the book is > correct (150) it will mean that we will need to spend ~85 days in code > reviews (considering a day made out of 8 working hours)! If you view code review as a pure cost then it will never become ingrained in your process. Code review done correctly should *save* you time, though it's always difficult to quantify it should be noticeable. If you're trying to review 100 KLOC then you're very unlikely to succeed. Ideally code review should be done in parallel with development, reviewing small chunks at a time. It is probably better to focus on introducing a process for new development rather than trying to retrospectively review historical code. > Considering that best practices mandate 4 people per review (moderator, > reader. recorder, author), only review would cost one and a half > man/year! > > Am I missing something? In order to make reviews effective how can we > organize them? I think these best practices sound like they are from the 80s! It's generally accepted that review meetings generally don't work nearly so well as individual reviews. Group meetings are more suitable for architecture review where there is likely to be more discussion, but you should really try and separate the agreed architecture from the implementation review. Those reviewing the code should already be familiar with the agreed architecture. If you try putting 4 people in a room to perform a code review you it will not be very efficient (and most likely un-productive). Current software industry best-practice is for individuals to perform reviews at their own desks, using a software tool to track any discussion and actions. You asked for advice so here is mine: 1. Make code review part of the development process This is really important. Unless code review is "designed in" then it will always fall by the wayside because everybody is always too busy. The best way to achieve this is to engineer your development process. I would suggest the following: Use branches in your source control to enforce code review. Development happens on a branch, merges back onto stable are reviewed before they can be merged. You should also integrate this flow with your continuous integration such that your regression tests are run on the branch before it is merged too. Effectively you have a stable branch where to commit to it a review must have taken place and tests run. This can (and should) be enforced rather than optional. 2. Review small chunks of code If the cost of rewriting the entire chunk of code being reviewed is perceived as too high then it's too late to be doing the review. Ideally you want to keep reviews under ~500 LOC. 3. Use decent tools to assist There are plenty of free and non-free tools available (reviewboard, phabricator, crucible, even gitlab). These will track comments and discussions, report test results etc. At bare minimum you need something that ties into your source control, but there are significant benefits from integrating into your bug-tracking system and continuous integration / regression tests too. 4. Don't underestimate the cultural adjustment required Often introducing code reviews can cause difficulties. Some people don't like having flaws in their code pointed out, some people will become defensive, some people will be aggressively anal in the review. In my experience hardware engineers are more prone to rejecting the idea of code reviews than pure software engineers. The key thing to remember is that code review serves multiple purposes. It should improve the quality of your code-base. It should improve the teams familiarity with the code-base. It should improve the skill levels of all your engineers as they learn from each other. To achieve this however the code review needs to be viewed as beneficial by the engineers as well as the management! For further reading this paper has some real data and interesting commentary: http://smartbear.com/SmartBear/media/pdfs/best-kept-secrets-of-peer-code-review.pdf Pretty much everything written about software code-review will be relevant to you because at the end of the day RTL development is identical to software development... we just have much longer compile times ;) Thanks, Chris From newsfish@newsfish Thu Aug 1 00:31:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review Date: 8 Dec 2014 13:29:08 GMT Lines: 27 Message-ID: References: X-Trace: individual.net qrQ5Ugofz3+bVMfk4BqCnAGfb8bjVRJQQL9u0PcxlvClVQTPL5 X-Orig-Path: not-for-mail Cancel-Lock: sha1:KSVPTonggbVKgJ5RIWBr3P0piRA= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3407 Hi Hans, In article you wrote: [] > I would suggest you look into linting tools as this is the only way to > handle large amount of code. There are some really nice ones like > Mentor's Design Checker, Atrenta's Spyclass, Aldec's Alint etc. linting tools are essential in order to verify coding rules, but won't lack of synchronization, asynchronous logic complexity, race conditions, wrong initialization and all the assumptions the coder has chosen when writing the code. Moreover comments are seldom analyzed and they are an important part of the code quality. > Unfortunately these tools are not cheap but they are quit powerful and > compared to the "old days" they do both static and dynamic linting > (running synthesis in the background). I'll give a look at those since they certainly can provide a lot of useful checking that can be skimmed off the review table (essentially the build should be clean, no errors, no warnings unless justified), but there are other aspects that can't be covered with the tool and on top of my small list above I suspect there are even more. Al From newsfish@newsfish Thu Aug 1 00:31:39 2024 X-Received: by 10.42.52.208 with SMTP id k16mr32980711icg.23.1418048065299; Mon, 08 Dec 2014 06:14:25 -0800 (PST) X-Received: by 10.140.19.225 with SMTP id 88mr3315qgh.19.1418048065227; Mon, 08 Dec 2014 06:14:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no15523126igd.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no4972597qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Dec 2014 06:14:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Throughput under Quartus II From: KJ Injection-Date: Mon, 08 Dec 2014 14:14:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3408 On Sunday, December 7, 2014 9:24:53 AM UTC-5, Andy Bartlett wrote: > > "AA" > > hi, > > How to calculate the throughput in Mbps of the design under Quartus II ? > > > > Thank you, > > Use the TimeQuest timing analyzer. This will give you the maximum internal > clock rate you can run your design at. That will not give you "throughput in Mbps", it will only give you clock rate in MHz. Not at all the same thing. KJ From newsfish@newsfish Thu Aug 1 00:31:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review Date: 8 Dec 2014 23:32:52 GMT Lines: 251 Message-ID: References: <7a005a45-c7a9-4443-a991-4471da18c678@googlegroups.com> X-Trace: individual.net RRDuCX0/LCDqs6gEJ+6IhQPujKHo2CrBClJ5HrkWK6mUb4QhL/ X-Orig-Path: not-for-mail Cancel-Lock: sha1:6USE3KBLkqkQkKVuLxuFYCTkBU4= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3409 Hi Chris, Chris Higgs wrote: [] > Great! It seems to have taken a while for code review to catch on for RTL > development but done correctly you should find it beneficial. good to know that I'm not alone in my madness! >> Our projects are on the scale of ~100 KLOC (including testbenches) and >> if the number of lines reviewed per hour presented in the book is >> correct (150) it will mean that we will need to spend ~85 days in code >> reviews (considering a day made out of 8 working hours)! > > If you view code review as a pure cost then it will never become ingrained > in your process. Code review done correctly should *save* you time, > though it's always difficult to quantify it should be noticeable. to be ingrained in the process, management needs to be onboard, otherwise, by definition, it won't be ingrained. I'm certainly not wanting to reduce code review to a mere *cost*, but this is how some not really enlightened manager may perceive it. Moreover, technical staff as well should be the first driving force since they should see the immediate bbenefit of it and not just another burden on their shoulders. > > If you're trying to review 100 KLOC then you're very unlikely to succeed. > Ideally code review should be done in parallel with development, reviewing > small chunks at a time. It is probably better to focus on introducing a > process for new development rather than trying to retrospectively review > historical code. absolutely. The 100 KLOC is the size of a medium size project here in house and regardless of the way we integrate code review in our process at the end of the day we will still need to review it all, i.e. an extra amount of hours to budget in. >> Considering that best practices mandate 4 people per review (moderator, >> reader. recorder, author), only review would cost one and a half >> man/year! [] > It's generally accepted that review meetings generally don't work nearly > so well as individual reviews. Group meetings are more suitable for > architecture review where there is likely to be more discussion, but you > should really try and separate the agreed architecture from the > implementation review. Those reviewing the code should already be > familiar with the agreed architecture. Agreed, it is not uncommon indeed that people tend to discuss architectural choices instead of the implementation details, which invalidate the whole review and make them ineffective. A run down on the architecture should be preparatory for all the participants. We are trying to separate the verification effort completely from the development one, introducing at least two people, plus the technical coordinator who supervise the whole development, but rarely write any code. Both the verification engineer and the designer know the specifications as well as the architecture. The verification engineer could be part of the reviewers, but unfortunately his/her experience is more shaped around verification techniques. The same could be said for the RTL designer reviewing the testbench code. Asking people who are not part of the project to be educated on the architecture and the specs is a major drawback, it essentially would require the whole FPGA team to know everything about everything, which essentially is equivalent to knowing nothing about anything... :-/ [] > Current software industry best-practice is for individuals to perform > reviews at their own desks, using a software tool to track any discussion > and actions. I understand your point and I didn't think about having people sitting around a table and discussing hours about why the signal name has not been written in 'camel case'. We have formal round table reviews for hardware, with a checklist and the QA noting down any deviation, but the complexity you can get with 10M gates component is not comparable (at least in our designs the hardware is never driving the schedule) > 1. Make code review part of the development process > > This is really important. Unless code review is "designed in" then it > will always fall by the wayside because everybody is always too busy. The > best way to achieve this is to engineer your development process. I would > suggest the following: > > Use branches in your source control to enforce code review. Development > happens on a branch, merges back onto stable are reviewed before they can > be merged. By definition a ready to be integrated feature should be verified before the merging take place. If the code is already verified the code review may not be so attractive (the manager: the code is tested, why should we spend more time on it?). IMO instead, code review should take place before testing (but after elaboration *and* synthesis). IIRC effectiveness of code reviews are essentially due to the fact that a bug cost less if found early and there's no earlier than 'as soon as' the code is ready. Sometimes it costs more to run simulations that do not work because of simple bugs rather than having a pair of eyes reading the code. > You should also integrate this flow with your continuous > integration such that your regression tests are run on the branch before > it is merged too. Ok, this sentence by itself can start a whole new thread )on continuous integration), so I'll probably launch the discussion separately in the coming days. I think we've mildly talked about this in a not so distant past, but I'm still stuck where I was then (priorities are changing at a fast pace!). > Effectively you have a stable branch where to commit to it a review must > have taken place and tests run. This can (and should) be enforced rather > than optional. It's easy to enforce test runs with pre-hooks before merging onto mainstream, less evident how to force in the process the review. As said earlier the verification phase should not even start before code review is performed, but I'm asking myself if the review should be an iterative process not so different from the verification effort (test, modify, test). And when do we consider code review over? All lines of code have been reviewed, some where tagged as to be modified, some others will likely show bugs during simulation, should the code be reviewed after all the mods, along the mods? > 2. Review small chunks of code > > If the cost of rewriting the entire chunk of code being reviewed is > perceived as too high then it's too late to be doing the review. Ideally > you want to keep reviews under ~500 LOC. Divide and Conquer. The architectural phase is critical since is where we divide functions and establish their interconnections/interactions. Every functional block should also be divided in relatively manageable units which losely interact (micro architecture). Maybe we should envision multiple branches for each unit which all merge to a feature branch (that would eventually merge to the stable branch). It would be rather difficult though to break functionality with the number of lines of code as a delimiter, still I understand your idea and in practice most of our files (one entity per file) are around that number (with the exeception of testbenches which are usually longer and I believe wrongly structured!). > 3. Use decent tools to assist > > There are plenty of free and non-free tools available (reviewboard, > phabricator, crucible, even gitlab). These will track comments and > discussions, report test results etc. At bare minimum you need something > that ties into your source control, but there are significant benefits > from integrating into your bug-tracking system and continuous integration > / regression tests too. IIRC reviewboard should be easy to integrate with bugzilla, while I don't really see how to integrate it with the CI. Comments from reviewboard shall translate into bugs which should be treated before merging activities. This approach calls for somebody responsible for merging features in the trunk, verifying that no pending bugs are crawling under the carpet! > 4. Don't underestimate the cultural adjustment required > > Often introducing code reviews can cause difficulties. Some people don't > like having flaws in their code pointed out, some people will become > defensive, some people will be aggressively anal in the review. In my > experience hardware engineers are more prone to rejecting the idea of code > reviews than pure software engineers. Agreed. I see it frequently, everyone considering his/her domain the ultimate response to human struggles. I see lots of subjects which are common to both world, but even talented people often consider software practices like 'abstraction' as something to be rejected 'because I care about how many gates my code produces'. > The key thing to remember is that code review serves multiple purposes. Yet I've haven't found what should we focus on when reviewing the code. For what concerns coding rules maybe a fine tuned linting tool would solve the issue, but then? Here's my very small list off the top of my head (without no specific order): - entity interfaces types - wrongly initialized signals/variables - conditions for signals/states changes - clock domain transitions - resynchronization of asynchronous logic (if and when needed) - comments clarity - use of 'standard' functions/procedures - rewrite reused functional blocks into functions/procedures - do not discuss about architectural choices! - reasonable number of states for FSM, otherwise break in hierarchical FSM. Anything to add or to remove? > It should improve the quality of your code-base. It should improve the > teams familiarity with the code-base. It should improve the skill levels > of all your engineers as they learn from each other. To achieve this > however the code review needs to be viewed as beneficial by the engineers > as well as the management! Unfortunately too often management has rejected the idea to have a better quality code because 'it won't work better' (or at least is hard to prove). On top of it they often turn a blind eye on upfront efforts and prefers quick and dirty solution to ship in time. The lesser important argument is about skill level improvement, the answer would simply be 'not on my project'. No rational argument would be valid against such management. Still something needs to be done to improve our inability to tackle complexity at a larger scale. > For further reading this paper has some real data and interesting > commentary: http://smartbear.com/SmartBear/media/pdfs/best-kept-secrets-of-peer-code-review.pdf thanks for the link, someday I should start practice 'speed reading' to be more effective on the amount of stuff I *have to read* (it's piling up!). > Pretty much everything written about software code-review will be relevant > to you because at the end of the day RTL development is identical to > software development... we just have much longer compile times ;) Agreed and anyone rejecting the similarities because 'every flop counts' will not keep up with the increase of complexity. Even in a very conservative market like 'space', nowadays devices are monsters that allow complex SoC with multiple processors running and peripherals offloading the software stack. Willing to keep control over the register is IMO not affordable. In our house we are crazy about optimization in the very early phases, believing that if we can spare some gates on a functional block we have made the day. This approach is rather shortsighted since optimization should be looked at from a different perspective, often at system level, maybe moving functions from hardware to software, maybe rearchitecting the coupling between functions. On top of it, why optimizing a function whose impact is only 5% of the overall resource need? Donald Knuth wrote about 'premature optimization' as the 'root of all evil' and I could not agree more. Al From newsfish@newsfish Thu Aug 1 00:31:40 2024 X-Received: by 10.66.152.8 with SMTP id uu8mr31904758pab.24.1418093633893; Mon, 08 Dec 2014 18:53:53 -0800 (PST) X-Received: by 10.140.33.229 with SMTP id j92mr82748qgj.7.1418093633548; Mon, 08 Dec 2014 18:53:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no6206544igd.0!news-out.google.com!n9ni43qai.0!nntp.google.com!w8no5594770qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Dec 2014 18:53:53 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <95b23918-ff71-4aac-856f-cdf155e87974@googlegroups.com> Subject: Re: vhdl code review From: Andy Injection-Date: Tue, 09 Dec 2014 02:53:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2863 X-Received-Body-CRC: 3553276090 Xref: news.eternal-september.org comp.lang.vhdl:3410 A couple of things we have found helpful for PL code reviews: 1. As already mentioned, a good (set of) linting tools with customized rule= s. The results from running these tools should be reviewed. This speeds up = verification of compliance to local design and coding standards.=20 2. A good IDE is immensely helpful especially when reviewing code I am not = familiar with (as an independent reviewer). They can make it easy to find o= bject definitions, etc. as well as extensive syntax highlighting (especiall= y Sigasi for VHDL). These often provide graphical and outline views, where-= used info, etc. 3. Code complexity analysis tools like SciTools Understand can help target = effective reviews commensurate with complexity/size of code. These tools al= so provide helpful graphical views of the code base. 4. Above all, invite younger, less experienced developers to reviews. This = is an excellent way for them to learn, and pays big dividends down the road= . 5. Don't forget to review constraints files, simulation/synthesis/place/rou= te logs, code/functional coverage results, etc.=20 6. Unless you have specific tools or items for which you wish to review net= lists, I don't recommend it. Reviewing log files is more cost effective. 7. Review issue tracking tool reports (types of issues found, how/when foun= d, how fixed, etc. This information is very useful for process improvement. As mentioned earlier, these are all pretty normal for experienced SW person= nel, but if your organization has not embraced the SW aspects of PL/ASIC de= velopment, much of this will seem foreign to participants and to management= . Additional training may be in order (how to prepare for and conduct code = reviews.) Andy From newsfish@newsfish Thu Aug 1 00:31:40 2024 X-Received: by 10.43.57.79 with SMTP id wf15mr1375865icb.24.1418111501692; Mon, 08 Dec 2014 23:51:41 -0800 (PST) X-Received: by 10.140.84.170 with SMTP id l39mr761qgd.33.1418111501660; Mon, 08 Dec 2014 23:51:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6279733igd.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no5144578qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Dec 2014 23:51:41 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=89.210.188.129; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 89.210.188.129 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL From: Nikolaos Kavvadias Injection-Date: Tue, 09 Dec 2014 07:51:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3411 Hi Gandalf and Rick, > >>> I was studying VHDL, when this thought struck me. What features do yo= u think a new microprocessor written in VHDL must possess? If this is the w= rong place to ask, kindly redirect me to the relevant group if possible. There are lots of new designs ranging from tiny micros, to DSP/VLIWs, vecto= r processors, embedded multicores etc. As a shameless plug, you can have a look at my processor, ByoRISC. ByoRISC = was conceived some ~8 years ago as a Nios-II or MIPS32 on steroids. Its des= ign is based around cheap, internal, multi-port storage for registers, the = kind of one that might be practical in FPGAs (and this depends). It is a sc= alable design (with full data forwarding from everywhere to everywhere) tha= t can be configured at compile/elaboration-time for a different maximum num= ber of read and write operands for the supported instructions. I was able t= o use it for at least up to 8 read and 8 write ports. For 8/8, MHz degradat= ion was 15-20% to a RISC-like with 2/1 read/write ports, but overall execut= ion time benefit was around 2.5x-4x for my application set (ByoRISC was bet= ter). ByoRISC is a good testbed for exercising custom instructions and stuf= fing it with additional tightly-coupled functional units. ByoRISC was also able to sustain better performance than some VLIWs, e.g. t= he HP Playdoh/VEX that I had used in experiments. Some readings:=20 http://www.nkavvadias.com/publications/kavvadias_vlsisoc08.pdf http://arxiv.org/abs/1403.6632 There was also its sister EDA tool, YARDstick for identifying custom instru= ctions (though not fully integrated into a single flow with ByoRISC develop= ment tools):=20 http://www.nkavvadias.com/yardstick/index.html The world has moved to embedded multicore of course and ByoRISC might not b= e too elemental as a brick, but it is a worthy experiment of a scalable ASI= P with performance at the 4/8-way VLIW range. Best regards Nikolaos Kavvadias http://www.nkavvadias.com > >> > >> If you want to know what features to include in a processor design, pi= ck > >> a processor suitable for the job you want to do and use those. :) > >> > >> Before you consider rolling your own processor, take a look at the > >> others out there. There are around 1000 of them so far. > >> > >> -- > >> > >> Rick > > > > Hey thanks Rick, > > I already went through the MIPS documentation and the ARM documentation= . Could you suggest me some more? >=20 > I meant that home grown CPU designs. >=20 > If you are serious about this the question is "why"? I've been down=20 > this path myself designing some number of iterations of MISC type=20 > processors. In the end it was educational, but only moderately useful.= =20 > The smallest practical processor I've seen is the picoBlaze from=20 > Xilinx, but it is not HDL, but rather done with Xilinx primitives. So=20 > in that sense my CPU was the smallest I have seen that wasn't also dog=20 > slow, but not by much. There are lots of CPUs of a wide range of sizes= =20 > all designed with different goals in mind. The question is, what is=20 > your goal? >=20 > --=20 >=20 > Rick From newsfish@newsfish Thu Aug 1 00:31:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe001.ams.xsnews.nl!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 09 Dec 2014 02:51:35 -0600 Date: Tue, 09 Dec 2014 08:51:23 +0000 From: MK User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL References: <76087c7254.DaveMeUK@my.inbox.com> <45bec985-5545-4671-9310-6b522e4b5884@googlegroups.com> In-Reply-To: <45bec985-5545-4671-9310-6b522e4b5884@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 27 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-q1CWcBmRsnHwZM+7YxNMNoIZNrH+NvxNBRLcaI8QF/EuYWjNfgkkQhVaPgbFULst9lyKlpzI5ySQmC1!btfc813XZWQa/wZZchN6qMe/cQnNjJG5gjegqz1fhnwDyXHyASh27qE9n8jO9Wg7Faw5c9ys9Nc= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2539 Xref: news.eternal-september.org comp.lang.vhdl:3412 On 08/12/2014 02:42, Gandalf wrote: > On Monday, December 8, 2014 3:54:11 AM UTC+5:30, Dave Higton wrote: >> In message >> Gandalf wrote: >> >>> I was studying VHDL, when this thought struck me. What features do you >>> think a new microprocessor written in VHDL must possess? If this is the >>> wrong place to ask, kindly redirect me to the relevant group if possible. >> >> Your question makes no sense at all. VHDL is a means to implement >> whatever features you wish. It has no limitations that would cause >> you to reduce the feature set. >> >> Dave > > Let me rephrase it- If you were to build a microprocessor today which is geared towards microcomputing platforms, what low level feature you would implement in addition to the standard PC,ALU, FPU etc. > The question still doesn't make much sense - the only two valid reasons I can imagine for developing yet another VHDL processor are: 1) because you want features that you can't get in anything else 2) for research/education In either case the required features are driving the project. Michael Kellett From newsfish@newsfish Thu Aug 1 00:31:41 2024 X-Received: by 10.66.142.226 with SMTP id rz2mr34138390pab.36.1418143163064; Tue, 09 Dec 2014 08:39:23 -0800 (PST) X-Received: by 10.140.84.21 with SMTP id k21mr176260qgd.6.1418143162975; Tue, 09 Dec 2014 08:39:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no16217776igd.0!news-out.google.com!r1ni44qat.1!nntp.google.com!w8no5730575qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 9 Dec 2014 08:39:22 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.99.0.254; posting-account=sKIcugkAAADuN1jxTpi0uMTrPcQWONSB NNTP-Posting-Host: 195.99.0.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Does writeline consume the line? From: davehigton14@gmail.com Injection-Date: Tue, 09 Dec 2014 16:39:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 13 X-Received-Bytes: 1696 X-Received-Body-CRC: 1459603799 Xref: news.eternal-september.org comp.lang.vhdl:3413 The general process for writing to a file involves a write to a line, followed by a writeline to a file. But does the writeline consume the contents of the line? I think it does. I'm doing a multi-channel filter simulation. I'm writing the line to a Results.txt file if the channel is the active channel; then I'm writing the same line to one of eight Results.txt files according to the channel number. I was surprised to see that Results0.txt is empty when the active channel is channel 0. I infer that this means that writeline to the active channel consumes the contents of the line so that there is nothing left to write to Results0.txt. Dave From newsfish@newsfish Thu Aug 1 00:31:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review Date: 9 Dec 2014 21:55:35 GMT Lines: 96 Message-ID: References: <95b23918-ff71-4aac-856f-cdf155e87974@googlegroups.com> X-Trace: individual.net zIBtDhhOuyNcSg0r3jAlownuyD8e8kEuQS9pqHl87toeRtSD/O X-Orig-Path: not-for-mail Cancel-Lock: sha1:AvjnOrcGg1P3E6axQNXp90z3pMo= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3414 Hi Andy, Andy wrote: [] > 1. As already mentioned, a good (set of) linting tools with customized > rules. The results from running these tools should be reviewed. This > speeds up verification of compliance to local design and coding > standards. Having coding rules would be the first step toward a better code quality, I have always have hard time to understand why practices so well recognized are simply neglected in the name of 'lack of time'. > 2. A good IDE is immensely helpful especially when reviewing code I am > not familiar with (as an independent reviewer). They can make it easy > to find object definitions, etc. as well as extensive syntax > highlighting (especially Sigasi for VHDL). These often provide > graphical and outline views, where-used info, etc. I am pretty much accustomed with emacs and etags which help me browse the code base rather quickly. Amongst 8 people we have I guess 6 editors (moreover I'm not one of them) and each of them is religiously addicted to his preferred one (http://xkcd.com/378/). > 3. Code complexity analysis tools like SciTools Understand can help > target effective reviews commensurate with complexity/size of code. > These tools also provide helpful graphical views of the code base. Thanks for the hint, I'll give it a try on a large (and unstructured) code base to see how it can help. I heard several times that subcontracted code is a nightmare to maintain because of the lack of detailed knowledge of it. Tools like these may assist in the code analysis and in the familiarization process. Same happens when, due to workload and/or priorities, designers are brought in from nowhere and asked to *contribute* without even knowing where to start from. > 4. Above all, invite younger, less experienced developers to reviews. > This is an excellent way for them to learn, and pays big dividends > down the road. This is what's called investment...depending on the historical or emotional phases, management may be interfering a lot on this point. > 5. Don't forget to review constraints files, > simulation/synthesis/place/route logs, code/functional coverage > results, etc. To my understanding reports are already way down the road w.r.t. to code review. They certainly need to be reviewed and in our case they are also contractually required to appear in our documentation set (verification report, validation report, detailed design report...). While their importance is crucial in the intent to ship a sound project, IMO they are not part of the code itself. OTOH I do agree that constraint files need to be reviewed as code. I'd like to separate reviewing of what goes in, from what goes out. > 6. Unless you have specific tools or items for which you wish to > review net lists, I don't recommend it. Reviewing log files is more > cost effective. I've personally found netlist analysis a big PITA and I prefer to spend time in describing behavior at higher level and *verify* it works correctly. We have post-synth and post-layout sims [1] to make sure the generated netlist is behaving as expected. How could you possibly review a netlist on a 2M gates device with 92% occupancy? > 7. Review issue tracking tool reports (types of issues found, how/when > found, how fixed, etc. This information is very useful for process > improvement. Unfortunately our issue tracking tool is extremely losely configured and this type of information is extremely difficult to extract. I believe there's another whole area of improvement there. What we tend to do though is to review the bug fix ASAP in our corners and if somebody is not satisfied with the bug closure it will reopen it, asking for clarifications or additional mods. > As mentioned earlier, these are all pretty normal for experienced SW > personnel, but if your organization has not embraced the SW aspects of > PL/ASIC development, much of this will seem foreign to participants > and to management. Additional training may be in order (how to prepare > for and conduct code reviews.) Cultural inertia is certainly something that doesn't ease introduction of new philosophies and approaches. Training might be done in house and should not take too much efforts to bring people on board in small steps. If you have any extra suggestion directly related to aspects of the code beyond the ones I listed in a previous message in this thread I'd be happy to hear them. Al [1] ECSS-Q-60-02C requires full coverage of post-layout sims according to the verification plan which specifies which test covers which requirement and how. From newsfish@newsfish Thu Aug 1 00:31:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 09 Dec 2014 17:46:38 -0600 Date: Tue, 09 Dec 2014 23:46:38 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Does writeline consume the line? References: In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-ID: <_dKdnQc5yqhDFBrJnZ2dnUVZ7rSdnZ2d@brightview.co.uk> Lines: 40 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-o4xbtk0BamOhVBgxMy9ORePB29VhTXzxm8gOUZNQ2AgON356Q68BjHLIEgYnBGV3NStjB2+cc1HgTpn!FoHEczghLUI0/aIPJhVIukmE2/fYN4vhoDUxgK5BJbPMqaPWPJcm2veUYxSlLqpH+G4lZJQ23Il0!w2BsvXQ5UvJFkcJDB67UW/55cVk= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2249 Xref: news.eternal-september.org comp.lang.vhdl:3415 On 09/12/14 16:39, davehigton14@gmail.com wrote: > The general process for writing to a file involves a write to a > line, followed by a writeline to a file. But does the writeline > consume the contents of the line? > > I think it does. I'm doing a multi-channel filter simulation. > I'm writing the line to a Results.txt file if the channel is the > active channel; then I'm writing the same line to one of eight > Results.txt files according to the channel number. I was > surprised to see that Results0.txt is empty when the active > channel is channel 0. I infer that this means that writeline > to the active channel consumes the contents of the line so that > there is nothing left to write to Results0.txt. > > Dave > Yes, writeline empties the line buffer. You can make a copy of the buffer if you know/realise that it is access string, e.g. process variable L1 : line; variable l2:: line; begin write(L1, fred); L2 := new string'(L1.all); writeline(F, L1); writeline(F2, L2); regards Alan -- Alan Fitch From newsfish@newsfish Thu Aug 1 00:31:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review Date: Tue, 09 Dec 2014 18:31:52 -0800 Organization: Aioe.org NNTP Server Lines: 13 Message-ID: References: NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3416 > inspired by a nice read (the art of designing embedded systems - Jack > Ganssle) I've started wondering what's the best way to perform code > reviews for vhdl. Among the other suggestion this thread present you, I suggest you look up Fagan inspections. It's a formalized process for reviews. If your management supports allocating the resources (people) to participate, you're in a good position. We've used Fagan inspections with great results for circuit designs and C code reviews. It should work just fine for HDL inspections. JJS From newsfish@newsfish Thu Aug 1 00:31:42 2024 X-Received: by 10.42.52.208 with SMTP id k16mr6665092icg.23.1418199971039; Wed, 10 Dec 2014 00:26:11 -0800 (PST) X-Received: by 10.140.109.9 with SMTP id k9mr14425qgf.17.1418199970906; Wed, 10 Dec 2014 00:26:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6688376igd.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no5383319qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 00:26:10 -0800 (PST) In-Reply-To: <_dKdnQc5yqhDFBrJnZ2dnUVZ7rSdnZ2d@brightview.co.uk> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.99.0.254; posting-account=sKIcugkAAADuN1jxTpi0uMTrPcQWONSB NNTP-Posting-Host: 195.99.0.254 References: <_dKdnQc5yqhDFBrJnZ2dnUVZ7rSdnZ2d@brightview.co.uk> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54577a10-7d42-43a2-9c3e-21d156aaef5f@googlegroups.com> Subject: Re: Does writeline consume the line? From: davehigton14@gmail.com Injection-Date: Wed, 10 Dec 2014 08:26:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3417 On Tuesday, December 9, 2014 11:46:41 PM UTC, Alan Fitch wrote: > On 09/12/14 16:39, Dave Higton wrote: > > The general process for writing to a file involves a write to a > > line, followed by a writeline to a file. But does the writeline > > consume the contents of the line? > > > > I think it does. I'm doing a multi-channel filter simulation. > > I'm writing the line to a Results.txt file if the channel is the > > active channel; then I'm writing the same line to one of eight > > Results.txt files according to the channel number. I was > > surprised to see that Results0.txt is empty when the active > > channel is channel 0. I infer that this means that writeline > > to the active channel consumes the contents of the line so that > > there is nothing left to write to Results0.txt. > > > > Dave > > > > Yes, writeline empties the line buffer. > > You can make a copy of the buffer if you know/realise that it is access > string, e.g. > > process > variable L1 : line; > variable l2:: line; > > begin > > write(L1, fred); > L2 := new string'(L1.all); > writeline(F, L1); > writeline(F2, L2); Thanks, Alan, for the confirmation, and for the simple solution. Dave From newsfish@newsfish Thu Aug 1 00:31:42 2024 X-Received: by 10.42.149.133 with SMTP id w5mr6614017icv.14.1418205484190; Wed, 10 Dec 2014 01:58:04 -0800 (PST) X-Received: by 10.140.101.247 with SMTP id u110mr16237qge.18.1418205484053; Wed, 10 Dec 2014 01:58:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!news.glorb.com!h15no16658782igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5396631qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 01:58:03 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=31.149.224.137; posting-account=F4r4WAoAAABE6olGH00oV5e4r70VrO8z NNTP-Posting-Host: 31.149.224.137 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Looking for expert VHDL books From: msteerefolk@gmail.com Injection-Date: Wed, 10 Dec 2014 09:58:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 14 Xref: news.eternal-september.org comp.lang.vhdl:3418 The past few weeks I'm often looking for information on very specific subje= cts. The more general books don't include these subjects, so I'm looking fo= r a list of specialised VHDL books. I'm currently looking specifically for books including the topics of bidire= ctional buses (most books skip this part because they're bad practice, but = they're essential for USB communication) optimizing LUTs, FPGAs and transmi= ssion protocols and more topics like that. Finding a list of beginner books is quite easy, but I'm specifically lookin= g for the higher-level reading. A few months ago I've studied Digital Signal Processing with Field Programm= able Gate Arrays (Uwe Meyer-Baese, ISBN 978-3-642-45308-3), which is exactl= y the type of book I'm looking for. Now I want more of those. From newsfish@newsfish Thu Aug 1 00:31:43 2024 X-Received: by 10.236.2.226 with SMTP id 62mr3047199yhf.1.1418207227338; Wed, 10 Dec 2014 02:27:07 -0800 (PST) X-Received: by 10.140.21.20 with SMTP id 20mr259qgk.30.1418207227283; Wed, 10 Dec 2014 02:27:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no5401175qap.1!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5401172qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 02:27:07 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.39.183.137; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 212.39.183.137 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> Subject: Help with Architecture design From: Olalekan Shittu Injection-Date: Wed, 10 Dec 2014 10:27:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 24 Xref: news.eternal-september.org comp.lang.vhdl:3419 Good morning everyone, I am a newbie to VHDL without background in programming language. Library ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity Sorter IS Port ( C: IN std_logic_vector (3 downto 0); Sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic ); end sorter; How do I declare the architecture given the condition that all the outputs of the sorter are set to Zero when Sel is different from 4 while the output = 1 if sel =4. I use Modelsim 10.3d version. Thanks From newsfish@newsfish Thu Aug 1 00:31:43 2024 X-Received: by 10.68.219.198 with SMTP id pq6mr3150433pbc.8.1418207427453; Wed, 10 Dec 2014 02:30:27 -0800 (PST) X-Received: by 10.140.85.134 with SMTP id n6mr16054qgd.20.1418207427405; Wed, 10 Dec 2014 02:30:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no16673136igd.0!news-out.google.com!r1ni50qat.1!nntp.google.com!w8no5893592qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 02:30:27 -0800 (PST) In-Reply-To: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.39.183.137; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 212.39.183.137 References: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e168750-fc4c-4140-94fd-16cb55f3a337@googlegroups.com> Subject: Re: Help with Architecture design From: Olalekan Shittu Injection-Date: Wed, 10 Dec 2014 10:30:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3420 On Wednesday, 10 December 2014 11:27:08 UTC+1, Olalekan Shittu wrote: > Good morning everyone, > > I am a newbie to VHDL without background in programming language. > > Library ieee; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use IEEE.std_logic_unsigned.all; > > entity Sorter IS > Port ( C: IN std_logic_vector (3 downto 0); > Sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); > out0: out std_logic; > out1: out std_logic; > out2: out std_logic; > out3: out std_logic > ); > end sorter; > > > How do I declare the architecture given the condition that all the outputs of the sorter are set to Zero when Sel is different from 4 while the output = 1 if sel =4. > > I use Modelsim 10.3d version. > > Thanks Books for beginners can also be recommended to aid my learning From newsfish@newsfish Thu Aug 1 00:31:43 2024 X-Received: by 10.182.92.163 with SMTP id cn3mr3669888obb.49.1418212627925; Wed, 10 Dec 2014 03:57:07 -0800 (PST) X-Received: by 10.140.87.68 with SMTP id q62mr31390qgd.8.1418212627897; Wed, 10 Dec 2014 03:57:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no16724884igd.0!news-out.google.com!r1ni50qat.1!nntp.google.com!w8no5912800qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 03:57:07 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.115.52.180; posting-account=RSDZnwoAAABlC_Dai9W9X1yTdgNRgfBu NNTP-Posting-Host: 85.115.52.180 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Subject: Is there still no elegant way to create a BFM with a transaction-level interface? From: Jon Skull Injection-Date: Wed, 10 Dec 2014 11:57:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3421 Hi VHDL fans, I've been slowly taking up the various enhancements provided in VHDL2008, a= nd I find some very useful for testbench construction, particularly generic= packages.=20 However, am I missing something, or is there still no elegant way to create= a pin-wiggling BFM driven by a transaction level (procedural) interface? Verilog has always supported this because it is possible to call a procedur= e from outside the module in which it is declared.=20 For years I've approximated this in VHDL by using an inout "transaction" re= cord port on the BFM, with some horrible bidirectional handshaking to trans= fer the transactions. I then define a package of procedures which take this= transaction record as an inout argument. I think other people use this app= roach too, but it's far from ideal as you are forced to use resolved signal= types for all of the record elements.=20 Has anyone found a better way using (supported!) VHDL2008 features? =20 Jon From newsfish@newsfish Thu Aug 1 00:31:44 2024 X-Received: by 10.67.14.232 with SMTP id fj8mr3654443pad.16.1418213883438; Wed, 10 Dec 2014 04:18:03 -0800 (PST) X-Received: by 10.140.84.21 with SMTP id k21mr85231qgd.6.1418213883387; Wed, 10 Dec 2014 04:18:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6770343igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5426880qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 04:18:03 -0800 (PST) In-Reply-To: <6e168750-fc4c-4140-94fd-16cb55f3a337@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> <6e168750-fc4c-4140-94fd-16cb55f3a337@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <31955b00-b20a-4f30-a0a5-151e6c19752f@googlegroups.com> Subject: Re: Help with Architecture design From: Thomas Stanka Injection-Date: Wed, 10 Dec 2014 12:18:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3422 Am Mittwoch, 10. Dezember 2014 11:30:28 UTC+1 schrieb Olalekan Shittu: > On Wednesday, 10 December 2014 11:27:08 UTC+1, Olalekan Shittu wrote: > > Good morning everyone, > > > > I am a newbie to VHDL without background in programming language. Do you have a background in digital logic? Electronics? > > use IEEE.std_logic_arith.all; > > use IEEE.std_logic_unsigned.all; Those two libraries are not recomended to be used at all. BTW your code did not need them, you just copied without knowing why I guess. > Books for beginners can also be recommended to aid my learning I recommend to ignore in first step the fact that you could program software in VHDL (as soon as you program an compiler VHDL to executeable). You like to describe digital hardware and therefore I suggest reading in the basics of digital logic (design) unless you are familiar with descrete logic design. http://en.wikipedia.org/wiki/Register-transfer_level would be one easy point to start. Another often named (not necessary the best) is the "VHDL Cookbook" by Peter Ashden (google will find it for you). From newsfish@newsfish Thu Aug 1 00:31:44 2024 X-Received: by 10.66.167.231 with SMTP id zr7mr3515778pab.46.1418217532307; Wed, 10 Dec 2014 05:18:52 -0800 (PST) X-Received: by 10.140.18.173 with SMTP id 42mr3271qgf.9.1418217532259; Wed, 10 Dec 2014 05:18:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no6799154igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5442109qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 05:18:52 -0800 (PST) In-Reply-To: <31955b00-b20a-4f30-a0a5-151e6c19752f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.39.183.137; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 212.39.183.137 References: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> <6e168750-fc4c-4140-94fd-16cb55f3a337@googlegroups.com> <31955b00-b20a-4f30-a0a5-151e6c19752f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <55e9804c-f6e1-4646-82c3-10e6de6b8844@googlegroups.com> Subject: Re: Help with Architecture design From: Olalekan Shittu Injection-Date: Wed, 10 Dec 2014 13:18:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 27 Xref: news.eternal-september.org comp.lang.vhdl:3423 On Wednesday, 10 December 2014 13:18:04 UTC+1, Thomas Stanka wrote: > Am Mittwoch, 10. Dezember 2014 11:30:28 UTC+1 schrieb Olalekan Shittu: > > On Wednesday, 10 December 2014 11:27:08 UTC+1, Olalekan Shittu wrote: > > > Good morning everyone, > > > > > > I am a newbie to VHDL without background in programming language. > > Do you have a background in digital logic? Electronics? Dont really have a srtong background in digital electronics > > > > use IEEE.std_logic_arith.all; > > > use IEEE.std_logic_unsigned.all; > > Those two libraries are not recomended to be used at all. BTW your code did not need them, you just copied without knowing why I guess. You are right > > > Books for beginners can also be recommended to aid my learning > > I recommend to ignore in first step the fact that you could program software in VHDL (as soon as you program an compiler VHDL to executeable). > > You like to describe digital hardware and therefore I suggest reading in the basics of digital logic (design) unless you are familiar with descrete logic design. > > http://en.wikipedia.org/wiki/Register-transfer_level > would be one easy point to start. > Another often named (not necessary the best) is the "VHDL Cookbook" by Peter Ashden (google will find it for you). From newsfish@newsfish Thu Aug 1 00:31:44 2024 X-Received: by 10.182.43.170 with SMTP id x10mr8472829obl.15.1418309880624; Thu, 11 Dec 2014 06:58:00 -0800 (PST) X-Received: by 10.140.106.229 with SMTP id e92mr8730qgf.29.1418309880597; Thu, 11 Dec 2014 06:58:00 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no17674921igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5796250qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Dec 2014 06:58:00 -0800 (PST) In-Reply-To: <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 78.154.109.115 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question pertaining to a project From: "colin_toogood@yahoo.com" Injection-Date: Thu, 11 Dec 2014 14:58:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2523 X-Received-Body-CRC: 1789828018 Xref: news.eternal-september.org comp.lang.vhdl:3424 A few notes that will help you out. 1) You are trying to gate the clocks. Assuming you are expecting to learn t= o write code for an FPGA this is bad. Imagine you have an FPGA with 10,000 = flip flops that all need a clock. Xilinx etc have put a lot of work into al= lowing a single clock to get to them all which is running at 100s of MHz. Y= ou can't put an AND gate (clock AND button press) on the clock input of a f= lip flop. The logic (LUT) in front of the flip flop will happily include fe= edback from the output of the same flip flop so that when it is clocked not= hing changes (except on the occasions when it should, of course). 2) As a result of 1) you need the button press to exist for exactly one clo= ck. VHDL code is always littered with=20 button1 <=3D button; if button1=3D'0' and button=3D'1' then --button has just been pressed and i= need to do something on this clock. 3) Someone said about having only one process, what they meant was probably= have only one clk'event although most would write "rising_edge" instead. W= ith the above in mind this is now possible. Colin (He's a beginner, lets not have a long discussion about whether synthesis w= ould unwrap the gated clock and put it where it should be(not that I have e= ver tried)). From newsfish@newsfish Thu Aug 1 00:31:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question pertaining to a project Date: Thu, 11 Dec 2014 23:21:51 -0500 Organization: A noiseless patient Spider Lines: 55 Message-ID: References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 12 Dec 2014 04:21:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22660"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX192KTsp9GNSW0p90LX/0dAr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:jUdO1FRmpe1rcQC+g2DD/MyXgNU= Xref: news.eternal-september.org comp.lang.vhdl:3425 On 12/11/2014 9:58 AM, colin_toogood@yahoo.com wrote: > A few notes that will help you out. > > 1) You are trying to gate the clocks. Assuming you are expecting to learn to write code for an FPGA this is bad. Imagine you have an FPGA with 10,000 flip flops that all need a clock. Xilinx etc have put a lot of work into allowing a single clock to get to them all which is running at 100s of MHz. You can't put an AND gate (clock AND button press) on the clock input of a flip flop. The logic (LUT) in front of the flip flop will happily include feedback from the output of the same flip flop so that when it is clocked nothing changes (except on the occasions when it should, of course). I'm not sure this is true. Tell me how the synthesis tool will distinguish these two examples... 1) elsif clk'EVENT AND clk = '1' AND button_strikes ='1' then . . . end if; 2) elsif clk'EVENT AND clk = '1' then if button_strikes ='1' then . . . end if; end if; I am no expert at how the tools work, but my understanding is the logic is simplified (flattened) and then optimization happens. Is that wrong? > 2) As a result of 1) you need the button press to exist for exactly one clock. VHDL code is always littered with > button1 <= button; > if button1='0' and button='1' then --button has just been pressed and i need to do something on this clock. I believe you are describing edge detection, no? And in front of that he will need a debounce circuit. > 3) Someone said about having only one process, what they meant was probably have only one clk'event although most would write "rising_edge" instead. With the above in mind this is now possible. Yeah, one clocked process to handle the outputs. We all know what happens when you try to assign a single output from multiple processes. > Colin > (He's a beginner, lets not have a long discussion about whether synthesis would unwrap the gated clock and put it where it should be(not that I have ever tried)). Sure, I won't argue the style issue. I agree the separate IF condition for describing the edge sensitivity is best from a readability standpoint. I can't say for sure about the clock gating. I suspect the OP is gone, but perhaps he will return to glean a bit more from this topic. -- Rick From newsfish@newsfish Thu Aug 1 00:31:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? Date: Fri, 12 Dec 2014 00:43:52 -0500 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 12 Dec 2014 05:43:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="2035"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19LAungJ7Gx2gU51U4NHrIB" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Cancel-Lock: sha1:jQbzWDh2lDji32oPrvEx1L4G98E= Xref: news.eternal-september.org comp.lang.vhdl:3426 On 12/10/2014 6:57 AM, Jon Skull wrote: > Hi VHDL fans, > > I've been slowly taking up the various enhancements provided in VHDL2008, and I find some very useful for testbench construction, particularly generic packages. > > However, am I missing something, or is there still no elegant way to create a pin-wiggling BFM driven by a transaction level (procedural) interface? > > Verilog has always supported this because it is possible to call a procedure from outside the module in which it is declared. > > For years I've approximated this in VHDL by using an inout "transaction" record port on the BFM, with some horrible bidirectional handshaking to transfer the transactions. I then define a package of procedures which take this transaction record as an inout argument. I think other people use this approach too, but it's far from ideal as you are forced to use resolved signal types for all of the record elements. > > Has anyone found a better way using (supported!) VHDL2008 features? Please educate me on what a BFM is? I know a BFS is a type of large screwdriver. I assume you mean some sort of an interface you wish to control via commands. I'm not sure what the problem is. I've done this many times in VHDL. I typically have a file with commands that define the action to take and the time to perform those actions. For example, an MCU interface has read and write transactions with address and data to be written on writes or verified on reads. I read a line from the file, parsed the information, waited for the time to match the simulation time and then passed the command to the function that handled bus transactions. Where is the problem? Oh, this was long before VHDL2008. -- Rick From newsfish@newsfish Thu Aug 1 00:31:45 2024 X-Received: by 10.236.1.201 with SMTP id 49mr11986630yhd.50.1418368525842; Thu, 11 Dec 2014 23:15:25 -0800 (PST) X-Received: by 10.140.92.176 with SMTP id b45mr9127qge.10.1418368525795; Thu, 11 Dec 2014 23:15:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!s7no6054395qap.1!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no6054390qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Dec 2014 23:15:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=89.210.188.129; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 89.210.188.129 References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <26ac7bc7-2170-4f23-b16e-753e7e0891de@googlegroups.com> Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? From: Nikolaos Kavvadias Injection-Date: Fri, 12 Dec 2014 07:15:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3427 Hi Rick and Jon, > Please educate me on what a BFM is? I know a BFS is a type of large=20 > screwdriver. @Rick: BFM stands for Bus Functional Model. It is an approach for modeling = .read() and .write() transactions from/to the system bus. SystemC/TLM is a = popular approach for developing BFMs and probably the right thing to do is = design a SystemC/TLM BFM and cosimulate with VHDL.=20 A BFM generation tool would be beneficial. On a second thought, ArchC (www.= archc.org) fits the bill at least partially, is open/free and has a tractab= le learning curve. It is an architecture description language for generatin= g SystemC simulators (functional and cycle-accurate) of processors, but als= o has been extended to generating models with TLM ports (e.g. for accessing= a memory via the bus), a binary utilities port, and even an LLVM compiler = backend [there is a prototype for that called accgen). So in this sense, ArchC is the closest thing to automating BFM generation s= ince you can include TLM ports in an ArchC model and generate a SystemC sim= ulator from it (and then you can tweak it according to your aim). @Jon: A VHDL package for easily designing BFM models would also be of inter= est. I don't think such thing exists, but again you can have a look at: htt= p://opencores.org/project,axi4_tlm_bfm This is an AXI (AMBA 4.0) transactor and BFM by Daniel Kho of Tauhop Soluti= ons (www.tauhop.com). It is fairly well documented and maybe you could reus= e some of the code for your purpose. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Thu Aug 1 00:31:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? Date: Fri, 12 Dec 2014 02:57:54 -0500 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> <26ac7bc7-2170-4f23-b16e-753e7e0891de@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 12 Dec 2014 07:57:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22794"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19l643qC3kwTS97CCLP6j88" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <26ac7bc7-2170-4f23-b16e-753e7e0891de@googlegroups.com> Cancel-Lock: sha1:NQtH1F63mWXqqSrdGUXGadBVU1k= Xref: news.eternal-september.org comp.lang.vhdl:3428 On 12/12/2014 2:15 AM, Nikolaos Kavvadias wrote: > Hi Rick and Jon, > >> Please educate me on what a BFM is? I know a BFS is a type of large >> screwdriver. > > @Rick: BFM stands for Bus Functional Model. It is an approach for modeling ..read() and .write() transactions from/to the system bus. SystemC/TLM is a popular approach for developing BFMs and probably the right thing to do is design a SystemC/TLM BFM and cosimulate with VHDL. > > A BFM generation tool would be beneficial. On a second thought, ArchC (www.archc.org) fits the bill at least partially, is open/free and has a tractable learning curve. It is an architecture description language for generating SystemC simulators (functional and cycle-accurate) of processors, but also has been extended to generating models with TLM ports (e.g. for accessing a memory via the bus), a binary utilities port, and even an LLVM compiler backend [there is a prototype for that called accgen). > > So in this sense, ArchC is the closest thing to automating BFM generation since you can include TLM ports in an ArchC model and generate a SystemC simulator from it (and then you can tweak it according to your aim). > > @Jon: A VHDL package for easily designing BFM models would also be of interest. I don't think such thing exists, but again you can have a look at: http://opencores.org/project,axi4_tlm_bfm > > This is an AXI (AMBA 4.0) transactor and BFM by Daniel Kho of Tauhop Solutions (www.tauhop.com). It is fairly well documented and maybe you could reuse some of the code for your purpose. That is what I did some 15 years ago. I don't get why this is a big deal. It seems like a pretty straight forward thing to me. The only work involved was writing the code to parse the text file to drive the bus. Am I missing something? -- Rick From newsfish@newsfish Thu Aug 1 00:31:46 2024 X-Received: by 10.42.20.3 with SMTP id e3mr5551870icb.11.1418376880966; Fri, 12 Dec 2014 01:34:40 -0800 (PST) X-Received: by 10.140.18.173 with SMTP id 42mr15515qgf.9.1418376880895; Fri, 12 Dec 2014 01:34:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no7987657igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no6093483qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Dec 2014 01:34:40 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 78.154.109.115 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4f3267ee-b753-4291-b877-6266889133ea@googlegroups.com> Subject: Re: Question pertaining to a project From: "colin_toogood@yahoo.com" Injection-Date: Fri, 12 Dec 2014 09:34:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3429 Rick We will probably never know for certain, but from many years experience with new graduates it is my belief that he intended to gate the clock. I had already posted in this thread about metastability and others had already talked about debouncing. Colin From newsfish@newsfish Thu Aug 1 00:31:46 2024 X-Received: by 10.236.70.100 with SMTP id o64mr20491622yhd.9.1418487069077; Sat, 13 Dec 2014 08:11:09 -0800 (PST) X-Received: by 10.50.49.52 with SMTP id r20mr160369ign.8.1418487068977; Sat, 13 Dec 2014 08:11:08 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no7074832qac.0!news-out.google.com!jh1ni11954igb.0!nntp.google.com!h15no19592631igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Dec 2014 08:11:08 -0800 (PST) In-Reply-To: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <56fb9216-e895-4452-ae05-b80319b11823@googlegroups.com> Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? From: Jim Lewis Injection-Date: Sat, 13 Dec 2014 16:11:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2160 X-Received-Body-CRC: 2904953018 Xref: news.eternal-september.org comp.lang.vhdl:3430 Hi Jon, Still using records myself, however, ... VHDL 2008 introduces generic packages. Allows generic packages to be passe= d on entity interfaces. Allows generic instances within an architecture. = Has always allowed signals to be defined in packages. This would solve the= BFM connection, however, when calling the transaction subprogram, the subp= rogram still needs to pass the signals it needs to drive - for the time bei= ng, I plan on using a record reference for that.=20 When vendors support these features, it will offer us a feature similar to = SystemVerilog interfaces (without the concurrent region of the interface an= d modports (which allow constraint checking on who is allowed to drive whic= h signals and who is allowed to call which subprograms)).=20 I have prototypes and such. I have submitted bug reports. I need others t= o indicate they would like such features supported. =20 Best Regards, Jim From newsfish@newsfish Thu Aug 1 00:31:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? Date: Sun, 14 Dec 2014 12:58:36 +0000 (UTC) Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> <56fb9216-e895-4452-ae05-b80319b11823@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sun, 14 Dec 2014 12:58:36 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="23392"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/rsGHDeufa+50PaUyPZEHcmVxnIFU49Ac=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:48f21xpc3K0b1o07P6kQjxYl7Xg= Xref: news.eternal-september.org comp.lang.vhdl:3431 On Sat, 13 Dec 2014 08:11:08 -0800, Jim Lewis wrote: > Hi Jon, > Still using records myself, however, ... > > VHDL 2008 introduces generic packages. Allows generic packages to be > passed on entity interfaces. Allows generic instances within an > architecture. Has always allowed signals to be defined in packages. > This would solve the BFM connection, however, when calling the > transaction subprogram, the subprogram still needs to pass the signals > it needs to drive - for the time being, I plan on using a record > reference for that. > > When vendors support these features, it will offer us a feature similar > to SystemVerilog interfaces (without the concurrent region of the > interface and modports (which allow constraint checking on who is > allowed to drive which signals and who is allowed to call which > subprograms)). > > I have prototypes and such. I have submitted bug reports. I need > others to indicate they would like such features supported. > > Best Regards, > Jim If you have simple testcases ... I'd be interested to see them - or talk to Tristan. He seems to be on a roll these days. ghdl (not 0.31 but 0.32 which is in the pre-release stage, anyone can build it from source) supports enough VHDL-2008 to run OSVVM 2014.01 now. If you have a prototype or testcase requiring additional VHDL-2008 support beyond that, it would be great to get that into the next release. - Brian From newsfish@newsfish Thu Aug 1 00:31:47 2024 X-Received: by 10.43.78.198 with SMTP id zn6mr28826056icb.12.1418620399419; Sun, 14 Dec 2014 21:13:19 -0800 (PST) X-Received: by 10.140.27.197 with SMTP id 63mr132284qgx.6.1418620399284; Sun, 14 Dec 2014 21:13:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no10331969igd.0!news-out.google.com!r1ni52qat.1!nntp.google.com!s7no7310831qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 14 Dec 2014 21:13:19 -0800 (PST) In-Reply-To: <56fb9216-e895-4452-ae05-b80319b11823@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> <56fb9216-e895-4452-ae05-b80319b11823@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? From: Andy Injection-Date: Mon, 15 Dec 2014 05:13:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2072 X-Received-Body-CRC: 1136280396 Xref: news.eternal-september.org comp.lang.vhdl:3432 Records work pretty well when you understand what the initializer does on a= signal or port declaration. It can be used to keep the signal benign until= /unless someone drives it. Another approach I have used is to declare a package procedure(s) with sepa= rate in/out/inout signal ports, that provides your procedural interface(s) = to the BFM.=20 Then in the process where you want to call the package procedure(s), you ca= n overload the package procedure(s) so that only pertinent, per-call info i= s passed to the local procedure(s). A procedure declared in a process can a= ccess/drive signals visible to the process without them having to be explic= itly passed to the local procedure. Just have the body of the local procedu= re call the package procedure with the full interface. Andy From newsfish@newsfish Thu Aug 1 00:31:47 2024 X-Received: by 10.66.155.230 with SMTP id vz6mr22496246pab.41.1418621803129; Sun, 14 Dec 2014 21:36:43 -0800 (PST) X-Received: by 10.140.95.182 with SMTP id i51mr6239qge.12.1418621802865; Sun, 14 Dec 2014 21:36:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no10349796igd.0!news-out.google.com!r1ni50qat.1!nntp.google.com!w8no7809830qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 14 Dec 2014 21:36:42 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <95b23918-ff71-4aac-856f-cdf155e87974@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <28903359-06a3-4333-ba60-dec83a6fff30@googlegroups.com> Subject: Re: vhdl code review From: Andy Injection-Date: Mon, 15 Dec 2014 05:36:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3433 Al, I don't recommend everyone has to use the same editor/ide, but regardless o= f the one(s) used by the developer(s), a good ide used by the reviewer is a= huge boost. I especially like sigasi, since it does not need a list of fil= es in compile order. Just point it at the directory(s) containing the sourc= e files, and it will figure it all out. Sigasi also can uniquely fontify di= fferent parts of speech (like ports, signals, variables, constants, functio= ns, types/subtypes etc.) making the code (that the reviewer did not write) = much easier to understand. IMHO, reviewing code that has not been compiled, or at least linted, is a w= aste of reviewers' time. If the code is only RTL unit level, the developer = should still synthesize it, at the unit level if necessary. It should also= be compiled into the simulator(s) to be used. The logs from these provide = useful information that can be quickly reviewed. Packages cannot be synthes= ized at the unit level, but maybe a simple test entity that uses the packag= e can be synthesized and the log files reviewed.=20 Andy From newsfish@newsfish Thu Aug 1 00:31:48 2024 X-Received: by 10.50.78.136 with SMTP id b8mr16756347igx.4.1418647159660; Mon, 15 Dec 2014 04:39:19 -0800 (PST) X-Received: by 10.140.87.68 with SMTP id q62mr27146qgd.8.1418647159588; Mon, 15 Dec 2014 04:39:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h15no21737844igd.0!news-out.google.com!r1ni52qat.1!nntp.google.com!s7no7509460qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Dec 2014 04:39:19 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.178.200.133; posting-account=vuXUMwoAAADswfNzA5_BcjyTXE29RRxQ NNTP-Posting-Host: 212.178.200.133 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1582cdb4-87d7-4eb5-a35a-58fd20e5bd23@googlegroups.com> Subject: Re: Looking for expert VHDL books From: Simon Thijs de Feber Injection-Date: Mon, 15 Dec 2014 12:39:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3434 The following books I recommend : 1. The Designer's Guide to VHDL by Peter Ashenden 2. VHDL-2008, just the new stuff, by Peter Ashenden and Jim Lewis and my personal favorite 3. Embedded DSP Processor Design by Dake Liu and still very informative 4. The Design Warrior's Guide to FPGAs, by Clive Maxfield grtz ST From newsfish@newsfish Thu Aug 1 00:31:48 2024 X-Received: by 10.66.255.97 with SMTP id ap1mr26636911pad.1.1418667617530; Mon, 15 Dec 2014 10:20:17 -0800 (PST) X-Received: by 10.140.16.55 with SMTP id 52mr25413qga.31.1418667617437; Mon, 15 Dec 2014 10:20:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed4.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no22050917igd.0!news-out.google.com!r1ni52qat.1!nntp.google.com!s7no7641005qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Dec 2014 10:20:17 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=178.61.0.144; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 178.61.0.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <518bb7c6-80cf-458f-a70f-e296fdcbc652@googlegroups.com> Subject: Total execution time in ModelSim From: AA Injection-Date: Mon, 15 Dec 2014 18:20:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 3 Xref: news.eternal-september.org comp.lang.vhdl:3435 hi, how to get the total execution time in ModelSim 14? Thank you From newsfish@newsfish Thu Aug 1 00:31:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx05.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Total execution time in ModelSim References: <518bb7c6-80cf-458f-a70f-e296fdcbc652@googlegroups.com> In-Reply-To: <518bb7c6-80cf-458f-a70f-e296fdcbc652@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 141215-0, 15/12/2014), Outbound message X-Antivirus-Status: Clean Lines: 30 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1418669152 86.17.210.161 (Mon, 15 Dec 2014 18:45:52 UTC) NNTP-Posting-Date: Mon, 15 Dec 2014 18:45:52 UTC Organization: virginmedia.com Date: Mon, 15 Dec 2014 18:45:52 +0000 X-Received-Body-CRC: 2082777091 X-Received-Bytes: 1924 Xref: news.eternal-september.org comp.lang.vhdl:3436 On 15/12/2014 18:20, AA wrote: > hi, > how to get the total execution time in ModelSim 14? > > Thank you > Not sure what Modelsim 14 is but you can get all sorts of statistics using the simstats command. VSIM 2> simstats # Memory Statistics # mem: size after elab (VSZ) 106724.00 Kb # mem: size during sim (VSZ) 112988.00 Kb # Elaboration Time # elab: wall time 0.45 s # elab: cpu time 0.20 s # Simulation Time # sim: wall time 0.02 s # sim: cpu time 0.00 s # Tcl Command Time # cmd: wall time 9.24 s # cmd: cpu time 0.17 s # Total Time # total: wall time 9.70 s # total: cpu time 0.37 s # Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:31:49 2024 X-Received: by 10.182.81.74 with SMTP id y10mr30026916obx.22.1418689575735; Mon, 15 Dec 2014 16:26:15 -0800 (PST) X-Received: by 10.50.66.144 with SMTP id f16mr337895igt.1.1418689575606; Mon, 15 Dec 2014 16:26:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no11273002igd.0!news-out.google.com!jh1ni16719igb.0!nntp.google.com!h15no11272994igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Dec 2014 16:26:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.182.111.139; posting-account=W6w2ZAoAAAAeI1nFywA0Wk0a67aNeYkb NNTP-Posting-Host: 70.182.111.139 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1f1687a7-5b6d-4eb0-b754-bb2839c367ec@googlegroups.com> Subject: Re: toggling an output From: weedenmatt@gmail.com Injection-Date: Tue, 16 Dec 2014 00:26:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3437 Thank you for this answer. It was helpful to me. From newsfish@newsfish Thu Aug 1 00:31:49 2024 X-Received: by 10.68.95.228 with SMTP id dn4mr13062927pbb.7.1418710919442; Mon, 15 Dec 2014 22:21:59 -0800 (PST) X-Received: by 10.140.48.69 with SMTP id n63mr577qga.21.1418710919130; Mon, 15 Dec 2014 22:21:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no11453267igd.0!news-out.google.com!r1ni52qat.1!nntp.google.com!s7no7879428qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Dec 2014 22:21:59 -0800 (PST) In-Reply-To: <28903359-06a3-4333-ba60-dec83a6fff30@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <95b23918-ff71-4aac-856f-cdf155e87974@googlegroups.com> <28903359-06a3-4333-ba60-dec83a6fff30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3cf36697-f932-4e61-919e-eba13a566210@googlegroups.com> Subject: Re: vhdl code review From: lars.anders.asplund@gmail.com Injection-Date: Tue, 16 Dec 2014 06:21:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3438 I'm using unit testing when developing for VHDL and a nice side effect is t= hat it makes you review your own code in a way that you wouldn't do otherwi= se. I suspect that I find as many bugs writing these tests as I do running = them. We have released our unit testing framework for VHDL as open source o= n Github (https://github.com/LarsAsplund/vunit) and there are also other so= lutions for Verilog. Lars From newsfish@newsfish Thu Aug 1 00:31:49 2024 X-Received: by 10.42.88.81 with SMTP id b17mr35045260icm.2.1418724186226; Tue, 16 Dec 2014 02:03:06 -0800 (PST) X-Received: by 10.140.102.211 with SMTP id w77mr3683qge.28.1418724186153; Tue, 16 Dec 2014 02:03:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h15no22771025igd.0!news-out.google.com!r1ni53qat.1!nntp.google.com!w8no8429363qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Dec 2014 02:03:05 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <70bd1fec-20d2-424c-bf18-7d49bbcd6fe5@googlegroups.com> Subject: Recursive Systematic Convolution Encoder From: Muhammad Injection-Date: Tue, 16 Dec 2014 10:03:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3439 Hi, i have to implement a turbo encoder and for that i need VHDL code of Recursive Systematic Convolution Encoder.Can any one help me thanks From newsfish@newsfish Thu Aug 1 00:31:49 2024 X-Received: by 10.70.140.206 with SMTP id ri14mr31206360pdb.9.1418748681116; Tue, 16 Dec 2014 08:51:21 -0800 (PST) X-Received: by 10.182.113.195 with SMTP id ja3mr9173obb.41.1418748681002; Tue, 16 Dec 2014 08:51:21 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no11865106igd.0!news-out.google.com!d20ni17812igz.0!nntp.google.com!h15no23139746igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Dec 2014 08:51:20 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.35.35.36 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Subject: automated converting records to std_logic_vector From: "V." Injection-Date: Tue, 16 Dec 2014 16:51:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1969 X-Received-Body-CRC: 1402634264 Xref: news.eternal-september.org comp.lang.vhdl:3440 Hello, First off, thank you everyone for contributing to this discussion group, it has been very helpful and informative to me as I progress with learning VHDL. I'm looking to convert a record that contains 16 std_logic types into a 16 bit std_logic_vector. I currently have a function call that manually assigns each element in the record to a specific bit location in the std_logic_vector : function rec2slv(x : rec_type) return std_logic_vector is variable result : std_logic_vector(15 downto 0) := (others => '0'); begin result(15) := x.element1; ... ... result(0) := x.element16; return result; end; === I have a large amount of records that I'd like to do this on, and it is very tedious to have to write a function for each of the record. Is there something similar to the following that could automate it? : for i in x'range loop result := x(i); end loop; Thank you all! From newsfish@newsfish Thu Aug 1 00:31:50 2024 X-Received: by 10.66.222.135 with SMTP id qm7mr33098697pac.20.1418758807879; Tue, 16 Dec 2014 11:40:07 -0800 (PST) X-Received: by 10.140.101.247 with SMTP id u110mr58153qge.18.1418758807825; Tue, 16 Dec 2014 11:40:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no12004458igd.0!news-out.google.com!r1ni57qat.1!nntp.google.com!s7no8162792qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Dec 2014 11:40:07 -0800 (PST) In-Reply-To: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d6e7531-768e-4f82-a6e5-569be41a115c@googlegroups.com> Subject: Re: automated converting records to std_logic_vector From: KJ Injection-Date: Tue, 16 Dec 2014 19:40:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3575 X-Received-Body-CRC: 1243375568 Xref: news.eternal-september.org comp.lang.vhdl:3441 On Tuesday, December 16, 2014 11:51:23 AM UTC-5, V. wrote: >=20 > I'm looking to convert a record that contains 16 std_logic types into a 1= 6=20 > bit std_logic_vector. I currently have a function call that manually assi= gns=20 > each element in the record to a specific bit location in the std_logic_ve= ctor :=20 There is no way to iterate through the elements of a record, so what you ar= e doing is basically the way it needs to be done. However, to decrease the= tedium a bit, if you define the record in the right fashion you can make i= t so an editor macro can munch on it and produce the functions quick enough= . What I do is to define the record like this... type t_IMG_DMA_IMG_SIZE is record Reserved1: std_ulogic_vector(31 downto 28); HSize: std_ulogic_vector(27 downto 16); Reserved2: std_ulogic_vector(15 downto 12); VSize: std_ulogic_vector(11 downto 0); end record t_IMG_DMA_IMG_SIZE; Then create functions that convert between the record and a std_ulogic_vect= or like this... function To_Std_ULogic_Vector(L: t_IMG_DMA_IMG_SIZE) return std_ulogic_= vector is variable RetVal: std_ulogic_vector(31 downto 0); begin RetVal(L.Reserved1'range) :=3D L.Reserved1; RetVal(L.HSize'range) :=3D L.HSize; RetVal(L.Reserved2'range) :=3D L.Reserved2; RetVal(L.VSize'range) :=3D L.VSize; return(RetVal); end function To_Std_ULogic_Vector; function From_Std_ULogic_Vector(L: std_ulogic_vector(31 downto 0)) retu= rn t_IMG_DMA_IMG_SIZE is variable RetVal: t_IMG_DMA_IMG_SIZE; begin RetVal :=3D ( Reserved1 =3D> L(RetVal.Reserved1'range), HSize =3D> L(RetVal.HSize'range), Reserved2 =3D> L(RetVal.Reserved2'range), VSize =3D> L(RetVal.VSize'range) ); return(RetVal); end function From_Std_ULogic_Vector; Note that the functions themselves do not need to be edited if all you do i= s change the bit positions. In that situation, you simply edit the record = definition. If you have one bit fields, you simply define them as one bit = vectors like this xyz: std_ulogic_vector(28 downto 28); Adding/removing a field from the record does require function editing. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:31:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: automated converting records to std_logic_vector Date: Tue, 16 Dec 2014 12:29:36 -0800 Organization: Highland Technology, Inc. Lines: 164 Message-ID: <20141216122936.1aaf935f@rg.highlandtechnology.com> References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="b789ea9a1fdbea3e4581bf19a1fd4beb"; logging-data="32208"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/yr1rVCsn0sdRl1BBDvS9S" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:DvPbzGUDY1vv5mWB7eOoyIyp7Lk= Xref: news.eternal-september.org comp.lang.vhdl:3442 On Tue, 16 Dec 2014 08:51:20 -0800 (PST) "V." wrote: > Hello, > > First off, thank you everyone for contributing to this discussion group, it has been very helpful and informative to me as I progress with learning VHDL. > > > I'm looking to convert a record that contains 16 std_logic types into a 16 bit std_logic_vector. I currently have a function call that manually assigns each element in the record to a specific bit location in the std_logic_vector : > > > function rec2slv(x : rec_type) return std_logic_vector is > variable result : std_logic_vector(15 downto 0) := (others => '0'); > begin > result(15) := x.element1; > ... > ... > result(0) := x.element16; > > return result; > end; > > > === > > > I have a large amount of records that I'd like to do this on, and it is very tedious to have to write a function for each of the record. > > Is there something similar to the following that could automate it? : > > for i in x'range loop > result := x(i); > end loop; > > > Thank you all! Not really. I wrote pack/unpack functions that I get a lot of use of when I have to cast a record type into an SLV, usually because I have to work with some generated core. Then I wind up writing functions for each direction as: function TO_SLV(rec : t_pvme_request) return t_pvme_request_slv is variable slv : t_pvme_request_slv; variable idx : integer; begin slv := (others => 'U'); idx := 0; pack(slv, idx, rec.data); pack(slv, idx, rec.address); pack(slv, idx, rec.timing); pack(slv, idx, rec.am); pack(slv, idx, rec.dm); pack(slv, idx, rec.req); return slv; end function TO_SLV; function TO_REQUEST (slv : t_pvme_request_slv) return t_pvme_request is variable rec : t_pvme_request; variable idx : integer; begin idx := 0; unpack(slv, idx, rec.data); unpack(slv, idx, rec.address); unpack(slv, idx, rec.timing); unpack(slv, idx, rec.am); unpack(slv, idx, rec.dm); unpack(slv, idx, rec.req); return rec; end function TO_REQUEST; I'll put all my overloads on the pack/unpack functions here in case anyone ever wants them. ----------------------------------------------------------------------- -- Record conversion functions ----------------------------------------------------------------------- procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in std_logic_vector ) is begin target(idx + nd'length - 1 downto idx) := nd; idx := idx + nd'length; end procedure pack; procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in std_logic ) is begin target(idx) := nd; idx := idx + 1; end procedure pack; procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in unsigned ) is begin target(idx + nd'length - 1 downto idx) := STD_LOGIC_VECTOR(nd); idx := idx + nd'length; end procedure pack; procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in signed ) is begin target(idx + nd'length - 1 downto idx) := STD_LOGIC_VECTOR(nd); idx := idx + nd'length; end procedure pack; ---------------------------------------------------------------------- procedure unpack ( source : in std_logic_vector; idx : inout integer; dat : out std_logic_vector ) is begin dat := source(idx + dat'length - 1 downto idx); idx := idx + dat'length; end procedure unpack; procedure unpack ( source : in std_logic_vector; idx : inout integer; dat : out std_logic ) is begin dat := source(idx); idx := idx + 1; end procedure unpack; procedure unpack ( source : in std_logic_vector; idx : inout integer; dat : out unsigned ) is begin dat := UNSIGNED(source(idx + dat'length - 1 downto idx)); idx := idx + dat'length; end procedure unpack; procedure unpack ( source : in std_logic_vector; idx : inout integer; dat : out signed ) is begin dat := SIGNED(source(idx + dat'length - 1 downto idx)); idx := idx + dat'length; end procedure unpack; -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:31:50 2024 X-Received: by 10.50.66.37 with SMTP id c5mr5150166igt.4.1418782955495; Tue, 16 Dec 2014 18:22:35 -0800 (PST) X-Received: by 10.140.93.17 with SMTP id c17mr286qge.26.1418782955338; Tue, 16 Dec 2014 18:22:35 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no23550387igd.0!news-out.google.com!r1ni59qat.1!nntp.google.com!n8no125118qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Dec 2014 18:22:35 -0800 (PST) In-Reply-To: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: automated converting records to std_logic_vector From: KJ Injection-Date: Wed, 17 Dec 2014 02:22:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 15 X-Received-Bytes: 1784 X-Received-Body-CRC: 1771948397 Xref: news.eternal-september.org comp.lang.vhdl:3443 Actually, there is another way for your particular case. Your case happens to have 16 named bits that you want to turn into a vector. Instead of a record then you can use an enumerated type. Type mytype is (element1, element2, ... element16); Type arr_mytype is array (mytype) of std_ulogic; Then you would refer to elements as x(element1) instead of x.element1. More important though you can iterate through the enumerations with For i in mytype loop Sulv(mytype'pos(i) := Inp(i); End loop; Where Inp is of type mytype, Sulv is the output std_ulogic_vector. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:31:51 2024 X-Received: by 10.68.68.173 with SMTP id x13mr35499441pbt.6.1418828182158; Wed, 17 Dec 2014 06:56:22 -0800 (PST) X-Received: by 10.140.81.169 with SMTP id f38mr871909qgd.3.1418828181902; Wed, 17 Dec 2014 06:56:21 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no24087401igd.0!news-out.google.com!r1ni62qat.1!nntp.google.com!s7no8490943qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Dec 2014 06:56:21 -0800 (PST) In-Reply-To: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: automated converting records to std_logic_vector From: Chris Higgs Injection-Date: Wed, 17 Dec 2014 14:56:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 19 Xref: news.eternal-september.org comp.lang.vhdl:3444 On Tuesday, December 16, 2014 4:51:23 PM UTC, V. wrote: > I'm looking to convert a record that contains 16 std_logic types > into a 16 bit std_logic_vector. I currently have a function call > that manually assigns each element in the record to a specific > bit location in the std_logic_vector Sadly as other contributors have mentioned there's no way to do this without explicitly rolling your own pack/unpack functions for each record type. There is however a proposal for the next VHDL revision to add functionality that would remove the need to write functions that are specific to each record: http://www.eda.org/twiki/bin/view.cgi/P1076/RecordIntrospection Thanks, Chris From newsfish@newsfish Thu Aug 1 00:31:51 2024 X-Received: by 10.224.46.7 with SMTP id h7mr3225967qaf.2.1418934896322; Thu, 18 Dec 2014 12:34:56 -0800 (PST) X-Received: by 10.50.143.102 with SMTP id sd6mr89170igb.13.1418934896222; Thu, 18 Dec 2014 12:34:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no347210qae.0!news-out.google.com!h6ni1784igv.0!nntp.google.com!h15no25331764igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Dec 2014 12:34:55 -0800 (PST) In-Reply-To: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.151.61; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.151.61 References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? From: Daniel Kho Injection-Date: Thu, 18 Dec 2014 20:34:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2891 X-Received-Body-CRC: 1044522406 Xref: news.eternal-september.org comp.lang.vhdl:3445 On Wednesday, 10 December 2014 19:57:11 UTC+8, Jon Skull wrote: > Hi VHDL fans, >=20 > I've been slowly taking up the various enhancements provided in VHDL2008,= and I find some very useful for testbench construction, particularly gener= ic packages.=20 >=20 > However, am I missing something, or is there still no elegant way to crea= te a pin-wiggling BFM driven by a transaction level (procedural) interface? >=20 > Verilog has always supported this because it is possible to call a proced= ure from outside the module in which it is declared.=20 >=20 > For years I've approximated this in VHDL by using an inout "transaction" = record port on the BFM, with some horrible bidirectional handshaking to tra= nsfer the transactions. I then define a package of procedures which take th= is transaction record as an inout argument. I think other people use this a= pproach too, but it's far from ideal as you are forced to use resolved sign= al types for all of the record elements.=20 >=20 > Has anyone found a better way using (supported!) VHDL2008 features? =20 >=20 > Jon As Nikolaos pointed out, do take a look at the AXI4 TLM/BFM project on Open= Cores. If you're not into AXI, you still can reuse some of the packages fro= m there. I've written it in a very reusable way - the pkg-tlm.vhdl generic = package can even be reused without any changes (possibly minor changes, if = you would) for any other protocol. The pkg-axi-tlm.vhdl is an instance of t= his generic package, so you can create other instances for other protocols. The project even uses OS-VVM to do coverage-driven constrained randomisatio= n of test vectors. Cheers, dan From newsfish@newsfish Thu Aug 1 00:31:51 2024 X-Received: by 10.68.112.66 with SMTP id io2mr3314450pbb.2.1418936699250; Thu, 18 Dec 2014 13:04:59 -0800 (PST) X-Received: by 10.50.43.199 with SMTP id y7mr91744igl.3.1418936698946; Thu, 18 Dec 2014 13:04:58 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no13632179igd.0!news-out.google.com!d20ni19676igz.0!nntp.google.com!h15no13632163igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Dec 2014 13:04:58 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.151.61; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.151.61 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 support in Modelsim? From: Daniel Kho Injection-Date: Thu, 18 Dec 2014 21:04:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2672 X-Received-Body-CRC: 3044519012 Xref: news.eternal-september.org comp.lang.vhdl:3446 On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote: > On 05/12/2014 12:48, Anssi Saari wrote: > > > > Is Modelsim still not implementing VHDL 2008? I have some code with the > > "new" if ... generate with else branch but Modelsim 10.1e doesn't seem > > to support that. Or is it just that the Altera's Starter Edition doesn't > > support that? I don't have a Modelsim PE or SE installed right now... I > > tried case in generate as well but it didn't work any better. > > Modelsim 10.1e was released in June of 2013. Your code compiled OK in > the latest 10.3d release. > > Modelsim SE is an obsolete product and replaced by Questa core. > > Regards, > Hans > www.ht-lab.com > > > > > > > Example code, vcom -2008 says > > ** Error: generate_prob.vhdl(20): near "else": syntax error > > (line 20 is the else generate line.) > > > > LIBRARY ieee; > > USE ieee.std_logic_1164.ALL; > > > > entity dummy is > > generic ( > > some_boolean_generic : boolean := false); > > port( > > clk : in std_logic; > > reset_n : in std_logic; > > dout : out std_logic > > ); > > end dummy; > > > > architecture dummy_arch of dummy is > > > > begin > > > > some_label: if some_boolean_generic = false generate > > dout <= '0'; > > else generate > > dout <= '1'; > > end generate some_label; > > > > end dummy_arch; > > The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty well. It's free (as in beer) - you can get it from Altera's website. -dan From newsfish@newsfish Thu Aug 1 00:31:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Spectral Purity Measurement Date: Fri, 19 Dec 2014 10:06:50 -0500 Organization: A noiseless patient Spider Lines: 16 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Dec 2014 15:06:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="d24b6b05896a8cf9cfa56f7a9e385806"; logging-data="4375"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/XoiGiLmqGkKI69qEe99R3" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 Cancel-Lock: sha1:9RNXTwzfxB9VvmzGNPwgHgwNgXo= Xref: news.eternal-september.org comp.dsp:25964 comp.lang.vhdl:3447 I want to analyze the output of a DDS circuit and am wondering if an FFT is the best way to do this. I'm mainly concerned with the "close in" spurs that are often generated by a DDS. My analysis of the errors involved in the sine generation is that they will be on the order of 1 ppm which I believe will be -240 dBc. Is that right? Sounds far too easy to get such good results. I guess I'm worried that it will be hard to measure such low levels. Any suggestions? I'll be coding both the implementation and the measurement code. The implementation will be synthesizable and the measurement code will not. I'm thinking a fairly large FFT, 2048 or maybe 4096 bins in floating point. -- Rick From newsfish@newsfish Thu Aug 1 00:31:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 19 Dec 2014 12:24:53 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 19 Dec 2014 12:24:53 -0600 Lines: 56 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-XK3Ec4uWRHiQvww7P5yCDGVyCZK3V8F3XyNLI2IzjalJii9nACWyz6j/bE92Ssjv987RI3EYscXVQd0!ZprrZ6PfaFIZ0smxZWzLPV4jZrucn21PJyv9UoPwb63g1727rab6yxz9pWVdN04+zuVGuw/25rYd X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4026 X-Received-Bytes: 4138 X-Received-Body-CRC: 2151817098 Xref: news.eternal-september.org comp.dsp:25968 comp.lang.vhdl:3448 On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. If you mean a real circuit and not an FPGA configuration, and if you have any analog components in there, then you need to measure the thing with a spectrum analyzer. No spectrum analyzer in the world has a 240dB dynamic range, so you'd need to notch out the carrier with something absurdly deep and narrow-band, like a crystal filter. Measuring spurs down to that level would be a significant challenge for an experienced RF engineer -- I don't know that I could, or if I'd trust my results without double- checking from someone who did it every day. Even if you're measuring this numerically I think you need to do some careful and close analysis of whatever method you choose. An FFT that short will only be good to -240dBc if it collects an exact integer number of samples -- if it collects more or less, the artifacts from truncating the series will overwhelm any real effects. -240dBc implies 40 bits of precision, so you'll need to be sure that the error build-up in your FFT (or whatever) doesn't exceed that. You're talking a 12-stage FFT, and double-precision floating point has a 52-bit mantissa, so if everything stacks up wrong you've just blown your error budget. Such errors tend to be smeared out rather than to build up -- but you need to check with analysis to be sure. If you can, it may be best to generate a file of DDS outputs, and then do the analysis in some separate package like Scilab, Octave or Matlab. Even there, however, I would be concerned about the needed precision, and I'd seriously consider finding an FFT package that is, or can be compiled to, a quad-precision version. All of this really makes me want to ask _why_ -- if you're working in some application where you need to keep your DDS that spectrally pure, then chances are good that even with an absolutely perfect DDS, you're already screwed. You may want to review how well this thing is going to work when your input signal has noise, and has the inevitable distortion that comes from being measured by analog components. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com From newsfish@newsfish Thu Aug 1 00:31:52 2024 X-Received: by 10.66.229.66 with SMTP id so2mr7106784pac.15.1419015877027; Fri, 19 Dec 2014 11:04:37 -0800 (PST) X-Received: by 10.140.33.229 with SMTP id j92mr59366qgj.7.1419015876978; Fri, 19 Dec 2014 11:04:36 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no26285714igd.0!news-out.google.com!r1ni76qat.1!nntp.google.com!dc16no333231qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Dec 2014 11:04:36 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.91.173.34 References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9a8c82b3-6bbc-41c0-af8c-2549e721d77d@googlegroups.com> Subject: Re: automated converting records to std_logic_vector From: "V." Injection-Date: Fri, 19 Dec 2014 19:04:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2124 X-Received-Body-CRC: 3565825025 Xref: news.eternal-september.org comp.lang.vhdl:3449 On Tuesday, December 16, 2014 8:22:38 PM UTC-6, KJ wrote: > Actually, there is another way for your particular case. Your case happens to have 16 named bits that you want to turn into a vector. Instead of a record then you can use an enumerated type. > > Type mytype is (element1, element2, ... element16); > > Type arr_mytype is array (mytype) of std_ulogic; > > Then you would refer to elements as x(element1) instead of x.element1. > > More important though you can iterate through the enumerations with > For i in mytype loop > Sulv(mytype'pos(i) := Inp(i); > End loop; > > Where Inp is of type mytype, Sulv is the output std_ulogic_vector. > > Kevin Jennings Thanks Kevin ... Yes, that will work for about half of my records, which is good news! Unfortunately the other half contains a mix of logic types that won't play as nicely. Thank you Chris for the link, glad to know it's been brought up before. From newsfish@newsfish Thu Aug 1 00:31:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!not-for-mail Date: Fri, 19 Dec 2014 21:38:52 +0000 From: Andy Botterill User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Lines: 22 Message-ID: <54949aec$0$12285$bed64819@gradwell.net> NNTP-Posting-Host: 93d8898e.gradwell.net X-Trace: DXC=I7YdnIH]<00M:5lSP^d;@;aEW\3OJZ9Z3Po1k6Q\Tjc?NWPO_8o@]:>OT6Q0a]eYD2`mdDhe]3nh<5J0h1k;Ekc42;ZeR9iQSl0 X-Complaints-To: abuse@gradwell.net X-Received-Bytes: 1817 X-Received-Body-CRC: 87750330 Xref: news.eternal-september.org comp.dsp:25971 comp.lang.vhdl:3450 -240dbc is a very low signal level and will be below the noise floor of the environment being tested in. With a good spectrum analyser you may get down to -160dbm. Are you really sure about the power level. Compare with http://www.rohde-schwarz.co.uk/en/product/fsu-productstartpage_63493-7993.html On 19/12/14 15:06, rickman wrote: > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. > From newsfish@newsfish Thu Aug 1 00:31:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 19 Dec 2014 17:22:14 -0500 Organization: Alacron, Inc. Lines: 31 Message-ID: References: <54949aec$0$12285$bed64819@gradwell.net> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Dec 2014 22:23:05 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="18354"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ldMKpInUGy1sZuhnASOiAXEUBEtkAfm0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <54949aec$0$12285$bed64819@gradwell.net> Cancel-Lock: sha1:Da6CwU22INw+IrvhRFj0f8Vwuro= Xref: news.eternal-september.org comp.dsp:25972 comp.lang.vhdl:3451 Andy Botterill wrote: > -240dbc is a very low signal level and will be below the noise floor of > the environment being tested in. With a good spectrum analyser you may > get down to -160dbm. Are you really sure about the power level. > > Compare with > http://www.rohde-schwarz.co.uk/en/product/fsu-productstartpage_63493-7993.html > > > On 19/12/14 15:06, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be hard >> to measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. The implementation will be synthesizable and the >> measurement code will not. I'm thinking a fairly large FFT, 2048 or >> maybe 4096 bins in floating point. >> > Are decibels used differently for dBc than for other usages? I would have thought that 6 orders of magnitude (1 ppm) was -120 dB not -240 dB 20 * log10 (10**-6) = 20 * -6 = -120 -- Gabor From newsfish@newsfish Thu Aug 1 00:31:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 19 Dec 2014 17:10:32 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54949aec$0$12285$bed64819@gradwell.net> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 19 Dec 2014 17:10:32 -0600 Lines: 47 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-SWXI3+HkivnzplC8Od11LuU4k2dsVIXh76YzxWKBrLDftgULpiKHzn0OiJv2lOs3nCuHIdvov28sV6J!P0CJLTv/dAI99vd4nrT/+vuCTZpohgKDwX5iabmHqzZv9W11W/5Za50Zk93ax6L30fzTcjGRCdhj X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3213 X-Received-Bytes: 3325 X-Received-Body-CRC: 3255967788 Xref: news.eternal-september.org comp.dsp:25973 comp.lang.vhdl:3452 On Fri, 19 Dec 2014 17:22:14 -0500, GaborSzakacs wrote: > Andy Botterill wrote: >> -240dbc is a very low signal level and will be below the noise floor of >> the environment being tested in. With a good spectrum analyser you may >> get down to -160dbm. Are you really sure about the power level. >> >> Compare with >> http://www.rohde-schwarz.co.uk/en/product/fsu- productstartpage_63493-7993.html >> >> >> On 19/12/14 15:06, rickman wrote: >>> I want to analyze the output of a DDS circuit and am wondering if an >>> FFT is the best way to do this. I'm mainly concerned with the "close >>> in" spurs that are often generated by a DDS. My analysis of the >>> errors involved in the sine generation is that they will be on the >>> order of 1 ppm which I believe will be -240 dBc. Is that right? >>> Sounds far too easy to get such good results. I guess I'm worried >>> that it will be hard to measure such low levels. >>> >>> Any suggestions? I'll be coding both the implementation and the >>> measurement code. The implementation will be synthesizable and the >>> measurement code will not. I'm thinking a fairly large FFT, 2048 or >>> maybe 4096 bins in floating point. >>> >>> >> > Are decibels used differently for dBc than for other usages? I would > have thought that 6 orders of magnitude (1 ppm) was -120 dB not -240 dB > 20 * log10 (10**-6) = 20 * -6 = -120 No, Rick made an arithmetic mistake, or he doubled his dB twice. And I didn't notice in my posting where I went on and on about the difficulty of verifying -240dBc, and the uselessness thereof. (-120dBc is still exceedingly hard to achieve in analog-land, and not necessarily useful in digital-land unless your goal is to be so damned good that you never have to worry about that being the source of your problems). dBc simply means "dB referenced to the carrier", so a signal that's -20dBc is 1/10th the amplitude, and 1/100th the power, of the carrier. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com From newsfish@newsfish Thu Aug 1 00:31:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 19 Dec 2014 18:19:24 -0500 Organization: A noiseless patient Spider Lines: 51 Message-ID: References: Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Dec 2014 23:19:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="e1858bee1a7b8abf48ddd79e9de335b2"; logging-data="31810"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/LyonnfrUWzQrK3tpXIu+3" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:xD71z9TdmTmTK/20WByIsIIpfYE= Xref: news.eternal-september.org comp.dsp:25974 comp.lang.vhdl:3453 On 12/19/14 10:06 AM, rickman wrote: > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. i still get the concepts of DDS and NCO mixed up. what are the differences? is this a circuit with an analog output? or are you looking at the stream of samples before they get to the D/A converter? > My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too easy > to get such good results. I guess I'm worried that it will be hard to > measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. okay so you're at the samples before they're output to the D/A. instead of, i presume windowing with a decent window (like a Kaiser, but a Hamming might do in a pinch), using the FFT and looking for how clean the spike is, i would suggest a notch filter tuned to the frequency that you *know* is coming out of the NCO because you know the phase increment. or is this DDS generated differently than an NCO, like using some recursion equation? anyway, whatever comes out of that precisely-tuned, narrowband notch filter is the error signal. if there are spurs or whatever distortion, it will be in that notch filter output. > The implementation will be synthesizable and the > measurement code will not. i dunno what synthesizable code is. > I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. i wouldn't bother with the FFT unless you want to run it on the notch filter output. if you have an FFT in your toolbag, it sounds like your code is floating point. is that the case? because with "vhdl", that sounds like it might be a fixed-point architecture. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Thu Aug 1 00:31:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 19 Dec 2014 18:19:57 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 19 Dec 2014 18:19:58 -0600 Lines: 64 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-7QH/pWGcbnxd5UWQvCTN0EPZQhtWXMOtP91c8jnHCJ3z58KnIFfGJ39o3+aqO7p3jfhfaJXX0L+Aw6s!RXn+9siOTxRJK2jQvijpiX366FN0SX1l6iOtjjJHK+AQuyZChj+AMBVDMFtGE/Kp62f4hogA8JMH X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3844 X-Received-Bytes: 3956 X-Received-Body-CRC: 3173327248 Xref: news.eternal-september.org comp.dsp:25975 comp.lang.vhdl:3454 On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson wrote: > On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an >> FFT is the best way to do this. I'm mainly concerned with the "close >> in" spurs that are often generated by a DDS. > > i still get the concepts of DDS and NCO mixed up. what are the > differences? > > is this a circuit with an analog output? or are you looking at the > stream of samples before they get to the D/A converter? > > >> My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be hard >> to measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. > > okay so you're at the samples before they're output to the D/A. instead > of, i presume windowing with a decent window (like a Kaiser, but a > Hamming might do in a pinch), using the FFT and looking for how clean > the spike is, i would suggest a notch filter tuned to the frequency that > you *know* is coming out of the NCO because you know the phase > increment. or is this DDS generated differently than an NCO, like using > some recursion equation? anyway, whatever comes out of that > precisely-tuned, narrowband notch filter is the error signal. if there > are spurs or whatever distortion, it will be in that notch filter > output. > >> The implementation will be synthesizable and the measurement code will >> not. > > i dunno what synthesizable code is. Synthesizable code is code that the tool knows how to make into FPGA firmware. HDL projects generally have both a hardware description component which is synthesizable (or at least one fervently hopes) and a test component which generally is not. The tools will simulate the whole design under the control of the test component. >> I'm thinking a fairly large FFT, 2048 or maybe 4096 bins in floating >> point. > > i wouldn't bother with the FFT unless you want to run it on the notch > filter output. if you have an FFT in your toolbag, it sounds like your > code is floating point. is that the case? because with "vhdl", that > sounds like it might be a fixed-point architecture. The test component can have floating point. For that matter, FPGAs are big enough to support code bloat these days; it's not unheard of to have floating-point math on them, although I think that fixed-point math is still the most common. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com From newsfish@newsfish Thu Aug 1 00:31:54 2024 X-Received: by 10.236.63.6 with SMTP id z6mr8337536yhc.47.1419041798503; Fri, 19 Dec 2014 18:16:38 -0800 (PST) X-Received: by 10.140.87.68 with SMTP id q62mr1037qgd.8.1419041798486; Fri, 19 Dec 2014 18:16:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!dc16no413284qab.1!news-out.google.com!r1ni87qat.1!nntp.google.com!v10no12704qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Dec 2014 18:16:38 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.6.79; posting-account=tpu9BAoAAAAZL2gZtrWqYIYAoMw9iVDq NNTP-Posting-Host: 72.64.6.79 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> Subject: Re: Spectral Purity Measurement From: Brian Davis Injection-Date: Sat, 20 Dec 2014 02:16:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2260 X-Received-Body-CRC: 620307632 Xref: news.eternal-september.org comp.lang.vhdl:3455 On Friday, December 19, 2014 10:07:02 AM UTC-5, rickman wrote: > > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. > I've posted some notes to comp.arch.fpga about this on occasion; the following post provides some analysis examples and links to modeling software: https://groups.google.com/forum/#!msg/comp.arch.fpga/MAyeKC9SRDI/H9vE28kvuF0J > > I'm thinking a fairly large FFT, 2048 or maybe 4096 bins in floating point. > Typically you'll need a much bigger FFT than that to see the close in stuff, the dds_oddities.pdf examples from the above links used variable sizes up to 2 Mpoints. Another difficulty in seeing these close in spurs with an FFT is that the "Grand Repetition Period" of a DDS with a large phase accumulator is so long that brute force FFT analysis of the whole truncation/quantization sequence is practically impossible. You can make some headway on this (for certain sequences) by precessing the phase of the DDS to near one of the truncation transients such that the transient occurs midway through the FFT input record. -Brian From newsfish@newsfish Thu Aug 1 00:31:54 2024 X-Received: by 10.66.179.140 with SMTP id dg12mr8727377pac.9.1419042412421; Fri, 19 Dec 2014 18:26:52 -0800 (PST) X-Received: by 10.140.18.173 with SMTP id 42mr40qgf.9.1419042412368; Fri, 19 Dec 2014 18:26:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no26487250igd.0!news-out.google.com!r1ni76qat.1!nntp.google.com!dc16no414694qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Dec 2014 18:26:52 -0800 (PST) In-Reply-To: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.6.79; posting-account=tpu9BAoAAAAZL2gZtrWqYIYAoMw9iVDq NNTP-Posting-Host: 72.64.6.79 References: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Spectral Purity Measurement From: Brian Davis Injection-Date: Sat, 20 Dec 2014 02:26:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 23 X-Received-Bytes: 2014 X-Received-Body-CRC: 81075505 Xref: news.eternal-september.org comp.lang.vhdl:3456 Earlier, I wrote: > > I've posted some notes to comp.arch.fpga about this > on occasion; the following post provides some analysis > examples and links to modeling software: > > https://groups.google.com/forum/#!msg/comp.arch.fpga/MAyeKC9SRDI/H9vE28kvuF0J > Updated location of the broken link[2] from that old post: https://sites.google.com/site/fpgastuff/dds_oddities.pdf " "[1] close in DDS phase noise artifacts: " http://groups.google.com/group/comp.arch.fpga/msg/0b1a2f345aa1c350 " "[2] plots of DDS spur pileups ( modeling numeical spurs only ) " http://members.aol.com/fpgastuff/dds_oddities.pdf " "[3] related posts about the pdf file in [2] " http://groups.yahoo.com/group/spectrumanalyzer/message/1027 " http://groups.yahoo.com/group/spectrumanalyzer/message/1038 " -Brian From newsfish@newsfish Thu Aug 1 00:31:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 04:04:06 GMT Organization: Anchor Hill Communications Lines: 67 Message-ID: <5494f4a1.456409145@news.eternal-september.org> References: Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="18383"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/jWvDY9Z2Tv08UlwQ1bXiA2RsDAX6LGpI=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141219-1, 12/19/2014), Outbound message Cancel-Lock: sha1:jmvzmeg1Yo3BWMV5/pyVM6ea1YU= Xref: news.eternal-september.org comp.dsp:25977 comp.lang.vhdl:3457 On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson wrote: >On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. > >i still get the concepts of DDS and NCO mixed up. what are the differences? One is spelled DDS and the other is spelled NCO. They're basically the same thing, like 4WD and AWD. The difference is mostly marketing. ;) >is this a circuit with an analog output? or are you looking at the >stream of samples before they get to the D/A converter? > > >> My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too easy >> to get such good results. I guess I'm worried that it will be hard to >> measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. > >okay so you're at the samples before they're output to the D/A. instead >of, i presume windowing with a decent window (like a Kaiser, but a >Hamming might do in a pinch), using the FFT and looking for how clean >the spike is, i would suggest a notch filter tuned to the frequency that >you *know* is coming out of the NCO because you know the phase >increment. or is this DDS generated differently than an NCO, like using >some recursion equation? anyway, whatever comes out of that >precisely-tuned, narrowband notch filter is the error signal. if there >are spurs or whatever distortion, it will be in that notch filter output. > >> The implementation will be synthesizable and the >> measurement code will not. > >i dunno what synthesizable code is. Hardware Description Language that can be synthesized to gates or other hardware. >> I'm thinking a fairly large FFT, 2048 or >> maybe 4096 bins in floating point. > >i wouldn't bother with the FFT unless you want to run it on the notch >filter output. if you have an FFT in your toolbag, it sounds like your >code is floating point. is that the case? because with "vhdl", that >sounds like it might be a fixed-point architecture. > > >-- > >r b-j rbj@audioimagination.com > >"Imagination is more important than knowledge." > > Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:31:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 01:54:52 -0500 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Dec 2014 06:54:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14745"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18F4sgmw0MgDbooXlByH7+N" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:Z1xBZpsst788l902l6G6ShpgRcc= Xref: news.eternal-september.org comp.lang.vhdl:3458 On 12/19/2014 9:26 PM, Brian Davis wrote: > Earlier, I wrote: >> >> I've posted some notes to comp.arch.fpga about this >> on occasion; the following post provides some analysis >> examples and links to modeling software: >> >> https://groups.google.com/forum/#!msg/comp.arch.fpga/MAyeKC9SRDI/H9vE28kvuF0J >> > > Updated location of the broken link[2] from that old post: > https://sites.google.com/site/fpgastuff/dds_oddities.pdf > " > "[1] close in DDS phase noise artifacts: > " http://groups.google.com/group/comp.arch.fpga/msg/0b1a2f345aa1c350 > " > "[2] plots of DDS spur pileups ( modeling numeical spurs only ) > " http://members.aol.com/fpgastuff/dds_oddities.pdf > " > "[3] related posts about the pdf file in [2] > " http://groups.yahoo.com/group/spectrumanalyzer/message/1027 > " http://groups.yahoo.com/group/spectrumanalyzer/message/1038 > " Thank you for the references. The PDF file was especially interesting with all the plots of effects of PT and AQ. Just curious, what is up with the AOL thing? I couldn't view the link without joining. What good is posting content people can't view? -- Rick From newsfish@newsfish Thu Aug 1 00:31:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 11:05:54 +0000 (UTC) Organization: A noiseless patient Spider Lines: 23 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 20 Dec 2014 11:05:54 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="9827"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19MX9kUUo8XMUBZDUXgVtEstbpXI2mmbQM=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:qsFCK9UIPj1wu338MNAPFMoWouY= Xref: news.eternal-september.org comp.dsp:25978 comp.lang.vhdl:3459 On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. 1ppm would be 120dBc, surely... (20 bits) I believe you can subtract an ideal signal, then FFT the remainder. You may also want to downconvert to a relatively low frequency so that you can get a decent bin spacing to examine close-in spurs. - Brian From newsfish@newsfish Thu Aug 1 00:31:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: N0Spam@daqarta.com (Bob Masta) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 13:29:15 GMT Organization: Interstellar Research Lines: 23 Message-ID: <549578bc.631514@news.eternal-september.org> References: Reply-To: NoSpam@daqarta.com Injection-Info: mx02.eternal-september.org; posting-host="1f489ea76e115f0420309a4a7252d84a"; logging-data="27293"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jFX9MmS70nMeiVZyMGq8Mxxil4OZVt18=" X-Newsreader: Forte Free Agent 1.11/32.235 Cancel-Lock: sha1:F8hXYGb+I3xs1JIHgU+nuLeIELc= Xref: news.eternal-september.org comp.dsp:25979 comp.lang.vhdl:3460 On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson wrote: >On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. > >i still get the concepts of DDS and NCO mixed up. what are the differences? According to Wikipedia (under "numerically controlled oscillator") the NCO is the digital part, which drives a DAC to make a DDS. Bob Masta DAQARTA v7.60 Data AcQuisition And Real-Time Analysis www.daqarta.com Scope, Spectrum, Spectrogram, Sound Level Meter Frequency Counter, Pitch Track, Pitch-to-MIDI FREE Signal Generator, DaqMusiq generator Science with your sound card! From newsfish@newsfish Thu Aug 1 00:31:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 20 Dec 2014 13:43:55 GMT Lines: 56 Message-ID: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: a55b373a.news.astraweb.com X-Trace: DXC=GIUoV^?kWc2Of6BS7?ncjjh_8]Unb> I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. BTW, you are looking for spurs at -120dBc, not -240dBc. An FFT is part of the solution, but naively FFTing the DDS output waveform won't give you good results. Consider the difference between a regular Spectrum Analyser and a Phase Noise test set. The Phase Noise test set is really just a sort of spectrum analyser but it is designed for looking at low level phase noise. Keysight (used to be Agilent) claim to have a sensitivity of about -180 dBc/Hz on their top of the line model. That's an awful lot better than any regular SA. (It also claims to work to 110GHz.) The trick is to get rid of the carrier before calculating the spectrum. The FFT only needs to see the noise, rather than the signal + noise. May I suggest you do the following in your HDL simulation: 1. Generate an "ideal" reference waveform. Use floating point (but use it carefully). 2. Mix this ideal waveform with the waveform from your simulated DDS. You can use a real mixer (i.e. a multiplier). The ideal waveform and the DDS output must be close to pi/2 out of phase. The accuracy of this phase shift determines the amount of carrier cancellation. 3. Get rid of the 2F component at the output of the mixer, i.e. low pass filter. 4. FFT the output of the lpf. 5a Spend half an hour scratching your head trying to work out how to interpret the results. 5b. Decide that the maths is beyond human comprehension. At this point, you either refer to some HP system journal from last century, or determine the scale factors empirically by measuring a test signal with a known amount of phase or frequency modulation. Allan From newsfish@newsfish Thu Aug 1 00:31:56 2024 X-Received: by 10.66.182.7 with SMTP id ea7mr10439532pac.23.1419086258515; Sat, 20 Dec 2014 06:37:38 -0800 (PST) X-Received: by 10.140.18.173 with SMTP id 42mr28724qgf.9.1419086258468; Sat, 20 Dec 2014 06:37:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no14944034igd.0!news-out.google.com!r1ni87qat.1!nntp.google.com!v10no184820qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Dec 2014 06:37:38 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.6.79; posting-account=tpu9BAoAAAAZL2gZtrWqYIYAoMw9iVDq NNTP-Posting-Host: 72.64.6.79 References: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Spectral Purity Measurement From: Brian Davis Injection-Date: Sat, 20 Dec 2014 14:37:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2416 X-Received-Body-CRC: 4258892891 Xref: news.eternal-september.org comp.lang.vhdl:3462 On Saturday, December 20, 2014 1:55:06 AM UTC-5, rickman wrote: > >> Updated location of the broken link[2] from that old post: >> https://sites.google.com/site/fpgastuff/dds_oddities.pdf >=20 > Thank you for the references. The PDF file was especially interesting=20 > with all the plots of effects of PT and AQ. >=20 > Just curious, what is up with the AOL thing? I couldn't view the link=20 > without joining. What good is posting content people can't view? >=20 AOL used to provide free FTP space, but silently axed the service about 5 = years ago, so the files aren't there anymore; I moved all the stuff I'd pos= ted over the years to that new google sites page. I think that the login re= direct you're seeing is just some sort of broken link default for their sit= e. Allan wrote: > Consider the difference between a regular Spectrum Analyser=20 > and a Phase Noise test set. The Phase Noise test set is really=20 > just a sort of spectrum analyser but it is designed for looking > at low level phase noise. I first noticed these close-in spurious effects whilst measuring DDS phase= noise on a 3048A in the early 90's :) =20 -Brian From newsfish@newsfish Thu Aug 1 00:31:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 20 Dec 2014 15:06:41 GMT Lines: 67 Message-ID: <54959080$0$11124$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 43f189fd.news.astraweb.com X-Trace: DXC=kP2LRe3cEUF0UO2<>T]L;AL?0kYOcDh@JW\:Hm@YlDbJeDjgCTE@N;IAg3ieXVF9\HS8EWM:L2H[E Xref: news.eternal-september.org comp.dsp:25981 comp.lang.vhdl:3463 On Sat, 20 Dec 2014 13:43:55 +0000, Allan Herriman wrote: > On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: > >> I want to analyze the output of a DDS circuit and am wondering if an >> FFT is the best way to do this. I'm mainly concerned with the "close >> in" spurs that are often generated by a DDS. My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be >> hard to measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. The implementation will be synthesizable and the >> measurement code will not. I'm thinking a fairly large FFT, 2048 or >> maybe 4096 bins in floating point. > > > BTW, you are looking for spurs at -120dBc, not -240dBc. > > > An FFT is part of the solution, but naively FFTing the DDS output > waveform won't give you good results. > > Consider the difference between a regular Spectrum Analyser and a Phase > Noise test set. The Phase Noise test set is really just a sort of > spectrum analyser but it is designed for looking at low level phase > noise. Keysight (used to be Agilent) claim to have a sensitivity of > about -180 dBc/Hz on their top of the line model. That's an awful lot > better than any regular SA. (It also claims to work to 110GHz.) > > The trick is to get rid of the carrier before calculating the spectrum. > The FFT only needs to see the noise, rather than the signal + noise. > > May I suggest you do the following in your HDL simulation: > > 1. Generate an "ideal" reference waveform. Use floating point (but use > it carefully). > > 2. Mix this ideal waveform with the waveform from your simulated DDS. > You can use a real mixer (i.e. a multiplier). The ideal waveform and > the DDS output must be close to pi/2 out of phase. The accuracy of this > phase shift determines the amount of carrier cancellation. > > 3. Get rid of the 2F component at the output of the mixer, i.e. low > pass filter. > > 4. FFT the output of the lpf. > > 5a Spend half an hour scratching your head trying to work out how to > interpret the results. > > 5b. Decide that the maths is beyond human comprehension. At this > point, > you either refer to some HP system journal from last century, or > determine the scale factors empirically by measuring a test signal with > a known amount of phase or frequency modulation. > > Allan oops, forgot to mention that after you get rid of the carrier by mixing down to 0Hz (in step 2) and removing the 2F components (in step 3), you can decimate the signal to reduce the bandwidth. This allows you to avoid the need to calculate monster FFTs if you're only interested in the "close in" spurs. Allan From newsfish@newsfish Thu Aug 1 00:31:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 19:43:33 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 71 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.dsp:25983 comp.lang.vhdl:3464 In comp.dsp Allan Herriman wrote: > On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be hard >> to measure such low levels. (snip) > BTW, you are looking for spurs at -120dBc, not -240dBc. > An FFT is part of the solution, but naively FFTing the DDS output > waveform won't give you good results. > Consider the difference between a regular Spectrum Analyser and a Phase > Noise test set. The Phase Noise test set is really just a sort of > spectrum analyser but it is designed for looking at low level phase > noise. Keysight (used to be Agilent) claim to have a sensitivity of > about -180 dBc/Hz on their top of the line model. That's an awful lot > better than any regular SA. (It also claims to work to 110GHz.) > The trick is to get rid of the carrier before calculating the spectrum. > The FFT only needs to see the noise, rather than the signal + noise. > May I suggest you do the following in your HDL simulation: > 1. Generate an "ideal" reference waveform. Use floating point (but use it carefully). My choice would be fixed point. With fixed point, you know exactly how the rounding is done, and it is done independent of the size of the values at any point in the computation. You could, for example, use 64 bit fixed point instead of 64 bit floating point. > 2. Mix this ideal waveform with the waveform from your simulated DDS. > You can use a real mixer (i.e. a multiplier). The ideal waveform and the > DDS output must be close to pi/2 out of phase. The accuracy of this > phase shift determines the amount of carrier cancellation. Pretty much you are computing, and then subtracting, one frequency (Fourier) component from the signal. You need enough bits (accuracy) to not have rounding contribute to the result (noise). > 3. Get rid of the 2F component at the output of the mixer, > i.e. low pass filter. > 4. FFT the output of the lpf. For fixed point FFT, the values can increase one bit at each stage of the FFT. On average they will increase by sqrt(2) (RMS), but if the orginal carrier is still there, you likely get an increase by a factor of 2 in some bin. If you have enough bits, original signal resolution plus log2(FFT length) seems to me you could just run it through the FFT. Well, that might work best if the carrier was in a single bin. > 5a Spend half an hour scratching your head trying to work out how to > interpret the results. > 5b. Decide that the maths is beyond human comprehension. At this point, > you either refer to some HP system journal from last century, or > determine the scale factors empirically by measuring a test signal with a > known amount of phase or frequency modulation. -- glen From newsfish@newsfish Thu Aug 1 00:31:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.albasani.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 21 Dec 2014 04:33:28 GMT Lines: 38 Message-ID: <54964d98$0$21718$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 83f41704.news.astraweb.com X-Trace: DXC=GBbFdFZaRH2 In comp.dsp Allan Herriman wrote: >> 1. Generate an "ideal" reference waveform. Use floating point > (but use it carefully). > > My choice would be fixed point. > > With fixed point, you know exactly how the rounding is done, and it is > done independent of the size of the values at any point in the > computation. You could, for example, use 64 bit fixed point instead of > 64 bit floating point. Rickman appears to be writing a testbench in VHDL. If that is the case, he already has double precision floating point trig functions built in to his simulator (in package ieee.math_real). To use fixed point would be to reimplement and verify the trig functions from scratch - a task that is possibly harder than the original problem he is trying to solve. In general though, I do take your point about the rounding. I would also hazard a guess that Rickman is outputting samples from his testbench and then using a standalone FFT package (outside the VHDL simulation environment) instead of trying to code the FFT in VHDL. I guess this will probably only use floating point. I was thinking about the size of the FFT. The DDS is an FSM. The output is periodic. It's possible to match the number of points in the FFT to the number of states in the FSM, completely eliminating spectral leakage due to windowing. But I suspect he's using a 32 bit phase accumulator, which would rule out this approach. (How big can FFTs get these days? The largest I've ever done had 2**19 complex points, but that was last century on a Sparc.) Regards, Allan From newsfish@newsfish Thu Aug 1 00:31:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 01:28:00 -0500 Organization: A noiseless patient Spider Lines: 55 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Dec 2014 06:27:49 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="18609"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19wuxCOMuartm+KPoyt9vUa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <54964d98$0$21718$c3e8da3@news.astraweb.com> Cancel-Lock: sha1:iNhnttEGs2y1qD7ywcbbN3ai8l0= Xref: news.eternal-september.org comp.dsp:25987 comp.lang.vhdl:3466 On 12/20/2014 11:33 PM, Allan Herriman wrote: > On Sat, 20 Dec 2014 19:43:33 +0000, glen herrmannsfeldt wrote: > >> In comp.dsp Allan Herriman wrote: > >>> 1. Generate an "ideal" reference waveform. Use floating point >> (but use it carefully). >> >> My choice would be fixed point. >> >> With fixed point, you know exactly how the rounding is done, and it is >> done independent of the size of the values at any point in the >> computation. You could, for example, use 64 bit fixed point instead of >> 64 bit floating point. > > Rickman appears to be writing a testbench in VHDL. If that is the case, > he already has double precision floating point trig functions built in to > his simulator (in package ieee.math_real). To use fixed point would be > to reimplement and verify the trig functions from scratch - a task that > is possibly harder than the original problem he is trying to solve. A reasonable assumption although I couldn't find info that said that reals were double precision (64 bit). In fact, the info I found said they are only assured to be 32 bit, single precision. Is that wrong? If the VHDL floating point only has a 24 bit mantissa the resolution is only slightly better than the signals I am attempting to measure. In that case I would consider writing out the NCO data to a file for processing in some other environment. In fact, maybe I should do that anyway for multiple reasons. I understand there are open source packages similar to Matlab. I may try using one of these. > In general though, I do take your point about the rounding. > > I would also hazard a guess that Rickman is outputting samples from his > testbench and then using a standalone FFT package (outside the VHDL > simulation environment) instead of trying to code the FFT in VHDL. I > guess this will probably only use floating point. > > > I was thinking about the size of the FFT. The DDS is an FSM. The output > is periodic. It's possible to match the number of points in the FFT to > the number of states in the FSM, completely eliminating spectral leakage > due to windowing. But I suspect he's using a 32 bit phase accumulator, > which would rule out this approach. (How big can FFTs get these days? > The largest I've ever done had 2**19 complex points, but that was last > century on a Sparc.) Once I find the spurs in an FFT, I can narrow down the search to selected bins and use a DFT. -- Rick From newsfish@newsfish Thu Aug 1 00:31:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 21 Dec 2014 11:03:38 GMT Lines: 21 Message-ID: <5496a90a$0$11117$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 5942ee25.news.astraweb.com X-Trace: DXC=`K6_UHb1b4VkR1VMS3E6>\L?0kYOcDh@ZW\:Hm@YlDbZ\Z=oIO[;=mTAg3ieXVF9\X5mUR5neNX1] Xref: news.eternal-september.org comp.dsp:25990 comp.lang.vhdl:3467 On Sun, 21 Dec 2014 01:28:00 -0500, rickman wrote: > A reasonable assumption although I couldn't find info that said that > reals were double precision (64 bit). In fact, the info I found said > they are only assured to be 32 bit, single precision. Is that wrong? That's a good point. It's implementation dependent. The old version of Modelsim that I have on this computer has this in the source for the std library: type real is range -1.0E308 to 1.0E308; which is equivalent to 64 bit "double". I don't imagine that any mainstream compiler would use less than 64 bits for real, but I could be wrong. OTOH, if you know that all the compilers you're using support 64 bit, it's probably safe to rely on that. Regards, Allan From newsfish@newsfish Thu Aug 1 00:31:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: HpW-Works Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 11:20:02 -0300 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Dec 2014 14:19:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="6c3e357dc38119382b92f62f4efda144"; logging-data="31865"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+NqSuX4Hc8BO9jkI+xAjA47RLEG/gb5MM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:p+tXpAGX3I80mEtfFcxzq5p+kiY= Xref: news.eternal-september.org comp.dsp:25991 comp.lang.vhdl:3468 Am 19.12.2014 15:24, schrieb Tim Wescott: > No spectrum analyzer in the world has a 240dB dynamic > range Hmm, yes analog based on the todays ADC limitations O:( My PC based spectrum analyser supports more then an 240dB dynamic range, while internal calculations are done using double float and even 80 bit float O;) Hp www.hpw-works.com From newsfish@newsfish Thu Aug 1 00:31:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: chrisabele Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 09:49:42 -0500 Lines: 11 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net GlvMCPid4YrfgaqNQfhgrA15ANm+kC5reYEuWYR12B7LbpJcp4 Cancel-Lock: sha1:OgZ7yWM6B8XYYNNbO1jSPQETPek= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Xref: news.eternal-september.org comp.dsp:25992 comp.lang.vhdl:3469 On 12/21/2014 1:28 AM, rickman wrote: > > I understand there are open source > packages similar to Matlab. I may try using one of these. > I've found Scilab (http://www.scilab.org/) to be a very functional and well supported alternative to Matlab, at a compelling price point (free). From newsfish@newsfish Thu Aug 1 00:31:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Gerhard Hoffmann Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 17:11:03 +0100 Lines: 39 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> Reply-To: ghf@hoffmann-hochfrequenz.de Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net AvVnyRpL1+CORgz++jTP0w6rXv9VGKPIavD0opRuZ8xjSzVJgW Cancel-Lock: sha1:ncf4EZFXeMJjLhOFawr8Jfzmmxc= User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <54964d98$0$21718$c3e8da3@news.astraweb.com> Xref: news.eternal-september.org comp.dsp:25993 comp.lang.vhdl:3470 Am 21.12.2014 um 05:33 schrieb Allan Herriman: > On Sat, 20 Dec 2014 19:43:33 +0000, glen herrmannsfeldt wrote: > >> In comp.dsp Allan Herriman wrote: > >>> 1. Generate an "ideal" reference waveform. Use floating point >> (but use it carefully). >> >> My choice would be fixed point. >> >> With fixed point, you know exactly how the rounding is done, and it is >> done independent of the size of the values at any point in the >> computation. You could, for example, use 64 bit fixed point instead of >> 64 bit floating point. > > Rickman appears to be writing a testbench in VHDL. If that is the case, > he already has double precision floating point trig functions built in to > his simulator (in package ieee.math_real). To use fixed point would be > to reimplement and verify the trig functions from scratch - a task that > is possibly harder than the original problem he is trying to solve. The test bed for my sine & cos functions on opencores can write the time series generated by a DDS to a file that could be used for further processing with matlab or whatever. There are also functions to convert between float and un/signed and fractional un/signed. They expect however, that the floats are higher resolution than the signed vectors, they will cease to work when one approaches 48 bit or whatever the size of the mantissa happens to be. Going via int/natural would be even more limiting (31 bit). regards, Gerhard < http://opencores.org/project,sincos > From newsfish@newsfish Thu Aug 1 00:31:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 12:05:39 -0500 Organization: A noiseless patient Spider Lines: 43 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Dec 2014 17:05:29 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13365"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19pcslpI9BlDCUpFvHZk3VB" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:UfnZAn30K1ZCf5o1RVKx0Rzn/no= Xref: news.eternal-september.org comp.dsp:25994 comp.lang.vhdl:3471 On 12/21/2014 11:11 AM, Gerhard Hoffmann wrote: > Am 21.12.2014 um 05:33 schrieb Allan Herriman: >> On Sat, 20 Dec 2014 19:43:33 +0000, glen herrmannsfeldt wrote: >> >>> In comp.dsp Allan Herriman wrote: >> >>>> 1. Generate an "ideal" reference waveform. Use floating point >>> (but use it carefully). >>> >>> My choice would be fixed point. >>> >>> With fixed point, you know exactly how the rounding is done, and it is >>> done independent of the size of the values at any point in the >>> computation. You could, for example, use 64 bit fixed point instead of >>> 64 bit floating point. >> >> Rickman appears to be writing a testbench in VHDL. If that is the case, >> he already has double precision floating point trig functions built in to >> his simulator (in package ieee.math_real). To use fixed point would be >> to reimplement and verify the trig functions from scratch - a task that >> is possibly harder than the original problem he is trying to solve. > > The test bed for my sine & cos functions on opencores can write > the time series generated by a DDS to a file that could be used > for further processing with matlab or whatever. > > There are also functions to convert between float and un/signed > and fractional un/signed. They expect however, that > the floats are higher resolution than the signed vectors, they > will cease to work when one approaches 48 bit or whatever the > size of the mantissa happens to be. > > Going via int/natural would be even more limiting (31 bit). > > regards, Gerhard > > < http://opencores.org/project,sincos > Thanks, I'll take a look. :) -- Rick From newsfish@newsfish Thu Aug 1 00:31:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 14:52:40 -0500 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Dec 2014 19:52:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="93a28beffd6034b7478094f1f552d895"; logging-data="23774"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++R87hlGqV/n+Y5V34yBZX" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: <5494f4a1.456409145@news.eternal-september.org> Cancel-Lock: sha1:VhULhLQqX06RjWOfluWLmaM5Wbk= Xref: news.eternal-september.org comp.dsp:25995 comp.lang.vhdl:3472 On 12/19/14 11:04 PM, Eric Jacobsen wrote: > On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson > wrote: > >> On 12/19/14 10:06 AM, rickman wrote: >>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>> is the best way to do this. I'm mainly concerned with the "close in" >>> spurs that are often generated by a DDS. >> >> i still get the concepts of DDS and NCO mixed up. what are the differences? > > One is spelled DDS and the other is spelled NCO. is the NCO the typical table-lookup kind (with phase accumulator)? or can it be algorithmic? like y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] where omega_0 is the normalized angular frequency of the sinusoid and with appropriate initial states, y[-1] and y[-2] to result in the amplitude and initial phase desired. is that an NCO that can be used in this DDS? or must it be LUT? anyway, in either case, the oscillator frequency is well defined and i don't understand why rickman would just put in a simple sharp notch filter tuned to the very same frequency and whack the sinusoid and analyze (however he does) what is residual. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Thu Aug 1 00:32:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Mon, 22 Dec 2014 00:13:10 GMT Organization: Anchor Hill Communications Lines: 47 Message-ID: <549760f9.615217305@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="17843"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+B0suBGDRsxQNlZ7/6H9USP4cBFfA+byw=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141221-1, 12/21/2014), Outbound message Cancel-Lock: sha1:exxRL9pSDUDqwezgUwkhYF5RWVI= Xref: news.eternal-september.org comp.dsp:25996 comp.lang.vhdl:3473 On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson wrote: >On 12/19/14 11:04 PM, Eric Jacobsen wrote: >> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >> wrote: >> >>> On 12/19/14 10:06 AM, rickman wrote: >>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>> is the best way to do this. I'm mainly concerned with the "close in" >>>> spurs that are often generated by a DDS. >>> >>> i still get the concepts of DDS and NCO mixed up. what are the differences? >> >> One is spelled DDS and the other is spelled NCO. > >is the NCO the typical table-lookup kind (with phase accumulator)? or >can it be algorithmic? like > > y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] > >where omega_0 is the normalized angular frequency of the sinusoid and >with appropriate initial states, y[-1] and y[-2] to result in the >amplitude and initial phase desired. > >is that an NCO that can be used in this DDS? or must it be LUT? Generally NCO or DDS refers to a phase accumulator with a LUT, since it is easily implemented in hardware. That's a general architecture that is well-known and can be adjusted to produce very clean local oscillators. If somebody tried to sell me a block of IP with an "NCO" built some other way I'd be asking a lot of questions. >anyway, in either case, the oscillator frequency is well defined and i >don't understand why rickman would just put in a simple sharp notch >filter tuned to the very same frequency and whack the sinusoid and >analyze (however he does) what is residual. It could be because the phase accumulator/LUT architecture is general and the range of operation of the output frequency is pretty broad. A more generalized test approach is more flexible to testing over a broader range of outputs. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 19:30:48 -0500 Organization: A noiseless patient Spider Lines: 76 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 22 Dec 2014 00:30:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21463"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19groOp5Mdx+9Ej1Rylh7JX" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549760f9.615217305@news.eternal-september.org> Cancel-Lock: sha1:C29TAPmyyRgvewU/M8WYyMHvrQc= Xref: news.eternal-september.org comp.dsp:25997 comp.lang.vhdl:3474 On 12/21/2014 7:13 PM, Eric Jacobsen wrote: > On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson > wrote: > >> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>> wrote: >>> >>>> On 12/19/14 10:06 AM, rickman wrote: >>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>> spurs that are often generated by a DDS. >>>> >>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>> >>> One is spelled DDS and the other is spelled NCO. >> >> is the NCO the typical table-lookup kind (with phase accumulator)? or >> can it be algorithmic? like >> >> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >> >> where omega_0 is the normalized angular frequency of the sinusoid and >> with appropriate initial states, y[-1] and y[-2] to result in the >> amplitude and initial phase desired. >> >> is that an NCO that can be used in this DDS? or must it be LUT? > > Generally NCO or DDS refers to a phase accumulator with a LUT, since > it is easily implemented in hardware. That's a general architecture > that is well-known and can be adjusted to produce very clean local > oscillators. If somebody tried to sell me a block of IP with an > "NCO" built some other way I'd be asking a lot of questions. Actually this started with a discussion is s.e.d about how bad the spurs are with a typical DDS and how to mitigate them. That made me dig up my memory of designing a DDS a few years back as part of a test set. It didn't need to be anything special, but for grins I took a look at what could be done in a rather small FPGA for audio frequencies. I considered linear interpolation which gets around the close in spurs from phase truncation (seems to be the major objection to using a DDS) and with even a smallish LUT of 256 entries I get about 18 bit accuracy in the sine values. With a 1024 entry table the accuracy is more than 10 times better or around 21 bits. Of course quantization error will add to that, but this allows the close in spurs to be *much* smaller than with straight LUTs. >> anyway, in either case, the oscillator frequency is well defined and i >> don't understand why rickman would just put in a simple sharp notch >> filter tuned to the very same frequency and whack the sinusoid and >> analyze (however he does) what is residual. > > It could be because the phase accumulator/LUT architecture is general > and the range of operation of the output frequency is pretty broad. > A more generalized test approach is more flexible to testing over a > broader range of outputs. I'm not sure I understand the question, notwithstanding the grammar error. I think Robert meant "i don't understand why rickman >>wouldn't<< just put in"... I don't know why I wouldn't do that either. I am here asking what would be the best way. I seem to remember something similar being done in a digital receiver test. A carrier is applied to the analog input and in the digital domain (somewhere) a notch filter is used to drop out the carrier leaving most of the artifacts. It's all very fuzzy at this point. I think they also used a two tone test which shows the effects of inter-modulation products, a real concern with real signals. -- Rick From newsfish@newsfish Thu Aug 1 00:32:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!Xl.tags.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!buffer2.nntp.dca1.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 21 Dec 2014 16:44:33 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> <5496a90a$0$11117$c3e8da3@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Sun, 21 Dec 2014 16:44:33 -0600 Lines: 34 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-tyjGmkV2gQeXYlSwkxdWq+SirL4hrYR78kBNijzR1QbRx8usQvUImNpfs1BvWgMAocfMVhyJcvy4WbV!sdq9ktP7Aqx6ThYJqZxYnq9tDrjPyNyBXMIPAEtQrp1Rz5PglvtWo+nrM0JTE57tkpgeZ4865tMs X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2594 Xref: news.eternal-september.org comp.dsp:25998 comp.lang.vhdl:3475 On Sun, 21 Dec 2014 11:03:38 +0000, Allan Herriman wrote: > On Sun, 21 Dec 2014 01:28:00 -0500, rickman wrote: > >> A reasonable assumption although I couldn't find info that said that >> reals were double precision (64 bit). In fact, the info I found said >> they are only assured to be 32 bit, single precision. Is that wrong? > > That's a good point. It's implementation dependent. > > The old version of Modelsim that I have on this computer has this in the > source for the std library: > > type real is range -1.0E308 to 1.0E308; > > which is equivalent to 64 bit "double". I don't imagine that any > mainstream compiler would use less than 64 bits for real, but I could be > wrong. > OTOH, if you know that all the compilers you're using support 64 bit, > it's probably safe to rely on that. If by "compiler" you mean VHDL, I can't speak to that. However, there are a distressingly large number of C compilers for 8- and 16-bit machines that use 32-bit floating point even when you call out "double". This just torques me. While there is every reason for making comprehensive libraries that work with 32-bit floating point numbers in resource-constrained machines, you don't have to make non-ANSI-compliant code to do it. -- www.wescottdesign.com From newsfish@newsfish Thu Aug 1 00:32:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!Xl.tags.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!buffer2.nntp.dca1.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 21 Dec 2014 16:46:42 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Sun, 21 Dec 2014 16:46:42 -0600 Lines: 21 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-TTIg4kEfVN43dlBV+99F/CScHoCzgzzp58Q/4wgUlkfRAsuoMv7pYQk+8RI3DuxDkc8ukIWew37Ehp8!ywNkRv6/WFQLum/c7/jei8sazA7/NeO454QWrRXgbZEbXvyJGtaS2cEHPn92KpNwdtamKuyAZeZN X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1958 Xref: news.eternal-september.org comp.dsp:25999 comp.lang.vhdl:3476 On Sun, 21 Dec 2014 09:49:42 -0500, chrisabele wrote: > On 12/21/2014 1:28 AM, rickman wrote: > >> >> I understand there are open source packages similar to Matlab. I may >> try using one of these. >> > > > I've found Scilab (http://www.scilab.org/) to be a very functional and > well supported alternative to Matlab, at a compelling price point > (free). +1 on using Scilab, at least if you were incorrect on your 240dBc calculation. At this point, I would prefer Scilab even if it were priced the same as Matlab. It doesn't have Matlab's bells and whistle's, but it does edge Matlab out in git-er-done utility. -- www.wescottdesign.com From newsfish@newsfish Thu Aug 1 00:32:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Mon, 22 Dec 2014 19:10:27 GMT Organization: Anchor Hill Communications Lines: 110 Message-ID: <54986aaf.683238858@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="15146"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19tJRqhnNV1xo2/WsWSxT6WxK//0VwNqD8=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141222-0, 12/22/2014), Outbound message Cancel-Lock: sha1:7e5SyCEJX6ek1DzTh7GPx31U1pM= Xref: news.eternal-september.org comp.dsp:26001 comp.lang.vhdl:3477 On Sun, 21 Dec 2014 19:30:48 -0500, rickman wrote: >On 12/21/2014 7:13 PM, Eric Jacobsen wrote: >> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >> wrote: >> >>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>> spurs that are often generated by a DDS. >>>>> >>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>> >>>> One is spelled DDS and the other is spelled NCO. >>> >>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>> can it be algorithmic? like >>> >>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>> >>> where omega_0 is the normalized angular frequency of the sinusoid and >>> with appropriate initial states, y[-1] and y[-2] to result in the >>> amplitude and initial phase desired. >>> >>> is that an NCO that can be used in this DDS? or must it be LUT? >> >> Generally NCO or DDS refers to a phase accumulator with a LUT, since >> it is easily implemented in hardware. That's a general architecture >> that is well-known and can be adjusted to produce very clean local >> oscillators. If somebody tried to sell me a block of IP with an >> "NCO" built some other way I'd be asking a lot of questions. > >Actually this started with a discussion is s.e.d about how bad the spurs >are with a typical DDS and how to mitigate them. That made me dig up my >memory of designing a DDS a few years back as part of a test set. It >didn't need to be anything special, but for grins I took a look at what >could be done in a rather small FPGA for audio frequencies. I >considered linear interpolation which gets around the close in spurs >from phase truncation (seems to be the major objection to using a DDS) >and with even a smallish LUT of 256 entries I get about 18 bit accuracy >in the sine values. With a 1024 entry table the accuracy is more than >10 times better or around 21 bits. > >Of course quantization error will add to that, but this allows the close >in spurs to be *much* smaller than with straight LUTs. > > >>> anyway, in either case, the oscillator frequency is well defined and i >>> don't understand why rickman would just put in a simple sharp notch >>> filter tuned to the very same frequency and whack the sinusoid and >>> analyze (however he does) what is residual. >> >> It could be because the phase accumulator/LUT architecture is general >> and the range of operation of the output frequency is pretty broad. >> A more generalized test approach is more flexible to testing over a >> broader range of outputs. > >I'm not sure I understand the question, notwithstanding the grammar >error. I think Robert meant "i don't understand why rickman > >>wouldn't<< just put in"... > >I don't know why I wouldn't do that either. I am here asking what would >be the best way. > >I seem to remember something similar being done in a digital receiver >test. A carrier is applied to the analog input and in the digital >domain (somewhere) a notch filter is used to drop out the carrier >leaving most of the artifacts. It's all very fuzzy at this point. I >think they also used a two tone test which shows the effects of >inter-modulation products, a real concern with real signals. > >-- > >Rick Do a web search on "Analog Devices DDS", and in the first few entries you should find links to some white papers that are good on details of DDS architecture and analysis. Also, Qualcomm's "Synthesizer Products Data Book" is also very good. Some of those documents are from the 90s, and there are other public docs out there that go into more detail on spur mitigation and analysis, but these are good references. BTW, Qualcomm was a leader in supplying stand-alone silicon DDS products, which were called by the name DDS, even though they didn't have an integrated DAC. Back then mixed-signal products weren't really available. For implementations where memory is very constrained, like potentially in an FPGA, the phase resolution in the LUT can be increased 4x by only storing a quarter of the wave. We've done this in the past with good results. DDS implementations can sometimes also benefit from dithering, at the outputs of both the phase accumulator and the LUT, although the usual tradeoffs apply. There are a number of tricks that have been learned over the years, and many are application dependent. e.g., different tricks may apply for generating a low-jitter clock than generating a local oscillator. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Mon, 22 Dec 2014 15:17:23 -0700 Organization: Aioe.org NNTP Server Lines: 64 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> NNTP-Posting-Host: 670CkSRN2ntYFEZN8nXcjg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.dsp:26004 comp.lang.vhdl:3478 On 12/21/2014 5:13 PM, Eric Jacobsen wrote: > On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson > wrote: > >> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>> wrote: >>> >>>> On 12/19/14 10:06 AM, rickman wrote: >>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>> spurs that are often generated by a DDS. >>>> >>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>> >>> One is spelled DDS and the other is spelled NCO. >> >> is the NCO the typical table-lookup kind (with phase accumulator)? or >> can it be algorithmic? like >> >> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >> >> where omega_0 is the normalized angular frequency of the sinusoid and >> with appropriate initial states, y[-1] and y[-2] to result in the >> amplitude and initial phase desired. >> >> is that an NCO that can be used in this DDS? or must it be LUT? > > Generally NCO or DDS refers to a phase accumulator with a LUT, since > it is easily implemented in hardware. That's a general architecture > that is well-known and can be adjusted to produce very clean local > oscillators. If somebody tried to sell me a block of IP with an > "NCO" built some other way I'd be asking a lot of questions. I have built NCOs using CORDIC rotators. No lookup tables. They pipeline nicely and are therefore very fast, they require no multipliers [1], they generate quadrature outputs for free, they can perform frequency translations for free (again no multipliers), and they are simple prove numerical accuracy. [1] Maybe not a huge issue these days. The LUT-based NCOs requires two multipliers to combine the coarse and fine LUTs (four multipliers if you need a complex NCO output) and perhaps another four multipliers if you need to do a frequency translation. Rob. >> anyway, in either case, the oscillator frequency is well defined and i >> don't understand why rickman would just put in a simple sharp notch >> filter tuned to the very same frequency and whack the sinusoid and >> analyze (however he does) what is residual. > > It could be because the phase accumulator/LUT architecture is general > and the range of operation of the output frequency is pretty broad. > A more generalized test approach is more flexible to testing over a > broader range of outputs. > > > Eric Jacobsen > Anchor Hill Communications > http://www.anchorhill.com > From newsfish@newsfish Thu Aug 1 00:32:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Mon, 22 Dec 2014 20:25:36 -0500 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 23 Dec 2014 01:25:15 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="93a28beffd6034b7478094f1f552d895"; logging-data="7516"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19fR9Jqdyd7n6UoNynANu4E" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:oXQw9IY2E7SptBt9A9n/OiL98OE= Xref: news.eternal-september.org comp.dsp:26005 comp.lang.vhdl:3479 On 12/21/14 7:30 PM, rickman wrote: > On 12/21/2014 7:13 PM, Eric Jacobsen wrote: >> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >> wrote: >> ... >>> anyway, in either case, the oscillator frequency is well defined and i >>> don't understand why rickman would just put in a simple sharp notch >>> filter tuned to the very same frequency and whack the sinusoid and >>> analyze (however he does) what is residual. >> >> It could be because the phase accumulator/LUT architecture is general >> and the range of operation of the output frequency is pretty broad. >> A more generalized test approach is more flexible to testing over a >> broader range of outputs. > > I'm not sure I understand the question, notwithstanding the grammar > error. I think Robert meant "i don't understand why rickman >>wouldn't<< > just put in"... abstively correct. i often suffer from the "Wicked Bible" syndrome. > I don't know why I wouldn't do that either. I am here asking what would > be the best way. > > I seem to remember something similar being done in a digital receiver > test. A carrier is applied to the analog input and in the digital domain > (somewhere) a notch filter is used to drop out the carrier leaving most > of the artifacts. It's all very fuzzy at this point. I think they also > used a two tone test which shows the effects of inter-modulation > products, a real concern with real signals. okay, let's say that you have N points in your LUT. (if N is a power of two, the table wrap-around is trivial.) and let's say that there is a single cycle of a sine function in that LUT. and let's say your sample rate is Fs. the phase increment for a frequency of f0 would be phase_increment = N*(f0/Fs) every sample the phase is incremented: phase[n] = (phase[n-1] + phase_increment)modulo_N and phase[n] is divided into its integer part that tells you where to go in your LUT and a fractional part that tells you how you might interpolate. integer_part = floor(phase[n]) fractional_part = phase[n] - integer_part if you're doing no interpolation the waveform output is x[n] = LUT[integer_part] if you're doing linear interpolation the waveform output is x[n] = LUT[integer_part] + fractional_part*(LUT[integer_part+1] - LUT[integer_part]) just make sure you have an extra point at the end of your LUT that is the same as the zeroth point: LUT[N] = LUT[0] now, using that very same f0 and Fs and some Q or BW that you'll have to decide (make the BW sorta tight), then implement a very simple biquad notch filter: y[n] = b0*x[n] + b1*x[n-1] + b2*x[n-2] - a1*y[n-1] - a2*y[n-2] where b0 = b2 = 1/( 1 + sin(w0)/(2Q) ) b1 = a1 = -2*cos(w0)/(1 + sin(w0)/(2Q)) a2 = ( 1 - sin(w0)/(2Q) )/( 1 + sin(w0)/(2Q) ) and w0 = 2*pi*f0/Fs 1/Q = 2*sinh( ln(2)/2 * BW * w0/sin(w0) ) (BW in octaves) straight outa da cookbook. whatever comes out at y[n] is whatever is impure in your sinusoidal output. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Thu Aug 1 00:32:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 23 Dec 2014 09:23:35 -0600 From: techman Subject: Finding the difference between two numbers Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 513219d1-ac8c-4b5b-88e0-2ea8ad503715 Message-ID: Date: Tue, 23 Dec 2014 09:23:35 -0600 Lines: 10 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-NO0DROzUkjnb8OdBoXFIqlvFrs0KKPPUeeFu0huj5PJ3NVNmCLHLw1qnSJ6ZVprCLSHKz9bJIq2KzVP!BSnVMqdxywYlxcKzTarv87NvzNcQoj4NRrGShNRIMKx5uMLrS69Sft0C0v3KQZrLo3lFYsk6Kx9p!pKM= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1262 Xref: news.eternal-september.org comp.lang.vhdl:3480 Hi All, I would be grateful if someone can tell me the best way to find the difference between two std logic vectors which at any one time may or may not be signed. In simple terms if I was to use the integer equivalents then I would be looking for the following answers -2 -5 = 3 -2 +5 = 7 5 - 2 = 3 -5 -2 = 3 Thanks From newsfish@newsfish Thu Aug 1 00:32:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 15:35:13 GMT Organization: Anchor Hill Communications Lines: 83 Message-ID: <549989f6.756782253@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="20300"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+F2mFOyb8+L/fEc/6FEOa/oADKyWiGIK0=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141223-0, 12/23/2014), Outbound message Cancel-Lock: sha1:VqFEYr2PlleZMODyDoXLQDxKGOA= Xref: news.eternal-september.org comp.dsp:26010 comp.lang.vhdl:3481 On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle wrote: >On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >> wrote: >> >>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>> spurs that are often generated by a DDS. >>>>> >>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>> >>>> One is spelled DDS and the other is spelled NCO. >>> >>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>> can it be algorithmic? like >>> >>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>> >>> where omega_0 is the normalized angular frequency of the sinusoid and >>> with appropriate initial states, y[-1] and y[-2] to result in the >>> amplitude and initial phase desired. >>> >>> is that an NCO that can be used in this DDS? or must it be LUT? >> >> Generally NCO or DDS refers to a phase accumulator with a LUT, since >> it is easily implemented in hardware. That's a general architecture >> that is well-known and can be adjusted to produce very clean local >> oscillators. If somebody tried to sell me a block of IP with an >> "NCO" built some other way I'd be asking a lot of questions. > >I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >nicely and are therefore very fast, they require no multipliers [1], >they generate quadrature outputs for free, they can perform frequency >translations for free (again no multipliers), and they are simple prove >numerical accuracy. CORDICs are fine when and where they make sense, but they are often not the best tradeoff. If you have no memory, no multipliers, or gates are way cheaper than memory, and if the latency is tolerable, then a CORDIC may be a good option. >[1] Maybe not a huge issue these days. The LUT-based NCOs requires two >multipliers to combine the coarse and fine LUTs (four multipliers if you >need a complex NCO output) and perhaps another four multipliers if you >need to do a frequency translation. Many applications don't need separate LUTs to get the required performance, and even then, or even in the case of complex output, it can be done without multipliers. As is often the case, there are many ways to get the job done. Sometimes the complications aren't necessary, they're just convenient. >Rob. > >>> anyway, in either case, the oscillator frequency is well defined and i >>> don't understand why rickman would just put in a simple sharp notch >>> filter tuned to the very same frequency and whack the sinusoid and >>> analyze (however he does) what is residual. >> >> It could be because the phase accumulator/LUT architecture is general >> and the range of operation of the output frequency is pretty broad. >> A more generalized test approach is more flexible to testing over a >> broader range of outputs. >> >> >> Eric Jacobsen >> Anchor Hill Communications >> http://www.anchorhill.com >> > > Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 11:06:39 -0500 Organization: A noiseless patient Spider Lines: 75 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 23 Dec 2014 16:06:28 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="28140"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ApYGY5oUR6nvd77yDUG6j" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549989f6.756782253@news.eternal-september.org> Cancel-Lock: sha1:TUheB/6RO1r6U7CWmVX+FSJrqSw= Xref: news.eternal-september.org comp.dsp:26012 comp.lang.vhdl:3482 On 12/23/2014 10:35 AM, Eric Jacobsen wrote: > On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle > wrote: > >> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>> wrote: >>> >>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>> wrote: >>>>> >>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>>> spurs that are often generated by a DDS. >>>>>> >>>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>>> >>>>> One is spelled DDS and the other is spelled NCO. >>>> >>>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>>> can it be algorithmic? like >>>> >>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>> >>>> where omega_0 is the normalized angular frequency of the sinusoid and >>>> with appropriate initial states, y[-1] and y[-2] to result in the >>>> amplitude and initial phase desired. >>>> >>>> is that an NCO that can be used in this DDS? or must it be LUT? >>> >>> Generally NCO or DDS refers to a phase accumulator with a LUT, since >>> it is easily implemented in hardware. That's a general architecture >>> that is well-known and can be adjusted to produce very clean local >>> oscillators. If somebody tried to sell me a block of IP with an >>> "NCO" built some other way I'd be asking a lot of questions. >> >> I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >> nicely and are therefore very fast, they require no multipliers [1], >> they generate quadrature outputs for free, they can perform frequency >> translations for free (again no multipliers), and they are simple prove >> numerical accuracy. > > CORDICs are fine when and where they make sense, but they are often > not the best tradeoff. If you have no memory, no multipliers, or > gates are way cheaper than memory, and if the latency is tolerable, > then a CORDIC may be a good option. > >> [1] Maybe not a huge issue these days. The LUT-based NCOs requires two >> multipliers to combine the coarse and fine LUTs (four multipliers if you >> need a complex NCO output) and perhaps another four multipliers if you >> need to do a frequency translation. > > Many applications don't need separate LUTs to get the required > performance, and even then, or even in the case of complex output, it > can be done without multipliers. Care to elaborate on this? I'm not at all clear on how you make a LUT based NCO without LUTs and unless you are using a very coarse approximation, without multipliers. > As is often the case, there are many ways to get the job done. > Sometimes the complications aren't necessary, they're just convenient. Yes, there is more than one way to skin a goose. But they all have their issues. CORDIC for example, has no multiplier... but has an iteration that is essentially the same as multiplication by iteration. -- Rick From newsfish@newsfish Thu Aug 1 00:32:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed1.news.xs4all.nl!xs4all!usenetcore.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 23 Dec 2014 10:42:31 -0600 Date: Tue, 23 Dec 2014 16:42:24 +0000 From: Mike Perkins User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Finding the difference between two numbers References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 17 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-JLWur/p9kadO9VVSCdXu5UUeL+3Nkv+pCL6IS1EgL0lwy3QYiOuLyR7pn2P1bi40iZpcwxKEX5qw2OP!CpjgNSEX/7ybrMMZkilNewOG7/NW+/niiuggio4k4SlTJo1C/EYAii4hv25bhhGl7S1Kzjqt X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1745 Xref: news.eternal-september.org comp.lang.vhdl:3483 On 23/12/2014 15:23, techman wrote: > Hi All, > I would be grateful if someone can tell me the best way to find the difference between two std logic vectors which at any one time may or may not be signed. > In simple terms if I was to use the integer equivalents then I would be looking for the following answers > -2 -5 = 3 > -2 +5 = 7 > 5 - 2 = 3 > -5 -2 = 3 > Thanks I'm sorry but this is very basic. Can I suggest you google for arithmetic examples in VHDL? -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk From newsfish@newsfish Thu Aug 1 00:32:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 21:48:22 GMT Organization: Anchor Hill Communications Lines: 89 Message-ID: <5499e27d.779445002@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="13553"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19aLM+VNGzlXL6V6R5zRt3O2QAohukPQfE=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141223-0, 12/23/2014), Outbound message Cancel-Lock: sha1:nUQafofgf71naVee71EYVAB4OC8= Xref: news.eternal-september.org comp.dsp:26014 comp.lang.vhdl:3484 On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >> On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle >> wrote: >> >>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>>>> spurs that are often generated by a DDS. >>>>>>> >>>>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>>>> >>>>>> One is spelled DDS and the other is spelled NCO. >>>>> >>>>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>>>> can it be algorithmic? like >>>>> >>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>> >>>>> where omega_0 is the normalized angular frequency of the sinusoid and >>>>> with appropriate initial states, y[-1] and y[-2] to result in the >>>>> amplitude and initial phase desired. >>>>> >>>>> is that an NCO that can be used in this DDS? or must it be LUT? >>>> >>>> Generally NCO or DDS refers to a phase accumulator with a LUT, since >>>> it is easily implemented in hardware. That's a general architecture >>>> that is well-known and can be adjusted to produce very clean local >>>> oscillators. If somebody tried to sell me a block of IP with an >>>> "NCO" built some other way I'd be asking a lot of questions. >>> >>> I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >>> nicely and are therefore very fast, they require no multipliers [1], >>> they generate quadrature outputs for free, they can perform frequency >>> translations for free (again no multipliers), and they are simple prove >>> numerical accuracy. >> >> CORDICs are fine when and where they make sense, but they are often >> not the best tradeoff. If you have no memory, no multipliers, or >> gates are way cheaper than memory, and if the latency is tolerable, >> then a CORDIC may be a good option. >> >>> [1] Maybe not a huge issue these days. The LUT-based NCOs requires two >>> multipliers to combine the coarse and fine LUTs (four multipliers if you >>> need a complex NCO output) and perhaps another four multipliers if you >>> need to do a frequency translation. >> >> Many applications don't need separate LUTs to get the required >> performance, and even then, or even in the case of complex output, it >> can be done without multipliers. > >Care to elaborate on this? I'm not at all clear on how you make a LUT >based NCO without LUTs and unless you are using a very coarse >approximation, without multipliers. Not sure what you're asking. You a need a LUT, but just one in many cases. Having a dual-ported single LUT is easy in an FPGA and usually in silicon as well. What makes a multiplier necessary? I've never found the need, but my apps are limited to comm. >> As is often the case, there are many ways to get the job done. >> Sometimes the complications aren't necessary, they're just convenient. > >Yes, there is more than one way to skin a goose. But they all have >their issues. > >CORDIC for example, has no multiplier... but has an iteration that is >essentially the same as multiplication by iteration. Yup. >-- > >Rick Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 18:10:43 -0500 Organization: A noiseless patient Spider Lines: 80 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 23 Dec 2014 23:10:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="32437"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19dZGbVBA8OCtXd5nofPFRE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <5499e27d.779445002@news.eternal-september.org> Cancel-Lock: sha1:lDhLJ3J3hGrvhAtX6QJkogcaRNU= Xref: news.eternal-september.org comp.dsp:26016 comp.lang.vhdl:3485 On 12/23/2014 4:48 PM, Eric Jacobsen wrote: > On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: > >> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>> On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle >>> wrote: >>> >>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>> wrote: >>>>> >>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>> wrote: >>>>>>> >>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>>>>> spurs that are often generated by a DDS. >>>>>>>> >>>>>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>>>>> >>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>> >>>>>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>>>>> can it be algorithmic? like >>>>>> >>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>> >>>>>> where omega_0 is the normalized angular frequency of the sinusoid and >>>>>> with appropriate initial states, y[-1] and y[-2] to result in the >>>>>> amplitude and initial phase desired. >>>>>> >>>>>> is that an NCO that can be used in this DDS? or must it be LUT? >>>>> >>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, since >>>>> it is easily implemented in hardware. That's a general architecture >>>>> that is well-known and can be adjusted to produce very clean local >>>>> oscillators. If somebody tried to sell me a block of IP with an >>>>> "NCO" built some other way I'd be asking a lot of questions. >>>> >>>> I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >>>> nicely and are therefore very fast, they require no multipliers [1], >>>> they generate quadrature outputs for free, they can perform frequency >>>> translations for free (again no multipliers), and they are simple prove >>>> numerical accuracy. >>> >>> CORDICs are fine when and where they make sense, but they are often >>> not the best tradeoff. If you have no memory, no multipliers, or >>> gates are way cheaper than memory, and if the latency is tolerable, >>> then a CORDIC may be a good option. >>> >>>> [1] Maybe not a huge issue these days. The LUT-based NCOs requires two >>>> multipliers to combine the coarse and fine LUTs (four multipliers if you >>>> need a complex NCO output) and perhaps another four multipliers if you >>>> need to do a frequency translation. >>> >>> Many applications don't need separate LUTs to get the required >>> performance, and even then, or even in the case of complex output, it >>> can be done without multipliers. >> >> Care to elaborate on this? I'm not at all clear on how you make a LUT >> based NCO without LUTs and unless you are using a very coarse >> approximation, without multipliers. > > Not sure what you're asking. You a need a LUT, but just one in many > cases. Having a dual-ported single LUT is easy in an FPGA and > usually in silicon as well. > > What makes a multiplier necessary? I've never found the need, but my > apps are limited to comm. Maybe we aren't on the same page. The multiplier is there for the fine adjustment. If you are happy with some -60 or -80 dB spurs one LUT is fine. But if you want better performance the single LUT approach requires *very* large tables. -- Rick From newsfish@newsfish Thu Aug 1 00:32:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 20:10:59 -0500 Organization: A noiseless patient Spider Lines: 82 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Dec 2014 01:10:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="93a28beffd6034b7478094f1f552d895"; logging-data="23049"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ZYdk01zJTgr76etvfwAYh" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:Jc4/Cbjss34eIRHEX797R2eo9Sg= Xref: news.eternal-september.org comp.dsp:26017 comp.lang.vhdl:3486 this did not seem to get posted so i am reposting. sorry for any repeated post. On 12/22/14 5:17 PM, Rob Doyle wrote: > On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >> wrote: >> >>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>> I want to analyze the output of a DDS circuit and am wondering if >>>>>> an FFT >>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>> spurs that are often generated by a DDS. >>>>> >>>>> i still get the concepts of DDS and NCO mixed up. what are the >>>>> differences? >>>> >>>> One is spelled DDS and the other is spelled NCO. >>> >>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>> can it be algorithmic? like >>> >>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>> >>> where omega_0 is the normalized angular frequency of the sinusoid and >>> with appropriate initial states, y[-1] and y[-2] to result in the >>> amplitude and initial phase desired. >>> >>> is that an NCO that can be used in this DDS? or must it be LUT? >> >> Generally NCO or DDS refers to a phase accumulator with a LUT, since >> it is easily implemented in hardware. That's a general architecture >> that is well-known and can be adjusted to produce very clean local >> oscillators. If somebody tried to sell me a block of IP with an >> "NCO" built some other way I'd be asking a lot of questions. > > I have built NCOs using CORDIC rotators. No lookup tables. They pipeline > nicely and are therefore very fast, they require no multipliers [1], ??? i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here a while back), but i always thought that CORDIC did essentially x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] or, as complex numbers: (x[n] + j*y[n]) = exp(j*2*pi*f0/Fs) * (x[n-1] + j*y[n-1]) doesn't that require a few multiplications? > they generate quadrature outputs for free, they can perform frequency > translations for free (again no multipliers), and they are simple prove > numerical accuracy. > > [1] Maybe not a huge issue these days. The LUT-based NCOs requires two > multipliers to combine the coarse and fine LUTs even for linear interpolation? i think one multiplier is enough. the higher order the interpolation, the more multipliers needed (and the fewer points int he LUT are needed). > (four multipliers if you need a complex NCO output) and perhaps another > four multipliers if you need to do a frequency translation. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Thu Aug 1 00:32:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 21:02:48 -0700 Organization: Aioe.org NNTP Server Lines: 149 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> NNTP-Posting-Host: 670CkSRN2ntYFEZN8nXcjg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.dsp:26020 comp.lang.vhdl:3487 On 12/23/2014 6:10 PM, robert bristow-johnson wrote: > > this did not seem to get posted so i am reposting. sorry for any > repeated post. > > On 12/22/14 5:17 PM, Rob Doyle wrote: >> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>> wrote: >>> >>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>> wrote: >>>>> >>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>> mainly concerned with the "close > in" >>>>>>> spurs that are often generated by a DDS. >>>>>> >>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>> the differences? >>>>> >>>>> One is spelled DDS and the other is spelled NCO. >>>> >>>> is the NCO the typical table-lookup kind (with phase >>>> accumulator)? or can it be algorithmic? like >>>> >>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>> >>>> where omega_0 is the normalized angular frequency of the >>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>> to result in the amplitude and initial phase desired. >>>> >>>> is that an NCO that can be used in this DDS? or must it be >>>> LUT? >>> >>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>> since it is easily implemented in hardware. That's a general >>> architecture that is well-known and can be adjusted to produce >>> very clean local oscillators. If somebody tried to sell me a >>> block of IP with an "NCO" built some other way I'd be asking a >>> lot of questions. >> >> I have built NCOs using CORDIC rotators. No lookup tables. They >> pipeline nicely and are therefore very fast, they require no >> multipliers [1], > > ??? > > i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here > a while back), but i always thought that CORDIC did essentially > > x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] > y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] Yes. So far. So good. These are my notes if anyone is interested... [snip] Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase accumulator for an NCO application. Factor out the cos(theta): x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} At this point you might be thinking "Holy crap. That's one heck of a constraint!" Yeh... but keep reading anyway. You can drop the cos(theta) common term. It's just a gain term that rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. x[n] = x[n-1] - y[n-1] / 2**i y[n] = y[n-1] + x[n-1] / 2**i or (assuming twos complement math) - simply: x[n] = x[n-1] - y[n-1] >> i y[n] = y[n-1] + x[n-1] >> i where >> is a shift right operation [1] As this point it seems as if an *extreme* limitation has been placed on the selection of rotation angles. The equation above only describes how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of the following angles: atan(1) (45.000000000000000000000000000000 degrees) atan(1/2) (26.565051177077989351572193720453 degrees) atan(1/4) (14.036243467926478582892320159163 degrees) atan(1/8) (7.1250163489017975619533008412068 degrees) atan(1/16) (3.5763343749973510306847789144588 degrees) atan(1/32) (1.7899106082460693071502497760791 degrees) ...and so forth. The equation above does not describe how to rotate an input signal an arbitrary angle! Although this is true; all is not lost. Notice that in general that theta/2 < tan(theta). This truth allows the CORDIC to be used iteratively to rotate any input to any angle with any precision. IMO this is the genius of the CORDIC. I probably should have mentioned that you swap the rotation direction by flipping the additions and subtractions. The term z[n] is introduced to accumulate the angle as the CORDIC iterates. The term d[n] swaps the direction of rotation. Finally the familiar recursive CORDIC equation can be written as follows: x[n] = x[n-1] - d[n] y[n-1] >> i y[n] = y[n-1] + d[n] x[n-1] >> i z[n] = z[n-1] - d[n] tan(1/2**i) where: d[n] is +1 for z[n-1] < theta. Clockwise rotation next. d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. No multiplies here. The CORDIC simply does a successive approximation to the angle - rotating the angle clockwise or counter-clockwise by these limited selection of angles as necessary to converge on the desired angle. Each time the iteration occurs, the angle error is reduced by at least half. > doesn't that require a few multiplications? Nope. Just adds/subtracts - the sign of the angle error determines which direction to rotate on the next iteration. If this is pipelined, the shifts aren't real - they just select which bits of the previous iteration are used on the next iteration. The tan(1/2**i) term is a constant for each iteration. As an implementation detail, it saves hardware if you iterate from the angle toward zero instead of from zero toward the angle. If you do that, the sign of z[i] is the direction of rotation. It saves a magnitude compare for each iteration. Rob. From newsfish@newsfish Thu Aug 1 00:32:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 23:40:20 -0500 Organization: A noiseless patient Spider Lines: 161 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Dec 2014 04:40:11 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="18606"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18F882VOE0cNwur0H8ewn5r" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:DspwKTN75TEhFIQ8scai6tO9x3k= Xref: news.eternal-september.org comp.dsp:26021 comp.lang.vhdl:3488 On 12/23/2014 11:02 PM, Rob Doyle wrote: > On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >> >> this did not seem to get posted so i am reposting. sorry for any >> repeated post. >> >> On 12/22/14 5:17 PM, Rob Doyle wrote: >>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>>> mainly concerned with the "close >> in" >>>>>>>> spurs that are often generated by a DDS. >>>>>>> >>>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>>> the differences? >>>>>> >>>>>> One is spelled DDS and the other is spelled NCO. >>>>> >>>>> is the NCO the typical table-lookup kind (with phase >>>>> accumulator)? or can it be algorithmic? like >>>>> >>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>> >>>>> where omega_0 is the normalized angular frequency of the >>>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>>> to result in the amplitude and initial phase desired. >>>>> >>>>> is that an NCO that can be used in this DDS? or must it be >>>>> LUT? >>>> >>>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>>> since it is easily implemented in hardware. That's a general >>>> architecture that is well-known and can be adjusted to produce >>>> very clean local oscillators. If somebody tried to sell me a >>>> block of IP with an "NCO" built some other way I'd be asking a >>>> lot of questions. >>> >>> I have built NCOs using CORDIC rotators. No lookup tables. They >>> pipeline nicely and are therefore very fast, they require no >>> multipliers [1], >> >> ??? >> >> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >> a while back), but i always thought that CORDIC did essentially >> >> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] > > Yes. So far. So good. These are my notes if anyone is interested... > > [snip] > > Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase > accumulator for an NCO application. > > Factor out the cos(theta): > > x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} > y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} > > If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: > > x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} > y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} > > At this point you might be thinking "Holy crap. That's one heck of a > constraint!" Yeh... but keep reading anyway. > > You can drop the cos(theta) common term. It's just a gain term that > rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. > > x[n] = x[n-1] - y[n-1] / 2**i > y[n] = y[n-1] + x[n-1] / 2**i > > or (assuming twos complement math) - simply: > > x[n] = x[n-1] - y[n-1] >> i > y[n] = y[n-1] + x[n-1] >> i > > where >> is a shift right operation > > [1] As this point it seems as if an *extreme* limitation has been placed > on the selection of rotation angles. The equation above only describes > how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of > the following angles: > > atan(1) (45.000000000000000000000000000000 degrees) > atan(1/2) (26.565051177077989351572193720453 degrees) > atan(1/4) (14.036243467926478582892320159163 degrees) > atan(1/8) (7.1250163489017975619533008412068 degrees) > atan(1/16) (3.5763343749973510306847789144588 degrees) > atan(1/32) (1.7899106082460693071502497760791 degrees) > > ...and so forth. > > The equation above does not describe how to rotate an input signal an > arbitrary angle! Although this is true; all is not lost. > > Notice that in general that theta/2 < tan(theta). > > This truth allows the CORDIC to be used iteratively to rotate any input > to any angle with any precision. IMO this is the genius of the CORDIC. > > I probably should have mentioned that you swap the rotation direction by > flipping the additions and subtractions. > > The term z[n] is introduced to accumulate the angle as the CORDIC > iterates. The term d[n] swaps the direction of rotation. Finally the > familiar recursive CORDIC equation can be written as follows: > > x[n] = x[n-1] - d[n] y[n-1] >> i > y[n] = y[n-1] + d[n] x[n-1] >> i > z[n] = z[n-1] - d[n] tan(1/2**i) > > where: > > d[n] is +1 for z[n-1] < theta. Clockwise rotation next. > d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. > > No multiplies here. But this is the same as a multiply in terns of complexity, no? One large difference is that a multiply can be supported in commonly available hardware while this algorithm requires dedicated hardware or iterative software. > The CORDIC simply does a successive approximation to the angle - > rotating the angle clockwise or counter-clockwise by these limited > selection of angles as necessary to converge on the desired angle. Each > time the iteration occurs, the angle error is reduced by at least half. > >> doesn't that require a few multiplications? > > Nope. Just adds/subtracts - the sign of the angle error determines which > direction to rotate on the next iteration. If this is pipelined, the > shifts aren't real - they just select which bits of the previous > iteration are used on the next iteration. The tan(1/2**i) term is a > constant for each iteration. > > As an implementation detail, it saves hardware if you iterate from > the angle toward zero instead of from zero toward the angle. If you do > that, the sign of z[i] is the direction of rotation. It saves a > magnitude compare for each iteration. > > Rob. -- Rick From newsfish@newsfish Thu Aug 1 00:32:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 01:24:42 -0700 Organization: Aioe.org NNTP Server Lines: 181 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> NNTP-Posting-Host: 670CkSRN2ntYFEZN8nXcjg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.dsp:26022 comp.lang.vhdl:3489 On 12/23/2014 9:40 PM, rickman wrote: > On 12/23/2014 11:02 PM, Rob Doyle wrote: >> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>> >>> this did not seem to get posted so i am reposting. sorry for any >>> repeated post. >>> >>> On 12/22/14 5:17 PM, Rob Doyle wrote: >>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>> wrote: >>>>> >>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>> wrote: >>>>>>> >>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>>>> mainly concerned with the "close >>> in" >>>>>>>>> spurs that are often generated by a DDS. >>>>>>>> >>>>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>>>> the differences? >>>>>>> >>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>> >>>>>> is the NCO the typical table-lookup kind (with phase >>>>>> accumulator)? or can it be algorithmic? like >>>>>> >>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>> >>>>>> where omega_0 is the normalized angular frequency of the >>>>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>>>> to result in the amplitude and initial phase desired. >>>>>> >>>>>> is that an NCO that can be used in this DDS? or must it be >>>>>> LUT? >>>>> >>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>>>> since it is easily implemented in hardware. That's a general >>>>> architecture that is well-known and can be adjusted to produce >>>>> very clean local oscillators. If somebody tried to sell me a >>>>> block of IP with an "NCO" built some other way I'd be asking a >>>>> lot of questions. >>>> >>>> I have built NCOs using CORDIC rotators. No lookup tables. They >>>> pipeline nicely and are therefore very fast, they require no >>>> multipliers [1], >>> >>> ??? >>> >>> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >>> a while back), but i always thought that CORDIC did essentially >>> >>> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >>> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] >> >> Yes. So far. So good. These are my notes if anyone is interested... >> >> [snip] >> >> Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase >> accumulator for an NCO application. >> >> Factor out the cos(theta): >> >> x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} >> y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} >> >> If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: >> >> x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} >> y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} >> >> At this point you might be thinking "Holy crap. That's one heck of a >> constraint!" Yeh... but keep reading anyway. >> >> You can drop the cos(theta) common term. It's just a gain term that >> rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. >> >> x[n] = x[n-1] - y[n-1] / 2**i >> y[n] = y[n-1] + x[n-1] / 2**i >> >> or (assuming twos complement math) - simply: >> >> x[n] = x[n-1] - y[n-1] >> i >> y[n] = y[n-1] + x[n-1] >> i >> >> where >> is a shift right operation >> >> [1] As this point it seems as if an *extreme* limitation has been placed >> on the selection of rotation angles. The equation above only describes >> how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of >> the following angles: >> >> atan(1) (45.000000000000000000000000000000 degrees) >> atan(1/2) (26.565051177077989351572193720453 degrees) >> atan(1/4) (14.036243467926478582892320159163 degrees) >> atan(1/8) (7.1250163489017975619533008412068 degrees) >> atan(1/16) (3.5763343749973510306847789144588 degrees) >> atan(1/32) (1.7899106082460693071502497760791 degrees) >> >> ...and so forth. >> >> The equation above does not describe how to rotate an input signal an >> arbitrary angle! Although this is true; all is not lost. >> >> Notice that in general that theta/2 < tan(theta). >> >> This truth allows the CORDIC to be used iteratively to rotate any input >> to any angle with any precision. IMO this is the genius of the CORDIC. >> >> I probably should have mentioned that you swap the rotation direction by >> flipping the additions and subtractions. >> >> The term z[n] is introduced to accumulate the angle as the CORDIC >> iterates. The term d[n] swaps the direction of rotation. Finally the >> familiar recursive CORDIC equation can be written as follows: >> >> x[n] = x[n-1] - d[n] y[n-1] >> i >> y[n] = y[n-1] + d[n] x[n-1] >> i >> z[n] = z[n-1] - d[n] tan(1/2**i) >> >> where: >> >> d[n] is +1 for z[n-1] < theta. Clockwise rotation next. >> d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. >> >> No multiplies here. > > But this is the same as a multiply in terns of complexity, no? One > large difference is that a multiply can be supported in commonly > available hardware while this algorithm requires dedicated hardware or > iterative software. I agree that the CORDIC has the same complexity as a multiply. I agree that table-based algorithms using multipliers use less FPGA fabric. I was simply pointing out that there might be places where a CORDIC has advantages over LUT-based NCOs. Especially if have ROM or multiplier limitations. I also wanted to point out that if you need to do a 20-bit (using your 120dB example) complex downconversion for example, the CORDIC still requires zero multipliers. If you want to do a 20-bit complex downconversion using a table-based NCO followed by a complex mixer, you might need a *lot* of multipliers. If you only have an 18-bit multiplier, each multiplication requires (maybe up to) 4 multiplier blocks and you need 8 multiplications. I also /suspect/ that for any given device technology the CORDIC will execute at higher speeds. Thats all... >> The CORDIC simply does a successive approximation to the angle - >> rotating the angle clockwise or counter-clockwise by these limited >> selection of angles as necessary to converge on the desired angle. Each >> time the iteration occurs, the angle error is reduced by at least half. >> >>> doesn't that require a few multiplications? >> >> Nope. Just adds/subtracts - the sign of the angle error determines which >> direction to rotate on the next iteration. If this is pipelined, the >> shifts aren't real - they just select which bits of the previous >> iteration are used on the next iteration. The tan(1/2**i) term is a >> constant for each iteration. >> >> As an implementation detail, it saves hardware if you iterate from >> the angle toward zero instead of from zero toward the angle. If you do >> that, the sign of z[i] is the direction of rotation. It saves a >> magnitude compare for each iteration. >> >> Rob. > > From newsfish@newsfish Thu Aug 1 00:32:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 04:13:38 -0500 Organization: A noiseless patient Spider Lines: 175 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Dec 2014 09:13:27 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="30468"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1821V7BIu20tFweYqCoMej8" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:P/as2fG1fn9eokc/e1/6HTAhnUc= Xref: news.eternal-september.org comp.dsp:26023 comp.lang.vhdl:3490 On 12/24/2014 3:24 AM, Rob Doyle wrote: > On 12/23/2014 9:40 PM, rickman wrote: >> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>> >>>> this did not seem to get posted so i am reposting. sorry for any >>>> repeated post. >>>> >>>> On 12/22/14 5:17 PM, Rob Doyle wrote: >>>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>>> wrote: >>>>>>>> >>>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>>>>> mainly concerned with the "close >>>> in" >>>>>>>>>> spurs that are often generated by a DDS. >>>>>>>>> >>>>>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>>>>> the differences? >>>>>>>> >>>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>>> >>>>>>> is the NCO the typical table-lookup kind (with phase >>>>>>> accumulator)? or can it be algorithmic? like >>>>>>> >>>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>>> >>>>>>> where omega_0 is the normalized angular frequency of the >>>>>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>>>>> to result in the amplitude and initial phase desired. >>>>>>> >>>>>>> is that an NCO that can be used in this DDS? or must it be >>>>>>> LUT? >>>>>> >>>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>>>>> since it is easily implemented in hardware. That's a general >>>>>> architecture that is well-known and can be adjusted to produce >>>>>> very clean local oscillators. If somebody tried to sell me a >>>>>> block of IP with an "NCO" built some other way I'd be asking a >>>>>> lot of questions. >>>>> >>>>> I have built NCOs using CORDIC rotators. No lookup tables. They >>>>> pipeline nicely and are therefore very fast, they require no >>>>> multipliers [1], >>>> >>>> ??? >>>> >>>> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >>>> a while back), but i always thought that CORDIC did essentially >>>> >>>> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >>>> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] >>> >>> Yes. So far. So good. These are my notes if anyone is interested... >>> >>> [snip] >>> >>> Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase >>> accumulator for an NCO application. >>> >>> Factor out the cos(theta): >>> >>> x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} >>> y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} >>> >>> If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: >>> >>> x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} >>> y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} >>> >>> At this point you might be thinking "Holy crap. That's one heck of a >>> constraint!" Yeh... but keep reading anyway. >>> >>> You can drop the cos(theta) common term. It's just a gain term that >>> rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. >>> >>> x[n] = x[n-1] - y[n-1] / 2**i >>> y[n] = y[n-1] + x[n-1] / 2**i >>> >>> or (assuming twos complement math) - simply: >>> >>> x[n] = x[n-1] - y[n-1] >> i >>> y[n] = y[n-1] + x[n-1] >> i >>> >>> where >> is a shift right operation >>> >>> [1] As this point it seems as if an *extreme* limitation has been placed >>> on the selection of rotation angles. The equation above only describes >>> how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of >>> the following angles: >>> >>> atan(1) (45.000000000000000000000000000000 degrees) >>> atan(1/2) (26.565051177077989351572193720453 degrees) >>> atan(1/4) (14.036243467926478582892320159163 degrees) >>> atan(1/8) (7.1250163489017975619533008412068 degrees) >>> atan(1/16) (3.5763343749973510306847789144588 degrees) >>> atan(1/32) (1.7899106082460693071502497760791 degrees) >>> >>> ...and so forth. >>> >>> The equation above does not describe how to rotate an input signal an >>> arbitrary angle! Although this is true; all is not lost. >>> >>> Notice that in general that theta/2 < tan(theta). >>> >>> This truth allows the CORDIC to be used iteratively to rotate any input >>> to any angle with any precision. IMO this is the genius of the CORDIC. >>> >>> I probably should have mentioned that you swap the rotation direction by >>> flipping the additions and subtractions. >>> >>> The term z[n] is introduced to accumulate the angle as the CORDIC >>> iterates. The term d[n] swaps the direction of rotation. Finally the >>> familiar recursive CORDIC equation can be written as follows: >>> >>> x[n] = x[n-1] - d[n] y[n-1] >> i >>> y[n] = y[n-1] + d[n] x[n-1] >> i >>> z[n] = z[n-1] - d[n] tan(1/2**i) >>> >>> where: >>> >>> d[n] is +1 for z[n-1] < theta. Clockwise rotation next. >>> d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. >>> >>> No multiplies here. >> >> But this is the same as a multiply in terns of complexity, no? One >> large difference is that a multiply can be supported in commonly >> available hardware while this algorithm requires dedicated hardware or >> iterative software. > > I agree that the CORDIC has the same complexity as a multiply. I agree > that table-based algorithms using multipliers use less FPGA fabric. > > I was simply pointing out that there might be places where a CORDIC has > advantages over LUT-based NCOs. > > Especially if have ROM or multiplier limitations. > > I also wanted to point out that if you need to do a 20-bit (using your > 120dB example) complex downconversion for example, the CORDIC still > requires zero multipliers. > > If you want to do a 20-bit complex downconversion using a table-based > NCO followed by a complex mixer, you might need a *lot* of multipliers. > If you only have an 18-bit multiplier, each multiplication requires > (maybe up to) 4 multiplier blocks and you need 8 multiplications. > > I also /suspect/ that for any given device technology the CORDIC will > execute at higher speeds. > > Thats all... I understand, but the distinction between a multiplier and a CORDIC implementation is pretty pointless these days. If you have the space to implement a CORDIC wouldn't you have the space to implement an iterative multiply? I did a linear interpolation just because I could do the multiply iteratively while the previous sample was shifted out to the CODEC. One adder is the same as the CORDIC, no? I guess the difference is you only need one CORDIC while for a sine that is not an approximation you need two multipliers. I don't see how one would be faster than the other except for the case of a dedicated multiplier being much faster. -- Rick From newsfish@newsfish Thu Aug 1 00:32:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 15:19:50 -0500 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Dec 2014 20:19:28 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="72f16bed1b42f4f6b518c584e62de743"; logging-data="385"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX182oeis4qAwZOois8r+OuGa" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:ZataK4YgyypZSkH5p5V4+5noYzE= Xref: news.eternal-september.org comp.dsp:26030 comp.lang.vhdl:3491 On 12/24/14 4:13 AM, rickman wrote: > On 12/24/2014 3:24 AM, Rob Doyle wrote: >> On 12/23/2014 9:40 PM, rickman wrote: >>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>> >>>>> ..... (a whole bunch of stuff) > so, Rick, did that built-in notch filter make any sense to you? it's so cheap in software that i would think it would be cheap in VHDL or whatever your hardware language is. and i would just do LUT with linear interpolation. extend the table by one point so that LUT[N] = LUT[0] and you won't have to worry about an additional wrap-around in the linear interpolation. linear interpolation has a sinc^2 frequency response, so it puts zeros smack into the middle of images which reduces their amplitude a lot if the content frequency is much less than the sample rate. if your LUT length is decently long (like 512 or 1K or more), you'll do pretty good regarding the "purity" of your sinusoid. and with a perfectly tuned notch filter with, say, a 1/3 octave BW, you'll know exactly what your impurities are in either time domain or frequency domain (if you FFT it). -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Thu Aug 1 00:32:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 16:43:57 -0500 Organization: A noiseless patient Spider Lines: 45 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Wed, 24 Dec 2014 21:43:44 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="17858"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18J+YcO/+5rlRpo2OPWva4E" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:KpXrkxSTr6aH3dMfYljKfLvQRXc= Xref: news.eternal-september.org comp.dsp:26032 comp.lang.vhdl:3492 On 12/24/2014 3:19 PM, robert bristow-johnson wrote: > On 12/24/14 4:13 AM, rickman wrote: >> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>> On 12/23/2014 9:40 PM, rickman wrote: >>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>> >>>>>> ..... (a whole bunch of stuff) >> > > so, Rick, did that built-in notch filter make any sense to you? it's so > cheap in software that i would think it would be cheap in VHDL or > whatever your hardware language is. > > and i would just do LUT with linear interpolation. extend the table by > one point so that LUT[N] = LUT[0] and you won't have to worry about an > additional wrap-around in the linear interpolation. linear > interpolation has a sinc^2 frequency response, so it puts zeros smack > into the middle of images which reduces their amplitude a lot if the > content frequency is much less than the sample rate. if your LUT length > is decently long (like 512 or 1K or more), you'll do pretty good > regarding the "purity" of your sinusoid. > > and with a perfectly tuned notch filter with, say, a 1/3 octave BW, > you'll know exactly what your impurities are in either time domain or > frequency domain (if you FFT it). I thought I replied about the notch filter. I"m not clear on what it buys me. If I FFT the data without the filter I get the same spectrum with the signal present which does not interfere with the spectrum. So what is the point? None of the analysis stuff will be implemented in hardware, so that is not an issue. BTW, in a sine table for linear interpolation, I don't use sine(0) as the value in LUT(0). I give the points a half step phase offset with the linear interp signed. I also offset the values to minimize the error over the step range which will be interpolated. BTW, LUT(N) won't equal LUT(0). Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. In my table each of the values are non-zero and not 1 although if the table is large enough, the value of LUT(N-1) is also 1. Having a table of 2^N+1 entries is a PITA in hardware. -- Rick From newsfish@newsfish Thu Aug 1 00:32:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 18:56:41 -0500 Organization: A noiseless patient Spider Lines: 76 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Wed, 24 Dec 2014 23:56:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="b1de198917c3b7d2f6897de3aaab5522"; logging-data="11560"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18CD1IerjYwWJqne/DaezVf" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:R8Ec5PbsJX63G81RKzFVywfkmpA= Xref: news.eternal-september.org comp.dsp:26033 comp.lang.vhdl:3493 On 12/24/14 4:43 PM, rickman wrote: > On 12/24/2014 3:19 PM, robert bristow-johnson wrote: >> On 12/24/14 4:13 AM, rickman wrote: >>> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>>> On 12/23/2014 9:40 PM, rickman wrote: >>>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>>> >>>>>>> ..... (a whole bunch of stuff) >>> >> ... >> >> and with a perfectly tuned notch filter with, say, a 1/3 octave BW, >> you'll know exactly what your impurities are in either time domain or >> frequency domain (if you FFT it). > > I thought I replied about the notch filter. I"m not clear on what it > buys me. If I FFT the data without the filter I get the same spectrum > with the signal present which does not interfere with the spectrum. do you know exactly what to subtract from the FFT to get whatever your residual nasty stuff is? is that bump a sidelobe of your windowed sinusoid or is it part of the "impurity" that you're measuring? > So > what is the point? None of the analysis stuff will be implemented in > hardware, so that is not an issue. > > BTW, in a sine table for linear interpolation, I don't use sine(0) as > the value in LUT(0). i don't think that matters. > I give the points a half step phase offset with the > linear interp signed. nor that. > I also offset the values to minimize the error > over the step range which will be interpolated. so it's kinda an optimal phase offset that gets your quantized sine values the least error (however the total error is defined). > BTW, LUT(N) won't equal LUT(0). it's N+1 points instead of N. so it's the same N points you would have had anyway, with one more added. > Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. okay. i guess i'm looking at resources more like a software guy would. if i were coding this for a DSP chip or something, i would just quadruple the number of entries and have a single cycle of the waveform, whatever it is. > In my table each of the values are non-zero and not 1 although if > the table is large enough, the value of LUT(N-1) is also 1. Having a > table of 2^N+1 entries is a PITA in hardware. i understand. ((2*pi)/N)/2 radians offset so the points are the same symmetry for each quadrant. and then it's sign manipulation that the hardware folk don't mind fiddling with. but you still know the frequency in advance and a notch filter can be tuned to that frequency. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Thu Aug 1 00:32:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 19:48:22 -0500 Organization: A noiseless patient Spider Lines: 91 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 25 Dec 2014 00:48:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21641"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/QbRjf6u47Bdizo9m7oCxa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:MN1cx0prhuArNe+uz/SAIjHYcq0= Xref: news.eternal-september.org comp.dsp:26034 comp.lang.vhdl:3494 On 12/24/2014 6:56 PM, robert bristow-johnson wrote: > On 12/24/14 4:43 PM, rickman wrote: >> On 12/24/2014 3:19 PM, robert bristow-johnson wrote: >>> On 12/24/14 4:13 AM, rickman wrote: >>>> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>>>> On 12/23/2014 9:40 PM, rickman wrote: >>>>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>>>> >>>>>>>> ..... (a whole bunch of stuff) >>>> >>> > ... >>> >>> and with a perfectly tuned notch filter with, say, a 1/3 octave BW, >>> you'll know exactly what your impurities are in either time domain or >>> frequency domain (if you FFT it). >> >> I thought I replied about the notch filter. I"m not clear on what it >> buys me. If I FFT the data without the filter I get the same spectrum >> with the signal present which does not interfere with the spectrum. > > do you know exactly what to subtract from the FFT to get whatever your > residual nasty stuff is? is that bump a sidelobe of your windowed > sinusoid or is it part of the "impurity" that you're measuring? I believe you are making this too complex. The measurement is a one time thing. I can use as large a transform as I am willing to wait for and therefore minimize the sidelobes. The measurement should be good enough that if I can't measure it, I won't really care about it. Check out these plots... https://sites.google.com/site/fpgastuff/dds_oddities.pdf The last page has some interesting data. >> So >> what is the point? None of the analysis stuff will be implemented in >> hardware, so that is not an issue. >> >> BTW, in a sine table for linear interpolation, I don't use sine(0) as >> the value in LUT(0). > > i don't think that matters. > >> I give the points a half step phase offset with the >> linear interp signed. > > nor that. > >> I also offset the values to minimize the error >> over the step range which will be interpolated. > > so it's kinda an optimal phase offset that gets your quantized sine > values the least error (however the total error is defined). > >> BTW, LUT(N) won't equal LUT(0). > > it's N+1 points instead of N. so it's the same N points you would have > had anyway, with one more added. > >> Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. > > okay. i guess i'm looking at resources more like a software guy would. > if i were coding this for a DSP chip or something, i would just > quadruple the number of entries and have a single cycle of the waveform, > whatever it is. Even in software that can get expensive. The LUT is O(2^N) in size so you don't want N to get too large. *Much* better to use your N for storing useful data rather than duplicate info. >> In my table each of the values are non-zero and not 1 although if >> the table is large enough, the value of LUT(N-1) is also 1. Having a >> table of 2^N+1 entries is a PITA in hardware. > > i understand. ((2*pi)/N)/2 radians offset so the points are the same > symmetry for each quadrant. and then it's sign manipulation that the > hardware folk don't mind fiddling with. > > but you still know the frequency in advance and a notch filter can be > tuned to that frequency. If there is a purpose to it. -- Rick From newsfish@newsfish Thu Aug 1 00:32:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 19:50:26 -0500 Organization: A noiseless patient Spider Lines: 98 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 25 Dec 2014 00:50:13 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21641"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Kj3ApprO2QhjL6EhWhlpN" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:wWXzFXhaVYDENtYU0lVsnV+JDpI= Xref: news.eternal-september.org comp.dsp:26035 comp.lang.vhdl:3495 On 12/24/2014 7:48 PM, rickman wrote: > On 12/24/2014 6:56 PM, robert bristow-johnson wrote: >> On 12/24/14 4:43 PM, rickman wrote: >>> On 12/24/2014 3:19 PM, robert bristow-johnson wrote: >>>> On 12/24/14 4:13 AM, rickman wrote: >>>>> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>>>>> On 12/23/2014 9:40 PM, rickman wrote: >>>>>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>>>>> >>>>>>>>> ..... (a whole bunch of stuff) >>>>> >>>> >> ... >>>> >>>> and with a perfectly tuned notch filter with, say, a 1/3 octave BW, >>>> you'll know exactly what your impurities are in either time domain or >>>> frequency domain (if you FFT it). >>> >>> I thought I replied about the notch filter. I"m not clear on what it >>> buys me. If I FFT the data without the filter I get the same spectrum >>> with the signal present which does not interfere with the spectrum. >> >> do you know exactly what to subtract from the FFT to get whatever your >> residual nasty stuff is? is that bump a sidelobe of your windowed >> sinusoid or is it part of the "impurity" that you're measuring? > > I believe you are making this too complex. The measurement is a one > time thing. I can use as large a transform as I am willing to wait for > and therefore minimize the sidelobes. The measurement should be good > enough that if I can't measure it, I won't really care about it. > > Check out these plots... > > https://sites.google.com/site/fpgastuff/dds_oddities.pdf > > The last page has some interesting data. I hit send too quickly. I also meant to point out that the spurs of interest are the ones closer to the carrier. How well can I filter the carrier without filtering the side lobes? >>> So >>> what is the point? None of the analysis stuff will be implemented in >>> hardware, so that is not an issue. >>> >>> BTW, in a sine table for linear interpolation, I don't use sine(0) as >>> the value in LUT(0). >> >> i don't think that matters. >> >>> I give the points a half step phase offset with the >>> linear interp signed. >> >> nor that. >> >>> I also offset the values to minimize the error >>> over the step range which will be interpolated. >> >> so it's kinda an optimal phase offset that gets your quantized sine >> values the least error (however the total error is defined). >> >>> BTW, LUT(N) won't equal LUT(0). >> >> it's N+1 points instead of N. so it's the same N points you would have >> had anyway, with one more added. >> >>> Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. >> >> okay. i guess i'm looking at resources more like a software guy would. >> if i were coding this for a DSP chip or something, i would just >> quadruple the number of entries and have a single cycle of the waveform, >> whatever it is. > > Even in software that can get expensive. The LUT is O(2^N) in size so > you don't want N to get too large. *Much* better to use your N for > storing useful data rather than duplicate info. > > >>> In my table each of the values are non-zero and not 1 although if >>> the table is large enough, the value of LUT(N-1) is also 1. Having a >>> table of 2^N+1 entries is a PITA in hardware. >> >> i understand. ((2*pi)/N)/2 radians offset so the points are the same >> symmetry for each quadrant. and then it's sign manipulation that the >> hardware folk don't mind fiddling with. >> >> but you still know the frequency in advance and a notch filter can be >> tuned to that frequency. > > If there is a purpose to it. > -- Rick From newsfish@newsfish Thu Aug 1 00:32:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 10:41:28 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 65 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.dsp:26038 comp.lang.vhdl:3496 In comp.dsp Rob Doyle wrote: > On 12/23/2014 6:10 PM, robert bristow-johnson wrote: (snip) >> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >> a while back), but i always thought that CORDIC did essentially >> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] > Yes. So far. So good. These are my notes if anyone is interested... > [snip] > Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase > accumulator for an NCO application. > Factor out the cos(theta): > x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} > y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} > If you select tan(theta) from the set of 1/(2**i) > then [1] this becomes: Nice if you are doing it in binary, but many hand calculators do it in decimal. I believe I have seen the explanation once, but it is much harder to find than the binary version. This goes back to at least the beginning of HP hand calculators. > x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} > y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} > At this point you might be thinking "Holy crap. That's one heck of a > constraint!" Yeh... but keep reading anyway. > You can drop the cos(theta) common term. It's just a gain term that > rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. > x[n] = x[n-1] - y[n-1] / 2**i > y[n] = y[n-1] + x[n-1] / 2**i > or (assuming twos complement math) - simply: > x[n] = x[n-1] - y[n-1] >> i > y[n] = y[n-1] + x[n-1] >> i > where >> is a shift right operation > [1] As this point it seems as if an *extreme* limitation has been placed > on the selection of rotation angles. The equation above only describes > how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of > the following angles: > atan(1) (45.000000000000000000000000000000 degrees) > atan(1/2) (26.565051177077989351572193720453 degrees) > atan(1/4) (14.036243467926478582892320159163 degrees) > atan(1/8) (7.1250163489017975619533008412068 degrees) > atan(1/16) (3.5763343749973510306847789144588 degrees) > atan(1/32) (1.7899106082460693071502497760791 degrees) (snip) -- glen From newsfish@newsfish Thu Aug 1 00:32:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 15:52:36 GMT Organization: Anchor Hill Communications Lines: 86 Message-ID: <549c32a9.931041360@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="4131"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19JUCXvqegKro0z4wjz806vlvYkJnMMvGI=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-0, 12/25/2014), Outbound message Cancel-Lock: sha1:rwBPf1kU6NIK9QE9QjgrxcMgCac= Xref: news.eternal-september.org comp.dsp:26039 comp.lang.vhdl:3497 On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >> >>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>> On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle >>>> wrote: >>>> >>>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>>> wrote: >>>>>>>> >>>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>>>>>> spurs that are often generated by a DDS. >>>>>>>>> >>>>>>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>>>>>> >>>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>>> >>>>>>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>>>>>> can it be algorithmic? like >>>>>>> >>>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>>> >>>>>>> where omega_0 is the normalized angular frequency of the sinusoid and >>>>>>> with appropriate initial states, y[-1] and y[-2] to result in the >>>>>>> amplitude and initial phase desired. >>>>>>> >>>>>>> is that an NCO that can be used in this DDS? or must it be LUT? >>>>>> >>>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, since >>>>>> it is easily implemented in hardware. That's a general architecture >>>>>> that is well-known and can be adjusted to produce very clean local >>>>>> oscillators. If somebody tried to sell me a block of IP with an >>>>>> "NCO" built some other way I'd be asking a lot of questions. >>>>> >>>>> I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >>>>> nicely and are therefore very fast, they require no multipliers [1], >>>>> they generate quadrature outputs for free, they can perform frequency >>>>> translations for free (again no multipliers), and they are simple prove >>>>> numerical accuracy. >>>> >>>> CORDICs are fine when and where they make sense, but they are often >>>> not the best tradeoff. If you have no memory, no multipliers, or >>>> gates are way cheaper than memory, and if the latency is tolerable, >>>> then a CORDIC may be a good option. >>>> >>>>> [1] Maybe not a huge issue these days. The LUT-based NCOs requires two >>>>> multipliers to combine the coarse and fine LUTs (four multipliers if you >>>>> need a complex NCO output) and perhaps another four multipliers if you >>>>> need to do a frequency translation. >>>> >>>> Many applications don't need separate LUTs to get the required >>>> performance, and even then, or even in the case of complex output, it >>>> can be done without multipliers. >>> >>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>> based NCO without LUTs and unless you are using a very coarse >>> approximation, without multipliers. >> >> Not sure what you're asking. You a need a LUT, but just one in many >> cases. Having a dual-ported single LUT is easy in an FPGA and >> usually in silicon as well. >> >> What makes a multiplier necessary? I've never found the need, but my >> apps are limited to comm. > >Maybe we aren't on the same page. The multiplier is there for the fine >adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >fine. But if you want better performance the single LUT approach >requires *very* large tables. There are a lot of tricks that can be used to keep the table size down. I've mentioned one already. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 15:55:24 GMT Organization: Anchor Hill Communications Lines: 199 Message-ID: <549c32f5.931117005@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="4131"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190mCWuptpvbRsy0aXutr6ti+bYUqXzdOs=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-0, 12/25/2014), Outbound message Cancel-Lock: sha1:daVWJ/sri8nhZ+dA/rh0VMoMOug= Xref: news.eternal-september.org comp.dsp:26040 comp.lang.vhdl:3498 On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle wrote: >On 12/23/2014 9:40 PM, rickman wrote: >> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>> >>>> this did not seem to get posted so i am reposting. sorry for any >>>> repeated post. >>>> >>>> On 12/22/14 5:17 PM, Rob Doyle wrote: >>>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>>> wrote: >>>>>>>> >>>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>>>>> mainly concerned with the "close >>>> in" >>>>>>>>>> spurs that are often generated by a DDS. >>>>>>>>> >>>>>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>>>>> the differences? >>>>>>>> >>>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>>> >>>>>>> is the NCO the typical table-lookup kind (with phase >>>>>>> accumulator)? or can it be algorithmic? like >>>>>>> >>>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>>> >>>>>>> where omega_0 is the normalized angular frequency of the >>>>>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>>>>> to result in the amplitude and initial phase desired. >>>>>>> >>>>>>> is that an NCO that can be used in this DDS? or must it be >>>>>>> LUT? >>>>>> >>>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>>>>> since it is easily implemented in hardware. That's a general >>>>>> architecture that is well-known and can be adjusted to produce >>>>>> very clean local oscillators. If somebody tried to sell me a >>>>>> block of IP with an "NCO" built some other way I'd be asking a >>>>>> lot of questions. >>>>> >>>>> I have built NCOs using CORDIC rotators. No lookup tables. They >>>>> pipeline nicely and are therefore very fast, they require no >>>>> multipliers [1], >>>> >>>> ??? >>>> >>>> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >>>> a while back), but i always thought that CORDIC did essentially >>>> >>>> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >>>> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] >>> >>> Yes. So far. So good. These are my notes if anyone is interested... >>> >>> [snip] >>> >>> Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase >>> accumulator for an NCO application. >>> >>> Factor out the cos(theta): >>> >>> x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} >>> y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} >>> >>> If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: >>> >>> x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} >>> y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} >>> >>> At this point you might be thinking "Holy crap. That's one heck of a >>> constraint!" Yeh... but keep reading anyway. >>> >>> You can drop the cos(theta) common term. It's just a gain term that >>> rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. >>> >>> x[n] = x[n-1] - y[n-1] / 2**i >>> y[n] = y[n-1] + x[n-1] / 2**i >>> >>> or (assuming twos complement math) - simply: >>> >>> x[n] = x[n-1] - y[n-1] >> i >>> y[n] = y[n-1] + x[n-1] >> i >>> >>> where >> is a shift right operation >>> >>> [1] As this point it seems as if an *extreme* limitation has been placed >>> on the selection of rotation angles. The equation above only describes >>> how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of >>> the following angles: >>> >>> atan(1) (45.000000000000000000000000000000 degrees) >>> atan(1/2) (26.565051177077989351572193720453 degrees) >>> atan(1/4) (14.036243467926478582892320159163 degrees) >>> atan(1/8) (7.1250163489017975619533008412068 degrees) >>> atan(1/16) (3.5763343749973510306847789144588 degrees) >>> atan(1/32) (1.7899106082460693071502497760791 degrees) >>> >>> ...and so forth. >>> >>> The equation above does not describe how to rotate an input signal an >>> arbitrary angle! Although this is true; all is not lost. >>> >>> Notice that in general that theta/2 < tan(theta). >>> >>> This truth allows the CORDIC to be used iteratively to rotate any input >>> to any angle with any precision. IMO this is the genius of the CORDIC. >>> >>> I probably should have mentioned that you swap the rotation direction by >>> flipping the additions and subtractions. >>> >>> The term z[n] is introduced to accumulate the angle as the CORDIC >>> iterates. The term d[n] swaps the direction of rotation. Finally the >>> familiar recursive CORDIC equation can be written as follows: >>> >>> x[n] = x[n-1] - d[n] y[n-1] >> i >>> y[n] = y[n-1] + d[n] x[n-1] >> i >>> z[n] = z[n-1] - d[n] tan(1/2**i) >>> >>> where: >>> >>> d[n] is +1 for z[n-1] < theta. Clockwise rotation next. >>> d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. >>> >>> No multiplies here. >> >> But this is the same as a multiply in terns of complexity, no? One >> large difference is that a multiply can be supported in commonly >> available hardware while this algorithm requires dedicated hardware or >> iterative software. > >I agree that the CORDIC has the same complexity as a multiply. I agree >that table-based algorithms using multipliers use less FPGA fabric. > >I was simply pointing out that there might be places where a CORDIC has >advantages over LUT-based NCOs. > >Especially if have ROM or multiplier limitations. > >I also wanted to point out that if you need to do a 20-bit (using your >120dB example) complex downconversion for example, the CORDIC still >requires zero multipliers. > >If you want to do a 20-bit complex downconversion using a table-based >NCO followed by a complex mixer, you might need a *lot* of multipliers. >If you only have an 18-bit multiplier, each multiplication requires >(maybe up to) 4 multiplier blocks and you need 8 multiplications. > >I also /suspect/ that for any given device technology the CORDIC will >execute at higher speeds. > >Thats all... That's been my experience; that if multipliers are scarce or too expensive, or memory is scarce or too expensive, then a CORDIC is a nice back-up option. These days multipliers and memory are both plentiful in most platforms, so CORDICs just aren't as useful as they used to be. The latency is sometimes an issue as well. There are still some places where they make sense, though. >>> The CORDIC simply does a successive approximation to the angle - >>> rotating the angle clockwise or counter-clockwise by these limited >>> selection of angles as necessary to converge on the desired angle. Each >>> time the iteration occurs, the angle error is reduced by at least half. >>> >>>> doesn't that require a few multiplications? >>> >>> Nope. Just adds/subtracts - the sign of the angle error determines which >>> direction to rotate on the next iteration. If this is pipelined, the >>> shifts aren't real - they just select which bits of the previous >>> iteration are used on the next iteration. The tan(1/2**i) term is a >>> constant for each iteration. >>> >>> As an implementation detail, it saves hardware if you iterate from >>> the angle toward zero instead of from zero toward the angle. If you do >>> that, the sign of z[i] is the direction of rotation. It saves a >>> magnitude compare for each iteration. >>> >>> Rob. >> >> > Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 16:03:54 GMT Organization: Anchor Hill Communications Lines: 95 Message-ID: <549c338c.931268482@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="7868"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/mIaCruTz3sORVPFa9lRaYd7p3u3mptWw=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-0, 12/25/2014), Outbound message Cancel-Lock: sha1:P6Gew+S8yRUFDrUvI6zQOwer59Y= Xref: news.eternal-september.org comp.dsp:26041 comp.lang.vhdl:3499 On Wed, 24 Dec 2014 18:56:41 -0500, robert bristow-johnson wrote: >On 12/24/14 4:43 PM, rickman wrote: >> On 12/24/2014 3:19 PM, robert bristow-johnson wrote: >>> On 12/24/14 4:13 AM, rickman wrote: >>>> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>>>> On 12/23/2014 9:40 PM, rickman wrote: >>>>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>>>> >>>>>>>> ..... (a whole bunch of stuff) >>>> >>> >... >>> >>> and with a perfectly tuned notch filter with, say, a 1/3 octave BW, >>> you'll know exactly what your impurities are in either time domain or >>> frequency domain (if you FFT it). >> >> I thought I replied about the notch filter. I"m not clear on what it >> buys me. If I FFT the data without the filter I get the same spectrum >> with the signal present which does not interfere with the spectrum. > >do you know exactly what to subtract from the FFT to get whatever your >residual nasty stuff is? is that bump a sidelobe of your windowed >sinusoid or is it part of the "impurity" that you're measuring? > >> So >> what is the point? None of the analysis stuff will be implemented in >> hardware, so that is not an issue. >> >> BTW, in a sine table for linear interpolation, I don't use sine(0) as >> the value in LUT(0). > >i don't think that matters. > >> I give the points a half step phase offset with the >> linear interp signed. > >nor that. Actually, not having a zero entries in the table for the zero crossings can help solve some common problems with artifacts like spurs (for oscillators) and jitter (for clock generators). The case for the clock output is easy to explain, since the MSB duty cycle is not symmetric when there are two zero entries. Just offsetting the phase a tiny bit, even to just one LSB present in the table output near the zero crossing, makes the MSB duty cycle 50% in the table. >> I also offset the values to minimize the error >> over the step range which will be interpolated. > >so it's kinda an optimal phase offset that gets your quantized sine >values the least error (however the total error is defined). > >> BTW, LUT(N) won't equal LUT(0). > >it's N+1 points instead of N. so it's the same N points you would have >had anyway, with one more added. Which means you just doubled the size of the memory. >> Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. > >okay. i guess i'm looking at resources more like a software guy would. > if i were coding this for a DSP chip or something, i would just >quadruple the number of entries and have a single cycle of the waveform, >whatever it is. A quarter cycle is all that's really needed. >> In my table each of the values are non-zero and not 1 although if >> the table is large enough, the value of LUT(N-1) is also 1. Having a >> table of 2^N+1 entries is a PITA in hardware. > >i understand. ((2*pi)/N)/2 radians offset so the points are the same >symmetry for each quadrant. and then it's sign manipulation that the >hardware folk don't mind fiddling with. > >but you still know the frequency in advance and a notch filter can be >tuned to that frequency. If there's only one frequency needed and it's known in advance, you may not need a DDS/NCO. Usually an NCO is used because it needs to vary a bit either for tracking or tuning or other adjustments. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 11:56:15 -0500 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 16:56:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="18965"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1//txFjuZhulgC6NjCXP50j" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c32a9.931041360@news.eternal-september.org> Cancel-Lock: sha1:HHsWOqKZ+J41Hb6+vg2LvtHqMkA= Xref: news.eternal-september.org comp.dsp:26044 comp.lang.vhdl:3500 On 12/25/2014 10:52 AM, Eric Jacobsen wrote: > On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: > >> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>> >>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>> >>>>> Many applications don't need separate LUTs to get the required >>>>> performance, and even then, or even in the case of complex output, it >>>>> can be done without multipliers. >>>> >>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>> based NCO without LUTs and unless you are using a very coarse >>>> approximation, without multipliers. >>> >>> Not sure what you're asking. You a need a LUT, but just one in many >>> cases. Having a dual-ported single LUT is easy in an FPGA and >>> usually in silicon as well. >>> >>> What makes a multiplier necessary? I've never found the need, but my >>> apps are limited to comm. >> >> Maybe we aren't on the same page. The multiplier is there for the fine >> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >> fine. But if you want better performance the single LUT approach >> requires *very* large tables. > > There are a lot of tricks that can be used to keep the table size > down. I've mentioned one already. And what was that? You have made some 20 or more posts in this thread, I don't feel like weeding through all of them to find this. Reading back through this thread it seems like your posts are intended to be mysterious rather than informative. Every one leaves enough unsaid that more questions are needed. -- Rick From newsfish@newsfish Thu Aug 1 00:32:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 12:02:57 -0500 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 17:02:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="20241"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ZRRLmOa10SL4+tI+FiJ1Y" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c32f5.931117005@news.eternal-september.org> Cancel-Lock: sha1:fsVGX/iCPD+mUCkWc5oOPIXSswU= Xref: news.eternal-september.org comp.dsp:26045 comp.lang.vhdl:3501 On 12/25/2014 10:55 AM, Eric Jacobsen wrote: > On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle > wrote: > >> I agree that the CORDIC has the same complexity as a multiply. I agree >> that table-based algorithms using multipliers use less FPGA fabric. >> >> I was simply pointing out that there might be places where a CORDIC has >> advantages over LUT-based NCOs. >> >> Especially if have ROM or multiplier limitations. >> >> I also wanted to point out that if you need to do a 20-bit (using your >> 120dB example) complex downconversion for example, the CORDIC still >> requires zero multipliers. >> >> If you want to do a 20-bit complex downconversion using a table-based >> NCO followed by a complex mixer, you might need a *lot* of multipliers. >> If you only have an 18-bit multiplier, each multiplication requires >> (maybe up to) 4 multiplier blocks and you need 8 multiplications. >> >> I also /suspect/ that for any given device technology the CORDIC will >> execute at higher speeds. >> >> Thats all... > > That's been my experience; that if multipliers are scarce or too > expensive, or memory is scarce or too expensive, then a CORDIC is a > nice back-up option. These days multipliers and memory are both > plentiful in most platforms, so CORDICs just aren't as useful as they > used to be. I think the distinction between a multiply and the CORDIC technique is bogus. CORDIC is an iterative process including all the operations that make up a multiply. The only difference is that in many cases there is hardware available that facilitates execution of generic multiplies while the CORDIC must be implemented in detail in every case. > The latency is sometimes an issue as well. > > There are still some places where they make sense, though. Care to explain? -- Rick From newsfish@newsfish Thu Aug 1 00:32:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 20:56:47 GMT Organization: Anchor Hill Communications Lines: 47 Message-ID: <549c79aa.949218051@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="4724"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/eSWyXSi9amODB2mcpd4YZttdMnQ3zPHE=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-1, 12/25/2014), Outbound message Cancel-Lock: sha1:m4VIPaWKBbbGrb3nnC2Ua4W0mPI= Xref: news.eternal-september.org comp.dsp:26048 comp.lang.vhdl:3502 On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >> >>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>> >>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>> >>>>>> Many applications don't need separate LUTs to get the required >>>>>> performance, and even then, or even in the case of complex output, it >>>>>> can be done without multipliers. >>>>> >>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>> based NCO without LUTs and unless you are using a very coarse >>>>> approximation, without multipliers. >>>> >>>> Not sure what you're asking. You a need a LUT, but just one in many >>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>> usually in silicon as well. >>>> >>>> What makes a multiplier necessary? I've never found the need, but my >>>> apps are limited to comm. >>> >>> Maybe we aren't on the same page. The multiplier is there for the fine >>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>> fine. But if you want better performance the single LUT approach >>> requires *very* large tables. >> >> There are a lot of tricks that can be used to keep the table size >> down. I've mentioned one already. > >And what was that? You have made some 20 or more posts in this thread, >I don't feel like weeding through all of them to find this. Reading >back through this thread it seems like your posts are intended to be >mysterious rather than informative. Every one leaves enough unsaid that >more questions are needed. I can't divulge trade secrets or proprietary information that doesn't belong to me. I can, however, hint in directions of benefit. Take it or leave it. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 21:01:22 GMT Organization: Anchor Hill Communications Lines: 66 Message-ID: <549c7a34.949356689@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="4724"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+xL7Evvl68wG2VReWB+HLbcTiXY25TGro=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-1, 12/25/2014), Outbound message Cancel-Lock: sha1:WYaaooCe/YOXdw/V5MOZzl5rURA= Xref: news.eternal-september.org comp.dsp:26049 comp.lang.vhdl:3503 On Thu, 25 Dec 2014 12:02:57 -0500, rickman wrote: >On 12/25/2014 10:55 AM, Eric Jacobsen wrote: >> On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle >> wrote: >> >>> I agree that the CORDIC has the same complexity as a multiply. I agree >>> that table-based algorithms using multipliers use less FPGA fabric. >>> >>> I was simply pointing out that there might be places where a CORDIC has >>> advantages over LUT-based NCOs. >>> >>> Especially if have ROM or multiplier limitations. >>> >>> I also wanted to point out that if you need to do a 20-bit (using your >>> 120dB example) complex downconversion for example, the CORDIC still >>> requires zero multipliers. >>> >>> If you want to do a 20-bit complex downconversion using a table-based >>> NCO followed by a complex mixer, you might need a *lot* of multipliers. >>> If you only have an 18-bit multiplier, each multiplication requires >>> (maybe up to) 4 multiplier blocks and you need 8 multiplications. >>> >>> I also /suspect/ that for any given device technology the CORDIC will >>> execute at higher speeds. >>> >>> Thats all... >> >> That's been my experience; that if multipliers are scarce or too >> expensive, or memory is scarce or too expensive, then a CORDIC is a >> nice back-up option. These days multipliers and memory are both >> plentiful in most platforms, so CORDICs just aren't as useful as they >> used to be. > >I think the distinction between a multiply and the CORDIC technique is >bogus. CORDIC is an iterative process including all the operations that >make up a multiply. The only difference is that in many cases there is >hardware available that facilitates execution of generic multiplies >while the CORDIC must be implemented in detail in every case. In the past (some of it long ago) when we did tradeoffs on using a CORDIC or an NCO, or a CORDIC or a complex mix implemented with multipliers, it comes down to resource availability. If multipliers are available (either in FPGA fabric or as a module in silicon), then a mixer is generally much more efficient with multipliers. If the memory is available, then a LUT with a phase accumulator is hard to beat for a numeric oscillator. The latency may also tilt the tradeoff further away from the CORDIC. They certainly have their place, but those places have gotten more limited as silicon resources get cheaper. > >> The latency is sometimes an issue as well. >> >> There are still some places where they make sense, though. > >Care to explain? > >-- > >Rick Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 16:08:45 -0500 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 21:08:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="6442"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX183pkh0RhB/DOGBIktewO2o" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c79aa.949218051@news.eternal-september.org> Cancel-Lock: sha1:Dgq4sOvRQm1CT+fNmnnm3WvILqw= Xref: news.eternal-september.org comp.dsp:26050 comp.lang.vhdl:3504 On 12/25/2014 3:56 PM, Eric Jacobsen wrote: > On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: > >> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>> >>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>> >>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>> >>>>>>> Many applications don't need separate LUTs to get the required >>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>> can be done without multipliers. >>>>>> >>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>> approximation, without multipliers. >>>>> >>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>> usually in silicon as well. >>>>> >>>>> What makes a multiplier necessary? I've never found the need, but my >>>>> apps are limited to comm. >>>> >>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>> fine. But if you want better performance the single LUT approach >>>> requires *very* large tables. >>> >>> There are a lot of tricks that can be used to keep the table size >>> down. I've mentioned one already. >> >> And what was that? You have made some 20 or more posts in this thread, >> I don't feel like weeding through all of them to find this. Reading >> back through this thread it seems like your posts are intended to be >> mysterious rather than informative. Every one leaves enough unsaid that >> more questions are needed. > > I can't divulge trade secrets or proprietary information that doesn't > belong to me. I can, however, hint in directions of benefit. Take > it or leave it. I have no idea what you are talking about. If you don't have anything to say, why are you bothering to post? I don't even recall the hints. Or are you forbidden from pointing out what those are? You said you had already mentioned a way to reduce table size. What was that? -- Rick From newsfish@newsfish Thu Aug 1 00:32:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 16:13:15 -0500 Organization: A noiseless patient Spider Lines: 71 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> <549c7a34.949356689@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 21:13:02 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="8834"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/I1uClhzeKwBRRh1O80df5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c7a34.949356689@news.eternal-september.org> Cancel-Lock: sha1:p2xkTMrovFmYMYpmQWZIKTMZ6eI= Xref: news.eternal-september.org comp.dsp:26051 comp.lang.vhdl:3505 On 12/25/2014 4:01 PM, Eric Jacobsen wrote: > On Thu, 25 Dec 2014 12:02:57 -0500, rickman wrote: > >> On 12/25/2014 10:55 AM, Eric Jacobsen wrote: >>> On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle >>> wrote: >>> >>>> I agree that the CORDIC has the same complexity as a multiply. I agree >>>> that table-based algorithms using multipliers use less FPGA fabric. >>>> >>>> I was simply pointing out that there might be places where a CORDIC has >>>> advantages over LUT-based NCOs. >>>> >>>> Especially if have ROM or multiplier limitations. >>>> >>>> I also wanted to point out that if you need to do a 20-bit (using your >>>> 120dB example) complex downconversion for example, the CORDIC still >>>> requires zero multipliers. >>>> >>>> If you want to do a 20-bit complex downconversion using a table-based >>>> NCO followed by a complex mixer, you might need a *lot* of multipliers. >>>> If you only have an 18-bit multiplier, each multiplication requires >>>> (maybe up to) 4 multiplier blocks and you need 8 multiplications. >>>> >>>> I also /suspect/ that for any given device technology the CORDIC will >>>> execute at higher speeds. >>>> >>>> Thats all... >>> >>> That's been my experience; that if multipliers are scarce or too >>> expensive, or memory is scarce or too expensive, then a CORDIC is a >>> nice back-up option. These days multipliers and memory are both >>> plentiful in most platforms, so CORDICs just aren't as useful as they >>> used to be. >> >> I think the distinction between a multiply and the CORDIC technique is >> bogus. CORDIC is an iterative process including all the operations that >> make up a multiply. The only difference is that in many cases there is >> hardware available that facilitates execution of generic multiplies >> while the CORDIC must be implemented in detail in every case. > > In the past (some of it long ago) when we did tradeoffs on using a > CORDIC or an NCO, or a CORDIC or a complex mix implemented with > multipliers, it comes down to resource availability. If multipliers > are available (either in FPGA fabric or as a module in silicon), then > a mixer is generally much more efficient with multipliers. If the > memory is available, then a LUT with a phase accumulator is hard to > beat for a numeric oscillator. The latency may also tilt the > tradeoff further away from the CORDIC. > > They certainly have their place, but those places have gotten more > limited as silicon resources get cheaper. Let's assume there is no multiplier blocks and no LUTs. Now how is the CORDIC better than using a multiplies? Just like the CORDIC the multiplies can be done iteratively using virtually the same logic. Speed, in most cases, will be determined by the carry chain in the adder so speed should be about the same. >>> The latency is sometimes an issue as well. >>> >>> There are still some places where they make sense, though. >> >> Care to explain? So where are the places where the CORDIC makes sense? -- Rick From newsfish@newsfish Thu Aug 1 00:32:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 21:32:55 GMT Organization: Anchor Hill Communications Lines: 72 Message-ID: <549c8171.951208826@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="11567"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18dNbYLZL1qZquayIakBuok9mApxf6vzrE=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-1, 12/25/2014), Outbound message Cancel-Lock: sha1:dOjJGWvgkcUWyKhh/yldaYgqV0E= Xref: news.eternal-september.org comp.dsp:26054 comp.lang.vhdl:3506 On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >> >>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>> >>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>> >>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>> >>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>> can be done without multipliers. >>>>>>> >>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>> approximation, without multipliers. >>>>>> >>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>> usually in silicon as well. >>>>>> >>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>> apps are limited to comm. >>>>> >>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>> fine. But if you want better performance the single LUT approach >>>>> requires *very* large tables. >>>> >>>> There are a lot of tricks that can be used to keep the table size >>>> down. I've mentioned one already. >>> >>> And what was that? You have made some 20 or more posts in this thread, >>> I don't feel like weeding through all of them to find this. Reading >>> back through this thread it seems like your posts are intended to be >>> mysterious rather than informative. Every one leaves enough unsaid that >>> more questions are needed. >> >> I can't divulge trade secrets or proprietary information that doesn't >> belong to me. I can, however, hint in directions of benefit. Take >> it or leave it. > >I have no idea what you are talking about. If you don't have anything >to say, why are you bothering to post? Why do you care whether I post or not? Feel free to put me in your kill file if you don't like my posts. > I don't even recall the hints. >Or are you forbidden from pointing out what those are? No, but it seems to me like unnecessary duplication. There are lots of hints from multiple people scattered throughout the thread, as well as in some of the literature mentioned previously. >You said you had already mentioned a way to reduce table size. What was >that? One way is to store a quarter wave instead of a full cycle. I think that was mentioned more than once, but here it is again just for you. >-- > >Rick Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 21:34:41 GMT Organization: Anchor Hill Communications Lines: 79 Message-ID: <549c82a3.951515306@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> <549c7a34.949356689@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="11567"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Z4lbMEFUCX77+P4QjZF4618iu/0dpjE0=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-1, 12/25/2014), Outbound message Cancel-Lock: sha1:SjQl0a5ESQu0Oysef3o/OxhSHJs= Xref: news.eternal-september.org comp.dsp:26055 comp.lang.vhdl:3507 On Thu, 25 Dec 2014 16:13:15 -0500, rickman wrote: >On 12/25/2014 4:01 PM, Eric Jacobsen wrote: >> On Thu, 25 Dec 2014 12:02:57 -0500, rickman wrote: >> >>> On 12/25/2014 10:55 AM, Eric Jacobsen wrote: >>>> On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle >>>> wrote: >>>> >>>>> I agree that the CORDIC has the same complexity as a multiply. I agree >>>>> that table-based algorithms using multipliers use less FPGA fabric. >>>>> >>>>> I was simply pointing out that there might be places where a CORDIC has >>>>> advantages over LUT-based NCOs. >>>>> >>>>> Especially if have ROM or multiplier limitations. >>>>> >>>>> I also wanted to point out that if you need to do a 20-bit (using your >>>>> 120dB example) complex downconversion for example, the CORDIC still >>>>> requires zero multipliers. >>>>> >>>>> If you want to do a 20-bit complex downconversion using a table-based >>>>> NCO followed by a complex mixer, you might need a *lot* of multipliers. >>>>> If you only have an 18-bit multiplier, each multiplication requires >>>>> (maybe up to) 4 multiplier blocks and you need 8 multiplications. >>>>> >>>>> I also /suspect/ that for any given device technology the CORDIC will >>>>> execute at higher speeds. >>>>> >>>>> Thats all... >>>> >>>> That's been my experience; that if multipliers are scarce or too >>>> expensive, or memory is scarce or too expensive, then a CORDIC is a >>>> nice back-up option. These days multipliers and memory are both >>>> plentiful in most platforms, so CORDICs just aren't as useful as they >>>> used to be. >>> >>> I think the distinction between a multiply and the CORDIC technique is >>> bogus. CORDIC is an iterative process including all the operations that >>> make up a multiply. The only difference is that in many cases there is >>> hardware available that facilitates execution of generic multiplies >>> while the CORDIC must be implemented in detail in every case. >> >> In the past (some of it long ago) when we did tradeoffs on using a >> CORDIC or an NCO, or a CORDIC or a complex mix implemented with >> multipliers, it comes down to resource availability. If multipliers >> are available (either in FPGA fabric or as a module in silicon), then >> a mixer is generally much more efficient with multipliers. If the >> memory is available, then a LUT with a phase accumulator is hard to >> beat for a numeric oscillator. The latency may also tilt the >> tradeoff further away from the CORDIC. >> >> They certainly have their place, but those places have gotten more >> limited as silicon resources get cheaper. > >Let's assume there is no multiplier blocks and no LUTs. Now how is the >CORDIC better than using a multiplies? Just like the CORDIC the >multiplies can be done iteratively using virtually the same logic. >Speed, in most cases, will be determined by the carry chain in the adder >so speed should be about the same. It could be there isn't much difference, which means if you have a CORDIC laying around, there may not be a reason to not use it. >>>> The latency is sometimes an issue as well. >>>> >>>> There are still some places where they make sense, though. >>> >>> Care to explain? > >So where are the places where the CORDIC makes sense? > >-- > >Rick Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 18:08:54 -0500 Organization: A noiseless patient Spider Lines: 92 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 23:08:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="32014"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xhEulFRZPIe7juyE0p0A6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c8171.951208826@news.eternal-september.org> Cancel-Lock: sha1:KqwWcax4DryqH5aJju+eB0YIoUY= Xref: news.eternal-september.org comp.dsp:26057 comp.lang.vhdl:3508 On 12/25/2014 4:32 PM, Eric Jacobsen wrote: > On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: > >> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>> >>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>> >>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>> >>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>> >>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>> can be done without multipliers. >>>>>>>> >>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>> approximation, without multipliers. >>>>>>> >>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>> usually in silicon as well. >>>>>>> >>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>> apps are limited to comm. >>>>>> >>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>> fine. But if you want better performance the single LUT approach >>>>>> requires *very* large tables. >>>>> >>>>> There are a lot of tricks that can be used to keep the table size >>>>> down. I've mentioned one already. >>>> >>>> And what was that? You have made some 20 or more posts in this thread, >>>> I don't feel like weeding through all of them to find this. Reading >>>> back through this thread it seems like your posts are intended to be >>>> mysterious rather than informative. Every one leaves enough unsaid that >>>> more questions are needed. >>> >>> I can't divulge trade secrets or proprietary information that doesn't >>> belong to me. I can, however, hint in directions of benefit. Take >>> it or leave it. >> >> I have no idea what you are talking about. If you don't have anything >> to say, why are you bothering to post? > > Why do you care whether I post or not? Feel free to put me in your > kill file if you don't like my posts. If you aren't interested in having a conversation, why do you bother to type? Above you said you had already mentioned "one" method already. Clearly that one is not a trade secret. Care to explain what method you are referring to? >> I don't even recall the hints. >> Or are you forbidden from pointing out what those are? > > No, but it seems to me like unnecessary duplication. There are lots > of hints from multiple people scattered throughout the thread, as well > as in some of the literature mentioned previously. Exactly, scattered in some 50 or so messages. If you have something to say, why no say it instead of being so vague? Just tell me which message you are referring to. >> You said you had already mentioned a way to reduce table size. What was >> that? > > One way is to store a quarter wave instead of a full cycle. I think > that was mentioned more than once, but here it is again just for you. Thank you for the response. Yes, that is table reduction 101. Anyone other than a newbie is aware of that. I believe *I* was the one who in this thread pointed it out to someone who said memory is cheap not fully appreciating that memory is order 2^N is size. Even so it is just a factor of four and does nothing to change the fact that memory is anything but cheap if you are looking for high resolution and low distortion. Using MBs of memory to store a LUT is usually not a good trade off. What was the technique *you* mentioned as you indicate above? -- Rick From newsfish@newsfish Thu Aug 1 00:32:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 26 Dec 2014 16:45:35 GMT Organization: Anchor Hill Communications Lines: 107 Message-ID: <549d8ef7.1020206758@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="17051"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1//YAYVSojgLLizsEWQbKRJh1Kzb6jcaZI=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141226-0, 12/26/2014), Outbound message Cancel-Lock: sha1:cEBmjhHQEJnK73pIXHZlNDnjrg4= Xref: news.eternal-september.org comp.dsp:26066 comp.lang.vhdl:3509 On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >> >>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>> >>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>> >>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>> >>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>> >>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>> can be done without multipliers. >>>>>>>>> >>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>> approximation, without multipliers. >>>>>>>> >>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>> usually in silicon as well. >>>>>>>> >>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>> apps are limited to comm. >>>>>>> >>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>> fine. But if you want better performance the single LUT approach >>>>>>> requires *very* large tables. >>>>>> >>>>>> There are a lot of tricks that can be used to keep the table size >>>>>> down. I've mentioned one already. >>>>> >>>>> And what was that? You have made some 20 or more posts in this thread, >>>>> I don't feel like weeding through all of them to find this. Reading >>>>> back through this thread it seems like your posts are intended to be >>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>> more questions are needed. >>>> >>>> I can't divulge trade secrets or proprietary information that doesn't >>>> belong to me. I can, however, hint in directions of benefit. Take >>>> it or leave it. >>> >>> I have no idea what you are talking about. If you don't have anything >>> to say, why are you bothering to post? >> >> Why do you care whether I post or not? Feel free to put me in your >> kill file if you don't like my posts. > >If you aren't interested in having a conversation, why do you bother to >type? Above you said you had already mentioned "one" method already. >Clearly that one is not a trade secret. Care to explain what method you >are referring to? I did later in the same post. >>> I don't even recall the hints. >>> Or are you forbidden from pointing out what those are? >> >> No, but it seems to me like unnecessary duplication. There are lots >> of hints from multiple people scattered throughout the thread, as well >> as in some of the literature mentioned previously. > >Exactly, scattered in some 50 or so messages. If you have something to >say, why no say it instead of being so vague? Just tell me which >message you are referring to. So you want me to go back and search through the thread for you? Are you not capable of doing that? I'm not at all clear why you think that I should do the search if you're the one that wants the information. >>> You said you had already mentioned a way to reduce table size. What was >>> that? >> >> One way is to store a quarter wave instead of a full cycle. I think >> that was mentioned more than once, but here it is again just for you. > >Thank you for the response. > >Yes, that is table reduction 101. Anyone other than a newbie is aware >of that. I believe *I* was the one who in this thread pointed it out to >someone who said memory is cheap not fully appreciating that memory is >order 2^N is size. Even so it is just a factor of four and does nothing >to change the fact that memory is anything but cheap if you are looking >for high resolution and low distortion. Using MBs of memory to store a >LUT is usually not a good trade off. > >What was the technique *you* mentioned as you indicate above? That was one of them. I mentioned it more than once. In my experience a 4x reduction in memory can be significant, and the quarter-wave trick isn't obvious to some people so I didn't make the assumption that it was. You're welcome. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 26 Dec 2014 12:05:24 -0500 Organization: A noiseless patient Spider Lines: 122 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 26 Dec 2014 17:05:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21348"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Nb4gR7FvRS2mN1oRFyQ+e" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549d8ef7.1020206758@news.eternal-september.org> Cancel-Lock: sha1:AB0al25NbOBt5tFON+ctJ4QnSh4= Xref: news.eternal-september.org comp.dsp:26067 comp.lang.vhdl:3510 On 12/26/2014 11:45 AM, Eric Jacobsen wrote: > On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: > >> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>> >>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>> >>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>> >>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>> >>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>> >>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>> can be done without multipliers. >>>>>>>>>> >>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>> approximation, without multipliers. >>>>>>>>> >>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>> usually in silicon as well. >>>>>>>>> >>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>> apps are limited to comm. >>>>>>>> >>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>> requires *very* large tables. >>>>>>> >>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>> down. I've mentioned one already. >>>>>> >>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>> back through this thread it seems like your posts are intended to be >>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>> more questions are needed. >>>>> >>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>> it or leave it. >>>> >>>> I have no idea what you are talking about. If you don't have anything >>>> to say, why are you bothering to post? >>> >>> Why do you care whether I post or not? Feel free to put me in your >>> kill file if you don't like my posts. >> >> If you aren't interested in having a conversation, why do you bother to >> type? Above you said you had already mentioned "one" method already. >> Clearly that one is not a trade secret. Care to explain what method you >> are referring to? > > I did later in the same post. What same post would that be? I'm not sure what "same" means since the context is not clear. >>>> I don't even recall the hints. >>>> Or are you forbidden from pointing out what those are? >>> >>> No, but it seems to me like unnecessary duplication. There are lots >>> of hints from multiple people scattered throughout the thread, as well >>> as in some of the literature mentioned previously. >> >> Exactly, scattered in some 50 or so messages. If you have something to >> say, why no say it instead of being so vague? Just tell me which >> message you are referring to. > > So you want me to go back and search through the thread for you? Are > you not capable of doing that? I'm not at all clear why you think > that I should do the search if you're the one that wants the > information. I'm assuming that you might have more recollection of having made a post than I do of reading it. I did a scan and I never saw any useful comments on table reduction. Everything you posted seems to allude to things but always shies away from actually giving any info. >>>> You said you had already mentioned a way to reduce table size. What was >>>> that? >>> >>> One way is to store a quarter wave instead of a full cycle. I think >>> that was mentioned more than once, but here it is again just for you. >> >> Thank you for the response. >> >> Yes, that is table reduction 101. Anyone other than a newbie is aware >> of that. I believe *I* was the one who in this thread pointed it out to >> someone who said memory is cheap not fully appreciating that memory is >> order 2^N is size. Even so it is just a factor of four and does nothing >> to change the fact that memory is anything but cheap if you are looking >> for high resolution and low distortion. Using MBs of memory to store a >> LUT is usually not a good trade off. >> >> What was the technique *you* mentioned as you indicate above? > > That was one of them. I mentioned it more than once. In my > experience a 4x reduction in memory can be significant, and the > quarter-wave trick isn't obvious to some people so I didn't make the > assumption that it was. > > You're welcome. Yes, a four fold reduction in size can be useful, but like I said, this is sine table 101. Was there anything else of value you have to offer on the topic? -- Rick From newsfish@newsfish Thu Aug 1 00:32:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 26 Dec 2014 18:15:24 GMT Organization: Anchor Hill Communications Lines: 135 Message-ID: <549da465.1025693142@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="7009"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Y05Qsu8LlJfIjxxbwuZLT3M/6hiGRbRk=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141226-0, 12/26/2014), Outbound message Cancel-Lock: sha1:TwBj2udw7cpwt7GQXeeIXhRPJDU= Xref: news.eternal-september.org comp.dsp:26069 comp.lang.vhdl:3511 On Fri, 26 Dec 2014 12:05:24 -0500, rickman wrote: >On 12/26/2014 11:45 AM, Eric Jacobsen wrote: >> On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >> >>> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>>> >>>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>>> >>>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>>> >>>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>>> >>>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>>> >>>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>>> can be done without multipliers. >>>>>>>>>>> >>>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>>> approximation, without multipliers. >>>>>>>>>> >>>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>>> usually in silicon as well. >>>>>>>>>> >>>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>>> apps are limited to comm. >>>>>>>>> >>>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>>> requires *very* large tables. >>>>>>>> >>>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>>> down. I've mentioned one already. >>>>>>> >>>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>>> back through this thread it seems like your posts are intended to be >>>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>>> more questions are needed. >>>>>> >>>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>>> it or leave it. >>>>> >>>>> I have no idea what you are talking about. If you don't have anything >>>>> to say, why are you bothering to post? >>>> >>>> Why do you care whether I post or not? Feel free to put me in your >>>> kill file if you don't like my posts. >>> >>> If you aren't interested in having a conversation, why do you bother to >>> type? Above you said you had already mentioned "one" method already. >>> Clearly that one is not a trade secret. Care to explain what method you >>> are referring to? >> >> I did later in the same post. > >What same post would that be? I'm not sure what "same" means since the >context is not clear. The same one you were responding to at the time. >>>>> I don't even recall the hints. >>>>> Or are you forbidden from pointing out what those are? >>>> >>>> No, but it seems to me like unnecessary duplication. There are lots >>>> of hints from multiple people scattered throughout the thread, as well >>>> as in some of the literature mentioned previously. >>> >>> Exactly, scattered in some 50 or so messages. If you have something to >>> say, why no say it instead of being so vague? Just tell me which >>> message you are referring to. >> >> So you want me to go back and search through the thread for you? Are >> you not capable of doing that? I'm not at all clear why you think >> that I should do the search if you're the one that wants the >> information. > >I'm assuming that you might have more recollection of having made a >post than I do of reading it. I did a scan and I never saw any useful >comments on table reduction. Everything you posted seems to allude to >things but always shies away from actually giving any info. I mentioned the quarter-wave reduction specifically multiple times. Sorry you weren't able to glean anything. Not everybody does. >>>>> You said you had already mentioned a way to reduce table size. What was >>>>> that? >>>> >>>> One way is to store a quarter wave instead of a full cycle. I think >>>> that was mentioned more than once, but here it is again just for you. >>> >>> Thank you for the response. >>> >>> Yes, that is table reduction 101. Anyone other than a newbie is aware >>> of that. I believe *I* was the one who in this thread pointed it out to >>> someone who said memory is cheap not fully appreciating that memory is >>> order 2^N is size. Even so it is just a factor of four and does nothing >>> to change the fact that memory is anything but cheap if you are looking >>> for high resolution and low distortion. Using MBs of memory to store a >>> LUT is usually not a good trade off. >>> >>> What was the technique *you* mentioned as you indicate above? >> >> That was one of them. I mentioned it more than once. In my >> experience a 4x reduction in memory can be significant, and the >> quarter-wave trick isn't obvious to some people so I didn't make the >> assumption that it was. >> >> You're welcome. > >Yes, a four fold reduction in size can be useful, but like I said, this >is sine table 101. > >Was there anything else of value you have to offer on the topic? You can go back and see what's valuable to you, and I can't anticipate what will or won't be. You seem to resent having the quarter-wave trick pointed out to you, so I'm not going to try to guess what you might or might not find obvious. One of the nice things about usenet is that the posts a pretty sticky, so you can go back and review if you want to and take or leave things as you see fit. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 01:35:55 -0500 Organization: A noiseless patient Spider Lines: 150 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> <549da465.1025693142@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 27 Dec 2014 06:35:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="9797"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/JO59OGUJ9Mz6tFhC99LiH" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549da465.1025693142@news.eternal-september.org> Cancel-Lock: sha1:fcfVhLGF1c6IuhWkpCm/fg1dOEU= Xref: news.eternal-september.org comp.dsp:26074 comp.lang.vhdl:3512 On 12/26/2014 1:15 PM, Eric Jacobsen wrote: > On Fri, 26 Dec 2014 12:05:24 -0500, rickman wrote: > >> On 12/26/2014 11:45 AM, Eric Jacobsen wrote: >>> On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >>> >>>> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>>>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>>>> >>>>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>>>> >>>>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>>>> >>>>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>>>> >>>>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>>>> >>>>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>>>> can be done without multipliers. >>>>>>>>>>>> >>>>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>>>> approximation, without multipliers. >>>>>>>>>>> >>>>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>>>> usually in silicon as well. >>>>>>>>>>> >>>>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>>>> apps are limited to comm. >>>>>>>>>> >>>>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>>>> requires *very* large tables. >>>>>>>>> >>>>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>>>> down. I've mentioned one already. >>>>>>>> >>>>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>>>> back through this thread it seems like your posts are intended to be >>>>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>>>> more questions are needed. >>>>>>> >>>>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>>>> it or leave it. >>>>>> >>>>>> I have no idea what you are talking about. If you don't have anything >>>>>> to say, why are you bothering to post? >>>>> >>>>> Why do you care whether I post or not? Feel free to put me in your >>>>> kill file if you don't like my posts. >>>> >>>> If you aren't interested in having a conversation, why do you bother to >>>> type? Above you said you had already mentioned "one" method already. >>>> Clearly that one is not a trade secret. Care to explain what method you >>>> are referring to? >>> >>> I did later in the same post. >> >> What same post would that be? I'm not sure what "same" means since the >> context is not clear. > > The same one you were responding to at the time. At this point it is pretty clear you are just playing with me and have nothing to say. >>>>>> I don't even recall the hints. >>>>>> Or are you forbidden from pointing out what those are? >>>>> >>>>> No, but it seems to me like unnecessary duplication. There are lots >>>>> of hints from multiple people scattered throughout the thread, as well >>>>> as in some of the literature mentioned previously. >>>> >>>> Exactly, scattered in some 50 or so messages. If you have something to >>>> say, why no say it instead of being so vague? Just tell me which >>>> message you are referring to. >>> >>> So you want me to go back and search through the thread for you? Are >>> you not capable of doing that? I'm not at all clear why you think >>> that I should do the search if you're the one that wants the >>> information. >> >> I'm assuming that you might have more recollection of having made a >> post than I do of reading it. I did a scan and I never saw any useful >> comments on table reduction. Everything you posted seems to allude to >> things but always shies away from actually giving any info. > > I mentioned the quarter-wave reduction specifically multiple times. > Sorry you weren't able to glean anything. Not everybody does. I just never read your post in this thread where you mentioned that. That's why I pointed it out to someone who spoke of using the full wave. >>>>>> You said you had already mentioned a way to reduce table size. What was >>>>>> that? >>>>> >>>>> One way is to store a quarter wave instead of a full cycle. I think >>>>> that was mentioned more than once, but here it is again just for you. >>>> >>>> Thank you for the response. >>>> >>>> Yes, that is table reduction 101. Anyone other than a newbie is aware >>>> of that. I believe *I* was the one who in this thread pointed it out to >>>> someone who said memory is cheap not fully appreciating that memory is >>>> order 2^N is size. Even so it is just a factor of four and does nothing >>>> to change the fact that memory is anything but cheap if you are looking >>>> for high resolution and low distortion. Using MBs of memory to store a >>>> LUT is usually not a good trade off. >>>> >>>> What was the technique *you* mentioned as you indicate above? >>> >>> That was one of them. I mentioned it more than once. In my >>> experience a 4x reduction in memory can be significant, and the >>> quarter-wave trick isn't obvious to some people so I didn't make the >>> assumption that it was. >>> >>> You're welcome. >> >> Yes, a four fold reduction in size can be useful, but like I said, this >> is sine table 101. >> >> Was there anything else of value you have to offer on the topic? > > You can go back and see what's valuable to you, and I can't anticipate > what will or won't be. You seem to resent having the quarter-wave > trick pointed out to you, so I'm not going to try to guess what you > might or might not find obvious. One of the nice things about usenet > is that the posts a pretty sticky, so you can go back and review if > you want to and take or leave things as you see fit. I have read your posts here and I didn't see you mention the quarter wave table or anything else specific. Rather you gave thin references to the fact that "significant" reductions are possible. That's why I asked and so far you have not been able to explain what you meant or point to a post. You just keep repeating that you have already said things. Ok, nuff said. -- Rick From newsfish@newsfish Thu Aug 1 00:32:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 10:33:15 +0100 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> <549c7a34.949356689@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 27 Dec 2014 09:32:52 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="b4bd7f96a7efdaa1b5fa87721b3547c4"; logging-data="5537"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/rbPECLYBzcG0KWNczR0he" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:SPk3QStB5D7+glkliL8w9O9M4VE= Xref: news.eternal-september.org comp.lang.vhdl:3513 > So where are the places where the CORDIC makes sense? rickman, You are annoying with your posts. Use your imagination. Nearly every calculator use cordic instead of LUT for trigonometric functions. Why? (Please don't answer, it's a rhetorical question.) Bart From newsfish@newsfish Thu Aug 1 00:32:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 05:25:07 -0500 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> <549c7a34.949356689@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 27 Dec 2014 10:24:52 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14277"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+tfZnZvVzfHNl+l2LEPclz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:ao/JFKvXBxuPBhDnAOBg9T7hBjE= Xref: news.eternal-september.org comp.lang.vhdl:3514 On 12/27/2014 4:33 AM, Bart Fox wrote: >> So where are the places where the CORDIC makes sense? > rickman, > You are annoying with your posts. > > Use your imagination. > Nearly every calculator use cordic instead of LUT for trigonometric > functions. Why? > (Please don't answer, it's a rhetorical question.) I don't get your post. You say my questions are annoying, and then you ask a "rhetorical" question as if I am supposed to know the answer. If I knew the answer, I wouldn't be asking the question myself. -- Rick From newsfish@newsfish Thu Aug 1 00:32:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 16:33:10 GMT Organization: Anchor Hill Communications Lines: 165 Message-ID: <549edda8.1105888388@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> <549da465.1025693142@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="25843"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qBPNzii2Cjfu57S7RFdIC3dxvB9xzvwE=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141227-0, 12/27/2014), Outbound message Cancel-Lock: sha1:jh3dgQKWeaq0tviQNtTyrgX3BdE= Xref: news.eternal-september.org comp.dsp:26075 comp.lang.vhdl:3515 On Sat, 27 Dec 2014 01:35:55 -0500, rickman wrote: >On 12/26/2014 1:15 PM, Eric Jacobsen wrote: >> On Fri, 26 Dec 2014 12:05:24 -0500, rickman wrote: >> >>> On 12/26/2014 11:45 AM, Eric Jacobsen wrote: >>>> On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >>>> >>>>> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>>>>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>>>>> >>>>>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>>>>> >>>>>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>>>>> >>>>>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>>>>> >>>>>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>>>>> >>>>>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>>>>> can be done without multipliers. >>>>>>>>>>>>> >>>>>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>>>>> approximation, without multipliers. >>>>>>>>>>>> >>>>>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>>>>> usually in silicon as well. >>>>>>>>>>>> >>>>>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>>>>> apps are limited to comm. >>>>>>>>>>> >>>>>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>>>>> requires *very* large tables. >>>>>>>>>> >>>>>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>>>>> down. I've mentioned one already. >>>>>>>>> >>>>>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>>>>> back through this thread it seems like your posts are intended to be >>>>>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>>>>> more questions are needed. >>>>>>>> >>>>>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>>>>> it or leave it. >>>>>>> >>>>>>> I have no idea what you are talking about. If you don't have anything >>>>>>> to say, why are you bothering to post? >>>>>> >>>>>> Why do you care whether I post or not? Feel free to put me in your >>>>>> kill file if you don't like my posts. >>>>> >>>>> If you aren't interested in having a conversation, why do you bother to >>>>> type? Above you said you had already mentioned "one" method already. >>>>> Clearly that one is not a trade secret. Care to explain what method you >>>>> are referring to? >>>> >>>> I did later in the same post. >>> >>> What same post would that be? I'm not sure what "same" means since the >>> context is not clear. >> >> The same one you were responding to at the time. > >At this point it is pretty clear you are just playing with me and have >nothing to say. No, seriously, it was in the same post. I found it ironic that you were asking me to explain the method I was referring to, and I had explained in the post you were responding to at the time. >>>>>>> I don't even recall the hints. >>>>>>> Or are you forbidden from pointing out what those are? >>>>>> >>>>>> No, but it seems to me like unnecessary duplication. There are lots >>>>>> of hints from multiple people scattered throughout the thread, as well >>>>>> as in some of the literature mentioned previously. >>>>> >>>>> Exactly, scattered in some 50 or so messages. If you have something to >>>>> say, why no say it instead of being so vague? Just tell me which >>>>> message you are referring to. >>>> >>>> So you want me to go back and search through the thread for you? Are >>>> you not capable of doing that? I'm not at all clear why you think >>>> that I should do the search if you're the one that wants the >>>> information. >>> >>> I'm assuming that you might have more recollection of having made a >>> post than I do of reading it. I did a scan and I never saw any useful >>> comments on table reduction. Everything you posted seems to allude to >>> things but always shies away from actually giving any info. >> >> I mentioned the quarter-wave reduction specifically multiple times. >> Sorry you weren't able to glean anything. Not everybody does. > >I just never read your post in this thread where you mentioned that. >That's why I pointed it out to someone who spoke of using the full wave. > >>>>>>> You said you had already mentioned a way to reduce table size. What was >>>>>>> that? >>>>>> >>>>>> One way is to store a quarter wave instead of a full cycle. I think >>>>>> that was mentioned more than once, but here it is again just for you. >>>>> >>>>> Thank you for the response. >>>>> >>>>> Yes, that is table reduction 101. Anyone other than a newbie is aware >>>>> of that. I believe *I* was the one who in this thread pointed it out to >>>>> someone who said memory is cheap not fully appreciating that memory is >>>>> order 2^N is size. Even so it is just a factor of four and does nothing >>>>> to change the fact that memory is anything but cheap if you are looking >>>>> for high resolution and low distortion. Using MBs of memory to store a >>>>> LUT is usually not a good trade off. >>>>> >>>>> What was the technique *you* mentioned as you indicate above? >>>> >>>> That was one of them. I mentioned it more than once. In my >>>> experience a 4x reduction in memory can be significant, and the >>>> quarter-wave trick isn't obvious to some people so I didn't make the >>>> assumption that it was. >>>> >>>> You're welcome. >>> >>> Yes, a four fold reduction in size can be useful, but like I said, this >>> is sine table 101. >>> >>> Was there anything else of value you have to offer on the topic? >> >> You can go back and see what's valuable to you, and I can't anticipate >> what will or won't be. You seem to resent having the quarter-wave >> trick pointed out to you, so I'm not going to try to guess what you >> might or might not find obvious. One of the nice things about usenet >> is that the posts a pretty sticky, so you can go back and review if >> you want to and take or leave things as you see fit. > >I have read your posts here and I didn't see you mention the quarter >wave table or anything else specific. Rather you gave thin references >to the fact that "significant" reductions are possible. That's why I >asked and so far you have not been able to explain what you meant or >point to a post. You just keep repeating that you have already said >things. Ok, nuff said. I've mentioned several techniques for improving DDS performance specifically. I didn't go into a lot of detail, but I mentioned a number of things pretty unambiguously, both before and after the thread started cross-posting. Maybe you just didn't see them. I use Forte newsreader, and there's not a simple way to go back and search which posts in a thread contained what, even if I posted it. I'm not inclined to do that for you. Sorry. It's there if you, or anybody, want to look, though. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Thu Aug 1 00:32:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 14:49:33 -0500 Organization: A noiseless patient Spider Lines: 171 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> <549da465.1025693142@news.eternal-september.org> <549edda8.1105888388@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 27 Dec 2014 19:49:18 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="4217"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+EG/qoSE/U+tTxpKzqnR6P" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549edda8.1105888388@news.eternal-september.org> Cancel-Lock: sha1:Pj6OIDFOtpL3WB8PIoG4oE39IJM= Xref: news.eternal-september.org comp.dsp:26077 comp.lang.vhdl:3516 On 12/27/2014 11:33 AM, Eric Jacobsen wrote: > On Sat, 27 Dec 2014 01:35:55 -0500, rickman wrote: > >> On 12/26/2014 1:15 PM, Eric Jacobsen wrote: >>> On Fri, 26 Dec 2014 12:05:24 -0500, rickman wrote: >>> >>>> On 12/26/2014 11:45 AM, Eric Jacobsen wrote: >>>>> On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >>>>> >>>>>> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>>>>>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>>>>>> >>>>>>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>>>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>>>>>> >>>>>>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>>>>>> >>>>>>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>>>>>> >>>>>>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>>>>>> can be done without multipliers. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>>>>>> approximation, without multipliers. >>>>>>>>>>>>> >>>>>>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>>>>>> usually in silicon as well. >>>>>>>>>>>>> >>>>>>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>>>>>> apps are limited to comm. >>>>>>>>>>>> >>>>>>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>>>>>> requires *very* large tables. >>>>>>>>>>> >>>>>>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>>>>>> down. I've mentioned one already. >>>>>>>>>> >>>>>>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>>>>>> back through this thread it seems like your posts are intended to be >>>>>>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>>>>>> more questions are needed. >>>>>>>>> >>>>>>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>>>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>>>>>> it or leave it. >>>>>>>> >>>>>>>> I have no idea what you are talking about. If you don't have anything >>>>>>>> to say, why are you bothering to post? >>>>>>> >>>>>>> Why do you care whether I post or not? Feel free to put me in your >>>>>>> kill file if you don't like my posts. >>>>>> >>>>>> If you aren't interested in having a conversation, why do you bother to >>>>>> type? Above you said you had already mentioned "one" method already. >>>>>> Clearly that one is not a trade secret. Care to explain what method you >>>>>> are referring to? >>>>> >>>>> I did later in the same post. >>>> >>>> What same post would that be? I'm not sure what "same" means since the >>>> context is not clear. >>> >>> The same one you were responding to at the time. >> >> At this point it is pretty clear you are just playing with me and have >> nothing to say. > > No, seriously, it was in the same post. I found it ironic that you > were asking me to explain the method I was referring to, and I had > explained in the post you were responding to at the time. I have no idea which post you are referring to. Context is long lost and you keep saying the "same post". >>>>>>>> I don't even recall the hints. >>>>>>>> Or are you forbidden from pointing out what those are? >>>>>>> >>>>>>> No, but it seems to me like unnecessary duplication. There are lots >>>>>>> of hints from multiple people scattered throughout the thread, as well >>>>>>> as in some of the literature mentioned previously. >>>>>> >>>>>> Exactly, scattered in some 50 or so messages. If you have something to >>>>>> say, why no say it instead of being so vague? Just tell me which >>>>>> message you are referring to. >>>>> >>>>> So you want me to go back and search through the thread for you? Are >>>>> you not capable of doing that? I'm not at all clear why you think >>>>> that I should do the search if you're the one that wants the >>>>> information. >>>> >>>> I'm assuming that you might have more recollection of having made a >>>> post than I do of reading it. I did a scan and I never saw any useful >>>> comments on table reduction. Everything you posted seems to allude to >>>> things but always shies away from actually giving any info. >>> >>> I mentioned the quarter-wave reduction specifically multiple times. >>> Sorry you weren't able to glean anything. Not everybody does. >> >> I just never read your post in this thread where you mentioned that. >> That's why I pointed it out to someone who spoke of using the full wave. >> >>>>>>>> You said you had already mentioned a way to reduce table size. What was >>>>>>>> that? >>>>>>> >>>>>>> One way is to store a quarter wave instead of a full cycle. I think >>>>>>> that was mentioned more than once, but here it is again just for you. >>>>>> >>>>>> Thank you for the response. >>>>>> >>>>>> Yes, that is table reduction 101. Anyone other than a newbie is aware >>>>>> of that. I believe *I* was the one who in this thread pointed it out to >>>>>> someone who said memory is cheap not fully appreciating that memory is >>>>>> order 2^N is size. Even so it is just a factor of four and does nothing >>>>>> to change the fact that memory is anything but cheap if you are looking >>>>>> for high resolution and low distortion. Using MBs of memory to store a >>>>>> LUT is usually not a good trade off. >>>>>> >>>>>> What was the technique *you* mentioned as you indicate above? >>>>> >>>>> That was one of them. I mentioned it more than once. In my >>>>> experience a 4x reduction in memory can be significant, and the >>>>> quarter-wave trick isn't obvious to some people so I didn't make the >>>>> assumption that it was. >>>>> >>>>> You're welcome. >>>> >>>> Yes, a four fold reduction in size can be useful, but like I said, this >>>> is sine table 101. >>>> >>>> Was there anything else of value you have to offer on the topic? >>> >>> You can go back and see what's valuable to you, and I can't anticipate >>> what will or won't be. You seem to resent having the quarter-wave >>> trick pointed out to you, so I'm not going to try to guess what you >>> might or might not find obvious. One of the nice things about usenet >>> is that the posts a pretty sticky, so you can go back and review if >>> you want to and take or leave things as you see fit. >> >> I have read your posts here and I didn't see you mention the quarter >> wave table or anything else specific. Rather you gave thin references >> to the fact that "significant" reductions are possible. That's why I >> asked and so far you have not been able to explain what you meant or >> point to a post. You just keep repeating that you have already said >> things. Ok, nuff said. > > I've mentioned several techniques for improving DDS performance > specifically. I didn't go into a lot of detail, but I mentioned a > number of things pretty unambiguously, both before and after the > thread started cross-posting. Maybe you just didn't see them. > > I use Forte newsreader, and there's not a simple way to go back and > search which posts in a thread contained what, even if I posted it. > I'm not inclined to do that for you. Sorry. It's there if you, or > anybody, want to look, though. Yes, it's there... on the Internet. Anyone can find that! -- Rick From newsfish@newsfish Thu Aug 1 00:32:12 2024 X-Received: by 10.236.11.70 with SMTP id 46mr57640017yhw.22.1420188953915; Fri, 02 Jan 2015 00:55:53 -0800 (PST) X-Received: by 10.140.36.134 with SMTP id p6mr5528qgp.16.1420188953874; Fri, 02 Jan 2015 00:55:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!bm13no2717196qab.0!news-out.google.com!n9ni77qai.0!nntp.google.com!bm13no2717191qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 2 Jan 2015 00:55:53 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=84.11.95.114; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 84.11.95.114 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> Subject: Help with VHDL architecture From: Olalekan Shittu Injection-Date: Fri, 02 Jan 2015 08:55:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3517 Hello everyone. I have been trying to write a VHDL architecture for the circuit below but doesn't seem to be making headway, can anyone be of help. Below is my entity declaration from the system Library ieee; use IEEE.std_logic_1164.all; entity Sorter IS Port ( C: IN std_logic_vector (0 to 3); Sel: IN STD_LOGIC_VECTOR(0 to 2); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic ); end sorter; I am to write an architecture for the above with condition that: When Sel equal 4, the resulting output as shown in the table below is generated out0 out1 out2 out3 0 <= C < 4 1 0 0 0 4 <= C < 8 0 1 0 0 8 <= C < 12 0 0 1 0 12 <= C < 16 0 0 0 1 otherwise out0,out1,out2,out3 are all equal to zero. Thanks From newsfish@newsfish Thu Aug 1 00:32:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe002.ams.xsnews.nl!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 02 Jan 2015 03:16:47 -0600 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> In-Reply-To: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> Subject: Re: Help with VHDL architecture Date: Fri, 2 Jan 2015 09:16:23 -0000 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: Lines: 76 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-wgusDPkBGHgxpeOlzM8knku5Z4k+qsf/aD5cGZV8bCU8trjEKeM7OlNCWu2DtOidmJXyB81SoKmLyoW!6tPlbJWgPBbpaYQkPfkZc7a4BlusjrenqgzgnK5bi8zkS5A/opL8ewkE/oJslA2OZpTailB7LASZ!5qaxsCfsMbt+I6fnoCvO5cNahWI= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2636 Xref: news.eternal-september.org comp.lang.vhdl:3518 "Olalekan Shittu" wrote in message news:622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com... Hello everyone. I have been trying to write a VHDL architecture for the circuit below but doesn't seem to be making headway, can anyone be of help. Below is my entity declaration from the system Library ieee; use IEEE.std_logic_1164.all; entity Sorter IS Port ( C: IN std_logic_vector (0 to 3); Sel: IN STD_LOGIC_VECTOR(0 to 2); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic ); end sorter; I am to write an architecture for the above with condition that: When Sel equal 4, the resulting output as shown in the table below is generated out0 out1 out2 out3 0 <= C < 4 1 0 0 0 4 <= C < 8 0 1 0 0 8 <= C < 12 0 0 1 0 12 <= C < 16 0 0 0 1 otherwise out0,out1,out2,out3 are all equal to zero. Thanks Something like:- Defaults:- Out[3..0] = 0 End defaults If C >= 0 or C < 4 then out0 = 1 end if If C >= 4 or C < 8 then out1 = 1 end if If C >= 8 or C < 12end if out2 = 1 end if If C >= 12 or C < 16 then out3 = 1 end if From newsfish@newsfish Thu Aug 1 00:32:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe002.ams.xsnews.nl!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 02 Jan 2015 03:19:39 -0600 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> In-Reply-To: Subject: Re: Help with VHDL architecture Date: Fri, 2 Jan 2015 09:19:39 -0000 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: Lines: 48 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-6k7zh6VNplCoReRDFP3+mypcBqrittFW2J7/x02Rf4/8z4HyPtVFo6KjY12wi4rcOFDoj+z5odAuFrZ!TXw42VRwBwJysiggdRdnfF0foqBrqUVJ4+EICBKm6d5EMVnS2hGbyNzMCxHANSSMpYnRPH/KxVPF!Kzv5lvGn1zIvFOK/sVJObncXaVw= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1844 Xref: news.eternal-september.org comp.lang.vhdl:3519 "Andy Bennett" wrote in message news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk... Forgot to add sel ... so Something like:- Defaults:- Out[3..0] = 0 End defaults If sel = 4 then If C >= 0 or C < 4 then out0 = 1 end if If C >= 4 or C < 8 then out1 = 1 end if If C >= 8 or C < 12end if out2 = 1 end if If C >= 12 or C < 16 then out3 = 1 end if end if The student can add/correct the syntax Andy From newsfish@newsfish Thu Aug 1 00:32:13 2024 X-Received: by 10.182.68.10 with SMTP id r10mr68008390obt.13.1420281497360; Sat, 03 Jan 2015 02:38:17 -0800 (PST) X-Received: by 10.140.104.166 with SMTP id a35mr1540qgf.20.1420281497336; Sat, 03 Jan 2015 02:38:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no20632480igd.0!news-out.google.com!n9ni76qai.0!nntp.google.com!dc16no3798361qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Jan 2015 02:38:17 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=105.112.8.4; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 105.112.8.4 References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8aa2903c-12b4-4784-8a69-8eb7349ef645@googlegroups.com> Subject: Re: Help with VHDL architecture From: Olalekan Shittu Injection-Date: Sat, 03 Jan 2015 10:38:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3520 On Friday, 2 January 2015 10:19:42 UTC+1, Andy Bennett wrote: > "Andy Bennett" wrote in message > news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk... > > Forgot to add sel ... so > > > > > > > > Something like:- > > Defaults:- > > Out[3..0] = 0 > > End defaults > > > If sel = 4 then > If C >= 0 or C < 4 then > out0 = 1 > end if > > If C >= 4 or C < 8 then > out1 = 1 > end if > > If C >= 8 or C < 12end if > out2 = 1 > end if > > If C >= 12 or C < 16 then > out3 = 1 > end if > end if > > > The student can add/correct the syntax > > > Andy Thanks Andy, trying to work on the syntax for now. Is there a way I can combine this system with another system before writing a test bench for it. If you dont mind, I can send you a personal email. From newsfish@newsfish Thu Aug 1 00:32:13 2024 X-Received: by 10.236.22.71 with SMTP id s47mr1280331yhs.7.1420296652079; Sat, 03 Jan 2015 06:50:52 -0800 (PST) X-Received: by 10.140.84.103 with SMTP id k94mr667880qgd.3.1420296652035; Sat, 03 Jan 2015 06:50:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dc16no3840180qab.1!news-out.google.com!n9ni77qai.0!nntp.google.com!bm13no2982635qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Jan 2015 06:50:51 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=196.46.245.126; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 196.46.245.126 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1948d48f-320b-4111-828c-bf2fa62229cf@googlegroups.com> Subject: Re: Finding the difference between two numbers From: Olalekan Shittu Injection-Date: Sat, 03 Jan 2015 14:50:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3521 Hello Mike, Can you help with an architecture for the below entity and conditions. Thanks Library ieee; use IEEE.std_logic_1164.all; entity Sorter IS Port ( C: IN std_logic_vector (0 to 3); Sel: IN STD_LOGIC_VECTOR(0 to 2); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic ); end sorter; I am to write an architecture for the above with condition that: When Sel equal 4, the resulting output as shown in the table below is generated out0 out1 out2 out3 0 <= C < 4 1 0 0 0 4 <= C < 8 0 1 0 0 8 <= C < 12 0 0 1 0 12 <= C < 16 0 0 0 1 otherwise out0,out1,out2,out3 are all equal to zero. Thanks From newsfish@newsfish Thu Aug 1 00:32:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Initializing Large Arrays Date: Mon, 05 Jan 2015 12:11:27 -0500 Organization: A noiseless patient Spider Lines: 12 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 5 Jan 2015 17:11:17 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="17667"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qD1wwzp/KBzqX1OC/zioj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 Cancel-Lock: sha1:TxKXwqqhpZSEq0q3gLPjP6iLFT0= Xref: news.eternal-september.org comp.lang.vhdl:3522 I have some large arrays to initialize from a function call. This is a ROM table containing integer values derived from trig functions. I'm thinking the best way is to use a process on startup that will step through the table elements invoking the function to generate the data. The only variable input to the function is the index although there may be scaling constants as well to make the function more general purpose. Any other suggestions? -- Rick From newsfish@newsfish Thu Aug 1 00:32:14 2024 X-Received: by 10.50.78.136 with SMTP id b8mr11322877igx.4.1420479865061; Mon, 05 Jan 2015 09:44:25 -0800 (PST) X-Received: by 10.140.23.50 with SMTP id 47mr19717qgo.27.1420479865024; Mon, 05 Jan 2015 09:44:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no36699607igd.0!news-out.google.com!n9ni76qai.0!nntp.google.com!dc16no4280903qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Jan 2015 09:44:24 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8fe83954-e8b5-40e7-9fd1-8bf636ff51c9@googlegroups.com> Subject: Re: Initializing Large Arrays From: KJ Injection-Date: Mon, 05 Jan 2015 17:44:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3523 On Monday, January 5, 2015 12:11:46 PM UTC-5, rickman wrote: > I have some large arrays to initialize from a function call. This is a= =20 > ROM table containing integer values derived from trig functions. I'm=20 > thinking the best way is to use a process on startup that will step=20 > through the table elements invoking the function to generate the data.=20 > The only variable input to the function is the index although there may= =20 > be scaling constants as well to make the function more general purpose. >=20 > Any other suggestions? >=20 If this is meant to be synthesizable, then you will also need another funct= ion that loops through the entire index range to generate the entire table = so that the whole thing can then be assigned to a constant integer array. = Even if it does not need to be synthesized, I still tend to like this metho= d of having a function generate the entire table. A function(s) can simply= be reused directly, whereas using a process to call a function involves co= py/paste when reusing. Kevin From newsfish@newsfish Thu Aug 1 00:32:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Initializing Large Arrays Date: Mon, 5 Jan 2015 10:04:22 -0800 Organization: Highland Technology, Inc. Lines: 43 Message-ID: <20150105100422.267aa57d@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="00c0529b11392f77bf1ca106a3de87ed"; logging-data="22628"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18scETh5Fzo8uesG1wof6gX" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:gF9VZ3kaLwGOyNWsHKIdf2a7GaM= Xref: news.eternal-september.org comp.lang.vhdl:3524 On Mon, 05 Jan 2015 12:11:27 -0500 rickman wrote: > I have some large arrays to initialize from a function call. This is a > ROM table containing integer values derived from trig functions. I'm > thinking the best way is to use a process on startup that will step > through the table elements invoking the function to generate the data. > The only variable input to the function is the index although there may > be scaling constants as well to make the function more general purpose. > > Any other suggestions? > > -- > > Rick Something like the following? (Note, this is all in the architecture declaration bit, not the bit with the processes). type RAM is array (INT_MAX_ADDR downto 0) of std_logic_vector(15 downto 0); -- Function to initialize the RAM to a sinewave impure function SetTable return RAM is variable count : integer; variable phase : real; variable sinx : real; variable nextval : integer; variable data : RAM; begin for count in 0 to INT_MAX_ADDR loop phase := REAL(count * 2) * MATH_PI / REAL(INT_MAX_ADDR); sinx := SIN(phase) * 32767.0; nextval := INTEGER(ROUND(sinx)); data(count) := STD_LOGIC_VECTOR(TO_SIGNED(nextval, 16)); end loop; return data; end function; signal internal_data : RAM := SetTable; -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:32:14 2024 X-Received: by 10.182.65.227 with SMTP id a3mr9648412obt.2.1420517163844; Mon, 05 Jan 2015 20:06:03 -0800 (PST) X-Received: by 10.50.110.101 with SMTP id hz5mr208189igb.6.1420517163762; Mon, 05 Jan 2015 20:06:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no161916igd.0!news-out.google.com!h6ni6igv.0!nntp.google.com!h15no84983igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Jan 2015 20:06:03 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=163.180.171.34; posting-account=4Z7noQoAAACvo8dN9s9CMQogvE7lEACd NNTP-Posting-Host: 163.180.171.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <18ea7387-fb8b-4cf0-9ff6-2923c7f3982a@googlegroups.com> Subject: what is the reason of this error?? From: Youjung Hong Injection-Date: Tue, 06 Jan 2015 04:06:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3525 I am making eeprom on Actel A3PE3000 board. when I place and route ports, I got this errors. I don't know what is the reason. Here is the error report. ***** Layout Variables ********************************************* Mode: TIMING_DRIVEN Power-driven Layout: OFF Incremental Placement: OFF Incremental Route: OFF Running I/O Bank Assigner. I/O Bank Assigner completed successfully. Planning global net placement... Error: PLC004: No legal global assignment could be found. Some global nets have shared instances, requiring them to be assigned to overlapping global regions. Global Nets Whose Drivers Are Limited to Quadrants or Which Have No Valid Locations: |--------------------------------------------| |Global Net |Valid Driver Locations | |--------------------------------------------| |CLK_c |(None) |--------------------------------------------| |RST_c |(None) |--------------------------------------------| Info: Consider relaxing the constraints for these nets by removing region constraints, unassigning fixed cells and I/Os, relaxing I/O bank assignments, or using input buffers without hardwired pad connections. Error: PLC003: No legal global assignment could be found because of complex region and/or IO technology constraints. Error: PLC005: Automatic global net placement failed. INFO: See the GlobalNet Report from the Reports option of the Tools menu for information about the global assignment. The Layout command failed ( 00:00:01 ) The Layout command failed ( 00:00:02 ) Error: Failure when executing Tcl script. [ Line 18 ] The Execute Script command failed ( 00:00:05 ) Warning: The database was closed without a save, modifications are lost Design closed. From newsfish@newsfish Thu Aug 1 00:32:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: what is the reason of this error?? Date: Tue, 6 Jan 2015 13:48:34 +0000 (UTC) Organization: A noiseless patient Spider Lines: 60 Message-ID: References: <18ea7387-fb8b-4cf0-9ff6-2923c7f3982a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 6 Jan 2015 13:48:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="4557"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18YrU3r09PlF62eb+0TyAkVKyh4uJ5BHVc=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:DWO/FopdOEINci8inJwSPhTx/PE= Xref: news.eternal-september.org comp.lang.vhdl:3526 On Mon, 05 Jan 2015 20:06:03 -0800, Youjung Hong wrote: > I am making eeprom on Actel A3PE3000 board. > when I place and route ports, I got this errors. > I don't know what is the reason. > > Here is the error report. > > ***** Layout Variables ********************************************* > > Mode: TIMING_DRIVEN Power-driven Layout: OFF Incremental Placement: OFF > Incremental Route: OFF > > > > Running I/O Bank Assigner. > > I/O Bank Assigner completed successfully. > > > Planning global net placement... > Error: PLC004: No legal global assignment could be found. I hope you haven't laid out the PCB yet. > > |--------------------------------------------| > |Global Net |Valid Driver Locations | > |--------------------------------------------| > |CLK_c |(None) > |--------------------------------------------| > |RST_c |(None) > |--------------------------------------------| > Your pin assignment is incorrect. While you have apparently assigned CLK_c and RST_c to "global" pins, that is not good enough, because, incredibly, "global" pins are not actually global. You need "chip global" pins as opposed to the "quadrant global" pins you are apparently using now (which the name implies can only access 1/4 of the device). This unique interpretation of the word "global" nearly caught me out too ... fortunately I mistrust the tools enough to have insisted on a PAR run before board layout... The data sheet I'm looking at says (section 3-2), User Pins "All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. " and "All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals" Unfortunately this seems to contradict itself, probably a cut&paste error, and I can't be bothered to find another datasheet. But it means you have to select pins named (probably) GCnn or GFnn to get truly global clock and reset signals. - Brian From newsfish@newsfish Thu Aug 1 00:32:15 2024 X-Received: by 10.236.45.68 with SMTP id o44mr11335749yhb.51.1420808941766; Fri, 09 Jan 2015 05:09:01 -0800 (PST) X-Received: by 10.140.109.162 with SMTP id l31mr4546qgf.22.1420808941649; Fri, 09 Jan 2015 05:09:01 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1984933igd.0!news-out.google.com!qk8ni1868igc.0!nntp.google.com!h15no1984925igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jan 2015 05:09:01 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.176.1.84; posting-account=-qULwgoAAADJOPTEj_v8bQ7RHRQyCpyP NNTP-Posting-Host: 192.176.1.84 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Subject: Learning VHDL beyond basics From: johan.falkenstrom@gmail.com Injection-Date: Fri, 09 Jan 2015 13:09:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3527 a month ago I decided that I was lacking FPGA knowhow, said and done I orde= red an experiment board (beeing an opensource aficionado I ordered the Logi= cStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's "= The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Exampl= es: Spartan 3". My reasoning behind these two books is that I start with As= henden to learn the whole language then go to Pong to learn how to write sy= ntezisable VHDL, since both contain exercises they make for really good sel= f teaching material. I know Pong is targeting another experiment board but = it's the same FPGA and im very confident I can myself make adjustments, exc= ept for e.g. the PS2 port which my papilio thankfully does not have. I have now started to search for what to do after these books, how do I get= more advanced in my FPGA knowledge. I'm a software guy and if I got the qu= estion "I want to start programming" from someone new to programming I woul= d recomend a good starting book in python, then a good book on how to do te= st driven design, then a book about patterns, then moving to C followed by = a book about object oriented design, then perhaps going for a best practice= book and so on, by level of complexity and relevance. I have scoured the i= nternet (or feels like it) to find such a list regarding FPGA, but at no lu= ck so far, so thinking of posting the question here. I have looked at three books for continued learning after I'm finished with= Pong Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aimed= at explaining deeper the differences beetwen syntezisable and simulated VH= DL. Though it seem to go through the VHDL language constructs yet again per= haps it is too much overlapping with Pong and Ashenden Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; seem= s a good continuation, I understand that FSM is a very important topic in H= W world and that they are completely different from SW FSM, also it seem to= have excersises after each chapter which is good. Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portabili= ty, and Scalability ; seems good, no more comments. Thats my thinking, any suggestions or comments? Have not come about any boo= ks regarding FPGA testing? Perhaps I should look outside the more hands on = book to one of the "meta" books out there? From newsfish@newsfish Thu Aug 1 00:32:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Fri, 09 Jan 2015 12:43:17 -0500 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 9 Jan 2015 17:43:09 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="131d71abdca206f852e85f753b3a8167"; logging-data="29838"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CGhm/9sHRQwyd6iJ8HX7i" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Cancel-Lock: sha1:8FIYzB72hp+Gtlx183kpxai7Jhg= Xref: news.eternal-september.org comp.lang.vhdl:3528 On 1/9/2015 8:09 AM, johan.falkenstrom@gmail.com wrote: > a month ago I decided that I was lacking FPGA knowhow, said and done I ordered an experiment board (beeing an opensource aficionado I ordered the LogicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Examples: Spartan 3". My reasoning behind these two books is that I start with Ashenden to learn the whole language then go to Pong to learn how to write syntezisable VHDL, since both contain exercises they make for really good self teaching material. I know Pong is targeting another experiment board but it's the same FPGA and im very confident I can myself make adjustments, except for e.g. the PS2 port which my papilio thankfully does not have. > > I have now started to search for what to do after these books, how do I get more advanced in my FPGA knowledge. I'm a software guy and if I got the question "I want to start programming" from someone new to programming I would recomend a good starting book in python, then a good book on how to do test driven design, then a book about patterns, then moving to C followed by a book about object oriented design, then perhaps going for a best practice book and so on, by level of complexity and relevance. I have scoured the internet (or feels like it) to find such a list regarding FPGA, but at no luck so far, so thinking of posting the question here. > > I have looked at three books for continued learning after I'm finished with Pong > > Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aimed at explaining deeper the differences beetwen syntezisable and simulated VHDL. Though it seem to go through the VHDL language constructs yet again perhaps it is too much overlapping with Pong and Ashenden > > Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; seems a good continuation, I understand that FSM is a very important topic in HW world and that they are completely different from SW FSM, also it seem to have excersises after each chapter which is good. > > Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability ; seems good, no more comments. > > Thats my thinking, any suggestions or comments? Have not come about any books regarding FPGA testing? Perhaps I should look outside the more hands on book to one of the "meta" books out there? I don't think I ever read HDL books to learn higher level ideas. I read them to learn the basics. Oddly enough every one had a rather different approach to teaching what I think is very simple and straightforward really. Still, they got me over the hump and on the road to teaching myself. I learned FSMs in school and never felt the need to worry with how others write FSM code. I also tossed most of what I learned about FSMs actually. The whole Mealy/Moore thing is not so valuable when coding them up in HDL. I don't think any of my FSM designs are purely either now. It was a useful concept to learn about FSMs, but not so useful in practice. The Pong Chu book may be useful, at least it sounds good. I have to wonder if it is better than reading the app notes from the FPGA vendors. All HDL compilers are a little different and of course the chip architectures are also different. So how can one book be applicable to all? There is a standard for synthesis which I suppose is what he covers. I suggest you look more toward the vendors for info on how to use their tools. To me that is the bottom line. After all, in FPGAland there is no way to completely avoid the vendor tools. -- Rick From newsfish@newsfish Thu Aug 1 00:32:16 2024 X-Received: by 10.66.150.33 with SMTP id uf1mr568377pab.33.1420828763212; Fri, 09 Jan 2015 10:39:23 -0800 (PST) X-Received: by 10.140.96.202 with SMTP id k68mr26852qge.24.1420828763012; Fri, 09 Jan 2015 10:39:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no1648916igd.0!news-out.google.com!qk8ni2672igc.0!nntp.google.com!f12no32649qad.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jan 2015 10:39:22 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2e3c382c-eba0-4c5e-9a4e-4d29d7893231@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: Lars Asplund Injection-Date: Fri, 09 Jan 2015 18:39:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 9 Xref: news.eternal-september.org comp.lang.vhdl:3529 If you have a software and TDD background I would recommend a look at VUnit= , an open-source unit testing framework for VHDL, which we just released on= GitHub (https://github.com/LarsAsplund/vunit). It will let you work with T= DD in a way that you are used to. I'm just about to add more introduction material on YouTube so make sure to= follow the project and sign up for the referenced YouTube channel if you'r= e interested. Lars From newsfish@newsfish Thu Aug 1 00:32:16 2024 X-Received: by 10.236.4.194 with SMTP id 42mr12717242yhj.24.1420836787845; Fri, 09 Jan 2015 12:53:07 -0800 (PST) X-Received: by 10.182.219.13 with SMTP id pk13mr16645obc.39.1420836787387; Fri, 09 Jan 2015 12:53:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f12no60083qad.0!news-out.google.com!qk8ni2634igc.0!nntp.google.com!h15no2306664igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jan 2015 12:53:07 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=12.251.154.34; posting-account=w728HAoAAAAF2xrMb6mkfbhZUlYwqJjV NNTP-Posting-Host: 12.251.154.34 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: KKoorndyk Injection-Date: Fri, 09 Jan 2015 20:53:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2979 X-Received-Body-CRC: 1123848707 Xref: news.eternal-september.org comp.lang.vhdl:3530 The Ashenden book is a great reference but may be a bit difficult to sit an= d read cover to cover to learn the language. I assume you bought the 3rd e= dition, right? A lot of examples early in the book are fine for models and= learning the language, but are not synthesizable. Pay particular attentio= n to the new Design for Synthesis chapter (21). =20 Along the lines of rickman's suggestion, I would *HIGHLY* recommend that yo= u read the synthesis guides for Altera Quartus II and Xilinx's XST and Viva= do Synthesis. They'll provide guidance on what constructs are supported. = =20 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.= pdf http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-v= ivado-synthesis.pdf I would also recommend reading Xilinx's UltraFast Design Methodology Guide.= It is obviously heavily geared towards the Vivado tool suite, but it also= contains a lot of best practices. http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-= methodology.pdf You might also consider an on-demand college course like the one mentioned = on this page: http://dangerousprototypes.com/2013/03/09/cornell-online-courses-designing-= with-microcontrollers-and-fpgas/ Altera also offers quite a few free, on-demand training "courses", but they= 're a little light on quality content. Xilinx also has several videos: http://www.xilinx.com/training/free-video-courses.htm#FPGA Doulos has some good, free material on their site: http://www.doulos.com/kn= owhow/vhdl_designers_guide/ Check out OpenCores.org. There are a ton of open modules that you can lear= n from reviewing, but be careful - some are garbage. There's also some material on the EETimes Programmable Logic Designline blo= g. From newsfish@newsfish Thu Aug 1 00:32:16 2024 X-Received: by 10.182.143.34 with SMTP id sb2mr13071421obb.27.1420836961761; Fri, 09 Jan 2015 12:56:01 -0800 (PST) X-Received: by 10.140.30.118 with SMTP id c109mr50671qgc.15.1420836961536; Fri, 09 Jan 2015 12:56:01 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no1699392igd.0!news-out.google.com!qk8ni2672igc.0!nntp.google.com!f12no60952qad.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jan 2015 12:56:01 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=190.247.132.79; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 190.247.132.79 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07812bd8-20af-4ce5-9f7a-7bd9ca8caa94@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: Leonardo Capossio Injection-Date: Fri, 09 Jan 2015 20:56:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2547 X-Received-Body-CRC: 3881391190 Xref: news.eternal-september.org comp.lang.vhdl:3531 It is difficult to say, since advanced stuff this days is mostly done by ex= perience and reading other peoples code/papers. Also...remember that actually VHDL is a low level language, and what you ac= tually have to get knowledge about is hardware architectures (or digital de= sign in general). Get into some project, set some goal, when the need arise= s search for more specific knowledge. There is possible exception, if you only want to do verification (usually a= ttributed to be a pure-software task), then I would advise to get some veri= fication book I don't know about, but I do know that if you are going to be= using VHDL the most advanced verification can be done with OSVVM (search i= t). Otherwise SystemVerilog is what you are looking for. But advanced verif= ication is most well suited to ASICs, in FPGA sometimes it doesn't make sen= s because you can prototype quickly. I could recommend Altera Cookbook for learning a couple of synthesis tricks= (search, it is free downloadable, but it is mostly in Verilog). Then for D= igital Design I recommend Wakerly (Digital Design: Principles and Practices= ), it is one the most comprehensible and cool books that I have found (and = also detailed). Also I recommend a The Design Warrior's Guide to FPGA, as a= general FPGA knowledge book. Good luck and welcome to the FPGA world! From newsfish@newsfish Thu Aug 1 00:32:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Fri, 9 Jan 2015 15:22:03 -0800 Organization: Highland Technology, Inc. Lines: 19 Message-ID: <20150109152203.61d253d8@rg.highlandtechnology.com> References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="00c0529b11392f77bf1ca106a3de87ed"; logging-data="18267"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+9H5cCEhZmPZFsm6g1Q8al" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:Xviv774AJjpSg0PB9F+2VBY5VjE= Xref: news.eternal-september.org comp.lang.vhdl:3532 On Fri, 9 Jan 2015 12:53:07 -0800 (PST) KKoorndyk wrote: > The Ashenden book is a great reference but may be a bit difficult to sit and read cover to cover to learn the language. I assume you bought the 3rd edition, right? A lot of examples early in the book are fine for models and learning the language, but are not synthesizable. Pay particular attention to the new Design for Synthesis chapter (21). > > Along the lines of rickman's suggestion, I would *HIGHLY* recommend that you read the synthesis guides for Altera Quartus II and Xilinx's XST and Vivado Synthesis. They'll provide guidance on what constructs are supported. > http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf > http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf > Wow. Just flipped through the Vivado Synthesis guide. It's all still recommending you use std_logic_arith/std_logic_unsigned. There's no mention of numeric_std at all, let along the VHDL-2008 packages. This is why we can't have nice things. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:32:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Fri, 9 Jan 2015 15:39:09 -0800 Organization: Highland Technology, Inc. Lines: 29 Message-ID: <20150109153909.0a7f8ef9@rg.highlandtechnology.com> References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="00c0529b11392f77bf1ca106a3de87ed"; logging-data="18267"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Qaap5N4s5lCDJjbe76UgA" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:bp7wTaJEVu3E8ZoAYTgg2CJzepg= Xref: news.eternal-september.org comp.lang.vhdl:3533 On Fri, 9 Jan 2015 15:22:03 -0800 Rob Gaddi wrote: > On Fri, 9 Jan 2015 12:53:07 -0800 (PST) > KKoorndyk wrote: > > > The Ashenden book is a great reference but may be a bit difficult to sit and read cover to cover to learn the language. I assume you bought the 3rd edition, right? A lot of examples early in the book are fine for models and learning the language, but are not synthesizable. Pay particular attention to the new Design for Synthesis chapter (21). > > > > Along the lines of rickman's suggestion, I would *HIGHLY* recommend that you read the synthesis guides for Altera Quartus II and Xilinx's XST and Vivado Synthesis. They'll provide guidance on what constructs are supported. > > http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf > > http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf > > > > Wow. Just flipped through the Vivado Synthesis guide. It's all still > recommending you use std_logic_arith/std_logic_unsigned. There's no > mention of numeric_std at all, let along the VHDL-2008 packages. > > This is why we can't have nice things. Never mind. Finally made it all the way to the section on the IEEE packages for VHDL, where they do mention support for numeric_std, fixed_pkg, and float_pkg. The latter two are just shunted off into ieee_proposed. Good to see support for such things, even if all their design examples are still recommending packages that were deprecated in 1992. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:32:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Mon, 12 Jan 2015 11:31:44 +0100 Lines: 32 Message-ID: References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net RNm6W7HgwDPIZ2Qw53T3WAMuanBQ23Oo33q3PGS9ahyt92wvIz Cancel-Lock: sha1:0AUCGYYpsr4f8aVubziCxVW2ykw= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <20150109152203.61d253d8@rg.highlandtechnology.com> Xref: news.eternal-september.org comp.lang.vhdl:3534 Rob Gaddi wrote: > Wow. Just flipped through the Vivado Synthesis guide. It's all still > recommending you use std_logic_arith/std_logic_unsigned. There's no > mention of numeric_std at all, let along the VHDL-2008 packages. > > This is why we can't have nice things. Not only that, but all their examples and all of their cores use std_logic and std_logic_vector almost exclusively, instead of std_ulogic/std_ulogic_vector. That is not only useless, because the hardware doesn't really support it (what does a FF do with an 'X' input?), but more importantly it prevents detecting multiple driver errors early in the process (like right at the beginning during VHDL elaboration). I'd like to stick to std_ulogic in my designs, but it's a hassle to have to convert to std_logic every time I connect to a core or code snippet from them, sometimes needing intermediate signals just for the conversion (because no type conversions allowed in instantiations...). So in the end you can either have readable code or "safe" code. At the moment (at least up to Vivdao 2014.3) they have an issue in Vivado that causes them sometimes to not detect multiple drivers at all; but even if they do, you sometimes only get a "critical warning" that does not stop the flow and can be easily missed when you don't search the logs for it (or you can configure synthesis to promote that warning to an error). The only time you really get a multiple drivers error is at the very end during bitfile generation, so they let you waste hours with a completely useless synthesis/map/pnr run before issuing an error that should really occur before it starts synthesizing... Greetings, Sean From newsfish@newsfish Thu Aug 1 00:32:17 2024 X-Received: by 10.182.78.69 with SMTP id z5mr9604912obw.4.1421069035568; Mon, 12 Jan 2015 05:23:55 -0800 (PST) X-Received: by 10.182.219.200 with SMTP id pq8mr35384obc.6.1421069035283; Mon, 12 Jan 2015 05:23:55 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3844874igd.0!news-out.google.com!qk8ni2634igc.0!nntp.google.com!h15no3844844igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Jan 2015 05:23:55 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: KJ Injection-Date: Mon, 12 Jan 2015 13:23:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3535 On Monday, January 12, 2015 at 5:31:48 AM UTC-5, Sean Durkin wrote: > I'd like to stick to std_ulogic in my designs, but it's a hassle to have > to convert to std_logic every time I connect to a core or code snippet > from them, sometimes needing intermediate signals just for the > conversion (because no type conversions allowed in instantiations...). > So in the end you can either have readable code or "safe" code. >=20 No conversion is necessary between std_logic and std_ulogic; only between s= td_logic_vector and std_ulogic_vector. If your tools support VHDL-2008, yo= u don't even need to convert the vectors. If your tools do not support VHD= L-2008, you can put the type conversion right in the port map (both for inp= uts and outputs) so there is no need for intermediate signals. Example: My_Entity port map( std_logic_vector(some_slv) =3D> some_sulv, some_other_slv =3D> std_ulogic_vector(some_other_sulv)); Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Mon, 12 Jan 2015 16:25:31 +0100 Lines: 67 Message-ID: References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net Y4613/vfBqQkyKqaVLqfNAiMSLpyZMv2Uz28i1Kd6DPjUQrnyF Cancel-Lock: sha1:VEjgb/t2zhjtOCY7R7FSTm9QvtU= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:3536 KJ wrote: > On Monday, January 12, 2015 at 5:31:48 AM UTC-5, Sean Durkin wrote: > >> I'd like to stick to std_ulogic in my designs, but it's a hassle to >> have to convert to std_logic every time I connect to a core or code >> snippet from them, sometimes needing intermediate signals just for >> the conversion (because no type conversions allowed in >> instantiations...). So in the end you can either have readable code >> or "safe" code. >> > No conversion is necessary between std_logic and std_ulogic; only > between std_logic_vector and std_ulogic_vector. Correct, but that only messes things up further: you need a conversion for one signal and not for the other... Again, sucks for readability IMHO. > If your tools support VHDL-2008, you don't even need to convert the vectors. Well, Vivado has some very rudimentary support vor VHDL-2008, but not for that AFAIK. > If your tools do not support VHDL-2008, you can put the type conversion > right in the port map (both for inputs and outputs) so there is no > need for intermediate signals. > Example: My_Entity port map( > std_logic_vector(some_slv) => some_sulv, > some_other_slv => std_ulogic_vector(some_other_sulv)); Ah, OK, didn't know about the type conversion of the port (the second line in your example). I only tried converting the actual, which does not work for entity outputs (Vivado quits saying "output designator some_slv cannot contain an actual type-conversion"). Now that you say it, kinda makes sense to put the conversion at the "source", I just never had dared to use type conversions on the ports themselves, only on signals connected to ports. The entire std_ulogic-thing just seems to be utterly broken in Vivado. Even if there wasn't added hassle for conversions, it wouldn't help any, since Vivado synthesis doesn't catch multiple drivers in some cases, which for me is the main reason to use std_ulogic in the first place. Concurrent assignments like: sig <= some_other_sig; ... sig <= '0'; ... with "sig" being a std_ulogic do not produce an error; this produces a bitfile that simply does not work as expected, no warnings or errors in any of the logfiles. Modelsim or any other synthesis tool do not even compile that, which is what I'd expect. Interesting enough, the simulation tool that comes with Vivado does also not compile that, but the synthesis tool by the same vendor integrated in the same IDE does not seem to have a problem with it. It took a lot of complaining and week-long discussions until Xilinx even acknowledged that this is indeed a bug, and there's a CR for it now. Don't know when it will be fixed... I haven't tried the latest Vivado release though; it might be fixed now, but at least there's nothing in the release notes about this issue being addressed. I'm in release-freeze now and don't have half a day to spare to install and try out the new release. Anyway, to cut a long story short: - Xilinx still use std_logic_arith in almost all of their code - Xilinx still use std_logic in almost any case, even if std_ulogic would make a lot more sense IMHO Old habits really die hard... From newsfish@newsfish Thu Aug 1 00:32:18 2024 X-Received: by 10.236.202.207 with SMTP id d55mr1280703yho.4.1421197035085; Tue, 13 Jan 2015 16:57:15 -0800 (PST) X-Received: by 10.140.39.39 with SMTP id u36mr16208qgu.17.1421197035003; Tue, 13 Jan 2015 16:57:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!v8no809938qal.1!news-out.google.com!n9ni488qai.0!nntp.google.com!bm13no292047qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Jan 2015 16:57:14 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.4.87.209; posting-account=Uk0pMgoAAADu6ZbtaHLSUFljg_8C_HaD NNTP-Posting-Host: 94.4.87.209 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> Subject: compare std_logic_vector to a constant using std_logic_vector package ONLY,possible? From: KM23 Injection-Date: Wed, 14 Jan 2015 00:57:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 15 Xref: news.eternal-september.org comp.lang.vhdl:3537 Hi, I use the following package only in my vhdl file: library IEEE; use IEEE.STD_LOGIC_1164.ALL; In the code, i compare an std_logic_vector signal : A with a constant value= , e.g ...if A<=3D"00001011" then yet the code was checked correctly by Xilinx ISE. My understanding is that = STD_LOGIC_1164 package does not include an implementation of inequalities h= aving as an operand std_logic_vector so why the above code statement was ac= cepted and will the above comparison treat A as signed or unsigned number? Cheers From newsfish@newsfish Thu Aug 1 00:32:18 2024 X-Received: by 10.68.224.5 with SMTP id qy5mr3534024pbc.7.1421249584172; Wed, 14 Jan 2015 07:33:04 -0800 (PST) X-Received: by 10.140.95.182 with SMTP id i51mr18246qge.12.1421249583912; Wed, 14 Jan 2015 07:33:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no5141849igd.0!news-out.google.com!ik4ni254qab.1!nntp.google.com!v8no928309qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Jan 2015 07:33:03 -0800 (PST) In-Reply-To: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7576a42f-3a97-406a-a67e-a0cafb8c5779@googlegroups.com> Subject: Re: compare std_logic_vector to a constant using std_logic_vector package ONLY,possible? From: Thomas Stanka Injection-Date: Wed, 14 Jan 2015 15:33:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2110 X-Received-Body-CRC: 1904466646 Xref: news.eternal-september.org comp.lang.vhdl:3538 Am Mittwoch, 14. Januar 2015 01:57:16 UTC+1 schrieb KM23: > use IEEE.STD_LOGIC_1164.ALL; [..] > ...if A<=3D"00001011" then Std_ulogic_vector means your signal A is an arbitrary collection of single = bits without further meaning, than beeing a collection of 8 bits (eg. the s= tatus signals of 8 one bit inputs collected). If you like to compare a collection of bits with an string containing bits = the operation "=3D" is well defined. The operation ">" and "<" can only mea= n has more or less bits.=20 If you want to compare if A <=3D "101" you need to define if "101" is a col= lection of bits and you like to know if A has no more than 3 bits, or if y= ou like to see if A<=3D5 or A<=3D-3. This can only be achieved by declaring= explicite, that A is signed or unsigned instead of arbitrary bit collectio= n. This is usually done with numeric_std package. From newsfish@newsfish Thu Aug 1 00:32:19 2024 X-Received: by 10.43.99.202 with SMTP id ct10mr5763276icc.29.1421268637144; Wed, 14 Jan 2015 12:50:37 -0800 (PST) X-Received: by 10.50.7.100 with SMTP id i4mr126279iga.11.1421268637064; Wed, 14 Jan 2015 12:50:37 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!209.85.213.215.MISMATCH!h15no3401587igd.0!news-out.google.com!qk8ni6628igc.0!nntp.google.com!h15no5313653igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Jan 2015 12:50:36 -0800 (PST) In-Reply-To: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: compare std_logic_vector to a constant using std_logic_vector package ONLY,possible? From: Jim Lewis Injection-Date: Wed, 14 Jan 2015 20:50:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3539 > ...if A<=3D"00001011" then All enumerated types and arrays of enumerated types implicitly define the r= egular ordering relational operators (>, >=3D, <, <=3D). Unfortunately it = is not numerically ordered, so the results may not be as expected. Instead= it is dictionary ordered.=20 First you have to look at the element type, which is std_logic whose base t= ype is std_ulogic. For an enumerated type, such as std_ulogic, left values= are less than right values, hence, for std_ulogic (and std_logic): 'U' < 'X' < '0' < '1' < 'Z' < 'W' < 'L' < 'H' < '-' For equal length arrays whose element base type is std_ulogic (such as std_= logic_vector or std_ulogic_vector) whose values are only 0 or 1, things wor= k out fine: "1010" > "0101" Note that dictionary comparisons always compare the left element first. He= nce, for string, something that starts with 'S' is always less than somethi= ng that starts with 'T' independent of length. This is great for sorting s= trings into a dictionary and is the only practical default - if we are goin= g to provide such as thing. OTOH, this is not so great if you are thinking things are numeric. For exa= mple, if the arrays are not equal length, then the following is true becaus= e the leading '1'on the left parameter is > the leading '0' of the right pa= rameter. =20 "100" > "0111" Hence, with only "use ieee.std_logic_1164.all", you have potential exposure= to bad coding practices that mistakenly think of std_logic_vector as numer= ic (such as unsigned). =20 Many will argue, never use std_logic_vector for math and ">" is math. I ge= nerally agree. So what do I do? How do I protect my design and design team from this. Fi= rst you have to decide a policy and how to implement it.=20 1) Forbid use of regular ordering relational operators (>, >=3D, <, <=3D) w= ith std_logic_vector and enforce it with a lint tool. However this means y= ou have to buy and require the use of a lint tool. 2) Forbid use of regular ordering relational operators (>, >=3D, <, <=3D) w= ith std_logic_vector and enforce it by using the both of the following pack= age references. Note that this generates errors by referencing two definit= ions for each of the operators, and hence, when used the expression becomes= ambiguous. Note this may be problematic since numeric_std_unsigned was in= troduced in 1076-2008 and it may not yet be supported by your synthesis too= ls. =20 library ieee ;=20 use ieee.numeric_std_unsigned.all ;=20 use ieee.std_logic_unsigned.all ; 3) Relax the rules some. Our biggest concern is design correctness. Allow= std_logic_vector to be interpreted as an unsigned value and either referen= ce numeric_std_unsigned (preferred, but it is VHDL-2008 and may not be impl= emented by your synthesis tool yet - but if it is not be sure to submit a b= ug report) or std_logic_unsigned (not preferred - this is an old shareware = package that is not an IEEE standard and perhaps does not belong in the IEE= E library - OTOH, it is well supported and it plays nice with other package= s - such as numeric_std). =20 The nice result of this is that it also allows comparisons that include int= egers: if A <=3D 11 then=20 Note, some suggest that the overloading of ">" and friends in numeric_std_u= nsigned/std_logic_unsigned is illegal. This was a very conservative interp= retation of 1076 prior to VHDL-2008. It was fixed for all revisions of VHD= L with an ISAC resolution prior to VHDL-2008 that determined that explicitl= y defined operators always overload implicitly defined operators without cr= eating any ambiguity. I note that even the VHDL FAQ is out of date on this = issue.=20 4) Be formal, but practical. Never use std_logic_vector. Only use numeric= types, such as unsigned and signed from package ieee.numeric_std. Types s= igned and unsigned also support comparisons with integers. There are probably a few strategies I left out. =20 Note that VHDL-2008 introduces matching operators which also address this i= ssue by not defining them for types that do not have a numeric interpretati= on. These operators are: ?=3D, ?/=3D, ?>, ?>=3D, ?<, ?<=3D Best Regards, Jim Lewis IEEE 1076 WG Member (among other things) From newsfish@newsfish Thu Aug 1 00:32:19 2024 X-Received: by 10.70.13.161 with SMTP id i1mr8694752pdc.3.1421347743306; Thu, 15 Jan 2015 10:49:03 -0800 (PST) X-Received: by 10.182.230.133 with SMTP id sy5mr97997obc.1.1421347743173; Thu, 15 Jan 2015 10:49:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no5925470igd.0!news-out.google.com!db6ni86igc.0!nntp.google.com!h15no3804604igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Jan 2015 10:49:03 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: Andy Injection-Date: Thu, 15 Jan 2015 18:49:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3540 VHDL-2008 redefines std_logic_vector as a resolved subtype of std_ulogic_ve= ctor, using a new syntax that effectively applies the scalar resolution fun= ction to each bit (meaning each bit is also resolved), so they are now inte= rchangeable.=20 Whether or not multiple drivers are allowed is dependent on the type/subtyp= e of the object being driven. So now, you can declare your signals/ports as= SULV and connect to IP with SLV ports just fine, with no port conversions = or any other syntactic gymnastics. I do not know whether Xilinx Vivado supports this yet. If not, open a bug f= or it. This is how we get what we want. There are other (better) synthesis = tools available (Synplify & Precision are two), and it doesn't hurt to remi= nd Xilinx of that fact. Andy From newsfish@newsfish Thu Aug 1 00:32:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Thu, 15 Jan 2015 10:54:45 -0800 Organization: Highland Technology, Inc. Lines: 23 Message-ID: <20150115105445.75ba3f19@rg.highlandtechnology.com> References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="00c0529b11392f77bf1ca106a3de87ed"; logging-data="23176"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IbbcfoPdbOP3CcSxt2l9k" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:TRIY+hUrQhCisOHWacEExkrPEiY= Xref: news.eternal-september.org comp.lang.vhdl:3541 On Thu, 15 Jan 2015 10:49:03 -0800 (PST) Andy wrote: > VHDL-2008 redefines std_logic_vector as a resolved subtype of std_ulogic_vector, using a new syntax that effectively applies the scalar resolution function to each bit (meaning each bit is also resolved), so they are now interchangeable. > > Whether or not multiple drivers are allowed is dependent on the type/subtype of the object being driven. So now, you can declare your signals/ports as SULV and connect to IP with SLV ports just fine, with no port conversions or any other syntactic gymnastics. > > I do not know whether Xilinx Vivado supports this yet. If not, open a bug for it. This is how we get what we want. There are other (better) synthesis tools available (Synplify & Precision are two), and it doesn't hurt to remind Xilinx of that fact. > > Andy The problem is that threat lacks credibility. Xilinx doesn't give a damn whether you don't want to use their software to do synthesis so long as you're going to buy their silicon to put it on. The software is almost certainly a money loser, even with their preposterous and short-sighted efforts to squeeze money out of you for the right to use their chips. Not that Altera's more than fractionally better, mind. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:32:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Mon, 19 Jan 2015 11:52:09 +0100 Lines: 23 Message-ID: References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net aWZrqIGeC1xPGAYKpGGxFQKKVvlkEXvw/cBlkb370ofpdeVuBX Cancel-Lock: sha1:DSBkj1ULzfMKs01imx048ZDaU5w= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:3542 Andy wrote: > I do not know whether Xilinx Vivado supports this yet. If not, open a > bug for it. This is how we get what we want. There are other (better) > synthesis tools available (Synplify & Precision are two), and it > doesn't hurt to remind Xilinx of that fact. Well, it's getting increasingly difficult to open bugs. They used to have this WebCase thing on their website you could use, but that is now only available to premium customers. The rest has to go through the Xilinx user support forums and/or through the FAE that is usually totally swamped already. And, as I said before, going through the forum for me resulted in week-long discussions before they even ackowledged that there was indeed a problem there (A SULV with multiple drivers should result in an error no matter which VHDL standard is chosen...). So if it's that hard to get them recognize something that very clearly is a bug, how interested do you think they are in adding "nice to have" features that the majority of FPGA developers still doesn't even know about (sadly)? AFAIK, the rudimentary VHDL-2008-support they do have was requested by one of the big customers, the rest they don't really seem to care about... From newsfish@newsfish Thu Aug 1 00:32:20 2024 X-Received: by 10.236.28.102 with SMTP id f66mr2245541yha.31.1421815313883; Tue, 20 Jan 2015 20:41:53 -0800 (PST) X-Received: by 10.140.39.39 with SMTP id u36mr3859qgu.17.1421815313825; Tue, 20 Jan 2015 20:41:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!v8no2472845qal.1!news-out.google.com!l7ni0qai.0!nntp.google.com!bm13no1955319qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Jan 2015 20:41:53 -0800 (PST) In-Reply-To: <20150115105445.75ba3f19@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> <20150115105445.75ba3f19@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <63571c7d-10e7-47d5-86a9-28fded86747f@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: Andy Injection-Date: Wed, 21 Jan 2015 04:41:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:3543 Does anyone know that Vivado does not support this 2008 feature? Or do we simply assume not, and accept it like sheep? Vote with your next design-in. Andy From newsfish@newsfish Thu Aug 1 00:32:20 2024 X-Received: by 10.236.28.230 with SMTP id g66mr4922007yha.2.1421849663389; Wed, 21 Jan 2015 06:14:23 -0800 (PST) X-Received: by 10.182.153.66 with SMTP id ve2mr2167obb.40.1421849663148; Wed, 21 Jan 2015 06:14:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!bm13no2048278qab.0!news-out.google.com!db6ni4746igc.0!nntp.google.com!hl2no745460igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Jan 2015 06:14:22 -0800 (PST) In-Reply-To: <63571c7d-10e7-47d5-86a9-28fded86747f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=12.251.154.34; posting-account=w728HAoAAAAF2xrMb6mkfbhZUlYwqJjV NNTP-Posting-Host: 12.251.154.34 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> <20150115105445.75ba3f19@rg.highlandtechnology.com> <63571c7d-10e7-47d5-86a9-28fded86747f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: KKoorndyk Injection-Date: Wed, 21 Jan 2015 14:14:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3068 X-Received-Body-CRC: 3538559653 Xref: news.eternal-september.org comp.lang.vhdl:3544 On Tuesday, January 20, 2015 at 11:41:55 PM UTC-5, Andy wrote: > Does anyone know that Vivado does not support this 2008 feature? > > Or do we simply assume not, and accept it like sheep? > > Vote with your next design-in. > > Andy http://www.xilinx.com/support/answers/62005.html The supported language constructs are as follows: Feature Vivado Release Unconstrained Element Types 2014.3 Relational operators: ??, ?=, ?/=, ?>, ?>=, ?<, ?<= 2014.3 Maximum and Minimum 2014.3 shift operators 2014.3 bit_vector, boolean_vector, integer_vector and the predefined operators 2014.3 Strength Reduction Functions 2014.3 Unary reduction Operators (and,or,nand,nor,xor,xnor) 2014.3 Array Logic Operators 2014.3 Scalar Logic Operators 2014.3 If-else-if & Case Generate 2014.3 Sequential Signal Assignments 2014.3 Matching Select for Variables 2014.3 Matching Case for Variables 2014.3 Matching Select for Signals 2014.3 Matching Case for Signals 2014.3 Case? Statement 2014.3 Select? Statement 2014.3 Slices in aggregates 2014.3 Sized Bit String Literals 2014.3 Reading Output Ports 2014.3 Expressions in Port Maps 2014.3 Process(all) 2014.3 Referencing Generics in Generic Lists 2014.3 Relaxed return rules for Function Return Values 2014.3 Relaxed Qualified Expressions 2014.3 Type Conversions 2014.3 Extensions to globally static and locally static expressions 2014.3 Static Ranges and Integer expressions in range bounds 2014.3 Block Comments 2014.3 std_logic_1164/Numeric_bit/Numeric_std updates 2014.3 From newsfish@newsfish Thu Aug 1 00:32:21 2024 X-Received: by 10.236.11.193 with SMTP id 41mr1787545yhx.53.1421907304948; Wed, 21 Jan 2015 22:15:04 -0800 (PST) X-Received: by 10.51.15.133 with SMTP id fo5mr556276igd.3.1421907304738; Wed, 21 Jan 2015 22:15:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!bm13no2200035qab.0!news-out.google.com!db6ni5834igc.0!nntp.google.com!h15no1699509igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Jan 2015 22:15:04 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:7:1780:4ef:b9a0:bdba:7dfc:be59; posting-account=6q9j7QoAAABb1svNDLq2pkeRwQoxnxfP NNTP-Posting-Host: 2601:7:1780:4ef:b9a0:bdba:7dfc:be59 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Pulse Width detection in verilog? From: redgar@pdx.edu Injection-Date: Thu, 22 Jan 2015 06:15:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3545 I'm working on a project that requires me to detect the frequency and duty cycle of the PWM signal this is what i have so far but i have couple errors that i don't know how to fix: module low_high_count( input clk, input pwm0_signal, input reset_n, output [31:0] frequency, //embsus GPIO outputs count output [31:0] duty_cycle); //inter variables wire sysclk; wire sysreset_n; wire axi_timer_0_pwm0; wire [31:0] axi_gpio_1_duty_cycle; wire [31:0] axi_gpio_1_frequency; //local variables used for calcuation reg [31:0] hightime_count; reg [31:0] lowtime_count; reg [31:0] duty_cycle_calculation; reg [31:0] frequency_calculation; reg [31:0] period_calculation; reg [31:0] old_frequency; reg [31:0] old_duty_cycle; assign old_frequency =0; assign old_duty_cycle=0; //connect the ports-wires ("wire" = "verilog input/output") assign axi_timer_0_pwm0 = pwm0_signal; assign sysclk=clk; assign sysreset_n=reset_n; assign axi_gpio_1_frequency = frequency; assign axi_gpio_1_duty_cycle = duty_cycle; //counts, starting at the first positive edge, the hight time always @(posedge pwm0_signal ) if(!reset_n) begin hightime_count <= 32'd0 ; //resets positive clock count end else begin hightime_count <= hightime_count + 32'd1; //increment the count by 1 end always @(negedge pwm0_signal) if(!reset_n) begin lowtime_count <= 32'd0; //resets negative clock count end else begin lowtime_count <= lowtime_count + 32'd1; //increment the count by 1 end //duty cycle and frequency calculation assign period_calculation = (hightime_count + lowtime_count)/100000000; assign frequency_calculation = (1/period_calculation); assign duty_cycle_calculation = (hightime_count/(hightime_count + lowtime_count))*100; assign old_frequency = frequency_calculation; assign old_duty_cycle = duty_cycle_calculation; assign frequency = frequency_calculation; assign duty_cycle = duty_cycle_calculation; endmodule thank you so much edgar From newsfish@newsfish Thu Aug 1 00:32:21 2024 X-Received: by 10.236.17.197 with SMTP id j45mr763741yhj.35.1421930688228; Thu, 22 Jan 2015 04:44:48 -0800 (PST) X-Received: by 10.140.36.134 with SMTP id p6mr17150qgp.16.1421930688210; Thu, 22 Jan 2015 04:44:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!bm13no2259689qab.0!news-out.google.com!l7ni0qai.0!nntp.google.com!bm13no2259687qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Jan 2015 04:44:48 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77bbd3f3-50db-4dcd-83bc-b6287d8ebc75@googlegroups.com> Subject: Re: Pulse Width detection in verilog? From: Thomas Stanka Injection-Date: Thu, 22 Jan 2015 12:44:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 45 X-Received-Bytes: 2743 X-Received-Body-CRC: 2884996525 Xref: news.eternal-september.org comp.lang.vhdl:3546 Hello, there exists a group for verilog. YOu might get some answers concerning ver= ilog there. But the principle is the same in VHDL, so this post should stil= l help you. BTW your topic is somehow a FAQ, Google provides several sollut= ions to this problem. > module low_high_count( > input clk, > input pwm0_signal, > input reset_n, > output [31:0] frequency, //embsus GPIO outputs count > output [31:0] duty_cycle); > //counts, starting at the first positive edge, the hight time > always @(posedge pwm0_signal ) It is usually the wrong way to use the signal you like to measure as clock = signal in a process. What you like to do is to oversample the pwm signal with clk and measure ho= w many cycles of clk the signal pwm is high after a rising edge. Therefore you use best a two rank FF to bring the signal PWM stable in cloc= k domain of signal "clk" (avoid problems with clock domain crossing), use a= third ff for edge detection and measure the number of clock cycles the sig= nal in clk-clock domain is set high. In VHDL this would be: signal pwm_clk : std_ulogic_vector(1 downto 0); signal counter : integer range 0 to .....; process (clk, reset) if reset=3DACTIVE then pwm_clk <=3D (others=3D>'0'); counter <=3D 0; elsif rising_edge(clk) pwm_clk <=3D pwm_clk(1) & pwm0_signal; if pwm_clk(2 downto 1) =3D "01" then counter <=3D 0; elsif pwm_clk(2)=3D'1' then counter <=3D counter+1; end if; end if; From newsfish@newsfish Thu Aug 1 00:32:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer01.fr7!news.highwinds-media.com!post01.fr7!fx37.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: UVM for VHDL Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150128-0, 28/01/2015), Outbound message X-Antivirus-Status: Clean Lines: 13 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1422440924 86.17.210.161 (Wed, 28 Jan 2015 10:28:44 UTC) NNTP-Posting-Date: Wed, 28 Jan 2015 10:28:44 UTC Organization: virginmedia.com Date: Wed, 28 Jan 2015 10:28:43 +0000 X-Received-Body-CRC: 240998217 X-Received-Bytes: 1252 Xref: news.eternal-september.org comp.lang.vhdl:3547 For those who haven't seen it: http://bitvis.no/resources/presentations/uvvm/ Looks promising and IMHO hugely important for the VHDL community (even if you don't need it). With UVVM/OS-VVM/OVL/PSL and VHDL2008 I think we have a good tool set to tackle complex verification jobs. Regards, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:32:21 2024 X-Received: by 10.66.65.202 with SMTP id z10mr1212394pas.29.1422551944992; Thu, 29 Jan 2015 09:19:04 -0800 (PST) X-Received: by 10.140.108.166 with SMTP id j35mr27362qgf.18.1422551944940; Thu, 29 Jan 2015 09:19:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no4395453igb.0!news-out.google.com!q4ni24qan.0!nntp.google.com!v8no4342399qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 Jan 2015 09:19:04 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=84.212.255.208; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 84.212.255.208 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: UVM for VHDL From: espen.tallaksen@bitvis.no Injection-Date: Thu, 29 Jan 2015 17:19:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2215 X-Received-Body-CRC: 744020633 Xref: news.eternal-september.org comp.lang.vhdl:3548 onsdag 28. januar 2015 11.28.48 UTC+1 skrev HT-Lab f=F8lgende: > For those who haven't seen it: >=20 > http://bitvis.no/resources/presentations/uvvm/ >=20 > Looks promising and IMHO hugely important for the VHDL community (even=20 > if you don't need it). >=20 > With UVVM/OS-VVM/OVL/PSL and VHDL2008 I think we have a good tool set to= =20 > tackle complex verification jobs. >=20 > Regards, > Hans > www.ht-lab.com Thanks Hans, for the nice feedback. We plan to do the UVVM release in Q2 (May?) with a beta release in March. We will present an introduction to UVVM at FPGA-forum in February, and prob= ably publish the presentation not long after that. This will show what we w= ill implement in the first version that is focused on making a good verific= ation component system with a structured distribution of commands from the = sequencer to the verification components. This will allow both direct comma= nds and local sequencers - and an easily understandable way of controlling = the test cases. After that we will continue with more advanced features.=20 Best regards Espen www.bitvis.no From newsfish@newsfish Thu Aug 1 00:32:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-01.inet.qwest.net!216.166.98.85.MISMATCH!border2.nntp.dca1.giganews.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 29 Jan 2015 11:35:56 -0600 From: friendsa17 Subject: Re: Carry Save Adder (CSA) Verilog code Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 41488da0-fe9c-4b8d-ab6b-06cf7dcbe2b2 References: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> Message-ID: <8PKdnaDTBfnh8lfJnZ2dnUU7-VednZ2d@giganews.com> Date: Thu, 29 Jan 2015 11:35:56 -0600 Lines: 3 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-8zpaGya4FHmSlzIxey4qTzkNulz5735BeGzoNJC5liesHu1QWvYORZimhMuadsPY3xlbegIiDaOzCTA!y4wRKGdR70s/PXjct44E1aMrFVQcIgJi3jf+M0su/AA6b/JPwMdKUdIH/c7EAVidO9SImnD3jvXm!Y0Y= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1051 Xref: news.eternal-september.org comp.lang.vhdl:3549 sir, i need verilog coding for 16pt dif computation From newsfish@newsfish Thu Aug 1 00:32:22 2024 X-Received: by 10.67.1.100 with SMTP id bf4mr5349749pad.4.1422627570891; Fri, 30 Jan 2015 06:19:30 -0800 (PST) X-Received: by 10.140.16.55 with SMTP id 52mr81884qga.31.1422627570846; Fri, 30 Jan 2015 06:19:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no3745894igb.0!news-out.google.com!q4ni22qan.0!nntp.google.com!bm13no3998950qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Jan 2015 06:19:30 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.164.136.112; posting-account=r2yQngoAAABH6wHUUUDXnfZDWZunMbzu NNTP-Posting-Host: 146.164.136.112 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: FSM recurring state technique From: revkarol Injection-Date: Fri, 30 Jan 2015 14:19:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3550 Let's say I have an FSM such as the example on the Altera website. =20 This is a typical 4-state FSM in the Moore style.=20 Now, let's say I want a state where the inputs don't change but I want the = outputs to change (say, a counter output). For example, I want to get to s= tate s2 and when I do, I'll stay in state s2 for say 10 cycles and then exi= t to state s3. I'm not sure how to do this. Using the format of the examp= le below, because the state doesn't change, the output is latched. This seems like a standard problem, but I don't know the standard solution. Advance thanks, Karol. -- A Moore machine's outputs are dependent only on the current state. -- The output is written only when the state changes. (State -- transitions are synchronous.) library ieee; use ieee.std_logic_1164.all; entity moore_4s is port( clk : in std_logic; data_in : in std_logic; reset : in std_logic; data_out : out std_logic_vector(1 downto 0) ); =09 end entity; architecture rtl of moore_4s is -- Build an enumerated type for the state machine type state_type is (s0, s1, s2, s3); =09 -- Register to hold the current state signal state : state_type; begin -- Logic to advance to the next state process (clk, reset) begin if reset =3D '1' then state <=3D s0; elsif (rising_edge(clk)) then case state is when s0=3D> if data_in =3D '1' then state <=3D s1; else state <=3D s0; end if; when s1=3D> if data_in =3D '1' then state <=3D s2; =20 else state <=3D s1; end if; when s2=3D> if data_in =3D '1' then -- here I would have something like -- if counter > 10 then state <=3D s3; else state <=3D s2; end if; when s3 =3D> if data_in =3D '1' then state <=3D s0; else state <=3D s3; end if; end case; end if; end process; =09 -- Output depends solely on the current state process (state) begin =09 case state is when s0 =3D> data_out <=3D "00"; when s1 =3D> data_out <=3D "01"; when s2 =3D> data_out <=3D "10"; -- here I would have=20 data_out <=3D value depending on counter; when s3 =3D> data_out <=3D "11"; end case; end process; =09 end rtl; From newsfish@newsfish Thu Aug 1 00:32:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Date: Fri, 30 Jan 2015 11:10:41 -0500 Organization: Alacron, Inc. Lines: 126 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Jan 2015 16:12:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="27944"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+XCwOfMxMJSa3/xEY4K7DZASDEsdtblM=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:MFWG3Xs6sfSraEHofF2utUfLAmQ= Xref: news.eternal-september.org comp.lang.vhdl:3551 revkarol wrote: > Let's say I have an FSM such as the example on the Altera website. > This is a typical 4-state FSM in the Moore style. > > Now, let's say I want a state where the inputs don't change but I want the outputs to change (say, a counter output). For example, I want to get to state s2 and when I do, I'll stay in state s2 for say 10 cycles and then exit to state s3. I'm not sure how to do this. Using the format of the example below, because the state doesn't change, the output is latched. > > This seems like a standard problem, but I don't know the standard solution. > > > > Advance thanks, > Karol. > > > > > > -- A Moore machine's outputs are dependent only on the current state. > -- The output is written only when the state changes. (State > -- transitions are synchronous.) > > library ieee; > use ieee.std_logic_1164.all; > > entity moore_4s is > > port( > clk : in std_logic; > data_in : in std_logic; > reset : in std_logic; > data_out : out std_logic_vector(1 downto 0) > ); > > end entity; > > architecture rtl of moore_4s is > > -- Build an enumerated type for the state machine > type state_type is (s0, s1, s2, s3); > > -- Register to hold the current state > signal state : state_type; > > begin > -- Logic to advance to the next state > process (clk, reset) > begin > if reset = '1' then > state <= s0; > elsif (rising_edge(clk)) then > case state is > when s0=> > if data_in = '1' then > state <= s1; > else > state <= s0; > end if; > when s1=> > if data_in = '1' then > state <= s2; > > else > state <= s1; > end if; > when s2=> > if data_in = '1' then > -- here I would have something like > -- if counter > 10 then > state <= s3; > else > state <= s2; > end if; > when s3 => > if data_in = '1' then > state <= s0; > else > state <= s3; > end if; > end case; > end if; > end process; > > -- Output depends solely on the current state > process (state) > begin > > case state is > when s0 => > data_out <= "00"; > when s1 => > data_out <= "01"; > when s2 => > data_out <= "10"; > -- here I would have > data_out <= value depending on counter; > when s3 => > data_out <= "11"; > end case; > end process; > > end rtl; It's not hard to add "counter" as a ranged integer and then increment it while in state s2. Then the only other thing you need is to reset the counter before entering state s2. You can do this in several ways: 1) reset "counter" in all other states. 2) reset "counter" in states that can lead to s2. 3) reset "counter" in the transition terms (when assigning state <= s2 from another state). There are other ways to do this including building a timer "subroutine." I've used this is more complex FSM's where I needed a variable amount of time spent in a number of different states. In this case I have a state that just counts down on a counter until it reaches 0. States that need the delay will set up their outputs as required, set the delay value into the counter, store the "return state" in another signal of the same type as "state" and then set "state" to the wait state. When the counter is decremented to zero, the wait state then just assigns state to the return state. -- Gabor From newsfish@newsfish Thu Aug 1 00:32:23 2024 X-Received: by 10.68.57.175 with SMTP id j15mr5788169pbq.1.1422638538567; Fri, 30 Jan 2015 09:22:18 -0800 (PST) X-Received: by 10.140.19.193 with SMTP id 59mr95937qgh.23.1422638538306; Fri, 30 Jan 2015 09:22:18 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!bloom-beacon.mit.edu!bloom-beacon.mit.edu!newsswitch.lcs.mit.edu!ottix-news.ottix.net!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no4965751igb.0!news-out.google.com!q4ni24qan.0!nntp.google.com!v8no4552866qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Jan 2015 09:22:18 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.164.136.112; posting-account=r2yQngoAAABH6wHUUUDXnfZDWZunMbzu NNTP-Posting-Host: 146.164.136.112 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Subject: Re: FSM recurring state technique From: revkarol Injection-Date: Fri, 30 Jan 2015 17:22:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 145 Xref: news.eternal-september.org comp.lang.vhdl:3552 On Friday, 30 January 2015 14:12:42 UTC-2, Gabor Sz wrote: > revkarol wrote: > > Let's say I have an FSM such as the example on the Altera website. =20 > > This is a typical 4-state FSM in the Moore style.=20 > >=20 > > Now, let's say I want a state where the inputs don't change but I want = the outputs to change (say, a counter output). For example, I want to get = to state s2 and when I do, I'll stay in state s2 for say 10 cycles and then= exit to state s3. I'm not sure how to do this. Using the format of the e= xample below, because the state doesn't change, the output is latched. > >=20 > > This seems like a standard problem, but I don't know the standard solut= ion. > >=20 > >=20 > >=20 > > Advance thanks, > > Karol. > >=20 > >=20 > >=20 > >=20 > >=20 > > -- A Moore machine's outputs are dependent only on the current state. > > -- The output is written only when the state changes. (State > > -- transitions are synchronous.) > >=20 > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity moore_4s is > >=20 > > port( > > clk : in std_logic; > > data_in : in std_logic; > > reset : in std_logic; > > data_out : out std_logic_vector(1 downto 0) > > ); > > =09 > > end entity; > >=20 > > architecture rtl of moore_4s is > >=20 > > -- Build an enumerated type for the state machine > > type state_type is (s0, s1, s2, s3); > > =09 > > -- Register to hold the current state > > signal state : state_type; > >=20 > > begin > > -- Logic to advance to the next state > > process (clk, reset) > > begin > > if reset =3D '1' then > > state <=3D s0; > > elsif (rising_edge(clk)) then > > case state is > > when s0=3D> > > if data_in =3D '1' then > > state <=3D s1; > > else > > state <=3D s0; > > end if; > > when s1=3D> > > if data_in =3D '1' then > > state <=3D s2; > > =20 > > else > > state <=3D s1; > > end if; > > when s2=3D> > > if data_in =3D '1' then > > -- here I would have something = like > > -- if counter > 10 then > > state <=3D s3; > > else > > state <=3D s2; > > end if; > > when s3 =3D> > > if data_in =3D '1' then > > state <=3D s0; > > else > > state <=3D s3; > > end if; > > end case; > > end if; > > end process; > > =09 > > -- Output depends solely on the current state > > process (state) > > begin > > =09 > > case state is > > when s0 =3D> > > data_out <=3D "00"; > > when s1 =3D> > > data_out <=3D "01"; > > when s2 =3D> > > data_out <=3D "10"; > > -- here I would have=20 > > data_out <=3D value depending on counte= r; > > when s3 =3D> > > data_out <=3D "11"; > > end case; > > end process; > > =09 > > end rtl; >=20 > It's not hard to add "counter" as a ranged integer and > then increment it while in state s2. Then the only > other thing you need is to reset the counter before > entering state s2. You can do this in several ways: >=20 > 1) reset "counter" in all other states. > 2) reset "counter" in states that can lead to s2. > 3) reset "counter" in the transition terms (when assigning > state <=3D s2 from another state). >=20 > There are other ways to do this including building a timer > "subroutine." I've used this is more complex FSM's where > I needed a variable amount of time spent in a number of > different states. In this case I have a state that just > counts down on a counter until it reaches 0. States that > need the delay will set up their outputs as required, set > the delay value into the counter, store the "return state" > in another signal of the same type as "state" and then > set "state" to the wait state. When the counter is decremented > to zero, the wait state then just assigns state to the return > state. >=20 > --=20 > Gabor Hi Gabor, I think I follow you. So what I think I should do is create another clocke= d process that deals with the counting (and the special output based on the= counting). When I enter the correct state in the FSM, I set an enable for= this clocked process. Without the enable the process does essentially not= hing. Then when I'm done I set a "finished" flag, and that in turn trigger= s the FSM to exit the current state and de-asserts the enable flag. Many thanks, Karol. From newsfish@newsfish Thu Aug 1 00:32:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Supersedes: Date: Fri, 30 Jan 2015 17:55:38 +0000 (UTC) Organization: A noiseless patient Spider Lines: 69 Message-ID: References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 30 Jan 2015 17:55:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="1c311ff5f358f6f093526cc26a26a1ec"; logging-data="3096"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mw49u9j3d0cNr5LkWJRgD" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Key: sha1:7atxe9c+fZEObzTk+RugA5eQacI= Cancel-Lock: sha1:CWZ/fYmbZtZDd/9Xd1cj/GUWctI= Xref: news.eternal-september.org comp.lang.vhdl:3553 On Fri, 30 Jan 2015 09:22:18 -0800, revkarol wrote: > > Hi Gabor, > > I think I follow you. So what I think I should do is create another > clocked process that deals with the counting (and the special output > based on the counting). When I enter the correct state in the FSM, I > set an enable for this clocked process. Without the enable the process > does essentially nothing. Then when I'm done I set a "finished" flag, > and that in turn triggers the FSM to exit the current state and > de-asserts the enable flag. > > Many thanks, > Karol. More processes = more problems. I've frequently done things like below (untested, so beware the syntax). Note two important things. 1) The entire FSM is one process. The FPGA vendors LOVE to tell you to use two process state machines, even for simple Moore ones. They're wrong, it just adds confusion to your world. 2) The states have real people names, not S0, S1, S2. signal go : boolean; signal count : integer range 0 to 15; signal lamp : boolean; type t_state is (IDLE, LAMPOFF, LAMPON); signal state : t_state; ... FSM: process(clk) begin if rising_edge(clk) then lamp <= false; case state is when IDLE => count <= 0; if go then state <= LAMPOFF; end if; when LAMPOFF => if count = 15 then count <= 0; state <= LAMPON; else count <= count + 1; end if; when LAMPON => lamp <= true; if count = 15 then count <= 0; state <= IDLE; else count <= count + 1; end if; end case; end if; end process FSM; -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:32:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Date: Fri, 30 Jan 2015 14:02:18 -0500 Organization: Alacron, Inc. Lines: 117 Message-ID: References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Jan 2015 19:03:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="9899"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19vy5VAmI6oKD6uEk37LrJRiB8bWEOaNAY=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:2MWcg8jgy6EbFx11Zd6/LT/ZAU0= Xref: news.eternal-september.org comp.lang.vhdl:3554 Rob Gaddi wrote: > On Fri, 30 Jan 2015 09:22:18 -0800, revkarol wrote: >> Hi Gabor, >> >> I think I follow you. So what I think I should do is create another >> clocked process that deals with the counting (and the special output >> based on the counting). When I enter the correct state in the FSM, I >> set an enable for this clocked process. Without the enable the process >> does essentially nothing. Then when I'm done I set a "finished" flag, >> and that in turn triggers the FSM to exit the current state and >> de-asserts the enable flag. >> >> Many thanks, >> Karol. > > More processes = more problems. > > I've frequently done things like below (untested, so beware the syntax). > Note two important things. > > 1) The entire FSM is one process. The FPGA vendors LOVE to tell you to > use two process state machines, even for simple Moore ones. They're > wrong, it just adds confusion to your world. > > 2) The states have real people names, not S0, S1, S2. > > signal go : boolean; > signal count : integer range 0 to 15; > signal lamp : boolean; > type t_state is (IDLE, LAMPOFF, LAMPON); > signal state : t_state; > > ... > > FSM: process(clk) > begin > if rising_edge(clk) then > lamp <= false; > > case state is > when IDLE => > count <= 0; > if go then > state <= LAMPOFF; > end if; > > when LAMPOFF => > if count = 15 then > count <= 0; > state <= LAMPON; > else > count <= count + 1; > end if; > > when LAMPON => > lamp <= true; > if count = 15 then > count <= 0; > state <= IDLE; > else > count <= count + 1; > end if; > end case; > end if; > end process FSM; > That is in fact what I was suggesting. There is no need to count in a separate process, since your FSM was already a clocked process. Similarly, here's the "subroutine" approach: signal go : boolean; signal count : integer range 0 to 15; signal lamp : boolean; type t_state is (IDLE, LAMPOFF, LAMPON, SPIN); signal state : t_state; signal rtn_state : t_state; ... FSM: process(clk) begin if rising_edge(clk) then case state is when IDLE => count <= 0; if go then state <= LAMPOFF; end if; when LAMPOFF => lamp <= false; count <= 15; rtn_state <= LAMPON; state <= SPIN; when LAMPON => lamp <= true; count <= 15; rtn_state <= IDLE; state <= SPIN; when SPIN => if count = 0 then state <= rtn_state; else count <= count - 1; end if; end case; end if; end process FSM; -- Gabor From newsfish@newsfish Thu Aug 1 00:32:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Proposed additions to std.env Date: Fri, 30 Jan 2015 19:26:51 +0000 (UTC) Organization: A noiseless patient Spider Lines: 51 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 30 Jan 2015 19:26:51 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="1c311ff5f358f6f093526cc26a26a1ec"; logging-data="3096"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19RVfS89m8m3CHVqo6j2bwZ" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:muBxycJSNXxSqyFd8kbULpy2oQw= Xref: news.eternal-september.org comp.lang.vhdl:3555 A couple things that might be really nice to have, probably in std.env *** function simulation return bool; This would allow the use of if/else/endif blocks to get around one of my least favorite VHDL anti-patterns, the use of --synthesis translate_on/off Pragmas are awful. They're error-prone kludges that can lead to accidentally and silently knocking huge chunks of your code out, because a misformed pragma is just a comment. Additionally, while most vendors support knocking code out for synthesis, support for putting some back in for synthesis such as Altera's comment_as_hdl is limited. Another way around this would be to pass SIMULATION down as a generic, but this a) doesn't work for functions in packages and b) requires that you manually pass the generic all the way down the hierarchy. You could also put it into a package, but then you're responsible for manually changing it back and forth in the code. Now, an argument could be made that this is all awful because you shouldn't be doing it anyhow; that synthesizing code that is different than what you simulate is inherently dangerous. I wouldn't disagree. But at the end of the day, sometimes it's the only way to get it to actually work; the vendor synthesis tools are pretty dumb and get confused by things like assigning 'X' values so that you can trace invalid states through your simulation. Or debugging log file writes. And if there has to be a knock-out mechanism, it should at least be linguistically sound. *** function file_path return string; Provides the path to the current VHDL file. Not sure if there's a better implementation option than that, but some way of enforcing relative paths for files that is better than "Hope the tool has the same understanding of the root directory than I do." would be great. Again, there are workarounds with generics or packages, but again they're a pain for all the same reasons; who wants to have to hard code absolute paths into a VHDL package that you may need to move to another machine? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:32:24 2024 X-Received: by 10.42.10.206 with SMTP id r14mr7216247icr.15.1422654821285; Fri, 30 Jan 2015 13:53:41 -0800 (PST) X-Received: by 10.140.98.198 with SMTP id o64mr110839qge.41.1422654821205; Fri, 30 Jan 2015 13:53:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no3885278igb.0!news-out.google.com!q4ni22qan.0!nntp.google.com!bm13no4084909qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Jan 2015 13:53:41 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7ea7cdab-fac3-46c9-8f2c-3283b1803088@googlegroups.com> Subject: Re: Proposed additions to std.env From: Lars Asplund Injection-Date: Fri, 30 Jan 2015 21:53:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1430 X-Received-Body-CRC: 3399345164 Xref: news.eternal-september.org comp.lang.vhdl:3556 A way to get the current line number would also be great. Together with file path and the now function you have a solid foundation for logging. It can be achieved with preprocessing like we do in VUnit (https://github.com/LarsAsplund/vunit): 86810000 ps: DEBUG in traffic_logger (uart_rx.vhd:39): Received 77 but language support would be better. /Lars From newsfish@newsfish Thu Aug 1 00:32:24 2024 X-Received: by 10.42.111.201 with SMTP id v9mr5530056icp.1.1422903643097; Mon, 02 Feb 2015 11:00:43 -0800 (PST) X-Received: by 10.50.128.202 with SMTP id nq10mr174779igb.12.1422903642979; Mon, 02 Feb 2015 11:00:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no5954098igb.0!news-out.google.com!qk8ni19963igc.0!nntp.google.com!hl2no7899364igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Feb 2015 11:00:42 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.235.165.203; posting-account=jeyu9goAAAADG4d2_eLFCWm4Vp6N4Svn NNTP-Posting-Host: 117.235.165.203 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <656dc9f9-79b1-4102-807c-c385e27af83f@googlegroups.com> Subject: vhdl coding for image centroid From: ann.140190@gmail.com Injection-Date: Mon, 02 Feb 2015 19:00:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1398 X-Received-Body-CRC: 2118766271 Xref: news.eternal-september.org comp.lang.vhdl:3557 hello, how to write the vhdl coding for finding the image centroid using following eqaution scalar (greyscale) image with pixel intensities I(x,y) http://en.wikipedia.org/wiki/Image_moment#Raw_moments M{ij} = sum_x sum_y x^i y^j I(x,y) Centroid: { x, y } = {M10/M00, M01/M00 } the pixel value have to be taken/read such that they are stored in the bram.my fpga have 8 bram of 18kb.kindly share the code thank you. From newsfish@newsfish Thu Aug 1 00:32:24 2024 X-Received: by 10.42.240.132 with SMTP id la4mr956411icb.15.1422967262031; Tue, 03 Feb 2015 04:41:02 -0800 (PST) X-Received: by 10.140.48.97 with SMTP id n88mr275943qga.35.1422967261995; Tue, 03 Feb 2015 04:41:01 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl2no8756143igb.0!news-out.google.com!q4ni25qan.0!nntp.google.com!v8no6263181qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Feb 2015 04:41:01 -0800 (PST) In-Reply-To: <656dc9f9-79b1-4102-807c-c385e27af83f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <656dc9f9-79b1-4102-807c-c385e27af83f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: vhdl coding for image centroid From: KJ Injection-Date: Tue, 03 Feb 2015 12:41:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3558 On Monday, February 2, 2015 at 2:00:45 PM UTC-5, ann.1...@gmail.com wrote: > hello, > > how to write the vhdl coding for finding the image centroid using following eqaution > > scalar (greyscale) image with pixel intensities I(x,y) > http://en.wikipedia.org/wiki/Image_moment#Raw_moments > > M{ij} = sum_x sum_y x^i y^j I(x,y) > Centroid: { x, y } = {M10/M00, M01/M00 } > > the pixel value have to be taken/read such that they are stored in the bram.my fpga have 8 bram of 18kb.kindly share the code > > thank you. Perhaps you can post the code that you've written over the past two weeks, that will give us a better idea of where you're having trouble http://www.edaboard.com/thread330375.html Don't ask people to do your work unless you're paying them to do so. KJ From newsfish@newsfish Thu Aug 1 00:32:25 2024 X-Received: by 10.50.85.18 with SMTP id d18mr15363665igz.3.1422981698258; Tue, 03 Feb 2015 08:41:38 -0800 (PST) X-Received: by 10.50.40.9 with SMTP id t9mr262027igk.7.1422981698180; Tue, 03 Feb 2015 08:41:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no8938880igb.0!news-out.google.com!qk8ni19963igc.0!nntp.google.com!hl2no8938877igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Feb 2015 08:41:37 -0800 (PST) In-Reply-To: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=216.65.182.66; posting-account=JlXAlwoAAACzvkJ2IoEBs0mddSuKa3cg NNTP-Posting-Host: 216.65.182.66 References: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to instantiate a verilog block inside a VHDL entity? From: LeRoss Calnek Injection-Date: Tue, 03 Feb 2015 16:41:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3478 X-Received-Body-CRC: 493813554 Xref: news.eternal-september.org comp.lang.vhdl:3560 very helpful thanks On Monday, 17 February 2014 06:46:24 UTC-6, Allan Herriman wrote: > On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote: > > > Hello > > > > > > My design consists of VHDL blocks. Now i need to instantiate a verilog > > block inside my VHDL block. > > > > QS: Is it possible to instantiate a verilog block inside a VHDL block? > > QS: If the answer to the above question is yes, how to achieve this? > > > > Thanks in advance > > My experience is that it is possible to instantiate a verilog module > inside a VHDL architecture, both using component instantiation and entity > instantiation, in most tools, for both synthesis and simulation. > > Significantly, Altera Quartus does not allow entity instantiation, which > means if you want Altera compatibility you will need to write a component > declaration for each Verilog module. > > Things that don't work the way you'd want: > - heirarchical references typically can't go across a VHDL/Verilog > boundary. > > Things to avoid for portability: > - (for ports) types other than std_logic, std_logic_vector > - (for generics/parameters) types other than integer and string > - in some tools (e.g. older Modelsim), port mappings can only be to > signals. It is not possible to map a port to a constant, for example. > > > Example: > > module foo > #( > parameter bar = 1 > ) > ( > input wire bletch, > output reg baz = 1'b0 > ); > > You could instantiate this as an entity, provided that it has already > been compiled into the work library: > > some_label : entity work.foo > generic map ( > bar => 2 > ) > port map ( > bletch => signal1, > baz => signal2 > ); > > Or if you really like typing you could instantiate module foo as a > component: > > component foo is > generic ( > bar : integer := 1 > ); > port ( > bletch : in std_logic; > baz : out std_logic > ); > end component foo; > > ... > > some_label : component foo > generic map ( > bar => 2 > ) > port map ( > bletch => signal1, > baz => signal2 > ); > > Note that the keyword "component" is optional in a component > instantiation. Most people leave it out. > > Regards, > Allan From newsfish@newsfish Thu Aug 1 00:32:25 2024 X-Received: by 10.70.32.129 with SMTP id j1mr21081112pdi.8.1423000284905; Tue, 03 Feb 2015 13:51:24 -0800 (PST) X-Received: by 10.140.40.242 with SMTP id x105mr320476qgx.14.1423000284803; Tue, 03 Feb 2015 13:51:24 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!hl2no6937465igb.0!news-out.google.com!q4ni26qan.0!nntp.google.com!bm13no5903476qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Feb 2015 13:51:24 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.241.194.161; posting-account=RzNB3QoAAACErfT8OnroBxxwx7Ka-eQH NNTP-Posting-Host: 50.241.194.161 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12e20410-787b-4dcc-bcd9-b55d0036848d@googlegroups.com> Subject: Digital Design / Hardware Simulation From: jknight@metamorphsoftware.com Injection-Date: Tue, 03 Feb 2015 21:51:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3561 Hello, I am looking for a digital design engineer to come work for us, MetaMorph, on Google's Project Ara. Our tools use SystemC for digital simulation and we're looking for someone to help guide this area. I'm sorry if this is spamming, but I'm offering a legit well paying and permanent job. I'm open to all types of arrangements for the right person. Have a look or drop me a line. metamorphsoftware.com/careers/ projectara.com Thank you, Justin Knight CEO, MetaMorph jknight@metamorphsoftware.com From newsfish@newsfish Thu Aug 1 00:32:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Date: Tue, 03 Feb 2015 16:54:16 -0500 Organization: A noiseless patient Spider Lines: 129 Message-ID: References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 3 Feb 2015 21:53:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21303"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX185ucjLpvnuVZDta9gyGPyU" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 In-Reply-To: Cancel-Lock: sha1:Ny5HNCgq4rZQ1uHI61GZkKrvy9s= Xref: news.eternal-september.org comp.lang.vhdl:3562 On 1/30/2015 2:02 PM, GaborSzakacs wrote: > Rob Gaddi wrote: >> On Fri, 30 Jan 2015 09:22:18 -0800, revkarol wrote: >>> Hi Gabor, >>> >>> I think I follow you. So what I think I should do is create another >>> clocked process that deals with the counting (and the special output >>> based on the counting). When I enter the correct state in the FSM, I >>> set an enable for this clocked process. Without the enable the process >>> does essentially nothing. Then when I'm done I set a "finished" flag, >>> and that in turn triggers the FSM to exit the current state and >>> de-asserts the enable flag. >>> >>> Many thanks, >>> Karol. >> >> More processes = more problems. >> >> I've frequently done things like below (untested, so beware the syntax). >> Note two important things. >> >> 1) The entire FSM is one process. The FPGA vendors LOVE to tell you to >> use two process state machines, even for simple Moore ones. They're >> wrong, it just adds confusion to your world. >> >> 2) The states have real people names, not S0, S1, S2. >> >> signal go : boolean; >> signal count : integer range 0 to 15; >> signal lamp : boolean; >> type t_state is (IDLE, LAMPOFF, LAMPON); >> signal state : t_state; >> >> ... >> >> FSM: process(clk) >> begin >> if rising_edge(clk) then >> lamp <= false; >> case state is >> when IDLE => >> count <= 0; >> if go then >> state <= LAMPOFF; >> end if; >> when LAMPOFF => >> if count = 15 then >> count <= 0; >> state <= LAMPON; >> else >> count <= count + 1; >> end if; >> when LAMPON => >> lamp <= true; >> if count = 15 then >> count <= 0; >> state <= IDLE; >> else >> count <= count + 1; >> end if; >> end case; >> end if; >> end process FSM; >> > > That is in fact what I was suggesting. There is no need to count > in a separate process, since your FSM was already a clocked process. > > Similarly, here's the "subroutine" approach: > > signal go : boolean; > signal count : integer range 0 to 15; > signal lamp : boolean; > type t_state is (IDLE, LAMPOFF, LAMPON, SPIN); > signal state : t_state; > signal rtn_state : t_state; > > .... > > FSM: process(clk) > begin > if rising_edge(clk) then > > case state is > when IDLE => > count <= 0; > if go then > state <= LAMPOFF; > end if; > > when LAMPOFF => > lamp <= false; > count <= 15; > rtn_state <= LAMPON; > state <= SPIN; > > when LAMPON => > lamp <= true; > count <= 15; > rtn_state <= IDLE; > state <= SPIN; > > when SPIN => > if count = 0 then > state <= rtn_state; > else > count <= count - 1; > end if; > > end case; > end if; > end process FSM; Just my two cents worth... Rather than assign 0 to count in the idle state I would simply ignore count which will leave it unchanged at its present value. In other words the counter would have an enable rather than a reset. Not sure if it is more complex in the logic or not, but if the FSM is otherwise not enabled, there should be a "free" enable input to each of the FFs which likely would be used for this. Also, and I realize this is not finished code, but an initialization should be considered for all of this logic including the counter. Since the counter is only used in the SPIN state and set before entering the SPIN state, the counter likely doesn't need initialization although it can make simulations more readable. -- Rick From newsfish@newsfish Thu Aug 1 00:32:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Date: Tue, 03 Feb 2015 18:03:30 -0500 Organization: Alacron, Inc. Lines: 139 Message-ID: References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 3 Feb 2015 23:04:07 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="9892"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+SlKmZCJhIsO9M+2ch0CCZcyc7LESGGQQ=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:ARD0XF98VQJ6zNpqbNpYs0aNE2E= Xref: news.eternal-september.org comp.lang.vhdl:3563 rickman wrote: > On 1/30/2015 2:02 PM, GaborSzakacs wrote: >> Rob Gaddi wrote: >>> On Fri, 30 Jan 2015 09:22:18 -0800, revkarol wrote: >>>> Hi Gabor, >>>> >>>> I think I follow you. So what I think I should do is create another >>>> clocked process that deals with the counting (and the special output >>>> based on the counting). When I enter the correct state in the FSM, I >>>> set an enable for this clocked process. Without the enable the process >>>> does essentially nothing. Then when I'm done I set a "finished" flag, >>>> and that in turn triggers the FSM to exit the current state and >>>> de-asserts the enable flag. >>>> >>>> Many thanks, >>>> Karol. >>> >>> More processes = more problems. >>> >>> I've frequently done things like below (untested, so beware the syntax). >>> Note two important things. >>> >>> 1) The entire FSM is one process. The FPGA vendors LOVE to tell you to >>> use two process state machines, even for simple Moore ones. They're >>> wrong, it just adds confusion to your world. >>> >>> 2) The states have real people names, not S0, S1, S2. >>> >>> signal go : boolean; >>> signal count : integer range 0 to 15; >>> signal lamp : boolean; >>> type t_state is (IDLE, LAMPOFF, LAMPON); >>> signal state : t_state; >>> >>> ... >>> >>> FSM: process(clk) >>> begin >>> if rising_edge(clk) then >>> lamp <= false; >>> case state is >>> when IDLE => >>> count <= 0; >>> if go then >>> state <= LAMPOFF; >>> end if; >>> when LAMPOFF => >>> if count = 15 then >>> count <= 0; >>> state <= LAMPON; >>> else >>> count <= count + 1; >>> end if; >>> when LAMPON => >>> lamp <= true; >>> if count = 15 then >>> count <= 0; >>> state <= IDLE; >>> else >>> count <= count + 1; >>> end if; >>> end case; >>> end if; >>> end process FSM; >>> >> >> That is in fact what I was suggesting. There is no need to count >> in a separate process, since your FSM was already a clocked process. >> >> Similarly, here's the "subroutine" approach: >> >> signal go : boolean; >> signal count : integer range 0 to 15; >> signal lamp : boolean; >> type t_state is (IDLE, LAMPOFF, LAMPON, SPIN); >> signal state : t_state; >> signal rtn_state : t_state; >> >> .... >> >> FSM: process(clk) >> begin >> if rising_edge(clk) then >> >> case state is >> when IDLE => >> count <= 0; >> if go then >> state <= LAMPOFF; >> end if; >> >> when LAMPOFF => >> lamp <= false; >> count <= 15; >> rtn_state <= LAMPON; >> state <= SPIN; >> >> when LAMPON => >> lamp <= true; >> count <= 15; >> rtn_state <= IDLE; >> state <= SPIN; >> >> when SPIN => >> if count = 0 then >> state <= rtn_state; >> else >> count <= count - 1; >> end if; >> >> end case; >> end if; >> end process FSM; > > Just my two cents worth... Rather than assign 0 to count in the idle > state I would simply ignore count which will leave it unchanged at its > present value. In other words the counter would have an enable rather > than a reset. Not sure if it is more complex in the logic or not, but > if the FSM is otherwise not enabled, there should be a "free" enable > input to each of the FFs which likely would be used for this. > > Also, and I realize this is not finished code, but an initialization > should be considered for all of this logic including the counter. Since > the counter is only used in the SPIN state and set before entering the > SPIN state, the counter likely doesn't need initialization although it > can make simulations more readable. > You're right. I think the count <= 0 came from the old code and I just left it there. If anything it would best be initialized to 15 since no other value is ever loaded in parallel. However the point of the "subroutine" method is that you could load different values into the counter depending on the time required by each state. Even if the count was allowed to start up "U" there would be no issue with simulation since it is always loaded before it is used. The "state" variable would need an initial value for simulation, though. -- Gabor From newsfish@newsfish Thu Aug 1 00:32:26 2024 X-Received: by 10.182.143.34 with SMTP id sb2mr1552408obb.27.1423104347417; Wed, 04 Feb 2015 18:45:47 -0800 (PST) X-Received: by 10.182.106.233 with SMTP id gx9mr12989obb.0.1423104347330; Wed, 04 Feb 2015 18:45:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no9844513igb.0!news-out.google.com!qk8ni25140igc.0!nntp.google.com!hl2no7347955igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Feb 2015 18:45:45 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f703a14-f0c1-4fdb-9141-32b27c8fe79c@googlegroups.com> Subject: Re: FSM recurring state technique From: Andy Injection-Date: Thu, 05 Feb 2015 02:45:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1957 X-Received-Body-CRC: 3015286656 Xref: news.eternal-september.org comp.lang.vhdl:3565 Beware that saving/restoring the state to/from a separate register may prev= ent the synthesis tool from recognizing and optimizing/augmenting the FSM (= many require reading and writing state only from/to one register.) Be sure = to check it out before you use this method if that is important to your app= lication. An alternative method would be to use separate register(s) with flag(s) or = a separate enumerated type to determine where to go from the subroutine. An= if/then/else tree or case statement in the subroutine state could be used = to assign the state register based on the flags/enum, without preventing FS= M synthesis optimization/augmentation. Andy From newsfish@newsfish Thu Aug 1 00:32:26 2024 X-Received: by 10.236.26.108 with SMTP id b72mr1484502yha.33.1423104954860; Wed, 04 Feb 2015 18:55:54 -0800 (PST) X-Received: by 10.182.252.232 with SMTP id zv8mr12326obc.37.1423104954746; Wed, 04 Feb 2015 18:55:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v8no6677928qal.1!news-out.google.com!qk8ni25600igc.0!nntp.google.com!hl2no9846036igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Feb 2015 18:55:54 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Proposed additions to std.env From: Andy Injection-Date: Thu, 05 Feb 2015 02:55:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3566 I've used a deferred constant for detection of simulation. Just compile a different package body for simulation, after compiling the RTL. constant simulation: Boolean; -- package constant simulation: Boolean := false; -- rtl package body constant simulation: Boolean := true; -- simulation package body Andy On Friday, January 30, 2015 at 1:27:26 PM UTC-6, Rob Gaddi wrote: > A couple things that might be really nice to have, probably in std.env > > *** > > function simulation return bool; > > This would allow the use of if/else/endif blocks to get around one of my > least favorite VHDL anti-patterns, the use of > --synthesis translate_on/off > > Pragmas are awful. They're error-prone kludges that can lead to > accidentally and silently knocking huge chunks of your code out, because > a misformed pragma is just a comment. Additionally, while most vendors > support knocking code out for synthesis, support for putting some back in > for synthesis such as Altera's comment_as_hdl is limited. > > Another way around this would be to pass SIMULATION down as a generic, > but this a) doesn't work for functions in packages and b) requires that > you manually pass the generic all the way down the hierarchy. > > You could also put it into a package, but then you're responsible for > manually changing it back and forth in the code. > > Now, an argument could be made that this is all awful because you > shouldn't be doing it anyhow; that synthesizing code that is different > than what you simulate is inherently dangerous. I wouldn't disagree. > But at the end of the day, sometimes it's the only way to get it to > actually work; the vendor synthesis tools are pretty dumb and get > confused by things like assigning 'X' values so that you can trace > invalid states through your simulation. Or debugging log file writes. > And if there has to be a knock-out mechanism, it should at least be > linguistically sound. > > *** > > function file_path return string; > > Provides the path to the current VHDL file. Not sure if there's a better > implementation option than that, but some way of enforcing relative paths > for files that is better than "Hope the tool has the same understanding > of the root directory than I do." would be great. > > Again, there are workarounds with generics or packages, but again they're > a pain for all the same reasons; who wants to have to hard code absolute > paths into a VHDL package that you may need to move to another machine? > > > > -- > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:32:27 2024 X-Received: by 10.66.66.108 with SMTP id e12mr2008813pat.30.1423115994237; Wed, 04 Feb 2015 21:59:54 -0800 (PST) X-Received: by 10.50.66.141 with SMTP id f13mr439530igt.17.1423115994046; Wed, 04 Feb 2015 21:59:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no9886851igb.0!news-out.google.com!qk8ni25600igc.0!nntp.google.com!hl2no9886849igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Feb 2015 21:59:53 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=98.176.99.126; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 98.176.99.126 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4cde06d0-a565-4a11-bfb4-8643a9490bae@googlegroups.com> Subject: Split package - package body with deferred type definitions? From: David Rogoff Injection-Date: Thu, 05 Feb 2015 05:59:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3567 Hi all. Getting back into some VHDL verification after many years of SystemVerilog.= Question about packages and deferred definitions. Test environment has main test split into separate entity and architecture = files so that 1) entity can be compiled once with RTL and only architecture= file needs to be recompiled when changes, and 2) multiple architecture fil= es can be configured to the single entity. This works great. I'm now trying to extend this concept with a package to = be used by this test file. Again, I'm setting up the package and package b= ody in separate files so the test entity can "use" the package file and mul= tiple package body files (each corresponding to the test architecture files= ) would have the local definitions of things. This is fine for constants and procedures since I can put the prototype in = the package file and then the deferred constant assignment and procedure bo= dies in the package body files. So far, so good. However, it all dies for the type definitions. Each package body needs to = define its own version of the types. It doesn't look like there's such a t= hing as deferred type declarations. Am I missing something? Another way to implement this concept? I can brut= e-force a Verilog/C-like `define by using the compile script to concatenate= the package body file (minus the package body/end package body lines) and = the architecture file into one (inserting the "package" after the "architec= ture xx of yy is" line) and compiling that. Ugly, but it should work. Help! Thanks, David From newsfish@newsfish Thu Aug 1 00:32:27 2024 X-Received: by 10.66.123.16 with SMTP id lw16mr3913433pab.37.1423154020430; Thu, 05 Feb 2015 08:33:40 -0800 (PST) X-Received: by 10.182.236.74 with SMTP id us10mr37299obc.32.1423154020276; Thu, 05 Feb 2015 08:33:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no10157436igb.0!news-out.google.com!qk8ni25140igc.0!nntp.google.com!hl2no7535272igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Feb 2015 08:33:40 -0800 (PST) In-Reply-To: <4cde06d0-a565-4a11-bfb4-8643a9490bae@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.69.57; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.69.57 References: <4cde06d0-a565-4a11-bfb4-8643a9490bae@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <47f2ce6e-b363-41f1-8d6a-e56585c4b9c5@googlegroups.com> Subject: Re: Split package - package body with deferred type definitions? From: Jim Lewis Injection-Date: Thu, 05 Feb 2015 16:33:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2261 X-Received-Body-CRC: 3164425204 Xref: news.eternal-september.org comp.lang.vhdl:3568 Hi David, Have you considered using generics on packages? This is a VHDL-2008 feature. With VHDL-2008, generics can be put on packages, and generics can be constants (the pre-2008 generic), types, subprograms, and generic packages. The following shows a simple sketch of a package with type and subprogram generics: package ScoreBoardPkg is generic ( type BaseType ; function check(A, E : BaseType) return boolean ) ; -- remaining part of package goes here end ScoreBoardPkg ; To use the generic package you must create a package instance. This is done as follows: library IEEE ; use ieee.std_logic_1164.all ; package ScoreBoardPkg_slv8 is new work.ScoreBoardPkg generic map ( BaseType => std_logic_vector(7 downto 0), check => std_match ) ; If you are looking for features such as randomization and functional coverage, be sure to check out the Open Source VHDL Verification Methodology page at http://www.osvvm.org If you are looking for training on OSVVM and Advanced VHDL Verification techniques, see http://synthworks.com/vhdl_testbench_verification.htm Best Regards, Jim From newsfish@newsfish Thu Aug 1 00:32:27 2024 X-Received: by 10.236.15.69 with SMTP id e45mr4575220yhe.5.1423156874701; Thu, 05 Feb 2015 09:21:14 -0800 (PST) X-Received: by 10.182.73.170 with SMTP id m10mr40273obv.27.1423156874545; Thu, 05 Feb 2015 09:21:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v8no6802861qal.1!news-out.google.com!qk8ni25140igc.0!nntp.google.com!hl2no7548265igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Feb 2015 09:21:14 -0800 (PST) In-Reply-To: <47f2ce6e-b363-41f1-8d6a-e56585c4b9c5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.163.20.52; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 64.163.20.52 References: <4cde06d0-a565-4a11-bfb4-8643a9490bae@googlegroups.com> <47f2ce6e-b363-41f1-8d6a-e56585c4b9c5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ddc6974-7554-4389-9a39-95124d471c10@googlegroups.com> Subject: Re: Split package - package body with deferred type definitions? From: David Rogoff Injection-Date: Thu, 05 Feb 2015 17:21:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1792 X-Received-Body-CRC: 3924499039 Xref: news.eternal-september.org comp.lang.vhdl:3569 On Thursday, February 5, 2015 at 8:33:43 AM UTC-8, Jim Lewis wrote: > Hi David, > Have you considered using generics on packages? This is a VHDL-2008 feature. > > With VHDL-2008, generics can be put on packages, and generics can be constants (the pre-2008 generic), types, subprograms, and generic packages. > > Best Regards, > Jim Thanks Jim. I briefly thought about generics but didn't look into the details. I'll have to take some time with that. I think it could work but might be really messy given the number and size of some type enums I need to deal with. David From newsfish@newsfish Thu Aug 1 00:32:28 2024 X-Received: by 10.66.233.198 with SMTP id ty6mr11267549pac.24.1423396905407; Sun, 08 Feb 2015 04:01:45 -0800 (PST) X-Received: by 10.140.28.131 with SMTP id 3mr55758qgz.16.1423396905133; Sun, 08 Feb 2015 04:01:45 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no11886775igb.0!news-out.google.com!q4ni11076qan.0!nntp.google.com!v8no7398292qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Feb 2015 04:01:45 -0800 (PST) In-Reply-To: <8aa2903c-12b4-4784-8a69-8eb7349ef645@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.55.215.39; posting-account=sQsPdgoAAACgOMKaiBi8koqnE3-a4hm- NNTP-Posting-Host: 78.55.215.39 References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> <8aa2903c-12b4-4784-8a69-8eb7349ef645@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help with VHDL architecture From: saadriazqazi@gmail.com Injection-Date: Sun, 08 Feb 2015 12:01:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2422 X-Received-Body-CRC: 688637370 Xref: news.eternal-september.org comp.lang.vhdl:3570 On Saturday, 3 January 2015 11:38:20 UTC+1, Olalekan Shittu wrote: > On Friday, 2 January 2015 10:19:42 UTC+1, Andy Bennett wrote: > > "Andy Bennett" wrote in message > > news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk... > > > > Forgot to add sel ... so > > > > > > > > > > > > > > > > Something like:- > > > > Defaults:- > > > > Out[3..0] = 0 > > > > End defaults > > > > > > If sel = 4 then > > If C >= 0 or C < 4 then > > out0 = 1 > > end if > > > > If C >= 4 or C < 8 then > > out1 = 1 > > end if > > > > If C >= 8 or C < 12end if > > out2 = 1 > > end if > > > > If C >= 12 or C < 16 then > > out3 = 1 > > end if > > end if > > > > > > The student can add/correct the syntax > > > > > > Andy > > Thanks Andy, trying to work on the syntax for now. > > Is there a way I can combine this system with another system before writing a test bench for it. If you dont mind, I can send you a personal email. What do you want to combine this with? It is a very simple if statement logic and can be combined easily i think. From newsfish@newsfish Thu Aug 1 00:32:28 2024 X-Received: by 10.236.47.170 with SMTP id t30mr6087958yhb.19.1423781087320; Thu, 12 Feb 2015 14:44:47 -0800 (PST) X-Received: by 10.140.37.113 with SMTP id q104mr97915qgq.0.1423781087276; Thu, 12 Feb 2015 14:44:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no859048qae.0!news-out.google.com!n6ni6qar.0!nntp.google.com!j7no184942qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Feb 2015 14:44:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.163.20.52; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 64.163.20.52 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Overloading procedures with parameters of different size? From: David Rogoff Injection-Date: Thu, 12 Feb 2015 22:44:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2070 X-Received-Body-CRC: 3185681635 Xref: news.eternal-september.org comp.lang.vhdl:3572 Hi all. More VHDL headaches. I've been using a lot of overloaded procedur= es - mostly to deal with optional arguments / default values that VHDL does= not support. So far, so good. However, I need multiple versions of a pro= cedure that take an std_logic_vector as an input but with different widths.= I have something like the following: subtype shortdata_t is std_logic_vector (7 downto 0); subtype meddata_t is std_logic_vector (15 downto 0); procedure a (d_in : in shortdata_t; .....); procedure a (d_in : in meddata_t; .....); This just gets me illegal redeclaration errors from the compiler. I think = it's because they're different subtypes, not different types. I could use = a generic and pass the size but that's a big headache. Is there a way to d= o this? Also, is there a way (or upcoming standard) to have optional inputs with de= fault values like SystemVerilog so I don't have to have multiple, overloade= d versions of subprograms just to deal with that? Thanks, David From newsfish@newsfish Thu Aug 1 00:32:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Overloading procedures with parameters of different size? Date: Thu, 12 Feb 2015 22:59:12 +0000 (UTC) Organization: A noiseless patient Spider Lines: 42 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 12 Feb 2015 22:59:12 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="1c311ff5f358f6f093526cc26a26a1ec"; logging-data="22466"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Y3ACFaWFBz+4N80VXywiC" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:j9IW4r1ZCxVzW2v65+B2F1+naxk= Xref: news.eternal-september.org comp.lang.vhdl:3573 On Thu, 12 Feb 2015 14:44:47 -0800, David Rogoff wrote: > Hi all. More VHDL headaches. I've been using a lot of overloaded > procedures - mostly to deal with optional arguments / default values > that VHDL does not support. So far, so good. However, I need multiple > versions of a procedure that take an std_logic_vector as an input but > with different widths. I have something like the following: > > subtype shortdata_t is std_logic_vector (7 downto 0); > subtype meddata_t is std_logic_vector (15 downto 0); > > > procedure a (d_in : in shortdata_t; .....); > > procedure a (d_in : in meddata_t; .....); > > This just gets me illegal redeclaration errors from the compiler. I > think it's because they're different subtypes, not different types. I > could use a generic and pass the size but that's a big headache. Is > there a way to do this? > > Also, is there a way (or upcoming standard) to have optional inputs with > default values like SystemVerilog so I don't have to have multiple, > overloaded versions of subprograms just to deal with that? > > Thanks, > > David There's always procedure a (d_in : std_logic_vector; .....) is begin if d_in'length = shortdata_t'length then .... Inelegant, but it would get the job done. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:32:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Colin Paul de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: Digital Design / Hardware Simulation Date: Fri, 13 Feb 2015 12:51:14 +0100 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <12e20410-787b-4dcc-bcd9-b55d0036848d@googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; format=flowed; charset=US-ASCII Injection-Info: mx02.eternal-september.org; posting-host="1269e88b772369679a1c60bd0bac220f"; logging-data="20508"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+4h0LCp3rm93DQ3gdLeWzMRnO7Ra8mtLVKPS5Vw7lIFg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <12e20410-787b-4dcc-bcd9-b55d0036848d@googlegroups.com> Cancel-Lock: sha1:sa86APQfraVho3Of/GGHUwowT+M= X-X-Sender: gloster@anapnea.net Xref: news.eternal-september.org comp.lang.vhdl:3574 Justin Knight sent: |-------------------------------------------------------------------| |"Hello, | | | |I am looking for a digital design engineer to come work for us, | |MetaMorph, on Google's Project Ara. | | | |Our tools use SystemC for digital simulation and we're looking for | |someone to help guide this area. | | | |I'm sorry if this is spamming, but I'm offering a legit well paying| |and permanent job. I'm open to all types of arrangements for the | |right person. Have a look or drop me a line. | | | |metamorphsoftware.com/careers/ | |projectara.com | | | |Thank you, | | | |Justin Knight | |CEO, MetaMorph" | |-------------------------------------------------------------------| Hello, This is a VHDL (i.e.) engineering newsgroup, therefore this advertisement for a SystemC(R) is not appropriate for this newsgroup. I hope that you will see sense and use a language which is fit for purpose. Yours sincerely, Colin Paul de Gloucester From newsfish@newsfish Thu Aug 1 00:32:29 2024 X-Received: by 10.66.255.68 with SMTP id ao4mr8190242pad.1.1423828370593; Fri, 13 Feb 2015 03:52:50 -0800 (PST) X-Received: by 10.140.109.66 with SMTP id k60mr118479qgf.36.1423828370504; Fri, 13 Feb 2015 03:52:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl2no10910822igb.0!news-out.google.com!c1ni5qar.1!nntp.google.com!i13no951297qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Feb 2015 03:52:50 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8233b7c0-98a0-4129-b11b-cf891ccc6435@googlegroups.com> Subject: Re: Overloading procedures with parameters of different size? From: KJ Injection-Date: Fri, 13 Feb 2015 11:52:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3575 On Thursday, February 12, 2015 at 5:44:48 PM UTC-5, David Rogoff wrote: > > Also, is there a way (or upcoming standard) to have optional inputs with default values like SystemVerilog so I don't have to have multiple, overloaded versions of subprograms just to deal with that? > Yes, you just put the default value in the procedure declaration: The following defaults the value of 'd_in' to "00000000" procedure a (d_in : std_logic_vector "= x"00"; .....) Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Overloading procedures with parameters of different size? Date: Fri, 13 Feb 2015 13:39:34 +0000 (UTC) Organization: A noiseless patient Spider Lines: 23 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 13 Feb 2015 13:39:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="6184"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Gks+ndl/41Wv9hg62LbbL8VkXu4S11L8=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:rns8Wa3/68iWvlen2ZtHIZFhKbQ= Xref: news.eternal-september.org comp.lang.vhdl:3576 On Thu, 12 Feb 2015 14:44:47 -0800, David Rogoff wrote: > Hi all. More VHDL headaches. I've been using a lot of overloaded > procedures - mostly to deal with optional arguments / default values > that VHDL does not support. So far, so good. However, I need multiple > versions of a procedure that take an std_logic_vector as an input but > with different widths. I have something like the following: > > subtype shortdata_t is std_logic_vector (7 downto 0); > subtype meddata_t is std_logic_vector (15 downto 0); > > > procedure a (d_in : in shortdata_t; .....); procedure a (d_in : in std_logic_vector; .....); Make the body of "a" agnostic about d_in's actual length, using attributes where necessary, "for i in d_in'range loop ..." etc. If you need to identify the actual subtype, Rob's trick of testing d_in'length in an if or case statement will work. -- Brian From newsfish@newsfish Thu Aug 1 00:32:30 2024 X-Received: by 10.182.135.197 with SMTP id pu5mr9760978obb.32.1423854951797; Fri, 13 Feb 2015 11:15:51 -0800 (PST) X-Received: by 10.140.89.84 with SMTP id u78mr142968qgd.10.1423854951731; Fri, 13 Feb 2015 11:15:51 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!hl2no15755610igb.0!news-out.google.com!c1ni5qar.1!nntp.google.com!i13no1034993qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Feb 2015 11:15:51 -0800 (PST) In-Reply-To: <8233b7c0-98a0-4129-b11b-cf891ccc6435@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.163.20.52; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 64.163.20.52 References: <8233b7c0-98a0-4129-b11b-cf891ccc6435@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13df3cc1-8121-4404-a285-a291304eaee8@googlegroups.com> Subject: Re: Overloading procedures with parameters of different size? From: David Rogoff Injection-Date: Fri, 13 Feb 2015 19:15:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:3577 Thanks - Unfortunately, this will only work with named associations in the= procedure/function call. In general, I'm in favor of this, but when you h= ave hundreds of calls of the same procedure that each have long lists of ar= guments, it can be get really messy. Does it work for positional associati= ons if the optional argument is the last one? David From newsfish@newsfish Thu Aug 1 00:32:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe002.ams.xsnews.nl!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 13 Feb 2015 18:16:13 -0600 Date: Sat, 14 Feb 2015 00:16:13 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Overloading procedures with parameters of different size? References: <8233b7c0-98a0-4129-b11b-cf891ccc6435@googlegroups.com> <13df3cc1-8121-4404-a285-a291304eaee8@googlegroups.com> In-Reply-To: <13df3cc1-8121-4404-a285-a291304eaee8@googlegroups.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-ID: Lines: 14 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-exsMftOUZW9yaK8oy4cPA7MtkMODFxWgaeMk2MCsKlZ8ZVdG6gupcRIMdnkHtzlVaRHmLjnIgGnN8Z8!taK6sEIGvuHya8pnDoAA6wTKnW9B0o9zUWd2hdAeGh6ARFjJV2/dXffmgE8FEx7skf+C2XoThVTq!ZX+0H7iHDH2JekIKlswDe/gB X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1918 Xref: news.eternal-september.org comp.lang.vhdl:3578 On 13/02/15 19:15, David Rogoff wrote: > Thanks - Unfortunately, this will only work with named associations in the procedure/function call. In general, I'm in favor of this, but when you have hundreds of calls of the same procedure that each have long lists of arguments, it can be get really messy. Does it work for positional associations if the optional argument is the last one? > > David > Yes, you can mix positional and named association, as long as positional association comes first. You can't change back to positional association after you've started named assocation. regards Alan -- Alan Fitch From newsfish@newsfish Thu Aug 1 00:32:30 2024 X-Received: by 10.52.142.141 with SMTP id rw13mr13818276vdb.6.1423941101768; Sat, 14 Feb 2015 11:11:41 -0800 (PST) X-Received: by 10.50.85.17 with SMTP id d17mr285287igz.7.1423941101662; Sat, 14 Feb 2015 11:11:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j7no589219qaq.1!news-out.google.com!db6ni25585igc.0!nntp.google.com!hl2no16345823igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 14 Feb 2015 11:11:41 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: A searching miss for all papers published in the 11th annual international HDL conference & exhibition? From: Weng Tianxiang Injection-Date: Sat, 14 Feb 2015 19:11:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3579 Hi Jim, I published a paper "HDL code efficiency sources and its solutions" in the publication of the 11th annual international HDL conference & exhibition in 2002. The conference, as I knew, was held by VHDL committee chaired by Jim Lewis. In the paper I introduced two groups of total 5 new keywords: Group A: orif, elsor and errels. Group B: machine and exclusive. I used Google and Microsoft tools to search the paper and found nothing in the searching results. As Jim indicated before, some or all of new keywords are introduced into Verilog-2008, VHDL-2008 and VHDL2009. I tried another paper "Fault simulation with dynamic model abstraction switching" and it wasn't found either. I don't know why the articles in the conference cannot be found by Google and Microsoft searching tools. Is the conference's academic level so low that all papers published in the conference are not considered as scientific papers? Jim, you should pay attention to it! Thank you. Weng From newsfish@newsfish Thu Aug 1 00:32:31 2024 X-Received: by 10.66.221.5 with SMTP id qa5mr16129952pac.16.1423967930284; Sat, 14 Feb 2015 18:38:50 -0800 (PST) X-Received: by 10.50.79.131 with SMTP id j3mr301073igx.16.1423967930002; Sat, 14 Feb 2015 18:38:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!hl2no16516385igb.0!news-out.google.com!db6ni25585igc.0!nntp.google.com!hl2no16516384igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 14 Feb 2015 18:38:49 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.69.57; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.69.57 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13e73df5-e334-42bd-8297-712b6da3d24b@googlegroups.com> Subject: Re: A searching miss for all papers published in the 11th annual international HDL conference & exhibition? From: Jim Lewis Injection-Date: Sun, 15 Feb 2015 02:38:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: news.eternal-september.org comp.lang.vhdl:3580 Hi Weng, > I published a paper "HDL code efficiency sources and its solutions" in the publication of the 11th annual international HDL conference & exhibition in 2002. The conference, as I knew, was held by VHDL committee chaired by Jim Lewis. Sure I remember your paper. OTOH, VASG which I currently chair (but not back then) was not the conference organizer. > Is the conference's academic level so low that all papers published in the conference are not considered as scientific papers? > > Jim, you should pay attention to it! While I was on the program committee at that time, I did not organize the conference. I suspect that you may have received the proceedings on a CD. Did you search your resources for it? What you are searching for is papers from the International HDL Conference - in 2003, it changed names to DVCon. I looked on the DVCon site and only found papers back to 2008. I looked on my computer to see if I might have a copy of the conference papers and I do not. Looked around my office to see if I could find my disk but did not see it. Best Regards, Jim From newsfish@newsfish Thu Aug 1 00:32:31 2024 X-Received: by 10.66.136.79 with SMTP id py15mr17519053pab.40.1424020626320; Sun, 15 Feb 2015 09:17:06 -0800 (PST) X-Received: by 10.50.178.180 with SMTP id cz20mr326090igc.14.1424020626207; Sun, 15 Feb 2015 09:17:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!hl2no16836394igb.0!news-out.google.com!db6ni25585igc.0!nntp.google.com!hl2no16836385igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Feb 2015 09:17:05 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9985ada7-3730-4c75-91c5-b9d4ffbbfb58@googlegroups.com> Subject: Re: A searching miss for all papers published in the 11th annual international HDL conference & exhibition? From: Weng Tianxiang Injection-Date: Sun, 15 Feb 2015 17:17:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 50 Xref: news.eternal-september.org comp.lang.vhdl:3581 On Saturday, February 14, 2015 at 11:11:43 AM UTC-8, Weng Tianxiang wrote: > Hi Jim, > I published a paper "HDL code efficiency sources and its solutions" in th= e publication of the 11th annual international HDL conference & exhibition = in 2002. The conference, as I knew, was held by VHDL committee chaired by J= im Lewis. >=20 > In the paper I introduced two groups of total 5 new keywords:=20 > Group A: orif, elsor and errels.=20 > Group B: machine and exclusive. >=20 > I used Google and Microsoft tools to search the paper and found nothing i= n the searching results. >=20 > As Jim indicated before, some or all of new keywords are introduced into = Verilog-2008, VHDL-2008 and VHDL2009. >=20 > I tried another paper "Fault simulation with dynamic model abstraction sw= itching"=20 > and it wasn't found either.=20 >=20 > I don't know why the articles in the conference cannot be found by Google= and Microsoft searching tools. >=20 > Is the conference's academic level so low that all papers published in th= e conference are not considered as scientific papers? >=20 > Jim, you should pay attention to it! >=20 > Thank you. >=20 > Weng Hi Jim, Thank you for your reply. As the present VHDL committee chairman, you should do something to make sur= e that every paper published in the conferences held by VHDL committee shou= ld go into some data base so that it will be searchable through web. If you= couldn't do that it certainly would do deep harms to any future conference= held by your VHDL committee.=20 If your committee doesn't require any payment I think any digital paper lib= rary would like to freely accept your offer to register all papers which ha= ve been published in any conferences held by VHDL committee even though you= are not responsible for such blunder. Thank you. Weng From newsfish@newsfish Thu Aug 1 00:32:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Colin Paul de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: A searching miss for all papers published in the 11th annual international HDL conference & exhibition? Date: Mon, 16 Feb 2015 12:24:07 +0100 Organization: A noiseless patient Spider Lines: 92 Message-ID: References: <9985ada7-3730-4c75-91c5-b9d4ffbbfb58@googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx02.eternal-september.org; posting-host="1269e88b772369679a1c60bd0bac220f"; logging-data="26186"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18tVpyh8pz1IkSYbi1ELFGgus57AIHKFxGDz2tzURKSkg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <9985ada7-3730-4c75-91c5-b9d4ffbbfb58@googlegroups.com> Cancel-Lock: sha1:6zKXqUWuAO3Bg8/vMuKsGq3LKas= X-X-Sender: gloster@anapnea.net Xref: news.eternal-september.org comp.lang.vhdl:3582 On February 15th, 2015, Weng Tianxiang posted: |---------------------------------------------------------------------------| |"On Saturday, February 14, 2015 at 11:11:43 AM UTC-8, Weng Tianxiang wrote:| |> Hi Jim, | |> I published a paper "HDL code efficiency sources and its solutions" | |> in the publication of the 11th annual international HDL conference & | |> exhibition in 2002. The conference, as I knew, was held by VHDL | |> committee chaired by Jim Lewis. | |> | |> In the paper I introduced two groups of total 5 new keywords: | |> Group A: orif, elsor and errels. | |> Group B: machine and exclusive. | |> | |> I used Google and Microsoft tools to search the paper and found | |> nothing in the searching results. | |> | |> As Jim indicated before, some or all of new keywords are introduced | |> into Verilog-2008, VHDL-2008 and VHDL2009. | |> | |> I tried another paper "Fault simulation with dynamic model | |> abstraction switching" | |> and it wasn't found either." | |---------------------------------------------------------------------------| Dear Weng: Unfortunately I did not find "HDL code efficiency sources and its solutions". Google Scholar claimed today that "Fault simulation with dynamic model abstraction switching" was cited two times. |---------------------------------------------------------------------------| |"> I don't know why the articles in the conference cannot be found by | |> Google and Microsoft searching tools." | |---------------------------------------------------------------------------| What criteria are utilized by Google Scholar are subject to much speculation. See for example ListServ messages archived by HTTP://web.UTK.edu/~gwhitney/sigmetrics.html |---------------------------------------------------------------------------| |"> Is the conference's academic level so low that all papers published | |> in the conference are not considered as scientific papers?" | |---------------------------------------------------------------------------| Maybe the reason these search engines did not find them is because these papers are archived on C.D.s instead of being freely available on the Internet. They search the Internet instead of C.D.s. |---------------------------------------------------------------------------| |"> Jim, you should pay attention to it! | |> | |> Thank you. | |> | |> Weng | | | |Hi Jim, | |Thank you for your reply. | | | |As the present VHDL committee chairman, you should do something to | |make sure that every paper published in the conferences held by VHDL | |committee should go into some data base so that it will be searchable | |through web. If you couldn't do that it certainly would do deep harms | |to any future conference held by your VHDL committee. | | | |If your committee doesn't require any payment I think any digital | |paper library would like to freely accept your offer to register all | |papers which have been published in any conferences held by VHDL | |committee even though you are not responsible for such blunder. | | | |Thank you. | | | |Weng" | |---------------------------------------------------------------------------| Information should be available. Absurdly HDLCon.org obstructed making its information available. HTTPS://web.Archive.org/web/*/http://www.hdlcon.org reported: "Page cannot be crawled or displayed due to robots.txt. See www.hdlcon.org robots.txt page. Learn more about robots.txt." Archive.org can help to find some old files, e.g. HTTPS://web.Archive.org/web/20070212200049/http://www.dvcon.org/archive.html but I did not find files from this 2002 conference. HTTPS://web.Archive.org/web/20100127041856/http://dvcon.org/archive.html even had hyperlinks for 2001 and 2003, but not for 2002. Good luck, Colin Paul de Gloucester From newsfish@newsfish Thu Aug 1 00:32:31 2024 X-Received: by 10.236.40.112 with SMTP id e76mr23395715yhb.5.1424195428626; Tue, 17 Feb 2015 09:50:28 -0800 (PST) X-Received: by 10.140.109.181 with SMTP id l50mr356210qgf.3.1424195428584; Tue, 17 Feb 2015 09:50:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no1826457qae.0!news-out.google.com!n6ni8qar.0!nntp.google.com!j7no1152123qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 17 Feb 2015 09:50:28 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> Subject: Open source unit testing framework release From: Lars Asplund Injection-Date: Tue, 17 Feb 2015 17:50:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3127 X-Received-Body-CRC: 2362345869 Xref: news.eternal-september.org comp.lang.vhdl:3583 Hi, VUnit, an unit testing framework for VHDL, is now freely available on githu= b (https://github.com/LarsAsplund/vunit). It is released under the business= -friendly Mozilla Public License, v. 2.0 and features the functionality nee= ded to realize continuous and automated testing of your VHDL code. VUnit do= esn't replace but rather complements traditional testing methodologies by s= upporting a "test early and often" approach through automation. A quick 6 minute introduction to unit testing can be found at https://www.y= outube.com/watch?v=3DPZuBqcxS8t4 and a short (12 min) introduction to VUnit= can be found at https://www.youtube.com/watch?v=3DD8s_VLD91tw. Some of the VUnit highlights are - Python test runner that enables powerful test administration, can handle = VHDL fatal run-time errors (e.g. division by zero), and ensures test case i= ndependence. - Scanners for identifying files, tests, file dependencies, and file change= s enable for automatic (re)compilation and execution of test suites. - Scripting as well as command line support. - Support for running same test suite with different generics. - VHDL test runner which enables test execution for not fully supported sim= ulators. We currently have full support for ModelSim but Aldec support is c= oming soon. - Assertion checker library that extends VHDL built-in support (assert). - Logging framework supporting display and file output, different log level= s, filtering on level and design hierarchy, output formatting and multiple = loggers. Spreadsheet tool integration. - Location preprocessor that traces log and check calls back to file and li= ne number. - JUnit report files for better Jenkins integration. We are an active and responsive community but want to grow to benefit furth= er development. You can participate by adding questions on Github, suggesti= ng enhancement, reporting bugs, and contributing code. If you like what you= see click "star" and if you want to get notified of the progress you shoul= d click "follow". Regards, Lars Asplund From newsfish@newsfish Thu Aug 1 00:32:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Open source unit testing framework release Date: Wed, 18 Feb 2015 13:28:21 +0000 (UTC) Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 18 Feb 2015 13:28:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="31819"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18auCIgHIWZHSO6A3wz0LBBc2Ls5KZ+3Ok=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:pxphUnkRe1USmTIf887dZq24P4w= Xref: news.eternal-september.org comp.lang.vhdl:3584 On Tue, 17 Feb 2015 09:50:28 -0800, Lars Asplund wrote: > Hi, > > VUnit, an unit testing framework for VHDL, is now freely available on > github (https://github.com/LarsAsplund/vunit). It is released under the > business-friendly Mozilla Public License, v. 2.0 and features the > functionality needed to realize continuous and automated testing of your > VHDL code. VUnit doesn't replace but rather complements traditional > testing methodologies by supporting a "test early and often" approach > through automation. Interesting - another user of OSVVM too... You may be interested to know that as of ghdl-0.32 (not yet released but buildable from source for most systems : Mac OSX is giving a little trouble), ghdl understands enough VHDL-2008 to support OSVVM. Should be easy to integrate into Vunit... https://sourceforge.net/projects/ghdl-updates/?source=navbar -- Brian From newsfish@newsfish Thu Aug 1 00:32:32 2024 X-Received: by 10.50.176.202 with SMTP id ck10mr183152igc.5.1424267996593; Wed, 18 Feb 2015 05:59:56 -0800 (PST) X-Received: by 10.140.92.226 with SMTP id b89mr3981qge.29.1424267996424; Wed, 18 Feb 2015 05:59:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no18387490igb.0!news-out.google.com!n6ni9qar.0!nntp.google.com!j7no1332388qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Feb 2015 05:59:56 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1659df2a-9c50-4095-a689-a62d5bb57789@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Wed, 18 Feb 2015 13:59:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3585 Den onsdag 18 februari 2015 kl. 14:29:02 UTC+1 skrev Brian Drummond: > On Tue, 17 Feb 2015 09:50:28 -0800, Lars Asplund wrote: >=20 > > Hi, > >=20 > > VUnit, an unit testing framework for VHDL, is now freely available on > > github (https://github.com/LarsAsplund/vunit). It is released under the > > business-friendly Mozilla Public License, v. 2.0 and features the > > functionality needed to realize continuous and automated testing of you= r > > VHDL code. VUnit doesn't replace but rather complements traditional > > testing methodologies by supporting a "test early and often" approach > > through automation. >=20 > Interesting - another user of OSVVM too... >=20 > You may be interested to know that as of ghdl-0.32 (not yet released but= =20 > buildable from source for most systems : Mac OSX is giving a little=20 > trouble), ghdl understands enough VHDL-2008 to support OSVVM. Should be= =20 > easy to integrate into Vunit... >=20 > https://sourceforge.net/projects/ghdl-updates/?source=3Dnavbar >=20 > -- Brian Hi Brian, We redistribute OSVVM because it's commonly used and it's convenient for Gi= t users to only do git pull to have the latest version instead of relying o= n the version provided with your simulator or manually download and unzip f= rom osvvm.org. VUnit doesn't require OSVVM to work and it also supports, in addition to VH= DL 2008, the older VHDL 93 and 2002. Our acceptance tests run all these ver= sions of VHDL. We haven't tried VUnit under GHDL (maybe someone else did?) but there is a = question on github (https://github.com/LarsAsplund/vunit/issues/10) regardi= ng what simulator support people would like to see. As I said in my first p= ost I'd like an active community so that we can put our development efforts= where they are best needed. You should place your vote! Regards, Lars From newsfish@newsfish Thu Aug 1 00:32:32 2024 X-Received: by 10.66.237.140 with SMTP id vc12mr1718109pac.44.1424299631249; Wed, 18 Feb 2015 14:47:11 -0800 (PST) X-Received: by 10.140.108.9 with SMTP id i9mr54961qgf.1.1424299631202; Wed, 18 Feb 2015 14:47:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no12707543igb.0!news-out.google.com!n6ni11qar.0!nntp.google.com!j7no1457663qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Feb 2015 14:47:11 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <39eefd4a-d2b8-44f8-aedd-8f1f3f2f0d86@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Wed, 18 Feb 2015 22:47:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 36 Xref: news.eternal-september.org comp.lang.vhdl:3586 Den onsdag 18 februari 2015 kl. 14:29:02 UTC+1 skrev Brian Drummond: > On Tue, 17 Feb 2015 09:50:28 -0800, Lars Asplund wrote: >=20 > > Hi, > >=20 > > VUnit, an unit testing framework for VHDL, is now freely available on > > github (https://github.com/LarsAsplund/vunit). It is released under the > > business-friendly Mozilla Public License, v. 2.0 and features the > > functionality needed to realize continuous and automated testing of you= r > > VHDL code. VUnit doesn't replace but rather complements traditional > > testing methodologies by supporting a "test early and often" approach > > through automation. >=20 > Interesting - another user of OSVVM too... >=20 > You may be interested to know that as of ghdl-0.32 (not yet released but= =20 > buildable from source for most systems : Mac OSX is giving a little=20 > trouble), ghdl understands enough VHDL-2008 to support OSVVM. Should be= =20 > easy to integrate into Vunit... >=20 > https://sourceforge.net/projects/ghdl-updates/?source=3Dnavbar >=20 > -- Brian An addition to my previous post. VUnit is designed to integrate nicely with= Jenkins (https://www.youtube.com/watch?v=3DD8s_VLD91tw) which enables you = to distribute your simulations on several machines. This is never an option= for many due to license costs so a free option would certainly make a diff= erence in that area. However, the majority of our audience sits with Models= im or Aldec so we've focused our initial efforts there. After that I would = like to look into the free alternatives unless someone is willing to make t= hat effort in parallel ;-) /Lars From newsfish@newsfish Thu Aug 1 00:32:33 2024 X-Received: by 10.236.202.207 with SMTP id d55mr5046798yho.4.1424361844696; Thu, 19 Feb 2015 08:04:04 -0800 (PST) X-Received: by 10.140.104.174 with SMTP id a43mr106489qgf.2.1424361844679; Thu, 19 Feb 2015 08:04:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!j7no1681772qaq.1!news-out.google.com!n6ni12qar.0!nntp.google.com!i13no2355320qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Feb 2015 08:04:04 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Thu, 19 Feb 2015 16:04:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 24 Xref: news.eternal-september.org comp.lang.vhdl:3587 Den onsdag 18 februari 2015 kl. 14:29:02 UTC+1 skrev Brian Drummond: > On Tue, 17 Feb 2015 09:50:28 -0800, Lars Asplund wrote: > > > Hi, > > > > VUnit, an unit testing framework for VHDL, is now freely available on > > github (https://github.com/LarsAsplund/vunit). It is released under the > > business-friendly Mozilla Public License, v. 2.0 and features the > > functionality needed to realize continuous and automated testing of your > > VHDL code. VUnit doesn't replace but rather complements traditional > > testing methodologies by supporting a "test early and often" approach > > through automation. > > Interesting - another user of OSVVM too... > > You may be interested to know that as of ghdl-0.32 (not yet released but > buildable from source for most systems : Mac OSX is giving a little > trouble), ghdl understands enough VHDL-2008 to support OSVVM. Should be > easy to integrate into Vunit... > > https://sourceforge.net/projects/ghdl-updates/?source=navbar > > -- Brian @Brian Please join the VUnit with GHDL discussion on this thread: https://github.com/LarsAsplund/vunit/issues/10 Some requirements on GHDL are being discussed From newsfish@newsfish Thu Aug 1 00:32:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Open source unit testing framework release Date: Fri, 20 Feb 2015 10:47:04 +0000 (UTC) Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 20 Feb 2015 10:47:04 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="18148"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18a8hZgo88L0EUtu9jRNrJFWx7pGsMW5X0=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:/4ENvPn5FWlpGima6nRzCch3Bos= Xref: news.eternal-september.org comp.lang.vhdl:3588 On Thu, 19 Feb 2015 08:04:04 -0800, Lars Asplund wrote: > > @Brian Please join the VUnit with GHDL discussion on this thread: > https://github.com/LarsAsplund/vunit/issues/10 Some requirements on GHDL > are being discussed I'll have to subscribe to Github before I respond there. Probably the best thing would be to file a ticket - enhancement request - at https://sourceforge.net/p/ghdl-updates/tickets/?source=navbar It sounds like a reasonable facility to add. Thanks From newsfish@newsfish Thu Aug 1 00:32:33 2024 X-Received: by 10.182.94.204 with SMTP id de12mr9658171obb.13.1424433114503; Fri, 20 Feb 2015 03:51:54 -0800 (PST) X-Received: by 10.140.31.134 with SMTP id f6mr175068qgf.33.1424433114472; Fri, 20 Feb 2015 03:51:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl2no13439487igb.0!news-out.google.com!n6ni12qar.0!nntp.google.com!i13no2540938qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Feb 2015 03:51:54 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <236c4dcb-ae8f-40ef-ad22-b1b5e823eb87@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Fri, 20 Feb 2015 11:51:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3589 Den fredag 20 februari 2015 kl. 11:47:46 UTC+1 skrev Brian Drummond: > On Thu, 19 Feb 2015 08:04:04 -0800, Lars Asplund wrote: > > > > > @Brian Please join the VUnit with GHDL discussion on this thread: > > https://github.com/LarsAsplund/vunit/issues/10 Some requirements on GHDL > > are being discussed > > I'll have to subscribe to Github before I respond there. > > Probably the best thing would be to file a ticket - enhancement request - > at > https://sourceforge.net/p/ghdl-updates/tickets/?source=navbar > > It sounds like a reasonable facility to add. > > Thanks Just my thought. I will do that. /Lars From newsfish@newsfish Thu Aug 1 00:32:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Open source unit testing framework release Date: Sat, 21 Feb 2015 12:32:17 +0000 (UTC) Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> <236c4dcb-ae8f-40ef-ad22-b1b5e823eb87@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 21 Feb 2015 12:32:17 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="7839"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19OIeeuVbATQbHQuP8syqyv7FN7hZmOSs0=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:hFe+Rojj2XJapDx6HnSMr1sndeI= Xref: news.eternal-september.org comp.lang.vhdl:3590 On Fri, 20 Feb 2015 03:51:54 -0800, Lars Asplund wrote: > Den fredag 20 februari 2015 kl. 11:47:46 UTC+1 skrev Brian Drummond: >> Probably the best thing would be to file a ticket - enhancement request >> It sounds like a reasonable facility to add. > Just my thought. I will do that. and Tristan has agreed to add it... -- Brian From newsfish@newsfish Thu Aug 1 00:32:34 2024 X-Received: by 10.182.246.73 with SMTP id xu9mr2424898obc.17.1424523541780; Sat, 21 Feb 2015 04:59:01 -0800 (PST) X-Received: by 10.140.36.134 with SMTP id p6mr5045qgp.26.1424523541671; Sat, 21 Feb 2015 04:59:01 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no14595753igb.0!news-out.google.com!c1ni8qar.1!nntp.google.com!i13no3093732qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 21 Feb 2015 04:59:01 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> <236c4dcb-ae8f-40ef-ad22-b1b5e823eb87@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6de78f57-a634-4773-926b-05bc7a220cc5@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Sat, 21 Feb 2015 12:59:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 16 Xref: news.eternal-september.org comp.lang.vhdl:3591 Den l=F6rdag 21 februari 2015 kl. 13:33:03 UTC+1 skrev Brian Drummond: > On Fri, 20 Feb 2015 03:51:54 -0800, Lars Asplund wrote: >=20 > > Den fredag 20 februari 2015 kl. 11:47:46 UTC+1 skrev Brian Drummond: >=20 > >> Probably the best thing would be to file a ticket - enhancement reques= t > >> It sounds like a reasonable facility to add. > > Just my thought. I will do that. >=20 > and Tristan has agreed to add it... >=20 > -- Brian Great! Thanks.=20 Lars From newsfish@newsfish Thu Aug 1 00:32:34 2024 X-Received: by 10.182.111.132 with SMTP id ii4mr17402168obb.2.1424797777671; Tue, 24 Feb 2015 09:09:37 -0800 (PST) X-Received: by 10.50.110.101 with SMTP id hz5mr281842igb.6.1424797777498; Tue, 24 Feb 2015 09:09:37 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no27765940igb.0!news-out.google.com!db6ni36953igc.0!nntp.google.com!hl2no27765930igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Feb 2015 09:09:36 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> Subject: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Tue, 24 Feb 2015 17:09:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3156 X-Received-Body-CRC: 1810898056 Xref: news.eternal-september.org comp.lang.vhdl:3592 Hi Jim, glen, JK, rickman, Mike, Andy,=20 I have filed a provisional patent application: "Systematic method of coding= wave pipelined circuits in HDL". If it is proved correct, the patent will = introduce 1 keyword, 3 permanent constants, 1 concurrent statement and four= source code modules for a new library in HDL and thoroughly resolve a pend= ing problem so that every digital designer can code wave-pipelined circuits= in HDL. Here is the abstract of the invention: The present invention classifies all critical paths into two basic type= s: a series critical path and a feedback critical path, and divides each of= wave-pipelined circuits into two components: a static logic part, called c= ritical path component (CPC), and a dynamic logic part, formalized into fou= r wave-pipelining components (WPC) shared by all wave-pipelined circuits. E= ach wave-pipelining ready code in HDL comprises two components: a WPC insta= ntiation and a CPC instantiation wire-connected and linked by a new link st= atement. Each WPC has new wave constants which play the same role as generi= c constants do, but whose initial values are determined and assigned by a s= ynthesizer after code analysis, so designers can use after-synthesization i= nformation in their code before synthesization for wave-pipelining technolo= gy. The responsibility of analyzing and manipulating wave-pipelining ready = code, generating and implementing wave-pipelined circuits on a design-wide = or chip-wide scale in HDL is shifted from designers to synthesizers. Anyone who are interested in its content is welcome to send a email request= to the following email address: wtx wtx @ gmail . com with title "Systemat= ic" and he will receive the full documents: one specification, 9 drawings a= nd one text file in VHDL. If one reviews the files and feels that it would be a good thing to recomme= nd the application to his company to buy it, the first person to do it afte= r his recommended company does so will receive $10,000 commission fee. Thank you. Weng From newsfish@newsfish Thu Aug 1 00:32:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Svenn Newsgroups: comp.lang.vhdl Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL Date: Thu, 26 Feb 2015 12:37:34 +0100 Organization: Aioe.org NNTP Server Lines: 10 Message-ID: References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> NNTP-Posting-Host: tDMmuv6iTFrCTcEz1T/Pnw.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.3.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3593 On 24/02/15 18:09, Weng Tianxiang wrote: > If one reviews the files and feels that it would be a good thing to recommend the application > to his company to buy it, the first person to do it after his recommended company does so > will receive $10,000 commission fee. In my country, I would go to jail for doing so. -- Svenn From newsfish@newsfish Thu Aug 1 00:32:35 2024 X-Received: by 10.236.222.103 with SMTP id s97mr8710686yhp.19.1424970309516; Thu, 26 Feb 2015 09:05:09 -0800 (PST) X-Received: by 10.50.129.98 with SMTP id nv2mr230272igb.1.1424970309333; Thu, 26 Feb 2015 09:05:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no8367616qae.0!news-out.google.com!qk8ni43839igc.0!nntp.google.com!hl2no32071864igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Feb 2015 09:05:08 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <99da35c2-083f-49e5-a2ea-0f88688f7409@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Thu, 26 Feb 2015 17:05:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1910 X-Received-Body-CRC: 423788661 Xref: news.eternal-september.org comp.lang.vhdl:3594 On Thursday, February 26, 2015 at 3:37:37 AM UTC-8, Svenn Are Bjerkem wrote: > On 24/02/15 18:09, Weng Tianxiang wrote: > > If one reviews the files and feels that it would be a good thing to recommend the application > > to his company to buy it, the first person to do it after his > recommended company does so > > will receive $10,000 commission fee. > > In my country, I would go to jail for doing so. > > -- > Svenn Svenn, Do it following your company bylaw: 1. The recommendation does benefit your company. 2. Tell your company the commission fee. If your company agree you can accept it; if not abandon it. 3. Pay due tax properly. I am not generate a crime scene for you to do the wrong thing. Weng From newsfish@newsfish Thu Aug 1 00:32:35 2024 X-Received: by 10.236.4.134 with SMTP id 6mr10611812yhj.35.1425002593664; Thu, 26 Feb 2015 18:03:13 -0800 (PST) X-Received: by 10.50.222.75 with SMTP id qk11mr34293igc.0.1425002593372; Thu, 26 Feb 2015 18:03:13 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j7no8048387qaq.1!news-out.google.com!qk8ni43055igc.0!nntp.google.com!hl2no26478065igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Feb 2015 18:03:12 -0800 (PST) In-Reply-To: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Fri, 27 Feb 2015 02:03:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 8179 X-Received-Body-CRC: 642128293 Xref: news.eternal-september.org comp.lang.vhdl:3595 On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wrote: > Hi Jim, glen, JK, rickman, Mike, Andy,=20 >=20 > I have filed a provisional patent application: "Systematic method of codi= ng wave pipelined circuits in HDL". If it is proved correct, the patent wil= l introduce 1 keyword, 3 permanent constants, 1 concurrent statement and fo= ur source code modules for a new library in HDL and thoroughly resolve a pe= nding problem so that every digital designer can code wave-pipelined circui= ts in HDL. >=20 > Here is the abstract of the invention: >=20 > The present invention classifies all critical paths into two basic ty= pes: a series critical path and a feedback critical path, and divides each = of wave-pipelined circuits into two components: a static logic part, called= critical path component (CPC), and a dynamic logic part, formalized into f= our wave-pipelining components (WPC) shared by all wave-pipelined circuits.= Each wave-pipelining ready code in HDL comprises two components: a WPC ins= tantiation and a CPC instantiation wire-connected and linked by a new link = statement. Each WPC has new wave constants which play the same role as gene= ric constants do, but whose initial values are determined and assigned by a= synthesizer after code analysis, so designers can use after-synthesization= information in their code before synthesization for wave-pipelining techno= logy. The responsibility of analyzing and manipulating wave-pipelining read= y code, generating and implementing wave-pipelined circuits on a design-wid= e or chip-wide scale in HDL is shifted from designers to synthesizers. >=20 > Anyone who are interested in its content is welcome to send a email reque= st to the following email address: wtx wtx @ gmail . com with title "System= atic" and he will receive the full documents: one specification, 9 drawings= and one text file in VHDL. >=20 > If one reviews the files and feels that it would be a good thing to recom= mend the application to his company to buy it, the first person to do it af= ter his recommended company does so will receive $10,000 commission fee. >=20 > Thank you. >=20 > Weng Hi, I want to add some introductions to what the wave-pipelined circuits are an= d their status. [0003] A synchronous digital system contains a lot of registers. Valid d= ata flow through successive registers from system input registers to system= output registers. All data flows are synchronous with triggering edges of = a chip clock. For example, data flow from registers A to registers B, from = registers B to registers C and so on in a successive order on the same cloc= k cycle. [0004] A path in a synchronous digital system is a route between any nei= ghboring registers connected by combinational logic. If the target running = frequency for a digital design is predetermined, the upper limit of propaga= ting time for any paths is determined and has the inverse value of the targ= et running frequency. A path is called a critical path if the time signals = take to propagate through it is beyond the predetermined propagating time, = and the time is called the path's critical time. If there are any critical = paths, digital designers must spend time reducing all critical times by all= means and eliminating all critical paths to meet the target running freque= ncy. [0005] Wave-pipelining is a technology which completes an operation that= needs several clock cycles to propagate without intermediate registers and= with input data acceptable on every clock cycle. For example, in a convent= ional pipelining operation, data flow from registers A to registers D throu= gh registers B and C to divide the critical path time into multiple smaller= intervals to meet the critical time: A to B to C to D; with wave-pipelinin= g, data flow through registers A and D without intermediate registers B and= C. Absolutely, wave-pipelining will reduce logic resource usage and is sup= erior to the conventional pipelining technology if it can be used. Here are the most important inequalities involving wave-pipelining from pap= er "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burleson e= t al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, no. 3, = pp. 464-474, Sep. 1998. [0018] Currently many memory chip manufacturers successfully use wave-pi= pelining in their memory chip products with higher rate outputs, reduced po= wer consumption and logic resources; and a few scientists use FPGA chips as= a base to show some circuits can be done with wave-pipelining in isolated = environments. Their works prove that the wave-pipelining is a very powerful= tool to reduce power consumption and logic resources. Now there are two ma= jor existing obstacles preventing any ordinary digital designers from using= the wave-pipelining in HDL: * The software algorithms making wave-pipelining successful, like Wong and = Klass algorithms and others, have already been developed and matured, but o= rdinary digital designers have no means or resources to access to the techn= ology, because there are no international HDL standards on how synthesizer = manufacturers incorporate those capabilities into their products. * HDL needs the capabilities for digital designers to write wave-pipelining= ready code for any number of critical paths on a design-wide or chip-wide = scale instead of in an isolated environment and the written code can be ide= ntified, synthesized and used to generate wave-pipelined circuits by any sy= nthesizer in ASIC or FPGA, and they should be part of HDL standards.=20 [0019] The target of the present invention is: * Invent a wave-pipelining coding system as new part of HDL standards for d= esigners to write wave-pipelining ready code which can be identified, synth= esized and used to generate wave-pipelined circuits by any synthesizer in A= SIC or FPGA. * Make wave-pipelining ready code written based on the coding system workin= g with no extra logic generated, compared with independently written wave-p= ipelined circuits, and with no code changes when switching from non-wave-pi= pelined mode to wave-pipelined mode or vice verse if all of wave-pipelining= ready code meet wave-pipelining requirements.=20 * Shift burdens of analyzing and manipulating wave-pipelining ready code, g= enerating and implementing wave-pipelined circuits on a design-wide or chip= -wide scale in HDL from individual designers to synthesizer manufacturers. [0020] If the coding system becomes new part of HDL standards all synthe= sizer manufactures will automatically be forced to implement all well-known= wave-pipelining algorithms and techniques within their products, a competi= tion will start for better implementations, making wave-pipelining techniqu= e available to every digital designer in HDL. Weng From newsfish@newsfish Thu Aug 1 00:32:35 2024 X-Received: by 10.66.224.42 with SMTP id qz10mr14844184pac.0.1425066693234; Fri, 27 Feb 2015 11:51:33 -0800 (PST) X-Received: by 10.140.33.202 with SMTP id j68mr241019qgj.27.1425066692965; Fri, 27 Feb 2015 11:51:32 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no28029101igb.0!news-out.google.com!n6ni190qar.0!nntp.google.com!j7no8768170qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Feb 2015 11:51:32 -0800 (PST) In-Reply-To: <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Fri, 27 Feb 2015 19:51:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 23 Xref: news.eternal-september.org comp.lang.vhdl:3596 On Thursday, February 26, 2015 at 9:03:15 PM UTC-5, Weng Tianxiang wrote: > [0020] If the coding system becomes new part of HDL standards all > synthesizer manufactures will automatically be forced to implement all we= ll- > known wave-pipelining algorithms and techniques within their products, a= =20 > competition will start for better implementations, making wave-pipelining= =20 > technique available to every digital designer in HDL. >=20 A couple of problems with your assumptions: - No standard body will accept a patent burdened idea to incorporate into a= new revision of a standard. You would likely have to effectively surrende= r your patent rights (should they be granted in the first place) in order t= o get this to happen. - If you think that simply being part of a standard will force synthesis ve= ndors to do anything at all, you're very mistaken. - Wave pipelining has not caught on with FPGA suppliers in the 45 years sin= ce the concept was first introduced nor in the 16 years since Burleson's pa= per was published so uptake on the technique has not been very quick. That= doesn't imply that it will never catch on, but it does suggest the wait wi= ll be significant. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:36 2024 X-Received: by 10.50.29.6 with SMTP id f6mr5146616igh.2.1425073598081; Fri, 27 Feb 2015 13:46:38 -0800 (PST) X-Received: by 10.50.72.37 with SMTP id a5mr120782igv.9.1425073598004; Fri, 27 Feb 2015 13:46:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!hl2no34595309igb.0!news-out.google.com!qk8ni43055igc.0!nntp.google.com!hl2no28217588igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Feb 2015 13:46:37 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Fri, 27 Feb 2015 21:46:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 41 Xref: news.eternal-september.org comp.lang.vhdl:3597 On Friday, February 27, 2015 at 11:51:37 AM UTC-8, KJ wrote: > On Thursday, February 26, 2015 at 9:03:15 PM UTC-5, Weng Tianxiang wrote: > > [0020] If the coding system becomes new part of HDL standards all > > synthesizer manufactures will automatically be forced to implement all = well- > > known wave-pipelining algorithms and techniques within their products, = a=20 > > competition will start for better implementations, making wave-pipelini= ng=20 > > technique available to every digital designer in HDL. > >=20 > A couple of problems with your assumptions: > - No standard body will accept a patent burdened idea to incorporate into= a new revision of a standard. You would likely have to effectively surren= der your patent rights (should they be granted in the first place) in order= to get this to happen. I don't have experience with it and will do some research on it. > - If you think that simply being part of a standard will force synthesis = vendors to do anything at all, you're very mistaken. It's not my business. I invent something and let others do their part. As I= often see Jim calling for help to do something with new standard implement= ations from manufacturers. > - Wave pipelining has not caught on with FPGA suppliers in the 45 years s= ince the concept was first introduced nor in the 16 years since Burleson's = paper was published so uptake on the technique has not been very quick. Th= at doesn't imply that it will never catch on, but it does suggest the wait = will be significant. You are right. In 2002 I published a paper "HDL code inefficient sourses an= d its solutions", introducing 5 keywords "orif, elsor, errels, machine and = exclusive", and they are incorporated into Verilog-2008 and VHDL-2008/2009,= according to Jim's comment, that takes 6 years to become standards. Weng >=20 > Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:36 2024 X-Received: by 10.236.4.100 with SMTP id 64mr17298047yhi.43.1425119004342; Sat, 28 Feb 2015 02:23:24 -0800 (PST) X-Received: by 10.140.86.85 with SMTP id o79mr79996qgd.36.1425119004296; Sat, 28 Feb 2015 02:23:24 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed4a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i13no9993769qae.0!news-out.google.com!c1ni203qar.1!nntp.google.com!i13no9993767qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Feb 2015 02:23:24 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> Subject: PSL help please From: niv Injection-Date: Sat, 28 Feb 2015 10:23:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 90 Xref: news.eternal-september.org comp.lang.vhdl:3598 How do I write PSL assertion for the following code? The idea is that if I/p sig is active for a certain time (number of clock cycles), an o/p is permanently set: Here's some noddy code for the idea: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.NUMERIC_STD.ALL; ENTITY limit_resp IS PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; stim_1 : IN STD_LOGIC; resp_1 : OUT STD_LOGIC ); END ENTITY limit_resp ; -- ARCHITECTURE rtl OF limit_resp IS SIGNAL clk_enable : STD_LOGIC; SIGNAL clk_en_cntr : UNSIGNED(3 DOWNTO 0); SIGNAL counter : UNSIGNED(7 DOWNTO 0); BEGIN -------------------------------------------------------------------------------- -- Generate a clock enable signal at 1/10 clock rate. -------------------------------------------------------------------------------- clk_en_gen:PROCESS(rst, clk) BEGIN IF rst = '1' THEN clk_enable <= '0'; clk_en_cntr <= TO_UNSIGNED(0,4); ELSIF rising_edge(clk) THEN IF clk_en_cntr = TO_UNSIGNED(9,4) THEN clk_enable <= '1'; clk_en_cntr <= TO_UNSIGNED(0,4); ELSE clk_enable <= '0'; clk_en_cntr <= clk_en_cntr + 1; END IF; END IF; END PROCESS clk_en_gen; -------------------------------------------------------------------------------- -- Count up to some arbitrary value (for this test) -------------------------------------------------------------------------------- count_up:PROCESS(rst, clk) BEGIN IF rst = '1' THEN counter <= TO_UNSIGNED(0,8); ELSIF rising_edge(clk) THEN IF clk_enable = '1' THEN IF stim_1 = '1' THEN IF counter < 200 THEN counter <= counter + 1; END IF; ELSE counter <= TO_UNSIGNED(0,8); END IF; END IF; END IF; END PROCESS count_up; -------------------------------------------------------------------------------- -- If counter has maxed out, set the output high (forever, unless master reset) -- i.e. if the counter ever reaches its max (200) then the output is set, -- regardless of whether the input stim subsequently is removed. -------------------------------------------------------------------------------- set_output:PROCESS(rst, clk) BEGIN IF rst = '1' THEN resp_1 <= '0'; ELSIF rising_edge(clk) THEN IF counter = 200 THEN resp_1 <= '1'; END IF; END IF; END PROCESS set_output; -------------------------------------------------------------------------------- -- Now include a PSL assertion to test the following; -- -- If stim is set for "N" clock cycles (or more) (2000 in this example), -- then the "resp" output is set. -- HELP REQUIRED FOR THE BELOW PLEASE! -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- psl begin -- default clock is rising_edge(clk); -- -- -- end -------------------------------------------------------------------------------- END ARCHITECTURE rtl; Regards, Niv From newsfish@newsfish Thu Aug 1 00:32:36 2024 X-Received: by 10.70.42.170 with SMTP id p10mr21456252pdl.3.1425209556057; Sun, 01 Mar 2015 03:32:36 -0800 (PST) X-Received: by 10.50.25.202 with SMTP id e10mr210949igg.4.1425209555915; Sun, 01 Mar 2015 03:32:35 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl2no1775695igb.0!news-out.google.com!qk8ni45613igc.0!nntp.google.com!hl2no1775692igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Mar 2015 03:32:35 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.139.181.229; posting-account=KO-KNwkAAADC2mbnvzGpph7FQxwtXLlX NNTP-Posting-Host: 14.139.181.229 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <722555e0-c905-4a95-ae89-7fdba680a470@googlegroups.com> Subject: How different is the synthesized results of for loop and for generate? From: Deepak kumar Singhaniya Injection-Date: Sun, 01 Mar 2015 11:32:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3599 Hi, Why is it that only concurrent statements are allowed to use within for generate? I want to understand the difference between for loop and for generate so that I can be aware of what I will synthesizing. From newsfish@newsfish Thu Aug 1 00:32:37 2024 X-Received: by 10.182.96.131 with SMTP id ds3mr21611232obb.35.1425233151288; Sun, 01 Mar 2015 10:05:51 -0800 (PST) X-Received: by 10.140.36.134 with SMTP id p6mr309308qgp.26.1425233151140; Sun, 01 Mar 2015 10:05:51 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no2006950igb.0!news-out.google.com!c1ni203qar.1!nntp.google.com!i13no10668394qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Mar 2015 10:05:50 -0800 (PST) In-Reply-To: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=190.247.132.79; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 190.247.132.79 References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: PSL help please From: Leonardo Capossio Injection-Date: Sun, 01 Mar 2015 18:05:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 10 Xref: news.eternal-september.org comp.lang.vhdl:3600 Using ModelSim embedded PSL syntax: --PSL property resp_check is always( {counter = 200} |=> {resp_1} ) abort rst; then assert the property: --PSL assert_resp_check: assert resp_check report "resp_1 is not working!!!"; If you are using VHDL-2008 PSL probably syntax would be a little different, never investigated this. Use this as a starting point, I haven't used PSL in a while, and even if I have, verification also needs debugging. From newsfish@newsfish Thu Aug 1 00:32:37 2024 X-Received: by 10.66.252.138 with SMTP id zs10mr24656691pac.3.1425255767427; Sun, 01 Mar 2015 16:22:47 -0800 (PST) X-Received: by 10.50.239.165 with SMTP id vt5mr232847igc.5.1425255767224; Sun, 01 Mar 2015 16:22:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no1921480igb.0!news-out.google.com!qk8ni45613igc.0!nntp.google.com!hl2no2216357igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Mar 2015 16:22:46 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: diogratia@gmail.com Injection-Date: Mon, 02 Mar 2015 00:22:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2802 X-Received-Body-CRC: 822894985 Xref: news.eternal-september.org comp.lang.vhdl:3601 On Saturday, February 28, 2015 at 10:46:43 AM UTC+13, Weng Tianxiang wrote: > You are right. In 2002 I published a paper "HDL code inefficient sourses = and its solutions", introducing 5 keywords "orif, elsor, errels, machine an= d exclusive", and they are incorporated into Verilog-2008 and VHDL-2008/200= 9, according to Jim's comment, that takes 6 years to become standards. None of those are reserved words in IEEE Std 1076-2008 (published in 2009). See Issue Report 2012 http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- No change. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Forward the submitter's request to the VHDL-200x Modeling and Productivity group for consideration. You'd be hard pressed to find any record that a 'VHDL-200x Modeling and Productivity group' considered your issue. This would have been under the = auspices of Accellera's VHDL activities and all those records are not avail= able today. There is a Unique Condition proposal encompassing IR2012: http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition It doesn't appear to be currently gaining a lot of traction. Searching IEEE std 1800-2012 (SystemVerilog) shows they aren't keywords the= re either. (Note there is unique and unique0). (See Annex B Keywords) From newsfish@newsfish Thu Aug 1 00:32:37 2024 X-Received: by 10.66.171.9 with SMTP id aq9mr25902721pac.20.1425273093824; Sun, 01 Mar 2015 21:11:33 -0800 (PST) X-Received: by 10.50.1.113 with SMTP id 17mr244657igl.8.1425273093622; Sun, 01 Mar 2015 21:11:33 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no1964410igb.0!news-out.google.com!qk8ni45613igc.0!nntp.google.com!hl2no2317018igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Mar 2015 21:11:33 -0800 (PST) In-Reply-To: <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Mon, 02 Mar 2015 05:11:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3602 On Sunday, March 1, 2015 at 4:22:50 PM UTC-8, diog...@gmail.com wrote: > On Saturday, February 28, 2015 at 10:46:43 AM UTC+13, Weng Tianxiang wrot= e: >=20 > > You are right. In 2002 I published a paper "HDL code inefficient sourse= s and its solutions", introducing 5 keywords "orif, elsor, errels, machine = and exclusive", and they are incorporated into Verilog-2008 and VHDL-2008/2= 009, according to Jim's comment, that takes 6 years to become standards. >=20 > None of those are reserved words in IEEE Std 1076-2008 (published in 2009= ). >=20 > See Issue Report 2012 > http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt >=20 > VASG-ISAC Recommendation for IEEE Std 1076-2002 > ----------------------------------------------- >=20 > No change. >=20 >=20 > VASG-ISAC Recommendation for Future Revisions > --------------------------------------------- >=20 > Forward the submitter's request to the VHDL-200x Modeling and > Productivity group for consideration. >=20 > You'd be hard pressed to find any record that a 'VHDL-200x Modeling and > Productivity group' considered your issue. This would have been under th= e auspices of Accellera's VHDL activities and all those records are not ava= ilable today. >=20 > There is a Unique Condition proposal encompassing IR2012: > http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition >=20 > It doesn't appear to be currently gaining a lot of traction. >=20 > Searching IEEE std 1800-2012 (SystemVerilog) shows they aren't keywords t= here either. (Note there is unique and unique0). (See Annex B Keywords) Thank you for your valuable comment. Jim, the current chairman of VHDL committee, told me the information. I will response to you comment a few days later and hope to make some contr= ibutions to SystemVerilog-2012. Weng From newsfish@newsfish Thu Aug 1 00:32:37 2024 X-Received: by 10.182.29.3 with SMTP id f3mr29214254obh.16.1425325757767; Mon, 02 Mar 2015 11:49:17 -0800 (PST) X-Received: by 10.50.127.232 with SMTP id nj8mr316724igb.0.1425325757566; Mon, 02 Mar 2015 11:49:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no2305321igb.0!news-out.google.com!db6ni40239igc.0!nntp.google.com!hl2no2305319igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Mar 2015 11:49:16 -0800 (PST) In-Reply-To: <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Mon, 02 Mar 2015 19:49:17 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 15459 X-Received-Body-CRC: 1550594812 Xref: news.eternal-september.org comp.lang.vhdl:3603 On Sunday, March 1, 2015 at 9:11:36 PM UTC-8, Weng Tianxiang wrote: > On Sunday, March 1, 2015 at 4:22:50 PM UTC-8, diog...@gmail.com wrote: > > On Saturday, February 28, 2015 at 10:46:43 AM UTC+13, Weng Tianxiang wr= ote: > >=20 > > > You are right. In 2002 I published a paper "HDL code inefficient sour= ses and its solutions", introducing 5 keywords "orif, elsor, errels, machin= e and exclusive", and they are incorporated into Verilog-2008 and VHDL-2008= /2009, according to Jim's comment, that takes 6 years to become standards. > >=20 > > None of those are reserved words in IEEE Std 1076-2008 (published in 20= 09). > >=20 > > See Issue Report 2012 > > http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt > >=20 > > VASG-ISAC Recommendation for IEEE Std 1076-2002 > > ----------------------------------------------- > >=20 > > No change. > >=20 > >=20 > > VASG-ISAC Recommendation for Future Revisions > > --------------------------------------------- > >=20 > > Forward the submitter's request to the VHDL-200x Modeling and > > Productivity group for consideration. > >=20 > > You'd be hard pressed to find any record that a 'VHDL-200x Modeling and > > Productivity group' considered your issue. This would have been under = the auspices of Accellera's VHDL activities and all those records are not a= vailable today. > >=20 > > There is a Unique Condition proposal encompassing IR2012: > > http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition > >=20 > > It doesn't appear to be currently gaining a lot of traction. > >=20 > > Searching IEEE std 1800-2012 (SystemVerilog) shows they aren't keywords= there either. (Note there is unique and unique0). (See Annex B Keywords) >=20 > Thank you for your valuable comment. >=20 > Jim, the current chairman of VHDL committee, told me the information. >=20 > I will response to you comment a few days later and hope to make some con= tributions to SystemVerilog-2012. >=20 > Weng Thank you very much for your comment. 0. I don't have any written versions of Verilog-2008 or VHDL-2008/2009. The information I listed in my comment was based on Jim Lewis's comment, th= e chairman of current VHDL committee.=20 His comment happened in about 2010 and I cannot find it again now. But you = may see the following comments: https://groups.google.com/forum/#!topic/comp.lang.vhdl/V1ZeRkQ-El4 1. "This would have been under the auspices of Accellera's VHDL activities = and all those records are not available today.? You are right. Jim Lewis is the current chairman of Accellera's VHDL and th= e first man mentioned reserved word "errels". 2. "None of those are reserved words in IEEE Std 1076-2008 (published in 20= 09)." It must be the situation that those reserved words mentioned in my paper we= re incorporated into IEEE Std 1076-2008 (published in 2009) using different= names. I was not contacted in their incorporation activities. Jim Lewis wi= ll clear that later. 3. "See Issue Report 2012 http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt" This request was made by me in 2001. It doesn't mean anything now, because = it occurred in 2002 and we are talking about Verilog-2008 and VHDL-2008/200= 9. 4. In http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition=20 Current Situation section clearly describes the situation and what the targ= et is, but the application range is narrowed unintentionally: "In those above 3 situations, a superfluous condition is posed on the equat= ion; it means a priority tree is implied in all three situations. Actually = most of time when dealing with main data flow, all above conditions are mut= ually exclusive, so there is no need to pose the extra conditions on the fi= nal equation." The above situation occurs not only in main data flow, but also occurs when= dealing with logic flow in a non-clocked state machine process. 5. There are two errors in section of Implementation:=20 "The proposed solution is to introduce a new keyword 'elsor', which implies= that the conditions are mutually exclusive. The keyword would have to be u= sed throughout the statement, and imply that all the conditions are mutuall= y exclusive. The question of checking whether none of the conditions have b= een met can be handled by an assertion.? 5.1. New keyword "elsor" can be nested, and has not to be used throughou= t the statement. In page 169 of The 11th Annual International HDL Conference, the paper "HDL= Code Inefficiency Sources and its Solutions" describes: "To make HDL code efficient, we should have a way to let HDL compilers know= if there are any partially or totally mutually exclusive conditions contai= ned in "if...elsif...else" statement. The solution is to include two new keywords"orif" and "elsor" in the next H= DL version. "orif" is used in sequential environments and "elsor" in concur= rent environments. Proposal 1: In sequential situations, any "elsif" keyword in "if...elsif...= else" statement may be replaced by new keyword "orif", specifying that cond= itions at any contiguous block of "orif(...)" lines and the condition at "i= f(...)" or "elsif(...) line that is located above the contiguous block of "= orif(...)" lines are mutually exclusive.=20 And a new keyword "errels" can be added after last "orif(...)" line of any = contiguous "orif(...)" blocks to specify what action should be taken when v= iolations of expecting mutually exclusive conditions occur during simulatio= n. All other rules appled to "if...elsif...else" don't change. Example: A : process(clk, nreset) begin if nreset =3D '0' then=20 Outbus <=3D (others=3D>'0'); =20 elsif clk'event and clk =3D '1' then if C1 then -- C1 and C2 are mutually exclusive Outbus <=3D Bus1; orif C2 then Outbus <=3D Bus2; errels -- if both C1 and C2 are true, an error oc= curs Outbus <=3D Outbus ; assert false report "1: mutually exclusive is violated" severity note; elsif C3 then -- C3 and C4 are mutually exclusive Outbus <=3D Bus3; orif C4 then Outbus <=3D Bus4; errels -- if both C3 and C4 are true, an error oc= curs Outbus <=3D Outbus ; assert false report "2: mutually exclusive is violated" severity note; else Outbus <=3D (others=3D>'0'); end if; end if; end process; The above equation tells that (C1 and C2), (C3 and C4) are mutually exclusi= ve. The following equation in AHDL is expected: Outbus <=3D (C1 * Bus1 + C2 * Bus2) + !(C1 + C2) (C3 * Bus3 + C4 * Bus4)= ; The new keyword "orif" is to emphasize that "or" operations are involved to= save logic.=20 Statements following "errels" are skipped in synthesis, but are involved in= simulation. 5.2 =E6=8F=9Fhe question of checking whether none of the conditions have be= en met can be handled by an assertion.? I don=E6=8A=B0 know SystemVerilog, but the above question can be handled= without any additional rules and it can be handled as an usual =E6=90=83f= =E5=8D=90lsif=E5=8D=90lse?does. If one contiguous block of "orif" and its above "if(...)" or "elsif(...)= " is treated as one if-level in a "if...elsif...else" statement, nothing sh= ould have changed. Please see following examples. 5.3. In the above conetext "The 'unique' keyword implies an error if none o= f the conditions is met and there is no 'else', whereas the 'unique0' keywo= rd does not imply this additional check." When no conditions are true in the mutually exclusive group, the situati= on is treated in the same way as how a usual "if...elsif...else" is treated= , but when more than one condition in a mutually exclusive group of conditi= ons is true, an error occurs, that can be detected using "elserr".=20 OneHot0(...) really has the bad effects as the recommendation indicated. 6. Here I give a very useful example showing how the new keyword "orif" is = used and how it would save logic in my unpublished code: If an idle state in a state machine State_2 is monitoring a data bus to = see if the command target address appeared in the bus falls into a designat= ed address space, the code would be: case State_2 is when Idle_s =3D> if Address =3D Area1 then State_2_NS <=3D S1; elsif Address =3D Area2 then State_2_NS <=3D S2; elsif Address =3D Area3 then State_2_NS <=3D S3; elsif Address =3D Area4 then State_2_NS <=3D S4; elsif Address =3D Area5 then State_2_NS <=3D S5; else State_2_NS <=3D Idle_s; end if; =20 end if; ... No experienced designers would write the above dumb code. Because each o= f area addresses can be written as a 32-bits address or so and rewrite the = equation to make them do no more logic comparison than needed. case State_2 is when Idle_s =3D> if Address_H8 =3D Common_address_H8 then case Address_L24 is when Address_L24_1 =3D> State_2_NS <=3D S1; when Address_L24_2 =3D> State_2_NS <=3D S2; when Address_L24_3 =3D> State_2_NS <=3D S3; when Address_L24_4 =3D> State_2_NS <=3D S4; when Address_L24_5 =3D> State_2_NS <=3D S5; when others =3D> State_2_NS <=3D Idle_s; end case; end if; ... =20 Now my problem comes here due to the jump conditions which are mutually exc= lusive and cannot be divided as above example shows. In one state machine State_1 it generates 7 situations which are generated = in one if-statement and mutually exclusive and very complex. In another state machine State_2 it is waiting in idle state to monitor the= progress of State_1 and acts when one of 7 situations occurs. The situations are very common in complex designs. case State_2 is when Idle_S =3D> If situation_1 then State_2_NS <=3D S2_1; elsif situation_2 then State_2_NS <=3D S2_2; elsif situation_3 then State_2_NS <=3D S2_3; elsif situation_4 then State_2_NS <=3D S2_4; elsif situation_5 then State_2_NS <=3D S2_5; elsif situation_6 then State_2_NS <=3D S2_6; elsif situation_7 then State_2_NS <=3D S2_7; else State_2_NS <=3D Idle_S; end if; The above code is unacceptable because all situation_x are mutually exclusi= vely generated in one if-statement in State_1 state machine. What I can do now in State_1 is as follows: code <=3D "000"; -- no action if A1 then code<=3D "001"; -- situation_1 else A2 then -- situation_2 code<=3D "010"; elsif A3 then if A4 then -- situation_3 code<=3D "011"; else A5 then -- situation_4 code<=3D "101"; ... In State_2 I have to use a case statement to simplify the situations as fol= lowing code shows: case State_2 is when Idle_s =3D> case code is when "001" =3D> ...; -- situation_1 when "010" =3D> ...; -- situation_2 when "011" =3D> ...; -- situation_3 when others =3D>Idle_s;-- no action If new keyword "orif" is introduced as my specification tells, the new code= in State_1 would be: situation_1 <=3D '0"; -- situation_1 situation_2 <=3D '0"; -- situation_2 situation_3 <=3D '0"; -- situation_3 situation_4 <=3D '0"; -- situation_4 situation_5 <=3D '0"; -- situation_5 situation_6 <=3D '0"; -- situation_6 situation_7 <=3D '0"; -- situation_7 =20 if A1 then situation_1 <=3D '1"; -- situation_1 else A2 then =20 situation_2 <=3D '1"; -- situation_2 elsif A3 then if A4 then =20 situation_3 <=3D '1"; -- situation_3 else A5 then =20 situation_4 <=3D '1"; -- situation_4 ... =20 the code in State_2 would be: case State_2 is when Idle_s =3D> if situatino_1 =3D '1' then State_2_NS <=3D S1; -- situation_1 orif situatino_2 =3D '1' then State_2_NS <=3D S2; -- situation_2 orif situatino_3 =3D '1' then State_2_NS <=3D S3; -- situation_3 orif situatino_4 =3D '1' then State_2_NS <=3D S4; -- situation_4 orif situatino_5 =3D '1' then State_2_NS <=3D S5; -- situation_5 orif situatino_6 =3D '1' then State_2_NS <=3D S6; -- situation_6 orif situatino_7 =3D '1' then State_2_NS <=3D S7; -- situation_7 errels -- if more than one wire is assert= ed State_2_NS <=3D Idle_s; -- keep State_2 unchanged assert false =20 report "Violation of mutually exclusiveness occurs" severity failure; -- that is what should be done if no condition is true in a contiguous bloc= k of "orif" else =20 State_2_NS <=3D Idle_s; -- keep State_2 unchanged end if; ... =20 =20 Weng From newsfish@newsfish Thu Aug 1 00:32:38 2024 X-Received: by 10.68.104.5 with SMTP id ga5mr27953996pbb.2.1425327469331; Mon, 02 Mar 2015 12:17:49 -0800 (PST) X-Received: by 10.140.32.34 with SMTP id g31mr43610qgg.21.1425327469053; Mon, 02 Mar 2015 12:17:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no2858256igb.0!news-out.google.com!n6ni190qar.0!nntp.google.com!j7no10324956qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Mar 2015 12:17:48 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Mon, 02 Mar 2015 20:17:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2236 X-Received-Body-CRC: 2996557782 Xref: news.eternal-september.org comp.lang.vhdl:3604 On Monday, March 2, 2015 at 2:49:26 PM UTC-5, Weng Tianxiang wrote: > On Sunday, March 1, 2015 at 9:11:36 PM UTC-8, Weng Tianxiang wrote: It looks like you submitted this back in 2001 but the suggestion was not re= commended for a change to VHDL-2002 (http://www.eda.org/isac/IRs-VHDL-2002/= IR2012.txt). It did not make the cut in VHDL-2008 either. Along with any other open proposals, it has been ported over to the current= working group for consideration (http://www.eda.org/twiki/bin/view.cgi/P10= 76/UniqueCondition). That working group has been together for just about 3= years, it's not clear if there is any particular target date that they are= working toward. Kevin From newsfish@newsfish Thu Aug 1 00:32:38 2024 X-Received: by 10.140.231.139 with SMTP id b133mr28881090qhc.1.1425340120421; Mon, 02 Mar 2015 15:48:40 -0800 (PST) X-Received: by 10.50.107.4 with SMTP id gy4mr336696igb.10.1425340120129; Mon, 02 Mar 2015 15:48:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!j7no10369646qaq.1!news-out.google.com!qk8ni45613igc.0!nntp.google.com!hl2no2976871igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Mar 2015 15:48:39 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <97ac969d-1424-44ad-9635-00a15bb055cc@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Mon, 02 Mar 2015 23:48:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 37 Xref: news.eternal-september.org comp.lang.vhdl:3605 On Monday, March 2, 2015 at 12:17:52 PM UTC-8, KJ wrote: > On Monday, March 2, 2015 at 2:49:26 PM UTC-5, Weng Tianxiang wrote: > > On Sunday, March 1, 2015 at 9:11:36 PM UTC-8, Weng Tianxiang wrote: >=20 > It looks like you submitted this back in 2001 but the suggestion was not = recommended for a change to VHDL-2002 (http://www.eda.org/isac/IRs-VHDL-200= 2/IR2012.txt). You are right. >=20 > It did not make the cut in VHDL-2008 either. No, it did make the cut in Verilog-2008 for both groups of new keywords and= in VHDL-2008/2009 for either. Jim Lewis provided me with the info in 2010 or 2011, but I couldn't find hi= s record. I will try again.=20 =20 >=20 > Along with any other open proposals, it has been ported over to the curre= nt working group for consideration (http://www.eda.org/twiki/bin/view.cgi/P= 1076/UniqueCondition). That working group has been together for just about= 3 years, it's not clear if there is any particular target date that they a= re working toward. You are right. I am very thankful for this SystemVerilog-1012 group. I will= try to publish a paper that will definitely confirm using schematics diagr= ams that "orif" saves logic in such a dramatic way as I claimed. >=20 > Kevin Hi KJ, Thank you for your comment. Weng From newsfish@newsfish Thu Aug 1 00:32:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!lightspeed.eweka.nl!lightspeed.eweka.nl!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx34.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PSL help please References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150302-2, 02/03/2015), Outbound message X-Antivirus-Status: Clean Lines: 23 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1425376487 86.17.210.161 (Tue, 03 Mar 2015 09:54:47 UTC) NNTP-Posting-Date: Tue, 03 Mar 2015 09:54:47 UTC Organization: virginmedia.com Date: Tue, 03 Mar 2015 09:54:46 +0000 X-Received-Body-CRC: 2688360251 X-Received-Bytes: 2114 Xref: news.eternal-september.org comp.lang.vhdl:3606 On 01/03/2015 18:05, Leonardo Capossio wrote: > Using ModelSim embedded PSL syntax: > > --PSL property resp_check is always( {counter = 200} |=> {resp_1} ) abort rst; > > then assert the property: > > --PSL assert_resp_check: assert resp_check report "resp_1 is not working!!!"; > > If you are using VHDL-2008 PSL probably syntax would be a little different, never investigated this. > > Use this as a starting point, I haven't used PSL in a while, and even if I have, verification also needs debugging. > I think the lecturer wants the student to learn about writing bad assertions hence he specifically asked to check for 2000 clock cycles. The counter is the obvious choice but you might not always be aware of what is available in the code. I am not going to give the answer as this is clearly homework. I give kudos to the University (tech college?) for teaching PSL, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:32:38 2024 X-Received: by 10.42.163.8 with SMTP id a8mr2498509icy.2.1425407911901; Tue, 03 Mar 2015 10:38:31 -0800 (PST) X-Received: by 10.140.37.113 with SMTP id q104mr7646qgq.0.1425407911731; Tue, 03 Mar 2015 10:38:31 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no3521917igb.0!news-out.google.com!c1ni204qar.1!nntp.google.com!j7no10581444qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 10:38:31 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> Subject: Re: PSL help please From: niv Injection-Date: Tue, 03 Mar 2015 18:38:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2902 X-Received-Body-CRC: 2513481031 Xref: news.eternal-september.org comp.lang.vhdl:3607 On Tuesday, March 3, 2015 at 9:54:53 AM UTC, HT-Lab wrote: > On 01/03/2015 18:05, Leonardo Capossio wrote: > > Using ModelSim embedded PSL syntax: > > > > --PSL property resp_check is always( {counter = 200} |=> {resp_1} ) abort rst; > > > > then assert the property: > > > > --PSL assert_resp_check: assert resp_check report "resp_1 is not working!!!"; > > > > If you are using VHDL-2008 PSL probably syntax would be a little different, never investigated this. > > > > Use this as a starting point, I haven't used PSL in a while, and even if I have, verification also needs debugging. > > > I think the lecturer wants the student to learn about writing bad > assertions hence he specifically asked to check for 2000 clock cycles. > The counter is the obvious choice but you might not always be aware of > what is available in the code. I am not going to give the answer as > this is clearly homework. > > I give kudos to the University (tech college?) for teaching PSL, > > Hans > www.ht-lab.com Not homework (other than self imposed)! I've been VHDL coding for ~25 years, but just started to grapple with PSL. Bought Cindy Eisner book, which I've started to read & creating my own examples to test myself. So, Leonardo answer worked, sort of, but I've changed the code so the resp_1 o/p is also clocked when clk_enable is '1', so this has caused a set of 9(?) assertion failures between counter = 200 & resp_1 going high. I tried this, which worked, but seems a bit too like the source code? -- property RESP_01 is -- ({counter = 200 AND clk_enable = '1'} |=> {resp_1} abort rst); -- assert always RESP_01 report "ERROR: resp_1 did not go to '1' at count max"; -- Any suggestions welcome! From newsfish@newsfish Thu Aug 1 00:32:39 2024 X-Received: by 10.182.96.131 with SMTP id ds3mr1735944obb.35.1425428068354; Tue, 03 Mar 2015 16:14:28 -0800 (PST) X-Received: by 10.140.81.229 with SMTP id f92mr32218qgd.28.1425428068250; Tue, 03 Mar 2015 16:14:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no3700892igb.0!news-out.google.com!c1ni204qar.1!nntp.google.com!j7no10666969qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 16:14:28 -0800 (PST) In-Reply-To: <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.150.32.12; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 83.150.32.12 References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: PSL help please From: Leonardo Capossio Injection-Date: Wed, 04 Mar 2015 00:14:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3609 El martes, 3 de marzo de 2015, 15:38:35 (UTC-3), niv escribi=F3: > On Tuesday, March 3, 2015 at 9:54:53 AM UTC, HT-Lab wrote: > > On 01/03/2015 18:05, Leonardo Capossio wrote: > > > Using ModelSim embedded PSL syntax: > > > > > > --PSL property resp_check is always( {counter =3D 200} |=3D> {resp_1}= ) abort rst; > > > > > > then assert the property: > > > > > > --PSL assert_resp_check: assert resp_check report "resp_1 is not work= ing!!!"; > > > > > > If you are using VHDL-2008 PSL probably syntax would be a little diff= erent, never investigated this. > > > > > > Use this as a starting point, I haven't used PSL in a while, and even= if I have, verification also needs debugging. > > > > > I think the lecturer wants the student to learn about writing bad=20 > > assertions hence he specifically asked to check for 2000 clock cycles.= =20 > > The counter is the obvious choice but you might not always be aware of= =20 > > what is available in the code. I am not going to give the answer as=20 > > this is clearly homework. > >=20 > > I give kudos to the University (tech college?) for teaching PSL, > >=20 > > Hans > > www.ht-lab.com >=20 > Not homework (other than self imposed)! > I've been VHDL coding for ~25 years, but just started to grapple with PSL= . > Bought Cindy Eisner book, which I've started to read & creating my own ex= amples to test myself. >=20 > So, Leonardo answer worked, sort of,=20 > but I've changed the code so the resp_1 o/p is also clocked when clk_enab= le is '1', so this has caused a set of 9(?) assertion failures between coun= ter =3D 200 & resp_1 going high. >=20 > I tried this, which worked, but seems a bit too like the source code? >=20 > -- property RESP_01 is > -- ({counter =3D 200 AND clk_enable =3D '1'} |=3D> {resp_1} abort rst= ); > -- assert always RESP_01 report "ERROR: resp_1 did not go to '1' at coun= t max"; > -- >=20 >=20 > Any suggestions welcome! Well, you can use that, it is simple, but PSL has many ways of doing the sa= me thing, and in this case some may be more 'correct' than others. Following Hans suggestion, you might not be able to access the counter (you= might want to do this PSL stuff from outside, hence only being able to acc= ess ports), so PSL provides a way for you to check for a condition that may= run in continuous clock cycles or not, for example you could do: --PSL property resp_check is always( {clk_enable[=3D200]} |=3D> {clk_enable= [=3D1]} |-> {resp_1} ) abort rst; The condition part of the implication is that the clock enable is sampled h= igh exactly 200 times every rising edge, and this times CAN be non-consecut= ive (in non-consecutive clock cycles, for them to be consecutive use [*200]= ). Then on the next clock cycle if clk_enable is HIGH exactly one cycle, th= en resp_1 must go HIGH, IN THE SAME CLOCK CYCLE. Try if it works, see this tutorial for more help: http://www.project-veripa= ge.com/psl_tutorial_6.php From newsfish@newsfish Thu Aug 1 00:32:39 2024 X-Received: by 10.182.33.97 with SMTP id q1mr2199389obi.42.1425432306863; Tue, 03 Mar 2015 17:25:06 -0800 (PST) X-Received: by 10.50.112.194 with SMTP id is2mr477497igb.2.1425432306768; Tue, 03 Mar 2015 17:25:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no3727889igb.0!news-out.google.com!qk8ni48798igc.0!nntp.google.com!hl2no3727886igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 17:25:06 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=208.13.76.142; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 208.13.76.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0cfc5822-d51b-456a-8a5d-1669c22b6fad@googlegroups.com> Subject: run-time path instance attribute? From: David Rogoff Injection-Date: Wed, 04 Mar 2015 01:25:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 22 X-Received-Bytes: 2194 X-Received-Body-CRC: 1839135175 Xref: news.eternal-september.org comp.lang.vhdl:3610 Hi all. More VHDL learning curve. I'm trying to copy some SystemVerilog verificati= on code I did a couple of years ago but I'm stuck. I want to report and/or= act based on the hierarchical instance of a procedure. I thought I could = use the 'instance_name attribute but that only statically determined and ju= st tells me the package name where I defined the procedure - not what I wan= t. How do I extra the hierarchical path during run-time? I thought of a way t= o do it using generics but I'd have to rewrite dozens of nested procedures = and functions to plumb a path string down. Not gonna happen. Thanks! David ps - I did find some handy string manipulation in VHDL 2008 (e.g. to_string= (time:) ). I also wrote an slv to string function that adds underscores ev= ery 4 digits to make long numbers readable. I'm working on a similar func= tion that takes a real and outputs a string with commas every 3 digits to t= he left and right of the decimal point. Don't suppose someone already has = this? Extra points for Euro input to swap "." and "," :) From newsfish@newsfish Thu Aug 1 00:32:39 2024 X-Received: by 10.182.248.227 with SMTP id yp3mr2880495obc.22.1425442012840; Tue, 03 Mar 2015 20:06:52 -0800 (PST) X-Received: by 10.182.97.200 with SMTP id ec8mr22353obb.20.1425442012744; Tue, 03 Mar 2015 20:06:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no2912083igb.0!news-out.google.com!qk8ni48798igc.0!nntp.google.com!hl2no3780135igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 20:06:52 -0800 (PST) In-Reply-To: <722555e0-c905-4a95-ae89-7fdba680a470@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <722555e0-c905-4a95-ae89-7fdba680a470@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <76619e15-8eed-4ea8-959d-0bf62201d63a@googlegroups.com> Subject: Re: How different is the synthesized results of for loop and for generate? From: Andy Injection-Date: Wed, 04 Mar 2015 04:06:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1971 X-Received-Body-CRC: 3882658202 Xref: news.eternal-september.org comp.lang.vhdl:3611 A generate is statically bound. A for loop is dynamically bound. They are different structures for different purposes than the sequential if/loop statements, though similar logic can be described using either one. You can use a variable in a for-loop for iterative behavior (updating the same variable over multiple iterations of the loop, such as when calculating parity of an SLV). In synthesis, both are "unrolled" and therefore the loop/generate index is treated as static (i.e. a constant) for each iteration. Note also that a generate statement can contain a declarative region where signals, types, constants, etc. unique to each iteration can be declared. I tend to use for-generate in structural code (e.g. instantiating N copies of an entity), and for-loop in behavioral code (TB or RTL). Andy From newsfish@newsfish Thu Aug 1 00:32:40 2024 X-Received: by 10.236.28.230 with SMTP id g66mr3003659yha.2.1425446804277; Tue, 03 Mar 2015 21:26:44 -0800 (PST) X-Received: by 10.50.118.42 with SMTP id kj10mr130743igb.9.1425446804091; Tue, 03 Mar 2015 21:26:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!k15no23147qaq.1!news-out.google.com!qk8ni48798igc.0!nntp.google.com!hl2no3807233igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 21:26:42 -0800 (PST) In-Reply-To: <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Wed, 04 Mar 2015 05:26:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 13061 X-Received-Body-CRC: 659939989 Xref: news.eternal-september.org comp.lang.vhdl:3612 On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wrote: > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wrote: > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > >=20 > > I have filed a provisional patent application: "Systematic method of co= ding wave pipelined circuits in HDL". If it is proved correct, the patent w= ill introduce 1 keyword, 3 permanent constants, 1 concurrent statement and = four source code modules for a new library in HDL and thoroughly resolve a = pending problem so that every digital designer can code wave-pipelined circ= uits in HDL. > >=20 > > Here is the abstract of the invention: > >=20 > > The present invention classifies all critical paths into two basic = types: a series critical path and a feedback critical path, and divides eac= h of wave-pipelined circuits into two components: a static logic part, call= ed critical path component (CPC), and a dynamic logic part, formalized into= four wave-pipelining components (WPC) shared by all wave-pipelined circuit= s. Each wave-pipelining ready code in HDL comprises two components: a WPC i= nstantiation and a CPC instantiation wire-connected and linked by a new lin= k statement. Each WPC has new wave constants which play the same role as ge= neric constants do, but whose initial values are determined and assigned by= a synthesizer after code analysis, so designers can use after-synthesizati= on information in their code before synthesization for wave-pipelining tech= nology. The responsibility of analyzing and manipulating wave-pipelining re= ady code, generating and implementing wave-pipelined circuits on a design-w= ide or chip-wide scale in HDL is shifted from designers to synthesizers. > >=20 > > Anyone who are interested in its content is welcome to send a email req= uest to the following email address: wtx wtx @ gmail . com with title "Syst= ematic" and he will receive the full documents: one specification, 9 drawin= gs and one text file in VHDL. > >=20 > > If one reviews the files and feels that it would be a good thing to rec= ommend the application to his company to buy it, the first person to do it = after his recommended company does so will receive $10,000 commission fee. > >=20 > > Thank you. > >=20 > > Weng >=20 > Hi, > I want to add some introductions to what the wave-pipelined circuits are = and their status. >=20 > [0003] A synchronous digital system contains a lot of registers. Valid= data flow through successive registers from system input registers to syst= em output registers. All data flows are synchronous with triggering edges o= f a chip clock. For example, data flow from registers A to registers B, fro= m registers B to registers C and so on in a successive order on the same cl= ock cycle. > [0004] A path in a synchronous digital system is a route between any n= eighboring registers connected by combinational logic. If the target runnin= g frequency for a digital design is predetermined, the upper limit of propa= gating time for any paths is determined and has the inverse value of the ta= rget running frequency. A path is called a critical path if the time signal= s take to propagate through it is beyond the predetermined propagating time= , and the time is called the path's critical time. If there are any critica= l paths, digital designers must spend time reducing all critical times by a= ll means and eliminating all critical paths to meet the target running freq= uency. > [0005] Wave-pipelining is a technology which completes an operation th= at needs several clock cycles to propagate without intermediate registers a= nd with input data acceptable on every clock cycle. For example, in a conve= ntional pipelining operation, data flow from registers A to registers D thr= ough registers B and C to divide the critical path time into multiple small= er intervals to meet the critical time: A to B to C to D; with wave-pipelin= ing, data flow through registers A and D without intermediate registers B a= nd C. Absolutely, wave-pipelining will reduce logic resource usage and is s= uperior to the conventional pipelining technology if it can be used. >=20 > Here are the most important inequalities involving wave-pipelining from p= aper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burleson= et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, no. 3= , pp. 464-474, Sep. 1998. >=20 > [0018] Currently many memory chip manufacturers successfully use wave-= pipelining in their memory chip products with higher rate outputs, reduced = power consumption and logic resources; and a few scientists use FPGA chips = as a base to show some circuits can be done with wave-pipelining in isolate= d environments. Their works prove that the wave-pipelining is a very powerf= ul tool to reduce power consumption and logic resources. Now there are two = major existing obstacles preventing any ordinary digital designers from usi= ng the wave-pipelining in HDL: > * The software algorithms making wave-pipelining successful, like Wong an= d Klass algorithms and others, have already been developed and matured, but= ordinary digital designers have no means or resources to access to the tec= hnology, because there are no international HDL standards on how synthesize= r manufacturers incorporate those capabilities into their products. > * HDL needs the capabilities for digital designers to write wave-pipelini= ng ready code for any number of critical paths on a design-wide or chip-wid= e scale instead of in an isolated environment and the written code can be i= dentified, synthesized and used to generate wave-pipelined circuits by any = synthesizer in ASIC or FPGA, and they should be part of HDL standards.=20 > [0019] The target of the present invention is: > * Invent a wave-pipelining coding system as new part of HDL standards for= designers to write wave-pipelining ready code which can be identified, syn= thesized and used to generate wave-pipelined circuits by any synthesizer in= ASIC or FPGA. > * Make wave-pipelining ready code written based on the coding system work= ing with no extra logic generated, compared with independently written wave= -pipelined circuits, and with no code changes when switching from non-wave-= pipelined mode to wave-pipelined mode or vice verse if all of wave-pipelini= ng ready code meet wave-pipelining requirements.=20 > * Shift burdens of analyzing and manipulating wave-pipelining ready code,= generating and implementing wave-pipelined circuits on a design-wide or ch= ip-wide scale in HDL from individual designers to synthesizer manufacturers= . > [0020] If the coding system becomes new part of HDL standards all synt= hesizer manufactures will automatically be forced to implement all well-kno= wn wave-pipelining algorithms and techniques within their products, a compe= tition will start for better implementations, making wave-pipelining techni= que available to every digital designer in HDL. >=20 > Weng Here I add some contents of the invention: Main idea behind the present invention [0057] The most difficult part coding all types of wave-pipelined circui= ts on a design-wide scale in HDL is that a wave-pipelined circuit code alwa= ys comprises two logic parts:=20 * A static logic part: it doesn't change if the number of series clock cycl= es through the circuit changes and is unique for each of wave-pipelined cir= cuits. * A dynamic logic part: it does change if the number of series clock cycles= through the circuit changes and is the same for one of groups of wave-pipe= lined circuits. [0058] Every wave-pipelined circuit has its own change rules and those c= hanges are unknown to designers when they are writing code and will be know= n to a synthesizer only after it has analyzed the circuit. [0059] The present invention classifies all critical paths into two basi= c types: a series critical path and a feedback critical path, and divides e= ach of wave-pipelined circuits into two components: one is static logic par= t and called critical path component (CPC); another is dynamic logic part a= nd formalized into four wave-pipelining components (WPC) shared by all wave= -pipelined circuits. Under the present invention each of standard wave-pipe= lining ready code in HDL comprises two components: a WPC instantiation and = a CPC instantiation which are wire-connected and linked by a new concurrent= link statement. Each of four WPC embodiments has a group of new type wave = constant, which plays the same role as a generic constant does, but whose i= nitial value is determined and assigned by a synthesizer after it has analy= zed the linked CPC component under slow mode and target mode, respectively,= so designers can use after-synthesization information in their code before= synthesization in HDL for wave-pipelining technology. Following the instru= ctions of the present invention creates a situation that digital designers = can write wave-pipelining ready code in HDL and the responsibility of analy= zing and manipulating wave-pipelining ready code, generating and implementi= ng wave-pipelined circuits on a design-wide or chip-wide scale in HDL is sh= ifted from individual designers to synthesizer manufacturers. How the method works [0060] The systematic method of coding wave-pipelined circuits in HDL co= mprises following ten parts: 1. Define five signals, one counter, one switch and one table that will be = used when generating wave-pipelined circuits on a design-wide or chip-wide = scale in HDL. 2. Define the interfaces of a CPC each of which encapsulates a critical pat= h's static logic part. 3. Define and implement four WPC embodiments in HDL each of which is a crit= ical path's dynamic logic part: a series_module, an input_delay_module, a m= ultiple_copy_module1 and a multiple_copy_module2. 4. Define one new keyword wave and three new wave constants which provide a= means to dynamically transfer after-synthesization information to designer= s' code before synthesization. 5. Define the methods of determining and searching for wave constant values= of a known WPC instantiation under slow mode and target mode, respectively= . 6. Define three versions of a concurrent link statement: link1, link2 and l= ink3, and rules on how they are used. 7. Define the pairing rules between a WPC and a CPC. 8. Define how a digital designer prepares wave-pipelining ready code system= atically. 9. Shift the responsibility of analyzing and manipulating wave-pipelining r= eady code, generating and implementing wave-pipelined circuits on a design-= wide or chip-wide scale in HDL from individual designers to synthesizer man= ufacturers. 10. Define how four WPC embodiments are simulated and debugged under any of= current versions of a synthesizer in HDL. [0061] It is fair to put the burden of successfully generating wave-pipe= lined circuits based on wave-pipelining ready code squarely on synthesizer = manufacturers' shoulder if all necessary information is passed to a synthes= izer. For example, with tens of papers claiming that successful wave-pipeli= ned circuits are implemented in FPGA chips in an isolated environment, it i= s the responsibility of FPGA synthesizers to be capable of generating those= wave-pipelined circuits in a design-wide environment without designers' fu= rther involvements, a process similar for them to the task of generating a = circuit with the highest running frequency and minimum used resources if po= ssible for any normal digital design code. Thank you for your reading. From newsfish@newsfish Thu Aug 1 00:32:40 2024 X-Received: by 10.236.26.179 with SMTP id c39mr3313167yha.27.1425455260336; Tue, 03 Mar 2015 23:47:40 -0800 (PST) X-Received: by 10.140.84.213 with SMTP id l79mr43543qgd.41.1425455260258; Tue, 03 Mar 2015 23:47:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!k15no49377qaq.1!news-out.google.com!c1ni205qar.1!nntp.google.com!k15no49373qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 23:47:40 -0800 (PST) In-Reply-To: <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: hssig Injection-Date: Wed, 04 Mar 2015 07:47:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3613 Aaah, the "VHDL hater" is back ;-) From newsfish@newsfish Thu Aug 1 00:32:40 2024 X-Received: by 10.236.63.42 with SMTP id z30mr3373226yhc.37.1425458317384; Wed, 04 Mar 2015 00:38:37 -0800 (PST) X-Received: by 10.50.43.234 with SMTP id z10mr140235igl.8.1425458317254; Wed, 04 Mar 2015 00:38:37 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!k15no62007qaq.1!news-out.google.com!db6ni40239igc.0!nntp.google.com!hl2no2981511igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 00:38:36 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=202.62.65.48; posting-account=x4WE3QoAAACvybfiq0gf93gqOYCxol97 NNTP-Posting-Host: 202.62.65.48 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Subject: c-language to VHDL converter From: Sai Jaswanth Injection-Date: Wed, 04 Mar 2015 08:38:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3614 hi friends can any one help me in knowing how to convert the c-code to VHDL directly by any software. (or) can we compile C-code in xilinx IDE? From newsfish@newsfish Thu Aug 1 00:32:41 2024 X-Received: by 10.50.23.75 with SMTP id k11mr5765097igf.3.1425460518093; Wed, 04 Mar 2015 01:15:18 -0800 (PST) X-Received: by 10.140.108.182 with SMTP id j51mr52994qgf.24.1425460517920; Wed, 04 Mar 2015 01:15:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no2992477igb.0!news-out.google.com!n6ni192qar.0!nntp.google.com!w8no375585qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 01:15:17 -0800 (PST) In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3a37e343-8d49-4394-8de3-23e18a676e59@googlegroups.com> Subject: Re: c-language to VHDL converter From: hssig Injection-Date: Wed, 04 Mar 2015 09:15:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3615 In Vivado you can (HLS) From newsfish@newsfish Thu Aug 1 00:32:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx46.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: c-language to VHDL converter References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150303-1, 03/03/2015), Outbound message X-Antivirus-Status: Clean Lines: 15 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1425467364 86.17.210.161 (Wed, 04 Mar 2015 11:09:24 UTC) NNTP-Posting-Date: Wed, 04 Mar 2015 11:09:24 UTC Organization: virginmedia.com Date: Wed, 04 Mar 2015 11:09:23 +0000 X-Received-Body-CRC: 747208525 X-Received-Bytes: 1394 Xref: news.eternal-september.org comp.lang.vhdl:3616 On 04/03/2015 08:38, Sai Jaswanth wrote: > hi friends can any one help me in knowing how to convert the c-code to VHDL directly by any software. (or) can we compile C-code in xilinx IDE? > Hi Sai, Check out Hercules: http://www.nkavvadias.com/hercules/ You could also try Xilinx HLS, Good luck, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:32:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!peer02.fr7!news.highwinds-media.com!post02.fr7!fx04.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PSL help please References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> In-Reply-To: <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150303-1, 03/03/2015), Outbound message X-Antivirus-Status: Clean Lines: 51 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1425468423 86.17.210.161 (Wed, 04 Mar 2015 11:27:03 UTC) NNTP-Posting-Date: Wed, 04 Mar 2015 11:27:03 UTC Organization: virginmedia.com Date: Wed, 04 Mar 2015 11:27:02 +0000 X-Received-Body-CRC: 1238012365 X-Received-Bytes: 2996 Xref: news.eternal-september.org comp.lang.vhdl:3617 On 03/03/2015 18:38, niv wrote: Hi Niv, > On Tuesday, March 3, 2015 at 9:54:53 AM UTC, HT-Lab wrote: ..snip > > Not homework (other than self imposed)! That is good! PSL is amazingly powerful language especially on a formal tool. > I've been VHDL coding for ~25 years, but just started to grapple with PSL. > Bought Cindy Eisner book, which I've started to read & creating my own examples to test myself. > > So, Leonardo answer worked, sort of, > but I've changed the code so the resp_1 o/p is also clocked when clk_enable is '1', so this has caused a set of 9(?) assertion failures between counter = 200 & resp_1 going high. > > I tried this, which worked, but seems a bit too like the source code? > > -- property RESP_01 is > -- ({counter = 200 AND clk_enable = '1'} |=> {resp_1} abort rst); > -- assert always RESP_01 report "ERROR: resp_1 did not go to '1' at count max"; > -- > > > Any suggestions welcome! Leonardo already gave you some good advice, however, watch out for the consecutive repeat [*n] operator as you could end up with a lot of assertion threads (when part of the LHS becomes valid your simulator will spawn a new thread, in Modelsim these are the blue blocks). A possible (but untested) better solution could be the goto repetition [->] operator. Some general comments, watch out were you put your () brackets, the abort operator takes precedence. In your code you are aborting the RHS of your property. I would have aborted the whole property or directive to avoid wasting simulation cycles, example: always (..) abort rst; (always ..) abort rst; I would also use {resp_1='1'} just in case your variable goes to 'X'/'Z' etc. Good luck, Regards, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:32:41 2024 X-Received: by 10.140.151.75 with SMTP id 72mr4919705qhx.3.1425481563824; Wed, 04 Mar 2015 07:06:03 -0800 (PST) X-Received: by 10.50.112.194 with SMTP id is2mr534212igb.2.1425481563638; Wed, 04 Mar 2015 07:06:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!au2pb.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!k15no148671qaq.1!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4104656igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 07:06:03 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Wed, 04 Mar 2015 15:06:03 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3382 X-Received-Body-CRC: 1278390142 Xref: news.eternal-september.org comp.lang.vhdl:3618 On Tuesday, March 3, 2015 at 11:47:41 PM UTC-8, hssig wrote: > Aaah, the "VHDL hater" is back ;-) Hi HSSIG, Ha, Ha, Ha, Ha, you have a really good memory!!! The story happened 13 year= s ago!!! You must have attended the 11th International HDL conference held in Double= Tree hotel, San Jose=EF=BC=8CCA=EF=BC=8Cin March, 2002, and listened to my= presentation! When I was doing my presentation, a big laugh was burst when I said "I hate= VHDL, because it lacks the data grammar structure which can nicely handle = the mutually exclusive cases."=20 During the period I met great pressure to increase the running frequency fo= r a 66MHz PCI DMA board. How could I do it to increase the running frequenc= y to meet 66MHz requirement in VHDL from 23 MHz running frequency achieved = from an Altera chip? I hoped to get experts' help, but none touched and ans= wered my question. Finally I successfully finished the job and my design go= t 480 MByte/s on a maximum 528 MByte/s 66MHz PCI bus achieved through a Xil= inx chip.=20 Thank you for giving me the nickname "VHDL hater."=20 After my distributions of my paper in this and FPGA group, I received more = than 150 paper requests to get the article within 3 month period. Now I gladly know that even SystemVerilog, a HDL language Intel uses, lacks= the function, even SystemVerilog-2012 "doesn't appear to be currently gain= ing a lot of traction." =E2=80=9COne person's medicine, another one's fortune."=20 Now it give me a chance to make a fortune to publish another group of inven= tion-patents which had been finished at least 4 years ago and would schemat= ically and definitely show that new keyword "orif" and its data structure r= eally saves logic and it is really indispensable=EF=BC=8Cessential, necessa= ry, all-important, of the utmost importance, of the essence, vital, must-ha= ve, crucial, key, needed, required, requisite, imperative and invaluable. Thank you for your comment. Weng From newsfish@newsfish Thu Aug 1 00:32:42 2024 X-Received: by 10.70.92.103 with SMTP id cl7mr7512252pdb.0.1425513283662; Wed, 04 Mar 2015 15:54:43 -0800 (PST) X-Received: by 10.182.65.169 with SMTP id y9mr75035obs.17.1425513283257; Wed, 04 Mar 2015 15:54:43 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl2no4416540igb.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4416513igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:54:43 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Learn VHDL and FPGA! From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:54:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3619 Want to learn more in engineering? If you are interested in learning VHDL programming and FPGA development take my course today! This coupon is good till April 6th, 2015 for $60 - 40% off the cost of the class at regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/ From newsfish@newsfish Thu Aug 1 00:32:42 2024 X-Received: by 10.236.222.103 with SMTP id s97mr7478241yhp.19.1425513307916; Wed, 04 Mar 2015 15:55:07 -0800 (PST) X-Received: by 10.182.142.66 with SMTP id ru2mr73172obb.5.1425513307702; Wed, 04 Mar 2015 15:55:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!k15no294255qaq.1!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4416746igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:55:07 -0800 (PST) In-Reply-To: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <508dd711-754c-4ed7-bc7f-539b54dbeaab@googlegroups.com> Subject: Re: PSL help please From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:55:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3620 On Saturday, February 28, 2015 at 5:23:26 AM UTC-5, niv wrote: > How do I write PSL assertion for the following code? > The idea is that if I/p sig is active for a certain time (number of clock cycles), an o/p is permanently set: > > Here's some noddy code for the idea: > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE ieee.NUMERIC_STD.ALL; > ENTITY limit_resp IS > PORT( > clk : IN STD_LOGIC; > rst : IN STD_LOGIC; > stim_1 : IN STD_LOGIC; > resp_1 : OUT STD_LOGIC > ); > END ENTITY limit_resp ; > -- > ARCHITECTURE rtl OF limit_resp IS > SIGNAL clk_enable : STD_LOGIC; > SIGNAL clk_en_cntr : UNSIGNED(3 DOWNTO 0); > SIGNAL counter : UNSIGNED(7 DOWNTO 0); > BEGIN > -------------------------------------------------------------------------------- > -- Generate a clock enable signal at 1/10 clock rate. > -------------------------------------------------------------------------------- > clk_en_gen:PROCESS(rst, clk) > BEGIN > IF rst = '1' THEN > clk_enable <= '0'; > clk_en_cntr <= TO_UNSIGNED(0,4); > ELSIF rising_edge(clk) THEN > IF clk_en_cntr = TO_UNSIGNED(9,4) THEN > clk_enable <= '1'; > clk_en_cntr <= TO_UNSIGNED(0,4); > ELSE > clk_enable <= '0'; > clk_en_cntr <= clk_en_cntr + 1; > END IF; > END IF; > END PROCESS clk_en_gen; > -------------------------------------------------------------------------------- > -- Count up to some arbitrary value (for this test) > -------------------------------------------------------------------------------- > count_up:PROCESS(rst, clk) > BEGIN > IF rst = '1' THEN > counter <= TO_UNSIGNED(0,8); > ELSIF rising_edge(clk) THEN > IF clk_enable = '1' THEN > IF stim_1 = '1' THEN > IF counter < 200 THEN > counter <= counter + 1; > END IF; > ELSE > counter <= TO_UNSIGNED(0,8); > END IF; > END IF; > END IF; > END PROCESS count_up; > -------------------------------------------------------------------------------- > -- If counter has maxed out, set the output high (forever, unless master reset) > -- i.e. if the counter ever reaches its max (200) then the output is set, > -- regardless of whether the input stim subsequently is removed. > -------------------------------------------------------------------------------- > set_output:PROCESS(rst, clk) > BEGIN > IF rst = '1' THEN > resp_1 <= '0'; > ELSIF rising_edge(clk) THEN > IF counter = 200 THEN > resp_1 <= '1'; > END IF; > END IF; > END PROCESS set_output; > -------------------------------------------------------------------------------- > -- Now include a PSL assertion to test the following; > -- > -- If stim is set for "N" clock cycles (or more) (2000 in this example), > -- then the "resp" output is set. > -- HELP REQUIRED FOR THE BELOW PLEASE! > -------------------------------------------------------------------------------- > -------------------------------------------------------------------------------- > -- psl begin > -- default clock is rising_edge(clk); > -- > -- > -- end > -------------------------------------------------------------------------------- > END ARCHITECTURE rtl; > > Regards, Niv Want to learn more in engineering? If you are interested in learning VHDL programming and FPGA development take my course today! This coupon is good till April 6th, 2015 for $60 - 40% off the cost of the class at regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/ From newsfish@newsfish Thu Aug 1 00:32:42 2024 X-Received: by 10.66.140.66 with SMTP id re2mr7522901pab.29.1425513327227; Wed, 04 Mar 2015 15:55:27 -0800 (PST) X-Received: by 10.182.220.229 with SMTP id pz5mr76506obc.34.1425513326981; Wed, 04 Mar 2015 15:55:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no4416825igb.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4416819igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:55:26 -0800 (PST) In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: c-language to VHDL converter From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:55:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3621 On Wednesday, March 4, 2015 at 3:38:38 AM UTC-5, Sai Jaswanth wrote: > hi friends can any one help me in knowing how to convert the c-code to VHDL directly by any software. (or) can we compile C-code in xilinx IDE? Want to learn more in engineering? If you are interested in learning VHDL programming and FPGA development take my course today! This coupon is good till April 6th, 2015 for $60 - 40% off the cost of the class at regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/ From newsfish@newsfish Thu Aug 1 00:32:43 2024 X-Received: by 10.140.151.75 with SMTP id 72mr7453741qhx.3.1425513357322; Wed, 04 Mar 2015 15:55:57 -0800 (PST) X-Received: by 10.182.220.229 with SMTP id pz5mr76519obc.34.1425513357120; Wed, 04 Mar 2015 15:55:57 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w8no598045qac.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4416974igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:55:57 -0800 (PST) In-Reply-To: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <43d0c6d9-716d-43ee-b3d2-8447950dea9a@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:55:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3622 On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang wrote: > Hi Jim, glen, JK, rickman, Mike, Andy,=20 >=20 > I have filed a provisional patent application: "Systematic method of codi= ng wave pipelined circuits in HDL". If it is proved correct, the patent wil= l introduce 1 keyword, 3 permanent constants, 1 concurrent statement and fo= ur source code modules for a new library in HDL and thoroughly resolve a pe= nding problem so that every digital designer can code wave-pipelined circui= ts in HDL. >=20 > Here is the abstract of the invention: >=20 > The present invention classifies all critical paths into two basic ty= pes: a series critical path and a feedback critical path, and divides each = of wave-pipelined circuits into two components: a static logic part, called= critical path component (CPC), and a dynamic logic part, formalized into f= our wave-pipelining components (WPC) shared by all wave-pipelined circuits.= Each wave-pipelining ready code in HDL comprises two components: a WPC ins= tantiation and a CPC instantiation wire-connected and linked by a new link = statement. Each WPC has new wave constants which play the same role as gene= ric constants do, but whose initial values are determined and assigned by a= synthesizer after code analysis, so designers can use after-synthesization= information in their code before synthesization for wave-pipelining techno= logy. The responsibility of analyzing and manipulating wave-pipelining read= y code, generating and implementing wave-pipelined circuits on a design-wid= e or chip-wide scale in HDL is shifted from designers to synthesizers. >=20 > Anyone who are interested in its content is welcome to send a email reque= st to the following email address: wtx wtx @ gmail . com with title "System= atic" and he will receive the full documents: one specification, 9 drawings= and one text file in VHDL. >=20 > If one reviews the files and feels that it would be a good thing to recom= mend the application to his company to buy it, the first person to do it af= ter his recommended company does so will receive $10,000 commission fee. >=20 > Thank you. >=20 > Weng Want to learn more in engineering? If you are interested in learning=20 VHDL programming and FPGA development take my course today! This coupon=20 is good till April 6th, 2015 for $60 - 40% off the cost of the class at=20 regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermedi= ates/?couponCode=3DMarch60#/ From newsfish@newsfish Thu Aug 1 00:32:43 2024 X-Received: by 10.70.131.81 with SMTP id ok17mr7496288pdb.6.1425513379889; Wed, 04 Mar 2015 15:56:19 -0800 (PST) X-Received: by 10.182.89.198 with SMTP id bq6mr76563obb.28.1425513379562; Wed, 04 Mar 2015 15:56:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no4417080igb.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4417076igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:56:19 -0800 (PST) In-Reply-To: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help with VHDL architecture From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:56:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2601 X-Received-Body-CRC: 4146377143 Xref: news.eternal-september.org comp.lang.vhdl:3623 On Friday, January 2, 2015 at 3:55:55 AM UTC-5, Olalekan Shittu wrote: > Hello everyone. > > I have been trying to write a VHDL architecture for the circuit below but doesn't seem to be making headway, can anyone be of help. > > Below is my entity declaration from the system > > Library ieee; > use IEEE.std_logic_1164.all; > > entity Sorter IS > Port ( C: IN std_logic_vector (0 to 3); > Sel: IN STD_LOGIC_VECTOR(0 to 2); > out0: out std_logic; > out1: out std_logic; > out2: out std_logic; > out3: out std_logic > ); > end sorter; > > I am to write an architecture for the above with condition that: > > When Sel equal 4, the resulting output as shown in the table below is generated > > out0 out1 out2 out3 > 0 <= C < 4 1 0 0 0 > > 4 <= C < 8 0 1 0 0 > > 8 <= C < 12 0 0 1 0 > > 12 <= C < 16 0 0 0 1 > > otherwise out0,out1,out2,out3 are all equal to zero. > > Thanks Want to learn more in engineering? If you are interested in learning VHDL programming and FPGA development take my course today! This coupon is good till April 6th, 2015 for $60 - 40% off the cost of the class at regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/ From newsfish@newsfish Thu Aug 1 00:32:43 2024 X-Received: by 10.42.209.135 with SMTP id gg7mr365865icb.9.1425513399206; Wed, 04 Mar 2015 15:56:39 -0800 (PST) X-Received: by 10.182.220.229 with SMTP id pz5mr76551obc.34.1425513398947; Wed, 04 Mar 2015 15:56:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no4417279igb.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4417275igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:56:38 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0cb65708-e019-48cb-9b10-bdc121c39877@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:56:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3624 On Friday, January 9, 2015 at 8:09:03 AM UTC-5, johan.fa...@gmail.com wrote= : > a month ago I decided that I was lacking FPGA knowhow, said and done I or= dered an experiment board (beeing an opensource aficionado I ordered the Lo= gicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's= "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Exam= ples: Spartan 3". My reasoning behind these two books is that I start with = Ashenden to learn the whole language then go to Pong to learn how to write = syntezisable VHDL, since both contain exercises they make for really good s= elf teaching material. I know Pong is targeting another experiment board bu= t it's the same FPGA and im very confident I can myself make adjustments, e= xcept for e.g. the PS2 port which my papilio thankfully does not have. >=20 > I have now started to search for what to do after these books, how do I g= et more advanced in my FPGA knowledge. I'm a software guy and if I got the = question "I want to start programming" from someone new to programming I wo= uld recomend a good starting book in python, then a good book on how to do = test driven design, then a book about patterns, then moving to C followed b= y a book about object oriented design, then perhaps going for a best practi= ce book and so on, by level of complexity and relevance. I have scoured the= internet (or feels like it) to find such a list regarding FPGA, but at no = luck so far, so thinking of posting the question here. >=20 > I have looked at three books for continued learning after I'm finished wi= th Pong >=20 > Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aim= ed at explaining deeper the differences beetwen syntezisable and simulated = VHDL. Though it seem to go through the VHDL language constructs yet again p= erhaps it is too much overlapping with Pong and Ashenden >=20 > Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; se= ems a good continuation, I understand that FSM is a very important topic in= HW world and that they are completely different from SW FSM, also it seem = to have excersises after each chapter which is good. >=20 > Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portabi= lity, and Scalability ; seems good, no more comments. >=20 > Thats my thinking, any suggestions or comments? Have not come about any b= ooks regarding FPGA testing? Perhaps I should look outside the more hands o= n book to one of the "meta" books out there? Want to learn more in engineering? If you are interested in learning=20 VHDL programming and FPGA development take my course today! This coupon=20 is good till April 6th, 2015 for $60 - 40% off the cost of the class at=20 regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermedi= ates/?couponCode=3DMarch60#/ From newsfish@newsfish Thu Aug 1 00:32:43 2024 X-Received: by 10.236.18.232 with SMTP id l68mr8177704yhl.16.1425528315295; Wed, 04 Mar 2015 20:05:15 -0800 (PST) X-Received: by 10.140.101.51 with SMTP id t48mr140681qge.10.1425528315249; Wed, 04 Mar 2015 20:05:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!k15no317895qaq.1!news-out.google.com!c1ni208qar.1!nntp.google.com!k15no317892qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 20:05:15 -0800 (PST) In-Reply-To: <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:f19d:6431:41a6:faec; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:f19d:6431:41a6:faec References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Thu, 05 Mar 2015 04:05:15 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 127 Xref: news.eternal-september.org comp.lang.vhdl:3625 On Wednesday, March 4, 2015 at 10:06:05 AM UTC-5, Weng Tianxiang wrote: > On Tuesday, March 3, 2015 at 11:47:41 PM UTC-8, hssig wrote: >=20 > Now it give me a chance to make a fortune to publish another group of=20 > invention-patents which had been finished at least 4 years ago and would= =20 > schematically and definitely show that new keyword "orif" and its data=20 > structure really saves logic and it is really indispensable=EF=BC=8Cessen= tial,=20 > necessary, all-important, of the utmost importance, of the essence, vital= ,=20 > must-have, crucial, key, needed, required, requisite, imperative and=20 > invaluable. >=20 You might want to save some of those superlatives for a different invention= , they do not apply to 'orif'. Back when you first proposed it, you used the keyword 'elsor' [1] which is = also how it is currently reflected in the proposal presented on the 1076 TW= IKI page [2]. However, the real problem is that if the control signals rea= lly are mutually exclusive, all of the different forms that you presented w= ill produce exactly the same result today. In your proposal, you presented= three different alternative forms (if/elsif...endif; sequential if/endif a= nd concurrent 'when/else') and you declared but presented no actual evidenc= e that these three will have 'superfluous condition is posed on the equatio= n' and that a 'priority tree' will be created which will in turn create ext= ra logic over the preferred form of a simple 'and/or' structure. You're mi= staken. All three of the alternatives will produce the exact same logic as= the preferred 'and/or' form. [3]. In order for their to be any actual utility to 'orif', you would first have= to come up with a scenario where the input control signals a, b, c, d, e t= ruly are mutually exclusive but the synthesis tool generates different resu= lts. One possible approach would be to say that a-e are top level inputs t= o the design and that those inputs are supposed to come from the output of = a decoder so therefore they are mutually exclusive. Besides limiting 'orif= ' to only be applicable to the scenario where the controls come only from d= evice input pins, this ignores the real world possibility that those input = pins have been shorted together so a-e are not absolutely guaranteed to be = mutually exclusive. But I'll leave it to you to: - Come up with the scenario where a-e are provably mutually exclusive but a= real synthesis tool produces different results for the four approaches tha= t you have defined and I have implemented in [3]. - Show how that scenario is of actual widespread benefit to anyone Kevin Jennings 1. http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt 2. http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition 3. Using brand 'Q' synthesis tool, and the code below, you will get exactly= the same result no matter what value you set the generic 'Method'. =3D=3D=3D=3D=3D=3D=3D START OF CODE =3D=3D=3D=3D=3D=3D=3D library ieee; use ieee.std_logic_1164.all; entity Orif_Example is generic(Method: in natural range 0 to 3); port( Address: in natural range 0 to 5; Abus: in std_ulogic; Bbus: in std_ulogic; Cbus: in std_ulogic; Dbus: in std_ulogic; Ebus: in std_ulogic; Outbus: out std_ulogic ); end Orif_Example; architecture RTL of Orif_Example is signal a: std_ulogic; signal b: std_ulogic; signal c: std_ulogic; signal d: std_ulogic; signal e: std_ulogic; begin a <=3D '1' when (Address =3D 1) else '0'; b <=3D '1' when (Address =3D 2) else '0'; c <=3D '1' when (Address =3D 3) else '0'; d <=3D '1' when (Address =3D 4) else '0'; e <=3D '1' when (Address =3D 5) else '0'; GEN_METHOD_0 : if (Method =3D 0) generate Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d and = DBus) or (e and EBus);=20 end generate GEN_METHOD_0; GEN_METHOD_1 : if (Method =3D 1) generate -- One statement structure in serial mode:=20 process(all) begin if(a =3D '1') then OutBus <=3D ABus; elsif(b =3D '1') then Outbus <=3D BBus; elsif(c =3D '1') then Outbus <=3D CBus; elsif(d =3D '1') then Outbus <=3D DBus; elsif(e =3D '1') then Outbus <=3D EBus; else Outbus <=3D '0'; end if;=20 end process; end generate GEN_METHOD_1; GEN_METHOD_2 : if (Method =3D 2) generate -- or in another equal form:=20 process(all) begin Outbus <=3D '0';=20 if(a =3D '1') then OutBus <=3D ABus; end if; if(b =3D '1') then OutBus <=3D BBus; end if; if(c =3D '1') then OutBus <=3D CBus; end if; if(d =3D '1') then OutBus <=3D DBus; end if; if(e =3D '1') then OutBus <=3D EBus; end if; end process; end generate GEN_METHOD_2; GEN_METHOD_3 : if (Method =3D 3) generate -- In concurrent mode: OutBus <=3D ABus when a =3D '1' else BBus when b =3D '1' else CBus when c =3D '1' else DBus when d =3D '1' else EBus when e =3D '1' else '0'; end generate GEN_METHOD_3; end RTL; =3D=3D=3D=3D=3D=3D=3D END OF CODE =3D=3D=3D=3D=3D=3D=3D From newsfish@newsfish Thu Aug 1 00:32:44 2024 X-Received: by 10.70.42.170 with SMTP id p10mr8638838pdl.3.1425535152113; Wed, 04 Mar 2015 21:59:12 -0800 (PST) X-Received: by 10.50.129.98 with SMTP id nv2mr126247igb.1.1425535151991; Wed, 04 Mar 2015 21:59:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no4538348igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no4538330igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 21:59:11 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Thu, 05 Mar 2015 05:59:12 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3626 On Wednesday, March 4, 2015 at 8:05:16 PM UTC-8, KJ wrote: > On Wednesday, March 4, 2015 at 10:06:05 AM UTC-5, Weng Tianxiang wrote: > > On Tuesday, March 3, 2015 at 11:47:41 PM UTC-8, hssig wrote: > >=20 > > Now it give me a chance to make a fortune to publish another group of= =20 > > invention-patents which had been finished at least 4 years ago and woul= d=20 > > schematically and definitely show that new keyword "orif" and its data= =20 > > structure really saves logic and it is really indispensable=EF=BC=8Cess= ential,=20 > > necessary, all-important, of the utmost importance, of the essence, vit= al,=20 > > must-have, crucial, key, needed, required, requisite, imperative and=20 > > invaluable. > >=20 >=20 > You might want to save some of those superlatives for a different inventi= on, they do not apply to 'orif'. >=20 > Back when you first proposed it, you used the keyword 'elsor' [1] which i= s also how it is currently reflected in the proposal presented on the 1076 = TWIKI page [2]. However, the real problem is that if the control signals r= eally are mutually exclusive, all of the different forms that you presented= will produce exactly the same result today. In your proposal, you present= ed three different alternative forms (if/elsif...endif; sequential if/endif= and concurrent 'when/else') and you declared but presented no actual evide= nce that these three will have 'superfluous condition is posed on the equat= ion' and that a 'priority tree' will be created which will in turn create e= xtra logic over the preferred form of a simple 'and/or' structure. You're = mistaken. All three of the alternatives will produce the exact same logic = as the preferred 'and/or' form. [3]. >=20 > In order for their to be any actual utility to 'orif', you would first ha= ve to come up with a scenario where the input control signals a, b, c, d, e= truly are mutually exclusive but the synthesis tool generates different re= sults. One possible approach would be to say that a-e are top level inputs= to the design and that those inputs are supposed to come from the output o= f a decoder so therefore they are mutually exclusive. Besides limiting 'or= if' to only be applicable to the scenario where the controls come only from= device input pins, this ignores the real world possibility that those inpu= t pins have been shorted together so a-e are not absolutely guaranteed to b= e mutually exclusive. >=20 > But I'll leave it to you to: > - Come up with the scenario where a-e are provably mutually exclusive but= a real synthesis tool produces different results for the four approaches t= hat you have defined and I have implemented in [3]. > - Show how that scenario is of actual widespread benefit to anyone >=20 > Kevin Jennings >=20 > 1. http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt > 2. http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition > 3. Using brand 'Q' synthesis tool, and the code below, you will get exact= ly the same result no matter what value you set the generic 'Method'. > =3D=3D=3D=3D=3D=3D=3D START OF CODE =3D=3D=3D=3D=3D=3D=3D > library ieee; > use ieee.std_logic_1164.all; >=20 > entity Orif_Example is > generic(Method: in natural range 0 to 3); > port( > Address: in natural range 0 to 5; > Abus: in std_ulogic; > Bbus: in std_ulogic; > Cbus: in std_ulogic; > Dbus: in std_ulogic; > Ebus: in std_ulogic; > Outbus: out std_ulogic > ); > end Orif_Example; >=20 > architecture RTL of Orif_Example is > signal a: std_ulogic; > signal b: std_ulogic; > signal c: std_ulogic; > signal d: std_ulogic; > signal e: std_ulogic; > begin > a <=3D '1' when (Address =3D 1) else '0'; > b <=3D '1' when (Address =3D 2) else '0'; > c <=3D '1' when (Address =3D 3) else '0'; > d <=3D '1' when (Address =3D 4) else '0'; > e <=3D '1' when (Address =3D 5) else '0'; >=20 > GEN_METHOD_0 : if (Method =3D 0) generate > Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d an= d DBus) or (e and EBus);=20 > end generate GEN_METHOD_0; >=20 > GEN_METHOD_1 : if (Method =3D 1) generate > -- One statement structure in serial mode:=20 > process(all) > begin > if(a =3D '1') then OutBus <=3D ABus; > elsif(b =3D '1') then Outbus <=3D BBus; > elsif(c =3D '1') then Outbus <=3D CBus; > elsif(d =3D '1') then Outbus <=3D DBus; > elsif(e =3D '1') then Outbus <=3D EBus; > else Outbus <=3D '0'; > end if;=20 > end process; > end generate GEN_METHOD_1; >=20 > GEN_METHOD_2 : if (Method =3D 2) generate > -- or in another equal form:=20 > process(all) > begin > Outbus <=3D '0';=20 > if(a =3D '1') then OutBus <=3D ABus; end if; > if(b =3D '1') then OutBus <=3D BBus; end if; > if(c =3D '1') then OutBus <=3D CBus; end if; > if(d =3D '1') then OutBus <=3D DBus; end if; > if(e =3D '1') then OutBus <=3D EBus; end if; > end process; >=20 > end generate GEN_METHOD_2; >=20 > GEN_METHOD_3 : if (Method =3D 3) generate > -- In concurrent mode: > OutBus <=3D ABus when a =3D '1' > else BBus when b =3D '1' > else CBus when c =3D '1' > else DBus when d =3D '1' > else EBus when e =3D '1' > else '0'; > end generate GEN_METHOD_3; > end RTL; > =3D=3D=3D=3D=3D=3D=3D END OF CODE =3D=3D=3D=3D=3D=3D=3D Hi KJ, Thank you for taking time to discuss the keyword "orif". I don't have to generate other example and just use your example with follo= wing changes: Generate a, b, c, d, e in two different state machines with t= he two state machines being mutually exclusive, so that a-e are mutually ex= clusive.=20 The two state machine may be a read state machine and a write state machine= of a bus. And a-e are used to drive the 2nd bus. Now please generate your code to see how a compiler knows if a-e are mutual= ly exclusive. The generated code must be different!!! What your example provides is the simplest one and a compiler can do it ver= y easily!!! Nature and coding in complex situations are more complex than your example = provides. 1. You must acknowledge that there are situations that only the code writer= knows which conditions are mutually exclusive. http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition#Arguments_FOR Current Situation Consider a basic equation in hardware design:=20 -- no priority tree is implied Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d and DBus) or= (e and EBus); One statement structure in serial mode: -- a priority tree is implied if(a =3D '1') then OutBus <=3D ABus; elsif(b =3D '1') then Outbus <=3D BBus; elsif(c =3D '1') then Outbus <=3D CBus; elsif(d =3D '1') then Outbus <=3D DBus; elsif(e =3D '1') then Outbus <=3D EBus; else Outbus <=3D '0'; end if; or in another equal form: -- a priority tree is implied Outbus <=3D '0'; if(a =3D '1') then OutBus <=3D ABus; end if; if(b =3D '1') then OutBus <=3D BBus; end if; if(c =3D '1') then OutBus <=3D CBus; end if; if(d =3D '1') then OutBus <=3D DBus; end if; if(e =3D '1') then OutBus <=3D EBus; end if; In concurrent mode: -- a priority tree is implied OutBus <=3D ABus when a =3D '1' else BBus when b =3D '1' else CBus when c =3D '1' else DBus when d =3D '1' else EBus when e =3D '1' else '0'; In those above 3 situations, a superfluous condition is posed on the equati= on, it means a priority tree is implied in all three situations. Actually m= ost of time when dealing with main data flow, all above conditions are mutu= ally exclusive, so there is no need to pose the extra conditions on the fin= al equation. Weng From newsfish@newsfish Thu Aug 1 00:32:44 2024 X-Received: by 10.140.216.150 with SMTP id m144mr9411177qhb.9.1425553138925; Thu, 05 Mar 2015 02:58:58 -0800 (PST) X-Received: by 10.50.79.170 with SMTP id k10mr634651igx.5.1425553138650; Thu, 05 Mar 2015 02:58:58 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no691677qac.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no3485066igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 02:58:57 -0800 (PST) In-Reply-To: <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Thu, 05 Mar 2015 10:58:58 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 10921 X-Received-Body-CRC: 2877488998 Xref: news.eternal-september.org comp.lang.vhdl:3627 On Wednesday, March 4, 2015 at 9:59:17 PM UTC-8, Weng Tianxiang wrote: > On Wednesday, March 4, 2015 at 8:05:16 PM UTC-8, KJ wrote: > > On Wednesday, March 4, 2015 at 10:06:05 AM UTC-5, Weng Tianxiang wrote: > > > On Tuesday, March 3, 2015 at 11:47:41 PM UTC-8, hssig wrote: > > >=20 > > > Now it give me a chance to make a fortune to publish another group of= =20 > > > invention-patents which had been finished at least 4 years ago and wo= uld=20 > > > schematically and definitely show that new keyword "orif" and its dat= a=20 > > > structure really saves logic and it is really indispensable=EF=BC=8Ce= ssential,=20 > > > necessary, all-important, of the utmost importance, of the essence, v= ital,=20 > > > must-have, crucial, key, needed, required, requisite, imperative and= =20 > > > invaluable. > > >=20 > >=20 > > You might want to save some of those superlatives for a different inven= tion, they do not apply to 'orif'. > >=20 > > Back when you first proposed it, you used the keyword 'elsor' [1] which= is also how it is currently reflected in the proposal presented on the 107= 6 TWIKI page [2]. However, the real problem is that if the control signals= really are mutually exclusive, all of the different forms that you present= ed will produce exactly the same result today. In your proposal, you prese= nted three different alternative forms (if/elsif...endif; sequential if/end= if and concurrent 'when/else') and you declared but presented no actual evi= dence that these three will have 'superfluous condition is posed on the equ= ation' and that a 'priority tree' will be created which will in turn create= extra logic over the preferred form of a simple 'and/or' structure. You'r= e mistaken. All three of the alternatives will produce the exact same logi= c as the preferred 'and/or' form. [3]. > >=20 > > In order for their to be any actual utility to 'orif', you would first = have to come up with a scenario where the input control signals a, b, c, d,= e truly are mutually exclusive but the synthesis tool generates different = results. One possible approach would be to say that a-e are top level inpu= ts to the design and that those inputs are supposed to come from the output= of a decoder so therefore they are mutually exclusive. Besides limiting '= orif' to only be applicable to the scenario where the controls come only fr= om device input pins, this ignores the real world possibility that those in= put pins have been shorted together so a-e are not absolutely guaranteed to= be mutually exclusive. > >=20 > > But I'll leave it to you to: > > - Come up with the scenario where a-e are provably mutually exclusive b= ut a real synthesis tool produces different results for the four approaches= that you have defined and I have implemented in [3]. > > - Show how that scenario is of actual widespread benefit to anyone > >=20 > > Kevin Jennings > >=20 > > 1. http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt > > 2. http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition > > 3. Using brand 'Q' synthesis tool, and the code below, you will get exa= ctly the same result no matter what value you set the generic 'Method'. > > =3D=3D=3D=3D=3D=3D=3D START OF CODE =3D=3D=3D=3D=3D=3D=3D > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity Orif_Example is > > generic(Method: in natural range 0 to 3); > > port( > > Address: in natural range 0 to 5; > > Abus: in std_ulogic; > > Bbus: in std_ulogic; > > Cbus: in std_ulogic; > > Dbus: in std_ulogic; > > Ebus: in std_ulogic; > > Outbus: out std_ulogic > > ); > > end Orif_Example; > >=20 > > architecture RTL of Orif_Example is > > signal a: std_ulogic; > > signal b: std_ulogic; > > signal c: std_ulogic; > > signal d: std_ulogic; > > signal e: std_ulogic; > > begin > > a <=3D '1' when (Address =3D 1) else '0'; > > b <=3D '1' when (Address =3D 2) else '0'; > > c <=3D '1' when (Address =3D 3) else '0'; > > d <=3D '1' when (Address =3D 4) else '0'; > > e <=3D '1' when (Address =3D 5) else '0'; > >=20 > > GEN_METHOD_0 : if (Method =3D 0) generate > > Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d = and DBus) or (e and EBus);=20 > > end generate GEN_METHOD_0; > >=20 > > GEN_METHOD_1 : if (Method =3D 1) generate > > -- One statement structure in serial mode:=20 > > process(all) > > begin > > if(a =3D '1') then OutBus <=3D ABus; > > elsif(b =3D '1') then Outbus <=3D BBus; > > elsif(c =3D '1') then Outbus <=3D CBus; > > elsif(d =3D '1') then Outbus <=3D DBus; > > elsif(e =3D '1') then Outbus <=3D EBus; > > else Outbus <=3D '0'; > > end if;=20 > > end process; > > end generate GEN_METHOD_1; > >=20 > > GEN_METHOD_2 : if (Method =3D 2) generate > > -- or in another equal form:=20 > > process(all) > > begin > > Outbus <=3D '0';=20 > > if(a =3D '1') then OutBus <=3D ABus; end if; > > if(b =3D '1') then OutBus <=3D BBus; end if; > > if(c =3D '1') then OutBus <=3D CBus; end if; > > if(d =3D '1') then OutBus <=3D DBus; end if; > > if(e =3D '1') then OutBus <=3D EBus; end if; > > end process; > >=20 > > end generate GEN_METHOD_2; > >=20 > > GEN_METHOD_3 : if (Method =3D 3) generate > > -- In concurrent mode: > > OutBus <=3D ABus when a =3D '1' > > else BBus when b =3D '1' > > else CBus when c =3D '1' > > else DBus when d =3D '1' > > else EBus when e =3D '1' > > else '0'; > > end generate GEN_METHOD_3; > > end RTL; > > =3D=3D=3D=3D=3D=3D=3D END OF CODE =3D=3D=3D=3D=3D=3D=3D >=20 > Hi KJ, > Thank you for taking time to discuss the keyword "orif". >=20 > I don't have to generate other example and just use your example with fol= lowing changes: Generate a, b, c, d, e in two different state machines with= the two state machines being mutually exclusive, so that a-e are mutually = exclusive.=20 >=20 > The two state machine may be a read state machine and a write state machi= ne of a bus. And a-e are used to drive the 2nd bus. >=20 > Now please generate your code to see how a compiler knows if a-e are mutu= ally exclusive. The generated code must be different!!! >=20 > What your example provides is the simplest one and a compiler can do it v= ery easily!!! >=20 > Nature and coding in complex situations are more complex than your exampl= e provides. >=20 > 1. You must acknowledge that there are situations that only the code writ= er knows which conditions are mutually exclusive. >=20 > http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition#Arguments_FOR >=20 > Current Situation > Consider a basic equation in hardware design:=20 > -- no priority tree is implied > Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d and DBus) = or (e and EBus); >=20 > One statement structure in serial mode: -- a priority tree is implied > if(a =3D '1') then OutBus <=3D ABus; > elsif(b =3D '1') then Outbus <=3D BBus; > elsif(c =3D '1') then Outbus <=3D CBus; > elsif(d =3D '1') then Outbus <=3D DBus; > elsif(e =3D '1') then Outbus <=3D EBus; > else Outbus <=3D '0'; > end if; >=20 > or in another equal form: -- a priority tree is implied > Outbus <=3D '0'; > if(a =3D '1') then OutBus <=3D ABus; end if; > if(b =3D '1') then OutBus <=3D BBus; end if; > if(c =3D '1') then OutBus <=3D CBus; end if; > if(d =3D '1') then OutBus <=3D DBus; end if; > if(e =3D '1') then OutBus <=3D EBus; end if; >=20 > In concurrent mode: -- a priority tree is implied > OutBus <=3D ABus when a =3D '1' > else BBus when b =3D '1' > else CBus when c =3D '1' > else DBus when d =3D '1' > else EBus when e =3D '1' > else '0'; >=20 > In those above 3 situations, a superfluous condition is posed on the equa= tion, it means a priority tree is implied in all three situations. Actually= most of time when dealing with main data flow, all above conditions are mu= tually exclusive, so there is no need to pose the extra conditions on the f= inal equation. >=20 > Weng Hi KJ, You don't have to look for mutually exclusive conditions in any artificial = examples. Just look at any of your successful projects, check any of complex if-state= ments to see if there are any contiguous conditions which are mutually excl= usive in an if-statement. If you find some, change related "elsif" to "orif= ", then this part of logic would run faster than the original one without e= ffecting other logic.=20 No matter it is a partial or a full if-statement. No matter it is a data bus or a state machine logic. No matter it is a top level if-statement or a deeply nested if-statement. That is the real magic the keyword "orif" plays: you provide more info and = the compiler should generate more efficient logic accordingly. Please remember that a compiler cannot know more than what you understand a= s a code writer. Thank you. Weng From newsfish@newsfish Thu Aug 1 00:32:44 2024 X-Received: by 10.66.232.133 with SMTP id to5mr10831767pac.27.1425577381655; Thu, 05 Mar 2015 09:43:01 -0800 (PST) X-Received: by 10.140.81.229 with SMTP id f92mr201270qgd.28.1425577381565; Thu, 05 Mar 2015 09:43:01 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no4954564igb.0!news-out.google.com!c1ni208qar.1!nntp.google.com!k15no489770qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 09:43:01 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.125.175.43; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 64.125.175.43 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7a9948cf-f0fd-440e-9756-f63dd6b4908f@googlegroups.com> Subject: Want to learn VHDL and FPGA programming? From: jjchristman13@gmail.com Injection-Date: Thu, 05 Mar 2015 17:43:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: news.eternal-september.org comp.lang.vhdl:3628 Hi, if you or anyone you know is interested in training or need additional learning material for VHDL and FPGA programming check out my course! I'm offering a special for $10 with lifetime access!! This coupon is valid till 4/7/15! www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=VHDL10#/ From newsfish@newsfish Thu Aug 1 00:32:44 2024 X-Received: by 10.182.191.65 with SMTP id gw1mr11468354obc.40.1425579242635; Thu, 05 Mar 2015 10:14:02 -0800 (PST) X-Received: by 10.50.60.71 with SMTP id f7mr688061igr.10.1425579242553; Thu, 05 Mar 2015 10:14:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no4975979igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no4975976igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 10:14:01 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Thu, 05 Mar 2015 18:14:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3629 On Friday, February 27, 2015 at 11:51:37 AM UTC-8, KJ wrote: > On Thursday, February 26, 2015 at 9:03:15 PM UTC-5, Weng Tianxiang wrote: > > [0020] If the coding system becomes new part of HDL standards all > > synthesizer manufactures will automatically be forced to implement all = well- > > known wave-pipelining algorithms and techniques within their products, = a=20 > > competition will start for better implementations, making wave-pipelini= ng=20 > > technique available to every digital designer in HDL. > >=20 > A couple of problems with your assumptions: > - No standard body will accept a patent burdened idea to incorporate into= a new revision of a standard. You would likely have to effectively surren= der your patent rights (should they be granted in the first place) in order= to get this to happen. Hi KJ, Here is an example that MIT has 4 patents for HDTV and now it is suing a Ja= panese HDTV manufacturer. MIT Sues Funai Over 4 HDTV Patents http://www.law360.com/articles/342212/mit-sues-funai-over-4-hdtv-patents Weng > - If you think that simply being part of a standard will force synthesis = vendors to do anything at all, you're very mistaken. > - Wave pipelining has not caught on with FPGA suppliers in the 45 years s= ince the concept was first introduced nor in the 16 years since Burleson's = paper was published so uptake on the technique has not been very quick. Th= at doesn't imply that it will never catch on, but it does suggest the wait = will be significant. >=20 > Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:45 2024 X-Received: by 10.42.63.10 with SMTP id a10mr3950159ici.25.1425579617322; Thu, 05 Mar 2015 10:20:17 -0800 (PST) X-Received: by 10.50.107.4 with SMTP id gy4mr334734igb.10.1425579617226; Thu, 05 Mar 2015 10:20:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no3685768igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no3685758igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 10:20:16 -0800 (PST) In-Reply-To: <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6407dd22-922b-4abb-a1e0-34a434343e6f@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Thu, 05 Mar 2015 18:20:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 9808 X-Received-Body-CRC: 774136007 Xref: news.eternal-september.org comp.lang.vhdl:3630 On Thursday, March 5, 2015 at 12:59:17 AM UTC-5, Weng Tianxiang wrote: > On Wednesday, March 4, 2015 at 8:05:16 PM UTC-8, KJ wrote: >=20 > I don't have to generate other example and just use your example with=20 > following changes: Generate a, b, c, d, e in two different state machines= =20 > with the two state machines being mutually exclusive, so that a-e are=20 > mutually exclusive.=20 >=20 You're the one making the unsubstantiated claim, so you should generate the= example. But I did make up one as you said [1]. Two state machines. One= generates a, b, c. The other generates d, e. Which state machine is acti= ve at any given time is controlled by an external device I/O pin. The result is exactly the same as I previously stated. Regardless of the m= ethod chosen to implement the data bus muxing, the synthesized output files= are identical. >=20 > Now please generate your code to see how a compiler knows if a-e are=20 > mutually exclusive. The generated code must be different!!! >=20 They are not different. > What your example provides is the simplest one and a compiler can do it= =20 > very easily!!! You provided no example of how a-e would be generated and probably mutually= exclusive which is more than you provided. You simply made claims based o= n the appearance of the source code and an incorrect assumption of how synt= hesis tools would create logic >=20 > Nature and coding in complex situations are more complex than your exampl= e=20 > provides. Don't try to hide behind 'complex situations'. In a good design you would = not code something that is intended to be mutually exclusive in a way that = makes it possibly not exclusive (i.e. the generation of a-e). So there wou= ld be no a-e, but simply an enumeration or an integer that might get decode= d into a-e at some point in a manner essentially identical to what I showed= . What I'm showing here on this post is that even if you try to make it 'more= complex', the described logic still resulted in absolutely no difference i= n the synthesized logic output so the 'orif' still would provide no benefit= . You're presenting 'orif' as if is somehow widely applicable to any numbe= r of situations. While there might be niches where 'orif' does have use, I= 've shown here in these two posts that it is not nearly as universal as you= seem to think. So the scope of where it is useful is quite a bit smaller.= In fact, to this point, you have not provided a single scenario where it = can actually be shown to result in less logic as you claim. What you shoul= d focus on is what types of situations would 'orif' actually be beneficial = instead of making a claim, not testing it and then be called on it. I'm no= t saying 'orif' isn't useful, but the scope of where it would be useful has= not been shown. >=20 > 1. You must acknowledge that there are situations that only the code writ= er knows which conditions are mutually exclusive. >=20 You have not presented actual working sample of such code to demonstrate a = single situation. I'll accept that maybe you could, but just have not. On= the other side, I've put forth two examples of situations where 'orif' wou= ld have no benefit even though you claimed that it would. For me though, these situations would not arise because I wouldn't be writi= ng code where something that is mutually exclusive is not explicitly coded = in that way as well. There would be no need for "only the code writer know= s..." =20 > In those above 3 situations, a superfluous condition is posed on the=20 > equation, it means a priority tree is implied in all three situations.=20 > Actually most of time when dealing with main data flow, all above=20 > conditions are mutually exclusive, so there is no need to pose the extra= =20 > conditions on the final equation. >=20 I've shown that to not be the case. Kevin [1] Modified code that demonstrates a 'more complex' version of creating a-= e that still results in identical implementation of the logic =3D=3D=3D=3D=3D=3D=3D START OF CODE =3D=3D=3D=3D=3D=3D=3D library ieee;=20 use ieee.std_logic_1164.all;=20 entity Orif_Example is=20 generic( Excl_Method:in natural range 0 to 1; Method: in natural range 0 to 3);=20 port( Clock: in std_ulogic; Selector: in std_ulogic; Address: in natural range 0 to 5;=20 Abus: in std_ulogic;=20 Bbus: in std_ulogic;=20 Cbus: in std_ulogic;=20 Dbus: in std_ulogic;=20 Ebus: in std_ulogic;=20 Outbus: out std_ulogic=20 );=20 end Orif_Example;=20 architecture RTL of Orif_Example is=20 signal a: std_ulogic;=20 signal b: std_ulogic;=20 signal c: std_ulogic;=20 signal d: std_ulogic;=20 signal e: std_ulogic;=20 begin=20 GEN_EXCL_METHOD_0 : if (Excl_Method =3D 0) generate a <=3D '1' when (Address =3D 1) else '0';=20 b <=3D '1' when (Address =3D 2) else '0';=20 c <=3D '1' when (Address =3D 3) else '0';=20 d <=3D '1' when (Address =3D 4) else '0';=20 e <=3D '1' when (Address =3D 5) else '0';=20 end generate GEN_EXCL_METHOD_0; GEN_EXCL_METHOD_1 : if (Excl_Method =3D 1) generate type t_STATES1 is (Idle, St_a, St_b, St_c); type t_STATES2 is (Idle, St_d, St_e); signal State1: t_STATES1; signal State2: t_STATES2; begin process(Clock) begin if rising_edge(Clock) then a <=3D '0'; b <=3D '0'; c <=3D '0'; d <=3D '0'; e <=3D '0'; case State1 is when Idle =3D> null; when St_a =3D> a <=3D '1'; if (Selector =3D '1') th= en State1 <=3D St_b; end if; when St_b =3D> b <=3D '1'; if (Selector =3D '1') th= en State1 <=3D St_c; end if; when St_c =3D> c <=3D '1'; if (Selector =3D '1') th= en State1 <=3D St_a; end if; end case; case State2 is when Idle =3D> null; when St_d =3D> d <=3D '1'; if (Selector =3D '0') th= en State2 <=3D St_e; end if; when St_e =3D> e <=3D '1'; if (Selector =3D '0') th= en State2 <=3D St_d; end if; end case; end if; end process; end generate GEN_EXCL_METHOD_1; GEN_METHOD_0 : if (Method =3D 0) generate=20 Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d and = DBus) or (e and EBus);=20 end generate GEN_METHOD_0;=20 GEN_METHOD_1 : if (Method =3D 1) generate=20 -- One statement structure in serial mode:=20 process(all)=20 begin=20 if(a =3D '1') then OutBus <=3D ABus;=20 elsif(b =3D '1') then Outbus <=3D BBus;=20 elsif(c =3D '1') then Outbus <=3D CBus;=20 elsif(d =3D '1') then Outbus <=3D DBus;=20 elsif(e =3D '1') then Outbus <=3D EBus;=20 else Outbus <=3D '0';=20 end if;=20 end process;=20 end generate GEN_METHOD_1;=20 GEN_METHOD_2 : if (Method =3D 2) generate=20 -- or in another equal form:=20 process(all)=20 begin=20 Outbus <=3D '0';=20 if(a =3D '1') then OutBus <=3D ABus; end if;=20 if(b =3D '1') then OutBus <=3D BBus; end if;=20 if(c =3D '1') then OutBus <=3D CBus; end if;=20 if(d =3D '1') then OutBus <=3D DBus; end if;=20 if(e =3D '1') then OutBus <=3D EBus; end if;=20 end process;=20 end generate GEN_METHOD_2;=20 GEN_METHOD_3 : if (Method =3D 3) generate=20 -- In concurrent mode:=20 OutBus <=3D ABus when a =3D '1'=20 else BBus when b =3D '1'=20 else CBus when c =3D '1'=20 else DBus when d =3D '1'=20 else EBus when e =3D '1'=20 else '0';=20 end generate GEN_METHOD_3;=20 end RTL;=20 =3D=3D=3D=3D=3D=3D=3D END OF CODE =3D=3D=3D=3D=3D=3D=3D From newsfish@newsfish Thu Aug 1 00:32:45 2024 X-Received: by 10.42.76.145 with SMTP id e17mr4122680ick.34.1425579874086; Thu, 05 Mar 2015 10:24:34 -0800 (PST) X-Received: by 10.50.107.4 with SMTP id gy4mr335120igb.10.1425579873979; Thu, 05 Mar 2015 10:24:33 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no4985410igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no4985399igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 10:24:33 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4efc6b8d-837a-4a56-a029-6df96667c6d9@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Thu, 05 Mar 2015 18:24:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 33 Xref: news.eternal-september.org comp.lang.vhdl:3631 On Thursday, March 5, 2015 at 5:59:00 AM UTC-5, Weng Tianxiang wrote: > On Wednesday, March 4, 2015 at 9:59:17 PM UTC-8, Weng Tianxiang wrote: > You don't have to look for mutually exclusive conditions in any artificia= l=20 > examples. You provided the examples. >=20 > Just look at any of your successful projects, check any of complex if- > statements to see if there are any contiguous conditions which are=20 > mutually exclusive in an if-statement. If you find some, change related= =20 > "elsif" to "orif", then this part of logic would run faster than the=20 > original one without effecting other logic.=20 I've already shown that it would not under common situations. >=20 > No matter it is a partial or a full if-statement. > No matter it is a data bus or a state machine logic. > No matter it is a top level if-statement or a deeply nested if-statement. >=20 > That is the real magic the keyword "orif" plays: you provide more info an= d=20 > the compiler should generate more efficient logic accordingly. The only 'more info' that is needed is to code properly. If something is m= utually exclusive, then it should be coded as a single signal that has mult= iple values, not as separate signals. Although as I've demonstrated, separ= ate signals can still be properly analyzed by synthesis and the optimum sol= ution obtained without 'orif'. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:45 2024 X-Received: by 10.236.28.44 with SMTP id f32mr14623093yha.11.1425681947327; Fri, 06 Mar 2015 14:45:47 -0800 (PST) X-Received: by 10.182.46.199 with SMTP id x7mr157993obm.13.1425681947243; Fri, 06 Mar 2015 14:45:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no6044387igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no6044381igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Mar 2015 14:45:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.31.106.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Subject: MODELSIM: Switch between two package libraries depending on environment From: "V." Injection-Date: Fri, 06 Mar 2015 22:45:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 26 Xref: news.eternal-september.org comp.lang.vhdl:3632 I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. I made two packages called intf_defn_sim and intf_defn . They have identical defines, but different values. I was trying to do the following in order to switch between them: use work.intf_defn -- synthesis translate_off _sim -- synthesis translate_on .all; ModelSim compile currently fails out of this as I think it doesn't recognize the "_" in front of the keyword sim. Is there a smarter way to do this? The following compiles without issue, but not quite what I want. use work -- synthesis translate_off .intf_defn -- synthesis translate_on .all; From newsfish@newsfish Thu Aug 1 00:32:46 2024 X-Received: by 10.182.78.69 with SMTP id z5mr18337148obw.4.1425730014674; Sat, 07 Mar 2015 04:06:54 -0800 (PST) X-Received: by 10.140.34.168 with SMTP id l37mr298660qgl.20.1425730014531; Sat, 07 Mar 2015 04:06:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl2no4612134igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no4612133igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Mar 2015 04:06:54 -0800 (PST) In-Reply-To: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:c073:c0e0:28cf:f653; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:c073:c0e0:28cf:f653 References: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <02cac647-df24-45b0-bdff-b3f72bfdbf98@googlegroups.com> Subject: Re: MODELSIM: Switch between two package libraries depending on environment From: KJ Injection-Date: Sat, 07 Mar 2015 12:06:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3633 On Friday, March 6, 2015 at 5:45:49 PM UTC-5, V. wrote: > I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. > > I made two packages called intf_defn_sim and intf_defn . They have identical > defines, but different values. > > Is there a smarter way to do this? > - Put the two packages into separate files - Use the same package name - Include the file with the 'sim' package in Modelsim; include the file with the 'synthesis' package into your synthesis tool. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:46 2024 X-Received: by 10.236.53.10 with SMTP id f10mr18579320yhc.17.1425744699556; Sat, 07 Mar 2015 08:11:39 -0800 (PST) X-Received: by 10.182.233.202 with SMTP id ty10mr170935obc.31.1425744699460; Sat, 07 Mar 2015 08:11:39 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!hl2no4710652igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no6561347igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Mar 2015 08:11:39 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.51.178.164; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 206.51.178.164 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5629b3d6-7633-4d10-a75f-da2afc3583d0@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: jjchristman13@gmail.com Injection-Date: Sat, 07 Mar 2015 16:11:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3634 Hi, if you or anyone you know is interested in training or need additional learning material for VHDL and FPGA programming check out my course! I'm offering a special for $10 with lifetime access!! This coupon is valid till 4/7/15! www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=VHDL10#/ From newsfish@newsfish Thu Aug 1 00:32:46 2024 X-Received: by 10.66.102.100 with SMTP id fn4mr19209481pab.19.1425749927036; Sat, 07 Mar 2015 09:38:47 -0800 (PST) X-Received: by 10.50.30.202 with SMTP id u10mr516659igh.6.1425749927003; Sat, 07 Mar 2015 09:38:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no6613545igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no4744860igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Mar 2015 09:38:46 -0800 (PST) In-Reply-To: <4efc6b8d-837a-4a56-a029-6df96667c6d9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> <4efc6b8d-837a-4a56-a029-6df96667c6d9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <227db440-0de6-45b7-9a5b-c207b931811f@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 07 Mar 2015 17:38:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3635 On Thursday, March 5, 2015 at 10:24:35 AM UTC-8, KJ wrote: > On Thursday, March 5, 2015 at 5:59:00 AM UTC-5, Weng Tianxiang wrote: > > On Wednesday, March 4, 2015 at 9:59:17 PM UTC-8, Weng Tianxiang wrote: > > You don't have to look for mutually exclusive conditions in any artific= ial=20 > > examples. >=20 > You provided the examples. >=20 > >=20 > > Just look at any of your successful projects, check any of complex if- > > statements to see if there are any contiguous conditions which are=20 > > mutually exclusive in an if-statement. If you find some, change related= =20 > > "elsif" to "orif", then this part of logic would run faster than the=20 > > original one without effecting other logic.=20 >=20 > I've already shown that it would not under common situations. >=20 > >=20 > > No matter it is a partial or a full if-statement. > > No matter it is a data bus or a state machine logic. > > No matter it is a top level if-statement or a deeply nested if-statemen= t. > >=20 > > That is the real magic the keyword "orif" plays: you provide more info = and=20 > > the compiler should generate more efficient logic accordingly. >=20 > The only 'more info' that is needed is to code properly. If something is= mutually exclusive, then it should be coded as a single signal that has mu= ltiple values, not as separate signals. Although as I've demonstrated, sep= arate signals can still be properly analyzed by synthesis and the optimum s= olution obtained without 'orif'. >=20 > Kevin Jennings Hi KJ, "If something is mutually exclusive, then it should be coded as a single si= gnal that has multiple values, not as separate signals. " How can a compiler know that a group of signals coming from two different s= tate machines are mutually exclusive unless you give more info? Those situations are common in my coding. As my example has shown, there is no better way than using a case statement= to tell a compiler that those signals are mutually exclusive. Please let me know if there is a better way than using case statement to do= so. Weng From newsfish@newsfish Thu Aug 1 00:32:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp6-1.free.fr!not-for-mail Date: Sun, 08 Mar 2015 11:40:32 +0100 From: manu User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: MODELSIM: Switch between two package libraries depending on environment References: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> In-Reply-To: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Lines: 41 Message-ID: <54fc2731$0$3354$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 08 Mar 2015 11:40:49 CET NNTP-Posting-Host: 82.229.198.7 X-Trace: 1425811249 news-2.free.fr 3354 82.229.198.7:43635 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3636 Hello, this is not a modelsim but a VHDL issue. I had the same problem in a mixed-signal design as "_sig" syntax is widely used among analog designers to reflect active low signals. Identifiers must start with letter. Special characters and even ciphers are not allowed. Some tools mays accept this but most will fail to compile your code. Regards, Manu On 06/03/2015 23:45, V. wrote: > I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. > > I made two packages called intf_defn_sim and intf_defn . They have identical defines, but different values. > > > I was trying to do the following in order to switch between them: > > use work.intf_defn > -- synthesis translate_off > _sim > -- synthesis translate_on > .all; > > > ModelSim compile currently fails out of this as I think it doesn't recognize the "_" in front of the keyword sim. > > Is there a smarter way to do this? > > > > The following compiles without issue, but not quite what I want. > > use work > -- synthesis translate_off > .intf_defn > -- synthesis translate_on > .all; > From newsfish@newsfish Thu Aug 1 00:32:47 2024 X-Received: by 10.182.18.102 with SMTP id v6mr25299962obd.11.1425850834042; Sun, 08 Mar 2015 14:40:34 -0700 (PDT) X-Received: by 10.140.32.34 with SMTP id g31mr399086qgg.21.1425850834007; Sun, 08 Mar 2015 14:40:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no7421039igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no7421036igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Mar 2015 14:40:33 -0700 (PDT) In-Reply-To: <227db440-0de6-45b7-9a5b-c207b931811f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2963:5d3a:e919:6aaf; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2963:5d3a:e919:6aaf References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> <4efc6b8d-837a-4a56-a029-6df96667c6d9@googlegroups.com> <227db440-0de6-45b7-9a5b-c207b931811f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <02bce619-0d24-4649-890f-0354b1238ec4@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Sun, 08 Mar 2015 21:40:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3637 On Saturday, March 7, 2015 at 12:38:52 PM UTC-5, Weng Tianxiang wrote: > On Thursday, March 5, 2015 at 10:24:35 AM UTC-8, KJ wrote: > >=20 > > "If something is mutually exclusive, then it should be coded as a singl= e > > signal that has multiple values, not as separate signals. " >=20 > How can a compiler know that a group of signals coming from two different= =20 > state machines are mutually exclusive unless you give more info? >=20 Synthesis tool don't give a hoot about whether you think something is mutua= lly exclusive or not. They implement Boolean logic from a hardware descrip= tion. I've already shown you two examples where you seem to believe it to = not be possible that synthesis tools do the proper thing, and apparently yo= u can't accept it. > Those situations are common in my coding. >=20 OK...so what? > As my example has shown, there is no better way than using a case stateme= nt=20 > to tell a compiler that those signals are mutually exclusive. >=20 A case statement does not "tell a compiler that those signals are mutually = exclusive". It is a enumeration of all of the states possible and what is = to be done under those conditions. Nothing more, nothing less. > Please let me know if there is a better way than using case statement to = do=20 > so. >=20 I already did, you don't accept it so I'm done. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:47 2024 X-Received: by 10.66.148.40 with SMTP id tp8mr9239662pab.35.1425895362991; Mon, 09 Mar 2015 03:02:42 -0700 (PDT) X-Received: by 10.50.22.3 with SMTP id z3mr644614ige.3.1425895362951; Mon, 09 Mar 2015 03:02:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no7694821igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no5343908igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Mar 2015 03:02:42 -0700 (PDT) In-Reply-To: <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Mon, 09 Mar 2015 10:02:42 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 303 X-Received-Bytes: 19720 X-Received-Body-CRC: 2508480071 Xref: news.eternal-september.org comp.lang.vhdl:3638 On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote: > On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wrote: > > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wrote= : > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > >=20 > > > I have filed a provisional patent application: "Systematic method of = coding wave pipelined circuits in HDL". If it is proved correct, the patent= will introduce 1 keyword, 3 permanent constants, 1 concurrent statement an= d four source code modules for a new library in HDL and thoroughly resolve = a pending problem so that every digital designer can code wave-pipelined ci= rcuits in HDL. > > >=20 > > > Here is the abstract of the invention: > > >=20 > > > The present invention classifies all critical paths into two basi= c types: a series critical path and a feedback critical path, and divides e= ach of wave-pipelined circuits into two components: a static logic part, ca= lled critical path component (CPC), and a dynamic logic part, formalized in= to four wave-pipelining components (WPC) shared by all wave-pipelined circu= its. Each wave-pipelining ready code in HDL comprises two components: a WPC= instantiation and a CPC instantiation wire-connected and linked by a new l= ink statement. Each WPC has new wave constants which play the same role as = generic constants do, but whose initial values are determined and assigned = by a synthesizer after code analysis, so designers can use after-synthesiza= tion information in their code before synthesization for wave-pipelining te= chnology. The responsibility of analyzing and manipulating wave-pipelining = ready code, generating and implementing wave-pipelined circuits on a design= -wide or chip-wide scale in HDL is shifted from designers to synthesizers. > > >=20 > > > Anyone who are interested in its content is welcome to send a email r= equest to the following email address: wtx wtx @ gmail . com with title "Sy= stematic" and he will receive the full documents: one specification, 9 draw= ings and one text file in VHDL. > > >=20 > > > If one reviews the files and feels that it would be a good thing to r= ecommend the application to his company to buy it, the first person to do i= t after his recommended company does so will receive $10,000 commission fee= . > > >=20 > > > Thank you. > > >=20 > > > Weng > >=20 > > Hi, > > I want to add some introductions to what the wave-pipelined circuits ar= e and their status. > >=20 > > [0003] A synchronous digital system contains a lot of registers. Val= id data flow through successive registers from system input registers to sy= stem output registers. All data flows are synchronous with triggering edges= of a chip clock. For example, data flow from registers A to registers B, f= rom registers B to registers C and so on in a successive order on the same = clock cycle. > > [0004] A path in a synchronous digital system is a route between any= neighboring registers connected by combinational logic. If the target runn= ing frequency for a digital design is predetermined, the upper limit of pro= pagating time for any paths is determined and has the inverse value of the = target running frequency. A path is called a critical path if the time sign= als take to propagate through it is beyond the predetermined propagating ti= me, and the time is called the path's critical time. If there are any criti= cal paths, digital designers must spend time reducing all critical times by= all means and eliminating all critical paths to meet the target running fr= equency. > > [0005] Wave-pipelining is a technology which completes an operation = that needs several clock cycles to propagate without intermediate registers= and with input data acceptable on every clock cycle. For example, in a con= ventional pipelining operation, data flow from registers A to registers D t= hrough registers B and C to divide the critical path time into multiple sma= ller intervals to meet the critical time: A to B to C to D; with wave-pipel= ining, data flow through registers A and D without intermediate registers B= and C. Absolutely, wave-pipelining will reduce logic resource usage and is= superior to the conventional pipelining technology if it can be used. > >=20 > > Here are the most important inequalities involving wave-pipelining from= paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burles= on et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, no.= 3, pp. 464-474, Sep. 1998. > >=20 > > [0018] Currently many memory chip manufacturers successfully use wav= e-pipelining in their memory chip products with higher rate outputs, reduce= d power consumption and logic resources; and a few scientists use FPGA chip= s as a base to show some circuits can be done with wave-pipelining in isola= ted environments. Their works prove that the wave-pipelining is a very powe= rful tool to reduce power consumption and logic resources. Now there are tw= o major existing obstacles preventing any ordinary digital designers from u= sing the wave-pipelining in HDL: > > * The software algorithms making wave-pipelining successful, like Wong = and Klass algorithms and others, have already been developed and matured, b= ut ordinary digital designers have no means or resources to access to the t= echnology, because there are no international HDL standards on how synthesi= zer manufacturers incorporate those capabilities into their products. > > * HDL needs the capabilities for digital designers to write wave-pipeli= ning ready code for any number of critical paths on a design-wide or chip-w= ide scale instead of in an isolated environment and the written code can be= identified, synthesized and used to generate wave-pipelined circuits by an= y synthesizer in ASIC or FPGA, and they should be part of HDL standards.=20 > > [0019] The target of the present invention is: > > * Invent a wave-pipelining coding system as new part of HDL standards f= or designers to write wave-pipelining ready code which can be identified, s= ynthesized and used to generate wave-pipelined circuits by any synthesizer = in ASIC or FPGA. > > * Make wave-pipelining ready code written based on the coding system wo= rking with no extra logic generated, compared with independently written wa= ve-pipelined circuits, and with no code changes when switching from non-wav= e-pipelined mode to wave-pipelined mode or vice verse if all of wave-pipeli= ning ready code meet wave-pipelining requirements.=20 > > * Shift burdens of analyzing and manipulating wave-pipelining ready cod= e, generating and implementing wave-pipelined circuits on a design-wide or = chip-wide scale in HDL from individual designers to synthesizer manufacture= rs. > > [0020] If the coding system becomes new part of HDL standards all sy= nthesizer manufactures will automatically be forced to implement all well-k= nown wave-pipelining algorithms and techniques within their products, a com= petition will start for better implementations, making wave-pipelining tech= nique available to every digital designer in HDL. > >=20 > > Weng >=20 > Here I add some contents of the invention: >=20 > Main idea behind the present invention >=20 > [0057] The most difficult part coding all types of wave-pipelined circ= uits on a design-wide scale in HDL is that a wave-pipelined circuit code al= ways comprises two logic parts:=20 > * A static logic part: it doesn't change if the number of series clock cy= cles through the circuit changes and is unique for each of wave-pipelined c= ircuits. > * A dynamic logic part: it does change if the number of series clock cycl= es through the circuit changes and is the same for one of groups of wave-pi= pelined circuits. > [0058] Every wave-pipelined circuit has its own change rules and those= changes are unknown to designers when they are writing code and will be kn= own to a synthesizer only after it has analyzed the circuit. > [0059] The present invention classifies all critical paths into two ba= sic types: a series critical path and a feedback critical path, and divides= each of wave-pipelined circuits into two components: one is static logic p= art and called critical path component (CPC); another is dynamic logic part= and formalized into four wave-pipelining components (WPC) shared by all wa= ve-pipelined circuits. Under the present invention each of standard wave-pi= pelining ready code in HDL comprises two components: a WPC instantiation an= d a CPC instantiation which are wire-connected and linked by a new concurre= nt link statement. Each of four WPC embodiments has a group of new type wav= e constant, which plays the same role as a generic constant does, but whose= initial value is determined and assigned by a synthesizer after it has ana= lyzed the linked CPC component under slow mode and target mode, respectivel= y, so designers can use after-synthesization information in their code befo= re synthesization in HDL for wave-pipelining technology. Following the inst= ructions of the present invention creates a situation that digital designer= s can write wave-pipelining ready code in HDL and the responsibility of ana= lyzing and manipulating wave-pipelining ready code, generating and implemen= ting wave-pipelined circuits on a design-wide or chip-wide scale in HDL is = shifted from individual designers to synthesizer manufacturers. >=20 > How the method works >=20 > [0060] The systematic method of coding wave-pipelined circuits in HDL = comprises following ten parts: > 1. Define five signals, one counter, one switch and one table that will b= e used when generating wave-pipelined circuits on a design-wide or chip-wid= e scale in HDL. > 2. Define the interfaces of a CPC each of which encapsulates a critical p= ath's static logic part. > 3. Define and implement four WPC embodiments in HDL each of which is a cr= itical path's dynamic logic part: a series_module, an input_delay_module, a= multiple_copy_module1 and a multiple_copy_module2. > 4. Define one new keyword wave and three new wave constants which provide= a means to dynamically transfer after-synthesization information to design= ers' code before synthesization. > 5. Define the methods of determining and searching for wave constant valu= es of a known WPC instantiation under slow mode and target mode, respective= ly. > 6. Define three versions of a concurrent link statement: link1, link2 and= link3, and rules on how they are used. > 7. Define the pairing rules between a WPC and a CPC. > 8. Define how a digital designer prepares wave-pipelining ready code syst= ematically. > 9. Shift the responsibility of analyzing and manipulating wave-pipelining= ready code, generating and implementing wave-pipelined circuits on a desig= n-wide or chip-wide scale in HDL from individual designers to synthesizer m= anufacturers. > 10. Define how four WPC embodiments are simulated and debugged under any = of current versions of a synthesizer in HDL. > [0061] It is fair to put the burden of successfully generating wave-pi= pelined circuits based on wave-pipelining ready code squarely on synthesize= r manufacturers' shoulder if all necessary information is passed to a synth= esizer. For example, with tens of papers claiming that successful wave-pipe= lined circuits are implemented in FPGA chips in an isolated environment, it= is the responsibility of FPGA synthesizers to be capable of generating tho= se wave-pipelined circuits in a design-wide environment without designers' = further involvements, a process similar for them to the task of generating = a circuit with the highest running frequency and minimum used resources if = possible for any normal digital design code. >=20 > Thank you for your reading. Here are more contents. Definitions of wave-pipelining component and critical path component [0062] A design component is called a critical path component (CPC) if i= t is an entity (a term in VHDL-2002) in HDL and encapsulates the static log= ic part of a critical path which is to be wave-pipelined circuit. There are= two types of CPCs:=20 =E2=80=A2 A series CPC: it encapsulates a series critical path=E2=80=99s st= atic logic part. =E2=80=A2 A feedback CPC: it encapsulates a feedback critical path=E2=80=99= s static logic part.=20 [0063] A CPC also refers to a CPC instantiation when it will not be misu= nderstood. The required interfaces of both a series CPC and a feedback CPC = are always the same. The combinational logic of a CPC may be located within= or outside of the component and there is no limit on it.=20 [0064] A design component is called a wave-pipelining component (WPC) if= it is an entity in HDL, provided by HDL in a new wave-pipelining system li= brary and used to generate a critical path=E2=80=99s dynamic logic part, i.= e., to generate output data valid signal and write enable signals to the in= put and output registers of a critical path.=20 [0065] There are three types of WPC:=20 =E2=80=A2 A series_module is used to connect to a series CPC with input dat= a acceptable on every clock cycle. =E2=80=A2 An input_delay_module is used to connect to a series or feedback = CPC with input data acceptable on every one or more clock cycle. =E2=80=A2 A multiple_copy_module1 or a multiple_copy_module2 is used to con= nect to multiple copied series or feedback CPCs with input data acceptable = on every clock cycle. [0066] A WPC also refers to a WPC instantiation when it will not be misu= nderstood. Later multiple_copy_module refers to either of multiple_copy_mod= ule1 and multiple_copy_module2. A synthesizer=E2=80=99s new signals, switch and table [0067] A synthesizer that is able of handling wave-pipelining needs six = signals, one switch, one table and the table=E2=80=99s row index to help fi= nish its job: =E2=80=A2 A floating signal target_running_frequency: it is set up by a des= igner and the target running frequency under which a design finally runs. =E2=80=A2 A bit signal generate_circuit: it is set up by a designer and its= initial value is deasserted. A synthesizer will generate related circuit f= iles for a design under slow mode for slow mode hardware testing if generat= e_circuit is asserted and no errors are detected after a synthesization, or= will not otherwise. A synthesizer will always generate related circuit fil= es for a design under target mode for target mode hardware testing if no er= rors are detected after a synthesization. =E2=80=A2 A bit signal feedback_bit: it is set up by a synthesizer and its = initial value is deasserted. Assert the bit if a CPC is being analyzed and = determined to have feedbacks, and deassert it after the analysis is finishe= d. =E2=80=A2 A bit signal keep_target_circuit: it is set up by a designer and = its initial value is deasserted. Assert the bit if a designer wants to keep= all CPC new circuits automatically and successfully modified by a synthesi= zer under target mode unchanged under slow mode when he is switching to syn= thesize the same design from under target mode to under slow mode and the r= elated code doesn=E2=80=99t change, or deassert it otherwise. The bit provi= des a method for a designer to check if the new automatically and successfu= lly modified circuits by a synthesizer don=E2=80=99t change basic logic.=20 =E2=80=A2 An integer signal parent_series_clock_number: it is set up by a s= ynthesizer and Its initial value is zero. When the instantiation of a WPC d= elay_input_module or multiple_copy_module is being analyzed and executed it= s series_clock_number value is stored in parent_series_clock_number, and it= is cleared to zero when the execution is finished. =E2=80=A2 An integer signal start_number: it is set up by a synthesizer and= used when the synthesizer determines that a CPC cannot meet the wave-pipel= ining requirements with input data acceptable on every clock cycle and the = CPC is linked with a WPC input_delay_module or multiple_copy_module. The st= art_number is made equal to 2 if a WPC multiple_copy_module is linked or to= feedback_clock_number if a WPC input_delay_module is linked as the startin= g value of wave constant input_clock_number or multiple_copy_number. =E2=80=A2 A bit switch running_mode: it is set up by a designer and it has = two valid values with slow mode being its initial value: o Slow mode: under slow mode a digital designer designs his code, a design = is synthesized, simulated, and hardware tested under the following assumpti= ons: =EF=82=A7 Signals take one clock cycle to propagate through any of CPCs und= er slow running frequency. =EF=82=A7 Any of CPCs has input data acceptable on every clock cycle. =EF=82=A7 No multiple copied CPCs are generated. o Target mode: under target mode a design is synthesized, simulated, hardwa= re tested and finally runs under predetermined target running frequency, an= d its implementation is determined and generated by a synthesizer under the= following assumptions: =EF=82=A7 Signals take one or more clock cycle to propagate through any of = CPCs as designed. =EF=82=A7 Each of CPCs has input data acceptable on every one or more clock= cycle as wave-pipelining ready code indicates and it is necessary. =EF=82=A7 Multiple copied CPCs are generated as wave-pipelining ready code = indicates and it is necessary. =E2=80=A2 A wave constant signal table: it is generated and manipulated by = a synthesizer and stores information about each linked pair of a CPC and a = WPC; all wave constant values and alias wave constant values can be accesse= d from the table. =E2=80=A2 An integer row_index to the wave constant signal table: it is set= up by a synthesizer and its initial value is 1. It is used as a row index = for a new link statement in the wave constant signal table and will be incr= eased by 1 after a synthesizer finishes the filling of the row during the s= ource code scanning.=20 Thank you for your reading. Weng From newsfish@newsfish Thu Aug 1 00:32:48 2024 X-Received: by 10.42.33.134 with SMTP id i6mr25953212icd.22.1425993436750; Tue, 10 Mar 2015 06:17:16 -0700 (PDT) X-Received: by 10.182.107.228 with SMTP id hf4mr276418obb.6.1425993436405; Tue, 10 Mar 2015 06:17:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!ecngs!feeder2.ecngs.de!news.glorb.com!hl2no8681962igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no6025916igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 10 Mar 2015 06:17:16 -0700 (PDT) In-Reply-To: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4625ee40-c5a1-4d8b-9206-baebb356ffc2@googlegroups.com> Subject: Re: MODELSIM: Switch between two package libraries depending on environment From: Andy Injection-Date: Tue, 10 Mar 2015 13:17:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3639 VHDL 2008 includes generics for packages. Check your tool documentation to see if it is supported yet (many do because generics are used for the fixed and floating point packages). Define a generic on your package that alters the values of the constants. You may need to initialize the constants with functions that uses the generic to select which value to return. If that generic value is passed down from a top-level generic, then you can override the default value in the tool command line. I usually set the default to the value for synthesis, and let the simulation scripts override it. Hope this helps, Andy From newsfish@newsfish Thu Aug 1 00:32:48 2024 X-Received: by 10.182.97.2 with SMTP id dw2mr40008929obb.0.1426100451771; Wed, 11 Mar 2015 12:00:51 -0700 (PDT) X-Received: by 10.182.149.235 with SMTP id ud11mr348515obb.42.1426100451650; Wed, 11 Mar 2015 12:00:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no6844709igb.0!news-out.google.com!db6ni50310igc.0!nntp.google.com!hl2no6844700igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Mar 2015 12:00:51 -0700 (PDT) In-Reply-To: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.91.173.42 References: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: MODELSIM: Switch between two package libraries depending on environment From: "V." Injection-Date: Wed, 11 Mar 2015 19:00:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3640 On Friday, March 6, 2015 at 4:45:49 PM UTC-6, V. wrote: > I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. > > I made two packages called intf_defn_sim and intf_defn . They have identical defines, but different values. > > > I was trying to do the following in order to switch between them: > > use work.intf_defn > -- synthesis translate_off > _sim > -- synthesis translate_on > .all; > > > ModelSim compile currently fails out of this as I think it doesn't recognize the "_" in front of the keyword sim. > > Is there a smarter way to do this? > > > > The following compiles without issue, but not quite what I want. > > use work > -- synthesis translate_off > .intf_defn > -- synthesis translate_on > .all; On Friday, March 6, 2015 at 4:45:49 PM UTC-6, V. wrote: > I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. > > I made two packages called intf_defn_sim and intf_defn . They have identical defines, but different values. > > > I was trying to do the following in order to switch between them: > > use work.intf_defn > -- synthesis translate_off > _sim > -- synthesis translate_on > .all; > > > ModelSim compile currently fails out of this as I think it doesn't recognize the "_" in front of the keyword sim. > > Is there a smarter way to do this? > > > > The following compiles without issue, but not quite what I want. > > use work > -- synthesis translate_off > .intf_defn > -- synthesis translate_on > .all; Gents, Appreciate all the great feedback. I should clarify that the main reason I'm trying to do this is because of some pretty long (and numerous) delays I've setup in my design (hundreds of milliseconds), and did not want to bog down my simulation. I seem to have some success by redefining these delays within the modules that use them using the synthesis pragma. So the shorter delays should only take affect in simulation, and for synthesis, it will use the longer delays defined in my package file. -- these defines override the longer delays -- synthesis translate_off constant DELAY : integer := 10; -- 10clk cycles instead of 10ms constant DELAY2 : integer := 50; .. .. constant DELAY30 : integer := 20; -- synthesis translate_on Is this is a viable approach? From newsfish@newsfish Thu Aug 1 00:32:48 2024 X-Received: by 10.43.135.194 with SMTP id ih2mr44529010icc.7.1426311907233; Fri, 13 Mar 2015 22:45:07 -0700 (PDT) X-Received: by 10.50.35.162 with SMTP id i2mr600710igj.4.1426311907186; Fri, 13 Mar 2015 22:45:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no11763263igb.0!news-out.google.com!db6ni50316igc.0!nntp.google.com!hl2no11763261igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Mar 2015 22:45:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 14 Mar 2015 05:45:07 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3641 On Monday, March 9, 2015 at 3:02:48 AM UTC-7, Weng Tianxiang wrote: > On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote: > > On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wrot= e: > > > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wro= te: > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > >=20 > > > > I have filed a provisional patent application: "Systematic method o= f coding wave pipelined circuits in HDL". If it is proved correct, the pate= nt will introduce 1 keyword, 3 permanent constants, 1 concurrent statement = and four source code modules for a new library in HDL and thoroughly resolv= e a pending problem so that every digital designer can code wave-pipelined = circuits in HDL. > > > >=20 > > > > Here is the abstract of the invention: > > > >=20 > > > > The present invention classifies all critical paths into two ba= sic types: a series critical path and a feedback critical path, and divides= each of wave-pipelined circuits into two components: a static logic part, = called critical path component (CPC), and a dynamic logic part, formalized = into four wave-pipelining components (WPC) shared by all wave-pipelined cir= cuits. Each wave-pipelining ready code in HDL comprises two components: a W= PC instantiation and a CPC instantiation wire-connected and linked by a new= link statement. Each WPC has new wave constants which play the same role a= s generic constants do, but whose initial values are determined and assigne= d by a synthesizer after code analysis, so designers can use after-synthesi= zation information in their code before synthesization for wave-pipelining = technology. The responsibility of analyzing and manipulating wave-pipelinin= g ready code, generating and implementing wave-pipelined circuits on a desi= gn-wide or chip-wide scale in HDL is shifted from designers to synthesizers= . > > > >=20 > > > > Anyone who are interested in its content is welcome to send a email= request to the following email address: wtx wtx @ gmail . com with title "= Systematic" and he will receive the full documents: one specification, 9 dr= awings and one text file in VHDL. > > > >=20 > > > > If one reviews the files and feels that it would be a good thing to= recommend the application to his company to buy it, the first person to do= it after his recommended company does so will receive $10,000 commission f= ee. > > > >=20 > > > > Thank you. > > > >=20 > > > > Weng > > >=20 > > > Hi, > > > I want to add some introductions to what the wave-pipelined circuits = are and their status. > > >=20 > > > [0003] A synchronous digital system contains a lot of registers. V= alid data flow through successive registers from system input registers to = system output registers. All data flows are synchronous with triggering edg= es of a chip clock. For example, data flow from registers A to registers B,= from registers B to registers C and so on in a successive order on the sam= e clock cycle. > > > [0004] A path in a synchronous digital system is a route between a= ny neighboring registers connected by combinational logic. If the target ru= nning frequency for a digital design is predetermined, the upper limit of p= ropagating time for any paths is determined and has the inverse value of th= e target running frequency. A path is called a critical path if the time si= gnals take to propagate through it is beyond the predetermined propagating = time, and the time is called the path's critical time. If there are any cri= tical paths, digital designers must spend time reducing all critical times = by all means and eliminating all critical paths to meet the target running = frequency. > > > [0005] Wave-pipelining is a technology which completes an operatio= n that needs several clock cycles to propagate without intermediate registe= rs and with input data acceptable on every clock cycle. For example, in a c= onventional pipelining operation, data flow from registers A to registers D= through registers B and C to divide the critical path time into multiple s= maller intervals to meet the critical time: A to B to C to D; with wave-pip= elining, data flow through registers A and D without intermediate registers= B and C. Absolutely, wave-pipelining will reduce logic resource usage and = is superior to the conventional pipelining technology if it can be used. > > >=20 > > > Here are the most important inequalities involving wave-pipelining fr= om paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burl= eson et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, n= o. 3, pp. 464-474, Sep. 1998. > > >=20 > > > [0018] Currently many memory chip manufacturers successfully use w= ave-pipelining in their memory chip products with higher rate outputs, redu= ced power consumption and logic resources; and a few scientists use FPGA ch= ips as a base to show some circuits can be done with wave-pipelining in iso= lated environments. Their works prove that the wave-pipelining is a very po= werful tool to reduce power consumption and logic resources. Now there are = two major existing obstacles preventing any ordinary digital designers from= using the wave-pipelining in HDL: > > > * The software algorithms making wave-pipelining successful, like Won= g and Klass algorithms and others, have already been developed and matured,= but ordinary digital designers have no means or resources to access to the= technology, because there are no international HDL standards on how synthe= sizer manufacturers incorporate those capabilities into their products. > > > * HDL needs the capabilities for digital designers to write wave-pipe= lining ready code for any number of critical paths on a design-wide or chip= -wide scale instead of in an isolated environment and the written code can = be identified, synthesized and used to generate wave-pipelined circuits by = any synthesizer in ASIC or FPGA, and they should be part of HDL standards.= =20 > > > [0019] The target of the present invention is: > > > * Invent a wave-pipelining coding system as new part of HDL standards= for designers to write wave-pipelining ready code which can be identified,= synthesized and used to generate wave-pipelined circuits by any synthesize= r in ASIC or FPGA. > > > * Make wave-pipelining ready code written based on the coding system = working with no extra logic generated, compared with independently written = wave-pipelined circuits, and with no code changes when switching from non-w= ave-pipelined mode to wave-pipelined mode or vice verse if all of wave-pipe= lining ready code meet wave-pipelining requirements.=20 > > > * Shift burdens of analyzing and manipulating wave-pipelining ready c= ode, generating and implementing wave-pipelined circuits on a design-wide o= r chip-wide scale in HDL from individual designers to synthesizer manufactu= rers. > > > [0020] If the coding system becomes new part of HDL standards all = synthesizer manufactures will automatically be forced to implement all well= -known wave-pipelining algorithms and techniques within their products, a c= ompetition will start for better implementations, making wave-pipelining te= chnique available to every digital designer in HDL. > > >=20 > > > Weng > >=20 > > Here I add some contents of the invention: > >=20 > > Main idea behind the present invention > >=20 > > [0057] The most difficult part coding all types of wave-pipelined ci= rcuits on a design-wide scale in HDL is that a wave-pipelined circuit code = always comprises two logic parts:=20 > > * A static logic part: it doesn't change if the number of series clock = cycles through the circuit changes and is unique for each of wave-pipelined= circuits. > > * A dynamic logic part: it does change if the number of series clock cy= cles through the circuit changes and is the same for one of groups of wave-= pipelined circuits. > > [0058] Every wave-pipelined circuit has its own change rules and tho= se changes are unknown to designers when they are writing code and will be = known to a synthesizer only after it has analyzed the circuit. > > [0059] The present invention classifies all critical paths into two = basic types: a series critical path and a feedback critical path, and divid= es each of wave-pipelined circuits into two components: one is static logic= part and called critical path component (CPC); another is dynamic logic pa= rt and formalized into four wave-pipelining components (WPC) shared by all = wave-pipelined circuits. Under the present invention each of standard wave-= pipelining ready code in HDL comprises two components: a WPC instantiation = and a CPC instantiation which are wire-connected and linked by a new concur= rent link statement. Each of four WPC embodiments has a group of new type w= ave constant, which plays the same role as a generic constant does, but who= se initial value is determined and assigned by a synthesizer after it has a= nalyzed the linked CPC component under slow mode and target mode, respectiv= ely, so designers can use after-synthesization information in their code be= fore synthesization in HDL for wave-pipelining technology. Following the in= structions of the present invention creates a situation that digital design= ers can write wave-pipelining ready code in HDL and the responsibility of a= nalyzing and manipulating wave-pipelining ready code, generating and implem= enting wave-pipelined circuits on a design-wide or chip-wide scale in HDL i= s shifted from individual designers to synthesizer manufacturers. > >=20 > > How the method works > >=20 > > [0060] The systematic method of coding wave-pipelined circuits in HD= L comprises following ten parts: > > 1. Define five signals, one counter, one switch and one table that will= be used when generating wave-pipelined circuits on a design-wide or chip-w= ide scale in HDL. > > 2. Define the interfaces of a CPC each of which encapsulates a critical= path's static logic part. > > 3. Define and implement four WPC embodiments in HDL each of which is a = critical path's dynamic logic part: a series_module, an input_delay_module,= a multiple_copy_module1 and a multiple_copy_module2. > > 4. Define one new keyword wave and three new wave constants which provi= de a means to dynamically transfer after-synthesization information to desi= gners' code before synthesization. > > 5. Define the methods of determining and searching for wave constant va= lues of a known WPC instantiation under slow mode and target mode, respecti= vely. > > 6. Define three versions of a concurrent link statement: link1, link2 a= nd link3, and rules on how they are used. > > 7. Define the pairing rules between a WPC and a CPC. > > 8. Define how a digital designer prepares wave-pipelining ready code sy= stematically. > > 9. Shift the responsibility of analyzing and manipulating wave-pipelini= ng ready code, generating and implementing wave-pipelined circuits on a des= ign-wide or chip-wide scale in HDL from individual designers to synthesizer= manufacturers. > > 10. Define how four WPC embodiments are simulated and debugged under an= y of current versions of a synthesizer in HDL. > > [0061] It is fair to put the burden of successfully generating wave-= pipelined circuits based on wave-pipelining ready code squarely on synthesi= zer manufacturers' shoulder if all necessary information is passed to a syn= thesizer. For example, with tens of papers claiming that successful wave-pi= pelined circuits are implemented in FPGA chips in an isolated environment, = it is the responsibility of FPGA synthesizers to be capable of generating t= hose wave-pipelined circuits in a design-wide environment without designers= ' further involvements, a process similar for them to the task of generatin= g a circuit with the highest running frequency and minimum used resources i= f possible for any normal digital design code. > >=20 > > Thank you for your reading. >=20 > Here are more contents. >=20 > Definitions of wave-pipelining component and critical path component >=20 > [0062] A design component is called a critical path component (CPC) if= it is an entity (a term in VHDL-2002) in HDL and encapsulates the static l= ogic part of a critical path which is to be wave-pipelined circuit. There a= re two types of CPCs:=20 > =E2=80=A2 A series CPC: it encapsulates a series critical path=E2=80=99s = static logic part. > =E2=80=A2 A feedback CPC: it encapsulates a feedback critical path=E2=80= =99s static logic part.=20 >=20 > [0063] A CPC also refers to a CPC instantiation when it will not be mi= sunderstood. The required interfaces of both a series CPC and a feedback CP= C are always the same. The combinational logic of a CPC may be located with= in or outside of the component and there is no limit on it.=20 >=20 > [0064] A design component is called a wave-pipelining component (WPC) = if it is an entity in HDL, provided by HDL in a new wave-pipelining system = library and used to generate a critical path=E2=80=99s dynamic logic part, = i.e., to generate output data valid signal and write enable signals to the = input and output registers of a critical path.=20 >=20 > [0065] There are three types of WPC:=20 > =E2=80=A2 A series_module is used to connect to a series CPC with input d= ata acceptable on every clock cycle. > =E2=80=A2 An input_delay_module is used to connect to a series or feedbac= k CPC with input data acceptable on every one or more clock cycle. > =E2=80=A2 A multiple_copy_module1 or a multiple_copy_module2 is used to c= onnect to multiple copied series or feedback CPCs with input data acceptabl= e on every clock cycle. >=20 > [0066] A WPC also refers to a WPC instantiation when it will not be mi= sunderstood. Later multiple_copy_module refers to either of multiple_copy_m= odule1 and multiple_copy_module2. >=20 > A synthesizer=E2=80=99s new signals, switch and table >=20 > [0067] A synthesizer that is able of handling wave-pipelining needs si= x signals, one switch, one table and the table=E2=80=99s row index to help = finish its job: > =E2=80=A2 A floating signal target_running_frequency: it is set up by a d= esigner and the target running frequency under which a design finally runs. > =E2=80=A2 A bit signal generate_circuit: it is set up by a designer and i= ts initial value is deasserted. A synthesizer will generate related circuit= files for a design under slow mode for slow mode hardware testing if gener= ate_circuit is asserted and no errors are detected after a synthesization, = or will not otherwise. A synthesizer will always generate related circuit f= iles for a design under target mode for target mode hardware testing if no = errors are detected after a synthesization. > =E2=80=A2 A bit signal feedback_bit: it is set up by a synthesizer and it= s initial value is deasserted. Assert the bit if a CPC is being analyzed an= d determined to have feedbacks, and deassert it after the analysis is finis= hed. > =E2=80=A2 A bit signal keep_target_circuit: it is set up by a designer an= d its initial value is deasserted. Assert the bit if a designer wants to ke= ep all CPC new circuits automatically and successfully modified by a synthe= sizer under target mode unchanged under slow mode when he is switching to s= ynthesize the same design from under target mode to under slow mode and the= related code doesn=E2=80=99t change, or deassert it otherwise. The bit pro= vides a method for a designer to check if the new automatically and success= fully modified circuits by a synthesizer don=E2=80=99t change basic logic.= =20 > =E2=80=A2 An integer signal parent_series_clock_number: it is set up by a= synthesizer and Its initial value is zero. When the instantiation of a WPC= delay_input_module or multiple_copy_module is being analyzed and executed = its series_clock_number value is stored in parent_series_clock_number, and = it is cleared to zero when the execution is finished. > =E2=80=A2 An integer signal start_number: it is set up by a synthesizer a= nd used when the synthesizer determines that a CPC cannot meet the wave-pip= elining requirements with input data acceptable on every clock cycle and th= e CPC is linked with a WPC input_delay_module or multiple_copy_module. The = start_number is made equal to 2 if a WPC multiple_copy_module is linked or = to feedback_clock_number if a WPC input_delay_module is linked as the start= ing value of wave constant input_clock_number or multiple_copy_number. > =E2=80=A2 A bit switch running_mode: it is set up by a designer and it ha= s two valid values with slow mode being its initial value: > o Slow mode: under slow mode a digital designer designs his code, a desig= n is synthesized, simulated, and hardware tested under the following assump= tions: > =EF=82=A7 Signals take one clock cycle to propagate through any of CPCs u= nder slow running frequency. > =EF=82=A7 Any of CPCs has input data acceptable on every clock cycle. > =EF=82=A7 No multiple copied CPCs are generated. > o Target mode: under target mode a design is synthesized, simulated, hard= ware tested and finally runs under predetermined target running frequency, = and its implementation is determined and generated by a synthesizer under t= he following assumptions: > =EF=82=A7 Signals take one or more clock cycle to propagate through any o= f CPCs as designed. > =EF=82=A7 Each of CPCs has input data acceptable on every one or more clo= ck cycle as wave-pipelining ready code indicates and it is necessary. > =EF=82=A7 Multiple copied CPCs are generated as wave-pipelining ready cod= e indicates and it is necessary. > =E2=80=A2 A wave constant signal table: it is generated and manipulated b= y a synthesizer and stores information about each linked pair of a CPC and = a WPC; all wave constant values and alias wave constant values can be acces= sed from the table. > =E2=80=A2 An integer row_index to the wave constant signal table: it is s= et up by a synthesizer and its initial value is 1. It is used as a row inde= x for a new link statement in the wave constant signal table and will be in= creased by 1 after a synthesizer finishes the filling of the row during the= source code scanning.=20 >=20 > Thank you for your reading. >=20 > Weng Here are more contents. It shows how a complicated problem is resolved by c= reative ideas. New keyword wave and wave constant in HDL [0068] When writing wave-pipelining code, digital designers don=E2=80=99= t know how many clock cycles signals need to propagate through a critical p= ath, and to finish their jobs, it may take several working cycles for them = manually to adjust their code to make a wave-pipelined circuit working. Thi= s method is not feasible on a design-wide or chip-wide scale, because a des= ign may have 100 or more critical paths to be wave-pipelined circuits and t= here is no guarantee for designers to perfectly remember which is finished = and which is not, and most importantly, synthesizers are left aside of the = business of wave-pipelining, giving no help at all. One of obstacles using = wave-pipelining in HDL is how to establish a communication channel between = a synthesizer and digital designers to provide the following essential func= tions: =E2=80=A2 How a designer can use after-synthesization information to write = code for wave-pipelined circuits before they have been synthesized in HDL f= or wave-pipelining technology. This function is not necessary for successfu= lly generating a wave-pipelined circuit, but beneficial to implement a comp= lex one. =E2=80=A2 If all pieces of wave-pipelining ready code are written, a design= has passed simulations and/or hardware testing under slow mode perfectly, = and a synthesizer certifies that all wave-pipelining requirements are met w= ith input data acceptable on every one or more clock cycle and no errors ar= e detected after a synthesization, then correct full design circuits can be= generated under target mode and work as designed with no code change durin= g the switching from slow mode to target mode or vice verse on a design-wid= e or chip-wide scale. This function is critical and essential for successf= ully generating all wave-pipelined circuits on a design-wide or chip-wide s= cale in HDL. [0069] New keyword wave and three wave constants are introduced to resol= ve the problem. In the following listing characters in bold type are new su= ggested definitions based on VHDL-2002. entity_declaration ::=3D=20 entity identifier is entity_header entity_declarative_part [begin entity_statement_part ] end [ entity ] [ entity_simple_name ] ; entity_header ::=3D [formal_generic_clause ] [formal_port_clause ] generic_clause ::=3D generic ( generic_list ) ; generic_list ::=3D generic_interface_list interface_list ::=3D interface_element { ; interface_element } interface_element ::=3D interface_declaration interface_declaration ::=3D interface_constant_declaration |interface_wave_constant_declaration | interface_signal_declaration | interface_variable_declaration | interface_file_declaration interface_constant_declaration ::=3D [constant] identifier_list : [ in] subtype_indication [ :=3D static_express= ion ] interface_wave_constant_declaration ::=3D wave [constant] wave_constant_list : [ in ] subtype_indication [ :=3D static_expression ] wave_constant_list ::=3D=20 wave_constant_element { , wave_constant_element } wave_constant_element ::=3D=20 wave_constant |internal_wave_constant wave_constant ::=3D series_clock_number | input_clock_number | multiple_copy_number internal_wave_constant ::=3D one_hot entity_declarative_part ::=3D { entity_declarative_item } entity_declarative_item ::=3D subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | alias_wave_constant_declaration | signal_declaration |shared_variable_declaration | file_declaration | alias_declaration | attribute_declaration | attribute_specification | disconnection_specification | use_clause | group_template_declaration | group_declaration architecture_body ::=3D architecture identifier of entity_name is architecture_declarative_part begin architecture_statement_part end[ architecture ] [ architecture_simple_name ] ; architecture_declarative_part ::=3D { block_declarative_item } block_declarative_item ::=3D subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | alias_wave_constant_declaration | signal_declaration | shared_variable_declaration | file_declaration | alias_declaration | component_declaration | attribute_declaration | attribute_specification | configuration_specification | disconnection_specification | use_clause | group_template_declaration | group_declaration constant_declaration ::=3D constant identifier_list : subtype_indication [ :=3D expression ] ; alias_wave_constant_declaration ::=3D wave [ constant ] alias_wave_constant_list : subtype_indication :=3D=20 wave_constant ; alias_wave_constant_list ::=3D alias_wave_constant { , alias_wave_constant } alias_wave_constant ::=3D identifier [0070] The set of following rules is called wave constant mechanism: =E2=80=A2 There are three wave constants related to wave-pipelining techniq= ue: series_clock_number, input_clock_number and multiple_copy_number.=20 =E2=80=A2 A wave constant can only be declared in the generic_clause of the= entity definition of a WPC embodiment, plays the same role as a generic co= nstant declared in the same place does except that it has actual initial va= lue 1 under slow mode, and actual initial value equal to or greater than 1 = determined and assigned by a synthesizer under target mode, and the static = expression in an interface wave constant declaration is always ignored. =E2=80=A2 A WPC instantiation must not include corresponding association el= ement with a formal wave constant in the generic map aspect.=20 =E2=80=A2 Any wave constant declared in a WPC definition is accessible by d= esigners through an alias wave constant declaration. =E2=80=A2 An alias wave constant declaration identifies a list of alias wav= e constants which are assigned a wave constant. Each alias wave constant mu= st be linked with a WPC instantiation through a link statement and shares t= he wave constant value of the linked WPC instantiation for testing, debuggi= ng or implementing purpose. An alias wave constant plays the same role as a= normal constant declared in the same place does.=20 =E2=80=A2 A CPC may have any of its linked WPC=E2=80=99s wave constants and= output signals as its own input signal, but must have no input signals whi= ch are related to any unrelated WPC instantiation=E2=80=99s wave constants. =E2=80=A2 The internal wave constant one_hot is used internally by a synthe= sizer to optimize the implementation of a WPC and not accessible by designe= rs.=20 =E2=80=A2 A synthesizer has its discretion to determine internal wave const= ant one_hot value based on the environment and the consideration of its pro= duction technique used unless a WPC input_delay_module has its R_O output c= onnected in which case one_hot will be =E2=80=981=E2=80=99 in order to gene= rate valid R_O output signal.=20 Thank you for your reading. Weng From newsfish@newsfish Thu Aug 1 00:32:48 2024 X-Received: by 10.182.125.100 with SMTP id mp4mr25503409obb.21.1426503171890; Mon, 16 Mar 2015 03:52:51 -0700 (PDT) X-Received: by 10.140.21.113 with SMTP id 104mr901685qgk.11.1426503171771; Mon, 16 Mar 2015 03:52:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no12940477igb.0!news-out.google.com!q90ni145qgd.1!nntp.google.com!z107no1944170qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 16 Mar 2015 03:52:51 -0700 (PDT) In-Reply-To: <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:9c80:85be:2c27:3b39; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:9c80:85be:2c27:3b39 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Mon, 16 Mar 2015 10:52:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3642 On Saturday, March 14, 2015 at 1:45:11 AM UTC-4, Weng Tianxiang wrote: > Here are more contents. It shows how a complicated problem is resolved by > creative ideas. > > [0069] New keyword wave and three wave constants are introduced to resolve > the problem. In the following listing characters in bold type are new suggested > definitions based on VHDL-2002. > Do you have any data to support your contention that your solution actually solves the problem of designer productivity in implementing wave-pipeline code? Kevin From newsfish@newsfish Thu Aug 1 00:32:49 2024 X-Received: by 10.66.224.42 with SMTP id qz10mr71582980pac.0.1426616123525; Tue, 17 Mar 2015 11:15:23 -0700 (PDT) X-Received: by 10.50.49.2 with SMTP id q2mr1822ign.12.1426616123485; Tue, 17 Mar 2015 11:15:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no478095igj.0!news-out.google.com!qk8ni59857igc.0!nntp.google.com!z20no478086igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 17 Mar 2015 11:15:22 -0700 (PDT) In-Reply-To: <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Tue, 17 Mar 2015 18:15:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3643 On Monday, March 16, 2015 at 3:52:56 AM UTC-7, KJ wrote: > On Saturday, March 14, 2015 at 1:45:11 AM UTC-4, Weng Tianxiang wrote: >=20 > > Here are more contents. It shows how a complicated problem is resolved = by=20 > > creative ideas. > >=20 > =20 > > [0069] New keyword wave and three wave constants are introduced to r= esolve=20 > > the problem. In the following listing characters in bold type are new s= uggested=20 > > definitions based on VHDL-2002. > >=20 >=20 > Do you have any data to support your contention that your solution actual= ly solves the problem of designer productivity in implementing wave-pipelin= e code? >=20 > Kevin KJ, I didn't invent any method to generate correct wave pipelined circuits, wha= t I did is I invented a systematic method for all digital designers to be a= ble to write any types of wave pipelined circuits in HDL and shifted the re= sponsibility to generate such circuits from individual designers to compile= rs!!!=20 So your question is pointless. Here is a historical example: Before HDL introduction, everyone had to write logic to make 32-bit*32-bit = multiplication if he needed to do it. After HDL and multiple sign "*' introduction, everyone now can do 32*32 mul= tiplication using multiple sign "*'. What difference between my invention and multiple sign "*' introduction is = that the idea behind my method is very complex, non-obvious so that after 1= 967 first paper published on wave pipelined circuits, no one had figured ou= t how it can be done in HDL. The invention is 65 pages long, a jumbo invention according to USPTO standa= rds, and describes all rules for designers and compilers to observe to make= such things happening harmoniously without any defects. The results of my invention are: 1. Every digital designer can write wave pipelined circuits in HDL if the i= nvention is adopted by HDL. 2. Every wave pipelined circuit published publicly, implemented or non-impl= emented, ASIC or FPGA, can be implemented by any compiler without any doubt= . 3. The method to write the circuit for digital designers is both very simpl= e and comprehensive. The method will not generate any extra logic, compared= to the original method. 4. What a designer needs to do is very simple: tell compiler that this is a= wave pipelined circuit design and generate it for me, and I have tools to = check if you do a correct thing and if you cannot do it, let me know what I= should do to improve the successful rate. Please be patient to see my posting which will finally publish all related = source code for public to check if my claims are correct.=20 After that you may have more rights to comment and I will welcome any comme= nts. Weng From newsfish@newsfish Thu Aug 1 00:32:49 2024 X-Received: by 10.236.8.69 with SMTP id 45mr56522974yhq.39.1426642008035; Tue, 17 Mar 2015 18:26:48 -0700 (PDT) X-Received: by 10.140.98.7 with SMTP id n7mr1067261qge.13.1426642007994; Tue, 17 Mar 2015 18:26:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h3no3128604qgf.1!news-out.google.com!f74ni149qge.0!nntp.google.com!h3no3128603qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 17 Mar 2015 18:26:47 -0700 (PDT) In-Reply-To: <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:7510:8352:f8d2:dfbc; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:7510:8352:f8d2:dfbc References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Wed, 18 Mar 2015 01:26:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5436 X-Received-Body-CRC: 1854744208 Xref: news.eternal-september.org comp.lang.vhdl:3644 On Tuesday, March 17, 2015 at 2:15:26 PM UTC-4, Weng Tianxiang wrote: >=20 > KJ, > I didn't invent any method to generate correct wave pipelined circuits,= =20 I never said or implied that you did > what I did is I invented a systematic method for all digital designers to= be=20 > able to write any types of wave pipelined circuits in HDL and shifted the= =20 > responsibility to generate such circuits from individual designers to > compilers!!!=20 >=20 And my question was simply: "Do you have any data to support your contentio= n that your solution actually solves the problem of designer productivity i= n implementing wave-pipeline code?"=20 >=20 > So your question is pointless. >=20 Sure...if you have nothing to support your position, try to blame it on the= question. So I'll have to assume at this point that this you have nothing= to back up your claims, just like you had nothing to backup your claims wi= th 'orif' which I showed to be incorrect. >=20 > What difference between my invention and multiple sign "*' introduction i= s=20 > that the idea behind my method is very complex, non-obvious so that after= =20 > 1967 first paper published on wave pipelined circuits, no one had figured= out=20 > how it can be done in HDL. >=20 But does your method have any practical utility? You say it does, and mayb= e you're right, but you haven't demonstrated that with any of your posting = here. To get a patent you may not need to show this, but since you're post= ing here to an open forum you should consider that without practical utilit= y what you're posting isn't interesting reading. =20 Maybe you haven't gotten to that part of showing the utility even after all= of the postings in this newsgroup, or maybe it's because this idea is like= your idea for 'orif' which has little or no real utility as I demonstrated= on one of the sidebars of this thread. > The invention is 65 pages long, a jumbo invention according to USPTO=20 > standards, and describes all rules for designers and compilers to observe= to=20 > make such things happening harmoniously without any defects. >=20 > The results of my invention are: > 1. Every digital designer can write wave pipelined circuits in HDL if the= =20 > invention is adopted by HDL. >=20 Without any data to backup what you say...it becomes easy to claim most any= thing > 2. Every wave pipelined circuit published publicly, implemented or non- > implemented, ASIC or FPGA, can be implemented by any compiler without any= =20 > doubt. >=20 Can you provide evidence of this? > 3. The method to write the circuit for digital designers is both very sim= ple=20 > and comprehensive. The method will not generate any extra logic, compared= to=20 > the original method. >=20 You're contradicting yourself. A few lines up you said "no one had figured= out how it can be done in HDL" and yet now you say that there is some "ori= ginal method". And again...can you demonstrate it or can you only claim th= at it must be? > 4. What a designer needs to do is very simple: tell compiler that this is= a=20 > wave pipelined circuit design and generate it for me, and I have tools to= =20 > check if you do a correct thing and if you cannot do it, let me know what= I=20 > should do to improve the successful rate. >=20 What if I tell it that it is a wave pipelined circuit when in fact it is no= t? > Please be patient to see my posting which will finally publish all relate= d=20 > source code for public to check if my claims are correct.=20 >=20 OK > After that you may have more rights to comment and I will welcome any=20 > comments. I have the same 'rights' to post and comment here as you do. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:49 2024 X-Received: by 10.66.157.194 with SMTP id wo2mr77352548pab.17.1426714288191; Wed, 18 Mar 2015 14:31:28 -0700 (PDT) X-Received: by 10.50.40.9 with SMTP id t9mr156176igk.7.1426714288144; Wed, 18 Mar 2015 14:31:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no1315655igj.0!news-out.google.com!qk8ni61499igc.0!nntp.google.com!z20no1315651igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Mar 2015 14:31:27 -0700 (PDT) In-Reply-To: <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <52b3490c-3579-4716-aa9f-c54001dc1137@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: diogratia@gmail.com Injection-Date: Wed, 18 Mar 2015 21:31:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3645 On Wednesday, March 18, 2015 at 2:26:49 PM UTC+13, KJ wrote: > On Tuesday, March 17, 2015 at 2:15:26 PM UTC-4, Weng Tianxiang wrote: > > After that you may have more rights to comment and I will welcome any > > comments. > > I have the same 'rights' to post and comment here as you do. > > Kevin Jennings I'd echo Kevin's sentiments. If you want to control the story do your own blog or website. In the mean time your comportment in this thread doesn't portray you nor your questionable-yet-not-to-be-questioned ideas in a particularly good light. From newsfish@newsfish Thu Aug 1 00:32:49 2024 X-Received: by 10.236.220.74 with SMTP id n70mr89581169yhp.40.1426862976166; Fri, 20 Mar 2015 07:49:36 -0700 (PDT) X-Received: by 10.50.85.17 with SMTP id d17mr66214igz.7.1426862976139; Fri, 20 Mar 2015 07:49:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h3no3707624qgf.1!news-out.google.com!db6ni58136igc.0!nntp.google.com!z20no2156043igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2015 07:49:35 -0700 (PDT) In-Reply-To: <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Fri, 20 Mar 2015 14:49:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 7160 X-Received-Body-CRC: 424211717 Xref: news.eternal-september.org comp.lang.vhdl:3646 On Tuesday, March 17, 2015 at 6:26:49 PM UTC-7, KJ wrote: > On Tuesday, March 17, 2015 at 2:15:26 PM UTC-4, Weng Tianxiang wrote: > >=20 > > KJ, > > I didn't invent any method to generate correct wave pipelined circuits,= =20 >=20 > I never said or implied that you did >=20 > > what I did is I invented a systematic method for all digital designers = to be=20 > > able to write any types of wave pipelined circuits in HDL and shifted t= he=20 > > responsibility to generate such circuits from individual designers to > > compilers!!!=20 > >=20 >=20 > And my question was simply: "Do you have any data to support your content= ion that your solution actually solves the problem of designer productivity= in implementing wave-pipeline code?"=20 >=20 > >=20 > > So your question is pointless. > >=20 > Sure...if you have nothing to support your position, try to blame it on t= he question. So I'll have to assume at this point that this you have nothi= ng to back up your claims, just like you had nothing to backup your claims = with 'orif' which I showed to be incorrect. >=20 > > >=20 > > What difference between my invention and multiple sign "*' introduction= is=20 > > that the idea behind my method is very complex, non-obvious so that aft= er=20 > > 1967 first paper published on wave pipelined circuits, no one had figur= ed out=20 > > how it can be done in HDL. > >=20 >=20 > But does your method have any practical utility? You say it does, and ma= ybe you're right, but you haven't demonstrated that with any of your postin= g here. To get a patent you may not need to show this, but since you're po= sting here to an open forum you should consider that without practical util= ity what you're posting isn't interesting reading. > =20 > Maybe you haven't gotten to that part of showing the utility even after a= ll of the postings in this newsgroup, or maybe it's because this idea is li= ke your idea for 'orif' which has little or no real utility as I demonstrat= ed on one of the sidebars of this thread. >=20 > > The invention is 65 pages long, a jumbo invention according to USPTO=20 > > standards, and describes all rules for designers and compilers to obser= ve to=20 > > make such things happening harmoniously without any defects. > >=20 > > The results of my invention are: > > 1. Every digital designer can write wave pipelined circuits in HDL if t= he=20 > > invention is adopted by HDL. > >=20 >=20 > Without any data to backup what you say...it becomes easy to claim most a= nything >=20 > > 2. Every wave pipelined circuit published publicly, implemented or non- > > implemented, ASIC or FPGA, can be implemented by any compiler without a= ny=20 > > doubt. > >=20 >=20 > Can you provide evidence of this? >=20 > > 3. The method to write the circuit for digital designers is both very s= imple=20 > > and comprehensive. The method will not generate any extra logic, compar= ed to=20 > > the original method. > >=20 >=20 > You're contradicting yourself. A few lines up you said "no one had figur= ed out how it can be done in HDL" and yet now you say that there is some "o= riginal method". And again...can you demonstrate it or can you only claim = that it must be? >=20 > > 4. What a designer needs to do is very simple: tell compiler that this = is a=20 > > wave pipelined circuit design and generate it for me, and I have tools = to=20 > > check if you do a correct thing and if you cannot do it, let me know wh= at I=20 > > should do to improve the successful rate. > >=20 >=20 > What if I tell it that it is a wave pipelined circuit when in fact it is = not? >=20 > > Please be patient to see my posting which will finally publish all rela= ted=20 > > source code for public to check if my claims are correct.=20 > >=20 >=20 > OK >=20 > > After that you may have more rights to comment and I will welcome any= =20 > > comments. >=20 > I have the same 'rights' to post and comment here as you do. >=20 > Kevin Jennings KJ, "Critical questions are inventions' mother." Einstein Thank you for your critical comments.=20 The reason is that your comments are driving me to file another patent appl= ication on the same wave-pipelined circuits theory to fully support my theo= ry and meet your curiosity:=20 1. It will provide an example implementation used for a 4-core processor en= vironment with source code included. The included source code is not necess= ary, but will certainly accelerate the process of understanding, distributi= ng, helping and correct assessing my patent applications. 2. It will fully describe using the implementable example why my invented m= ethod really resolves the 50-year pending problem and makes it successful w= ithout failure with sharp-point targeting and answering all questionable-ye= t-not-to-be-questioned ideas. I will continue publishing all remaining part of my patent application when= I am available, including all related source code of 52,089 bytes, about 1= ,100 lines, for public verification, because that invention is targeted and= assumed to be incorporated into all HDL language, and public has the right= s to know it. If any readers find any questionable-yet-not-to-be-questioned ideas while r= eading my application text, you may immediately ask me the questions after = my posting and I will immediately answer your doubts without any delay. Weng From newsfish@newsfish Thu Aug 1 00:32:50 2024 X-Received: by 10.182.248.227 with SMTP id yp3mr93320030obc.22.1426867957839; Fri, 20 Mar 2015 09:12:37 -0700 (PDT) X-Received: by 10.50.129.98 with SMTP id nv2mr80409igb.1.1426867957814; Fri, 20 Mar 2015 09:12:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z20no1543177igj.0!news-out.google.com!db6ni58136igc.0!nntp.google.com!z20no2193647igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2015 09:12:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.255.147.121; posting-account=FbGAbQoAAADo4S2QpylKfP0Gt2DSb2ry NNTP-Posting-Host: 103.255.147.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Need: DevOps Engineer in EI Segundo, CA From: latha.karnti@gmail.com Injection-Date: Fri, 20 Mar 2015 16:12:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3371 X-Received-Body-CRC: 2892403991 Xref: news.eternal-september.org comp.lang.vhdl:3647 Hi, Please go through below the requirement if you're comfortable please forward his/her resume along with contact number & email-id to panand@sageitinc.net Position: DevOps Engineer Location: EI Segundo, CA Duration: 12 Months Required Qualifications: 5-7 years DevOps, IT, and/or software engineering work experience Experienced in the installation, configuration and administration of Red Hat Enterprise and its derivatives Rich DevOps skills across SCM, Static Code Analyzer, Build and Release, Continuous Integration tools and frameworks such as, SVN, GIT, ANT, MVN, Sonar etc Deep understanding and practical working knowledge of Puppet, Chef, Jenkins Ability to use a wide variety of open source technologies and cloud services (particularly Amazon Web Services and OpenStack) Working understanding of code and script (Bash, Python, Perl and/or Ruby) Knowledge of IP networking, VPN's, DNS, load balancing and firewalling Familiar with implementing Continuous Integration, Delivery and Deployment practices Experience with automated testing tools Familiarity with some of the Big Data tools like Hadoop, Splunk Experience with relational & NoSQL data stores, such as MongoDB, CouchDB etc Excellent verbal and written communication skills, with the ability to work effectively across internal and external organizations Bachelor's degree in computer science or related field or equivalent experience DevOps engineer responsibilities/activities : Automating software deployment and configuration management Release (with tools such as jenkins, travis, teamcity) Configuration management and infrastructure provisioning (with tools such as puppet, chef, ansible, cfengine) Orchestration (with tools such as zookeeper, noah, mesos) Revision control source code repositories (such as Git, SVN, Perforce) Developing and supporting deployment and rollback tools and processes Monitoring (with tools such as Nagios, Incinga, SiteScope) Virtualization and containerization (with tools such as AWS, OpenStack, vagrant, docker) Participate in capacity planning, provisioning and scaling of the application infrastructure Ability to develop High-Level Design interaction diagrams, system functionality changes, data model, data flow, high-level interface specifications Thanks & Regards, Lalitha.K ksivalalitha@sageitinc.net panand@sageitinc.net From newsfish@newsfish Thu Aug 1 00:32:50 2024 X-Received: by 10.182.246.37 with SMTP id xt5mr89161034obc.25.1426879011175; Fri, 20 Mar 2015 12:16:51 -0700 (PDT) X-Received: by 10.50.66.141 with SMTP id f13mr386447igt.17.1426879011124; Fri, 20 Mar 2015 12:16:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!z20no2276746igj.0!news-out.google.com!qk8ni62932igc.0!nntp.google.com!z20no1607034igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2015 12:16:50 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.255.147.121; posting-account=FbGAbQoAAADo4S2QpylKfP0Gt2DSb2ry NNTP-Posting-Host: 103.255.147.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e143f7e-38f5-4799-88c8-dc1735460274@googlegroups.com> Subject: AWS Administrator - Lexington, Kentucky - 12 Months From: latha.karnti@gmail.com Injection-Date: Fri, 20 Mar 2015 19:16:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3648 Hi , This is Lalitha from SAGE IT INC. Hope you are doing great. Please send me your updated resume if you're interested for this position. AWS Administrator Lexington, Kentucky 6 to 12 Months Client : Wipro / Lexmark Job Description: * Experience: 8-10 yrs * End to end Amazon Web Service knowledge & experience * Must have experience as AWS Admin * Must Have skills - AWS (VPC, EC2, Redshift, RDS, S3, SWF, SQS), Python/Java * Good to have Skills - Hadoop/EMR Thanks Lalitha Reddy K ksivalalitha@sageitinc.net From newsfish@newsfish Thu Aug 1 00:32:50 2024 X-Received: by 10.50.43.229 with SMTP id z5mr5951436igl.3.1426885536199; Fri, 20 Mar 2015 14:05:36 -0700 (PDT) X-Received: by 10.50.1.113 with SMTP id 17mr401902igl.8.1426885536182; Fri, 20 Mar 2015 14:05:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z20no1636505igj.0!news-out.google.com!db6ni58136igc.0!nntp.google.com!z20no2317749igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2015 14:05:35 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.255.147.121; posting-account=FbGAbQoAAADo4S2QpylKfP0Gt2DSb2ry NNTP-Posting-Host: 103.255.147.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Need: Unix Admin in EI Segundo, CA From: latha.karnti@gmail.com Injection-Date: Fri, 20 Mar 2015 21:05:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 39 Xref: news.eternal-september.org comp.lang.vhdl:3649 Hi, Please go through below the requirement if you're comfortable please forward his/her resume along with contact number & email-id to panand@sageitinc.net Position: Unix Admin Location: EI Segundo,CA Duration: 6+ Months Responsibilities will include: Analysis of the organization's business needs with the capability to translate LoB requirements for automation use cases into design and implementation plans Engineering and architectural development of robust Operating system, middleware and application configuration solution. Proactive review of environment to suggest/develop new configuration management policies Qualifications: Experience in medium to large enterprise or service provider of a distributed platform Experience implementing highly automated data driven automation. Minimum of 6+ years' experience of Redhat in a large, mission critical global production enterprise(5000+ servers). Minimum of 2+ years professional experience working with CFEngine or equivalent (Puppet, Chef) Experience of one or both of Solaris or AIX Strong understanding of Unix Security and LDAP Understanding of security best practices for multi-tiered operating systems Advanced scripting abilities with Shell and Perl Programming development skills with C, C++ Ability to adapt to a dynamic work environment and must be able to multi-task and work with minimal guidance Effective written and verbal communication skills Results driven, ensuring short-term goals are achieved while supporting long-term initiatives with an appropriate sense of urgency Desired Skills/Product Skills: Configuration Management: CFEngine 3, Chef or Puppet Operating System: Redhat 5/6/7, AIX 5/6/7 Solaris 10 Experience in database technologies Experience in scripting and automation such as: PERL, Shell (Bourne, Korn, C-Shell), JAVA, JavaScript, HTML and PHP Thanks & Regards, Anand Executive-Talent Acquisition Direct: 972-996-0650 Ext: 339 panand@sageitinc.net www.sageitinc.com From newsfish@newsfish Thu Aug 1 00:32:51 2024 X-Received: by 10.68.209.164 with SMTP id mn4mr5185222pbc.8.1426976610715; Sat, 21 Mar 2015 15:23:30 -0700 (PDT) X-Received: by 10.50.110.101 with SMTP id hz5mr56046igb.6.1426976610658; Sat, 21 Mar 2015 15:23:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!z20no2855641igj.0!news-out.google.com!qk8ni62932igc.0!nntp.google.com!z20no1972833igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 21 Mar 2015 15:23:29 -0700 (PDT) In-Reply-To: <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 21 Mar 2015 22:23:30 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3650 On Friday, March 13, 2015 at 10:45:11 PM UTC-7, Weng Tianxiang wrote: > On Monday, March 9, 2015 at 3:02:48 AM UTC-7, Weng Tianxiang wrote: > > On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote: > > > On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wr= ote: > > > > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang w= rote: > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > >=20 > > > > > I have filed a provisional patent application: "Systematic method= of coding wave pipelined circuits in HDL". If it is proved correct, the pa= tent will introduce 1 keyword, 3 permanent constants, 1 concurrent statemen= t and four source code modules for a new library in HDL and thoroughly reso= lve a pending problem so that every digital designer can code wave-pipeline= d circuits in HDL. > > > > >=20 > > > > > Here is the abstract of the invention: > > > > >=20 > > > > > The present invention classifies all critical paths into two = basic types: a series critical path and a feedback critical path, and divid= es each of wave-pipelined circuits into two components: a static logic part= , called critical path component (CPC), and a dynamic logic part, formalize= d into four wave-pipelining components (WPC) shared by all wave-pipelined c= ircuits. Each wave-pipelining ready code in HDL comprises two components: a= WPC instantiation and a CPC instantiation wire-connected and linked by a n= ew link statement. Each WPC has new wave constants which play the same role= as generic constants do, but whose initial values are determined and assig= ned by a synthesizer after code analysis, so designers can use after-synthe= sization information in their code before synthesization for wave-pipelinin= g technology. The responsibility of analyzing and manipulating wave-pipelin= ing ready code, generating and implementing wave-pipelined circuits on a de= sign-wide or chip-wide scale in HDL is shifted from designers to synthesize= rs. > > > > >=20 > > > > > Anyone who are interested in its content is welcome to send a ema= il request to the following email address: wtx wtx @ gmail . com with title= "Systematic" and he will receive the full documents: one specification, 9 = drawings and one text file in VHDL. > > > > >=20 > > > > > If one reviews the files and feels that it would be a good thing = to recommend the application to his company to buy it, the first person to = do it after his recommended company does so will receive $10,000 commission= fee. > > > > >=20 > > > > > Thank you. > > > > >=20 > > > > > Weng > > > >=20 > > > > Hi, > > > > I want to add some introductions to what the wave-pipelined circuit= s are and their status. > > > >=20 > > > > [0003] A synchronous digital system contains a lot of registers.= Valid data flow through successive registers from system input registers t= o system output registers. All data flows are synchronous with triggering e= dges of a chip clock. For example, data flow from registers A to registers = B, from registers B to registers C and so on in a successive order on the s= ame clock cycle. > > > > [0004] A path in a synchronous digital system is a route between= any neighboring registers connected by combinational logic. If the target = running frequency for a digital design is predetermined, the upper limit of= propagating time for any paths is determined and has the inverse value of = the target running frequency. A path is called a critical path if the time = signals take to propagate through it is beyond the predetermined propagatin= g time, and the time is called the path's critical time. If there are any c= ritical paths, digital designers must spend time reducing all critical time= s by all means and eliminating all critical paths to meet the target runnin= g frequency. > > > > [0005] Wave-pipelining is a technology which completes an operat= ion that needs several clock cycles to propagate without intermediate regis= ters and with input data acceptable on every clock cycle. For example, in a= conventional pipelining operation, data flow from registers A to registers= D through registers B and C to divide the critical path time into multiple= smaller intervals to meet the critical time: A to B to C to D; with wave-p= ipelining, data flow through registers A and D without intermediate registe= rs B and C. Absolutely, wave-pipelining will reduce logic resource usage an= d is superior to the conventional pipelining technology if it can be used. > > > >=20 > > > > Here are the most important inequalities involving wave-pipelining = from paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Bu= rleson et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6,= no. 3, pp. 464-474, Sep. 1998. > > > >=20 > > > > [0018] Currently many memory chip manufacturers successfully use= wave-pipelining in their memory chip products with higher rate outputs, re= duced power consumption and logic resources; and a few scientists use FPGA = chips as a base to show some circuits can be done with wave-pipelining in i= solated environments. Their works prove that the wave-pipelining is a very = powerful tool to reduce power consumption and logic resources. Now there ar= e two major existing obstacles preventing any ordinary digital designers fr= om using the wave-pipelining in HDL: > > > > * The software algorithms making wave-pipelining successful, like W= ong and Klass algorithms and others, have already been developed and mature= d, but ordinary digital designers have no means or resources to access to t= he technology, because there are no international HDL standards on how synt= hesizer manufacturers incorporate those capabilities into their products. > > > > * HDL needs the capabilities for digital designers to write wave-pi= pelining ready code for any number of critical paths on a design-wide or ch= ip-wide scale instead of in an isolated environment and the written code ca= n be identified, synthesized and used to generate wave-pipelined circuits b= y any synthesizer in ASIC or FPGA, and they should be part of HDL standards= .=20 > > > > [0019] The target of the present invention is: > > > > * Invent a wave-pipelining coding system as new part of HDL standar= ds for designers to write wave-pipelining ready code which can be identifie= d, synthesized and used to generate wave-pipelined circuits by any synthesi= zer in ASIC or FPGA. > > > > * Make wave-pipelining ready code written based on the coding syste= m working with no extra logic generated, compared with independently writte= n wave-pipelined circuits, and with no code changes when switching from non= -wave-pipelined mode to wave-pipelined mode or vice verse if all of wave-pi= pelining ready code meet wave-pipelining requirements.=20 > > > > * Shift burdens of analyzing and manipulating wave-pipelining ready= code, generating and implementing wave-pipelined circuits on a design-wide= or chip-wide scale in HDL from individual designers to synthesizer manufac= turers. > > > > [0020] If the coding system becomes new part of HDL standards al= l synthesizer manufactures will automatically be forced to implement all we= ll-known wave-pipelining algorithms and techniques within their products, a= competition will start for better implementations, making wave-pipelining = technique available to every digital designer in HDL. > > > >=20 > > > > Weng > > >=20 > > > Here I add some contents of the invention: > > >=20 > > > Main idea behind the present invention > > >=20 > > > [0057] The most difficult part coding all types of wave-pipelined = circuits on a design-wide scale in HDL is that a wave-pipelined circuit cod= e always comprises two logic parts:=20 > > > * A static logic part: it doesn't change if the number of series cloc= k cycles through the circuit changes and is unique for each of wave-pipelin= ed circuits. > > > * A dynamic logic part: it does change if the number of series clock = cycles through the circuit changes and is the same for one of groups of wav= e-pipelined circuits. > > > [0058] Every wave-pipelined circuit has its own change rules and t= hose changes are unknown to designers when they are writing code and will b= e known to a synthesizer only after it has analyzed the circuit. > > > [0059] The present invention classifies all critical paths into tw= o basic types: a series critical path and a feedback critical path, and div= ides each of wave-pipelined circuits into two components: one is static log= ic part and called critical path component (CPC); another is dynamic logic = part and formalized into four wave-pipelining components (WPC) shared by al= l wave-pipelined circuits. Under the present invention each of standard wav= e-pipelining ready code in HDL comprises two components: a WPC instantiatio= n and a CPC instantiation which are wire-connected and linked by a new conc= urrent link statement. Each of four WPC embodiments has a group of new type= wave constant, which plays the same role as a generic constant does, but w= hose initial value is determined and assigned by a synthesizer after it has= analyzed the linked CPC component under slow mode and target mode, respect= ively, so designers can use after-synthesization information in their code = before synthesization in HDL for wave-pipelining technology. Following the = instructions of the present invention creates a situation that digital desi= gners can write wave-pipelining ready code in HDL and the responsibility of= analyzing and manipulating wave-pipelining ready code, generating and impl= ementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL= is shifted from individual designers to synthesizer manufacturers. > > >=20 > > > How the method works > > >=20 > > > [0060] The systematic method of coding wave-pipelined circuits in = HDL comprises following ten parts: > > > 1. Define five signals, one counter, one switch and one table that wi= ll be used when generating wave-pipelined circuits on a design-wide or chip= -wide scale in HDL. > > > 2. Define the interfaces of a CPC each of which encapsulates a critic= al path's static logic part. > > > 3. Define and implement four WPC embodiments in HDL each of which is = a critical path's dynamic logic part: a series_module, an input_delay_modul= e, a multiple_copy_module1 and a multiple_copy_module2. > > > 4. Define one new keyword wave and three new wave constants which pro= vide a means to dynamically transfer after-synthesization information to de= signers' code before synthesization. > > > 5. Define the methods of determining and searching for wave constant = values of a known WPC instantiation under slow mode and target mode, respec= tively. > > > 6. Define three versions of a concurrent link statement: link1, link2= and link3, and rules on how they are used. > > > 7. Define the pairing rules between a WPC and a CPC. > > > 8. Define how a digital designer prepares wave-pipelining ready code = systematically. > > > 9. Shift the responsibility of analyzing and manipulating wave-pipeli= ning ready code, generating and implementing wave-pipelined circuits on a d= esign-wide or chip-wide scale in HDL from individual designers to synthesiz= er manufacturers. > > > 10. Define how four WPC embodiments are simulated and debugged under = any of current versions of a synthesizer in HDL. > > > [0061] It is fair to put the burden of successfully generating wav= e-pipelined circuits based on wave-pipelining ready code squarely on synthe= sizer manufacturers' shoulder if all necessary information is passed to a s= ynthesizer. For example, with tens of papers claiming that successful wave-= pipelined circuits are implemented in FPGA chips in an isolated environment= , it is the responsibility of FPGA synthesizers to be capable of generating= those wave-pipelined circuits in a design-wide environment without designe= rs' further involvements, a process similar for them to the task of generat= ing a circuit with the highest running frequency and minimum used resources= if possible for any normal digital design code. > > >=20 > > > Thank you for your reading. > >=20 > > Here are more contents. > >=20 > > Definitions of wave-pipelining component and critical path component > >=20 > > [0062] A design component is called a critical path component (CPC) = if it is an entity (a term in VHDL-2002) in HDL and encapsulates the static= logic part of a critical path which is to be wave-pipelined circuit. There= are two types of CPCs:=20 > > =E2=80=A2 A series CPC: it encapsulates a series critical path=E2=80=99= s static logic part. > > =E2=80=A2 A feedback CPC: it encapsulates a feedback critical path=E2= =80=99s static logic part.=20 > >=20 > > [0063] A CPC also refers to a CPC instantiation when it will not be = misunderstood. The required interfaces of both a series CPC and a feedback = CPC are always the same. The combinational logic of a CPC may be located wi= thin or outside of the component and there is no limit on it.=20 > >=20 > > [0064] A design component is called a wave-pipelining component (WPC= ) if it is an entity in HDL, provided by HDL in a new wave-pipelining syste= m library and used to generate a critical path=E2=80=99s dynamic logic part= , i.e., to generate output data valid signal and write enable signals to th= e input and output registers of a critical path.=20 > >=20 > > [0065] There are three types of WPC:=20 > > =E2=80=A2 A series_module is used to connect to a series CPC with input= data acceptable on every clock cycle. > > =E2=80=A2 An input_delay_module is used to connect to a series or feedb= ack CPC with input data acceptable on every one or more clock cycle. > > =E2=80=A2 A multiple_copy_module1 or a multiple_copy_module2 is used to= connect to multiple copied series or feedback CPCs with input data accepta= ble on every clock cycle. > >=20 > > [0066] A WPC also refers to a WPC instantiation when it will not be = misunderstood. Later multiple_copy_module refers to either of multiple_copy= _module1 and multiple_copy_module2. > >=20 > > A synthesizer=E2=80=99s new signals, switch and table > >=20 > > [0067] A synthesizer that is able of handling wave-pipelining needs = six signals, one switch, one table and the table=E2=80=99s row index to hel= p finish its job: > > =E2=80=A2 A floating signal target_running_frequency: it is set up by a= designer and the target running frequency under which a design finally run= s. > > =E2=80=A2 A bit signal generate_circuit: it is set up by a designer and= its initial value is deasserted. A synthesizer will generate related circu= it files for a design under slow mode for slow mode hardware testing if gen= erate_circuit is asserted and no errors are detected after a synthesization= , or will not otherwise. A synthesizer will always generate related circuit= files for a design under target mode for target mode hardware testing if n= o errors are detected after a synthesization. > > =E2=80=A2 A bit signal feedback_bit: it is set up by a synthesizer and = its initial value is deasserted. Assert the bit if a CPC is being analyzed = and determined to have feedbacks, and deassert it after the analysis is fin= ished. > > =E2=80=A2 A bit signal keep_target_circuit: it is set up by a designer = and its initial value is deasserted. Assert the bit if a designer wants to = keep all CPC new circuits automatically and successfully modified by a synt= hesizer under target mode unchanged under slow mode when he is switching to= synthesize the same design from under target mode to under slow mode and t= he related code doesn=E2=80=99t change, or deassert it otherwise. The bit p= rovides a method for a designer to check if the new automatically and succe= ssfully modified circuits by a synthesizer don=E2=80=99t change basic logic= .=20 > > =E2=80=A2 An integer signal parent_series_clock_number: it is set up by= a synthesizer and Its initial value is zero. When the instantiation of a W= PC delay_input_module or multiple_copy_module is being analyzed and execute= d its series_clock_number value is stored in parent_series_clock_number, an= d it is cleared to zero when the execution is finished. > > =E2=80=A2 An integer signal start_number: it is set up by a synthesizer= and used when the synthesizer determines that a CPC cannot meet the wave-p= ipelining requirements with input data acceptable on every clock cycle and = the CPC is linked with a WPC input_delay_module or multiple_copy_module. Th= e start_number is made equal to 2 if a WPC multiple_copy_module is linked o= r to feedback_clock_number if a WPC input_delay_module is linked as the sta= rting value of wave constant input_clock_number or multiple_copy_number. > > =E2=80=A2 A bit switch running_mode: it is set up by a designer and it = has two valid values with slow mode being its initial value: > > o Slow mode: under slow mode a digital designer designs his code, a des= ign is synthesized, simulated, and hardware tested under the following assu= mptions: > > =EF=82=A7 Signals take one clock cycle to propagate through any of CPCs= under slow running frequency. > > =EF=82=A7 Any of CPCs has input data acceptable on every clock cycle. > > =EF=82=A7 No multiple copied CPCs are generated. > > o Target mode: under target mode a design is synthesized, simulated, ha= rdware tested and finally runs under predetermined target running frequency= , and its implementation is determined and generated by a synthesizer under= the following assumptions: > > =EF=82=A7 Signals take one or more clock cycle to propagate through any= of CPCs as designed. > > =EF=82=A7 Each of CPCs has input data acceptable on every one or more c= lock cycle as wave-pipelining ready code indicates and it is necessary. > > =EF=82=A7 Multiple copied CPCs are generated as wave-pipelining ready c= ode indicates and it is necessary. > > =E2=80=A2 A wave constant signal table: it is generated and manipulated= by a synthesizer and stores information about each linked pair of a CPC an= d a WPC; all wave constant values and alias wave constant values can be acc= essed from the table. > > =E2=80=A2 An integer row_index to the wave constant signal table: it is= set up by a synthesizer and its initial value is 1. It is used as a row in= dex for a new link statement in the wave constant signal table and will be = increased by 1 after a synthesizer finishes the filling of the row during t= he source code scanning.=20 > >=20 > > Thank you for your reading. > >=20 > > Weng >=20 > Here are more contents. It shows how a complicated problem is resolved by= creative ideas. >=20 >=20 > New keyword wave and wave constant in HDL >=20 > [0068] When writing wave-pipelining code, digital designers don=E2=80= =99t know how many clock cycles signals need to propagate through a critica= l path, and to finish their jobs, it may take several working cycles for th= em manually to adjust their code to make a wave-pipelined circuit working. = This method is not feasible on a design-wide or chip-wide scale, because a = design may have 100 or more critical paths to be wave-pipelined circuits an= d there is no guarantee for designers to perfectly remember which is finish= ed and which is not, and most importantly, synthesizers are left aside of t= he business of wave-pipelining, giving no help at all. One of obstacles usi= ng wave-pipelining in HDL is how to establish a communication channel betwe= en a synthesizer and digital designers to provide the following essential f= unctions: >=20 > =E2=80=A2 How a designer can use after-synthesization information to writ= e code for wave-pipelined circuits before they have been synthesized in HDL= for wave-pipelining technology. This function is not necessary for success= fully generating a wave-pipelined circuit, but beneficial to implement a co= mplex one. >=20 > =E2=80=A2 If all pieces of wave-pipelining ready code are written, a desi= gn has passed simulations and/or hardware testing under slow mode perfectly= , and a synthesizer certifies that all wave-pipelining requirements are met= with input data acceptable on every one or more clock cycle and no errors = are detected after a synthesization, then correct full design circuits can = be generated under target mode and work as designed with no code change dur= ing the switching from slow mode to target mode or vice verse on a design-w= ide or chip-wide scale. This function is critical and essential for succes= sfully generating all wave-pipelined circuits on a design-wide or chip-wide= scale in HDL. >=20 > [0069] New keyword wave and three wave constants are introduced to res= olve the problem. In the following listing characters in bold type are new = suggested definitions based on VHDL-2002. >=20 > entity_declaration ::=3D=20 > entity identifier is > entity_header > entity_declarative_part > [begin > entity_statement_part ] > end [ entity ] [ entity_simple_name ] ; >=20 > entity_header ::=3D > [formal_generic_clause ] > [formal_port_clause ] >=20 > generic_clause ::=3D generic ( generic_list ) ; > generic_list ::=3D generic_interface_list > interface_list ::=3D interface_element { ; interface_element } > interface_element ::=3D interface_declaration >=20 > interface_declaration ::=3D > interface_constant_declaration > |interface_wave_constant_declaration > | interface_signal_declaration > | interface_variable_declaration > | interface_file_declaration >=20 > interface_constant_declaration ::=3D > [constant] identifier_list : [ in] subtype_indication [ :=3D static_expre= ssion ] >=20 > interface_wave_constant_declaration ::=3D > wave [constant] wave_constant_list : [ in ] subtype_indication > [ :=3D static_expression ] >=20 > wave_constant_list ::=3D=20 > wave_constant_element { , wave_constant_element } >=20 > wave_constant_element ::=3D=20 > wave_constant > |internal_wave_constant >=20 > wave_constant ::=3D > series_clock_number > | input_clock_number > | multiple_copy_number >=20 > internal_wave_constant ::=3D one_hot >=20 > entity_declarative_part ::=3D > { entity_declarative_item } >=20 > entity_declarative_item ::=3D > subprogram_declaration > | subprogram_body > | type_declaration > | subtype_declaration > | constant_declaration > | alias_wave_constant_declaration > | signal_declaration > |shared_variable_declaration > | file_declaration > | alias_declaration > | attribute_declaration > | attribute_specification > | disconnection_specification > | use_clause > | group_template_declaration > | group_declaration >=20 > architecture_body ::=3D > architecture identifier of entity_name is > architecture_declarative_part > begin > architecture_statement_part > end[ architecture ] [ architecture_simple_name ] ; >=20 > architecture_declarative_part ::=3D > { block_declarative_item } >=20 > block_declarative_item ::=3D > subprogram_declaration > | subprogram_body > | type_declaration > | subtype_declaration > | constant_declaration > | alias_wave_constant_declaration > | signal_declaration > | shared_variable_declaration > | file_declaration > | alias_declaration > | component_declaration > | attribute_declaration > | attribute_specification > | configuration_specification > | disconnection_specification > | use_clause > | group_template_declaration > | group_declaration >=20 > constant_declaration ::=3D > constant identifier_list : subtype_indication [ :=3D expression ] ; >=20 > alias_wave_constant_declaration ::=3D > wave [ constant ] alias_wave_constant_list : subtype_indication :=3D=20 > wave_constant ; >=20 > alias_wave_constant_list ::=3D > alias_wave_constant { , alias_wave_constant } >=20 > alias_wave_constant ::=3D identifier >=20 > [0070] The set of following rules is called wave constant mechanism: >=20 > =E2=80=A2 There are three wave constants related to wave-pipelining techn= ique: series_clock_number, input_clock_number and multiple_copy_number.=20 >=20 > =E2=80=A2 A wave constant can only be declared in the generic_clause of t= he entity definition of a WPC embodiment, plays the same role as a generic = constant declared in the same place does except that it has actual initial = value 1 under slow mode, and actual initial value equal to or greater than = 1 determined and assigned by a synthesizer under target mode, and the stati= c expression in an interface wave constant declaration is always ignored. >=20 > =E2=80=A2 A WPC instantiation must not include corresponding association = element with a formal wave constant in the generic map aspect.=20 >=20 > =E2=80=A2 Any wave constant declared in a WPC definition is accessible by= designers through an alias wave constant declaration. >=20 > =E2=80=A2 An alias wave constant declaration identifies a list of alias w= ave constants which are assigned a wave constant. Each alias wave constant = must be linked with a WPC instantiation through a link statement and shares= the wave constant value of the linked WPC instantiation for testing, debug= ging or implementing purpose. An alias wave constant plays the same role as= a normal constant declared in the same place does.=20 >=20 > =E2=80=A2 A CPC may have any of its linked WPC=E2=80=99s wave constants a= nd output signals as its own input signal, but must have no input signals w= hich are related to any unrelated WPC instantiation=E2=80=99s wave constant= s. >=20 > =E2=80=A2 The internal wave constant one_hot is used internally by a synt= hesizer to optimize the implementation of a WPC and not accessible by desig= ners.=20 >=20 > =E2=80=A2 A synthesizer has its discretion to determine internal wave con= stant one_hot value based on the environment and the consideration of its p= roduction technique used unless a WPC input_delay_module has its R_O output= connected in which case one_hot will be =E2=80=981=E2=80=99 in order to ge= nerate valid R_O output signal.=20 >=20 >=20 > Thank you for your reading. >=20 > Weng Wave-pipelining component series_module (SM) in HDL [0071] FIG. 3 is the interface of a WPC embodiment series_module (SM) li= nked with a series CPC in FIG. 3A. CLK, RESET and SINI are three standard i= nput signals for a synchronous component and the same for each of four WPCs= , and play the same roles. CLK is clock source of the CPC. RESET is a globa= l asynchronous initialization input signal. SINI is a global synchronous in= itialization input signal. Either of RESET/SINI is used to initialize a SM = and one of them must be asserted once to keep SM in initial working status = before it is used. One of RESET/SINI is necessary and another is optional, = and if one of RESET/SINI is not used, it must be connected to =E2=80=980=E2= =80=99 to make it optimized out. [0072] FIG. 3 has two additional input signals and three output signals: =E2=80=A2 Input signal INI is designed to load initialization data into the= linked series CPC. Input data at D_I for the linked CPC is initialization = data if INI is asserted, or working input data otherwise. The assertion of = input signal INI may last as long as needed. Input INI must be connected to= =E2=80=980=E2=80=99 or left opened with default value being =E2=80=980=E2= =80=99 if the linked CPC doesn=E2=80=99t need initialization data. Input si= gnal INI must be asserted after one of RESET/SINI is asserted to make sure = that SM is at the initial state, or wait for the series_clock_number of clo= ck cycles to let the CPC go empty. =E2=80=A2 Input signal WE_I drives write enable signal to the input registe= rs of the linked CPC; input data at D_I of the linked CPC will be latched i= nto the input registers of the CPC on the next clock cycle if WE_I is asser= ted on the current clock cycle, or will not otherwise.=20 =E2=80=A2 Output signal WE_O drives write enable signal to the output regis= ters of the linked CPC; current arriving wave of combinational logic data w= ill be latched into the output registers on the next clock cycle if WE_O is= asserted on the current clock cycle, or will not otherwise.=20 =E2=80=A2 Output signal Valid_O is a data valid output signal; data at D_O = of the linked CPC is valid if Valid_O is asserted or invalid otherwise.=20 =E2=80=A2 Output signal S_O is the Q outputs of each of internal right shif= t registers and may be useful when debugging or implementing a wave-pipelin= ing ready code and optional. No extra logic will be generated if it is left= opened without connection. [0073] The assertion of each of WE_I, WE_O and Valid_O lasts one clock c= ycle for each valid input or output data, respectively.=20 [0074] FIG. 3A is the interface of a series CPC linked with a WPC series= _module in FIG. 3. In addition to the global input signal CLK, the interfac= e has four input signals and one output signal that are essential to wave-p= ipelining: =E2=80=A2 Input signal INI is optional. If it exists, input data at D_I for= the CPC is initialization data when INI is asserted, or working input data= otherwise. The INI assertion may last as long as needed.=20 =E2=80=A2 Input signal WE_I is shared with the linked SM as write enable si= gnal to the input registers. =E2=80=A2 Input signal D_I is data input bus to the CPC.=20 =E2=80=A2 Input signal WE_O_I is write enable signal to the output register= s of the CPC. It comes from the linked SM output signal WE_O and is used to= latch current arriving wave of combinational logic data into output regist= ers.=20 =E2=80=A2 Output signal D_O is output data bus. Output data at D_O is valid= if output signal Valid_O of the linked SM is asserted, or invalid otherwis= e.=20 [0075] A CPC in FIG. 3A may have any number of additional input and outp= ut signals to assist the component and those signals are not drawn here. Th= e dashed lines between FIG. 3 and FIG. 3A show how input and output signals= of two components, a WPC SM and a series CPC, are connected. In addition t= o the connection of global clock signal CLK there are three connections bet= ween the two connected components:=20 =E2=80=A2 Input signals INI of both WPC and CPC are connected together if t= he CPC needs to load initialization data into it before working normally. =E2=80=A2 Input signals WE_I of both components are connected. =E2=80=A2 Output signal WE_O of SM in FIG. 3 drives write enable signal WE_= O_I of its linked series CPC in FIG. 3A. [0076] FIG. 4 is the schematics of a WPC embodiment series_module (SM) l= inked with a series CPC and with input data acceptable on every clock cycle= . 400 is a series CPC; 410 is the input registers of input data bus width; = 420 is its combinational logic circuit; 430 is the output registers of outp= ut data width and input data bus width may be different from output data w= idth. 440 is a SM linked with a series CPC 400 and comprises two sub-compon= ents: 450 is right shift registers with two or more bits; 460 is the right = shift register controller and its schematics are shown in FIG. 4A. In FIG. = 4 dotted line 470 represents the situations when signals take one clock cyc= le to propagate through the series CPC 400 under either slow mode or target= mode; dashed lines represent the situations where the design runs under ta= rget mode and signals take X clock cycles to propagate through the series C= PC 400 with X > 1. The dotted line 470 and dashed lines are mutually exclus= ive. [0077] A SM is essentially right shift registers 450 with a variable len= gth and its controller 460. The right shift registers have X+1 bits, where = X is the number of series clock cycles for CPC 400. When a designer designs= a series CPC or it runs under slow mode, signals are assumed to take one c= lock cycle to propagate through the component, X =3D 1 and the right shift = registers have 2 bits; when the CPC runs under target mode, its number of s= eries clock cycles is X, determined by a synthesizer, and the right shift r= egisters have X+1 bits. S_O output signal is Q outputs of each bit register= of the right shift registers 450 for possible debugging or implementing us= e and optional. [0078] After either RESET or SINI input signal is asserted, the right sh= ift registers are cleared immediately for RESET or on the next clock cycle = for SINI. Each bit register of the right shift registers is connected toget= her one after another with its Q output driving D input of next bit registe= r with following exceptions:=20 =E2=80=A2 A 2-input and-gate A0 has one input coupled to input signal WE_I,= another inversely coupled to input signal INI, and its output driving node= W, D input of the most left bit register FFx and input W of controller 460= .=20 =E2=80=A2 The Q output of second most right bit register drives output sign= al WE_O. =E2=80=A2 The Q output of the most right bit register FF0 drives output sig= nal Valid_O.=20 [0079] A linked pair of a SM and a CPC has two states based on input sig= nal INI value if the CPC has INI input: =E2=80=A2 Initial data loading state: When INI is asserted, node W is deass= erted, leaving right shift registers 450 in an idle state. There will be no= output data latched into the output registers FFo and output signal Valid_= O will be deasserted. Initialization data will be latched into the input re= gisters FFi through D_I on the next clock cycle if input signal WE_I is ass= erted on the current clock cycle. =E2=80=A2 Working state: When INI is deasserted, working data will be latch= ed into the input registers FFi through D_I on the next clock cycle if inpu= t signal WE_I is asserted on the current clock cycle; right shift registers= 450 and its controller 460 are active, output signals WE_O, D_O and Valid_= O work as designed. [0080] In both situations input data will be acceptable on every clock c= ycle. Clock signal is not drawn in the present invention for clarity and si= mplicity. [0081] FIG. 4A is the schematics of the right shift register controller = 460 of a WPC series_module (SM). Or-gate OR1 has (X+2) input signals, where= X is the number of series clock cycles, and under slow mode X =3D 1. =E2=80=A2 Each of input signals Q0-Qx is driven by Q output of one bit regi= ster of the right shift registers, respectively, and the series CPC has val= id data if one of Q0-Qx is asserted or invalid data otherwise. =E2=80=A2 Input signal W is working input data ready signal. If input signa= l INI of a SM is asserted, W is deasserted; when input signal INI is deasse= rted, input signal W is equal to input signal WE_I of the SM.=20 [0082] Or-gate OR1 output signal E drives enable signal E to each bit re= gister of the right shift registers 450. The right shift registers 450 will= right shift one bit on next clock cycle if E is asserted on the current cl= ock cycle or will not otherwise. Right shift registers 450 will right shift= one bit on next clock cycle in either of two situations: =E2=80=A2 There are valid data in the linked CPC. =E2=80=A2 There is a working input data to enter the linked CPC. [0083] Care must be taken before input signal INI is asserted if its CPC= still contains valid data in it. In the situation the linked SM will conti= nue to work to output internal valid data until it is empty, but the CPC ma= y change its internal data flow if input signal INI to the CPC is asserted,= contaminating the outgoing data. Of course, to people in the art the embod= iment of right shift registers can be replaced by embodiment of left shift = registers. [0084] Based on connections of FIG. 3 and FIG. 3A a WPC series_module ha= s nothing to do with input data at D_I and output data at D_O of its linked= CPC, so series_module can handle any types of input data and output data o= f a series CPC and doesn=E2=80=99t have any overloading type. Weng From newsfish@newsfish Thu Aug 1 00:32:51 2024 X-Received: by 10.182.80.7 with SMTP id n7mr2568662obx.10.1427162442489; Mon, 23 Mar 2015 19:00:42 -0700 (PDT) X-Received: by 10.140.34.56 with SMTP id k53mr29349qgk.19.1427162442367; Mon, 23 Mar 2015 19:00:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed1a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z20no3967514igj.0!news-out.google.com!q90ni527qgd.1!nntp.google.com!h3no4425160qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Mar 2015 19:00:42 -0700 (PDT) In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.49.104.28; posting-account=9GnU7goAAAAHU53ujXD8Ejd5wZPBXz8p NNTP-Posting-Host: 50.49.104.28 References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <06a2a4ed-38e1-42bb-9ceb-619ec784bc8a@googlegroups.com> Subject: Re: c-language to VHDL converter From: Derek Simmons Injection-Date: Tue, 24 Mar 2015 02:00:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 27 Xref: news.eternal-september.org comp.lang.vhdl:3652 On Wednesday, March 4, 2015 at 3:38:38 AM UTC-5, Sai Jaswanth wrote: > hi friends can any one help me in knowing how to convert the c-code to VH= DL directly by any software. (or) can we compile C-code in xilinx IDE? I tried out Impulse C it had its pluses and minuses.=20 Pluses:=20 In an image processing environment the FPGA engineers created that was shar= ed between the FPGA engineers and the imaging scientist. The imaging scient= ist didn't understand what we did but worked within the framework we create= d for them. They would develop their algorithms is Visual Studio and demo a= pplications. We would make sure the projects would translate from C to VHDL= . Minuses: You were limited to do things that would translate 'nicely' to VHDL and usi= ng constructs that would convert to VHDL.=20 My advice is get a copy of Pong Chu's, "RTL Hardware Design Using VHDL" and= read chapters 11 and 12 on Register Transfer Methodology. We had a plain t= ext license and under the hood this is kind of what the C to VHDL compiler = was doing.=20 What we decided to do was create a design standard and write it by hand bec= ause it was easier for us to support. You can't beat a good VHDL designer. From newsfish@newsfish Thu Aug 1 00:32:51 2024 X-Received: by 10.52.29.4 with SMTP id f4mr6203249vdh.3.1427221371762; Tue, 24 Mar 2015 11:22:51 -0700 (PDT) X-Received: by 10.50.51.67 with SMTP id i3mr303507igo.15.1427221371700; Tue, 24 Mar 2015 11:22:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!border2.nntp.ams2.giganews.com!backlog4.nntp.ams3.giganews.com!buffer2.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!h3no4567023qgf.1!news-out.google.com!db6ni61707igc.0!nntp.google.com!z20no2876875igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Mar 2015 11:22:50 -0700 (PDT) In-Reply-To: <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Tue, 24 Mar 2015 18:22:51 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 2094 X-Original-Bytes: 93234 Xref: news.eternal-september.org comp.lang.vhdl:3653 On Saturday, March 21, 2015 at 3:23:34 PM UTC-7, Weng Tianxiang wrote: > On Friday, March 13, 2015 at 10:45:11 PM UTC-7, Weng Tianxiang wrote: > > On Monday, March 9, 2015 at 3:02:48 AM UTC-7, Weng Tianxiang wrote: > > > On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote: > > > > On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang = wrote: > > > > > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang= wrote: > > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > > >=20 > > > > > > I have filed a provisional patent application: "Systematic meth= od of coding wave pipelined circuits in HDL". If it is proved correct, the = patent will introduce 1 keyword, 3 permanent constants, 1 concurrent statem= ent and four source code modules for a new library in HDL and thoroughly re= solve a pending problem so that every digital designer can code wave-pipeli= ned circuits in HDL. > > > > > >=20 > > > > > > Here is the abstract of the invention: > > > > > >=20 > > > > > > The present invention classifies all critical paths into tw= o basic types: a series critical path and a feedback critical path, and div= ides each of wave-pipelined circuits into two components: a static logic pa= rt, called critical path component (CPC), and a dynamic logic part, formali= zed into four wave-pipelining components (WPC) shared by all wave-pipelined= circuits. Each wave-pipelining ready code in HDL comprises two components:= a WPC instantiation and a CPC instantiation wire-connected and linked by a= new link statement. Each WPC has new wave constants which play the same ro= le as generic constants do, but whose initial values are determined and ass= igned by a synthesizer after code analysis, so designers can use after-synt= hesization information in their code before synthesization for wave-pipelin= ing technology. The responsibility of analyzing and manipulating wave-pipel= ining ready code, generating and implementing wave-pipelined circuits on a = design-wide or chip-wide scale in HDL is shifted from designers to synthesi= zers. > > > > > >=20 > > > > > > Anyone who are interested in its content is welcome to send a e= mail request to the following email address: wtx wtx @ gmail . com with tit= le "Systematic" and he will receive the full documents: one specification, = 9 drawings and one text file in VHDL. > > > > > >=20 > > > > > > If one reviews the files and feels that it would be a good thin= g to recommend the application to his company to buy it, the first person t= o do it after his recommended company does so will receive $10,000 commissi= on fee. > > > > > >=20 > > > > > > Thank you. > > > > > >=20 > > > > > > Weng > > > > >=20 > > > > > Hi, > > > > > I want to add some introductions to what the wave-pipelined circu= its are and their status. > > > > >=20 > > > > > [0003] A synchronous digital system contains a lot of register= s. Valid data flow through successive registers from system input registers= to system output registers. All data flows are synchronous with triggering= edges of a chip clock. For example, data flow from registers A to register= s B, from registers B to registers C and so on in a successive order on the= same clock cycle. > > > > > [0004] A path in a synchronous digital system is a route betwe= en any neighboring registers connected by combinational logic. If the targe= t running frequency for a digital design is predetermined, the upper limit = of propagating time for any paths is determined and has the inverse value o= f the target running frequency. A path is called a critical path if the tim= e signals take to propagate through it is beyond the predetermined propagat= ing time, and the time is called the path's critical time. If there are any= critical paths, digital designers must spend time reducing all critical ti= mes by all means and eliminating all critical paths to meet the target runn= ing frequency. > > > > > [0005] Wave-pipelining is a technology which completes an oper= ation that needs several clock cycles to propagate without intermediate reg= isters and with input data acceptable on every clock cycle. For example, in= a conventional pipelining operation, data flow from registers A to registe= rs D through registers B and C to divide the critical path time into multip= le smaller intervals to meet the critical time: A to B to C to D; with wave= -pipelining, data flow through registers A and D without intermediate regis= ters B and C. Absolutely, wave-pipelining will reduce logic resource usage = and is superior to the conventional pipelining technology if it can be used= . > > > > >=20 > > > > > Here are the most important inequalities involving wave-pipelinin= g from paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. = Burleson et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. = 6, no. 3, pp. 464-474, Sep. 1998. > > > > >=20 > > > > > [0018] Currently many memory chip manufacturers successfully u= se wave-pipelining in their memory chip products with higher rate outputs, = reduced power consumption and logic resources; and a few scientists use FPG= A chips as a base to show some circuits can be done with wave-pipelining in= isolated environments. Their works prove that the wave-pipelining is a ver= y powerful tool to reduce power consumption and logic resources. Now there = are two major existing obstacles preventing any ordinary digital designers = from using the wave-pipelining in HDL: > > > > > * The software algorithms making wave-pipelining successful, like= Wong and Klass algorithms and others, have already been developed and matu= red, but ordinary digital designers have no means or resources to access to= the technology, because there are no international HDL standards on how sy= nthesizer manufacturers incorporate those capabilities into their products. > > > > > * HDL needs the capabilities for digital designers to write wave-= pipelining ready code for any number of critical paths on a design-wide or = chip-wide scale instead of in an isolated environment and the written code = can be identified, synthesized and used to generate wave-pipelined circuits= by any synthesizer in ASIC or FPGA, and they should be part of HDL standar= ds.=20 > > > > > [0019] The target of the present invention is: > > > > > * Invent a wave-pipelining coding system as new part of HDL stand= ards for designers to write wave-pipelining ready code which can be identif= ied, synthesized and used to generate wave-pipelined circuits by any synthe= sizer in ASIC or FPGA. > > > > > * Make wave-pipelining ready code written based on the coding sys= tem working with no extra logic generated, compared with independently writ= ten wave-pipelined circuits, and with no code changes when switching from n= on-wave-pipelined mode to wave-pipelined mode or vice verse if all of wave-= pipelining ready code meet wave-pipelining requirements.=20 > > > > > * Shift burdens of analyzing and manipulating wave-pipelining rea= dy code, generating and implementing wave-pipelined circuits on a design-wi= de or chip-wide scale in HDL from individual designers to synthesizer manuf= acturers. > > > > > [0020] If the coding system becomes new part of HDL standards = all synthesizer manufactures will automatically be forced to implement all = well-known wave-pipelining algorithms and techniques within their products,= a competition will start for better implementations, making wave-pipelinin= g technique available to every digital designer in HDL. > > > > >=20 > > > > > Weng > > > >=20 > > > > Here I add some contents of the invention: > > > >=20 > > > > Main idea behind the present invention > > > >=20 > > > > [0057] The most difficult part coding all types of wave-pipeline= d circuits on a design-wide scale in HDL is that a wave-pipelined circuit c= ode always comprises two logic parts:=20 > > > > * A static logic part: it doesn't change if the number of series cl= ock cycles through the circuit changes and is unique for each of wave-pipel= ined circuits. > > > > * A dynamic logic part: it does change if the number of series cloc= k cycles through the circuit changes and is the same for one of groups of w= ave-pipelined circuits. > > > > [0058] Every wave-pipelined circuit has its own change rules and= those changes are unknown to designers when they are writing code and will= be known to a synthesizer only after it has analyzed the circuit. > > > > [0059] The present invention classifies all critical paths into = two basic types: a series critical path and a feedback critical path, and d= ivides each of wave-pipelined circuits into two components: one is static l= ogic part and called critical path component (CPC); another is dynamic logi= c part and formalized into four wave-pipelining components (WPC) shared by = all wave-pipelined circuits. Under the present invention each of standard w= ave-pipelining ready code in HDL comprises two components: a WPC instantiat= ion and a CPC instantiation which are wire-connected and linked by a new co= ncurrent link statement. Each of four WPC embodiments has a group of new ty= pe wave constant, which plays the same role as a generic constant does, but= whose initial value is determined and assigned by a synthesizer after it h= as analyzed the linked CPC component under slow mode and target mode, respe= ctively, so designers can use after-synthesization information in their cod= e before synthesization in HDL for wave-pipelining technology. Following th= e instructions of the present invention creates a situation that digital de= signers can write wave-pipelining ready code in HDL and the responsibility = of analyzing and manipulating wave-pipelining ready code, generating and im= plementing wave-pipelined circuits on a design-wide or chip-wide scale in H= DL is shifted from individual designers to synthesizer manufacturers. > > > >=20 > > > > How the method works > > > >=20 > > > > [0060] The systematic method of coding wave-pipelined circuits i= n HDL comprises following ten parts: > > > > 1. Define five signals, one counter, one switch and one table that = will be used when generating wave-pipelined circuits on a design-wide or ch= ip-wide scale in HDL. > > > > 2. Define the interfaces of a CPC each of which encapsulates a crit= ical path's static logic part. > > > > 3. Define and implement four WPC embodiments in HDL each of which i= s a critical path's dynamic logic part: a series_module, an input_delay_mod= ule, a multiple_copy_module1 and a multiple_copy_module2. > > > > 4. Define one new keyword wave and three new wave constants which p= rovide a means to dynamically transfer after-synthesization information to = designers' code before synthesization. > > > > 5. Define the methods of determining and searching for wave constan= t values of a known WPC instantiation under slow mode and target mode, resp= ectively. > > > > 6. Define three versions of a concurrent link statement: link1, lin= k2 and link3, and rules on how they are used. > > > > 7. Define the pairing rules between a WPC and a CPC. > > > > 8. Define how a digital designer prepares wave-pipelining ready cod= e systematically. > > > > 9. Shift the responsibility of analyzing and manipulating wave-pipe= lining ready code, generating and implementing wave-pipelined circuits on a= design-wide or chip-wide scale in HDL from individual designers to synthes= izer manufacturers. > > > > 10. Define how four WPC embodiments are simulated and debugged unde= r any of current versions of a synthesizer in HDL. > > > > [0061] It is fair to put the burden of successfully generating w= ave-pipelined circuits based on wave-pipelining ready code squarely on synt= hesizer manufacturers' shoulder if all necessary information is passed to a= synthesizer. For example, with tens of papers claiming that successful wav= e-pipelined circuits are implemented in FPGA chips in an isolated environme= nt, it is the responsibility of FPGA synthesizers to be capable of generati= ng those wave-pipelined circuits in a design-wide environment without desig= ners' further involvements, a process similar for them to the task of gener= ating a circuit with the highest running frequency and minimum used resourc= es if possible for any normal digital design code. > > > >=20 > > > > Thank you for your reading. > > >=20 > > > Here are more contents. > > >=20 > > > Definitions of wave-pipelining component and critical path component > > >=20 > > > [0062] A design component is called a critical path component (CPC= ) if it is an entity (a term in VHDL-2002) in HDL and encapsulates the stat= ic logic part of a critical path which is to be wave-pipelined circuit. The= re are two types of CPCs:=20 > > > =E2=80=A2 A series CPC: it encapsulates a series critical path=E2=80= =99s static logic part. > > > =E2=80=A2 A feedback CPC: it encapsulates a feedback critical path=E2= =80=99s static logic part.=20 > > >=20 > > > [0063] A CPC also refers to a CPC instantiation when it will not b= e misunderstood. The required interfaces of both a series CPC and a feedbac= k CPC are always the same. The combinational logic of a CPC may be located = within or outside of the component and there is no limit on it.=20 > > >=20 > > > [0064] A design component is called a wave-pipelining component (W= PC) if it is an entity in HDL, provided by HDL in a new wave-pipelining sys= tem library and used to generate a critical path=E2=80=99s dynamic logic pa= rt, i.e., to generate output data valid signal and write enable signals to = the input and output registers of a critical path.=20 > > >=20 > > > [0065] There are three types of WPC:=20 > > > =E2=80=A2 A series_module is used to connect to a series CPC with inp= ut data acceptable on every clock cycle. > > > =E2=80=A2 An input_delay_module is used to connect to a series or fee= dback CPC with input data acceptable on every one or more clock cycle. > > > =E2=80=A2 A multiple_copy_module1 or a multiple_copy_module2 is used = to connect to multiple copied series or feedback CPCs with input data accep= table on every clock cycle. > > >=20 > > > [0066] A WPC also refers to a WPC instantiation when it will not b= e misunderstood. Later multiple_copy_module refers to either of multiple_co= py_module1 and multiple_copy_module2. > > >=20 > > > A synthesizer=E2=80=99s new signals, switch and table > > >=20 > > > [0067] A synthesizer that is able of handling wave-pipelining need= s six signals, one switch, one table and the table=E2=80=99s row index to h= elp finish its job: > > > =E2=80=A2 A floating signal target_running_frequency: it is set up by= a designer and the target running frequency under which a design finally r= uns. > > > =E2=80=A2 A bit signal generate_circuit: it is set up by a designer a= nd its initial value is deasserted. A synthesizer will generate related cir= cuit files for a design under slow mode for slow mode hardware testing if g= enerate_circuit is asserted and no errors are detected after a synthesizati= on, or will not otherwise. A synthesizer will always generate related circu= it files for a design under target mode for target mode hardware testing if= no errors are detected after a synthesization. > > > =E2=80=A2 A bit signal feedback_bit: it is set up by a synthesizer an= d its initial value is deasserted. Assert the bit if a CPC is being analyze= d and determined to have feedbacks, and deassert it after the analysis is f= inished. > > > =E2=80=A2 A bit signal keep_target_circuit: it is set up by a designe= r and its initial value is deasserted. Assert the bit if a designer wants t= o keep all CPC new circuits automatically and successfully modified by a sy= nthesizer under target mode unchanged under slow mode when he is switching = to synthesize the same design from under target mode to under slow mode and= the related code doesn=E2=80=99t change, or deassert it otherwise. The bit= provides a method for a designer to check if the new automatically and suc= cessfully modified circuits by a synthesizer don=E2=80=99t change basic log= ic.=20 > > > =E2=80=A2 An integer signal parent_series_clock_number: it is set up = by a synthesizer and Its initial value is zero. When the instantiation of a= WPC delay_input_module or multiple_copy_module is being analyzed and execu= ted its series_clock_number value is stored in parent_series_clock_number, = and it is cleared to zero when the execution is finished. > > > =E2=80=A2 An integer signal start_number: it is set up by a synthesiz= er and used when the synthesizer determines that a CPC cannot meet the wave= -pipelining requirements with input data acceptable on every clock cycle an= d the CPC is linked with a WPC input_delay_module or multiple_copy_module. = The start_number is made equal to 2 if a WPC multiple_copy_module is linked= or to feedback_clock_number if a WPC input_delay_module is linked as the s= tarting value of wave constant input_clock_number or multiple_copy_number. > > > =E2=80=A2 A bit switch running_mode: it is set up by a designer and i= t has two valid values with slow mode being its initial value: > > > o Slow mode: under slow mode a digital designer designs his code, a d= esign is synthesized, simulated, and hardware tested under the following as= sumptions: > > > =EF=82=A7 Signals take one clock cycle to propagate through any of CP= Cs under slow running frequency. > > > =EF=82=A7 Any of CPCs has input data acceptable on every clock cycle. > > > =EF=82=A7 No multiple copied CPCs are generated. > > > o Target mode: under target mode a design is synthesized, simulated, = hardware tested and finally runs under predetermined target running frequen= cy, and its implementation is determined and generated by a synthesizer und= er the following assumptions: > > > =EF=82=A7 Signals take one or more clock cycle to propagate through a= ny of CPCs as designed. > > > =EF=82=A7 Each of CPCs has input data acceptable on every one or more= clock cycle as wave-pipelining ready code indicates and it is necessary. > > > =EF=82=A7 Multiple copied CPCs are generated as wave-pipelining ready= code indicates and it is necessary. > > > =E2=80=A2 A wave constant signal table: it is generated and manipulat= ed by a synthesizer and stores information about each linked pair of a CPC = and a WPC; all wave constant values and alias wave constant values can be a= ccessed from the table. > > > =E2=80=A2 An integer row_index to the wave constant signal table: it = is set up by a synthesizer and its initial value is 1. It is used as a row = index for a new link statement in the wave constant signal table and will b= e increased by 1 after a synthesizer finishes the filling of the row during= the source code scanning.=20 > > >=20 > > > Thank you for your reading. > > >=20 > > > Weng > >=20 > > Here are more contents. It shows how a complicated problem is resolved = by creative ideas. > >=20 > >=20 > > New keyword wave and wave constant in HDL > >=20 > > [0068] When writing wave-pipelining code, digital designers don=E2= =80=99t know how many clock cycles signals need to propagate through a crit= ical path, and to finish their jobs, it may take several working cycles for= them manually to adjust their code to make a wave-pipelined circuit workin= g. This method is not feasible on a design-wide or chip-wide scale, because= a design may have 100 or more critical paths to be wave-pipelined circuits= and there is no guarantee for designers to perfectly remember which is fin= ished and which is not, and most importantly, synthesizers are left aside o= f the business of wave-pipelining, giving no help at all. One of obstacles = using wave-pipelining in HDL is how to establish a communication channel be= tween a synthesizer and digital designers to provide the following essentia= l functions: > >=20 > > =E2=80=A2 How a designer can use after-synthesization information to wr= ite code for wave-pipelined circuits before they have been synthesized in H= DL for wave-pipelining technology. This function is not necessary for succe= ssfully generating a wave-pipelined circuit, but beneficial to implement a = complex one. > >=20 > > =E2=80=A2 If all pieces of wave-pipelining ready code are written, a de= sign has passed simulations and/or hardware testing under slow mode perfect= ly, and a synthesizer certifies that all wave-pipelining requirements are m= et with input data acceptable on every one or more clock cycle and no error= s are detected after a synthesization, then correct full design circuits ca= n be generated under target mode and work as designed with no code change d= uring the switching from slow mode to target mode or vice verse on a design= -wide or chip-wide scale. This function is critical and essential for succ= essfully generating all wave-pipelined circuits on a design-wide or chip-wi= de scale in HDL. > >=20 > > [0069] New keyword wave and three wave constants are introduced to r= esolve the problem. In the following listing characters in bold type are ne= w suggested definitions based on VHDL-2002. > >=20 > > entity_declaration ::=3D=20 > > entity identifier is > > entity_header > > entity_declarative_part > > [begin > > entity_statement_part ] > > end [ entity ] [ entity_simple_name ] ; > >=20 > > entity_header ::=3D > > [formal_generic_clause ] > > [formal_port_clause ] > >=20 > > generic_clause ::=3D generic ( generic_list ) ; > > generic_list ::=3D generic_interface_list > > interface_list ::=3D interface_element { ; interface_element } > > interface_element ::=3D interface_declaration > >=20 > > interface_declaration ::=3D > > interface_constant_declaration > > |interface_wave_constant_declaration > > | interface_signal_declaration > > | interface_variable_declaration > > | interface_file_declaration > >=20 > > interface_constant_declaration ::=3D > > [constant] identifier_list : [ in] subtype_indication [ :=3D static_exp= ression ] > >=20 > > interface_wave_constant_declaration ::=3D > > wave [constant] wave_constant_list : [ in ] subtype_indication > > [ :=3D static_expression ] > >=20 > > wave_constant_list ::=3D=20 > > wave_constant_element { , wave_constant_element } > >=20 > > wave_constant_element ::=3D=20 > > wave_constant > > |internal_wave_constant > >=20 > > wave_constant ::=3D > > series_clock_number > > | input_clock_number > > | multiple_copy_number > >=20 > > internal_wave_constant ::=3D one_hot > >=20 > > entity_declarative_part ::=3D > > { entity_declarative_item } > >=20 > > entity_declarative_item ::=3D > > subprogram_declaration > > | subprogram_body > > | type_declaration > > | subtype_declaration > > | constant_declaration > > | alias_wave_constant_declaration > > | signal_declaration > > |shared_variable_declaration > > | file_declaration > > | alias_declaration > > | attribute_declaration > > | attribute_specification > > | disconnection_specification > > | use_clause > > | group_template_declaration > > | group_declaration > >=20 > > architecture_body ::=3D > > architecture identifier of entity_name is > > architecture_declarative_part > > begin > > architecture_statement_part > > end[ architecture ] [ architecture_simple_name ] ; > >=20 > > architecture_declarative_part ::=3D > > { block_declarative_item } > >=20 > > block_declarative_item ::=3D > > subprogram_declaration > > | subprogram_body > > | type_declaration > > | subtype_declaration > > | constant_declaration > > | alias_wave_constant_declaration > > | signal_declaration > > | shared_variable_declaration > > | file_declaration > > | alias_declaration > > | component_declaration > > | attribute_declaration > > | attribute_specification > > | configuration_specification > > | disconnection_specification > > | use_clause > > | group_template_declaration > > | group_declaration > >=20 > > constant_declaration ::=3D > > constant identifier_list : subtype_indication [ :=3D expression ] ; > >=20 > > alias_wave_constant_declaration ::=3D > > wave [ constant ] alias_wave_constant_list : subtype_indication :=3D=20 > > wave_constant ; > >=20 > > alias_wave_constant_list ::=3D > > alias_wave_constant { , alias_wave_constant } > >=20 > > alias_wave_constant ::=3D identifier > >=20 > > [0070] The set of following rules is called wave constant mechanism: > >=20 > > =E2=80=A2 There are three wave constants related to wave-pipelining tec= hnique: series_clock_number, input_clock_number and multiple_copy_number.= =20 > >=20 > > =E2=80=A2 A wave constant can only be declared in the generic_clause of= the entity definition of a WPC embodiment, plays the same role as a generi= c constant declared in the same place does except that it has actual initia= l value 1 under slow mode, and actual initial value equal to or greater tha= n 1 determined and assigned by a synthesizer under target mode, and the sta= tic expression in an interface wave constant declaration is always ignored. > >=20 > > =E2=80=A2 A WPC instantiation must not include corresponding associatio= n element with a formal wave constant in the generic map aspect.=20 > >=20 > > =E2=80=A2 Any wave constant declared in a WPC definition is accessible = by designers through an alias wave constant declaration. > >=20 > > =E2=80=A2 An alias wave constant declaration identifies a list of alias= wave constants which are assigned a wave constant. Each alias wave constan= t must be linked with a WPC instantiation through a link statement and shar= es the wave constant value of the linked WPC instantiation for testing, deb= ugging or implementing purpose. An alias wave constant plays the same role = as a normal constant declared in the same place does.=20 > >=20 > > =E2=80=A2 A CPC may have any of its linked WPC=E2=80=99s wave constants= and output signals as its own input signal, but must have no input signals= which are related to any unrelated WPC instantiation=E2=80=99s wave consta= nts. > >=20 > > =E2=80=A2 The internal wave constant one_hot is used internally by a sy= nthesizer to optimize the implementation of a WPC and not accessible by des= igners.=20 > >=20 > > =E2=80=A2 A synthesizer has its discretion to determine internal wave c= onstant one_hot value based on the environment and the consideration of its= production technique used unless a WPC input_delay_module has its R_O outp= ut connected in which case one_hot will be =E2=80=981=E2=80=99 in order to = generate valid R_O output signal.=20 > >=20 > >=20 > > Thank you for your reading. > >=20 > > Weng >=20 > Wave-pipelining component series_module (SM) in HDL >=20 > [0071] FIG. 3 is the interface of a WPC embodiment series_module (SM) = linked with a series CPC in FIG. 3A. CLK, RESET and SINI are three standard= input signals for a synchronous component and the same for each of four WP= Cs, and play the same roles. CLK is clock source of the CPC. RESET is a glo= bal asynchronous initialization input signal. SINI is a global synchronous = initialization input signal. Either of RESET/SINI is used to initialize a S= M and one of them must be asserted once to keep SM in initial working statu= s before it is used. One of RESET/SINI is necessary and another is optional= , and if one of RESET/SINI is not used, it must be connected to =E2=80=980= =E2=80=99 to make it optimized out. >=20 > [0072] FIG. 3 has two additional input signals and three output signal= s: > =E2=80=A2 Input signal INI is designed to load initialization data into t= he linked series CPC. Input data at D_I for the linked CPC is initializatio= n data if INI is asserted, or working input data otherwise. The assertion o= f input signal INI may last as long as needed. Input INI must be connected = to =E2=80=980=E2=80=99 or left opened with default value being =E2=80=980= =E2=80=99 if the linked CPC doesn=E2=80=99t need initialization data. Input= signal INI must be asserted after one of RESET/SINI is asserted to make su= re that SM is at the initial state, or wait for the series_clock_number of = clock cycles to let the CPC go empty. > =E2=80=A2 Input signal WE_I drives write enable signal to the input regis= ters of the linked CPC; input data at D_I of the linked CPC will be latched= into the input registers of the CPC on the next clock cycle if WE_I is ass= erted on the current clock cycle, or will not otherwise.=20 > =E2=80=A2 Output signal WE_O drives write enable signal to the output reg= isters of the linked CPC; current arriving wave of combinational logic data= will be latched into the output registers on the next clock cycle if WE_O = is asserted on the current clock cycle, or will not otherwise.=20 > =E2=80=A2 Output signal Valid_O is a data valid output signal; data at D_= O of the linked CPC is valid if Valid_O is asserted or invalid otherwise.= =20 > =E2=80=A2 Output signal S_O is the Q outputs of each of internal right sh= ift registers and may be useful when debugging or implementing a wave-pipel= ining ready code and optional. No extra logic will be generated if it is le= ft opened without connection. >=20 > [0073] The assertion of each of WE_I, WE_O and Valid_O lasts one clock= cycle for each valid input or output data, respectively.=20 >=20 > [0074] FIG. 3A is the interface of a series CPC linked with a WPC seri= es_module in FIG. 3. In addition to the global input signal CLK, the interf= ace has four input signals and one output signal that are essential to wave= -pipelining: > =E2=80=A2 Input signal INI is optional. If it exists, input data at D_I f= or the CPC is initialization data when INI is asserted, or working input da= ta otherwise. The INI assertion may last as long as needed.=20 > =E2=80=A2 Input signal WE_I is shared with the linked SM as write enable = signal to the input registers. > =E2=80=A2 Input signal D_I is data input bus to the CPC.=20 > =E2=80=A2 Input signal WE_O_I is write enable signal to the output regist= ers of the CPC. It comes from the linked SM output signal WE_O and is used = to latch current arriving wave of combinational logic data into output regi= sters.=20 > =E2=80=A2 Output signal D_O is output data bus. Output data at D_O is val= id if output signal Valid_O of the linked SM is asserted, or invalid otherw= ise.=20 >=20 > [0075] A CPC in FIG. 3A may have any number of additional input and ou= tput signals to assist the component and those signals are not drawn here. = The dashed lines between FIG. 3 and FIG. 3A show how input and output signa= ls of two components, a WPC SM and a series CPC, are connected. In addition= to the connection of global clock signal CLK there are three connections b= etween the two connected components:=20 > =E2=80=A2 Input signals INI of both WPC and CPC are connected together if= the CPC needs to load initialization data into it before working normally. > =E2=80=A2 Input signals WE_I of both components are connected. > =E2=80=A2 Output signal WE_O of SM in FIG. 3 drives write enable signal W= E_O_I of its linked series CPC in FIG. 3A. >=20 > [0076] FIG. 4 is the schematics of a WPC embodiment series_module (SM)= linked with a series CPC and with input data acceptable on every clock cyc= le. 400 is a series CPC; 410 is the input registers of input data bus width= ; 420 is its combinational logic circuit; 430 is the output registers of ou= tput data width and input data bus width may be different from output data= width. 440 is a SM linked with a series CPC 400 and comprises two sub-comp= onents: 450 is right shift registers with two or more bits; 460 is the righ= t shift register controller and its schematics are shown in FIG. 4A. In FIG= . 4 dotted line 470 represents the situations when signals take one clock c= ycle to propagate through the series CPC 400 under either slow mode or targ= et mode; dashed lines represent the situations where the design runs under = target mode and signals take X clock cycles to propagate through the series= CPC 400 with X > 1. The dotted line 470 and dashed lines are mutually excl= usive. >=20 > [0077] A SM is essentially right shift registers 450 with a variable l= ength and its controller 460. The right shift registers have X+1 bits, wher= e X is the number of series clock cycles for CPC 400. When a designer desig= ns a series CPC or it runs under slow mode, signals are assumed to take one= clock cycle to propagate through the component, X =3D 1 and the right shif= t registers have 2 bits; when the CPC runs under target mode, its number of= series clock cycles is X, determined by a synthesizer, and the right shift= registers have X+1 bits. S_O output signal is Q outputs of each bit regist= er of the right shift registers 450 for possible debugging or implementing = use and optional. >=20 > [0078] After either RESET or SINI input signal is asserted, the right = shift registers are cleared immediately for RESET or on the next clock cycl= e for SINI. Each bit register of the right shift registers is connected tog= ether one after another with its Q output driving D input of next bit regis= ter with following exceptions:=20 > =E2=80=A2 A 2-input and-gate A0 has one input coupled to input signal WE_= I, another inversely coupled to input signal INI, and its output driving no= de W, D input of the most left bit register FFx and input W of controller 4= 60.=20 > =E2=80=A2 The Q output of second most right bit register drives output si= gnal WE_O. > =E2=80=A2 The Q output of the most right bit register FF0 drives output s= ignal Valid_O.=20 >=20 > [0079] A linked pair of a SM and a CPC has two states based on input s= ignal INI value if the CPC has INI input: > =E2=80=A2 Initial data loading state: When INI is asserted, node W is dea= sserted, leaving right shift registers 450 in an idle state. There will be = no output data latched into the output registers FFo and output signal Vali= d_O will be deasserted. Initialization data will be latched into the input = registers FFi through D_I on the next clock cycle if input signal WE_I is a= sserted on the current clock cycle. > =E2=80=A2 Working state: When INI is deasserted, working data will be lat= ched into the input registers FFi through D_I on the next clock cycle if in= put signal WE_I is asserted on the current clock cycle; right shift registe= rs 450 and its controller 460 are active, output signals WE_O, D_O and Vali= d_O work as designed. >=20 > [0080] In both situations input data will be acceptable on every clock= cycle. Clock signal is not drawn in the present invention for clarity and = simplicity. >=20 > [0081] FIG. 4A is the schematics of the right shift register controlle= r 460 of a WPC series_module (SM). Or-gate OR1 has (X+2) input signals, whe= re X is the number of series clock cycles, and under slow mode X =3D 1. > =E2=80=A2 Each of input signals Q0-Qx is driven by Q output of one bit re= gister of the right shift registers, respectively, and the series CPC has v= alid data if one of Q0-Qx is asserted or invalid data otherwise. > =E2=80=A2 Input signal W is working input data ready signal. If input sig= nal INI of a SM is asserted, W is deasserted; when input signal INI is deas= serted, input signal W is equal to input signal WE_I of the SM.=20 >=20 > [0082] Or-gate OR1 output signal E drives enable signal E to each bit = register of the right shift registers 450. The right shift registers 450 wi= ll right shift one bit on next clock cycle if E is asserted on the current = clock cycle or will not otherwise. Right shift registers 450 will right shi= ft one bit on next clock cycle in either of two situations: > =E2=80=A2 There are valid data in the linked CPC. > =E2=80=A2 There is a working input data to enter the linked CPC. >=20 > [0083] Care must be taken before input signal INI is asserted if its C= PC still contains valid data in it. In the situation the linked SM will con= tinue to work to output internal valid data until it is empty, but the CPC = may change its internal data flow if input signal INI to the CPC is asserte= d, contaminating the outgoing data. Of course, to people in the art the emb= odiment of right shift registers can be replaced by embodiment of left shif= t registers. >=20 > [0084] Based on connections of FIG. 3 and FIG. 3A a WPC series_module = has nothing to do with input data at D_I and output data at D_O of its link= ed CPC, so series_module can handle any types of input data and output data= of a series CPC and doesn=E2=80=99t have any overloading type. >=20 > Weng Here I publish all source code for public confirmation. There must be some = misunderstanding because only part of my application document was published= . You may copy this part of code to do simulation by yourself. The line maxim= um width is 95 char. -- Author: Weng Tianxiang -- Diamond Bar, CA 91705 -- USA -- Email: wtxwtx@gmail.com -- Date: 2014/09/14 -- 2015/01/29 -- Project: Systematic method of coding wave-pipelined circuits in HDL -- File name: WPC-CPC.vhd -- this design is written and works using VHDL-2002 synthsizer -- all changes using VHDL-2008 are noted properly. -- critical path coding is based on the assumption:=20 -- signals take 1 clock cycle to propagate thru any critical path under slo= w_mode=20 -- signals take N clock cycle to propagate thru a critical path under targe= t_mode ---------------------------------------------------------------------------= ---- -- it must do following sets of simulations under different parameter combi= nations -- INI =3D '1', '0' and following conbinations -- ONE_HOT =3D '1', '0' and following conbinations -- constant MULTIPLE_COPY_NUMBER : positive :=3D 1; it generates slow mode -- constant SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- constant INPUT_CLOCK_NUMBER : positive :=3D 1; =20 -- for target mode simulation,=20 -- 1 <=3D INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER; -- 1 <=3D MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER; -- it must do 6*2 sets of simulations and it generates target mode -- constant SERIES_CLOCK_NUMBER : positive :=3D 6; =20 -- constant MULTIPLE_COPY_NUMBER : positive :=3D 1.. <=3D SERIES_CLOCK_NUMB= ER -- constant INPUT_CLOCK_NUMBER : positive :=3D 1.. <=3D SERIES_CLOCK_NUMB= ER=20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- used only for this simulation package wave_pipeline_package is=20 -- for target mode simulation,=20 -- 1 <=3D INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER; -- 1 <=3D MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER; -- the number of clock cycles signals takes thru a serial critical path constant SERIES_CLOCK_NUMBER : positive :=3D 6; -- for target mode sim= ulation -- the number of multiple copied CPCs constant MULTIPLE_COPY_NUMBER : positive :=3D 4; -- the number of clock cycles to accept next input data constant INPUT_CLOCK_NUMBER : positive :=3D 3; =20 -- constant MULTIPLE_COPY_NUMBER : positive :=3D 1; -- for slow mode simula= tion -- constant SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- constant INPUT_CLOCK_NUMBER : positive :=3D 1; =20 -- '1': use Left_rotator; '0' : use Counter constant ONE_HOT : std_logic :=3D '1'; -- '1': initializaton data; '0': working data=20 constant INI : std_logic :=3D '0'; =20 -- in this simulation, DATA_IN_WIDTH =3D DATA_OUT_WIDTH for simplicity constant DATA_IN_WIDTH : positive :=3D 8; -- data in width constant DATA_OUT_WIDTH : positive :=3D 8; -- data out width -- VHDL-2002 type OUT_DATA_ARRAY is array(natural range <>) of unsigned(DATA_OUT_WIDT= H-1 downto 0); type OUT_SHIFT_ARRAY is array(natural range <>) of unsigned(SERIES_CLOCK= _NUMBER downto 0); -- VHDL-2008 -- type OUT_DATA_ARRAY_8 is array(natural range <>) of unsigned(natural ran= ge <>); end wave_pipeline_package; ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ---------------------------------------------------------------------------= ---- -- a wave-pipelining component (WPC) to be linked with a series CPC (CPC) entity series_module is generic ( -- the number of clock cycles for signals to propagate through a CPC -- wave SERIES_CLOCK_NUMBER : positive :=3D 1; =20 SERIES_CLOCK_NUMBER : positive :=3D 1; =20 CLK_EDGE : std_logic :=3D '1'; -- '1': rising_edge; '0': falling_e= dge RESET_DATA : std_logic :=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic :=3D '1');-- SINI assertion data port ( =20 -- 3 clock related signals CLK : in std_logic; RESET : in std_logic; -- one of RESET/SINI is necessary, an= other is optional SINI : in std_logic; -- connect the optional to '0' INI : in std_logic :=3D '0';-- '1': initialization data; '0':= working data WE_I : in std_logic; -- '1': write enable to input registe= rs WE_O : out std_logic; -- '1': write enable to output regist= ers Valid_O : out std_logic; -- '1': data in output registers is v= alid -- info of right shift registers for assistant use=20 S_O : out unsigned(SERIES_CLOCK_NUMBER downto 0) ); end series_module; ---------------------------------------------------------------------------= ---- architecture A of series_module is signal Right_shift : unsigned(SERIES_CLOCK_NUMBER downto 0);=20 constant C_RS : unsigned(SERIES_CLOCK_NUMBER downto 0) :=3D (othe= rs=3D>'0');=20 signal Working_WE_I: std_logic; -- '1': working input data is ready =20 ---------------------------------------------------------------------------= ---- begin WE_O <=3D Right_shift(1); -- '1': latch output registers Valid_O <=3D Right_shift(0); -- '1': data at output registers is valid S_O <=3D Right_shift; -- output use is optional -- INI =3D '0': Working_WE_I <=3D WE_I; INI =3D'1': Working_WE_I <=3D '0= ' -- '1': working input data is ready Working_WE_I <=3D (not INI) and WE_I; =20 =20 ---------------------------------------------------------------------------= ---- R_With_SINI : process(CLK, RESET) begin if RESET =3D RESET_DATA then Right_shift <=3D (others =3D> '0'); =20 elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then Right_shift <=3D (others =3D> '0'); =20 -- right shift 1 position only when: -- 1. Working_WE_I =3D '1': working input data is ready -- 2. Right_shift /=3D C_RS: there is a data in wave-pipeline elsif Working_WE_I =3D '1' or Right_shift /=3D C_RS then Right_shift <=3D Working_WE_I & Right_shift(SERIES_CLOCK_NUMBER= downto 1); end if; end if; end process; =20 end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ---------------------------------------------------------------------------= ---- -- a WPC input_delay_module is linked with a series or a feedback CPC -- using this module can generate write enable signal to input registers on= every one or=20 -- more clock cycle to relaxe wave-pipelining requirements or meet feedback= requirements -- it also has series critical path and a series_module is used to latch ou= tput registers=20 entity input_delay_module is generic ( -- the number of clock cycles for signals to propagate through a CPC -- wave SERIES_CLOCK_NUMBER : positive :=3D 1; =20 SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- the number of clock cycles to accept next input data -- 1 <=3D INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER -- wave INPUT_CLOCK_NUMBER : positive :=3D 1; =20 INPUT_CLOCK_NUMBER : positive :=3D 1; =20 -- wave ONE_HOT: std_logic :=3D '0'; -- '1': use a rotator; '0': use a = counter ONE_HOT : std_logic :=3D '0'; CLK_EDGE : std_logic :=3D '1'; -- '1': rising_edge; '0': falling_= edge RESET_DATA : std_logic :=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic :=3D '1');-- SINI assertion data port ( -- 3 clock related signals CLK : in std_logic; RESET : in std_logic; -- one of RESET/SINI is necessary, a= nother is optional SINI : in std_logic; -- connect the optional to '0' INI : in std_logic :=3D '0';-- '1': initialization data; '0': = working data Ready_I : in std_logic; -- input data is ready -- advance input data properly if WE_I_O =3D '1' WE_I_O : out std_logic; -- '1': write enable to input regist= ers WE_O : out std_logic; -- '1': write enable to output regis= ters Valid_O : out std_logic; -- '1': data in output registers is = valid -- assistant info S_O : out unsigned(SERIES_CLOCK_NUMBER downto 0);--right shift= registers' output R_O : out unsigned(INPUT_CLOCK_NUMBER-1 downto 0)-- left rotat= or's output ); end input_delay_module; ---------------------------------------------------------------------------= ---- =20 architecture A of input_delay_module is -- ONE_HOT =3D '1': Left_rotator(0) =3D '1': input data is acceptable signal Left_rotator : unsigned(INPUT_CLOCK_NUMBER-1 downto 0); constant Left_rotator_Zero : unsigned(INPUT_CLOCK_NUMBER-1 downto 0) := =3D (others=3D>'0'); -- ONE_HOT =3D '0': Counter =3D 0: input data is acceptable signal Counter : integer range 0 to INPUT_CLOCK_NUMBER-1; -- '1': write enable to input registers, internal use signal WE_I : std_logic; signal Woring_Ready_I : std_logic; -- '1': new working input data= is ready =20 ---------------------------------------------------------------------------= ---- begin -- WE_I =3D '1': write enable to input registers of the linked CPC -- 1. INPUT_CLOCK_NUMBER =3D 1: there is neither rotator nor Counter, WE= _I_O <=3D Ready_I -- 2. INI =3D '1': WE_I_O <=3D Ready_I WE_I <=3D Ready_I when INPUT_CLOCK_NUMBER =3D 1 or INI =3D '1' else = =20 -- ONE_HOT =3D '1': use a left rotator -- 1. Ready_I =3D '1': input data is ready -- 2. Left_rotator(0) =3D 1: indicates that next input data is = acceptable Ready_I and Left_rotator(0) when ONE_HOT =3D '1' else -- ONE_HOT =3D '0': use a counter -- 1. Ready_I =3D '1': input data is ready -- 2. Counter =3D 0: indicates that next input data is acceptab= le Ready_I when Counter =3D 0 else '0'; =20 =20 WE_I_O<=3D WE_I; =20 -- when R_O is connected, ONE_HOT must be '1' R_O <=3D Left_rotator when ONE_HOT =3D '1' else Left_rotator_Zero; =20 -- 1. if INI =3D '1', Woring_Ready_I =3D '0'; no working input data; -- if INI =3D '0', Woring_Ready_I <=3D Ready_I, working input data is= ready Woring_Ready_I <=3D (not INI) and Ready_I; -- '1': working input data = is ready =20 ---------------------------------------------------------------------------= ---- -- the instantiation of series_module is not at the top level, needs spe= cial handling SM_1 : entity work.series_module generic map ( -- wave constant SERIES_CLOCK_NUMBER will inherit SERIES_CLOCK_NUMBER= value at top level -- for this simulation only and skip if "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, CLK_EDGE =3D> CLK_EDGE, RESET_DATA =3D> RESET_DATA, SINI_DATA =3D> SINI_DATA) port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': working d= ata WE_I =3D> WE_I, -- '1': write enable to input registers WE_O =3D> WE_O, -- '1': write enable to output registers Valid_O =3D> Valid_O, -- '1': data in output registers is valid S_O =3D> S_O -- right right shift registers' output ); =20 ---------------------------------------------------------------------------= ---- Register_With_SINI : process(CLK, RESET) begin if INPUT_CLOCK_NUMBER =3D 1 then -- there is neither Left_rotator nor= Counter -- it is empty elsif ONE_HOT =3D '1' then -- use a rotator if RESET =3D RESET_DATA then -- Left_rotator <=3D (0=3D>'1', others=3D>'0'); for J in 0 to INPUT_CLOCK_NUMBER-1 loop Left_rotator(J) <=3D '0'; end loop; Left_rotator(0) <=3D '1'; elsif CLK'event and CLK =3D CLK_EDGE then -- for input registers if SINI =3D SINI_DATA then -- Left_rotator <=3D (0=3D>'1', others=3D>'0'); for J in 0 to INPUT_CLOCK_NUMBER-1 loop Left_rotator(J) <=3D '0'; end loop; Left_rotator(0) <=3D '1'; else -- 1. Left_rotator(0) =3D '0': there is a data in feedback path -- 2. Woring_Ready_I =3D '1': working input data is ready if Left_rotator(0) =3D '0' or Woring_Ready_I =3D '1' then -- left rotate 1 bit Left_rotator <=3D Left_rotator(INPUT_CLOCK_NUMBER-2 downt= o 0) & Left_rotator(INPUT_CLOCK_NUMBER-1); end if; end if; end if; else -- use a counter if RESET =3D RESET_DATA then Counter <=3D 0; elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then Counter <=3D 0; else -- 1: Counter /=3D 0: there is a data in feedback path -- 2: Woring_Ready_I =3D '1': working input data is ready if Counter /=3D 0 or Woring_Ready_I =3D '1' then -- Counter =3D (INPUT_CLOCK_NUMBER-1): Counter reaches it= s range limit if Counter =3D (INPUT_CLOCK_NUMBER-1) then Counter <=3D 0; else Counter <=3D Counter+1; end if; end if; end if; end if; end if; =20 end process; =20 end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wave_pipeline_package.all; ---------------------------------------------------------------------------= ---- -- a WPC to be linked with multiple copied CPCs=20 -- suffix "_m" of a signal: it is a signal which has multiple sets of input= or output signals -- each of which either comes from or goes to one of multiple copied CPCs. entity multiple_copy_module1 is generic ( -- the number of clock cycles for signals to propagate through a CPC -- wave SERIES_CLOCK_NUMBER : positive :=3D 1; =20 SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- wave MULTIPLE_COPY_NUMBER: positive :=3D 1; -- the number of CPCs c= opied MULTIPLE_COPY_NUMBER : positive :=3D 1; =20 -- wave ONE_HOT : std_logic:=3D '0'; -- '1': use left rotator; '0': u= se counter ONE_HOT : std_logic:=3D '0'; DATA_OUT_WIDTH: positive :=3D 8; CLK_EDGE : std_logic:=3D '1'; -- '1': rising_edge; '0': fallin= g_edge RESET_DATA : std_logic:=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic:=3D '1'); -- SINI assertion data port ( -- 3 clock related signals CLK : in std_logic; RESET : in std_logic; -- one of RESET/SINI is necessary, ano= ther is optional SINI : in std_logic; -- connect the optional to '0' INI : in std_logic :=3D '0';-- '1': initialization data; '0= ': working data -- on every clock cycle on both s= ituations -- each assertion of following inputs/outputs lasts one clock cycle f= or each valid data Ready_I : in std_logic; -- '1': input data is ready -- VHDL-2002 : input data from each set of output registers=20 Dr_I_m : in OUT_DATA_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); = =20 -- VHDL-2008 -- Dr_I_m : in OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(DATA_OUT= _WIDTH-1 downto 0); =20 -- '1': write enable to one set of input registers=20 WE_I_O_m : out unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- '1': write enable to one set of output registers WE_O_m : out unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 D_O : out unsigned(DATA_OUT_WIDTH-1 downto 0); -- final o= utput data Valid_O : out std_logic; -- '1': da= ta at D_O is valid -- VHDL-2002, output S_O of each SM S_O_m : out OUT_SHIFT_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0) -- VHDL-2008 -- S_O_m :out OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(SERIES_CLO= CK_NUMBER downto 0) ); end multiple_copy_module1; ---------------------------------------------------------------------------= ---- architecture A of multiple_copy_module1 is -- ONE_HOT =3D '1': determine which CPC is to accept input data signal Left_rotator : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0); = =20 -- ONE_HOT =3D '0': determine which CPC is to accept input data signal Counter : integer range 0 to MULTIPLE_COPY_NUMBER-1; -- internal use, =3D WE_I_O_m signal WE_I_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- '1': output registers is valid signal Valid_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 =20 ---------------------------------------------------------------------------= ---- begin WE_I_O_m <=3D WE_I_m; =20 ---------------------------------------------------------------------------= ---- P0 : process(Ready_I, Counter, Left_rotator, Valid_m, Dr_I_m) variable V : std_logic; variable D : unsigned(DATA_OUT_WIDTH-1 downto 0); begin if MULTIPLE_COPY_NUMBER =3D 1 then -- neither Left_rotator, nor Count= er WE_I_m(0) <=3D Ready_I; -- WE_I =3D Ready_I else -- determine which of multiple copied critical paths is to accept = input data for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if ONE_HOT =3D '1' then -- use Left_rotator -- 1. Ready_I =3D '1': a valid input data is ready -- 2. Left_rotator(J) =3D '1': it's its turn to accept input= data WE_I_m(J) <=3D Ready_I and Left_rotator(J); =20 else -- use Counter -- 1. Ready_I =3D '1': a valid input data is ready -- 2. Counter =3D J: it's its turn to accept input data if Ready_I =3D '1' and Counter =3D J then WE_I_m(J) <=3D '1'; -- '1': latch input registers else =20 WE_I_m(J) <=3D '0'; end if; =20 end if; =20 end loop; end if; =20 =20 -- Valid_O <=3D Valid_m(0) or Valid_m(1) or ... V :=3D '0'; for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if Valid_m(J) =3D '1' then V :=3D V or '1'; end if; =20 end loop; =20 Valid_O <=3D V; =20 -- D_O <=3D (Valid_m(0) and D_I(0)) or (Valid_m(1) and D_I(1)) or ... D :=3D (others=3D>'0'); for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if Valid_m(J) =3D '1' then D :=3D Dr_I_m(J) or D; end if; =20 end loop; D_O <=3D D; end process; =20 ---------------------------------------------------------------------------= ---- -- change the turn bit properly P1 : process(CLK, RESET) begin if MULTIPLE_COPY_NUMBER =3D 1 then -- neither Left_rotator, nor Count= er -- empty elsif ONE_HOT =3D '1' then -- use Left_rotator if RESET =3D RESET_DATA then -- Left_rotator <=3D (Left_rotator(0) =3D> '1', others =3D> '= 0'); for J in Left_rotator'range loop Left_rotator(J) <=3D '0'; end loop; =20 Left_rotator(0) <=3D '1'; =20 elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then -- Left_rotator <=3D (Left_rotator(0) =3D> '1', others =3D= > '0'); for J in Left_rotator'range loop Left_rotator(J) <=3D '0'; end loop; =20 Left_rotator(0) <=3D '1'; -- Ready_I =3D '1': there is a valid input data and do left rot= ation once elsif Ready_I =3D '1' then -- left rotate 1 position Left_rotator <=3D Left_rotator(MULTIPLE_COPY_NUMBER-2 downto= 0) & Left_rotator(MULTIPLE_COPY_NUMBER-1); end if; end if; =20 else -- use Counter if RESET =3D RESET_DATA then Counter <=3D 0; elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then Counter <=3D 0; -- Ready_I =3D '1': there is a valid input data and increase Co= unter by 1 elsif Ready_I =3D '1' then -- Counter =3D MULTIPLE_COPY_NUMBER-1: it is time for Counte= r to turn around if Counter =3D MULTIPLE_COPY_NUMBER-1 then Counter <=3D 0; else Counter <=3D Counter+1; end if; end if; end if; end if; end process; =20 =20 ---------------------------------------------------------------------------= ---- -- call series_module for each of CPCs G0 : for J in 0 to MULTIPLE_COPY_NUMBER-1 generate -- the instantiation of series_module is not at the top level E0 : entity work.series_module generic map ( -- SERIES_CLOCK_NUMBER will inherit data from SERIES_CLOCK_NUMB= ER value at top level=20 -- for this simulation only and skip if "wave" is accepted in H= DL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, =20 CLK_EDGE =3D> CLK_EDGE, RESET_DATA =3D> RESET_DATA, SINI_DATA =3D> SINI_DATA) port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': = working data WE_I =3D> WE_I_m(J), -- write enabl to each set of inpu= t registers WE_O =3D> WE_O_m(J), -- write enable to each set of out= put registers Valid_O =3D> Valid_m(J), -- '1': data at one set of outut r= egisters is valid S_O =3D> S_O_m(J) -- SM right shift register's info ); end generate; =20 end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wave_pipeline_package.all; ---------------------------------------------------------------------------= ---- -- a WPC to be linked with multiple copied CPCs entity multiple_copy_module2 is generic ( -- wave SERIES_CLOCK_NUMBER : positive :=3D 1; =20 SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- wave MULTIPLE_COPY_NUMBER: positive :=3D 1; MULTIPLE_COPY_NUMBER : positive :=3D 1; -- wave ONE_HOT : std_logic :=3D '0'; -- '1': use left rotator; '0':= use counter ONE_HOT : std_logic :=3D '0'; DATA_OUT_WIDTH : positive :=3D 8; -- user must define his output= data width CLK_EDGE : std_logic :=3D '1'; -- '1': rising_edge; '0': fall= ing_edge RESET_DATA : std_logic :=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic :=3D '1'); -- SINI assertion data port ( -- 3 clock related signals CLK : in std_logic; RESET : in std_logic; -- one of RESET/SINI is necessary, an= other is optional SINI : in std_logic; -- connect the optional to '0' INI : in std_logic :=3D '0'; -- '1': initialization data; = '0': working data -- on every clock cycle on both= situations -- each of following inputs/outputs lasts only one clock cycle for ea= ch valid data Ready_I : in std_logic; -- '1': input data is ready -- VHDL-2002, input from each set of combinational logic outputs Dc_I_m : in OUT_DATA_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0);= =20 -- VHDL-2008 -- Dc_I_m : in OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(DATA_OUT= _WIDTH-1 downto 0); =20 -- '1': write enable to each set of input registers WE_I_O_m : out unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 D_O : out unsigned(DATA_OUT_WIDTH-1 downto 0); -- final = data output Valid_O : out std_logic; -- '1': data at D_O is valid -- VHDL-2002, output S_O of each SM S_O_m : out OUT_SHIFT_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0) -- VHDL-2008 -- S_O_m: out OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(SERIES_CLO= CK_NUMBER downto 0) ); end multiple_copy_module2; ---------------------------------------------------------------------------= ---- architecture A of multiple_copy_module2 is -- ONE_HOT =3D '1': determine which is to accept input data signal Left_rotator : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- ONE_HOT =3D '0': determine which is to accept input data signal Counter: integer range 0 to MULTIPLE_COPY_NUMBER-1; signal WE_I_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0); -- internal= use, =3D WE_I_O_m -- write enable to each set of output registers signal WE_O_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- '1': output registers is valid signal Valid_m: unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 signal D_O_in : unsigned(DATA_OUT_WIDTH-1 downto 0); -- data to output= registers signal WE_Out : std_logic; -- write enable to output registers ---------------------------------------------------------------------------= ---- begin WE_I_O_m <=3D WE_I_m; =20 ---------------------------------------------------------------------------= ---- P0 : process(Ready_I, Counter, Left_rotator, Valid_m) variable V : std_logic; begin if MULTIPLE_COPY_NUMBER =3D 1 then -- there is neither Left_rotator n= or Counter WE_I_m(0) <=3D Ready_I; -- WE_I <=3D Ready_I else -- determine which of multiple copied CPCs is to accept input data for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if ONE_HOT =3D '1' then -- use Left_rotator -- 1. Ready_I =3D '1': a valid input data is ready -- 2. Left_rotator(J) =3D '1': it's its turn to accept input= data WE_I_m(J) <=3D Ready_I and Left_rotator(J); else -- use Counter -- 1. Ready_I =3D '1': a valid input data is ready -- 2. Counter =3D J: it's its turn to accept input data if Ready_I =3D '1' and Counter =3D J then WE_I_m(J) <=3D '1'; -- '1': latch one set of input regis= ters else =20 WE_I_m(J) <=3D '0'; end if; =20 end if; =20 end loop; =20 end if; =20 =20 -- Valid_O <=3D Valid_m(0) or Valid_m(1) or ... V :=3D '0'; for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if Valid_m(J) =3D '1' then V :=3D '1'; end if; =20 end loop; =20 Valid_O <=3D V; end process; =20 ---------------------------------------------------------------------------= ---- -- call series_module for each of CPCs G0 : for J in 0 to MULTIPLE_COPY_NUMBER-1 generate -- the instantiation of series_module is not at the top level E0 : entity work.series_module generic map ( -- SERIES_CLOCK_NUMBER inherits from SERIES_CLOCK_NUMBER value = at top level=20 -- for this simulation only and skip if "wave" is accepted in H= DL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, CLK_EDGE =3D> CLK_EDGE, RESET_DATA =3D> RESET_DATA, SINI_DATA =3D> SINI_DATA) port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': = working data WE_I =3D> WE_I_m(J), -- '1': write enable to input regi= sters WE_O =3D> WE_O_m(J), -- '1': write enable to output reg= isters Valid_O =3D> Valid_m(J), -- '1': data at output registers i= s valid S_O =3D> S_O_m(J) -- SM right shift register's info ); end generate; =20 ---------------------------------------------------------------------------= ---- -- turn bit is updated if Ready_I =3D '1' P1 : process(CLK, RESET) begin if MULTIPLE_COPY_NUMBER =3D 1 then -- there is neither Left_rotator n= or Counter -- it is empty elsif ONE_HOT =3D '1' then -- use Left_rotator if RESET =3D RESET_DATA then -- Left_rotate <=3D (0 =3D> '1', others =3D> '0'); for J in Left_rotator'range loop Left_rotator(J) <=3D '0'; end loop; =20 Left_rotator(0) <=3D '1'; =20 elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then -- Right_rotate <=3D (MULTIPLE_COPY_NUMBER-1 =3D> '1', oth= ers =3D> '0'); for J in Left_rotator'range loop Left_rotator(J) <=3D '0'; end loop; =20 Left_rotator(0) <=3D '1'; -- Ready_I =3D '1': there is a valid input data and do left rot= ation once elsif Ready_I =3D '1' then -- left rotate 1 position Left_rotator <=3D Left_rotator(MULTIPLE_COPY_NUMBER-2 downto= 0)=20 & Left_rotator(MULTIPLE_COPY_NUMBER-1); end if; end if; =20 else -- use Counter if RESET =3D RESET_DATA then Counter <=3D 0; elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then Counter <=3D 0; -- Ready_I =3D '1': there is a valid input data and increase Co= unter by 1 elsif Ready_I =3D '1' then -- Counter =3D MULTIPLE_COPY_NUMBER-1: it is time for Counte= r to turn around if Counter =3D MULTIPLE_COPY_NUMBER-1 then Counter <=3D 0; else Counter <=3D Counter+1; end if; end if; end if; =20 end if; end process; =20 =20 ---------------------------------------------------------------------------= ---- -- select circuit for combinational data to output registers is optimize= d for each case P2 : process(WE_O_m, Dc_I_m) variable W : std_logic; variable Out_in: unsigned(DATA_OUT_WIDTH-1 downto 0);=20 begin W :=3D '0'; for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if WE_O_m(J) =3D '1' then W :=3D '1'; end if; =20 end loop; -- WE_Out: write enable to output registers WE_Out <=3D W; =20 case MULTIPLE_COPY_NUMBER is when 1 =3D> D_O_in <=3D Dc_I_m(0); when 2 =3D> if WE_O_m(1) =3D '1' then D_O_in <=3D Dc_I_m(1); else D_O_in <=3D Dc_I_m(0); end if; when 3 =3D> if WE_O_m(2) =3D '1' then D_O_in <=3D Dc_I_m(2); else =20 if WE_O_m(1) =3D '1' then D_O_in <=3D Dc_I_m(1); else D_O_in <=3D Dc_I_m(0); end if; end if; =20 when 4 =3D> if WE_O_m(1) =3D '1' or WE_O_m(0) =3D '1' then if WE_O_m(1) =3D '1' then D_O_in <=3D Dc_I_m(1); else D_O_in <=3D Dc_I_m(0); end if; else if WE_O_m(3) =3D '1' then D_O_in <=3D Dc_I_m(3); else D_O_in <=3D Dc_I_m(2); end if; end if; when others =3D> Out_in :=3D (others=3D>'0'); for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if WE_O_m(J) =3D '1' then Out_in :=3D Out_in or Dc_I_m(J); end if; end loop; D_O_in <=3D Out_in; end case; end process; =20 =20 ---------------------------------------------------------------------------= ---- -- combinational logic data D_O_in is clocked in D_O P3 : process(CLK) begin if CLK'event and CLK =3D CLK_EDGE then if WE_Out =3D '1' then D_O <=3D D_O_in; end if; end if; end process; end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wave_pipeline_package.all; -- to be connected with a WPC series_module, input_delay_module or multiple= _copy_module1 -- its output comes from the output registers entity CPC1 is generic ( -- to simulate the variable combinational logic length SERIES_CLOCK_NUMBER : positive :=3D SERIES_CLOCK_NUMBER; =20 -- following parameters are used only for this simulation, or optiona= l otherwise DATA_IN_WIDTH : positive :=3D DATA_IN_WIDTH; -- data in width DATA_OUT_WIDTH : positive :=3D DATA_OUT_WIDTH; -- data out width CLK_EDGE : std_logic :=3D '1'; -- '1': rising_edge; '0': falli= ng_edge RESET_DATA : std_logic :=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic :=3D '1'); -- SINI assertion data port ( CLK : in std_logic; -- any number of input/output signals c= an be here=20 R_O_I : in std_logic :=3D '1'; -- 1: D_O is registers output; 0: com= binatinal output INI : in std_logic; -- '1': initialization data; '0': worki= ng data WE_I : in std_logic; -- '1': write enable to input registers= of a CPC D_I : in unsigned(DATA_IN_WIDTH-1 downto 0); -- input data WE_O_I : in std_logic; -- '1': write enable to output registers = of a CPC D_O : out unsigned(DATA_OUT_WIDTH-1 downto 0) -- output registers'= data ); end CPC1; ---------------------------------------------------------------------------= ---- architecture A of CPC1 is type IN_DATA_ARRAY is array(natural range <>) of unsigned(DATA_IN_WIDTH-= 1 downto 0); -- array of internal registers, total =3D SERIES_CLOCK_NUMBER -- reflecting the number of series clock cycles signal R_I : IN_DATA_ARRAY(SERIES_CLOCK_NUMBER-1 downto 0); = =20 signal R_Out : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output regist= ers ---------------------------------------------------------------------------= ---- begin -- D_O comes from output registers R_Out if R_O_I =3D '1' -- or from combinational output R_I(0) otherwise D_O <=3D R_Out when R_O_I =3D '1' else R_I(0); =20 P0 : process(CLK) begin if CLK'event and CLK =3D CLK_EDGE then if INI =3D '1' then -- for loading initialization simulation -- when INI =3D '1' and WE_I =3D '1',=20 -- input data will be latched into input registers if WE_I =3D '1' then R_I(SERIES_CLOCK_NUMBER-1) <=3D D_I; end if; =20 -- for working simulation elsif SERIES_CLOCK_NUMBER =3D 1 then -- when SERIES_CLOCK_NUMBER =3D '1' and WE_I =3D '1',=20 -- input data will be latched into input registers if WE_I =3D '1' then R_I(0) <=3D D_I; end if; =20 elsif WE_I =3D '1' then -- right shift if there is a new input data R_I <=3D D_I & R_I(SERIES_CLOCK_NUMBER-1 downto 1); else =20 -- extend the most recent input data to right R_I <=3D R_I(SERIES_CLOCK_NUMBER-1) & R_I(SERIES_CLOCK_NUMBER-1= downto 1); end if; -- WE_O_I =3D '1': write enable signal to output registers if WE_O_I =3D '1' then R_Out <=3D R_I(0); end if; =20 end if; =20 end process; end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wave_pipeline_package.all; ---------------------------------------------------------------------------= ---- entity WPC_CPC_TEST is end WPC_CPC_TEST; architecture A of WPC_CPC_TEST is ---------------------------------------------------------------------------= ---- signal CLK : std_logic; signal RESET : std_logic; signal SINI : std_logic; signal ClockSerial: unsigned(9 downto 0); -- for series_module testing signal se_Ready_I : std_logic; -- '1': se_D_I is ready signal se_WE_O : std_logic; -- write enable to output registers signal se_D_I : unsigned(DATA_IN_WIDTH-1 downto 0); -- new input = data signal se_D_O : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output dat= a signal se_Valid_O : std_logic; -- '1': output data at se_D_O is vali= d signal se_S_O : unsigned(SERIES_CLOCK_NUMBER downto 0); -- right= shiftor -- if wave constant mechanism is accepted in HDL=20 -- wave constant New_series: positive :=3D series_clk_number; -- signal se_S_O : unsigned(New_series downto 0); -- right shif= tor =20 -- for input_delay_module testing signal fb_Ready_I : std_logic; -- '1': input data at fb_D_I is ready signal fb_WE_I_O : std_logic; -- write enable to input register signal fb_WE_O : std_logic; -- write enable to outut registers signal fb_D_I : unsigned(DATA_IN_WIDTH-1 downto 0); -- new input = data signal fb_D_O : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output dat= a signal fb_Valid_O : std_logic; -- '1': output data at fb_D_O is vali= d signal fb_S_O : unsigned(SERIES_CLOCK_NUMBER downto 0); -- right s= hiftor -- if wave constant mechanism is accepted in HDL; an alien wave constant= declaration -- wave constant fb_series_name: positive :=3D series_clk_number;=20 -- signal fb_S_O : unsigned(fb_series_name downto 0); -- left rota= tor signal fb_R_O : unsigned(INPUT_CLOCK_NUMBER-1 downto 0);-- left ro= tator -- if wave constant mechanism is accepted in HDL -- wave fb_input_name: positive :=3D input_clk_number; -- an alien wave con= stant declaration -- signal fb_R_O : unsigned(fb_input_name-1 downto 0); -- left rota= tor =20 -- for duplciate_module1 testing signal D_I : unsigned(DATA_IN_WIDTH-1 downto 0); -- new input= data signal Ready_I : std_logic; -- data at D= _I is ready -- output data from each set of output registers of CPCs -- for VHDL-2002 signal Dr_O_m : OUT_DATA_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); -- for VHDL-2008 -- signal Dr_O_m:OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(DATA_OUT= _WIDTH-1 downto 0); signal D_O : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output da= ta -- '1': write enable to each of input registers signal WE_I_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- '1': write enable to each of output registers signal WE_O_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0); signal Valid_O : std_logic; -- data at D_O is valid -- for VHDL-2002 only signal Shift_Array: OUT_SHIFT_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); = =20 -- for VHDL-2008 and if wave constant mechanism is accepted in HDL -- wave Series_name : positive :=3D SERIES_CLOCK_NUMBER; -- an alien wave= constant declaration -- wave Multiple_name: positive :=3D MULTIPLE_COPY_NUMBER; -- an alien wave= constant declaration -- signal Shift_Array: OUT_DATA_ARRAY_8(Multiple_name-1 downto 0)(Series_= name downto 0); -- for duplciate_module2 testing signal D_I2 : unsigned(DATA_IN_WIDTH-1 downto 0); -- new input = data signal Ready_I2 : std_logic; -- '1': D_I2 = is ready -- VHDL_2002, output data from combinational logic of each of CPCs signal Dc_O_m2 : OUT_DATA_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); -- for VHDL-2008 -- signal Dc_O_m2:OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(DATA_OU= T_WIDTH-1 downto 0); signal D_O2 : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output dat= a -- '1': write enable to each of input registers signal WE_I_m2 : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 signal Valid_O2 : std_logic; -- output data at D_O2 is valid -- for VHDL-2002 only signal Shift_Array2: OUT_SHIFT_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); =20 -- for VHDL-2008 and if wave constant mechanism is accepted in HDL -- wave Series_name2 : positive :=3D SERIES_CLOCK_NUMBER; -- an alien wave= constant declaration -- wave Multiple_name2: positive :=3D MULTIPLE_COPY_NUMBER;-- an alien wave= constant declaration -- signal Shift_Array2 : OUT_DATA_ARRAY_8(Multiple_name2-1 downto 0)(Seri= es_name2 downto 0); ---------------------------------------------------------------------------= ---- begin RESET <=3D '1', '0' after 4 ns; MainClock : process begin CLK <=3D '1'; wait for 5 ns; CLK <=3D '0'; wait for 5 ns; end process; =20 Ready_I2 <=3D Ready_I; D_I2 <=3D D_I; =20 assert (INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER) -- report if fals= e report "It should be INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER" severity failure; =20 assert (MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER) -- report if fals= e report "It should be MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER" severity failure; =20 ---------------------------------------------------------------------------= ---- -- CLK_EDGE, RESET_DATA and SINI_DATA are not tested here for simplicity GenerateInput : process(RESET, CLK) begin if RESET =3D '1' then ClockSerial <=3D (others=3D>'0'); SINI <=3D '1'; se_Ready_I <=3D '0'; se_D_I <=3D (0=3D>'1', others=3D>'0'); fb_Ready_I <=3D '0'; fb_D_I <=3D (0=3D>'1', others=3D>'0'); Ready_I <=3D '0'; D_I <=3D (0=3D>'1', others=3D>'0'); elsif CLK'event and CLK =3D '1' then SINI <=3D RESET; ClockSerial <=3D ClockSerial + 1; -- for series_module testing if ClockSerial(2 downto 0) /=3D "110" and ClockSerial(2 downto 0) = /=3D "001" then -- if ClockSerial(3 downto 0) =3D "1000" then -- if ClockSerial(0) /=3D '1' then -- if ClockSerial >=3D 2 then se_Ready_I <=3D '1'; else se_Ready_I <=3D '0'; end if; =20 =20 if se_Ready_I =3D '1' then if se_D_I =3D 9 then -- D_I has 1 digit se_D_I <=3D (others=3D>'0'); else se_D_I <=3D se_D_I+1; end if; =20 end if; =20 ---------------------------------------------------------------------------= ---- -- for input_delay_module testing -- if ClockSerial(2 downto 0) /=3D "110" and ClockSerial(2 downto 0) = /=3D "001" then -- if ClockSerial(3 downto 0) =3D "1000" then -- if ClockSerial(1 downto 0) /=3D "11" then -- if ClockSerial >=3D 2 then if (ClockSerial mod 5) /=3D 0 then fb_Ready_I <=3D '1'; else fb_Ready_I <=3D '0'; end if; =20 =20 if fb_WE_I_O =3D '1' then if fb_D_I =3D 9 then -- D_I has 1 digit fb_D_I <=3D (others=3D>'0'); else fb_D_I <=3D fb_D_I+1; end if; =20 end if; =20 ---------------------------------------------------------------------------= ---- -- for multiple_copy_module1/multiple_copy_module2 testing if ClockSerial(2 downto 0) /=3D "110" and ClockSerial(2 downto 0) = /=3D "001" then -- if ClockSerial(3 downto 0) /=3D "1000" then -- if ClockSerial(0) =3D '1' then -- if ClockSerial >=3D 2 then Ready_I <=3D '1'; else Ready_I <=3D '0'; end if; =20 =20 if Ready_I =3D '1' then if D_I =3D 9 then -- D_I has 1 digit D_I <=3D (others=3D>'0'); else D_I <=3D D_I+1; end if; =20 end if; end if; end process; =20 ---------------------------------------------------------------------------= ---- -- if it is accepted in HDL, add link1 statement -- to establish links between series_module and CPC1 -- link1(critical_A, CPC10, New_series); =20 critical_A : entity work.series_module=20 generic map ( -- for this simulation only and skip after "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER) =20 port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initializaton data; '0': working d= ata WE_I =3D> se_Ready_I, -- data is ready to critical paths WE_O =3D> se_WE_O, -- '1': write enable to output registers Valid_O=3D> se_Valid_O, -- '1': data at se_D_O is valid=20 S_O =3D> se_S_O -- shift regiters info ); CPC10 : entity work.CPC1 port map ( CLK =3D> CLK, =20 INI =3D> INI, -- '1': initializaton data; '0': working d= ata; optional WE_I =3D> se_Ready_I, -- 1. write enable to input registers D_I =3D> se_D_I, -- not related to series_module WE_O_I =3D> se_WE_O, -- 2. new write enable to output registers= =20 D_O =3D> se_D_O -- not related to series_module ); =20 ---------------------------------------------------------------------------= ---- =20 -- if it is accepted in HDL, add link2 statement -- establish links among input_delay_module, fb_user_module, fb_series_name= and fb_input_name -- link2(Feedback_A, fb_user_module1, fb_series_name, fb_input_name); Feedback_A : entity work.input_delay_module generic map ( -- for this simulation only and skip after "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, =20 INPUT_CLOCK_NUMBER =3D> INPUT_CLOCK_NUMBER, ONE_HOT =3D> ONE_HOT) port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initializaton data; '0': working d= ata; optional Ready_I =3D> fb_Ready_I, -- data is ready to write into input regis= ters WE_I_O =3D> fb_WE_I_O, -- '1': write enable to input registers WE_O =3D> fb_WE_O, -- '1': write enable to output registers Valid_O =3D> fb_Valid_O, -- data at output registers is valid S_O =3D> fb_S_O, R_O =3D> fb_R_O ); =20 -- after a feedback_user_module linked with a input_delay_module it beha= ves as normal -- critical path module, but one input data is accepted per INPUT_CLOCK_= NUMBER clock cycles=20 -- and no wave-pipelining can be used through the feedback path=20 fb_user_module1 : entity work.CPC1 port map ( CLK =3D> CLK, =20 INI =3D> INI, -- '1': initializaton data; '0': working d= ata; optional WE_I =3D> fb_WE_I_O, -- 1. write enable to input registers D_I =3D> fb_D_I, -- not related to input_delay_module WE_O_I =3D> fb_WE_O, -- 2. new write enable to output registers= =20 D_O =3D> fb_D_O -- not related to input_delay_module ); =20 ---------------------------------------------------------------------------= ---- =20 -- if it is accepted in HDL, add link3 statement to establish links among -- multiple_copy_module1, multiple copied CPCs and their linked alien wave = constants -- link3(multiple_A, G0, user_module0, Multiple_name, Series_name);=20 multiple_A : entity work.multiple_copy_module1 generic map ( -- for this simulation only and skip after "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, MULTIPLE_COPY_NUMBER =3D> MULTIPLE_COPY_NUMBER, ONE_HOT =3D> ONE_HOT, DATA_OUT_WIDTH =3D> DATA_OUT_WIDTH)-- it is necessary if width is dif= ferent from default port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': working = data Ready_I =3D> Ready_I, -- data is ready for the critical path Dr_I_m =3D> Dr_O_m, -- 1. data from each of output registers WE_I_O_m =3D> WE_I_m, -- 2. write enable to each of input regist= ers WE_O_m =3D> WE_O_m, -- 3. write enable to each of output regis= ters D_O =3D> D_O, -- output data from multiple copied critic= al paths Valid_O =3D> Valid_O, -- '1': data at D_O is valid=20 S_O_m =3D> Shift_Array -- right shiftor's array ); -- user provides his own CPC1 with or without a feedback -- 1 <=3D MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER -- MULTIPLE_COPY_NUMBER gets its proper value through link3() and multip= le_A G0 : for J in 0 to MULTIPLE_COPY_NUMBER-1 generate =20 user_module0 : entity work.CPC1 port map ( CLK =3D> CLK, =20 INI =3D> INI, -- '1': initialization data; '0': working = data; optional WE_I =3D> WE_I_m(J), -- 2. write enable to input registers D_I =3D> D_I, -- each has the same data input WE_O_I =3D> WE_O_m(J), -- 3. new write enable to output registers= =20 D_O =3D> Dr_O_m(J) -- 1. each has its own output data ); end generate; =20 ---------------------------------------------------------------------------= ---- -- if it is accepted in HDL, add link3 statement to establish links among -- multiple_copy_module2, multiple copied CPCs and their alien wave constan= ts -- link3(multiple2_A, G2, user_module20, Multiple_name2, Series_name2); multiple2_A : entity work.multiple_copy_module2 generic map ( -- for this simulation only and skip after "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, =20 MULTIPLE_COPY_NUMBER =3D> MULTIPLE_COPY_NUMBER, ONE_HOT =3D> ONE_HOT, DATA_OUT_WIDTH =3D> DATA_OUT_WIDTH)-- it is necessary if width is dif= ferent from default port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': working = data Ready_I =3D> Ready_I2, -- data is ready to critical paths Dc_I_m =3D> Dc_O_m2, -- 1. combinational logic input to each of= output registers WE_I_O_m =3D> WE_I_m2, -- 2. write enable to each of input regist= ers D_O =3D> D_O2, -- output data from multiple copied critic= al paths Valid_O =3D> Valid_O2, -- '1': data at D_O is valid=20 S_O_m =3D> Shift_Array2-- info of right shiftors=20 ); -- user provides his own CPC1 with or without a feedback -- 1 <=3D MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER -- MULTIPLE_COPY_NUMBER gets its proper value through link3() and multip= le_A G2 : for J in 0 to MULTIPLE_COPY_NUMBER-1 generate =20 user_module20 : entity work.CPC1 port map ( CLK =3D> CLK, =20 R_O_I =3D> '0', -- output D_O comes from combinatinal logi= c INI =3D> INI, -- '1': initializaton data; '0': working d= ata WE_I =3D> WE_I_m2(J), -- 2. write enable to input registers D_I =3D> D_I2, -- each has the same data input WE_O_I =3D> '0', -- its output registers will be optimized = out D_O =3D> Dc_O_m2(J) -- 1. each has its own output data ); end generate; ---------------------------------------------------------------------------= ---- =20 end A; From newsfish@newsfish Thu Aug 1 00:32:51 2024 X-Received: by 10.66.102.66 with SMTP id fm2mr7123360pab.4.1427231058600; Tue, 24 Mar 2015 14:04:18 -0700 (PDT) X-Received: by 10.140.83.165 with SMTP id j34mr105308qgd.8.1427231058552; Tue, 24 Mar 2015 14:04:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!z20no2938151igj.0!news-out.google.com!q90ni527qgd.1!nntp.google.com!h3no4602594qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Mar 2015 14:04:17 -0700 (PDT) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.49.104.28; posting-account=9GnU7goAAAAHU53ujXD8Ejd5wZPBXz8p NNTP-Posting-Host: 50.49.104.28 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: Derek Simmons Injection-Date: Tue, 24 Mar 2015 21:04:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3654 If somebody tells me that they are going to school to become a doctor, I co= ngratulate tham and ask them if they have an area of interest. You haven't = told us what or area of interest or what you intend on using it for. So, in= the vein of a column in my favorite guitar magazine titled, "What strings = do you use?," I have answered,"What VHDL and computer design books are on y= our bookshelf." There are a lot of books here but I have gotten rid of a lot more and these= are the ones I've held onto. VHDL LANGUAGE TEXTS Pong P. Chu, "RTL Hardware Design Using VHDL: Coding for Efficiency, Portab= ility, and Scalability," ISBN: 0-471-72092-5. This is my preferred text at = the moment but the big sore spot is its price tag. The information is up to= date. I really liked the chapters Register Transfer Methodology and I foun= d them invaluable in implementing a vector-matrice math processor. [NOTE: A= t one time somebody announced in this group the public release of a library= of vector and matrice primitives. Sure enough, somebody grab the library a= nd did a literal implementation of their algorithm. They came back and bash= ed the library because they ran out of resources. If I was their boss I wou= ld be embarassed and considered sending them on an unpaid sabbatical to lea= rn VHDL and resource sharing.] Peter J. Ashenden, "The designer's Guide to VHDL," ISBN: 1-55860-270-4. Thi= s the text I really learned VHDL from. I made two passes at reading and doi= ng the exercises. The exercises in the text are given a difficulty level of= 1 to 4. On the first pass I did the problems with difficulty rating of 1 t= o 3. On the second pass I created test benches to demonstrate the solutions= and I did the level 4 problems. My favorite problem to talk about is at th= e end of Chapter 14, "Generate Statements", problem 14. The problem ask you= to create a hypercube multicomputer. The solution allows you to paramteriz= e the number of nodes. Each node is made up of a router and a processing el= ement. The router would pass a packet from a node to its destination node f= ollowing a specific set of rules. When it reached its destination the proce= ssor I created would create a new destination node. My test bench showed th= at it could systematically pass the packet to each node. Then I should each= node could route a packet from one node to each of the others. And, finall= y I showed it could route using each of the links between nodes. It makes f= or interesting discussions at job interviews. Sundar Rajan, "Essential VHDL: RTL Synthesis Done Right," ISBN:0-9669590-0-= 0. This book is a fast pace introduction to VHDL and really interesting exa= mples. I would recommend this to somebody that is faced with a small to med= ium size project but also would recommend that they have a copy of CHU's or= ASHENDEN's for a more indepth coverage of material. Peter Wilson, "Design Recipes for FPGAs," ISBN: 978-0-7506-6845-3. I wouldn= 't say they are good examples but I found it useful in solving writers bloc= k. Nothing is more frustrating then trying to do something and you can see = the solution in your head but can connect it with how to implement it. Some= times paging through this I see something related or even unrelated then al= l the peices of the problem I'm trying to solve fall into place. Douglas J. Smith, "HDL Chip Design: A Practical Guide for Designing, Synthe= sizing and Simulating ASICs and FPGAs using VHDl or Verilog," ISBN: 0-96519= 34-3-8. I include this only as an honorable mention because it was a highly= respected text but as VHDL as evolved it has become dated. Some engineers = still cling to it. If somebody referes to the blue book or a blue book, thi= s is the book they referring to. If you can borrow a copy its worth looking= through. I keep my copy because the typography, layout and organization ma= ke it easy to read.=20 ADVANCED VHDL TEXTS Steve Kilts, "Advanced FPGA Design: Architecture, Implementation, and Optim= ization," ISBN: 970-0-470-05437-6. An advance practices text. It guides the= reader through solving more difficult design issues that are more system r= elated then VHDL related. Jean-Pierre Deschamps, G=E9ry Jean Antoine Bioul and Gustavo D. Sutter, "Sy= nthesis of Arithemtaic Circuits: FPGA, ASIC, and Embedded Systems," ISBN: 0= -471-68783-9. The problems I'm normally faced with are math oriented or hea= vily math dependent. There is VHDL code on the author's website for the exa= mples in the text. Charles H. Roth, Jr., "Digital Systems Design Using VHDL," ISBN: 0-534-9509= 9-X. This book is dated. It was from the period of when PCs had 486's for p= rocessors. I liked the examples and exercises. I don't recommend it but if = you find a copy I think its worth your time to page through to see if anyth= ing sparks your interest. The reason I keep it is because it has design exa= mples for UART and floating point multiplier.=20 OTHER Clive "Max" Maxfield, "The Design Warrior's Guide to FPGA's: Devices, Tools= and Flows," ISBN: 0-7506-7604-3. If you are working in industry or a stude= nt you should read this at least once. If you take to heart the topics it c= overs will give your work the WOW factor. When you are writing your design = and engineering documents and you're 2/3 of the way through it, page throug= h this book to see if you are missing anything or you can add something mor= e. If you do that, someday somebody is going to say "Wow, I didn't think of= that!" It talks about all that other stuff that isn't part of coding but i= s just as important, like design flow, reusability, intellectual property, = ect. Wim Vanderbauwhede and Khaled Benkrid, "High-Performance Computing Using FP= GAs," ISBN: 978-1-4614-1790-3. My area of interest is in accelerating appl= ications. So, this book would be of particular interest for my objectives.= =20 COMPUTER ARCHITECTURE Kai Hwang, "Advanced Computer Architecture: Parallelism, Scalability, Progr= ammability," ISBN: 0-07-031622-8. This is a basic computer architecture boo= k. As architects study buildings and arcitecture I think more of an emphasi= s should be given to studying computer systems and computer architecture. Kai Hwang, "Computer Arithmetic: Principles, Architecture, and Design," ISB= N: 0-471-03496-7. This book has case studies on how arithematic functions a= nd pipelines were implemented in computer systems when both processor and m= emory were expensive. I didn't copy it but reading the sections on the TI A= SC gave me my eureka moment for my vector-matrice processor. The TI ASC had= a scalable SIMD architecture. It could be purchased with 1 to 4 math pipes= . Kai Hwang and Fay=E9 A. Briggs, "Computer Architecture and Parallel Process= ing," ISBN: 0-07-031556-6. Were as Hwang's first text was a first semester = text this would be the second semester text for a course study in computer = design and architecture. This book describes the processor architecture of = parallel processors and super computers. More information on the TI ASC and= CDC Star-100.=20 Israel Koren, "Computer Arithmetic Algorithms," ISBN: 1-56881-160-8. The 20= years apart that this book was published from Kai's there isn't a big diff= erence in material and it makes you wonder is Kai was a head of his time or= has so little really changed.=20 From newsfish@newsfish Thu Aug 1 00:32:52 2024 X-Received: by 10.43.16.70 with SMTP id px6mr29320179icb.28.1427250244689; Tue, 24 Mar 2015 19:24:04 -0700 (PDT) X-Received: by 10.182.24.5 with SMTP id q5mr67425obf.30.1427250244629; Tue, 24 Mar 2015 19:24:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no4553618igj.0!news-out.google.com!db6ni62281igc.0!nntp.google.com!z20no4553609igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Mar 2015 19:24:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:ac9e:4260:1157:ae24; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:ac9e:4260:1157:ae24 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Wed, 25 Mar 2015 02:24:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3655 On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote: > > Here I publish all source code for public confirmation. > What exactly would you like the public to confirm? Do you have made some specific claims? Given that you have not claimed anything specific, I can only confirm the following: - It does compile (Modelsim 10.3c) - It does synthesize to something (Quartus 14.0; Top level entity=CPC1; 56 Max II logic elements) > > You may copy this part of code to do simulation by yourself. > Why would I want to simulate it? Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:52 2024 X-Received: by 10.66.226.46 with SMTP id rp14mr10030195pac.0.1427280328169; Wed, 25 Mar 2015 03:45:28 -0700 (PDT) X-Received: by 10.50.148.98 with SMTP id tr2mr384017igb.3.1427280328111; Wed, 25 Mar 2015 03:45:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z20no4718019igj.0!news-out.google.com!db6ni62798igc.0!nntp.google.com!z20no4718014igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Mar 2015 03:45:27 -0700 (PDT) In-Reply-To: <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.125.115.98; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.125.115.98 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Daniel Kho Injection-Date: Wed, 25 Mar 2015 10:45:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 11 Xref: news.eternal-september.org comp.lang.vhdl:3656 On Friday, 6 March 2015 02:14:05 UTC+8, Weng Tianxiang wrote: > Here is an example that MIT has 4 patents for HDTV and now it is suing a Japanese HDTV manufacturer. > > MIT Sues Funai Over 4 HDTV Patents > http://www.law360.com/articles/342212/mit-sues-funai-over-4-hdtv-patents > > Weng > The Japanese manufacturer is not a standard body. What was said earlier was that no standard body would want to be burgeoned by patents, IEEE included. -dan From newsfish@newsfish Thu Aug 1 00:32:52 2024 X-Received: by 10.182.65.37 with SMTP id u5mr10319634obs.27.1427281398834; Wed, 25 Mar 2015 04:03:18 -0700 (PDT) X-Received: by 10.50.1.113 with SMTP id 17mr386646igl.8.1427281398774; Wed, 25 Mar 2015 04:03:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed4a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z20no3100390igj.0!news-out.google.com!db6ni62798igc.0!nntp.google.com!z20no4726539igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Mar 2015 04:03:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.125.115.98; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.125.115.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: NCVHDL VHDL-2008 support? From: Daniel Kho Injection-Date: Wed, 25 Mar 2015 11:03:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 12 Xref: news.eternal-september.org comp.lang.vhdl:3657 Hi all, I was thinking if I should be trying ncsim/ncvhdl, but before I do that, I'= d like to hear from those of you who have used the tool regarding its suppo= rt on VHDL-2008 features. There isn't much information with a Google search= , so I thought I'd ask a question here. Also, hopefully the simulator complies strictly with the older versions of = VHDL. I am using a simulator which does NOT report errors when I am driving= an unresolved net with multiple sources, which is not legal in VHDL. Hopef= ully, ncsim can do better than that. Best regards, Daniel From newsfish@newsfish Thu Aug 1 00:32:53 2024 X-Received: by 10.182.44.199 with SMTP id g7mr4636789obm.11.1427303040208; Wed, 25 Mar 2015 10:04:00 -0700 (PDT) X-Received: by 10.182.247.39 with SMTP id yb7mr108281obc.36.1427303040135; Wed, 25 Mar 2015 10:04:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no3207659igj.0!news-out.google.com!qk8ni67122igc.0!nntp.google.com!z20no3207658igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Mar 2015 10:03:59 -0700 (PDT) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.179.30.93; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.179.30.93 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: bknpk@hotmail.com Injection-Date: Wed, 25 Mar 2015 17:04:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3658 On Friday, January 9, 2015 at 3:09:03 PM UTC+2, johan.fa...@gmail.com wrote= : > a month ago I decided that I was lacking FPGA knowhow, said and done I or= dered an experiment board (beeing an opensource aficionado I ordered the Lo= gicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's= "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Exam= ples: Spartan 3". My reasoning behind these two books is that I start with = Ashenden to learn the whole language then go to Pong to learn how to write = syntezisable VHDL, since both contain exercises they make for really good s= elf teaching material. I know Pong is targeting another experiment board bu= t it's the same FPGA and im very confident I can myself make adjustments, e= xcept for e.g. the PS2 port which my papilio thankfully does not have. >=20 > I have now started to search for what to do after these books, how do I g= et more advanced in my FPGA knowledge. I'm a software guy and if I got the = question "I want to start programming" from someone new to programming I wo= uld recomend a good starting book in python, then a good book on how to do = test driven design, then a book about patterns, then moving to C followed b= y a book about object oriented design, then perhaps going for a best practi= ce book and so on, by level of complexity and relevance. I have scoured the= internet (or feels like it) to find such a list regarding FPGA, but at no = luck so far, so thinking of posting the question here. >=20 > I have looked at three books for continued learning after I'm finished wi= th Pong >=20 > Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aim= ed at explaining deeper the differences beetwen syntezisable and simulated = VHDL. Though it seem to go through the VHDL language constructs yet again p= erhaps it is too much overlapping with Pong and Ashenden >=20 > Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; se= ems a good continuation, I understand that FSM is a very important topic in= HW world and that they are completely different from SW FSM, also it seem = to have excersises after each chapter which is good. >=20 > Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portabi= lity, and Scalability ; seems good, no more comments. >=20 > Thats my thinking, any suggestions or comments? Have not come about any b= ooks regarding FPGA testing? Perhaps I should look outside the more hands o= n book to one of the "meta" books out there? May I recommend an IP stack implemented in FPGA. It was simulated using the= free VHDL simulator: GHDL. It was synthesized using xilinx free tool and s= imulated again with post NGD net-list. All scripts and explanations are at: http://bknpk.ddns.net/my_web/IP_STACK/start_1.html From newsfish@newsfish Thu Aug 1 00:32:53 2024 X-Received: by 10.66.249.99 with SMTP id yt3mr16920036pac.13.1427448090192; Fri, 27 Mar 2015 02:21:30 -0700 (PDT) X-Received: by 10.140.91.118 with SMTP id y109mr75871qgd.39.1427448090069; Fri, 27 Mar 2015 02:21:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no238247igj.0!news-out.google.com!q90ni531qgd.1!nntp.google.com!h3no5129392qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Mar 2015 02:21:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Subject: Quad SPI FLASH memory problems From: niv Injection-Date: Fri, 27 Mar 2015 09:21:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3659 Has anyone tried the Spansion s25fl series of FLASH memories with Quad SPI = interface? I've downloaded their VHDL model, but can't get it to talk. I've written s= ome very simple code to read a few addresses using just single SPI mode, bu= t I get nothing back, and all looks OK in the wave view for the read cycle = (command X"03"). I can see my initialisation data correct in the FLASH arr= ay, but just can't get the model to work, (or create an SDF file with their= tools)! Has anyone had any luck with this model? (I've used an s29... FLASH succes= sful in the past, but that's standard FLASH with addr & data busses etc). Any hints/help welcome. From newsfish@newsfish Thu Aug 1 00:32:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Quad SPI FLASH memory problems Date: Fri, 27 Mar 2015 08:21:42 -0400 Organization: Alacron, Inc. Lines: 14 Message-ID: References: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 27 Mar 2015 12:22:48 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="32192"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+VgmKBkLIJyAZ6JorZB5+gwc+Ey0F4KPs=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Cancel-Lock: sha1:d1aWXt/orD1zVcs5M0Kw/N6j3ro= Xref: news.eternal-september.org comp.lang.vhdl:3660 niv wrote: > Has anyone tried the Spansion s25fl series of FLASH memories with Quad SPI interface? > I've downloaded their VHDL model, but can't get it to talk. I've written some very simple code to read a few addresses using just single SPI mode, but I get nothing back, and all looks OK in the wave view for the read cycle (command X"03"). I can see my initialisation data correct in the FLASH array, but just can't get the model to work, (or create an SDF file with their tools)! > Has anyone had any luck with this model? (I've used an s29... FLASH successful in the past, but that's standard FLASH with addr & data busses etc). > Any hints/help welcome. What are you seeing on the data output? Is it "X" or "U"? Usually the models for these parts allow you to define the contents of the flash memory cells, but it's possible that they start up undefined by default if your model doesn't write them first. -- Gabor From newsfish@newsfish Thu Aug 1 00:32:53 2024 X-Received: by 10.68.168.99 with SMTP id zv3mr23109884pbb.6.1427482677600; Fri, 27 Mar 2015 11:57:57 -0700 (PDT) X-Received: by 10.140.39.148 with SMTP id v20mr336369qgv.24.1427482677512; Fri, 27 Mar 2015 11:57:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!z20no708500igj.0!news-out.google.com!q90ni531qgd.1!nntp.google.com!h3no5242316qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Mar 2015 11:57:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1badbaa6-9e1c-4d26-977a-76ec78e08a12@googlegroups.com> Subject: Re: Quad SPI FLASH memory problems From: niv Injection-Date: Fri, 27 Mar 2015 18:57:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3661 I have initialised the memory, I can see the values in the array after "running" for 0 ps. However, the output of the memory on the SPI line remains at 'H', not the data value(s) I'm expecting when reading. From newsfish@newsfish Thu Aug 1 00:32:54 2024 X-Received: by 10.68.209.164 with SMTP id mn4mr26725055pbc.8.1427541394673; Sat, 28 Mar 2015 04:16:34 -0700 (PDT) X-Received: by 10.50.35.162 with SMTP id i2mr58124igj.4.1427541394637; Sat, 28 Mar 2015 04:16:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no249484igd.0!news-out.google.com!db6ni128igc.0!nntp.google.com!h15no133915igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Mar 2015 04:16:33 -0700 (PDT) In-Reply-To: <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 28 Mar 2015 11:16:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3662 On Wednesday, March 25, 2015 at 3:45:34 AM UTC-7, Daniel Kho wrote: > On Friday, 6 March 2015 02:14:05 UTC+8, Weng Tianxiang wrote: > > Here is an example that MIT has 4 patents for HDTV and now it is suing a Japanese HDTV manufacturer. > > > > MIT Sues Funai Over 4 HDTV Patents > > http://www.law360.com/articles/342212/mit-sues-funai-over-4-hdtv-patents > > > > Weng > > > > The Japanese manufacturer is not a standard body. What was said earlier was that no standard body would want to be burgeoned by patents, IEEE included. > > -dan -dan, It is too simple and naive to think a patent holder should relinquish its patent rights to let their patents to be part of an international standard. Here is a Wikipedia website for your reference on how international standard body works. http://en.wikipedia.org/wiki/3GPP Here is a news about standard-essential patents: ITU to address surge in litigation over standards-essential patents: http://www.computerworld.com/article/2505517/technology-law-regulation/itu--to-address-surge-in-litigation-over-standards-essential-patents.html Another related news about standards patents: Nokia, HP, Verizon back FTC against import bans over standards patents: http://www.computerworld.com/article/2504127/technology-law-regulation/nokia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions. Weng From newsfish@newsfish Thu Aug 1 00:32:54 2024 X-Received: by 10.70.90.4 with SMTP id bs4mr28355054pdb.7.1427563760623; Sat, 28 Mar 2015 10:29:20 -0700 (PDT) X-Received: by 10.140.25.233 with SMTP id 96mr176582qgt.26.1427563760358; Sat, 28 Mar 2015 10:29:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no397503igd.0!news-out.google.com!q90ni548qgd.1!nntp.google.com!z60no153395qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Mar 2015 10:29:20 -0700 (PDT) In-Reply-To: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.179.30.93; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.179.30.93 References: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e18c445-37bc-4a72-89fe-c02ac04a0402@googlegroups.com> Subject: Re: Quad SPI FLASH memory problems From: bknpk@hotmail.com Injection-Date: Sat, 28 Mar 2015 17:29:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3663 On Friday, March 27, 2015 at 12:21:35 PM UTC+3, niv wrote: > Has anyone tried the Spansion s25fl series of FLASH memories with Quad SP= I interface? > I've downloaded their VHDL model, but can't get it to talk. I've written= some very simple code to read a few addresses using just single SPI mode, = but I get nothing back, and all looks OK in the wave view for the read cycl= e (command X"03"). I can see my initialisation data correct in the FLASH a= rray, but just can't get the model to work, (or create an SDF file with the= ir tools)! > Has anyone had any luck with this model? (I've used an s29... FLASH succ= essful in the past, but that's standard FLASH with addr & data busses etc). > Any hints/help welcome. -------------------------------------------------------- You may want to look on this work, which uses samsung flash "The existing SD slave project was extended recently to support a Samsung f= lash instead of the XILINX ROM components, which are used in the free versi= on of the code. The new design uses a FIFO, build up of XILINX dual port RAM components, in= both the direction of SD read from flash and SD write to flash. It was written in VHDL both design and test-bench..." http://bknpk.ddns.net/my_web/SDIO/sd_to_flash_write.html From newsfish@newsfish Thu Aug 1 00:32:54 2024 X-Received: by 10.182.24.74 with SMTP id s10mr8848941obf.8.1427564328538; Sat, 28 Mar 2015 10:38:48 -0700 (PDT) X-Received: by 10.140.97.137 with SMTP id m9mr404101qge.12.1427564328436; Sat, 28 Mar 2015 10:38:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no401326igd.0!news-out.google.com!q90ni548qgd.1!nntp.google.com!z60no154810qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Mar 2015 10:38:48 -0700 (PDT) In-Reply-To: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Quad SPI FLASH memory problems From: niv Injection-Date: Sat, 28 Mar 2015 17:38:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3664 Thanks for trying to help, but that's not the issue. I have written interf= aces to FLASH memory (with address & data lines etc) quite successfully, it= 's the new Quad SPI version I cannot get to respond to my, so far very simp= le, commands. The stimulus into the SPI in looks as per FLASH data sheet, = but I get not response on the SPI out pin of the FLASH. What I really need is example VHDL code of driving a QSPI FLASH. It may be= the model is not working because I don't have an sdf for it yet, but I exp= ected it to work, albeit without the expected access delays. From newsfish@newsfish Thu Aug 1 00:32:55 2024 X-Received: by 10.236.20.234 with SMTP id p70mr22931304yhp.46.1427604419938; Sat, 28 Mar 2015 21:46:59 -0700 (PDT) X-Received: by 10.50.221.44 with SMTP id qb12mr97881igc.11.1427604419896; Sat, 28 Mar 2015 21:46:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q107no229937qgd.1!news-out.google.com!db6ni763igc.0!nntp.google.com!h15no354410igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Mar 2015 21:46:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.74.37.137; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 119.74.37.137 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Daniel Kho Injection-Date: Sun, 29 Mar 2015 04:46:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3197 X-Received-Body-CRC: 2366743841 Xref: news.eternal-september.org comp.lang.vhdl:3665 On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote: > -dan, > It is too simple and naive to think a patent holder should relinquish its= patent rights to let their patents to be part of an international standard= . >=20 > Here is a Wikipedia website for your reference on how international stand= ard body works. >=20 > http://en.wikipedia.org/wiki/3GPP >=20 > Here is a news about standard-essential patents: ITU to address surge in = litigation over standards-essential patents: > =20 > http://www.computerworld.com/article/2505517/technology-law-regulation/it= u--to-address-surge-in-litigation-over-standards-essential-patents.html >=20 > Another related news about standards patents: Nokia, HP, Verizon back FTC= against import bans over standards patents: >=20 > http://www.computerworld.com/article/2504127/technology-law-regulation/no= kia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html >=20 > Why currently VHDL committee has so many difficulties financially to get = industries into its activities? One most important reason is that VHDL is n= ow free to use for all related companies and they don't have to make their = contributions. >=20 > Weng That's the reason why standard bodies have by-laws that make sure any infor= mation submitted or discussed within working groups are not encumbered by p= atents. If you are trying to discuss your patent idea within a working grou= p, you need to declare that the information has been patented. In which cas= e, the Chair will tell the whole group to not use that information in the s= tandardization process. I think this is how it goes for most standard bodie= s. -dan From newsfish@newsfish Thu Aug 1 00:32:55 2024 X-Received: by 10.50.73.7 with SMTP id h7mr9016005igv.2.1427618551638; Sun, 29 Mar 2015 01:42:31 -0700 (PDT) X-Received: by 10.50.43.133 with SMTP id w5mr106170igl.16.1427618551601; Sun, 29 Mar 2015 01:42:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no382539igd.0!news-out.google.com!q14ni2214ign.0!nntp.google.com!h15no671028igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 29 Mar 2015 01:42:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.153.32.66; posting-account=0KW5lQoAAABimvhLxpMPGETu7egRGajt NNTP-Posting-Host: 203.153.32.66 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> Subject: there is a problem with if statement please help me From: rama hareesh Injection-Date: Sun, 29 Mar 2015 08:42:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3666 here my code is i am doing lift control based on spartan 3e for my 4th year student here there a problem with if condition here my problem will present if srx='1' library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity lift is Port ( b0 : in STD_LOGIC; clk: in std_logic; b1 : in STD_LOGIC; b2 : in STD_LOGIC; srx : in STD_LOGIC; s0 : out STD_LOGIC; s1 : out STD_LOGIC; s2 : out STD_LOGIC; m1 : out STD_LOGIC; m0 : out STD_LOGIC); end lift; architecture Behavioral of lift is type STATE_TYPE is (f0, f1, f2, mup1,mup2,mdown1, mdown0); signal nes:state_type; begin process(b0,b1,b2,srx,clk) begin if(clk' event and clk='1') then case nes is --Ground floor when f0=> s0<='1'; s1<='0'; s2<='0'; if srx='1' then --m1<='0'; --m0<='0'; if b1='1' then s0<='0'; -- s1<='1'; -- s2<='0'; --m1<='1'; --m0<='0'; nes<=mup1; elsif b2='1' then s0<='0'; s1<='0'; s2<='1'; --m1<='1' after 5ns; --m0<='0'; nes<=mup2; else nes<=f0; end if; end if; -- first floor up when f1=> if srx='1' then -- m1<='0'; -- m0<='0'; if b0='1' then s0<='1'; s1<='0'; s2<='0'; m1<='0' after 5ns; m0<='1'; nes<=mdown0; elsif b2='1' then s0<='0'; s1<='0'; s2<='1'; --m1<='1' after 5ns; --m0<='0'; nes<=mup2; else nes<=f1; end if; end if; -- sencond floor when f2=> if srx ='1' then -- m1<='0'; -- m0<='0'; if b0='1' then s0<='1'; s1<='0'; s2<='0'; --m1<='0' after 5ns; --m0<='1'; nes<=mdown0; elsif b1='1' then s0<='0'; s1<='1'; s2<='0'; --m1<='0' after 5ns; --m0<='1'; nes<=mdown1; else nes<=f2; end if; end if; when mup1=> m1<='1'; m0<='0'; s0<='0'; s1<='1'; s2<='0'; if srx='0' then m1<='0'; m0<='0'; nes<=f1; else nes<=mup1; end if; when mup2=> m1<='1'; m0<='0'; nes<=f2; when mdown1=> m1<='0'; m0<='1'; nes<=f1; when mdown0=> m1<='0'; m0<='1'; nes<=f0; end case; end if; end process; end Behavioral; From newsfish@newsfish Thu Aug 1 00:32:55 2024 X-Received: by 10.43.100.138 with SMTP id cw10mr12820134icc.5.1427652010349; Sun, 29 Mar 2015 11:00:10 -0700 (PDT) X-Received: by 10.50.66.227 with SMTP id i3mr127597igt.14.1427652010335; Sun, 29 Mar 2015 11:00:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no910504igd.0!news-out.google.com!q14ni2565ign.0!nntp.google.com!h15no910493igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 29 Mar 2015 11:00:09 -0700 (PDT) In-Reply-To: <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0612675a-5d72-486f-98a3-05ac04a1bd73@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sun, 29 Mar 2015 18:00:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3667 On Saturday, March 28, 2015 at 9:47:01 PM UTC-7, Daniel Kho wrote: > On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote: > > -dan, > > It is too simple and naive to think a patent holder should relinquish its patent rights to let their patents to be part of an international standard. > > > > Here is a Wikipedia website for your reference on how international standard body works. > > > > http://en.wikipedia.org/wiki/3GPP > > > > Here is a news about standard-essential patents: ITU to address surge in litigation over standards-essential patents: > > > > http://www.computerworld.com/article/2505517/technology-law-regulation/itu--to-address-surge-in-litigation-over-standards-essential-patents.html > > > > Another related news about standards patents: Nokia, HP, Verizon back FTC against import bans over standards patents: > > > > http://www.computerworld.com/article/2504127/technology-law-regulation/nokia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html > > > > Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions. > > > > Weng > > -dan 1. > That's the reason why standard bodies have by-laws that make sure any information submitted or discussed within working groups are not encumbered by patents. Agree. 2. > If you are trying to discuss your patent idea within a working group, you need to declare that the information has been patented. Agree. 3. > In which case, the Chair will tell the whole group to not use that information in the standardization process. Don't agree. You may ask current VHDL committee Chairman Jim Lewis what the by-law of VHDL is in the situation. He is closely watching the development of the issue now. I remember he had recently mentioned in this group to organize a working group in VHDL to develop some patents for the VHDL committee. 4. > I think this is how it goes for most standard bodies. Don't agree. Without patented inventions there would be no all G2, G3, G4 and G5 standards in cellphone and internet industries. Weng > > -dan From newsfish@newsfish Thu Aug 1 00:32:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Safe FSM Date: Sun, 29 Mar 2015 22:12:27 +0200 (CEST) Organization: news.individual.net Lines: 34 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net yc6X4nf4KvV83ud1NTWqqQBDgfEXNf54nfPSbsvXNqubah7Txs Cancel-Lock: sha1:8AD9wb41AlOz1QFuqIgKjdxGLVE= X-Newsreader: PiaoHong.Usenet.Client.Free:1.65 Xref: news.eternal-september.org comp.lang.vhdl:3668 Hi everyone, I have an FSM of some (sigh) 150 states and Synplify Pro (from the Libero suite) is not able to recognize it as an FSM since it accepts 128 states max. The code simulates and works well on the target, but we are all aware that the implementation is not protected against non described states. Since we cannot rely on the tool capability to implement a safe FSM, I thought the easier way to implement a safe FSM would be to declare 2^n states explicitly and force the tool to preserve all states that are not reachable by design but could be triggered by an external event (say some heavy ion). Another possibility would be to encode a one hot FSM and monitor the state vector with another process responsible for checking any violation of the one hot coding. Are those reasonable paths? I'm excluding the possibility to split the FSM in hierarchical FSM since it will be a lot of work and raise more questions. Oh by the way, why the heck synthesis tools decide to neglect the "when others" closer unless I specify the safe FSM option? Couldn't they simplify follow the hdl description. Any suggestion/comment is appreciated. Al ----Android NewsGroup Reader---- http://usenet.sinaapp.com/ From newsfish@newsfish Thu Aug 1 00:32:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp5-1.free.fr!not-for-mail Date: Sun, 29 Mar 2015 22:23:45 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: there is a problem with if statement please help me References: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> In-Reply-To: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Antivirus: avast! (VPS 150329-1, 29/03/2015), Outbound message X-Antivirus-Status: Clean Lines: 15 Message-ID: <55185f4f$0$3058$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 29 Mar 2015 22:23:43 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1427660623 news-3.free.fr 3058 88.185.146.198:1302 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3669 Le 29/03/2015 10:42, rama hareesh a écrit : > here my code is > i am doing lift control based on spartan 3e for my 4th year student > here there a problem with if condition > here my problem will present if srx='1' Ok, can you now describe the actual problem ? Nicolas --- L'absence de virus dans ce courrier électronique a été vérifiée par le logiciel antivirus Avast. http://www.avast.com From newsfish@newsfish Thu Aug 1 00:32:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Sun, 29 Mar 2015 16:29:47 -0400 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 29 Mar 2015 20:28:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="8818"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX182lSaJHGMdtYo1JsRGHvgI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:E+cHwB9SNW7YdjsFya7pheTK93Y= Xref: news.eternal-september.org comp.lang.vhdl:3670 On 3/29/2015 4:12 PM, alb wrote: > > Hi everyone, > > I have an FSM of some (sigh) 150 states and Synplify Pro (from > the Libero suite) is not able to recognize it as an FSM since it > accepts 128 states max. The code simulates and works well on the > target, but we are all aware that the implementation is not > protected against non described states. > > Since we cannot rely on the tool capability to implement a safe FSM, > I thought the easier way to implement a safe FSM would be to > declare 2^n states explicitly and force the tool to preserve all > states that are not reachable by design but could be triggered by > an external event (say some heavy ion). > > Another possibility would be to encode a one hot FSM and monitor > the state vector with another process responsible for checking > any violation of the one hot coding. > > Are those reasonable paths? I'm excluding the possibility to split > the FSM in hierarchical FSM since it will be a lot of work and > raise more questions. > > Oh by the way, why the heck synthesis tools decide to neglect the > "when others" closer unless I specify the safe FSM option? > Couldn't they simplify follow the hdl description. > > > Any suggestion/comment is appreciated. Perhaps you can explain what you mean by a "safe" FSM? I have never heard this term. You might consider redesigning your machine as several smaller machines. Then the tool will recognize each of them since they will have less than 128 states. -- Rick From newsfish@newsfish Thu Aug 1 00:32:57 2024 X-Received: by 10.182.1.199 with SMTP id 7mr36924519obo.49.1427662423624; Sun, 29 Mar 2015 13:53:43 -0700 (PDT) X-Received: by 10.182.148.35 with SMTP id tp3mr257522obb.16.1427662423565; Sun, 29 Mar 2015 13:53:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no987774igd.0!news-out.google.com!q14ni2673ign.0!nntp.google.com!h15no587678igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 29 Mar 2015 13:53:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: Andy Injection-Date: Sun, 29 Mar 2015 20:53:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3671 You can use a syn_preserve attribute on the state register signal to disabl= e fsm compiler and other optimizations (such as due to reachability analysi= s). Then a "when others" choice can assign a legal state value if none of t= he other choices (presumably all the legal states) match. Without syn_prese= rve, the when others choice is usually ignored unless you actually assign a= value (including upon reset) that is not covered by an explicit when choic= e. Note that this does not detect an illegal transition to a legal state (such= as due to an SEU or an improperly synchronized input). Detecting all possible illegal states for a one-hot FSM is expensive. Howev= er, a simple parity check will detect single bit errors in one-hot FSMs (on= e-hot by definition is odd parity). I would also seriously consider breaking up a state machine with that many = states... Andy From newsfish@newsfish Thu Aug 1 00:32:57 2024 X-Received: by 10.182.1.199 with SMTP id 7mr37219821obo.49.1427666899760; Sun, 29 Mar 2015 15:08:19 -0700 (PDT) X-Received: by 10.50.129.98 with SMTP id nv2mr133665igb.1.1427666899741; Sun, 29 Mar 2015 15:08:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1016860igd.0!news-out.google.com!q14ni2725ign.0!nntp.google.com!h15no1016854igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 29 Mar 2015 15:08:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.43.4.223; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.43.4.223 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: Jim Lewis Injection-Date: Sun, 29 Mar 2015 22:08:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3672 Hi Al, I think the most reasonable answer is the one proposed by @rickman, partiti= on the statemachine into multiple statemachines, each with < 128 states.=20 > Since we cannot rely on the tool capability to implement a safe FSM,=20 > I thought the easier way to implement a safe FSM would be to > declare 2^n states explicitly and force the tool to preserve all > states that are not reachable by design but could be triggered by > an external event (say some heavy ion). If you want a safe FSM, then you need hamming distance between the states. = Hence you will need at least 2^(n+1). Code your states as constants that = have a hamming distance and use syn_preserve to keep redundancy from being = removed. Use the when others condition to detect illegal transitions or if= you use a hamming distance of at least 2, you can add the error recovery i= nto the code. =20 This is going to get real tedious and be interesting to debug if you run in= to issues. You will need to simulate your error recovery to prove you did = it right. You will probably be wishing you had enumerated states just for = debug - you could create them and create a mapping between them and the con= stant values just to assist with debug. All of this is alot of work. I would expect the better answer to be to spr= ing for the pay version of the tool. Yes expensive, but it may give you so= me additional options the free tool does not have - like a hamming distance= between states rather than one-hot. I agree with Andy that it is going to= be expensive to do recovery with a one-hot safe statemachine.=20 > Another possibility would be to encode a one hot FSM and monitor > the state vector with another process responsible for checking > any violation of the one hot coding.=20 My recommendation is don't. I have yet to see someone's one-hot VHDL state= machine code actually be a true one-hot statemachine. The problem is that = if you use a case statement to decode your states, most synthesis tools wil= l decode all bits rather than the one bit that determines the state, and he= nce, the state decoding is huge. The start of getting a synthesis tool to = get it right is to assign all outputs to a default value and use an if-end = if structure that only decodes a single bit in the state vector and only as= signs outputs to the opposite value of the default value. The only vector = value allowed in the structure is next state (or current state if you use a= single process statemachine). Next state needs to be defaulted to all zer= os and a state update may only assign a single bit to a '1'. =20 The code gets complicated, ugly, and unreadable by most, hence, my recommen= dation, if you need one-hot, you need the tool to understand your statemach= ine as a statemachine and for it to implement it as a one-hot statemachine. > Oh by the way, why the heck synthesis tools decide to neglect the > "when others" closer unless I specify the safe FSM option? > Couldn't they simplify follow the hdl description. Commercial needs the speed, so those who need the safe option have to work = harder to make it happen. A cruel, but fair balance to the problem. Jim From newsfish@newsfish Thu Aug 1 00:32:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: 30 Mar 2015 07:01:23 GMT Lines: 26 Message-ID: References: X-Trace: individual.net VAahCsJtN3Enf4fbjBTegQJsRNniKjoT7ZhvEnIe9XkZdZEA+Y X-Orig-Path: not-for-mail Cancel-Lock: sha1:f6tM25Oy4GufdgzeUh6p0j97tEc= User-Agent: tin/2.1.1-20120623 ("Mulindry") (UNIX) (Linux/3.2.0-4-686-pae (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3673 hi Rick, rickman wrote: [] > Perhaps you can explain what you mean by a "safe" FSM? I have never > heard this term. a safe FSM is an FSM that does not get stuck in an undefined state. > You might consider redesigning your machine as several smaller machines. > Then the tool will recognize each of them since they will have less > than 128 states. Even if I understand this is the best approach, we are talking about a 4.5 KLOC code that took three months to develop and many more to verify and validate on the hardware. I'm not sure I'd want to embark on such a nightmare. The problem is not in coding, is in the architecture of the FSM itself. At the architecture review somebody should have coughed a little harder when looking at the number of states and raise a hand before designers started hammering the code. Now I'm trying to get out of the dirt with the minimum amount of impact. Al From newsfish@newsfish Thu Aug 1 00:32:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: 30 Mar 2015 07:15:18 GMT Lines: 51 Message-ID: References: X-Trace: individual.net VHDmGK90d0WBfaxeSHlG3AEcXmiq5cpbY7K8gn136H+pfeLoWV X-Orig-Path: not-for-mail Cancel-Lock: sha1:Ssd1CcqxIf/YAp7+2ZU6wTTACAQ= User-Agent: tin/2.1.1-20120623 ("Mulindry") (UNIX) (Linux/3.2.0-4-686-pae (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3674 Hi Andy, Andy wrote: > You can use a syn_preserve attribute on the state register signal to > disable fsm compiler and other optimizations (such as due to > reachability analysis). Then a "when others" choice can assign a legal > state value if none of the other choices (presumably all the legal > states) match. Without syn_preserve, the when others choice is usually > ignored unless you actually assign a value (including upon reset) that > is not covered by an explicit when choice. I'm not sure it is even needed the syn_preserve, since the tool does not recognize the FSM at all (they admitedly reported the tool has a 128 bit limit for FSM state vector). Considering the 'when others' is not wiped out by their FSM compiler, maybe we are better off than thought. > Note that this does not detect an illegal transition to a legal state > (such as due to an SEU or an improperly synchronized input). That is correct, that's why I'd feel more confortable if states were decoded with a hamming distance greater than 1. We are talking about an implementation that is already 'TMRed', so chances of a double failure causing a transition to a legal state might be very small. Nevertheless SET on combinatorial logic that is not TMRed might give you troubles. The transient may be just enough to have the triplified register to get the wrong value on a perfect triple copy! > Detecting all possible illegal states for a one-hot FSM is expensive. > However, a simple parity check will detect single bit errors in > one-hot FSMs (one-hot by definition is odd parity). This is what I thought. One-hot and odd parity check (no need to verify overflow for cases like '...010101...' since they are too rare to be a real concern). > I would also seriously consider breaking up a state machine with that > many states... As mentioed in a different post in this thread, there's no simple breaking. We would need to get the architecture and shake it a bit before being able to split the number of states in several FSMs. On top of it there's a lot of verification that needs to be re-run as well, also on the real hardware (since long sequences were not verified in simulation). But as you said, maybe splitting, in the end, would be simpler that any other supposedly 'cheaper' alternative. From newsfish@newsfish Thu Aug 1 00:32:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: 30 Mar 2015 07:51:05 GMT Lines: 118 Message-ID: References: X-Trace: individual.net uXD1U806/giEZ3LTfffoJg72Gc1fkbzTacA9X7xYdFoNZUAIAZ X-Orig-Path: not-for-mail Cancel-Lock: sha1:MJL4dAumpaDe9UcK4SCcKRf8kLk= User-Agent: tin/2.1.1-20120623 ("Mulindry") (UNIX) (Linux/3.2.0-4-686-pae (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3675 Hi Jim, Jim Lewis wrote: [] > I think the most reasonable answer is the one proposed by @rickman, > partition the statemachine into multiple statemachines, each with < > 128 states. I'm kinda repeating to myself that as well, but I keep having everyone against since it is too 'expensive'. > >> Since we cannot rely on the tool capability to implement a safe FSM, >> I thought the easier way to implement a safe FSM would be to >> declare 2^n states explicitly and force the tool to preserve all >> states that are not reachable by design but could be triggered by an >> external event (say some heavy ion). > If you want a safe FSM, then you need hamming distance between the > states. Hence you will need at least 2^(n+1). Code your states as > constants that have a hamming distance and use syn_preserve to keep > redundancy from being removed. Use the when others condition to > detect illegal transitions or if you use a hamming distance of at > least 2, you can add the error recovery into the code. I haven't understood the 'add the error recovery into the code'. I would have done something like this: process(clk, rst) begin if rst = '1' then -- reset all output signals and state vector here elseif rising_edge(clk) then -- define all legal states here case state is when "ABC" => -- set output here -- set next state here when "DEF" => -- set output here -- set next state here when others => -- set output here -- set safe state here end case; end if; end process; the only place where I can recover from an illegal state would be in the 'when others' branch. > This is going to get real tedious and be interesting to debug if you > run into issues. You will need to simulate your error recovery to > prove you did it right. You will probably be wishing you had > enumerated states just for debug - you could create them and create a > mapping between them and the constant values just to assist with > debug. We normally force the state vector to show what it'll do in the event of an illegal state, this is standard practice, but not in post-synth sims. We do analyze the synthesis report to verify that implementation is correct. Seldom we do analyze the netlist as well. But very rarely we perform post-synth sims. > All of this is alot of work. I would expect the better answer to be > to spring for the pay version of the tool. Yes expensive, but it may > give you some additional options the free tool does not have - like a > hamming distance between states rather than one-hot. I agree with > Andy that it is going to be expensive to do recovery with a one-hot > safe statemachine. unfortunately the tool is the main issue here. Synplify Pro, no matter if paid or not, does not recognize more than 128 bit FSMs (if I understood it correctly). So we cannot really count on it. > >> Another possibility would be to encode a one hot FSM and monitor >> the state vector with another process responsible for checking any >> violation of the one hot coding. > My recommendation is don't. I have yet to see someone's one-hot VHDL > statemachine code actually be a true one-hot statemachine. The > problem is that if you use a case statement to decode your states, > most synthesis tools will decode all bits rather than the one bit that > determines the state, and hence, the state decoding is huge. The > start of getting a synthesis tool to get it right is to assign all > outputs to a default value and use an if-end if structure that only > decodes a single bit in the state vector and only assigns outputs to > the opposite value of the default value. The only vector value > allowed in the structure is next state (or current state if you use a > single process statemachine). Next state needs to be defaulted to all > zeros and a state update may only assign a single bit to a '1'. I see your point. It is possible that we have always used one-hot encoding ending with an enormous amount of resources because of the decoding logic. > The code gets complicated, ugly, and unreadable by most, hence, my > recommendation, if you need one-hot, you need the tool to understand > your statemachine as a statemachine and for it to implement it as a > one-hot statemachine. One-hot is not mandatory, a hamming distance of, say, 2 would be sufficient. >> Oh by the way, why the heck synthesis tools decide to neglect the >> "when others" closer unless I specify the safe FSM option? Couldn't >> they simplify follow the hdl description. > Commercial needs the speed, so those who need the safe option have to > work harder to make it happen. A cruel, but fair balance to the > problem. fair enough...we do it 'not because is easy, but because is hard'! Al From newsfish@newsfish Thu Aug 1 00:32:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Mon, 30 Mar 2015 03:53:38 -0400 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 30 Mar 2015 07:52:46 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="7904"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/cMeWpKqA6v9q9ke0Cr8L4" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:GUM502hOjV2jct0kmKL7b0qHNSQ= Xref: news.eternal-september.org comp.lang.vhdl:3676 On 3/30/2015 3:01 AM, alb wrote: > hi Rick, > > rickman wrote: > [] >> Perhaps you can explain what you mean by a "safe" FSM? I have never >> heard this term. > > a safe FSM is an FSM that does not get stuck in an undefined state. > >> You might consider redesigning your machine as several smaller machines. >> Then the tool will recognize each of them since they will have less >> than 128 states. > > Even if I understand this is the best approach, we are talking about a > 4.5 KLOC code that took three months to develop and many more to verify > and validate on the hardware. I'm not sure I'd want to embark on such a > nightmare. > > The problem is not in coding, is in the architecture of the FSM itself. > At the architecture review somebody should have coughed a little harder > when looking at the number of states and raise a hand before designers > started hammering the code. That's what splitting it into multiple FSMs would be, an architecture change. > Now I'm trying to get out of the dirt with the minimum amount of impact. If you just need to have the FSM handle the remaining 2^N-M states why not specify them explicitly? I assume you identify a start state and all the undefined states transition unconditionally to that start state. That can be coded in the "otherwise" clause of a case statement very easily. Or if you aren't using a case statement you can just surround the existing state code with an IF (all the undefined states) go to reset ELSE normal operation ENDIF -- Rick From newsfish@newsfish Thu Aug 1 00:32:58 2024 X-Received: by 10.66.155.9 with SMTP id vs9mr37884146pab.20.1427705027119; Mon, 30 Mar 2015 01:43:47 -0700 (PDT) X-Received: by 10.140.109.246 with SMTP id l109mr461177qgf.22.1427705027022; Mon, 30 Mar 2015 01:43:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no1317135igd.0!news-out.google.com!q90ni547qgd.1!nntp.google.com!q107no526451qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 01:43:46 -0700 (PDT) In-Reply-To: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.246.134.120; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 213.246.134.120 References: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a7b8bf7-35c2-4748-9a04-5f67c49573e4@googlegroups.com> Subject: Re: there is a problem with if statement please help me From: "colin_toogood@yahoo.com" Injection-Date: Mon, 30 Mar 2015 08:43:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 9 Xref: news.eternal-september.org comp.lang.vhdl:3677 A couple of simple things to begin with. 1) You say this code is going in a spartan 3e. THE VERY FIRST THING THAT YOU HAVE TO DO IS UNDERSTAND WHAT AN FPGA IS. Then you will understand that there is no "after 5ns" magic. If you have tried to synthesize yet you will find a "I have ignored this" message in the log files. 2) You have to understand what a process is. Then you will replace your process line with "process(clk)", unless you have cut some asynchronous stuff but I doubt it. Colin From newsfish@newsfish Thu Aug 1 00:32:59 2024 X-Received: by 10.182.97.2 with SMTP id dw2mr38414112obb.0.1427707117864; Mon, 30 Mar 2015 02:18:37 -0700 (PDT) X-Received: by 10.50.57.104 with SMTP id h8mr159016igq.15.1427707117838; Mon, 30 Mar 2015 02:18:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no816943igd.0!news-out.google.com!q14ni3136ign.0!nntp.google.com!h15no816940igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 02:18:37 -0700 (PDT) In-Reply-To: <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: diogratia@gmail.com Injection-Date: Mon, 30 Mar 2015 09:18:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3678 On Sunday, March 29, 2015 at 5:47:01 PM UTC+13, Daniel Kho wrote: > On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote: > >=20 > > Why currently VHDL committee has so many difficulties financially to ge= t industries into its activities? One most important reason is that VHDL is= now free to use for all related companies and they don't have to make thei= r contributions. > >=20 >=20 > That's the reason why standard bodies have by-laws that make sure any inf= ormation submitted or discussed within working groups are not encumbered by= patents. If you are trying to discuss your patent idea within a working gr= oup, you need to declare that the information has been patented. In which c= ase, the Chair will tell the whole group to not use that information in the= standardization process. I think this is how it goes for most standard bod= ies. >=20 See http://www.eda.org/vasg/docs/Patent_disc_appropriate_topics.pdf Page 4: * The DASC will only accept patented material under paragraph (a) of IEEE Patent Policy Where paragraph (a) is found on PDF Page 2 (Slide #1): a) A general disclaimer to the effect that the patentee will not enforc= e any of its present or future patent(s) whose use would be required t= o=20 implement either mandatory or optional potions of the proposed IEEE standard against any person or entity complying with the standard; o= r=20 The VASG P1076 effort falls under these conditions, no one is going to get = rich on a standard essential patent required to implement the VHDL standard= (nor either Verilog standards also under the auspices of DASC). Also note Page 3 (slide #2): Inappropriate Topics for IEEE WG Meetings * Don't discuss licensing terms or conditions ... From newsfish@newsfish Thu Aug 1 00:32:59 2024 X-Received: by 10.70.94.102 with SMTP id db6mr37105170pdb.0.1427709220194; Mon, 30 Mar 2015 02:53:40 -0700 (PDT) X-Received: by 10.50.60.71 with SMTP id f7mr163192igr.10.1427709220148; Mon, 30 Mar 2015 02:53:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h15no1377774igd.0!news-out.google.com!db6ni1996igc.0!nntp.google.com!h15no1377773igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 02:53:39 -0700 (PDT) In-Reply-To: <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.125.115.98; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.125.115.98 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Daniel Kho Injection-Date: Mon, 30 Mar 2015 09:53:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3679 On Monday, 30 March 2015 17:18:41 UTC+8, diog...@gmail.com wrote: > The VASG P1076 effort falls under these conditions, no one is going to get rich on a standard essential patent required to implement the VHDL standard (nor either Verilog standards also under the auspices of DASC). There goes... thanks Dio! From newsfish@newsfish Thu Aug 1 00:32:59 2024 X-Received: by 10.66.197.170 with SMTP id iv10mr35113137pac.25.1427720707102; Mon, 30 Mar 2015 06:05:07 -0700 (PDT) X-Received: by 10.140.104.34 with SMTP id z31mr454697qge.11.1427720706983; Mon, 30 Mar 2015 06:05:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!209.85.213.216.MISMATCH!h15no1535109igd.0!news-out.google.com!q90ni548qgd.1!nntp.google.com!z60no621757qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 06:05:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:f507:e136:acf0:5ff7; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:f507:e136:acf0:5ff7 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <71a7cb6e-6359-4458-89fd-7aca707608d4@googlegroups.com> Subject: Re: Safe FSM From: KJ Injection-Date: Mon, 30 Mar 2015 13:05:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3680 On Sunday, March 29, 2015 at 6:08:23 PM UTC-4, Jim Lewis wrote: > My recommendation is don't. I have yet to see someone's one-hot VHDL=20 > statemachine code actually be a true one-hot statemachine. The problem i= s=20 > that if you use a case statement to decode your states, most synthesis to= ols=20 > will decode all bits rather than the one bit that determines the state, a= nd=20 > hence, the state decoding is huge. The start of getting a synthesis tool= to=20 > get it right is to ... Do you have an example of this? I just looked at a recent design and what = I see is different number of fanout for the various state bit signals in th= e fitter report which indicates to me that the logic is using only those st= ate bits that it needs. The report doesn't blast out all of the logic equa= tions to validate the final usage but it would seem that if what you say wa= s true, then the fanout for each state bit would at least have to be the sa= me. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:32:59 2024 X-Received: by 10.236.29.146 with SMTP id i18mr17059599yha.58.1427723229499; Mon, 30 Mar 2015 06:47:09 -0700 (PDT) X-Received: by 10.140.21.145 with SMTP id 17mr472705qgl.1.1427723229481; Mon, 30 Mar 2015 06:47:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no631412qgd.0!news-out.google.com!q90ni547qgd.1!nntp.google.com!q107no631306qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 06:47:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Subject: Re: Safe FSM From: Thomas Stanka Injection-Date: Mon, 30 Mar 2015 13:47:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1741 X-Received-Body-CRC: 157679516 Xref: news.eternal-september.org comp.lang.vhdl:3681 Am Sonntag, 29. M=E4rz 2015 22:12:32 UTC+2 schrieb alb: > Since we cannot rely on the tool capability to implement a safe FSM,=20 > I thought the easier way to implement a safe FSM would be to > declare 2^n states explicitly and force the tool to preserve all > states that are not reachable by design but could be triggered by > an external event (say some heavy ion). The easiest way to ensure Synplify keeps all defined states is using 2^n st= ates and cycle at least once (after reset) through all "unused" states. In all other cases you might end up with a result different from your inten= tion. bye Thomas From newsfish@newsfish Thu Aug 1 00:33:00 2024 X-Received: by 10.236.32.238 with SMTP id o74mr39129460yha.2.1427728884485; Mon, 30 Mar 2015 08:21:24 -0700 (PDT) X-Received: by 10.50.57.104 with SMTP id h8mr196333igq.15.1427728884460; Mon, 30 Mar 2015 08:21:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q107no654447qgd.1!news-out.google.com!db6ni2220igc.0!nntp.google.com!h15no1616468igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 08:21:23 -0700 (PDT) In-Reply-To: <71a7cb6e-6359-4458-89fd-7aca707608d4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <71a7cb6e-6359-4458-89fd-7aca707608d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: KJ Injection-Date: Mon, 30 Mar 2015 15:21:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2627 X-Received-Body-CRC: 618823529 Xref: news.eternal-september.org comp.lang.vhdl:3682 On Monday, March 30, 2015 at 9:05:12 AM UTC-4, KJ wrote: > On Sunday, March 29, 2015 at 6:08:23 PM UTC-4, Jim Lewis wrote: > > My recommendation is don't. I have yet to see someone's one-hot VHDL= =20 > > statemachine code actually be a true one-hot statemachine. The problem= is=20 > > that if you use a case statement to decode your states, most synthesis = tools=20 > > will decode all bits rather than the one bit that determines the state,= and=20 > > hence, the state decoding is huge. The start of getting a synthesis to= ol to=20 > > get it right is to ... >=20 > Do you have an example of this? I just looked at a recent design and wha= t I see is different number of fanout for the various state bit signals in = the fitter report which indicates to me that the logic is using only those = state bits that it needs. The report doesn't blast out all of the logic eq= uations to validate the final usage but it would seem that if what you say = was true, then the fanout for each state bit would at least have to be the = same. >=20 > Kevin Jennings Or did you perhaps mean to say "yet to see someone's one-hot VHDL SAFE stat= emachine code actually be a true one-hot statemachine". If you did mean to= only refer to 'safe' state machines with your comment, then decode of all = of the bits would likely be part of the implementation of 'safe'. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:00 2024 X-Received: by 10.236.11.46 with SMTP id 34mr15778168yhw.22.1427740620331; Mon, 30 Mar 2015 11:37:00 -0700 (PDT) X-Received: by 10.50.119.131 with SMTP id ku3mr223602igb.2.1427740620254; Mon, 30 Mar 2015 11:37:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no712252qgd.0!news-out.google.com!db6ni2347igc.0!nntp.google.com!h15no1784562igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 11:36:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.255.147.121; posting-account=FbGAbQoAAADo4S2QpylKfP0Gt2DSb2ry NNTP-Posting-Host: 103.255.147.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <18c75c96-3d39-4b65-a3bb-58fad0eca63f@googlegroups.com> Subject: Need: Data Architect in Marlborough, MA From: latha.karnti@gmail.com Injection-Date: Mon, 30 Mar 2015 18:37:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1433 X-Received-Body-CRC: 1438712562 Xref: news.eternal-september.org comp.lang.vhdl:3683 HI, Please go through below the requirement if you're comfortable please forward his/her resume along with contact number & email-id to panand@sageitinc.net Position: Data Architect Location: Marlborough, MA Duration: 6+ Months Data Governance, Meta data Work Bench, Business Glossary, Pl/Sql, Good analytical and communication skills.. Thanks & Regards, Anand Executive-Talent Acquisition Direct: 972-996-0650 Ext: 339 panand@sageitinc.net From newsfish@newsfish Thu Aug 1 00:33:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Mon, 30 Mar 2015 18:03:16 -0400 Organization: A noiseless patient Spider Lines: 135 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 30 Mar 2015 22:02:25 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="9022"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19mOKF+YOhb68OjT5ZpTyCF" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:kAkGx1ki7rv9tGSzLSTEqokS8EY= Xref: news.eternal-september.org comp.lang.vhdl:3684 On 3/30/2015 3:51 AM, alb wrote: > Hi Jim, > > Jim Lewis wrote: > [] >> I think the most reasonable answer is the one proposed by @rickman, >> partition the statemachine into multiple statemachines, each with < >> 128 states. > > I'm kinda repeating to myself that as well, but I keep having everyone > against since it is too 'expensive'. > >> >>> Since we cannot rely on the tool capability to implement a safe FSM, >>> I thought the easier way to implement a safe FSM would be to >>> declare 2^n states explicitly and force the tool to preserve all >>> states that are not reachable by design but could be triggered by an >>> external event (say some heavy ion). > >> If you want a safe FSM, then you need hamming distance between the >> states. Hence you will need at least 2^(n+1). Code your states as >> constants that have a hamming distance and use syn_preserve to keep >> redundancy from being removed. Use the when others condition to >> detect illegal transitions or if you use a hamming distance of at >> least 2, you can add the error recovery into the code. > > I haven't understood the 'add the error recovery into the code'. I would > have done something like this: > > > process(clk, rst) > begin > if rst = '1' then > -- reset all output signals and state vector here > elseif rising_edge(clk) then > -- define all legal states here > case state is > when "ABC" => > -- set output here > -- set next state here > when "DEF" => > -- set output here > -- set next state here > when others => > -- set output here > -- set safe state here > end case; > end if; > end process; > > > the only place where I can recover from an illegal state would be in the > 'when others' branch. Not sure what you mean by this. Why do you care if it is the "only" place in the code? This one phrase covers *all* possible states not previously described as valid states. If there are some error states you want to recover from differently then they can be broken out as their own clauses in the case. >> This is going to get real tedious and be interesting to debug if you >> run into issues. You will need to simulate your error recovery to >> prove you did it right. You will probably be wishing you had >> enumerated states just for debug - you could create them and create a >> mapping between them and the constant values just to assist with >> debug. > > We normally force the state vector to show what it'll do in the event of > an illegal state, this is standard practice, but not in post-synth sims. > We do analyze the synthesis report to verify that implementation is > correct. Seldom we do analyze the netlist as well. But very rarely we > perform post-synth sims. > >> All of this is alot of work. I would expect the better answer to be >> to spring for the pay version of the tool. Yes expensive, but it may >> give you some additional options the free tool does not have - like a >> hamming distance between states rather than one-hot. I agree with >> Andy that it is going to be expensive to do recovery with a one-hot >> safe statemachine. > > unfortunately the tool is the main issue here. Synplify Pro, no matter > if paid or not, does not recognize more than 128 bit FSMs (if I > understood it correctly). So we cannot really count on it. > >> >>> Another possibility would be to encode a one hot FSM and monitor >>> the state vector with another process responsible for checking any >>> violation of the one hot coding. > >> My recommendation is don't. I have yet to see someone's one-hot VHDL >> statemachine code actually be a true one-hot statemachine. The >> problem is that if you use a case statement to decode your states, >> most synthesis tools will decode all bits rather than the one bit that >> determines the state, and hence, the state decoding is huge. The >> start of getting a synthesis tool to get it right is to assign all >> outputs to a default value and use an if-end if structure that only >> decodes a single bit in the state vector and only assigns outputs to >> the opposite value of the default value. The only vector value >> allowed in the structure is next state (or current state if you use a >> single process statemachine). Next state needs to be defaulted to all >> zeros and a state update may only assign a single bit to a '1'. > > I see your point. It is possible that we have always used one-hot > encoding ending with an enormous amount of resources because of the > decoding logic. One hot should provide very simple decode other than the error state. The error state could be detected simply by adding all the bits in a simplified adder which knows three states, 0, 1 and "more than one". Only the 1 output is not an error. I doubt the tool is smart enough to synthesize this though. It is something you can add separate from the case statement. >> The code gets complicated, ugly, and unreadable by most, hence, my >> recommendation, if you need one-hot, you need the tool to understand >> your statemachine as a statemachine and for it to implement it as a >> one-hot statemachine. > > One-hot is not mandatory, a hamming distance of, say, 2 would be > sufficient. I see the conversation has added this "Hamming" distance to the requirements. If you need a Hamming distance of 2 between valid states one-hot encoding gives you that automatically. If you need more than 2 one-hot is not possible. I don't know if the tools automatically give you a Hamming distance of 2 even if they recognize your design as a FSM, but it is easy enough to do by specifying the state values. -- Rick From newsfish@newsfish Thu Aug 1 00:33:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Mon, 30 Mar 2015 21:51:51 -0400 Organization: A noiseless patient Spider Lines: 62 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 31 Mar 2015 01:51:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="6746"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18wf7OF4PYW9M+JQfUtnwLL" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Cancel-Lock: sha1:+RE9AowsiU18eoGNrhTDx/ApQrE= Xref: news.eternal-september.org comp.lang.vhdl:3685 On 3/30/2015 9:47 AM, Thomas Stanka wrote: > Am Sonntag, 29. Mrz 2015 22:12:32 UTC+2 schrieb alb: >> Since we cannot rely on the tool capability to implement a safe FSM, >> I thought the easier way to implement a safe FSM would be to >> declare 2^n states explicitly and force the tool to preserve all >> states that are not reachable by design but could be triggered by >> an external event (say some heavy ion). > > The easiest way to ensure Synplify keeps all defined states is using 2^n states and cycle at least once (after reset) through all "unused" states. > > In all other cases you might end up with a result different from your intention. I'm not clear on what it means to "preserve" states...? The states are there, legal or illegal. You can't get rid of them. Are you saying the tool can remap the values of the state variable to mean something other than what you intend? If you want the efficiency of one-hot encoding you don't have to use a case statement. Instead of designing it as one state machine of N states and a state variable of N bits, consider each bit to be an independent state machine with entry and exit conditions. These conditions can be put in functions so that they are reused between the exit condition of one state and the entry condition of another. They can all still be described in the same process (quite hairy in the case of the OP's huge FSM). Here is an example... FSM : process (Clk, Rst) begin if ('1' = Rst) then StateA <= '1'; StateB <= '0'; StateC <= '0'; StateD <= '0'; . . . StateZ <= '0'; elsif (rising_edge(Clk)) then if ('0' = StateA) then StateA <= -- insert your state entry conditions here; else StateA <= not -- insert your state exit conditions here end if; -- (if StateA) if ('0' = StateB) then StateB <= -- insert your state entry conditions here; else StateB <= not -- insert your state exit conditions here end if; -- (if StateB) . . . end if; -- (if Rst) end process FSM; It is still the same FSM, but coded to minimize the decoding logic without any issues of what the tool will do. -- Rick From newsfish@newsfish Thu Aug 1 00:33:01 2024 X-Received: by 10.182.47.137 with SMTP id d9mr44763627obn.5.1427790630698; Tue, 31 Mar 2015 01:30:30 -0700 (PDT) X-Received: by 10.140.89.116 with SMTP id u107mr544071qgd.18.1427790630654; Tue, 31 Mar 2015 01:30:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no2221718igd.0!news-out.google.com!f74ni1qge.0!nntp.google.com!q107no813812qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 Mar 2015 01:30:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: Thomas Stanka Injection-Date: Tue, 31 Mar 2015 08:30:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3686 Am Dienstag, 31. M=E4rz 2015 03:51:55 UTC+2 schrieb rickman: > > The easiest way to ensure Synplify keeps all defined states is using 2^= n states and cycle at least once (after reset) through all "unused" states. > > > > In all other cases you might end up with a result different from your i= ntention. >=20 > I'm not clear on what it means to "preserve" states...? The states are= =20 > there, legal or illegal. You can't get rid of them. Are you saying the= =20 > tool can remap the values of the state variable to mean something other= =20 > than what you intend? Assume you have 10 user states and fill up to 16 by adding unused_state10-1= 5 than write "when others =3D> state <=3D idle;" This would logically ensure you recover from all states. On RTL simulation = you could even set the fsm by force command to unused state and see the FSM= recovers. But Synplify extracts during synthesise step, that you could not= reach the unused states and therefore starts optimising them in a way that= you might find later on a state from which your FSM cannot recover if it g= et stuck there. The same is valid if you use an counter from 0-9 "if counter < 10 then ... = else counter <=3D 0;". This statement can be optimised by Synplify to code = that might stuck, if your counter ever reaches value 14 due to SEE.=20 For One-Hot situation is even worse, if you consider states not reachable b= y normal operation, but you reach by accident (SEE, metastability,...), lik= e states with zero or two '1's. regards, Thomas From newsfish@newsfish Thu Aug 1 00:33:01 2024 X-Received: by 10.182.112.167 with SMTP id ir7mr46771694obb.29.1427815878487; Tue, 31 Mar 2015 08:31:18 -0700 (PDT) X-Received: by 10.50.40.9 with SMTP id t9mr72084igk.7.1427815878472; Tue, 31 Mar 2015 08:31:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no2521336igd.0!news-out.google.com!db6ni3162igc.0!nntp.google.com!h15no2521334igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 Mar 2015 08:31:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Tue, 31 Mar 2015 15:31:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 66 Xref: news.eternal-september.org comp.lang.vhdl:3687 On Tuesday, March 24, 2015 at 7:24:11 PM UTC-7, KJ wrote: > On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote: > >=20 > > Here I publish all source code for public confirmation. > > >=20 > What exactly would you like the public to confirm? Do you have made some= specific claims? >=20 > Given that you have not claimed anything specific, I can only confirm the= following: > - It does compile (Modelsim 10.3c) > - It does synthesize to something (Quartus 14.0; Top level entity=3DCPC1;= 56 Max II logic elements) >=20 > >=20 > > You may copy this part of code to do simulation by yourself. > > >=20 > Why would I want to simulate it? >=20 > Kevin Jennings Here is how I claim to increase very-hard-implemented wave pipelined circui= ts to 100% successful rate. The pairing rules between a WPC and a CPC [0140] Here are the paring rules on how a WPC and a CPC are paired. * A series CPC can be linked with one of four WPC embodiments: o With a WPC series_module: Input data is acceptable on every clock cycl= e. If wave-pipelining requirements are not met, a designer has to either re= peat the attempt with more CPC code modification, change code manually to m= ake it linking with an input_delay_module or a multiple_copy_module, or qui= t the attempt otherwise. o With a WPC input_delay_module: Input data is acceptable on every one o= r more clock cycle and its successful rate is 100%. If the number of input = data clock cycles is large enough, there is at most only one wave of input = data propagating through the CPC on any clock cycle and there are no wave-p= ipelining requirements any more. o With a WPC multiple_copy_module: Input data is acceptable on every clo= ck cycle and its successful rate is 100%. The cost may be the input registe= rs and combinational logic copied multiple times if it is linked with a mul= tiple_copy_module2, or the output registers may also be copied same times i= f it is linked with a multiple_copy_module1. * A feedback CPC can be linked with one of three WPC embodiments: o With a WPC input_delay_module: Input data is acceptable on every feedb= ack or more clock cycles and its successful rate is 100%. If the number of = input data clock cycles is large enough, there is at most only one wave of = input data propagating through the CPC on any clock cycle, and there are no= wave-pipelining requirements any more. o With a WPC multiple_copy_module: Input data is acceptable on every clo= ck cycle and its successful rate is 100%. The cost may be the input registe= rs and combinational logic copied the number of feedback clock cycles or mo= re times if it is linked with a multiple_copy_module2, or the output regist= ers may also be copied same times if it is linked with a multiple_copy_modu= le1. [0141] A linked WPC input_delay_module or multiple_copy_module will dege= nerate to a WPC series_module if a synthesizer later finds that wave-pipeli= ning requirements are met with one copy of the linked CPC and input data ac= ceptable on every clock cycle, and there will be neither code change nor ex= tra logic generated. Weng From newsfish@newsfish Thu Aug 1 00:33:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Tue, 31 Mar 2015 11:50:00 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 31 Mar 2015 15:49:08 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="10935"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18bzSAn3lGjn58btW21Vh0W" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:dptbhF0YSMEu7zye+ZlHQGdAt24= Xref: news.eternal-september.org comp.lang.vhdl:3688 On 3/31/2015 4:30 AM, Thomas Stanka wrote: > Am Dienstag, 31. Mrz 2015 03:51:55 UTC+2 schrieb rickman: >>> The easiest way to ensure Synplify keeps all defined states is using 2^n states and cycle at least once (after reset) through all "unused" states. >>> >>> In all other cases you might end up with a result different from your intention. >> >> I'm not clear on what it means to "preserve" states...? The states are >> there, legal or illegal. You can't get rid of them. Are you saying the >> tool can remap the values of the state variable to mean something other >> than what you intend? > > Assume you have 10 user states and fill up to 16 by adding unused_state10-15 than write "when others => state <= idle;" > This would logically ensure you recover from all states. On RTL simulation you could even set the fsm by force command to unused state and see the FSM recovers. But Synplify extracts during synthesise step, that you could not reach the unused states and therefore starts optimising them in a way that you might find later on a state from which your FSM cannot recover if it get stuck there. > > The same is valid if you use an counter from 0-9 "if counter < 10 then ... else counter <= 0;". This statement can be optimised by Synplify to code that might stuck, if your counter ever reaches value 14 due to SEE. > > For One-Hot situation is even worse, if you consider states not reachable by normal operation, but you reach by accident (SEE, metastability,...), like states with zero or two '1's. I was not aware that the tools would perform that level of analysis. Where did you learn this? Is this from the vendor's optimization? I suspect the method of one-hot coding I have described would prevent such optimization since each state is an independent FSM, it would be much harder to analyze and determine the various "impossible" states based on the logical analysis. -- Rick From newsfish@newsfish Thu Aug 1 00:33:02 2024 X-Received: by 10.236.50.227 with SMTP id z63mr38996765yhb.4.1427821823733; Tue, 31 Mar 2015 10:10:23 -0700 (PDT) X-Received: by 10.50.79.131 with SMTP id j3mr90344igx.4.1427821823703; Tue, 31 Mar 2015 10:10:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed3a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!q107no911704qgd.1!news-out.google.com!q14ni4346ign.0!nntp.google.com!h15no2604401igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 Mar 2015 10:10:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: KJ Injection-Date: Tue, 31 Mar 2015 17:10:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 28 Xref: news.eternal-september.org comp.lang.vhdl:3689 On Tuesday, March 31, 2015 at 11:50:03 AM UTC-4, rickman wrote: >=20 > I suspect the method of one-hot coding I have described would prevent=20 > such optimization since each state is an independent FSM, it would be=20 > much harder to analyze and determine the various "impossible" states=20 > based on the logical analysis. >=20 One hot encoding is exactly the case one can generate a large number of 'im= possible states'. If you have a four state state machine, and it is implem= ented as one-hot, then you will have four flip flops. Those four flip flop= s can theoretically be in any of 16 states; four 'legit' and 12 'impossible= '. Optimized logic that uses the state bit(s) would only look at the individua= l bit to see if a particular state is active (since that is the primary rea= son for using a one-hot encoding in the first place) and would ignore the o= ther state bits. Those state bits can only be interpreted as 'independent = FSMs' if you ignore the possibility of actually getting into 'impossible st= ates', which given a stray energetic space particle hit could happen theref= ore it is not impossible. Bottom line is that one hot encoding definitely does not prevent any vendor= optimization of the issue being discussed. In fact, the vendor optimizati= on to use one-hot (if not explicitly told to not use), creates more potenti= als for this problem (witness a four state machine having 12 impossible sta= tes). Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Tue, 31 Mar 2015 13:28:39 -0400 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 31 Mar 2015 17:27:46 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3733"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+beSLgkj+4Spikg+FGchzs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:azv9Tz/fhe+WdrhtyDNN89fOn4o= Xref: news.eternal-september.org comp.lang.vhdl:3690 On 3/31/2015 1:10 PM, KJ wrote: > On Tuesday, March 31, 2015 at 11:50:03 AM UTC-4, rickman wrote: >> >> I suspect the method of one-hot coding I have described would prevent >> such optimization since each state is an independent FSM, it would be >> much harder to analyze and determine the various "impossible" states >> based on the logical analysis. >> > > One hot encoding is exactly the case one can generate a large number of 'impossible states'. If you have a four state state machine, and it is implemented as one-hot, then you will have four flip flops. Those four flip flops can theoretically be in any of 16 states; four 'legit' and 12 'impossible'. > > Optimized logic that uses the state bit(s) would only look at the individual bit to see if a particular state is active (since that is the primary reason for using a one-hot encoding in the first place) and would ignore the other state bits. Those state bits can only be interpreted as 'independent FSMs' if you ignore the possibility of actually getting into 'impossible states', which given a stray energetic space particle hit could happen therefore it is not impossible. > > Bottom line is that one hot encoding definitely does not prevent any vendor optimization of the issue being discussed. In fact, the vendor optimization to use one-hot (if not explicitly told to not use), creates more potentials for this problem (witness a four state machine having 12 impossible states). I can't say I follow your reasoning. If the vendor's tools look across all logic for sequential logic that depends on other sequential logic and combines it into a FSM that can be optimized, then nearly every design would be treated as a single FSM. What makes this approach a group of separate FSMs which aren't optimized by the tools is that they are separate signals. How exactly do the tools decide what is a FSM and what is not? Of course I haven't tested this. But then I have never seen a tool perform optimization that throws out valid logic that has inputs and outputs. -- Rick From newsfish@newsfish Thu Aug 1 00:33:02 2024 X-Received: by 10.182.44.161 with SMTP id f1mr47848409obm.33.1427830280553; Tue, 31 Mar 2015 12:31:20 -0700 (PDT) X-Received: by 10.50.129.98 with SMTP id nv2mr110010igb.1.1427830280529; Tue, 31 Mar 2015 12:31:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!209.85.213.216.MISMATCH!h15no2730492igd.0!news-out.google.com!q14ni4436ign.0!nntp.google.com!h15no2730491igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 Mar 2015 12:31:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Subject: Re: Safe FSM From: KJ Injection-Date: Tue, 31 Mar 2015 19:31:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3691 On Tuesday, March 31, 2015 at 1:28:42 PM UTC-4, rickman wrote: >=20 > I can't say I follow your reasoning. If the vendor's tools look across= =20 > all logic for sequential logic that depends on other sequential logic=20 > and combines it into a FSM that can be optimized, then nearly every=20 > design would be treated as a single FSM. What makes this approach a=20 > group of separate FSMs which aren't optimized by the tools is that they= =20 > are separate signals. How exactly do the tools decide what is a FSM and= =20 > what is not? >=20 We could be talking different things since I didn't say anything about look= ing across all logic... For FSMs, I think we're talking about the followin= g type of coding: type t_My_States is (Idle, Do_Something, Do_Something_Important, Done); signal Current_State: t_My_States; ... case Current_State is when Idle=3D> ... when Do_Something =3D> ... when Do_Something_Important=3D> ... when Done =3D> ... end case; The synthesis tools don't have to look to far to see that 'Current_State' i= s a single signal. The tool can then choose to implement that single signa= l as one-hot in which case it will use four flip flops which, in theory, ha= ve 16 different combinations. Only 4 of the 16 are 'valid' in that they ar= e described by the code that was written. The other 12 are 'impossible', '= not valid' etc. that can only be reached by things such as an SEU, timing p= roblem, voltage problem and other things that 'should not happen'. Although the implementation of 'Current_State' is in four flops, those four= are not independent. The logic that gets synthesized takes advantage of t= he fact that it is choosing to implement Current_State as one-hot so any de= pendent logic will only have to look at one bit to decide if it is a partic= ular state or not. If some downstream logic depends on being in the 'Idle'= state than the boolean logic that actually gets implemented will depend on= 'Current_State.Idle' (a single bit), as opposed to using all four bits 'Cu= rrent_State[3..0]'. If you then take the above code and add 'when others=3D> Current_State <=3D= Idle' to the case statement as a method to cover those 'impossible' states= , synthesis tools will generally ignore it because I have already covered a= ll of the possible cases in an earlier 'when ...'.=20 > Of course I haven't tested this. But then I have never seen a tool=20 > perform optimization that throws out valid logic that has inputs and=20 > outputs. >=20 I don't know what you're talking about here. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Tue, 31 Mar 2015 18:40:24 -0400 Organization: A noiseless patient Spider Lines: 103 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 31 Mar 2015 22:39:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22838"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/GMlvnaj7BQkQ/hBqKLCSA" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Cancel-Lock: sha1:0p5ufA2/3X3coxDSjKdP6rmr9T8= Xref: news.eternal-september.org comp.lang.vhdl:3692 On 3/31/2015 3:31 PM, KJ wrote: > On Tuesday, March 31, 2015 at 1:28:42 PM UTC-4, rickman wrote: >> >> I can't say I follow your reasoning. If the vendor's tools look across >> all logic for sequential logic that depends on other sequential logic >> and combines it into a FSM that can be optimized, then nearly every >> design would be treated as a single FSM. What makes this approach a >> group of separate FSMs which aren't optimized by the tools is that they >> are separate signals. How exactly do the tools decide what is a FSM and >> what is not? >> > > We could be talking different things since I didn't say anything about looking across all logic... For FSMs, I think we're talking about the following type of coding: > > type t_My_States is (Idle, Do_Something, Do_Something_Important, Done); > signal Current_State: t_My_States; > .... > case Current_State is > when Idle=> ... > when Do_Something => ... > when Do_Something_Important=> ... > when Done => ... > end case; > > The synthesis tools don't have to look to far to see that 'Current_State' is a single signal. The tool can then choose to implement that single signal as one-hot in which case it will use four flip flops which, in theory, have 16 different combinations. Only 4 of the 16 are 'valid' in that they are described by the code that was written. The other 12 are 'impossible', 'not valid' etc. that can only be reached by things such as an SEU, timing problem, voltage problem and other things that 'should not happen'. > > Although the implementation of 'Current_State' is in four flops, those four are not independent. The logic that gets synthesized takes advantage of the fact that it is choosing to implement Current_State as one-hot so any dependent logic will only have to look at one bit to decide if it is a particular state or not. If some downstream logic depends on being in the 'Idle' state than the boolean logic that actually gets implemented will depend on 'Current_State.Idle' (a single bit), as opposed to using all four bits 'Current_State[3..0]'. > > If you then take the above code and add 'when others=> Current_State <= Idle' to the case statement as a method to cover those 'impossible' states, synthesis tools will generally ignore it because I have already covered all of the possible cases in an earlier 'when ...'. This is exactly my point. Don't code like this. Code the one hot states independently and the tool won't be able to see it as one large FSM. Instead each state will appear as a separate FSM with nothing to be optimized out. Error detection will consist of adding the state bits and if the count is not exactly one, go to a safe state, a signal that sets all the separate state bits to the appropriate value. I supplied code for this earlier, but here is a version I like better based on the transition specification rather than the present state value. FSM : process (Clk, Rst) begin if ('1' = Rst) then StateA <= '1'; StateB <= '0'; StateC <= '0'; StateD <= '0'; . . . StateZ <= '0'; elsif (rising_edge(Clk)) then if ( /state transition condition from X to A/ ) then StateX <= '0'; StateA <= '1'; end if; if ( /state transition condition from A to B/ ) then StateA <= '0'; StateB <= '1'; end if; . . . if ( error condition ) then StateA <= '0'; StateB <= '0'; ... all state signals defined ... StateZ <= '0'; end if; -- Error recovery end if; -- (if Rst) end process FSM; It would be trivial to create and maintain this from a state diagram. There is a one to one mapping of the state transitions to the functional sections of code. Rather than have a huge process, this could be simplified by writing each transition as a procedure. Unfortunately this might be a bit awkward to maintain as each procedure will require a custom list of inputs and outputs in two places in the code. But it might lend itself to some reuse of functions. An advantage of the previous state oriented method is that each signal is only controlled from a single IF statement so there is no interaction between the different sections. In the transition oriented code each state signal is set in one IF statement and reset in another so that there may be some mixing of conditions because the order in which they occur implies priority. Just thinking out loud here... >> Of course I haven't tested this. But then I have never seen a tool >> perform optimization that throws out valid logic that has inputs and >> outputs. >> > I don't know what you're talking about here. I believe someone mentioned that if cases were included for the error states that because the tool understands these states can not be reached it removes the logic for transitioning to "safe" states. I've never seen this behavior. I have only seen logic optimized away because it has either the input or output disconnected. -- Rick From newsfish@newsfish Thu Aug 1 00:33:03 2024 X-Received: by 10.68.134.66 with SMTP id pi2mr48106013pbb.9.1427878131768; Wed, 01 Apr 2015 01:48:51 -0700 (PDT) X-Received: by 10.140.108.38 with SMTP id i35mr541624qgf.3.1427878131511; Wed, 01 Apr 2015 01:48:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!m20no121019iga.0!news-out.google.com!q90ni2qgd.1!nntp.google.com!q107no1043026qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 01:48:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: Thomas Stanka Injection-Date: Wed, 01 Apr 2015 08:48:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3693 Am Dienstag, 31. M=E4rz 2015 17:50:03 UTC+2 schrieb rickman: > I was not aware that the tools would perform that level of analysis.=20 > Where did you learn this? Is this from the vendor's optimization? Just perform structural equivalence check of designs synthesised by Synplif= y (without synkeep or similar), ask yourself why the tool finds differences= even in rather simple counters and than verify the equivalence check patte= rn is right by simulating the netlist. This is not necessary happen the first 1-2 designs, but if you do this seve= ral times you learn what to expect. best regards, Thomas From newsfish@newsfish Thu Aug 1 00:33:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Wed, 1 Apr 2015 11:02:40 +0000 (UTC) Organization: A noiseless patient Spider Lines: 63 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 1 Apr 2015 11:02:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="844"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ApLuDMckBfybMt+2q7AHLZOq7eorXCG0=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:Ok8oMKr+cHkS8MQL1iEGmWDvnC4= Xref: news.eternal-september.org comp.lang.vhdl:3694 On Tue, 31 Mar 2015 18:40:24 -0400, rickman wrote: > On 3/31/2015 3:31 PM, KJ wrote: >> If you then take the above code and add 'when others=> Current_State <= >> Idle' to the case statement as a method to cover those 'impossible' >> states, synthesis tools will generally ignore it because I have already >> covered all of the possible cases in an earlier 'when ...'. > > This is exactly my point. Don't code like this. Code the one hot > states independently and the tool won't be able to see it as one large > FSM. Instead each state will appear as a separate FSM with nothing to > be optimized out. Error detection will consist of adding the state bits > and if the count is not exactly one, go to a safe state, a signal that > sets all the separate state bits to the appropriate value. I supplied > code for this earlier, but here is a version I like better based on the > transition specification rather than the present state value. > > FSM : process (Clk, Rst) > begin > if ('1' = Rst) then > StateA <= '1'; > StateB <= '0'; > StateC <= '0'; > StateD <= '0'; > . > . > . > StateZ <= '0'; I see where you're going with this, making every bit of every state assignment explicit. You could do the same without the clutter, by declaring State to be an array of bits, indexed by A to Z, and then: ------------------------------------------------------------- type State_Index is (A,B,C,...Z); type State_Type is array (State_Index) of bit; signal State : State_Type; constant State_A : State_Type is (A => '1', others => '0'); ... constant State_Z : State_Type is (Z => '1', others => '0'); ------------------------------------------------------------- All boiler plate, hide it in a package. But now your state machine is written as: ------------------------------------------------------------- FSM : process (Clk, Rst) begin if ('1' = Rst) then State <= State_A; elsif Rising_Edge(Clk) then ... ------------------------------------------------------------- all completely compatible with the traditional way of writing a state machine. In other words, we can retrofit your approach to any existing state machine - without any rewrite to them - simply by replacing its State_Type (an enumeration) declaration with the (packaged) declarations above. -- Brian From newsfish@newsfish Thu Aug 1 00:33:03 2024 X-Received: by 10.236.70.234 with SMTP id p70mr48831857yhd.56.1427892235860; Wed, 01 Apr 2015 05:43:55 -0700 (PDT) X-Received: by 10.140.91.47 with SMTP id y44mr80950qgd.39.1427892235845; Wed, 01 Apr 2015 05:43:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!q107no1080219qgd.1!news-out.google.com!q90ni1qgd.1!nntp.google.com!z60no94303qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 05:43:55 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.49.106.57; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 193.49.106.57 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0b0a317c-3f71-467d-aa70-6d18b8ff42bd@googlegroups.com> Subject: Asynchronous MUTEX IN VHDL From: Charles Effiong Injection-Date: Wed, 01 Apr 2015 12:43:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 26 Xref: news.eternal-september.org comp.lang.vhdl:3695 Hi all, I need help. 1. Does anyone knows a gate level implementation of asynchronous metastability filter for mutex ? I couldn't find a gate level description online. 2. I created a MUTEX using two NAND gate. Interface is as below: entity ME is Port ( R1 : in STD_LOGIC; R2 : in STD_LOGIC; G1 : out STD_LOGIC; G2 : out STD_LOGIC); end ME; In my testbench, I have something like this: wait for clock_cycle; R1 <= '1'; wait for clock_cycle; R2 <= '1'; After running simulation, the output G1, G2 is 'U' :( If I change one of R1,R2 to be '0' it works. What could be wrong ? 3. Does anyone knows how to code an asynchronous arbiter that can be used to control a MUX or demux. I'm did the coding but have some problems simulating it. Any help or reference materials would be appreciated. Thanks From newsfish@newsfish Thu Aug 1 00:33:04 2024 X-Received: by 10.50.103.41 with SMTP id ft9mr9699213igb.3.1427899720409; Wed, 01 Apr 2015 07:48:40 -0700 (PDT) X-Received: by 10.140.87.70 with SMTP id q64mr642517qgd.10.1427899720335; Wed, 01 Apr 2015 07:48:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!m20no206137iga.0!news-out.google.com!q90ni4qgd.1!nntp.google.com!z60no113508qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 07:48:40 -0700 (PDT) In-Reply-To: <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: hssig Injection-Date: Wed, 01 Apr 2015 14:48:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3696 Please spare us. I am so tired of reading your confusing and snotty postings. From newsfish@newsfish Thu Aug 1 00:33:04 2024 X-Received: by 10.42.76.145 with SMTP id e17mr74050185ick.34.1427909127351; Wed, 01 Apr 2015 10:25:27 -0700 (PDT) X-Received: by 10.50.1.113 with SMTP id 17mr236658igl.8.1427909127302; Wed, 01 Apr 2015 10:25:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed4a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!l13no380551iga.0!news-out.google.com!db6ni4151igc.0!nntp.google.com!m20no253835iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 10:25:26 -0700 (PDT) In-Reply-To: <0b0a317c-3f71-467d-aa70-6d18b8ff42bd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <0b0a317c-3f71-467d-aa70-6d18b8ff42bd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Asynchronous MUTEX IN VHDL From: KJ Injection-Date: Wed, 01 Apr 2015 17:25:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 18 Xref: news.eternal-september.org comp.lang.vhdl:3697 On Wednesday, April 1, 2015 at 8:43:57 AM UTC-4, Charles Effiong wrote: > > After running simulation, the output G1, G2 is 'U' :( If I change one of R1,R2 to be '0' it works. What could be wrong ? > It's your code and you haven't posted it so it's your problem to figure out. > 3. Does anyone knows how to code an asynchronous arbiter that can be used to control a MUX or demux. I'm did the coding but have some problems simulating it. > Seems pretty simple to me... if (R1 = '1') then G1 <= '1'; G2 <= '0'; else G1 <= '0'; G2 <= R2; end if; Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Non-contiguous Subtypes Date: Wed, 1 Apr 2015 20:50:20 +0000 (UTC) Organization: A noiseless patient Spider Lines: 12 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 1 Apr 2015 20:50:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="1c311ff5f358f6f093526cc26a26a1ec"; logging-data="5735"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mVkIrO/4foGISyfzAnCQ1" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:6ExorhrvEs04I5R1tYtVNwNxxTI= Xref: news.eternal-september.org comp.lang.vhdl:3698 Random question while it's on my mind. So, there's VHDL support for declaring contiguous subtypes. subtype t_index is integer range 0 to 7; Is there any syntax for declaring discontiguous subtypes? Something like: subtype t_axi_datawidth is integer (8, 16, 32, 64, 128, 256, 512, 1024); -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:33:05 2024 X-Received: by 10.50.103.41 with SMTP id ft9mr12148486igb.3.1427931352298; Wed, 01 Apr 2015 16:35:52 -0700 (PDT) X-Received: by 10.50.111.233 with SMTP id il9mr279954igb.13.1427931352283; Wed, 01 Apr 2015 16:35:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no522258iga.0!news-out.google.com!db6ni4365igc.0!nntp.google.com!m20no833iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 16:35:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <622673bb-6d01-45b9-9c66-b896999fc926@googlegroups.com> Subject: Re: Non-contiguous Subtypes From: diogratia@gmail.com Injection-Date: Wed, 01 Apr 2015 23:35:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3699 On Thursday, April 2, 2015 at 9:51:15 AM UTC+13, Rob Gaddi wrote: > Random question while it's on my mind. So, there's VHDL support for=20 > declaring contiguous subtypes. >=20 > subtype t_index is integer range 0 to 7; >=20 > Is there any syntax for declaring discontiguous subtypes? Something like= : >=20 > subtype t_axi_datawidth is integer (8, 16, 32, 64, 128, 256, 512, 1024)= ; No. IEEE Std 1076-2008 5.2 Scalar types, 5.2.1 General: Scalar types consist of enumeration types, integer types, physical types, a= nd floating-point types. Enumeration types and integer types are called dis= crete types. Integer types, floating-point types, and physical types are ca= lled numeric types. All scalar types are ordered; that is, all relational o= perators are predefined for their values. Each value of a discrete or physi= cal type has a position number that is an integer value. --=20 It's that position number which is used for numeric operations. 5.2.3 Integer types, 5.2.3.1 General: An integer type definition defines an integer type whose set of values incl= udes those of the specified range. Integer_type_definition ::=3D range_constraint -- Back to 5.2.1: range_constraint ::=3D range range range ::=3D=20 range_attribute_name | simple_expression direction simple_expression=20 direction ::=3D to | downto -- Only constrained range Back to 5.2.3.1: Integer literals are the literals of an anonymous predefined type that is c= alled universal_integer in this standard. Other integer types have no liter= als. However, for each integer type there exists an implicit conversion tha= t converts a value of type universal_integer into the corresponding value (= if any) of the integer type (see 9.3.6). The position number of an integer value is the corresponding value of the t= ype universal_integer. -- So we have two aspects to a type, position and value. For integer types pos= ition is given as a universal_integer, convertible to the integer type, and= it's position is also tied to universal_integer. =20 While you're proposed subtype is discrete, arithmetic operation results can= 't be expressed in it inclusively, for instance any two of it's values adde= d together don't result in a value of the proposed subtype. 5.2.3.1: The same arithmetic operators are predefined for all integer types (see 9.2= ). It is an error if the execution of such an operation (in particular, an = implicit conversion) cannot deliver the correct result (that is, if the val= ue corresponding to the mathematical result is not a value of the integer t= ype). -- Notice you can't use your subtype values as an enumeration type, an enumera= tion literal is either an identifier or a character literal (5.2.2.1). You could create an enumeration type and use it as an index into a constant= array of integer values: entity axiwidth is end entity; architecture foo of axiwidth is type axi_datawidth is ( AXI_WIDTH8, AXI_WIDTH16, AXI_WIDTH32,=20 AXI_WIDTH64, AXI_WIDTH128, AXI_WIDTH256, AXI_WIDTH_512, AXI_WIDTH1024); type axi_values is array (axi_datawidth) of positive; constant axi_datawidth_value: axi_values :=3D ( 8, 16, 32, 64,= =20 128, 256, 512, 1024);= =20 signal a: integer :=3D axi_datawidth_value(AXI_WIDTH16); begin RESULT: assert FALSE report "a =3D " & integer'image(a) severity NOTE; end architecture; =20 And if you wanted to access them by position of the axi_datawidth type you = could convert position to value by using axi_datawidth'VAL. From newsfish@newsfish Thu Aug 1 00:33:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Wed, 01 Apr 2015 19:38:36 -0400 Organization: A noiseless patient Spider Lines: 71 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 1 Apr 2015 23:37:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="7758"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+o1QrUZkorb0kVgpX2EUcj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:lCqoLQ35iHxT95OZrC+Mwk9+Skg= Xref: news.eternal-september.org comp.lang.vhdl:3700 On 4/1/2015 7:02 AM, Brian Drummond wrote: > On Tue, 31 Mar 2015 18:40:24 -0400, rickman wrote: > >> On 3/31/2015 3:31 PM, KJ wrote: > >>> If you then take the above code and add 'when others=> Current_State <= >>> Idle' to the case statement as a method to cover those 'impossible' >>> states, synthesis tools will generally ignore it because I have already >>> covered all of the possible cases in an earlier 'when ...'. >> >> This is exactly my point. Don't code like this. Code the one hot >> states independently and the tool won't be able to see it as one large >> FSM. Instead each state will appear as a separate FSM with nothing to >> be optimized out. Error detection will consist of adding the state bits >> and if the count is not exactly one, go to a safe state, a signal that >> sets all the separate state bits to the appropriate value. I supplied >> code for this earlier, but here is a version I like better based on the >> transition specification rather than the present state value. >> >> FSM : process (Clk, Rst) >> begin >> if ('1' = Rst) then >> StateA <= '1'; >> StateB <= '0'; >> StateC <= '0'; >> StateD <= '0'; >> . >> . >> . >> StateZ <= '0'; > > I see where you're going with this, making every bit of every state > assignment explicit. > > You could do the same without the clutter, by declaring State to be an > array of bits, indexed by A to Z, and then: > > ------------------------------------------------------------- > type State_Index is (A,B,C,...Z); > type State_Type is array (State_Index) of bit; > > signal State : State_Type; > constant State_A : State_Type is (A => '1', others => '0'); > ... > constant State_Z : State_Type is (Z => '1', others => '0'); > ------------------------------------------------------------- > All boiler plate, hide it in a package. > > But now your state machine is written as: > ------------------------------------------------------------- > FSM : process (Clk, Rst) > begin > if ('1' = Rst) then > State <= State_A; > elsif Rising_Edge(Clk) then ... > ------------------------------------------------------------- > all completely compatible with the traditional way of writing a state > machine. In other words, we can retrofit your approach to any existing > state machine - without any rewrite to them - simply by replacing its > State_Type (an enumeration) declaration with the (packaged) declarations > above. I was never a fan of the "traditional" way of describing a state machien. But my concern would be that your method would not get around the FSM recognition by the tools. You are still using one signal for the state variable, it just happens to have N bits just like any other state variable with more than two bits. -- Rick From newsfish@newsfish Thu Aug 1 00:33:05 2024 X-Received: by 10.236.97.99 with SMTP id s63mr7935790yhf.40.1428146798400; Sat, 04 Apr 2015 04:26:38 -0700 (PDT) X-Received: by 10.51.17.10 with SMTP id ga10mr140142igd.6.1428146798372; Sat, 04 Apr 2015 04:26:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!j5no451261qga.1!news-out.google.com!db6ni6690igc.0!nntp.google.com!l13no599405iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 4 Apr 2015 04:26:37 -0700 (PDT) In-Reply-To: <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <93a688d8-0559-46c6-ac5b-5170f9c1f65e@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 04 Apr 2015 11:26:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 173 Xref: news.eternal-september.org comp.lang.vhdl:3701 On Monday, March 30, 2015 at 2:18:41 AM UTC-7, diog...@gmail.com wrote: > On Sunday, March 29, 2015 at 5:47:01 PM UTC+13, Daniel Kho wrote: > > On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote: > > >=20 > > > Why currently VHDL committee has so many difficulties financially to = get industries into its activities? One most important reason is that VHDL = is now free to use for all related companies and they don't have to make th= eir contributions. > > >=20 > >=20 > > That's the reason why standard bodies have by-laws that make sure any i= nformation submitted or discussed within working groups are not encumbered = by patents. If you are trying to discuss your patent idea within a working = group, you need to declare that the information has been patented. In which= case, the Chair will tell the whole group to not use that information in t= he standardization process. I think this is how it goes for most standard b= odies. > >=20 >=20 > See http://www.eda.org/vasg/docs/Patent_disc_appropriate_topics.pdf Page = 4: >=20 > * The DASC will only accept patented material > under paragraph (a) of IEEE Patent Policy >=20 > Where paragraph (a) is found on PDF Page 2 (Slide #1): >=20 > a) A general disclaimer to the effect that the patentee will not enfo= rce > any of its present or future patent(s) whose use would be required= to=20 > implement either mandatory or optional potions of the proposed IEE= E > standard against any person or entity complying with the standard;= or=20 >=20 >=20 > The VASG P1076 effort falls under these conditions, no one is going to ge= t rich on a standard essential patent required to implement the VHDL standa= rd (nor either Verilog standards also under the auspices of DASC). >=20 > Also note Page 3 (slide #2): >=20 > Inappropriate Topics for IEEE WG Meetings > * Don't discuss licensing terms or conditions > ... -dio, Thank you for your good information.=20 No matter whether or not I get rich through it, I will perfect my invented = method to make contribution to science. I will have another two successive patent applications about the same topic= s to publish in this group to perfect "the systematic method of coding wave= pipelined circuits in HDL" so that it will be used universally in all mode= rn 4-core processors someday, not mention in FPGA. If someone is tired of reading new inventions, please stay away and you are= not forced or flirted to read those "confusing and snotty" inventions. Weng Here are some important sections in my patent application: New concurrent link statement in HDL [0137] In order to let a synthesizer identify which code is a wave-pipel= ining ready code and help check the correctness of connections and paired t= ype between a WPC instantiation and a CPC instantiation, three versions of = new concurrent link statement are suggested to be introduced into HDL. [0138] Here is the definition of new concurrent link statement in bold t= ype based on VHDL-2002:=20 concurrent_statement ::=3D block_statement | link_statement | process_statement | concurrent_procedure_call_statement | concurrent_assertion_statement | concurrent_signal_assignment_statement | component_instantiation_statement | generate_statement link_statement ::=3D [ link_label : ] link_name ( wave_pipelining_component_label ,=20 critical_path_component_label [ , alias_wave_constant_list ] ) ; link_label ::=3D label link_name ::=3D link1 | link2 | link3=20 wave_pipelining_component_label ::=3D label critical_path_component_label ::=3D=20 series_component_label |input_delay_component_label |multiple_copy_component_label series_component_label ::=3D label input_delay_component_label ::=3D label multiple_copy_component_label ::=3D generate_label , copy_component_label copy_component_label ::=3D label label ::=3D identifier [0139] The set of following rules is called link statement mechanism: * Link1 statement links a WPC series_module instantiation with a series CPC= instantiation and optional alias wave constants whose initial value is wav= e constant series_clock_number and which share the wave constant value of t= he linked WPC series_module. * Link2 statement links a WPC input_delay_module instantiation with a serie= s or a feedback CPC instantiation, and optional alias wave constants whose = initial value is either wave constant series_clock_number or input_clock_nu= mber and which share the wave constant value of the linked WPC input_delay_= module. * Link3 statement links a WPC multiple_copy_module instantiation with a gen= erate statement, a series or a feedback CPC instantiation, and optional ali= as wave constants whose initial value is either wave constant series_clock_= number or multiple_copy_number and which share the wave constant value of t= he linked WPC multiple_copy_module. * Wave_pipelining_component_label is the label marking the instantiation of= a WPC series_module, input_delay_module or multiple_copy_module.=20 * Critical_path_component_label is the label marking a CPC instantiation.= =20 o Series_component_label is the label marking the instantiation of a ser= ies CPC linked by a link1 statement. o Input_delay_component_label is the label marking the instantiation of = a series or a feedback CPC linked by a link2 statement. o Multiple_copy_component_label contains two labels, the first one is ge= nerate_label marking a generate statement which generates multiple copied C= PCs, the second is copy_component_label marking the instantiation of one of= multiple copied series or feedback CPCs and linked by a link3 statement.= =20 * Both wave_pipelining_component_label and critical_path_component_label mu= st be located within the concurrent statement area of same architecture bas= ed on VHDL-2002, and can be referenced before they are defined in a link st= atement which is located in the same concurrent statement area.=20 * An alias wave constant must be visible to the link statement it involves. * When a WPC multiple_copy_module is instantiated and linked with a generat= e statement through a link3 statement, the wave constant multiple_copy_numb= er in the multiple_copy_module receives its new initial value through wave = constant mechanism under slow mode and target mode, respectively, and the l= inked generate statement uses the wave constant multiple_copy_number consta= nt value to generate 1 or more CPC under slow mode and target mode, respect= ively. The range used in the generate statement is fixed and must be from 0= to multiple_copy_number-1 or multiple_copy_number-1 downto 0. The following several sections will not be published because it is related = to synthesizing technology: How a synthesizer determines wave constant values for a linked pair of a WP= C and a CPC. How a synthesizer gets wave constant values of a WPC under target mode. How a synthesizer gets an alias wave constant value under target mode. How a designer generates a successful wave-pipelined design in HDL. Thank you for your patient reading. Weng=20 From newsfish@newsfish Thu Aug 1 00:33:06 2024 X-Received: by 10.236.229.233 with SMTP id h99mr13576439yhq.42.1428261141421; Sun, 05 Apr 2015 12:12:21 -0700 (PDT) X-Received: by 10.140.23.163 with SMTP id 32mr133471qgp.13.1428261141343; Sun, 05 Apr 2015 12:12:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no695852qga.1!news-out.google.com!q14ni5765ign.0!nntp.google.com!j5no695850qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 12:12:21 -0700 (PDT) In-Reply-To: <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:a4c6:c67c:efb8:2a28; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:a4c6:c67c:efb8:2a28 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Sun, 05 Apr 2015 19:12:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2975 X-Received-Body-CRC: 284686477 Xref: news.eternal-september.org comp.lang.vhdl:3702 On Tuesday, March 31, 2015 at 11:31:35 AM UTC-4, Weng Tianxiang wrote: > On Tuesday, March 24, 2015 at 7:24:11 PM UTC-7, KJ wrote: > > On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote: > > >=20 > > > Here I publish all source code for public confirmation. > > > > >=20 > > What exactly would you like the public to confirm? Do you have made so= me specific claims? > >=20 > > Given that you have not claimed anything specific, I can only confirm t= he following: > > - It does compile (Modelsim 10.3c) > > - It does synthesize to something (Quartus 14.0; Top level entity=3DCPC= 1; 56 Max II logic elements) > >=20 > > >=20 > > > You may copy this part of code to do simulation by yourself. > > > > >=20 > > Why would I want to simulate it? > >=20 > > Kevin Jennings >=20 > Here is how I claim to increase very-hard-implemented wave pipelined circ= uits to 100% successful rate. >=20 Since you had requested 'public confirmation', the 'public' states that you= r claim can be refuted, not confirmed. Maybe you'll have better luck at US= PTO. Then again, you may actually have a requirement now to disclose this = thread to USPTO as being relevant background information regarding your pro= posed invention. Kevin From newsfish@newsfish Thu Aug 1 00:33:06 2024 X-Received: by 10.236.43.146 with SMTP id l18mr14363399yhb.55.1428261162035; Sun, 05 Apr 2015 12:12:42 -0700 (PDT) X-Received: by 10.140.41.164 with SMTP id z33mr136882qgz.21.1428261161997; Sun, 05 Apr 2015 12:12:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no896142qgd.0!news-out.google.com!k20ni2qgd.0!nntp.google.com!z60no896141qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 12:12:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.216.67.64; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 82.216.67.64 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> Subject: Connect output of inverter to it's input From: Charles Effiong Injection-Date: Sun, 05 Apr 2015 19:12:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2035 X-Received-Body-CRC: 1646991532 Xref: news.eternal-september.org comp.lang.vhdl:3703 Hi, I have this NOT gate code: entity NOTgate is generic (latency : time); Port ( Data_in : in STD_LOGIC; Data_out : out STD_LOGIC); end NOTgate; architecture NOTgate_arch of NOTgate is signal data_temp : STD_LOGIC := '0'; begin process (Data_in) begin data_temp <= NOT Data_in; end process; Data_out <= transport data_temp after latency; end NOTgate_arch; I now want to connect the inverter's output to its input to form a feedback loop. I Created another component as below: entity NOTG is generic (latency : time); Port ( Data_in : in STD_LOGIC); end NOTG; architecture NOTG_arch of NOTG is signal sig_in : STD_LOGIC := '0'; begin sig_in <= Data_in; NOTG0 : Entity work.NOTgate port map( Data_in => sig_in, Data_out => sig_in, ); end NOTG_arch; This doesn't work. Where am I missing it? Thanks From newsfish@newsfish Thu Aug 1 00:33:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.redatomik.org!nntpfeed.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed1-a.proxad.net!nnrp2-2.free.fr!not-for-mail Date: Sun, 05 Apr 2015 22:44:18 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Connect output of inverter to it's input References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> In-Reply-To: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Antivirus: avast! (VPS 150405-1, 05/04/2015), Outbound message X-Antivirus-Status: Clean Lines: 36 Message-ID: <55219ea1$0$3342$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 05 Apr 2015 22:44:18 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1428266658 news-4.free.fr 3342 88.185.146.198:1717 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3704 Le 05/04/2015 21:12, Charles Effiong a écrit : [...] > I now want to connect the inverter's output to its input to form a feedback loop. I Created another component as below: > > entity NOTG is > generic (latency : time); > Port ( > Data_in : in STD_LOGIC); > end NOTG; > > architecture NOTG_arch of NOTG is > signal sig_in : STD_LOGIC := '0'; > begin > sig_in <= Data_in; > > NOTG0 : Entity work.NOTgate > port map( > Data_in => sig_in, > Data_out => sig_in, > ); > end NOTG_arch; > > This doesn't work. Where am I missing it? Thanks What exactly doesn't work ? I see several problems. First, there shouldn't be a comma after data_out => sig_in since it's the last association of the list. This is where you close the parenthesis. Second, you create two drivers on sig_in, one is the entity input, the other is the not gate output. What exactly do you think you're doing ? Third, I don't know how the tool you're using optimizes the code but basically, you're trying to drive an input through sig_in. This doesn't work. Last, are you simulating this or trying to synthesize it ? (hint : synthesis won't work) Nicolas From newsfish@newsfish Thu Aug 1 00:33:06 2024 X-Received: by 10.182.97.2 with SMTP id dw2mr14426660obb.0.1428268311722; Sun, 05 Apr 2015 14:11:51 -0700 (PDT) X-Received: by 10.140.47.56 with SMTP id l53mr134216qga.25.1428268311614; Sun, 05 Apr 2015 14:11:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no1268633iga.0!news-out.google.com!k20ni2qgd.0!nntp.google.com!z60no913473qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 14:11:51 -0700 (PDT) In-Reply-To: <55219ea1$0$3342$426a34cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.216.67.64; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 82.216.67.64 References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Connect output of inverter to it's input From: Charles Effiong Injection-Date: Sun, 05 Apr 2015 21:11:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3705 On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote: > Le 05/04/2015 21:12, Charles Effiong a =E9crit : > [...] > > I now want to connect the inverter's output to its input to form a feed= back loop. I Created another component as below: > > > > entity NOTG is > > generic (latency : time); > > Port ( > > Data_in : in STD_LOGIC); > > end NOTG; > > > > architecture NOTG_arch of NOTG is > > signal sig_in : STD_LOGIC :=3D '0'; > > begin > > sig_in <=3D Data_in; > > > > NOTG0 : Entity work.NOTgate > > port map( > > Data_in =3D> sig_in, =09 > > Data_out =3D> sig_in, > > ); > > end NOTG_arch; > > > > This doesn't work. Where am I missing it? Thanks >=20 > What exactly doesn't work ? I see several problems. > First, there shouldn't be a comma after data_out =3D> sig_in since it's= =20 > the last association of the list. This is where you close the parenthesis= . > Second, you create two drivers on sig_in, one is the entity input, the=20 > other is the not gate output. What exactly do you think you're doing ? > Third, I don't know how the tool you're using optimizes the code but=20 > basically, you're trying to drive an input through sig_in. This doesn't= =20 > work. > Last, are you simulating this or trying to synthesize it ? (hint :=20 > synthesis won't work) >=20 > Nicolas Thanks @Nicolas.=20 "First, there shouldn't be a comma after data_out =3D> sig_in since it's=20 the last association of the list" That was a typo, I fixed that but it still doesn't work.=20 Basically, I want to connect the inverter's output to it's input so as to f= orm a feed back loop. What should I do ? From newsfish@newsfish Thu Aug 1 00:33:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 05 Apr 2015 19:01:47 -0500 Date: Mon, 06 Apr 2015 01:01:47 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Connect output of inverter to it's input References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Message-ID: Lines: 58 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-zigwmTWLpNhTEkAZwGuYCDR6F9BmUWHfSAs692VBBzupUw7R9HYMvD7nBY1RtbeWkE/pYZqPI2S9V3J!vuzzOGsxEb2LbXGVDm0JQRFAQ2yT4EL9zFbdslmsTwSrmJt720Tx1NLrswaPNZAWszS8mzR3LvxT!Zgh3K7R5Csl2Ye6D0ayNwECE0g== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2973 Xref: news.eternal-september.org comp.lang.vhdl:3706 On 05/04/15 22:11, Charles Effiong wrote: > On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote: >> Le 05/04/2015 21:12, Charles Effiong a crit : >> What exactly doesn't work ? I see several problems. >> First, there shouldn't be a comma after data_out => sig_in since it's >> the last association of the list. This is where you close the parenthesis. >> Second, you create two drivers on sig_in, one is the entity input, the >> other is the not gate output. What exactly do you think you're doing ? >> Third, I don't know how the tool you're using optimizes the code but >> basically, you're trying to drive an input through sig_in. This doesn't >> work. >> Last, are you simulating this or trying to synthesize it ? (hint : >> synthesis won't work) >> >> Nicolas > > Thanks @Nicolas. > > "First, there shouldn't be a comma after data_out => sig_in since it's > the last association of the list" > > That was a typo, I fixed that but it still doesn't work. > > Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ? > Don't you just want entity NOTG is generic (latency : time); Port ( Data_in : in STD_LOGIC); end NOTG; architecture NOTG_arch of NOTG is signal sig_in : STD_LOGIC := '0'; begin -- sig_in <= Data_in; -- <====== ?? NOTG0 : Entity work.NOTgate generic map (latency => latency) -- <======= you forgot this port map( Data_in => sig_in, Data_out => sig_in ); end NOTG_arch; ? I'm not sure what Data_in is for? Alan -- Alan Fitch From newsfish@newsfish Thu Aug 1 00:33:07 2024 X-Received: by 10.69.13.226 with SMTP id fb2mr14786132pbd.0.1428286091447; Sun, 05 Apr 2015 19:08:11 -0700 (PDT) X-Received: by 10.50.176.200 with SMTP id ck8mr60121igc.12.1428286091413; Sun, 05 Apr 2015 19:08:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!l13no1348347iga.0!news-out.google.com!db6ni8110igc.0!nntp.google.com!m20no1114962iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 19:08:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: diogratia@gmail.com Injection-Date: Mon, 06 Apr 2015 02:08:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3707 On Thursday, April 2, 2015 at 3:48:44 AM UTC+13, hssig wrote: > Please spare us. I am so tired of reading your confusing and snotty postings. hssig - Water off a ducks back. He didn't take the hint. It seems no matter how anyone attempts to discourage him he continues on like some dreary (in an Edgar Allan Poe sense) Energizer bunny. From newsfish@newsfish Thu Aug 1 00:33:08 2024 X-Received: by 10.50.43.229 with SMTP id z5mr16234698igl.3.1428294535005; Sun, 05 Apr 2015 21:28:55 -0700 (PDT) X-Received: by 10.50.66.141 with SMTP id f13mr630936igt.17.1428294534981; Sun, 05 Apr 2015 21:28:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no1374704iga.0!news-out.google.com!db6ni8267igc.0!nntp.google.com!l13no1374694iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 21:28:54 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.16.22.65; posting-account=B-IhCwoAAACJWXsdr6tDUzWsruhD9tjI NNTP-Posting-Host: 117.16.22.65 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c78fa9c-1452-42e8-8df5-f6b2f01263a8@googlegroups.com> Subject: Graduate Research Assistantship at the Computer Systems Lab, College of Electronics and Information Engineering, Chosun University, Gwangju, Republic of Korea From: Olufemi Adeluyi Injection-Date: Mon, 06 Apr 2015 04:28:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3708 Graduate Research Assistantship at the Computer Systems Lab, College of Ele= ctronics and Information Engineering, Chosun University, Gwangju, Republic = of Korea =3D=3D=3D We seek skillful, hard working and highly motivated candidates with good cr= edentials to join our dynamic international research team as PhD or Integra= ted MSc-PhD students. There are vacancies in the following areas of focus: a. Configurable Computing b. Embedded Computing c. Self-Aware Computing For a Fall Semester (September 1, 2015) admission, interested applicants sh= ould apply by Monday, April 27, 2015=20 An applicant must meet the following requirements: * Hold a Bachelor's or Master's degree by September 1, 2015 o For an Integrated MSc-PhD program: students should hold a Bachelor's deg= ree or a diploma that is equivalent to or higher than Bachelor's degree o For a Doctoral program: students should hold a Master's degree or a diplo= ma that is equivalent to or higher than Master's degree. * Important Requirements: o Good background in the listed area(s) of research o Good programming skills o Good English language skills- written and oral (For applicants whose moth= er tongue is not English: IELTS 6.5 or higher OR TOEFL IBT 90) o Good ability to cooperate with others in a multicultural environment o A cumulative GPA score of 80% or higher Application Procedure =3D=3D=3D Interested applicants should send the following to Prof Lee, Jeong-A, Depa= rtment of Computer Engineering by the application dead= line. 1) Study plan (clearly stating the research topics you are interested in. W= e would like to know your research interests and their relation to the give= n research areas) 2) Academic transcripts 3) Brief summary of most recent thesis and the status (eg accepted, in prog= ress, submitted, etc) 4) CV (to include names, date of birth, nationality, gender, contact detail= s, education, work experience, publications and referees) Only electronic applications are accepted. All items should be merged as on= e pdf file with the name Familyname_Firstname_Chosun_App2015.pdf. and must = be sent by the stated date with "2015 Application for Research Assistantshi= p at Computer Systems Lab" as the e-mail subject. From newsfish@newsfish Thu Aug 1 00:33:08 2024 X-Received: by 10.50.117.8 with SMTP id ka8mr35023800igb.6.1428309419367; Mon, 06 Apr 2015 01:36:59 -0700 (PDT) X-Received: by 10.140.18.237 with SMTP id 100mr153931qgf.8.1428309419239; Mon, 06 Apr 2015 01:36:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no1153986iga.0!news-out.google.com!k20ni2qgd.0!nntp.google.com!z60no975763qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 6 Apr 2015 01:36:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.216.67.64; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 82.216.67.64 References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7695d6c6-0585-4f1e-809e-b18eff0cc4cd@googlegroups.com> Subject: Re: Connect output of inverter to it's input From: Charles Effiong Injection-Date: Mon, 06 Apr 2015 08:36:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3709 On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote: > On 05/04/15 22:11, Charles Effiong wrote: > > On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote: > >> Le 05/04/2015 21:12, Charles Effiong a =E9crit : > > >> What exactly doesn't work ? I see several problems. > >> First, there shouldn't be a comma after data_out =3D> sig_in since it'= s=20 > >> the last association of the list. This is where you close the parenthe= sis. > >> Second, you create two drivers on sig_in, one is the entity input, the= =20 > >> other is the not gate output. What exactly do you think you're doing ? > >> Third, I don't know how the tool you're using optimizes the code but= =20 > >> basically, you're trying to drive an input through sig_in. This doesn'= t=20 > >> work. > >> Last, are you simulating this or trying to synthesize it ? (hint :=20 > >> synthesis won't work) > >> > >> Nicolas > >=20 > > Thanks @Nicolas.=20 > >=20 > > "First, there shouldn't be a comma after data_out =3D> sig_in since it'= s=20 > > the last association of the list" > >=20 > > That was a typo, I fixed that but it still doesn't work.=20 > >=20 > > Basically, I want to connect the inverter's output to it's input so as = to form a feed back loop. What should I do ? > >=20 >=20 > Don't you just want >=20 > entity NOTG is > generic (latency : time); > Port ( > Data_in : in STD_LOGIC); > end NOTG; >=20 > architecture NOTG_arch of NOTG is > signal sig_in : STD_LOGIC :=3D '0'; > begin >=20 > -- sig_in <=3D Data_in; -- <=3D=3D=3D=3D=3D=3D ?? >=20 > NOTG0 : Entity work.NOTgate > generic map (latency =3D> latency) -- <=3D=3D=3D=3D=3D=3D=3D yo= u forgot this > port map( > Data_in =3D> sig_in, =09 > Data_out =3D> sig_in > ); > end NOTG_arch; >=20 > ? >=20 > I'm not sure what Data_in is for? >=20 > Alan >=20 >=20 > --=20 > Alan Fitch Thanks @Alan. I want an initial entry point into the circuit, hence "Data_i= n" I guess this is wrong. Also how can I connect the NOT gate output to it'= s input to form a loop? From newsfish@newsfish Thu Aug 1 00:33:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 06 Apr 2015 08:29:07 -0500 Date: Mon, 06 Apr 2015 14:29:07 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Connect output of inverter to it's input References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> <7695d6c6-0585-4f1e-809e-b18eff0cc4cd@googlegroups.com> In-Reply-To: <7695d6c6-0585-4f1e-809e-b18eff0cc4cd@googlegroups.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Message-ID: Lines: 73 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-kYJgJKtF9CSLKdvAy2mUEYc2k2QLasTVgLgX/Ub6SxEnmIwCCVSanN4/iX0ACh4gJGyKKY2AXQTC6g7!Zs+sRR/utFHCB8Ul6SHX/Cm9osESHjKfbXARA3lVngbXYgk+xg58X3Re780bjwnNX7iE2U14ddjv!1mbd/YFMMV6O0EkyFT5LxHo6mg== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3665 Xref: news.eternal-september.org comp.lang.vhdl:3710 On 06/04/15 09:36, Charles Effiong wrote: > On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote: >> On 05/04/15 22:11, Charles Effiong wrote: >>> On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote: >>>> Le 05/04/2015 21:12, Charles Effiong a crit : >> >>>> What exactly doesn't work ? I see several problems. >>>> First, there shouldn't be a comma after data_out => sig_in since it's >>>> the last association of the list. This is where you close the parenthesis. >>>> Second, you create two drivers on sig_in, one is the entity input, the >>>> other is the not gate output. What exactly do you think you're doing ? >>>> Third, I don't know how the tool you're using optimizes the code but >>>> basically, you're trying to drive an input through sig_in. This doesn't >>>> work. >>>> Last, are you simulating this or trying to synthesize it ? (hint : >>>> synthesis won't work) >>>> >>>> Nicolas >>> >>> Thanks @Nicolas. >>> >>> "First, there shouldn't be a comma after data_out => sig_in since it's >>> the last association of the list" >>> >>> That was a typo, I fixed that but it still doesn't work. >>> >>> Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ? >>> >> >> Don't you just want >> >> entity NOTG is >> generic (latency : time); >> Port ( >> Data_in : in STD_LOGIC); >> end NOTG; >> >> architecture NOTG_arch of NOTG is >> signal sig_in : STD_LOGIC := '0'; >> begin >> >> -- sig_in <= Data_in; -- <====== ?? >> >> NOTG0 : Entity work.NOTgate >> generic map (latency => latency) -- <======= you forgot this >> port map( >> Data_in => sig_in, >> Data_out => sig_in >> ); >> end NOTG_arch; >> >> ? >> >> I'm not sure what Data_in is for? >> >> Alan >> >> >> -- >> Alan Fitch > > Thanks @Alan. I want an initial entry point into the circuit, hence "Data_in" I guess this is wrong. Also how can I connect the NOT gate output to it's input to form a loop? > I don't know what you mean by "initial entry point". I showed you how to connect the input to the output above, regards Alan -- Alan Fitch From newsfish@newsfish Thu Aug 1 00:33:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp4-2.free.fr!not-for-mail Date: Mon, 06 Apr 2015 16:30:01 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Connect output of inverter to it's input References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Antivirus: avast! (VPS 150406-0, 06/04/2015), Outbound message X-Antivirus-Status: Clean Lines: 8 Message-ID: <55229866$0$3191$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 06 Apr 2015 16:29:59 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1428330599 news-1.free.fr 3191 88.185.146.198:1437 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3711 Le 05/04/2015 23:11, Charles Effiong a écrit : > That was a typo, I fixed that but it still doesn't work. You still don't say what exactly doesn't work. That's like going to your doctor and telling him "Doctor, I'm sick" and hoping he'll cure you with that much information. Nicolas From newsfish@newsfish Thu Aug 1 00:33:09 2024 X-Received: by 10.182.44.199 with SMTP id g7mr25537145obm.11.1428421653984; Tue, 07 Apr 2015 08:47:33 -0700 (PDT) X-Received: by 10.50.90.178 with SMTP id bx18mr77300igb.13.1428421653968; Tue, 07 Apr 2015 08:47:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no2083307iga.0!news-out.google.com!n7ni1259igk.0!nntp.google.com!l13no2083297iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Apr 2015 08:47:33 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9e5eb9d1-72f2-4894-b3fd-0c2233dbb3ea@googlegroups.com> Subject: What is wrong tihis function code? From: fl Injection-Date: Tue, 07 Apr 2015 15:47:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3712 Hi, I am learning to write a VHDL function code. Modelsim complains that something wrong at function line. The code is: library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; function s1qrt ( d : unsigned ) return unsigned is variable a : unsigned(31 downto 0) := d; --original input. variable q : unsigned(15 downto 0) := (others => '0'); --result. variable left, right, r : unsigned(17 downto 0):= (others => '0'); --input to adder/sub.r-remainder. variable i : integer := 0; begin -- for i in 0 to 15 loop right(0) := '1'; right(1) := r(17); right(17 downto 2) := q; left(1 downto 0) := a(31 downto 30); left(17 downto 2) := r(15 downto 0); a(31 downto 2) := a(29 downto 0); --shifting by 2 bit. if ( r(17) = '1') then r := left + right; else r := left - right; end if; q(15 downto 1) := q(14 downto 0); q(0) := not r(17); -- end loop; return q; end s1qrt; I cannot make it out what is wrong. Could you help me? Thanks, From newsfish@newsfish Thu Aug 1 00:33:09 2024 X-Received: by 10.70.48.206 with SMTP id o14mr24960286pdn.1.1428430422699; Tue, 07 Apr 2015 11:13:42 -0700 (PDT) X-Received: by 10.50.57.104 with SMTP id h8mr98724igq.15.1428430422663; Tue, 07 Apr 2015 11:13:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no2150315iga.0!news-out.google.com!db6ni9744igc.0!nntp.google.com!l13no2150311iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Apr 2015 11:13:42 -0700 (PDT) In-Reply-To: <9e5eb9d1-72f2-4894-b3fd-0c2233dbb3ea@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <9e5eb9d1-72f2-4894-b3fd-0c2233dbb3ea@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6b9af879-90bf-4d3c-af35-f4f37454479e@googlegroups.com> Subject: Re: What is wrong tihis function code? From: KJ Injection-Date: Tue, 07 Apr 2015 18:13:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3713 On Tuesday, April 7, 2015 at 11:47:37 AM UTC-4, fl wrote: > Hi, > I am learning to write a VHDL function code. Modelsim complains that something > wrong at function line. The code is: > > library IEEE; > use IEEE.std_logic_1164.all; > use ieee.numeric_std.all; > function s1qrt ( d : unsigned ) return unsigned is > variable a : unsigned(31 downto 0) := d; --original input. > variable q : unsigned(15 downto 0) := (others => '0'); --result. > variable left, right, r : unsigned(17 downto 0):= (others => '0'); --input to adder/sub.r-remainder. > variable i : integer := 0; > begin > -- for i in 0 to 15 loop > right(0) := '1'; > right(1) := r(17); > right(17 downto 2) := q; > left(1 downto 0) := a(31 downto 30); > left(17 downto 2) := r(15 downto 0); > a(31 downto 2) := a(29 downto 0); --shifting by 2 bit. > if ( r(17) = '1') then > r := left + right; > else > r := left - right; > end if; > > q(15 downto 1) := q(14 downto 0); > q(0) := not r(17); > -- end loop; > return q; > > end s1qrt; > > I cannot make it out what is wrong. Could you help me? > > Thanks, Functions must always be embedded within something such as a package or an entity/architecture. The general hierarchy is: - entity: This will define the interface (i.e. inputs and outputs) of a design - architecture: This defines the logic implemented given the entity I/O. A function can be defined within an architecture or within a process. Below shows where it would go. Functions can also be defined in packages, but let's defer that for now entity foo is port map(....) end foo; architecture rtl of foo is function s1qrt ( d : unsigned ) return unsigned is ... end function s1qrt; begin process(...) function s1qrt ( d : unsigned ) return unsigned is ... end function s1qrt; begin end process; end rtl; Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:09 2024 X-Received: by 10.43.178.201 with SMTP id ox9mr25880533icc.12.1428579549941; Thu, 09 Apr 2015 04:39:09 -0700 (PDT) X-Received: by 10.140.30.118 with SMTP id c109mr424268qgc.15.1428579549799; Thu, 09 Apr 2015 04:39:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no2965906iga.0!news-out.google.com!k20ni70qgd.0!nntp.google.com!j5no511671qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Apr 2015 04:39:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.49.106.57; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 193.49.106.57 References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> <7695d6c6-0585-4f1e-809e-b18eff0cc4cd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Connect output of inverter to it's input From: Charles Effiong Injection-Date: Thu, 09 Apr 2015 11:39:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3714 On Monday, April 6, 2015 at 3:29:09 PM UTC+2, Alan Fitch wrote: > On 06/04/15 09:36, Charles Effiong wrote: > > On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote: > >> On 05/04/15 22:11, Charles Effiong wrote: > >>> On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote= : > >>>> Le 05/04/2015 21:12, Charles Effiong a =E9crit : > >> > >>>> What exactly doesn't work ? I see several problems. > >>>> First, there shouldn't be a comma after data_out =3D> sig_in since i= t's=20 > >>>> the last association of the list. This is where you close the parent= hesis. > >>>> Second, you create two drivers on sig_in, one is the entity input, t= he=20 > >>>> other is the not gate output. What exactly do you think you're doing= ? > >>>> Third, I don't know how the tool you're using optimizes the code but= =20 > >>>> basically, you're trying to drive an input through sig_in. This does= n't=20 > >>>> work. > >>>> Last, are you simulating this or trying to synthesize it ? (hint := =20 > >>>> synthesis won't work) > >>>> > >>>> Nicolas > >>> > >>> Thanks @Nicolas.=20 > >>> > >>> "First, there shouldn't be a comma after data_out =3D> sig_in since i= t's=20 > >>> the last association of the list" > >>> > >>> That was a typo, I fixed that but it still doesn't work.=20 > >>> > >>> Basically, I want to connect the inverter's output to it's input so a= s to form a feed back loop. What should I do ? > >>> > >> > >> Don't you just want > >> > >> entity NOTG is > >> generic (latency : time); > >> Port ( > >> Data_in : in STD_LOGIC); > >> end NOTG; > >> > >> architecture NOTG_arch of NOTG is > >> signal sig_in : STD_LOGIC :=3D '0'; > >> begin > >> > >> -- sig_in <=3D Data_in; -- <=3D=3D=3D=3D=3D=3D ?? > >> > >> NOTG0 : Entity work.NOTgate > >> generic map (latency =3D> latency) -- <=3D=3D=3D=3D=3D=3D=3D= you forgot this > >> port map( > >> Data_in =3D> sig_in, =09 > >> Data_out =3D> sig_in > >> ); > >> end NOTG_arch; > >> > >> ? > >> > >> I'm not sure what Data_in is for? > >> > >> Alan > >> > >> > >> --=20 > >> Alan Fitch > >=20 > > Thanks @Alan. I want an initial entry point into the circuit, hence "Da= ta_in" I guess this is wrong. Also how can I connect the NOT gate output to= it's input to form a loop? > >=20 >=20 > I don't know what you mean by "initial entry point". > I showed you how to connect the input to the output above, >=20 > regards > Alan >=20 >=20 > --=20 > Alan Fitch Hi @Alan thanks, I figured it out From newsfish@newsfish Thu Aug 1 00:33:10 2024 X-Received: by 10.236.216.52 with SMTP id f50mr25122647yhp.13.1428579725019; Thu, 09 Apr 2015 04:42:05 -0700 (PDT) X-Received: by 10.140.41.164 with SMTP id z33mr422163qgz.21.1428579724963; Thu, 09 Apr 2015 04:42:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no513081qgd.0!news-out.google.com!k20ni71qgd.0!nntp.google.com!z60no513078qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Apr 2015 04:42:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.49.106.57; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 193.49.106.57 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: 2 to 1 dual rail mux From: Charles Effiong Injection-Date: Thu, 09 Apr 2015 11:42:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:3715 Hi all, I need to implement a 1 bit "2 to 1 dual rail mux". I successfully implemented 2 to 1 mux using bundled data protocol but it doesn't suit my purpose. Any help or link to tutorials that could help would be appreciated. Thanks From newsfish@newsfish Thu Aug 1 00:33:10 2024 X-Received: by 10.140.145.199 with SMTP id 190mr21317343qhr.2.1428611574159; Thu, 09 Apr 2015 13:32:54 -0700 (PDT) X-Received: by 10.140.43.7 with SMTP id d7mr458710qga.17.1428611574103; Thu, 09 Apr 2015 13:32:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no598277qgd.0!news-out.google.com!k20ni79qgd.0!nntp.google.com!z60no598275qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Apr 2015 13:32:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.216.67.64; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 82.216.67.64 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <80c3f984-f079-4aaf-ac96-3a697c3e270f@googlegroups.com> Subject: Re: 2 to 1 dual rail mux From: Charles Effiong Injection-Date: Thu, 09 Apr 2015 20:32:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1562 X-Received-Body-CRC: 1380614350 Xref: news.eternal-september.org comp.lang.vhdl:3716 On Thursday, April 9, 2015 at 1:42:06 PM UTC+2, Charles Effiong wrote: > Hi all, > > I need to implement a 1 bit "2 to 1 dual rail mux". I successfully implemented 2 to 1 mux using bundled data protocol but it doesn't suit my purpose. > > Any help or link to tutorials that could help would be appreciated. > > Thanks Hi all, I figured out how to create an n bit dual rail mux. Contact me if you are interested in the implementation. Regards From newsfish@newsfish Thu Aug 1 00:33:10 2024 X-Received: by 10.182.27.139 with SMTP id t11mr2196706obg.38.1428733256115; Fri, 10 Apr 2015 23:20:56 -0700 (PDT) X-Received: by 10.140.100.136 with SMTP id s8mr66129qge.2.1428733255967; Fri, 10 Apr 2015 23:20:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no2564928iga.0!news-out.google.com!k20ni104qgd.0!nntp.google.com!j5no830740qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Apr 2015 23:20:55 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6c877065-28fb-40bc-b675-dc4417fcf139@googlegroups.com> Subject: Does anybody use systemc instead of VHDL From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 06:20:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3717 Hi I just wanted to know if people use systemc instead VHDL. Systemc can be used for cycle accurate simulation, where it can replace RTL. In this mode test-benches will usually take advantage of C++ and SCV (for writing constraints). For big designs where RTL completion takes a lot of time, systemc can be used for LT or AT simulations ( Loosely Timed, Approximately Timed TLM). Pini From newsfish@newsfish Thu Aug 1 00:33:11 2024 X-Received: by 10.42.58.69 with SMTP id g5mr9117431ich.14.1428760354489; Sat, 11 Apr 2015 06:52:34 -0700 (PDT) X-Received: by 10.140.29.119 with SMTP id a110mr80671qga.20.1428760353319; Sat, 11 Apr 2015 06:52:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no2653429iga.0!news-out.google.com!a41ni58qgf.1!nntp.google.com!z60no891369qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 06:52:33 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: implementing list (is access record) From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 13:52:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3718 I would like to share this work example: "This examples demonstrates how to create lists in VHDL. This may be useful in implementing a FIFO quickly in a test-bench. I used list style coding to read an unknown number of bytes, during simulation at time 0, from a file. The data is to be later driven to a DUT." http://bknpk.ddns.net/my_web/SDIO/vhdl_is_access_lists.html From newsfish@newsfish Thu Aug 1 00:33:11 2024 X-Received: by 10.236.63.230 with SMTP id a66mr8296967yhd.51.1428760883530; Sat, 11 Apr 2015 07:01:23 -0700 (PDT) X-Received: by 10.140.20.40 with SMTP id 37mr84924qgi.26.1428760883484; Sat, 11 Apr 2015 07:01:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no891711qga.1!news-out.google.com!k20ni108qgd.0!nntp.google.com!j5no891707qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 07:01:23 -0700 (PDT) In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5e146ba4-c39a-4b40-b692-e6774fe18415@googlegroups.com> Subject: Re: c-language to VHDL converter From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 14:01:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1970 X-Received-Body-CRC: 1290841998 Xref: news.eternal-september.org comp.lang.vhdl:3719 On Wednesday, March 4, 2015 at 10:38:38 AM UTC+2, Sai Jaswanth wrote: > hi friends can any one help me in knowing how to convert the c-code to VH= DL directly by any software. (or) can we compile C-code in xilinx IDE? Have you considered systemc flow. Systemc is a synthesis-able sub-class of = C++. It can be used for cycle accurate simulation and there are commercial = synthesis tools. Systemc is also used to create pre-RTL model for simulati= on (loosely-timed or approximate timed) models. If your design is purely C++ you can use the free OSCI simulator. Its insta= llation is simple (on debian): http://bknpk.ddns.net/my_web/SystemC_MyFirst/sysc2_3_0Nscv_install.html It comes with SCV, which allows to write nice constraints: http://bknpk.ddns.net/my_web/SystemC_MyFirst/scv_cmp_err_pop_constraint.htm= l From newsfish@newsfish Thu Aug 1 00:33:11 2024 X-Received: by 10.66.237.140 with SMTP id vc12mr9579180pac.44.1428778169989; Sat, 11 Apr 2015 11:49:29 -0700 (PDT) X-Received: by 10.140.87.70 with SMTP id q64mr93573qgd.10.1428778169730; Sat, 11 Apr 2015 11:49:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no2734484iga.0!news-out.google.com!a41ni65qgf.1!nntp.google.com!z60no940262qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:49:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <650b67e1-5ade-410d-a92d-da8ac431bbee@googlegroups.com> Subject: Re: Random Number Generator From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:49:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3720 On Thursday, July 10, 1997 at 10:00:00 AM UTC+3, Tim Holmes wrote: > Could anyone tell me how to create a "random" number generator in > VHDL. I imagine that the only method is to use a LFSR approach with > a seed. > > If there are any other ideas, then please let me know. > > Cheers. > > Tim > Hewlett Packard This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way. ... library my_lib; use my_lib.my_package.all; ... signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000"; signal rand_packet_delayi: integer; ... rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay); --write(my_line, rand_packet_delay'path_name); --write(my_line, string'(" ")); --hwrite(my_line, rand_packet_delay); --write(my_line, string'(" ")); --write(my_line, now); --writeline(output, my_line); --packet send ended if(unsigned(rand_packet_delay) > 3) then rand_packet_delayi <= conv_integer(rand_packet_delay); else rand_packet_delayi <= conv_integer(rand_packet_delay) + 3; end if; for j in 1 to rand_packet_delayi loop wait until rx_clk'event and rx_clk = '1'; end loop; Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. Please visit me at http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html From newsfish@newsfish Thu Aug 1 00:33:12 2024 X-Received: by 10.66.182.166 with SMTP id ef6mr9441699pac.42.1428778224601; Sat, 11 Apr 2015 11:50:24 -0700 (PDT) X-Received: by 10.140.101.148 with SMTP id u20mr93052qge.5.1428778224332; Sat, 11 Apr 2015 11:50:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no4050317iga.0!news-out.google.com!k20ni111qgd.0!nntp.google.com!j5no939181qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:50:24 -0700 (PDT) In-Reply-To: <6q6ci5$9na$1@o.online.no> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: <6q6ci5$9na$1@o.online.no> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: random integer generator From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:50:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3721 On Tuesday, August 4, 1998 at 10:00:00 AM UTC+3, Jon Eirik Sternang wrote: > Does anyone have a random generator that returns > integers between [a,b] (i.e. returns a integer > value between a and b) > > thanks > > Jon Eirik This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way. ... library my_lib; use my_lib.my_package.all; ... signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000"; signal rand_packet_delayi: integer; ... rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay); --write(my_line, rand_packet_delay'path_name); --write(my_line, string'(" ")); --hwrite(my_line, rand_packet_delay); --write(my_line, string'(" ")); --write(my_line, now); --writeline(output, my_line); --packet send ended if(unsigned(rand_packet_delay) > 3) then rand_packet_delayi <= conv_integer(rand_packet_delay); else rand_packet_delayi <= conv_integer(rand_packet_delay) + 3; end if; for j in 1 to rand_packet_delayi loop wait until rx_clk'event and rx_clk = '1'; end loop; Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. Please check http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html From newsfish@newsfish Thu Aug 1 00:33:12 2024 X-Received: by 10.66.101.100 with SMTP id ff4mr9522900pab.24.1428778272832; Sat, 11 Apr 2015 11:51:12 -0700 (PDT) X-Received: by 10.140.108.229 with SMTP id j92mr95326qgf.27.1428778272574; Sat, 11 Apr 2015 11:51:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no4050693iga.0!news-out.google.com!k20ni111qgd.0!nntp.google.com!j5no939239qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:51:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <88cfa1bb-4707-482e-90d6-26960aafc088@googlegroups.com> Subject: Re: Random Number Generator in VHDL From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:51:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3722 On Saturday, January 20, 1996 at 10:00:00 AM UTC+2, Lynn West wrote: > Is there a simple way to generate random numbers (preferably both > itegers and bit_vector or std_logic_vector type) in VHDL. I seem to > vaguely remember such but cannot find it in my books. (I have not yet > figured out how to master access to the FAQ for this newsgroup, so > cannot look there). > > Obvously something could be conjured up with a set of differently-timed > clocks, but I am hoping for something simpler than that. > > Thanks, > > Lynn West This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way. ... library my_lib; use my_lib.my_package.all; ... signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000"; signal rand_packet_delayi: integer; ... rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay); --write(my_line, rand_packet_delay'path_name); --write(my_line, string'(" ")); --hwrite(my_line, rand_packet_delay); --write(my_line, string'(" ")); --write(my_line, now); --writeline(output, my_line); --packet send ended if(unsigned(rand_packet_delay) > 3) then rand_packet_delayi <= conv_integer(rand_packet_delay); else rand_packet_delayi <= conv_integer(rand_packet_delay) + 3; end if; for j in 1 to rand_packet_delayi loop wait until rx_clk'event and rx_clk = '1'; end loop; Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. Please read also http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html From newsfish@newsfish Thu Aug 1 00:33:12 2024 X-Received: by 10.182.246.67 with SMTP id xu3mr9873475obc.18.1428778366637; Sat, 11 Apr 2015 11:52:46 -0700 (PDT) X-Received: by 10.140.92.51 with SMTP id a48mr91834qge.16.1428778366516; Sat, 11 Apr 2015 11:52:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no2735687iga.0!news-out.google.com!a41ni65qgf.1!nntp.google.com!z60no940871qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:52:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ecad407-f267-4d42-853e-03978c9a6c6f@googlegroups.com> Subject: Re: random number generator function From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:52:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3723 On Thursday, November 22, 2007 at 7:34:59 AM UTC+2, bb wrote: > Hi, > > I am creating a finite state machine, and within one of the states I > need to obtrain a random number by calling a function. > > random_value <= rand_val; > > I am new to VHDL. > > Thanks, This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way. ... library my_lib; use my_lib.my_package.all; ... signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000"; signal rand_packet_delayi: integer; ... rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay); --write(my_line, rand_packet_delay'path_name); --write(my_line, string'(" ")); --hwrite(my_line, rand_packet_delay); --write(my_line, string'(" ")); --write(my_line, now); --writeline(output, my_line); --packet send ended if(unsigned(rand_packet_delay) > 3) then rand_packet_delayi <= conv_integer(rand_packet_delay); else rand_packet_delayi <= conv_integer(rand_packet_delay) + 3; end if; for j in 1 to rand_packet_delayi loop wait until rx_clk'event and rx_clk = '1'; end loop; Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. This is discussed at http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html From newsfish@newsfish Thu Aug 1 00:33:12 2024 X-Received: by 10.42.154.133 with SMTP id q5mr11305805icw.4.1428778476440; Sat, 11 Apr 2015 11:54:36 -0700 (PDT) X-Received: by 10.140.83.165 with SMTP id j34mr93192qgd.23.1428778476314; Sat, 11 Apr 2015 11:54:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no4052121iga.0!news-out.google.com!a41ni65qgf.1!nntp.google.com!z60no941092qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:54:36 -0700 (PDT) In-Reply-To: <3A1BC2F0.DE7A9566@imms.de> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: <3A1BC2F0.DE7A9566@imms.de> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <539713fb-23fc-4290-b9d1-5365fc2e963f@googlegroups.com> Subject: Re: Getting the current instance name From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:54:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3724 On Wednesday, November 22, 2000 at 10:00:00 AM UTC+2, Kai Troester wrote: > Hi > > In a package I have a procedure which should print the time, the > instance and a message (I don't want to use the assert statements). My > problem is getting the name of the instance which is calling this > procedure without passing an additional parameter beside the message. > For time one can use 'now', but for the instance ? Does somebody have a > clue ? > > Thanx, Kai > -- > ----- Dipl. Ing. Kai Troester ------------------------------------- > Design Engineer -- System Design > IMMS - Institute of microelectronics and mechatronic systems > Langewiesener Strasse 22, 98693 Ilmenau, Germany > Tel: +49(3677)6783-52 | Fax: +49(3677)6783-38 > mailto:kai.troester@imms.de | http://www.imms.de/~troester > ------------------------------------------------------------------- While it is simple in VERILOG (%m in the display system function), in VHDL a bit more code writing is required. $display("dbg instance name %m at %d", $time); An example how to print an instance name in systemc is also available on this site. The importance of such debug information is when a design contains many instances of the very same component. First text IO library has to be called and line variable should be declared. Please refer to print example to see details. Next you have to select between two options: One is: instance name only in debug string and the other option gives more information such as entry and architecture names. Syntax example is given below: if(newByte = '1') then write (my_line, string'("path ")); write (my_line, clk'path_name);--short write (my_line, string'(" ")); writeline(output, my_line); write (my_line, string'("inst ")); write (my_line, clk'instance_name);--long write (my_line, string'(" ")); writeline(output, my_line); Please see a detailed explication at http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_path_name_print.html From newsfish@newsfish Thu Aug 1 00:33:13 2024 X-Received: by 10.50.20.135 with SMTP id n7mr13211630ige.8.1428871899493; Sun, 12 Apr 2015 13:51:39 -0700 (PDT) X-Received: by 10.50.4.34 with SMTP id h2mr136512igh.7.1428871899481; Sun, 12 Apr 2015 13:51:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no4507766iga.0!news-out.google.com!n7ni5964igk.0!nntp.google.com!l13no4507764iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 12 Apr 2015 13:51:38 -0700 (PDT) In-Reply-To: <3a24f454.12426254@news.dial.pipex.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.61.225.236; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.61.225.236 References: <3A1BC2F0.DE7A9566@imms.de> <3a1e49db.8965550@news.dial.pipex.com> <8vohtg$s7o$1@nnrp1.deja.com> <900td0$5dv$1@nnrp1.deja.com> <3a24f454.12426254@news.dial.pipex.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Getting the current instance name From: diogratia@gmail.com Injection-Date: Sun, 12 Apr 2015 20:51:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3725 On Wednesday, November 29, 2000 at 9:00:00 PM UTC+13, e...@riverside-machin= es.com.nospam wrote: > >Srini wrote: > >> > >> I am not sure if I understand the reasoning well here. I thought it > >> would be possible to "freeze" the "instance name" during Elaboration > >> (When the complete design hierearchy is known). So why should it be > >> known during Compilation itself (as an example Generics can be changed > >> during elaboration - isn't it?) >=20 > This was just my guess as to why it's implemented this way. In > general, you can't determine a complete hierarchical path to a named > item until runtime. Consider that subprograms are only elaborated at > runtime. It could be a real headache for a simulator to work out a > path to an item in a recursive procedure, for example, at runtime. >=20 > Evan A procedure call is a statement. A function call is an expression. Subprogr= am calls collectively use dynamic elaboration (Today we push the parameters= on a calling stack leaving space for a return value, and pop the whole mes= s when the call is complete and any return value has been evaluated). The only way to get the calling location is through a passed parameter on t= he calling stack.=20 There is a proposal to pass the calling_path in a hidden fashion on the cal= l stack (as an attribute which is a basic operation). That would require a= significant amount of overhead putting some potentially long string on the= calling stack impacting performance tremendously. =20 You could abstract that away to making a call a pseudo object, where you on= ly pass an index that tells you were to find it. Not sure if a 32 bit value= would be large enough. Somewhere there'd be a table of instance paths, pat= h names, calling paths and the calling overhead for the index would still b= e enough to significantly impact performance when all operators are functio= ns and all other operations of a type are basic operations. You could exemp= t predefined operators, but VHDL would still pay a heavy price because of i= t's strong typing. The value proposition doesn't appear to be there leaving user space solutio= ns. The alternative would be either to bite the bullet and pass the path as a p= arameter or restructure to use the equivalent of a POSIX logging call allow= ing the calling location to report the path. For the former you could use d= efault values allowing the parameters to only be passed for debugging. The = default values would be a zero length string for the path and a possibly a = boolean for determining whether or not report the path. Detecting error conditions is tough for function calls, strong typing doesn= 't allow in band error reporting, requiring either a returned record or mir= ror functions returning an error condition separately. The idea here is to = determine when the calling location reports it's instance path. What this boils down to is that VHDL isn't like other languages. It serves = for hardware descriptions that can be readily formally proven and that reli= es on strong typing. Despite rumors to the contrary it isn't a general purp= ose programming language, you can't bend it to other purposes readily. For = instance you couldn't implement a VHDL simulator in VHDL without describing= the simulation cycle in terms of hardware. The good news is you could put = it in an FPGA. From newsfish@newsfish Thu Aug 1 00:33:13 2024 X-Received: by 10.236.97.99 with SMTP id s63mr28628946yhf.40.1429601311682; Tue, 21 Apr 2015 00:28:31 -0700 (PDT) X-Received: by 10.50.3.105 with SMTP id b9mr27447igb.15.1429601311648; Tue, 21 Apr 2015 00:28:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!bcyclone04.am1.xlned.com!bcyclone04.am1.xlned.com!newsfeed.xs4all.nl!newsfeed1.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no2916802qgd.0!news-out.google.com!n7ni12892igk.0!nntp.google.com!l13no8020113iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Apr 2015 00:28:30 -0700 (PDT) In-Reply-To: <2m2g84$nqf@schema.fiu.edu> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=110.34.10.193; posting-account=4-AGgQoAAACioZu5dOMA_VCIzHyEbA8D NNTP-Posting-Host: 110.34.10.193 References: <2m2g84$nqf@schema.fiu.edu> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07fa0cd1-d487-4148-86ce-923a855be9ab@googlegroups.com> Subject: Re: 8-bit Shift Register VHDL Behavioral From: ektelcom@gmail.com Injection-Date: Tue, 21 Apr 2015 07:28:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 17 X-Received-Bytes: 1898 X-Received-Body-CRC: 3996828251 Xref: news.eternal-september.org comp.lang.vhdl:3727 On Tuesday, March 15, 1994 at 1:53:36 AM UTC+5:45, Habibie wrote: > Could someone please email me a copy of the above subject? I am relatively > new to VHDL language. I would like to simulate an 8-bit shift register. > > Thank you very much. > -habibie@srse.fiu.edu > > Note: Sorry for previous wrong post. you can design shift register in many ways, 1. using for loop http://appliedelectronicsengineering.blogspot.com/2015/04/using-for-loop-for-4-bit-shift-register_21.html 2. using a straight forward approach http://appliedelectronicsengineering.blogspot.com/2015/04/straight-forward-way-to-describe-shift.html and there are also other ways From newsfish@newsfish Thu Aug 1 00:33:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: 8-bit Shift Register VHDL Behavioral Date: Tue, 21 Apr 2015 11:52:22 -0400 Organization: Alacron, Inc. Lines: 9 Message-ID: References: <2m2g84$nqf@schema.fiu.edu> <07fa0cd1-d487-4148-86ce-923a855be9ab@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 21 Apr 2015 15:52:29 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="22107"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Wo8I/PHv2uV1+oyTotCsMoADfpr1GPts=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <07fa0cd1-d487-4148-86ce-923a855be9ab@googlegroups.com> Cancel-Lock: sha1:+fWCJS8bZAk4BW3/D4X62GNs4JU= Xref: news.eternal-september.org comp.lang.vhdl:3728 ektelcom@gmail.com wrote: > On Tuesday, March 15, 1994 at 1:53:36 AM UTC+5:45, Habibie wrote: [snip] A 21-year-old thread. This must be some sort of record. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:14 2024 X-Received: by 10.236.45.98 with SMTP id o62mr38325477yhb.42.1429717099813; Wed, 22 Apr 2015 08:38:19 -0700 (PDT) X-Received: by 10.140.93.14 with SMTP id c14mr392827qge.42.1429717099733; Wed, 22 Apr 2015 08:38:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no3168454qgd.0!news-out.google.com!k20ni1016qgd.0!nntp.google.com!j5no3167576qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Apr 2015 08:38:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.65.14.93; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 109.65.14.93 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Some tips how to print debug message from VHDL From: bknpk@hotmail.com Injection-Date: Wed, 22 Apr 2015 15:38:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 4 Xref: news.eternal-september.org comp.lang.vhdl:3729 I would like to share the following work: "...Recently I worked on an AHB project. I had many errors to debug in the initial bring up. Part of them were better debugged with print messages. The project contained some VHDL records, which GHDL (free VHDL simulator) does not dump to VCD wave. ..." http://bknpk.ddns.net/my_web/SDIO/vhdl_print_1_tips.html From newsfish@newsfish Thu Aug 1 00:33:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 23 Apr 2015 02:15:43 -0500 From: AhmedSokar Subject: Re: VHDL-AMS Q'ltf Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 98d4f114-395c-42c9-954c-b3469c3a0672 References: <1175689970.720561.150100@p77g2000hsh.googlegroups.com> Message-ID: Date: Thu, 23 Apr 2015 02:15:43 -0500 Lines: 4 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Kg1SHqNryLpb3c/ivYZmdJ7ojbjH384Dpt5fLKjoDC0EsWsBa4qslmumIUb1tBUAMY0DcJ6Sv/y4My3!pW8kdg1QK215pyYvxg6+OnNWfPABGzP2F/gvUiU/WBD5uhljQZa/eAeLSW54L5QoZgNA11Yl+nok!nBQ= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1017 Xref: news.eternal-september.org comp.lang.vhdl:3730 any solution for this problem yet? From newsfish@newsfish Thu Aug 1 00:33:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp1-1.free.fr!not-for-mail Date: Thu, 23 Apr 2015 23:01:49 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL-AMS Q'ltf References: <1175689970.720561.150100@p77g2000hsh.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 7 Message-ID: <55395dbd$0$3027$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 23 Apr 2015 23:01:50 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1429822910 news-1.free.fr 3027 88.185.146.198:2061 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3731 Le 23/04/2015 09:15, AhmedSokar a écrit : > any solution for this problem yet? 8 years later... Obviously, no. Nico From newsfish@newsfish Thu Aug 1 00:33:15 2024 X-Received: by 10.66.147.132 with SMTP id tk4mr12603890pab.23.1429896812417; Fri, 24 Apr 2015 10:33:32 -0700 (PDT) X-Received: by 10.140.38.232 with SMTP id t95mr146003qgt.36.1429896812157; Fri, 24 Apr 2015 10:33:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no5999622iga.0!news-out.google.com!k20ni1061qgd.0!nntp.google.com!z60no3539105qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Apr 2015 10:33:32 -0700 (PDT) In-Reply-To: <3h8mi2$ktb@vixen.cso.uiuc.edu> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=130.83.40.160; posting-account=1rGkOwoAAABn-dNxEVrNRvHKGXSYJRiG NNTP-Posting-Host: 130.83.40.160 References: <3h8mi2$ktb@vixen.cso.uiuc.edu> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: component implication in Synopsys From: ghada.dessouky@gmail.com Injection-Date: Fri, 24 Apr 2015 17:33:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3732 10 years later....I am struggling with that problem now. Any ideas since then :D? On Tuesday, February 7, 1995 at 9:52:18 PM UTC+1, Matthew Todd Gavin wrote: > In Synopsys, "component implication" occurs during synthesis, when you map > a function call to a component instantiation. The code below maps the > function call "check_one_count" to the entity one_counter. Whenever the > function is called in the code, the corresponding component is > instantiated. > > The problem is this: the entity uses a generic so that its input vector > (vin) can be of any length. When component implication is done, the > inputs to the corresponding function must be of _known_ length, or the > implication will not work. So my function parameter > > signal vin: in std_logic_vector; > > screws up the component implication. However, there is no way to pass in > the information for the length of vin, if we want to keep the design > generic. > > So is it possible to use component implication to imply a component > which has variable-length input/output? Just wondering if anyone had > encountered this besides me. > > Thanks, > > Matt > > -- check if there are exactly c high std_logics in v > function check_one_count > (signal vin: in std_logic_vector; n,c: integer) return std_logic is > -- pragma map_to_entity one_counter > -- pragma return_port_name c_ones > -- contents of this function are ignored but should > -- match the functionality of the module counter > variable count: integer range 0 to vin'length; > begin > count := 0; > for i in vin'range loop > if vin(i) = '1' then > count := count +1; > end if; > end loop; > > if (count = c) then > return '1'; > else > return '0'; > end if; > end; > > > > -- > ********************************************************* > Matt Gavin BSEE U of Iowa '93 > mtgavin@uiuc.edu Go Iowa Hawks!!!!! > http://www.cen.uiuc.edu/~mg12861/matt.html From newsfish@newsfish Thu Aug 1 00:33:15 2024 X-Received: by 10.236.25.35 with SMTP id y23mr2187458yhy.9.1429930788223; Fri, 24 Apr 2015 19:59:48 -0700 (PDT) X-Received: by 10.50.73.136 with SMTP id l8mr20285igv.0.1429930788196; Fri, 24 Apr 2015 19:59:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no3596259qgd.0!news-out.google.com!db6ni25048igc.0!nntp.google.com!m20no6083540iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Apr 2015 19:59:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.61.239.206; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.61.239.206 References: <3h8mi2$ktb@vixen.cso.uiuc.edu> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: component implication in Synopsys From: diogratia@gmail.com Injection-Date: Sat, 25 Apr 2015 02:59:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3283 X-Received-Body-CRC: 436468072 Xref: news.eternal-september.org comp.lang.vhdl:3733 Try taking off your shoes and socks when you count the years That's 20 year= s on. Instead of trolling through very old posts you could consider the issue in = terms of the modern specification of the the VHDL language (IEEE Std 1076-2= 008). (At the head post of this thread does stand out like a sore thumb doe= sn't it?) Try 4.4 Subprogram instantiation declarations in the standard where you'll = find that those function calls can be instantiated providing separation by = usage for varying length array parameter arguments. What we used to colloqu= ially refer to as uniquifying. The intended use is for this very purpose. http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/dta_type_genericity.pdf VHDL-200x Data Types and Abstractions White Paper 1, Type Genericity Peter Ashenden 1 Introduction Reuse of a design unit can be improved by making it applicable in a wider s= et of contexts, for example, by making it more generic. VHDL currently incl= udes a mechanism, generic constants, that allows components and entities to= be parameterized with formal constants. Actual generi c constants are spec= ified when components are instantiated and when entities are bound. The gen= eric constant mechanism is widely used to specify timing parameters and arr= ay port bounds, among other things. In this proposal we extend the generic mechanism of VHDL to improve support= for reuse. There are two main aspects to the extension. The first is to al= low subprograms and packages to have generic interface clauses. The second = is to allow formal types in a generic interface clause, making the generic = item reusable for a variety of different types. Formal subprograms and form= al packages are also allowed as a corollary to allowing formal type =20 -- If it's not supported today, it's due to a lack of -2008 support. Complain = to your synthesis vendor. It's a lack of love for VHDL on the part of your = synthesis vendor. And otherwise you're exhibiting hyperopia, unable to see = clearly into the historical record of the more recent past. From newsfish@newsfish Thu Aug 1 00:33:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 27 Apr 2015 01:09:45 -0500 From: Sumathigokul Subject: Re: TCL CODE WITH VHDL Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 1c74f010-f680-4d48-9462-34a57db641e6 References: <1135946281.847362.112360@g44g2000cwa.googlegroups.com> Message-ID: Date: Mon, 27 Apr 2015 01:09:45 -0500 Lines: 12 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-PffWCaI3BNZ+l67c1AFrGAoAnmdMoamFq9oUeu7HF4fnNw6NRLVIrvPd9b+4lyS8Wu4/Ba0Y7UtpPVQ!AslSzqQwkaeFg2oazNsQTB3ZHAk4DVDwnn4UD2RQP83c+hKjrBjkOMNF5Nj6qVanee/ccrZkUnbL!NKg= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1684 Xref: news.eternal-september.org comp.lang.vhdl:3734 Hi all... I have two doubts. 1. My first doubt is how to write the tcl script which locates my existing .vhd file and insert new line of code in it or replaces some of the existing codes and save the modified .vhd code back to same folder or in another new folder??? 2. My second doubt is if i want to modify .vhd code already existing (statement of my first doubt) using TCL command, how i can perform it? for example, to force any value at .vhd file using tcl command, am running that particular command in any of the simulation tool's command line. Similarly, if i write a tcl script to modify .vhd file, where can i run that file (i.e. using which tool) ??? Regards, Sumathi G. From newsfish@newsfish Thu Aug 1 00:33:16 2024 X-Received: by 10.43.130.198 with SMTP id hn6mr819790icc.26.1430266157749; Tue, 28 Apr 2015 17:09:17 -0700 (PDT) X-Received: by 10.182.181.10 with SMTP id ds10mr99064obc.12.1430266157692; Tue, 28 Apr 2015 17:09:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!l13no11395434iga.0!news-out.google.com!kd3ni2787igb.0!nntp.google.com!m20no7000164iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Apr 2015 17:09:17 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3a6b6b23-c122-4785-bbd5-af9bb147410d@googlegroups.com> Subject: Interested in VHDL and FPGA Development? From: Jackie Christman Injection-Date: Wed, 29 Apr 2015 00:09:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3735 Check out my course for only $15! Unlimited and Lifetime Access! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=FIVERR15 From newsfish@newsfish Thu Aug 1 00:33:16 2024 X-Received: by 10.52.7.194 with SMTP id l2mr5805856vda.12.1431006255863; Thu, 07 May 2015 06:44:15 -0700 (PDT) X-Received: by 10.50.73.136 with SMTP id l8mr336835igv.0.1431006255781; Thu, 07 May 2015 06:44:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!j5no5856441qga.1!news-out.google.com!kd3ni10371igb.0!nntp.google.com!m20no9155339iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 May 2015 06:44:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.35; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.35 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <23ebe552-8bdc-4825-a4ad-69588d2757ae@googlegroups.com> Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Jim Lewis Injection-Date: Thu, 07 May 2015 13:44:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3736 A very latent reply, however, in my scoreboard that does this, I keep a previous item pointer that I deallocate on entering pop and leave the previous item in when I exit. From newsfish@newsfish Thu Aug 1 00:33:16 2024 X-Received: by 10.68.180.5 with SMTP id dk5mr2377312pbc.3.1431051235171; Thu, 07 May 2015 19:13:55 -0700 (PDT) X-Received: by 10.140.23.166 with SMTP id 35mr24971qgp.12.1431051234873; Thu, 07 May 2015 19:13:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!m20no9333529iga.0!news-out.google.com!t92ni215qga.1!nntp.google.com!z60no5970869qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 May 2015 19:13:54 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.204.56.74; posting-account=uG-J6goAAAAcwMKpgt64lolkjJA4c0tE NNTP-Posting-Host: 73.204.56.74 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45879c82-6637-4679-adc2-045a9cdfbb62@googlegroups.com> Subject: Support Vector Machine VHDL From: Gee Won Han Injection-Date: Fri, 08 May 2015 02:13:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 10 Xref: news.eternal-september.org comp.lang.vhdl:3737 I would like to know if there someone has a VHDL code for Support Vector Machine. I would also like to know if someone could explain to me this line of code res: out sfixed(7 downto -10) I know what is downto, but I have never seen it to a negative number before. Does that mean this is sfixed is 17 bits? Thanks From newsfish@newsfish Thu Aug 1 00:33:17 2024 X-Received: by 10.70.118.99 with SMTP id kl3mr4821902pdb.12.1431082670501; Fri, 08 May 2015 03:57:50 -0700 (PDT) X-Received: by 10.140.41.164 with SMTP id z33mr40276qgz.21.1431082670241; Fri, 08 May 2015 03:57:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!m20no329241iga.0!news-out.google.com!k20ni1978qgd.0!nntp.google.com!z60no6034759qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 May 2015 03:57:50 -0700 (PDT) In-Reply-To: <45879c82-6637-4679-adc2-045a9cdfbb62@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:e875:f73d:c499:eae0; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:e875:f73d:c499:eae0 References: <45879c82-6637-4679-adc2-045a9cdfbb62@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Support Vector Machine VHDL From: KJ Injection-Date: Fri, 08 May 2015 10:57:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 22 Xref: news.eternal-september.org comp.lang.vhdl:3738 On Thursday, May 7, 2015 at 10:13:58 PM UTC-4, Gee Won Han wrote: >=20 > I would also like to know if someone could explain to me this line of cod= e >=20 > res: out sfixed(7 downto -10) >=20 >=20 > I know what is downto, but I have never seen it to a negative number befo= re. > Does that mean this is sfixed is 17 bits? >=20 sfixed is a data type that represents a signed fixed point number. There a= re 8 bits to the left of the point (7 downto 0) and there are 10 bits to th= e right of the point (-1 downto -10). There is also a type called ufixed w= hich is simply the unsigned version. Go here www.eda-stds.org/fphdl to get to the VHDL fixed and floating point = package. There is a user's guide that should be able to answer additional = questions you would have on how to use these packages. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:17 2024 X-Received: by 10.236.38.194 with SMTP id a42mr7616510yhb.4.1431107197092; Fri, 08 May 2015 10:46:37 -0700 (PDT) X-Received: by 10.140.102.172 with SMTP id w41mr73843qge.40.1431107197013; Fri, 08 May 2015 10:46:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no6109424qga.1!news-out.google.com!k20ni1998qgd.0!nntp.google.com!j5no6109422qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 May 2015 10:46:36 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.255.163; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.255.163 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Subject: Alliance CAD tool VHDL problem From: yaser fathy Injection-Date: Fri, 08 May 2015 17:46:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1527 X-Received-Body-CRC: 2720090035 Xref: news.eternal-september.org comp.lang.vhdl:3739 Hello, I'm learning an opensource cad tool called alliance , it takes a vhdl design and turns it into a wafer digital layout , its VHDL compiler is called SYF , the problem is that a code that compiled successfully on modelsim won't compile here , my VHDL is not very strong so I hope someone could give my an explanation : the problem is with variable declaration process(CS,wordin,reset) variable addr : std_logic_vector (7 DOWNTO 0); begin ... error : ILLEGAL DECLARATION at the variable declaration line any help ? From newsfish@newsfish Thu Aug 1 00:33:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Fri, 08 May 2015 14:56:19 -0400 Organization: Alacron, Inc. Lines: 27 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 8 May 2015 18:55:16 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="2766"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19VYPxxUN9MGzhyQYbFjEiooGx9NGfFQJ0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Cancel-Lock: sha1:zLclc/C4bR+f2UrXFCAneBiu5ao= Xref: news.eternal-september.org comp.lang.vhdl:3740 yaser fathy wrote: > Hello, > > I'm learning an opensource cad tool called alliance , it takes a vhdl > design and turns it into a wafer digital layout , its VHDL compiler is > called SYF , the problem is that a code that compiled successfully on > modelsim won't compile here , my VHDL is not very strong so I hope > someone could give my an explanation : > > the problem is with variable declaration > > process(CS,wordin,reset) > variable addr : std_logic_vector (7 DOWNTO 0); > begin > ... > > error : ILLEGAL DECLARATION > at the variable declaration line > > any help ? Maybe try naming the process, so the variable has an obvious hierarchical name like: proc_name: process (CS, wordin, reset) variable . . . From newsfish@newsfish Thu Aug 1 00:33:17 2024 X-Received: by 10.182.29.70 with SMTP id i6mr83065obh.27.1431121100277; Fri, 08 May 2015 14:38:20 -0700 (PDT) X-Received: by 10.140.31.196 with SMTP id f62mr1328qgf.30.1431121100087; Fri, 08 May 2015 14:38:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no623168iga.0!news-out.google.com!k20ni2008qgd.0!nntp.google.com!j5no6152950qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 May 2015 14:38:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.255.163; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.255.163 References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66ea8bf3-3e4b-4098-ace7-3339b39a4eb0@googlegroups.com> Subject: Re: Alliance CAD tool VHDL problem From: yaser fathy Injection-Date: Fri, 08 May 2015 21:38:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3741 thanks for your reply , but still not working. From newsfish@newsfish Thu Aug 1 00:33:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Fri, 08 May 2015 18:16:00 -0400 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> <66ea8bf3-3e4b-4098-ace7-3339b39a4eb0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 8 May 2015 22:14:56 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="19761"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Dhng0b8pivpbt97CSNGV6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: <66ea8bf3-3e4b-4098-ace7-3339b39a4eb0@googlegroups.com> Cancel-Lock: sha1:QKU1KfmaZwVHkGwGEfcaMvNDaow= Xref: news.eternal-september.org comp.lang.vhdl:3742 On 5/8/2015 5:38 PM, yaser fathy wrote: > thanks for your reply , but still not working. Something else is wrong. It won't be the first time the tool points to the wrong place to find an error. Check a few lines ahead of the process declaration. Any mistakes there? -- Rick From newsfish@newsfish Thu Aug 1 00:33:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Sat, 9 May 2015 10:32:47 +0000 (UTC) Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 9 May 2015 10:32:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="5354"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18v0fbF02L803cmAIG/dx7bq281Zcugrm0=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:pKvrFTi/eEmfRa3G/aGoNAfZ01c= Xref: news.eternal-september.org comp.lang.vhdl:3743 On Fri, 08 May 2015 10:46:36 -0700, yaser fathy wrote: > Hello, > > I'm learning an opensource cad tool called alliance , it takes a vhdl > design and turns it into a wafer digital layout , its VHDL compiler is > called SYF , the problem is that a code that compiled successfully on > modelsim won't compile here , Your code looks OK (from the fragment posted). How recent is this version of Alliance, how well maintained is it, and what is its support for newer versions of VHDL? My understanding is that Alliance is not actively supported, so it may not understand some perfectly legal constructs used in modern VHDL. (I'd be delighted f someone told me I'm wrong on this, but I haven't heard of any recent activity). -- Brian From newsfish@newsfish Thu Aug 1 00:33:18 2024 X-Received: by 10.66.151.234 with SMTP id ut10mr5955247pab.6.1431194801813; Sat, 09 May 2015 11:06:41 -0700 (PDT) X-Received: by 10.140.107.69 with SMTP id g63mr43332qgf.31.1431194801516; Sat, 09 May 2015 11:06:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!m20no1051472iga.0!news-out.google.com!t92ni259qga.1!nntp.google.com!j5no6314068qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 11:06:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.6.168.245; posting-account=p7IJzgkAAACsFeCX1coqmBrFeWDIplQ_ NNTP-Posting-Host: 128.6.168.245 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Verification of AVR8 Soft Core From: ssh105 Injection-Date: Sat, 09 May 2015 18:06:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3744 Hi, I managed to find some code for the AVR8 Soft Processor for the Arduino. It's VHDL code that you can implement on an FPGA to simulate the Arduino. You can find it here: http://papilio.cc/index.php?n=Papilio.ArduinoCore Does anyone know if it's possible to run some kind of VHDL formalism/hardware verification on it? Thanks in advance! From newsfish@newsfish Thu Aug 1 00:33:19 2024 X-Received: by 10.182.142.37 with SMTP id rt5mr6865524obb.47.1431202380896; Sat, 09 May 2015 13:13:00 -0700 (PDT) X-Received: by 10.140.20.40 with SMTP id 37mr47397qgi.26.1431202380820; Sat, 09 May 2015 13:13:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!m20no1110799iga.0!news-out.google.com!k20ni2048qgd.0!nntp.google.com!j5no6336756qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 13:13:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.226.202.39; posting-account=GxHQuAoAAAD5XUAW3CvS5ZEcFMip9aZO NNTP-Posting-Host: 41.226.202.39 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> Subject: 2spartan connected via Bluetooth From: Sam Souliez Injection-Date: Sat, 09 May 2015 20:13:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: news.eternal-september.org comp.lang.vhdl:3745 Can anyone help me with my projet i have to connect to spartan 6 or 3 using VHDl language via bluetooth mpodule but i don't where i start Need you help guys ! From newsfish@newsfish Thu Aug 1 00:33:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp5-1.free.fr!not-for-mail Date: Sat, 09 May 2015 22:21:24 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: 2spartan connected via Bluetooth References: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> In-Reply-To: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 8 Message-ID: <554e6c43$0$3034$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 09 May 2015 22:21:23 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1431202883 news-3.free.fr 3034 88.185.146.198:1788 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3746 Le 09/05/2015 22:13, Sam Souliez a écrit : > Can anyone help me with my projet i have to connect to spartan 6 or 3 using VHDl language via bluetooth mpodule but i don't where i start > Need you help guys ! Look at the BT module datasheet, there's certainly plenty of extremely useful information inside. Nicolas From newsfish@newsfish Thu Aug 1 00:33:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: 2spartan connected via Bluetooth Date: Sat, 09 May 2015 16:31:33 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 9 May 2015 20:30:28 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="10977"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19mclIk8vntC5pyYGnncucr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> Cancel-Lock: sha1:BZI5Wt5p/nTeYsHxd3NstTS1lzE= Xref: news.eternal-september.org comp.lang.vhdl:3747 On 5/9/2015 4:13 PM, Sam Souliez wrote: > Can anyone help me with my projet i have to connect to spartan 6 or 3 using VHDl language via bluetooth mpodule but i don't where i start > Need you help guys ! The easy way is to use a bluetooth module that provides a serial interface. Then all your FPGA design needs to do is push characters out the serial port and receive what comes back. Look for HC-05 on ebay. I have some which I will be working with very soon. -- Rick From newsfish@newsfish Thu Aug 1 00:33:20 2024 X-Received: by 10.70.135.10 with SMTP id po10mr7353546pdb.2.1431209679301; Sat, 09 May 2015 15:14:39 -0700 (PDT) X-Received: by 10.140.105.133 with SMTP id c5mr53086qgf.28.1431209679046; Sat, 09 May 2015 15:14:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no1160754iga.0!news-out.google.com!t92ni268qga.1!nntp.google.com!z60no6355795qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 15:14:38 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=158.227.185.115; posting-account=-EGgzQkAAAAEZAPEk3dU_oy6cNScQ5_l NNTP-Posting-Host: 158.227.185.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <553ae1d3-5a04-4dc7-858c-d65f127aa89d@googlegroups.com> Subject: Reducing verbosity in structural entity declaration From: unaimc@gmail.com Injection-Date: Sat, 09 May 2015 22:14:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3748 Hello, I recently learnt that, since VHDL'93, components are not needed any more, = and entities can be directly instantiated [0]. So that I can replace this a= rchitecture --entity testent is -- port ( CLK: in std_logic ); --end testent; --architecture withcomponents of testent is ---component mycomp ---port ( CLK, D: in std_logic; --- Q: out std_logic ); ---end component; ---signal f2s: std_logic; --begin ---MODA: mycomp port map ( CLK, open, f2s); ---MODB: mycomp port map ( CLK, f2s, open); --end withcomponents; with --architecture withoutcomponents of testent is ---signal f2s: std_logic; --begin ---MODA: entity work.mycomp port map ( CLK, open, f2s); ---MODB: entity work.mycomp port map ( CLK, f2s, open); --end withoutcomponents; On top of that, I would like to know whether VHDL supports any expression s= o that the declaration of the signal 'f2s' is not required. Something simil= ar to: --architecture direct of testent is --begin ---MODA: entity work.mycomp port map ( CLK, open, MODB.D); ---MODB: entity work.mycomp port map ( CLK, MODA.Q, open); --end direct; Which from my point of view would be explained as: can VHDL understand the = ports of an instantiated entity as if it was a record? I've tried it in ISE= with no success, and I've found no similar examples, so I would say that i= t's not supported. However, I'd like to know your opinions, in case you thi= nk that such a feature makes sense, or to hear of alternatives to achieve a= similar scheme. I've found this message [1] sent to the VHDL-200X - DASC mailing list in Fe= b 2003, which is much ambitious than what I'm asking. However, since it is = related, I'd like to be pointed to any later reference on it, if any. ---- Moreover, although I've presented a really simple example, I'd like to use = such a feature inside generate environments. Thus, to achieve so, besides s= upporting such an expression, the label of the instantiation should provide= references to each of the actually synthetized modules. A shift register, = with such an implicit declarations, would be: --architecture direct of testent is --begin ---MODS: for k in 7 downto 0 generate ----case k generate -----when 0 =3D> ------MODS(k): entity work.mycomp port map ( CLK, open, MODS(k+1).D); -----when 7 =3D> ------MODS(k): entity work.mycomp port map ( CLK, MODS(k-1).Q, MODS(k+1).D)= ; -----when others =3D> ------MODS(k): entity work.mycomp port map ( CLK, MODS(k-1).Q, open); ----end generate; ---end generate; --end direct; or --architecture direct of testent is --begin ---MODS: for k in 7 downto 0 generate ----MODS(k): case k generate -----when 0 =3D> ------entity work.mycomp port map ( CLK, open, MODS(k+1).D); -----when 7 =3D> ------entity work.mycomp port map ( CLK, MODS(k-1).Q, MODS(k+1).D); -----when others =3D> ------entity work.mycomp port map ( CLK, MODS(k-1).Q, open); ----end generate; ---end generate; --end direct; I'm quite sure that this is not supported neither in VHDL'93 nor in VHDL'08= . Nevertheless, to those of you who know the internals, does this feature(s= ) make any sense to you? Or is rather specific? [0] http://www.sigasi.com/content/four-and-half-ways-write-vhdl-instantiati= ons [1] http://www.eda.org/vhdl-200x/hm/0040.html From newsfish@newsfish Thu Aug 1 00:33:20 2024 X-Received: by 10.236.40.8 with SMTP id e8mr7375236yhb.35.1431210586242; Sat, 09 May 2015 15:29:46 -0700 (PDT) X-Received: by 10.140.102.75 with SMTP id v69mr52333qge.19.1431210586187; Sat, 09 May 2015 15:29:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!j5no6356020qga.1!news-out.google.com!k20ni2059qgd.0!nntp.google.com!j5no6356014qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 15:29:46 -0700 (PDT) In-Reply-To: <553ae1d3-5a04-4dc7-858c-d65f127aa89d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=158.227.185.115; posting-account=-EGgzQkAAAAEZAPEk3dU_oy6cNScQ5_l NNTP-Posting-Host: 158.227.185.115 References: <553ae1d3-5a04-4dc7-858c-d65f127aa89d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Reducing verbosity in structural entity declaration From: unaimc@gmail.com Injection-Date: Sat, 09 May 2015 22:29:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 9 Xref: news.eternal-september.org comp.lang.vhdl:3749 As a bonus conceptual script, this is what I would expect to be nearly minimum verbosity while still maintaing VHDL syntax (with richer generate structures): --architecture direct of testent is --begin ---MODS: for k in 7 downto 0 generate ----MODS(k): entity work.mycomp port map ( CLK, -----[case k generate when 0 => open; when others => MODS(k-1).Q; end generate;] , -----[case k generate when 7 => open; when others => MODS(k+1).D; end generate;] ); ---end generate; --end direct; From newsfish@newsfish Thu Aug 1 00:33:20 2024 X-Received: by 10.182.45.138 with SMTP id n10mr8194366obm.4.1431217505907; Sat, 09 May 2015 17:25:05 -0700 (PDT) X-Received: by 10.140.29.119 with SMTP id a110mr50130qga.20.1431217505806; Sat, 09 May 2015 17:25:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no1199399iga.0!news-out.google.com!k20ni2063qgd.0!nntp.google.com!j5no6368567qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 17:25:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:80ae:3f64:4c4a:fc98; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:80ae:3f64:4c4a:fc98 References: <553ae1d3-5a04-4dc7-858c-d65f127aa89d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Reducing verbosity in structural entity declaration From: KJ Injection-Date: Sun, 10 May 2015 00:25:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3750 On Saturday, May 9, 2015 at 6:29:47 PM UTC-4, una...@gmail.com wrote: You can't do exactly what you want since you're using 'MODS' both as the na= me of the instantiation as well as the name of a signal. However, you will= need to define the record structure and make an array of it anyway so ther= e will be just as much typing to do that, naming the signal uniquely isn't = any time saver. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:21 2024 X-Received: by 10.68.142.7 with SMTP id rs7mr10783571pbb.4.1431256300585; Sun, 10 May 2015 04:11:40 -0700 (PDT) X-Received: by 10.140.94.47 with SMTP id f44mr67601qge.22.1431256300271; Sun, 10 May 2015 04:11:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!m20no10002558iga.0!news-out.google.com!k20ni2075qgd.0!nntp.google.com!j5no6438781qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 May 2015 04:11:40 -0700 (PDT) In-Reply-To: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.233.105; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.233.105 References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <365da0e4-cb6a-48ca-a3fa-f1b0be728414@googlegroups.com> Subject: Re: Alliance CAD tool VHDL problem From: yaser fathy Injection-Date: Sun, 10 May 2015 11:11:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:3751 the version is 5 copyrighted 2015 if I remove the variable declaration and make a similar signal declaration (before the begin) it compiles and simulates successfully. From newsfish@newsfish Thu Aug 1 00:33:21 2024 X-Received: by 10.66.121.137 with SMTP id lk9mr11129780pab.11.1431256383312; Sun, 10 May 2015 04:13:03 -0700 (PDT) X-Received: by 10.140.20.40 with SMTP id 37mr68846qgi.26.1431256383006; Sun, 10 May 2015 04:13:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!m20no1394343iga.0!news-out.google.com!t92ni287qga.1!nntp.google.com!z60no6439939qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 May 2015 04:13:02 -0700 (PDT) In-Reply-To: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.233.105; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.233.105 References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <35f9adc8-0c16-48b8-8c62-9528a3f0be3f@googlegroups.com> Subject: Re: Alliance CAD tool VHDL problem From: yaser fathy Injection-Date: Sun, 10 May 2015 11:13:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3752 the version is 5 copyrighted 2015 if I remove the variable declaration and make a similar signal declaration (before the process) it compiles and simulates successfully. From newsfish@newsfish Thu Aug 1 00:33:21 2024 X-Received: by 10.236.7.133 with SMTP id 5mr11520402yhp.3.1431262038388; Sun, 10 May 2015 05:47:18 -0700 (PDT) X-Received: by 10.140.31.196 with SMTP id f62mr74161qgf.30.1431262038269; Sun, 10 May 2015 05:47:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no6453414qga.1!news-out.google.com!t92ni290qga.1!nntp.google.com!z60no6454416qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 May 2015 05:47:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.233.105; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.233.105 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Input storage in FSM From: yaser fathy Injection-Date: Sun, 10 May 2015 12:47:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1403 X-Received-Body-CRC: 312294366 Xref: news.eternal-september.org comp.lang.vhdl:3753 Hello, I want to create a fsm that takes a few inputs during its cycle and output these inputs at the end of the cycle . I wanted to use variables to store these input but the compiler won't accept variable declaration , so I used signals , now the code compiles fine , but the output doesn't show at the end , and the compiler log sais: output x is assigned by only 2 states refering to the signal I used to store the input From newsfish@newsfish Thu Aug 1 00:33:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Sun, 10 May 2015 21:45:19 -0400 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> <35f9adc8-0c16-48b8-8c62-9528a3f0be3f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 11 May 2015 01:44:15 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9bd0ba8c53fd0f12dc2ce700b744f948"; logging-data="16518"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/bZ4Yd0NjGaDIlqNcsqWnQ" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: <35f9adc8-0c16-48b8-8c62-9528a3f0be3f@googlegroups.com> Cancel-Lock: sha1:a3y5xu4dUNtf5L454a9LFcnWjgs= Xref: news.eternal-september.org comp.lang.vhdl:3754 On 5/10/2015 7:13 AM, yaser fathy wrote: > the version is 5 copyrighted 2015 > > if I remove the variable declaration and make a similar signal declaration (before the process) it compiles and simulates successfully. > While that probably is one workaround, you have to be careful if you start to do this globally on a design. Declaring the variable outside the process makes it shared, and you want to be careful not to use it elsewhere. Also you could have multiple processes with the same name for a local variable, and you would then have to re-name these when you pull them out of the process. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Sun, 10 May 2015 22:01:26 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> <35f9adc8-0c16-48b8-8c62-9528a3f0be3f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 11 May 2015 02:00:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9bd0ba8c53fd0f12dc2ce700b744f948"; logging-data="19271"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18NvWH5C50/dnnvwvncBOIy" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: Cancel-Lock: sha1:CqNykxLJYRd8ezBS2PkWoImMIxo= Xref: news.eternal-september.org comp.lang.vhdl:3755 On 5/10/2015 9:45 PM, Gabor wrote: > On 5/10/2015 7:13 AM, yaser fathy wrote: >> the version is 5 copyrighted 2015 >> >> if I remove the variable declaration and make a similar signal >> declaration (before the process) it compiles and simulates successfully. >> > > While that probably is one workaround, you have to be careful > if you start to do this globally on a design. Declaring the > variable outside the process makes it shared, and you want > to be careful not to use it elsewhere. Also you could have > multiple processes with the same name for a local variable, > and you would then have to re-name these when you pull them > out of the process. > OK I see from your new thread that you didn't declare shared variables but rather signals. You do understand that signals do not take on their assigned values until the process completes while variables take on the new value right away? So just moving the declaration outside the process will change the logic if you make the variable into a signal. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Input storage in FSM Date: Mon, 11 May 2015 16:59:00 +0000 (UTC) Organization: A noiseless patient Spider Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 11 May 2015 16:59:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="10055d0a889852f8818324769e017ab0"; logging-data="2970"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/tfHMcfj+dI7lD22hZdX4T" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:uqV8Cxq33tJXsbOmmwbVRJo+80Y= Xref: news.eternal-september.org comp.lang.vhdl:3756 On Sun, 10 May 2015 05:47:18 -0700, yaser fathy wrote: > Hello, > > I want to create a fsm that takes a few inputs during its cycle and > output these inputs at the end of the cycle . > > I wanted to use variables to store these input but the compiler won't > accept variable declaration , so I used signals , now the code compiles > fine , but the output doesn't show at the end , and the compiler log > sais: > > output x is assigned by only 2 states refering to the signal I used to > store the input That sounds like you've made an utter hash of things. I don't know of any compilers that won't accept VHDL legal variable definitions, so that's the first sign something's badly wrong. And whatever message you've got there regarding the output means that your state machine logic is probably some horrific tangle of combinational and clocked processes. You want to write the entire thing in a single process. Google for vhdl single process state machine. You'll get a ton of hits; most of which will be crap. Spend the time reading through them, valid and crap alike, until you understand the concept. Be willing to blow an hour on it. Then, and here's the part you won't like, delete your entire existing architecture definition. Wipe it out. It's wrong, it's a mess, I can tell you without even reading it. Even if you manage to cobble together code that seems to work from it, you'll miss something. It's what, 30 lines of code? 40? Write it fresh with a clear idea of how it should be structured; you'll get there in half the time. What you've currently got can only get in your way. So ends the advice of Rob. As an aside to the other old farts around here, I was going to point him to Mike Tressler's site for specific examples, and couldn't find even archives of it. Anyone still have a reference for it? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:33:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!not-for-mail Date: Mon, 11 May 2015 19:22:14 +0100 From: Andy Botterill User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Input storage in FSM References: In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 25 Message-ID: <5550f357$0$28970$bed64819@gradwell.net> NNTP-Posting-Host: d639f4a5.gradwell.net X-Trace: DXC=m34=ge=kWGo:=KiVkUL^lgaEW\3OJZ9ZcPo1k6Q\TjcoYjMIT`6J^KoOT6Q0a]eYDbA2:ZUKJ>:m`K>VKND1bjBiAT9C^SG@jHd X-Complaints-To: abuse@gradwell.net X-Received-Bytes: 1486 X-Received-Body-CRC: 4101716920 Xref: news.eternal-september.org comp.lang.vhdl:3757 On 11/05/15 17:59, Rob Gaddi wrote: > On Sun, 10 May 2015 05:47:18 -0700, yaser fathy wrote: > > > As an aside to the other old farts around here, I was going to point him > to Mike Tressler's site for specific examples, and couldn't find even > archives of it. Anyone still have a reference for it? This was posted in 2007. http://home.comcast.net/~mike_treseler/ Unfortunately that URL does not exist any more. Look at page 31 of this http://ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl.pdf It does refer to Mike Treseler's code and gives an example. The powerpoint points to a Verizon place which does not exist as well. Hopefully Mike will come back....... From newsfish@newsfish Thu Aug 1 00:33:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Input storage in FSM Date: Mon, 11 May 2015 15:51:29 -0400 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <5550f357$0$28970$bed64819@gradwell.net> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 11 May 2015 19:50:27 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22139"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19HqlyVEJXT7RIUbpyiTPhf" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: <5550f357$0$28970$bed64819@gradwell.net> Cancel-Lock: sha1:k1XFTGz/XelhWx/Y+q6UsyF3D1g= Xref: news.eternal-september.org comp.lang.vhdl:3758 On 5/11/2015 2:22 PM, Andy Botterill wrote: > On 11/05/15 17:59, Rob Gaddi wrote: >> On Sun, 10 May 2015 05:47:18 -0700, yaser fathy wrote: >> >> >> As an aside to the other old farts around here, I was going to point him >> to Mike Tressler's site for specific examples, and couldn't find even >> archives of it. Anyone still have a reference for it? > > This was posted in 2007. > > http://home.comcast.net/~mike_treseler/ > > Unfortunately that URL does not exist any more. > > Look at page 31 of this > http://ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl.pdf > > It does refer to Mike Treseler's code and gives an example. > > The powerpoint points to a Verizon place which does not exist as well. > > Hopefully Mike will come back....... I don't see where he has posted here since 2013. Searching a bit on the web uncovers him as being at Microsoft working on the XBox since Dec 2013. So that may explain it. He may be working on a black ops sort of thing and not allowed to participate in social media. -- Rick From newsfish@newsfish Thu Aug 1 00:33:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Input storage in FSM Date: Mon, 11 May 2015 22:47:46 +0000 (UTC) Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <5550f357$0$28970$bed64819@gradwell.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 11 May 2015 22:47:46 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="10055d0a889852f8818324769e017ab0"; logging-data="2970"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hw5kbAWrMNGXOQ9j4GhHB" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:/kpkgzQc0/kJMfogQCa+5Neg+7w= Xref: news.eternal-september.org comp.lang.vhdl:3759 On Mon, 11 May 2015 15:51:29 -0400, rickman wrote: > On 5/11/2015 2:22 PM, Andy Botterill wrote: >> >> Hopefully Mike will come back....... > > I don't see where he has posted here since 2013. Searching a bit on the > web uncovers him as being at Microsoft working on the XBox since Dec > 2013. So that may explain it. He may be working on a black ops sort of > thing and not allowed to participate in social media. This is USENET. Who's social? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:33:24 2024 X-Received: by 10.66.219.130 with SMTP id po2mr38667934pac.46.1432039531910; Tue, 19 May 2015 05:45:31 -0700 (PDT) X-Received: by 10.140.95.109 with SMTP id h100mr389578qge.6.1432039531853; Tue, 19 May 2015 05:45:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j8no5672518igd.0!news-out.google.com!t92ni24958qga.1!nntp.google.com!z60no2307849qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 19 May 2015 05:45:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.253.6.210; posting-account=fNDqwQoAAAB4_FDM62R1eG1rPB785aCE NNTP-Posting-Host: 197.253.6.210 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: MOD operator From: theultimateiq@gmail.com Injection-Date: Tue, 19 May 2015 12:45:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1774 X-Received-Body-CRC: 1394926736 Xref: news.eternal-september.org comp.lang.vhdl:3760 Dear Guilherme, I have been working on implementing a main memory for days now but it keeps= showing error: "Error (10327): VHDL error at memory_pkg.vhd(16): can't det= ermine definition of operator ""**"" -- found 0 possible definitions" and t= his has seriously slow down my coding speed. Can you help me out by telling= me the possible causes as well as the possible solution to this error. I was browsing through the net when I came across the solution provided to = the similar problem. I adopted the solution but unfortunately it doesn't un= ravel the problem. Best regards, Adetola Akinwale. From newsfish@newsfish Thu Aug 1 00:33:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: MOD operator Date: Wed, 20 May 2015 10:34:34 -0400 Organization: Alacron, Inc. Lines: 19 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 20 May 2015 14:32:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="10714"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++G4t+JDV4WcSTSnmQvkIkswRQD513jG8=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:ZsW3HRuHKVhD0M7GMxvVopRwRgI= Xref: news.eternal-september.org comp.lang.vhdl:3761 theultimateiq@gmail.com wrote: > Dear Guilherme, > > I have been working on implementing a main memory for days now but it keeps showing error: "Error (10327): VHDL error at memory_pkg.vhd(16): can't determine definition of operator ""**"" -- found 0 possible definitions" and this has seriously slow down my coding speed. Can you help me out by telling me the possible causes as well as the possible solution to this error. > > I was browsing through the net when I came across the solution provided to the similar problem. I adopted the solution but unfortunately it doesn't unravel the problem. > > Best regards, > > Adetola Akinwale. Sounds like a library issue. What libraries are you using in the design? One thing to note is that the error message may also be misleading. Sometimes "found 0 definitions" really means that it found multiple definitions (from different libraries) and has no way to determine which to use. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:25 2024 X-Received: by 10.66.118.198 with SMTP id ko6mr47777305pab.28.1432136782264; Wed, 20 May 2015 08:46:22 -0700 (PDT) X-Received: by 10.182.19.194 with SMTP id h2mr247580obe.41.1432136782180; Wed, 20 May 2015 08:46:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no7010035igd.0!news-out.google.com!kd3ni22899igb.0!nntp.google.com!j8no6893627igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 May 2015 08:46:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: MOD operator From: Andy Injection-Date: Wed, 20 May 2015 15:46:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:3762 You didn't say what types of data you are supplying as operands. "**" may only be defined for integer and real. Andy From newsfish@newsfish Thu Aug 1 00:33:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: MOD operator Date: Wed, 20 May 2015 12:22:18 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 20 May 2015 16:21:07 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="5505"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19zsrbISsnIk3/7oV2wP4Xq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:SkGURjwibcqUPSfVptPp6seHVns= Xref: news.eternal-september.org comp.lang.vhdl:3763 On 5/19/2015 8:45 AM, theultimateiq@gmail.com wrote: > Dear Guilherme, > > I have been working on implementing a main memory for days now but it keeps showing error: "Error (10327): VHDL error at memory_pkg.vhd(16): can't determine definition of operator ""**"" -- found 0 possible definitions" and this has seriously slow down my coding speed. Can you help me out by telling me the possible causes as well as the possible solution to this error. > > I was browsing through the net when I came across the solution provided to the similar problem. I adopted the solution but unfortunately it doesn't unravel the problem. I'm a bit confused. Your subject is about the MOD operator but you list the exponentiation operator? Can you give us some more info? What are your data types? Show us how the operator is used. -- Rick From newsfish@newsfish Thu Aug 1 00:33:25 2024 X-Received: by 10.67.23.36 with SMTP id hx4mr2623968pad.45.1432206907848; Thu, 21 May 2015 04:15:07 -0700 (PDT) X-Received: by 10.50.152.102 with SMTP id ux6mr41624igb.0.1432206907782; Thu, 21 May 2015 04:15:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!bcyclone01.am1.xlned.com!bcyclone01.am1.xlned.com!lightspeed.eweka.nl!lightspeed.eweka.nl!j8no7377791igd.0!news-out.google.com!n7ni40127igk.0!nntp.google.com!j8no7377789igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 21 May 2015 04:15:06 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Do you think my code is right on DFF with only variable usage From: fl Injection-Date: Thu, 21 May 2015 11:15:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Body-CRC: 3344972750 X-Received-Bytes: 1836 Lines: 32 Xref: news.eternal-september.org comp.lang.vhdl:3764 Hi, I see a question online: how will u write d ff using variables alone Below is my VHDL code. Because I do not see any specialties in the code, I suspect that the code is not it is supposed to be. What is your opinion on the question? Thanks, .................. process(CLR,PRE,CLK) --process with sensitivity list. variable v_d: std_ulogic := '0'; begin if (CLR = '1') then --Asynchronous clear input v_d := '0'; else if(PRE = '1') then --Asynchronous set input v_d := '1'; else if ( CE = '1' and falling_edge(CLK) ) then v_d := '1'; end if; end if; end if; Q <= v_d; end process; From newsfish@newsfish Thu Aug 1 00:33:26 2024 X-Received: by 10.236.19.51 with SMTP id m39mr3040908yhm.31.1432210095288; Thu, 21 May 2015 05:08:15 -0700 (PDT) X-Received: by 10.50.7.101 with SMTP id i5mr563257iga.15.1432210095236; Thu, 21 May 2015 05:08:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no3017600qgd.1!news-out.google.com!n7ni40167igk.0!nntp.google.com!j8no7396134igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 21 May 2015 05:08:14 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Do you think my code is right on DFF with only variable usage From: KJ Injection-Date: Thu, 21 May 2015 12:08:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 27 Xref: news.eternal-september.org comp.lang.vhdl:3765 On Thursday, May 21, 2015 at 7:15:11 AM UTC-4, fl wrote: > Hi, >=20 > I see a question online: >=20 > how will u write d ff using variables alone >=20 > Below is my VHDL code. Because I do not see any specialties in the code, > I suspect that the code is not it is supposed to be.=20 >=20 > What is your opinion on the question? >=20 >=20 1. You didn't actually use the 'D' input of the flip flop. Corrected code = is: if ( CE =3D '1' and falling_edge(CLK) ) then=20 v_d :=3D d; -- OLD v_d :=3D '1';=20 end if; 2. The assignment "Q <=3D v_d" makes use of a signal which violates your st= atement of "using variables alone". Obviously in order to be able to use t= he output of the flip flop outside of the process you have to use a signal,= so what exactly is your point of trying to have a process that supposedly = only uses variables (but doesn't). Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:26 2024 X-Received: by 10.182.79.234 with SMTP id m10mr10452780obx.22.1432302956849; Fri, 22 May 2015 06:55:56 -0700 (PDT) X-Received: by 10.50.18.20 with SMTP id s20mr94722igd.14.1432302956787; Fri, 22 May 2015 06:55:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no7897880igd.0!news-out.google.com!n7ni41145igk.0!nntp.google.com!j8no7897872igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 May 2015 06:55:56 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: What meaning of two '#'s in a to_signed function? From: fl Injection-Date: Fri, 22 May 2015 13:55:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3766 Hi, I see the following VHDL code: in5_out1_re <= to_signed(2#0000000000#, 10); What meaning of the two '#'s above? Thanks From newsfish@newsfish Thu Aug 1 00:33:26 2024 X-Received: by 10.67.14.194 with SMTP id fi2mr10230887pad.29.1432308683864; Fri, 22 May 2015 08:31:23 -0700 (PDT) X-Received: by 10.50.64.179 with SMTP id p19mr83483igs.6.1432308683775; Fri, 22 May 2015 08:31:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7608033igd.0!news-out.google.com!n7ni41200igk.0!nntp.google.com!j8no7937657igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 May 2015 08:31:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d245057-e57c-46e4-ae07-978ed67253d7@googlegroups.com> Subject: Re: What meaning of two '#'s in a to_signed function? From: KJ Injection-Date: Fri, 22 May 2015 15:31:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3767 On Friday, May 22, 2015 at 9:55:59 AM UTC-4, fl wrote: > Hi, > > I see the following VHDL code: > > > in5_out1_re <= to_signed(2#0000000000#, 10); > > > What meaning of the two '#'s above? > > Thanks VHDL allows you to specify a base for a numeric literal. So if you want the number 65535, you can specify it as 65535 -- Implicit base 10 10#65535# -- Explicit base 10 16#FFFF# -- Hex 8#177777# -- Octal 2#1111111111111111# -- Binary The # symbol delimits the beginning and end of the numeric literal. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:27 2024 X-Received: by 10.50.66.167 with SMTP id g7mr8865215igt.11.1432348270397; Fri, 22 May 2015 19:31:10 -0700 (PDT) X-Received: by 10.50.43.129 with SMTP id w1mr176380igl.0.1432348270342; Fri, 22 May 2015 19:31:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7726971igd.0!news-out.google.com!kd3ni25172igb.0!nntp.google.com!j8no8154009igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 May 2015 19:31:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> Subject: What return value should be besides '0' and '1' for this function? From: fl Injection-Date: Sat, 23 May 2015 02:31:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3768 Hi, I read the following code. I know that std_logic has value '0', '1', 'Z' and 'X' etc. There are only two values are considered below. Do you think it is an imperfect function or not? Thanks, FUNCTION to_integer( x : IN std_logic) RETURN integer IS VARIABLE int: integer; BEGIN IF x = '0' THEN int := 0; ELSE int := 1; END IF; RETURN int; END; From newsfish@newsfish Thu Aug 1 00:33:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What return value should be besides '0' and '1' for this function? Date: Fri, 22 May 2015 22:40:06 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 23 May 2015 02:38:58 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25707"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+LurDKR+04k2KrYUgguMeW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> Cancel-Lock: sha1:DIiZdOQj7EuaUnXMUg2ciyM7l+A= Xref: news.eternal-september.org comp.lang.vhdl:3769 On 5/22/2015 10:31 PM, fl wrote: > Hi, > > I read the following code. I know that std_logic has value '0', '1', 'Z' and > 'X' etc. > > There are only two values are considered below. Do you think it is an > imperfect function or not? > > > Thanks, > > > > > FUNCTION to_integer( x : IN std_logic) RETURN integer IS > VARIABLE int: integer; > BEGIN > IF x = '0' THEN > int := 0; > ELSE > int := 1; > END IF; > RETURN int; > END; Not sure why you say only two values are "considered". The input can be any of a number of states and all are translated to an integer 1 except for the input of '0' which is translated to 0. Is that what you want? std_logic can also be 'H' or 'L' which are often equated to '1' and '0' respectively. -- Rick From newsfish@newsfish Thu Aug 1 00:33:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: What return value should be besides '0' and '1' for this function? Date: Sat, 23 May 2015 09:52:30 +0000 (UTC) Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 23 May 2015 09:52:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="29105"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18lQmJF0ner7xW18z/6u+ozwo2vUjJTXsU=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:PnbvPwQIHht8zbHiJ93A3zJSMDM= Xref: news.eternal-september.org comp.lang.vhdl:3770 On Fri, 22 May 2015 19:31:09 -0700, fl wrote: > Hi, > There are only two values are considered below. Do you think it is an > imperfect function or not? > As Rickman hints, this function is definitely erroneous in converting 'L' to '1'. If you are only allowed 0 and 1 as return values, there is no choice but to resolve all the others 'U','Z' etc to either 0 or 1, and your choice to resolve them (except for 'L') as 1 is probably as good as any. I would recommend declaring a new Integer type (or at the very least a subtype) restricted in range to (0 to 1) and return that type, to make it crystal clear what this function does (and to catch unintended errors such as passing 2 (or -2143863148) as a value to code which was only written to handle 0,1. -- Brian From newsfish@newsfish Thu Aug 1 00:33:28 2024 X-Received: by 10.182.16.163 with SMTP id h3mr20074324obd.14.1432432052966; Sat, 23 May 2015 18:47:32 -0700 (PDT) X-Received: by 10.50.8.7 with SMTP id n7mr238009iga.15.1432432052950; Sat, 23 May 2015 18:47:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no8581654igd.0!news-out.google.com!kd3ni26054igb.0!nntp.google.com!j8no8581647igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 May 2015 18:47:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 References: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What return value should be besides '0' and '1' for this function? From: fl Injection-Date: Sun, 24 May 2015 01:47:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3771 On Saturday, May 23, 2015 at 2:53:43 AM UTC-7, Brian Drummond wrote: > On Fri, 22 May 2015 19:31:09 -0700, fl wrote: > > > Hi, > > > There are only two values are considered below. Do you think it is an > > imperfect function or not? > > > > As Rickman hints, this function is definitely erroneous in converting 'L' > to '1'. > > If you are only allowed 0 and 1 as return values, there is no choice but > to resolve all the others 'U','Z' etc to either 0 or 1, and your choice > to resolve them (except for 'L') as 1 is probably as good as any. > > I would recommend declaring a new Integer type (or at the very least a > subtype) restricted in range to (0 to 1) and return that type, to make it > crystal clear what this function does (and to catch unintended errors > such as passing 2 (or -2143863148) as a value to code which was only > written to handle 0,1. > > -- Brian Great thanks to both of you. From newsfish@newsfish Thu Aug 1 00:33:28 2024 X-Received: by 10.236.61.230 with SMTP id w66mr19956806yhc.26.1432433313199; Sat, 23 May 2015 19:08:33 -0700 (PDT) X-Received: by 10.50.79.164 with SMTP id k4mr238550igx.6.1432433313150; Sat, 23 May 2015 19:08:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no3477131qgd.0!news-out.google.com!kd3ni26054igb.0!nntp.google.com!j8no8585730igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 May 2015 19:08:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> Subject: What is your VHDL design flow for a complex project? From: fl Injection-Date: Sun, 24 May 2015 02:08:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2225 X-Received-Body-CRC: 2090543819 Xref: news.eternal-september.org comp.lang.vhdl:3772 Hi, I have quite several years of digital logic design, days in TTL and CPLD. I even designed several small FPGA projects with VHDL. For complex FPGA project, I once used Xilinx System Generator on that project. I know the basics on FPGA design, such as timing constraints, some attributes about place and route. But I still feel very incompetence at VHDL on a large project. Of course, if I had the opportunity on a large VHDL project, I can get there sooner or later. Here I just want to get your advice on a large VHDL project procedures. Let me make my question a little clear. I guess it may work using top-down or down-top for a large project. My concern is mainly about clock timing at different modules (entities?). At System Generator, I can try to add z^-1 to some modules to get the desired result output. For a large VHDL project, it looks like much more troublesome on a delay unit trials. For example, on an FFT design, I think I should make the basic butterfly unit work. Then, I still feel uncomfortable on the following procedures to add the required index/address calculation using VHDL code. Could you give me some help? What procedures do you take on a large VHDL project? Thanks, From newsfish@newsfish Thu Aug 1 00:33:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Sat, 23 May 2015 23:20:42 -0400 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 24 May 2015 03:19:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13587"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Fo0cWrSs3B7vmDdZs06mF" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> Cancel-Lock: sha1:xd0HVHr2FwW6qjlZ9/8vqXz9uVg= Xref: news.eternal-september.org comp.lang.vhdl:3773 On 5/23/2015 10:08 PM, fl wrote: > Hi, > > I have quite several years of digital logic design, days in TTL and CPLD. I > even designed several small FPGA projects with VHDL. For complex FPGA project, > I once used Xilinx System Generator on that project. > > I know the basics on FPGA design, such as timing constraints, some attributes > about place and route. But I still feel very incompetence at VHDL on a large > project. Of course, if I had the opportunity on a large VHDL project, I can > get there sooner or later. Here I just want to get your advice on a large > VHDL project procedures. > > Let me make my question a little clear. I guess it may work using top-down > or down-top for a large project. My concern is mainly about clock timing at > different modules (entities?). At System Generator, I can try to add z^-1 to > some modules to get the desired result output. For a large VHDL project, it > looks like much more troublesome on a delay unit trials. For example, on an > FFT design, I think I should make the basic butterfly unit work. Then, I still > feel uncomfortable on the following procedures to add the required > index/address calculation using VHDL code. > > Could you give me some help? What procedures do you take on a large VHDL > project? I'm not sure what to tell you. I do most projects in a similar manner. I do a top down design with some idea of the complexity of each module. If modules are so complex that you have no idea of the pipeline delays you need to do more work on those modules to determine how fast they can run and how many pipeline delays there will be (register delays). Once you have that info, you can redesign the interconnect to keep everything synchronized. Some would call that bottom up implementation. I have always found block diagrams to be my friend and to help me understand all the relationships between modules. An FFT is actually easy to implement once you understand how they work. They often need pipelining to make them run fast. I have never found pipelining of a linear flow to be difficult. Do you have feedback paths that make your design more complex? What else are you using other than FFTs? -- Rick From newsfish@newsfish Thu Aug 1 00:33:29 2024 X-Received: by 10.141.23.133 with SMTP id z127mr3832527qhd.5.1432475032142; Sun, 24 May 2015 06:43:52 -0700 (PDT) X-Received: by 10.50.137.101 with SMTP id qh5mr264364igb.3.1432475032106; Sun, 24 May 2015 06:43:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no3548166qgd.1!news-out.google.com!n7ni42893igk.0!nntp.google.com!h15no8046995igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 May 2015 06:43:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Subject: Re: What is your VHDL design flow for a complex project? From: fl Injection-Date: Sun, 24 May 2015 13:43:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 55 Xref: news.eternal-september.org comp.lang.vhdl:3774 On Saturday, May 23, 2015 at 8:20:47 PM UTC-7, rickman wrote: > On 5/23/2015 10:08 PM, fl wrote: > > Hi, > > > > I have quite several years of digital logic design, days in TTL and CPLD. I > > even designed several small FPGA projects with VHDL. For complex FPGA project, > > I once used Xilinx System Generator on that project. > > > > I know the basics on FPGA design, such as timing constraints, some attributes > > about place and route. But I still feel very incompetence at VHDL on a large > > project. Of course, if I had the opportunity on a large VHDL project, I can > > get there sooner or later. Here I just want to get your advice on a large > > VHDL project procedures. > > > > Let me make my question a little clear. I guess it may work using top-down > > or down-top for a large project. My concern is mainly about clock timing at > > different modules (entities?). At System Generator, I can try to add z^-1 to > > some modules to get the desired result output. For a large VHDL project, it > > looks like much more troublesome on a delay unit trials. For example, on an > > FFT design, I think I should make the basic butterfly unit work. Then, I still > > feel uncomfortable on the following procedures to add the required > > index/address calculation using VHDL code. > > > > Could you give me some help? What procedures do you take on a large VHDL > > project? > > I'm not sure what to tell you. I do most projects in a similar manner. > I do a top down design with some idea of the complexity of each > module. If modules are so complex that you have no idea of the pipeline > delays you need to do more work on those modules to determine how fast > they can run and how many pipeline delays there will be (register > delays). Once you have that info, you can redesign the interconnect to > keep everything synchronized. Some would call that bottom up > implementation. > > I have always found block diagrams to be my friend and to help me > understand all the relationships between modules. An FFT is actually > easy to implement once you understand how they work. They often need > pipelining to make them run fast. I have never found pipelining of a > linear flow to be difficult. Do you have feedback paths that make your > design more complex? What else are you using other than FFTs? > > -- > > Rick Thanks, Rick. I can imagine it could be more difficult when there is feedback for a high speed module. FFT has a simple, regular structure. For me, I am still in the phase of FFT. I know FFT and its coding in C, even in assembly code. I do not have time to finish a VHDL FFT yet. The main difficulties are about the memory addressing, twiddle coef selection etc. Yes, I need to be patient to work on these interconnect between memory, twiddle and multipliers. From newsfish@newsfish Thu Aug 1 00:33:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Sun, 24 May 2015 10:33:13 -0400 Organization: A noiseless patient Spider Lines: 69 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 24 May 2015 14:32:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="9535"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18STOxt2eAj+v6ATi6ojMgM" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Cancel-Lock: sha1:g0kp9RTUsVq9y5LAJsiiiajHQt0= Xref: news.eternal-september.org comp.lang.vhdl:3775 On 5/24/2015 9:43 AM, fl wrote: > On Saturday, May 23, 2015 at 8:20:47 PM UTC-7, rickman wrote: >> On 5/23/2015 10:08 PM, fl wrote: >>> Hi, >>> >>> I have quite several years of digital logic design, days in TTL and CPLD. I >>> even designed several small FPGA projects with VHDL. For complex FPGA project, >>> I once used Xilinx System Generator on that project. >>> >>> I know the basics on FPGA design, such as timing constraints, some attributes >>> about place and route. But I still feel very incompetence at VHDL on a large >>> project. Of course, if I had the opportunity on a large VHDL project, I can >>> get there sooner or later. Here I just want to get your advice on a large >>> VHDL project procedures. >>> >>> Let me make my question a little clear. I guess it may work using top-down >>> or down-top for a large project. My concern is mainly about clock timing at >>> different modules (entities?). At System Generator, I can try to add z^-1 to >>> some modules to get the desired result output. For a large VHDL project, it >>> looks like much more troublesome on a delay unit trials. For example, on an >>> FFT design, I think I should make the basic butterfly unit work. Then, I still >>> feel uncomfortable on the following procedures to add the required >>> index/address calculation using VHDL code. >>> >>> Could you give me some help? What procedures do you take on a large VHDL >>> project? >> >> I'm not sure what to tell you. I do most projects in a similar manner. >> I do a top down design with some idea of the complexity of each >> module. If modules are so complex that you have no idea of the pipeline >> delays you need to do more work on those modules to determine how fast >> they can run and how many pipeline delays there will be (register >> delays). Once you have that info, you can redesign the interconnect to >> keep everything synchronized. Some would call that bottom up >> implementation. >> >> I have always found block diagrams to be my friend and to help me >> understand all the relationships between modules. An FFT is actually >> easy to implement once you understand how they work. They often need >> pipelining to make them run fast. I have never found pipelining of a >> linear flow to be difficult. Do you have feedback paths that make your >> design more complex? What else are you using other than FFTs? >> >> -- >> >> Rick > > Thanks, Rick. I can imagine it could be more difficult when there is > feedback for a high speed module. FFT has a simple, regular structure. > For me, I am still in the phase of FFT. I know FFT and its coding in C, > even in assembly code. I do not have time to finish a VHDL FFT yet. The main > difficulties are about the memory addressing, twiddle coef selection etc. > Yes, I need to be patient to work on these interconnect between memory, > twiddle and multipliers. Maybe this stuff comes easier to me than most. I cut my teeth on signal processing back in the 80's working on array processors. They were rack cabinets of boards which did the same thing DSP chips do now. I was testing boards in the machine and so got to see and debug every part of the device at a micro level. I think the key to designing an FFT in hardware is much like these machines. First understand the timing of the multiplier. Then everything else will be to feed data to and from the multiplier so it never rests. -- Rick From newsfish@newsfish Thu Aug 1 00:33:29 2024 X-Received: by 10.50.114.129 with SMTP id jg1mr27880688igb.3.1432614803046; Mon, 25 May 2015 21:33:23 -0700 (PDT) X-Received: by 10.140.104.72 with SMTP id z66mr13734qge.14.1432614802877; Mon, 25 May 2015 21:33:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!j8no9543260igd.0!news-out.google.com!k20ni44933qgd.0!nntp.google.com!z60no3844919qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 25 May 2015 21:33:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.46.198.142; posting-account=fZovLAoAAAD3S-AUwPsJor4VbxwCeVmC NNTP-Posting-Host: 62.46.198.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> Subject: how to generate random time delays for simulation during compile time From: mubinicyer@gmail.com Injection-Date: Tue, 26 May 2015 04:33:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3776 I have ring oscilator design, I am generating 32 ring oscillators using fol= lowing code. How can I generate random time delays instead of loop variable= "i"? (I am sorry for code, it doesn't look like code formatted, I am writi= ng this post from mobile browser) for i in 0 to nr_entries-1 generate =20 multiple_n: w_entity=20 generic map (delay =3D> (i+1) * 1 ps , chain_len =3D> nr_chains) -- d= elay must be "random" from 100 to 300 ps port map ( rst_i =3D> s_rst, out_o =3D> s_inp(i) ); end generate; From newsfish@newsfish Thu Aug 1 00:33:30 2024 X-Received: by 10.42.129.20 with SMTP id o20mr37322269ics.19.1432671147366; Tue, 26 May 2015 13:12:27 -0700 (PDT) X-Received: by 10.140.98.138 with SMTP id o10mr359733qge.33.1432671147332; Tue, 26 May 2015 13:12:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no9902145igd.0!news-out.google.com!k20ni44948qgd.0!nntp.google.com!z60no3984277qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 May 2015 13:12:27 -0700 (PDT) In-Reply-To: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=190.247.132.79; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 190.247.132.79 References: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <91cd81d4-e919-4232-87a9-f91d20d56e8e@googlegroups.com> Subject: Re: how to generate random time delays for simulation during compile time From: Leonardo Capossio Injection-Date: Tue, 26 May 2015 20:12:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3777 El martes, 26 de mayo de 2015, 1:33:25 (UTC-3), mubin...@gmail.com escribi= =F3: > I have ring oscilator design, I am generating 32 ring oscillators using f= ollowing code. How can I generate random time delays instead of loop variab= le "i"? (I am sorry for code, it doesn't look like code formatted, I am wri= ting this post from mobile browser) >=20 > for i in 0 to nr_entries-1 generate =20 > multiple_n: w_entity=20 > generic map (delay =3D> (i+1) * 1 ps , chain_len =3D> nr_chains) --= delay must be "random" from 100 to 300 ps > port map ( > rst_i =3D> s_rst, > out_o =3D> s_inp(i) > ); > end generate; A well known trick, a quick search returns: http://vhdlguru.blogspot.com.ar/2013/08/generating-random-numbers-in-vhdl.h= tml From newsfish@newsfish Thu Aug 1 00:33:30 2024 X-Received: by 10.42.50.210 with SMTP id b18mr38362491icg.17.1432674782507; Tue, 26 May 2015 14:13:02 -0700 (PDT) X-Received: by 10.140.94.166 with SMTP id g35mr105969qge.1.1432674782329; Tue, 26 May 2015 14:13:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!j8no9924168igd.0!news-out.google.com!k20ni44951qgd.0!nntp.google.com!z60no3992918qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 May 2015 14:13:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.112.103.16; posting-account=Uy1rkAoAAABZ1DIR2wcD1AFFThUQYsGJ NNTP-Posting-Host: 79.112.103.16 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <42df585d-1ebc-444c-a785-cf8cbf043b8a@googlegroups.com> Subject: Assign same signal in one block - Verilog From: george.isachi@gmail.com Injection-Date: Tue, 26 May 2015 21:13:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3778 Hi, I want to make an assignment to a output signal in the same block but I need to keep some information and for that I need to do a double assignment in the same block. Can you please take a look: parameter VALID_BIT = 0; [...] if(data_in_cfg[VALID_BIT] == 0) begin data_out_cfg <= {DATA_WIDTH{1'b1}}; data_out_cfg[VALID_BIT] <= 1'b0; end else begin data_out_cfg <= (data_in_cfg >> BIT_NUMBERS); data_out_cfg[VALID_BIT] <= 1'b1; end From newsfish@newsfish Thu Aug 1 00:33:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp1-1.free.fr!not-for-mail Date: Tue, 26 May 2015 23:49:21 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: how to generate random time delays for simulation during compile time References: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> <91cd81d4-e919-4232-87a9-f91d20d56e8e@googlegroups.com> In-Reply-To: <91cd81d4-e919-4232-87a9-f91d20d56e8e@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 23 Message-ID: <5564ea61$0$2981$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 26 May 2015 23:49:21 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1432676961 news-3.free.fr 2981 88.185.146.198:1836 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:3779 Le 26/05/2015 22:12, Leonardo Capossio a écrit : > El martes, 26 de mayo de 2015, 1:33:25 (UTC-3), mubin...@gmail.com escribió: >> I have ring oscilator design, I am generating 32 ring oscillators using following code. How can I generate random time delays instead of loop variable "i"? (I am sorry for code, it doesn't look like code formatted, I am writing this post from mobile browser) >> >> for i in 0 to nr_entries-1 generate >> multiple_n: w_entity >> generic map (delay => (i+1) * 1 ps , chain_len => nr_chains) -- delay must be "random" from 100 to 300 ps >> port map ( >> rst_i => s_rst, >> out_o => s_inp(i) >> ); >> end generate; > > A well known trick, a quick search returns: > http://vhdlguru.blogspot.com.ar/2013/08/generating-random-numbers-in-vhdl.html Very nice but it won't work for a generic parameter, as requested by the original poster. It is probably possible to use the UNIFORM procedure from the math_real package to generate pseudo-random numbers inside the for...generate loop. Nicolas From newsfish@newsfish Thu Aug 1 00:33:31 2024 X-Received: by 10.236.61.82 with SMTP id v58mr38816566yhc.15.1432693469747; Tue, 26 May 2015 19:24:29 -0700 (PDT) X-Received: by 10.182.219.42 with SMTP id pl10mr179577obc.29.1432693469631; Tue, 26 May 2015 19:24:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no4021260qgd.1!news-out.google.com!kd3ni28818igb.0!nntp.google.com!m20no1786iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 May 2015 19:24:29 -0700 (PDT) In-Reply-To: <5564ea61$0$2981$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> <91cd81d4-e919-4232-87a9-f91d20d56e8e@googlegroups.com> <5564ea61$0$2981$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <03916ea5-bdd3-4918-bcbb-0e4c7b90c9bf@googlegroups.com> Subject: Re: how to generate random time delays for simulation during compile time From: Andy Injection-Date: Wed, 27 May 2015 02:24:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:3780 Take a look at Open Source VHDL Verification Methodology (osvvm.org). It provides constrained randomization, coverage modeling and more. You need to declare constant(s) initialized by function calls, then map the generics to the constants. Andy From newsfish@newsfish Thu Aug 1 00:33:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Assign same signal in one block - Verilog Followup-To: comp.lang.verilog Date: Wed, 27 May 2015 08:47:22 -0400 Organization: Alacron, Inc. Lines: 28 Message-ID: References: <42df585d-1ebc-444c-a785-cf8cbf043b8a@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 27 May 2015 12:45:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="32264"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+h7NFgYPXbxbCRiMl/rv1e4D8gzNF7G10=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <42df585d-1ebc-444c-a785-cf8cbf043b8a@googlegroups.com> Cancel-Lock: sha1:z4G5xYDSdAljaaNUNjV6uisZQ90= Xref: news.eternal-september.org comp.lang.vhdl:3781 george.isachi@gmail.com wrote: > Hi, > > I want to make an assignment to a output signal in the same block but I need to keep some information and for that I need to do a double assignment in the same block. Can you please take a look: > > parameter VALID_BIT = 0; > [...] > if(data_in_cfg[VALID_BIT] == 0) begin > data_out_cfg <= {DATA_WIDTH{1'b1}}; > data_out_cfg[VALID_BIT] <= 1'b0; > end else begin > data_out_cfg <= (data_in_cfg >> BIT_NUMBERS); > data_out_cfg[VALID_BIT] <= 1'b1; > end You do realize this is a VHDL newsgroup - setting follow-up to comp.lang.verilog It's not clear what your question is. Are you talking about first assigning all bits of data_out_cfg and then assigning only the VALID bit? That's perfectly acceptable and the final assigned value would be the same as if you only assigned bits other than the VALID bit in the first assignment (no "double" assignment). i.e. the last assignment "wins" when you make more than one. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:31 2024 X-Received: by 10.52.168.130 with SMTP id zw2mr28418660vdb.5.1433161300355; Mon, 01 Jun 2015 05:21:40 -0700 (PDT) X-Received: by 10.140.28.73 with SMTP id 67mr260427qgy.36.1433161300257; Mon, 01 Jun 2015 05:21:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no4982985qgd.1!news-out.google.com!4ni134qgh.1!nntp.google.com!z60no4982979qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 1 Jun 2015 05:21:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> <236c4dcb-ae8f-40ef-ad22-b1b5e823eb87@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Open source unit testing framework release From: olof.kraigher@gmail.com Injection-Date: Mon, 01 Jun 2015 12:21:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 3 Xref: news.eternal-september.org comp.lang.vhdl:3782 We have now officially added VUnit support for GHDL. Big thanks to Tristan who fixed many bugs and implemented some nice features for this to be possible. I would like to recommend anyone who has not used GHDL for a while to take a look at it again as there have been major improvements and lots of VHDL 2008 support added lately. From newsfish@newsfish Thu Aug 1 00:33:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 02 Jun 2015 17:12:59 -0500 From: Irhamish Subject: Re: Carry Save Adder (CSA) Verilog code Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 5d78c448-4830-45c4-bfea-e5fb0898b98a References: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> Message-ID: Date: Tue, 02 Jun 2015 17:12:59 -0500 Lines: 5 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-HNc5CNEhdi6PaDRmMaT384zbpgUKTNx0WW6S2J7ldSPGyX1NtbOeEd1fcOW/crHPmxEEnFKUmAJxSK2!U5L3p4VyCCXrfhrBRiGxo2zlQTzbaJY7lNQglSYavwHZNvf14SnzPAxvp5y4JD0Pq3Jv/CFUvCMZ!6h4= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1045 Xref: news.eternal-september.org comp.lang.vhdl:3783 need 3 to 2 compresser..!! with figures From newsfish@newsfish Thu Aug 1 00:33:32 2024 X-Received: by 10.13.202.211 with SMTP id m202mr18078255ywd.19.1433768070514; Mon, 08 Jun 2015 05:54:30 -0700 (PDT) X-Received: by 10.50.4.34 with SMTP id h2mr160843igh.7.1433768070485; Mon, 08 Jun 2015 05:54:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!q107no5829qgd.0!news-out.google.com!n7ni4248igk.0!nntp.google.com!h15no62756igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Jun 2015 05:54:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=138.128.222.98; posting-account=XUZW3woAAAAvqjhEa35ql7jqrM4YjoTn NNTP-Posting-Host: 138.128.222.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> Subject: verilog syntax check From: Yang Luo Injection-Date: Mon, 08 Jun 2015 12:54:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: news.eternal-september.org comp.lang.vhdl:3784 I'm using modelsim se 10.1c. I find that modelsim for syntax checking is not strict. There are some examples: 1) I use default settings to build a project. There is no error or warning whenn compiling but I used an undefined variable, only when simulating the signal is red line. Example code: input [D_SIZE: 0] i_a; wire signed [D_SIZE: 0] w_a; assign w_ia = i_a; 2) When using unassigned variable , the same situation with above. Example code: wire signed [D_SIZE: 0] w_ib; wire signed [D_SIZE: 0] w_id; wire signed [D_SIZE: 0] w_bd; assign w_bd = w_ib - w_id; Question: How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do? Another question: Modelsim rebuilding and cleanup project, how to operate? how to operate that I can know the compilation is all recompiled? From newsfish@newsfish Thu Aug 1 00:33:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: verilog syntax check Date: Mon, 08 Jun 2015 13:34:12 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 8 Jun 2015 17:32:59 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="11456"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/+Fzm/PxYqvm4U0nJprjTx" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> Cancel-Lock: sha1:Afc7PYVDkgrFSqKUYUXGDJOYvLI= Xref: news.eternal-september.org comp.lang.vhdl:3785 On 6/8/2015 8:54 AM, Yang Luo wrote: > I'm using modelsim se 10.1c. I find that modelsim for syntax checking is not strict. > There are some examples: > 1) I use default settings to build a project. There is no error or warning whenn compiling but I used an undefined variable, only when simulating the signal is red line. > Example code: > input [D_SIZE: 0] i_a; > wire signed [D_SIZE: 0] w_a; > assign w_ia = i_a; > 2) When using unassigned variable , the same situation with above. > Example code: > wire signed [D_SIZE: 0] w_ib; > wire signed [D_SIZE: 0] w_id; > wire signed [D_SIZE: 0] w_bd; > assign w_bd = w_ib - w_id; > Question: > How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do? > Another question: > Modelsim rebuilding and cleanup project, how to operate? how to operate that I can know the compilation is all recompiled? I see you posted this to the verilog and VHDL groups. You might try posting to the FPGA group instead of VHDL. -- Rick From newsfish@newsfish Thu Aug 1 00:33:33 2024 X-Received: by 10.50.50.97 with SMTP id b1mr20053656igo.9.1433795257404; Mon, 08 Jun 2015 13:27:37 -0700 (PDT) X-Received: by 10.50.72.42 with SMTP id a10mr193856igv.14.1433795257374; Mon, 08 Jun 2015 13:27:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no251835igd.0!news-out.google.com!kd3ni458igb.0!nntp.google.com!h15no251833igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Jun 2015 13:27:36 -0700 (PDT) In-Reply-To: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6b20d495-2426-4e83-884a-e2819aa93d25@googlegroups.com> Subject: Re: verilog syntax check From: KJ Injection-Date: Mon, 08 Jun 2015 20:27:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3786 On Monday, June 8, 2015 at 8:54:31 AM UTC-4, Yang Luo wrote: > Question: > How should I do to get more strict syntax checking in modelsim? If models= im cannot get strict checking, is there other software can do? If your code is intended to be synthesized at some point, then a relatively= easy to catch unconnected inputs like you have in your code is simply to r= un it through synthesis (i.e. Quartus if targeting Altera). An unconnected= input during synthesis will cause a warning to be reported. Peruse the li= st of warnings and go from there. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:33 2024 X-Received: by 10.43.69.83 with SMTP id yb19mr7719636icb.32.1433971557665; Wed, 10 Jun 2015 14:25:57 -0700 (PDT) X-Received: by 10.140.19.76 with SMTP id 70mr102819qgg.21.1433971557539; Wed, 10 Jun 2015 14:25:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no1266841igd.0!news-out.google.com!k20ni414qgd.0!nntp.google.com!q107no471996qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Jun 2015 14:25:57 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <138ebd46-75c7-4a5e-bcb7-6c29bf3b4d30@googlegroups.com> Subject: Increased test performance with VUnit From: Lars Asplund Injection-Date: Wed, 10 Jun 2015 21:25:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 42 Xref: news.eternal-september.org comp.lang.vhdl:3787 VUnit, the open source unit testing framework for VHDL (https://github.com/= LarsAsplund/vunit), has now added support for multithreaded execution. Than= ks to the nature of unit testing with several independent test cases in eac= h testbench (test suite) it lends itself to parallel execution. Simply take= your VUnit run script and add the -p option to specify the number of threa= ds/test cases you want to run in parallel. python run.py -p For example, the figures below show the relative speed improvements for dif= ferent number of threads when running on my quad core laptop with ModelSim-= Altera Starter Edition under Windows. My script runs a couple of testbenche= s, each with several test cases, for a total of about 60 test cases. If my = simulation threads never blocked on anything like I/O it wouldn't be much p= oint in using more threads than the number of cores but since that's not th= e case the example shows improved performance beyond that point. Eventually= you don't get any more performance by adding threads and there are differe= nt reasons for that. You can't be faster than your slowest test case, there= 's no point in having more threads than the number of test cases, at some p= oint the overhead of another thread is larger than the gain of the added pa= rallelism. You have to experiment to find your optimum. number of threads: speed improvement 1: 1.0x 2: 1.8x 3: 2.5x 4: 2.8x 5: 3.1x 6: 3.3x 7: 3.4x 8: 3.4x 9: 3.5x 10: 3.5x 11: 3.6x 12: 3.5x 13: 3.5x 14: 3.4x 15: 3.4x 16: 3.3x 17: 3.3x 18: 3.3x 19: 3.2x 20: 3.1x From newsfish@newsfish Thu Aug 1 00:33:33 2024 X-Received: by 10.43.69.83 with SMTP id yb19mr19264218icb.32.1434116383590; Fri, 12 Jun 2015 06:39:43 -0700 (PDT) X-Received: by 10.140.106.247 with SMTP id e110mr215692qgf.7.1434116383449; Fri, 12 Jun 2015 06:39:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no2100715igd.0!news-out.google.com!k20ni1129qgd.0!nntp.google.com!z60no823261qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Jun 2015 06:39:43 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.114.130; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.114.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Subject: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Fri, 12 Jun 2015 13:39:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3788 According to the Wilson Report (2014 Wilson Research Group Functional Verif= ication Study) on average 50% of FPGA designers' time is spent on verificat= ion, and almost half of that verification time is spent on debugging. This = means: 1. Good reports for unexpected design behaviour is critical. 2. Good progress reporting is also critical. 3. Good basic testbench features are required Thus we need a library with good functionality for mismatch reporting, prog= ress reporting and for checks etc. that are needed for every single testben= ch; like=20 - checking value against expected - waiting for something to happen - with a timeout - checking stability of a signal - waiting for a signal to be stable for a given time (with timeout) The only free library library (to my knowledge) to provide all this functio= nality is Bitvis Utility Library.=20 A bonus feature of this library is that the user threshold is extremely low= , as this has been a main goal throughout the development. Advanced feature= s are available when you need them. The library is free and open source, - and you will be up and running withi= n 20 min (by browsing through the downloadable PPT presentation). The library has been checked to work with simulators from Mentor, Aldec and= Xilinx. Version 2.5 with lots of new functionality was just published. If this sounds interesting, you should read the below intro. You can download the library and PPT from http://bitvis.no/resources/utilit= y-library-download/ without any registration. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D TB Purpose The purpose of a testbench (TB) is to check the behaviour of your DUT (Devi= ce Under Test). This really goes without saying, - but sometimes stating th= e obvious is really needed. For any testbench you always provide stimuli an= d check the response. Sometimes this is a simple operation, and sometimes t= his is really complex. Most testbenches do however have some basic checking= aspects in common. Basic Checking Aspects Checking a signal value against an expected value - sometimes with partial = don't care or a margin Checking stability on a given signal (that a certain time has elapsed since= the last signal event) Waiting for a signal change or specific value on a signal Improving TB development efficiency and quality The checks above are easily implemented in VHDL, or better - in self-made s= ub-programs. The challenge is not to make the actual procedures and functio= ns, but to add functionality to these checks to allow far more efficient TB= development and problem debugging. The following are some examples that wi= ll significantly speed up your FPGA development: Reporting the actual mismatch - like 'was 0xFE, but expected 0xFF' yields i= mportant debug-information Reporting what is actually being checked - like 'Checking correct CRC for p= acket 1' yields another piece of important information Reporting the source of a failing mismatch leads the problem search in the = right direction (e.g. problem in UART 1) A positive acknowledge when passing the test is very useful when building t= he TB, BFMs, Analysers, etc Allowing the positive acknowledge to be filtered away is really useful when= this part is working Counting alerts (errors, warnings, etc) and potentially stopping on N error= s allows good debugging flexibility Ignoring certain alerts is useful when provoking a misbehaviour Timeout on waiting for an event to happen inside a given time window - with= a proper message - rather than hanging on a 'wait until' Adding this functionality makes everything simpler, faster and better. The = TB code will be more understandable (by anyone) and far simpler to maintain= and extend. Debugging of both the DUT and TB will be far more efficient. T= he progress report will be more understandable and make more sense to anyon= e. And the quality of the design and the TB will increase significantly. A major impact on TB development Now going back to the introduction. The sad fact is that for most testbench= es a lot of development time is wasted and the quality of the TB is insuffi= cient, and a major reason for this is the lack of a structured approach to = logging and checking. The good news is that all this functionality is avail= able for free through Bitvis Utility Library. Bitvis Utility Library is a f= ree, open source VHDL library that will yield a major efficiency and qualit= y improvement for almost all FPGA (or ASIC) development. The library has be= en downloaded by developers all over the world, and the feedback has been v= ery good - also from specialists in the VHDL community. Bitvis Utility Library also has excellent support for logging/reporting and= verbosity control (see a previous post on LinkedIn). The combination of th= e logging/reporting/verbosity and checking support - all provided with Bitv= is Utility Library - now makes it possible to develop more structured testb= enches, with better verification of DUT functionality and better simulation= transcripts with progress report and debug-support - and at the same time = reduce the development workload and schedule. For more advanced testbenches you might need additional support and TB stru= cture for coverage (e.g. via OSVVM) and simultaneous access (stimuli/check)= (e.g. via UVVM) on multiple interfaces, but you still need the functionali= ty provided by Bitvis Utility Library as your base. A very low user threshold An essential feature of this library is that it has an extremely low user t= hreshold, and at the same time has advanced options available when needed f= or more complex testbenches. You will be up and running, making far better = testbenches in less than one hour. Invest 10 minutes to browse through our powerpoint presentations on 'Making= a simple, structured and efficient VHDL testbench - Step-by-step' and/or '= Bitvis Utility Library Concepts and usage', both available for download (wi= th no registration) from http://bitvis.no/resources/utility-library-downloa= d/. The library may be downloaded from the same page. The library is free, and there is no catch. Enjoy :-) From newsfish@newsfish Thu Aug 1 00:33:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 12 Jun 2015 14:28:29 GMT Lines: 47 Message-ID: References: X-Trace: individual.net lyDO62yrMKUkMB2UU+ve7w+lXcWMK8YnPokVnhNdXuFrHrf4QQ X-Orig-Path: not-for-mail Cancel-Lock: sha1:Y2i1RvbateQ8O3+dUNkf/aQI4xo= sha1:cf4uz5V3BoIokWpFkFGmQtHG02s= User-Agent: tin/2.1.1-20120623 ("Mulindry") (UNIX) (Linux/3.2.0-4-686-pae (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3789 Hi everyeone, last attempt... I'm cross-posting here from the SystemC Accellera Forum and comp.arch.fpga since I *hope* I'm going to receive more feedback here than there. alb wrote: [] > I've recently started to wonder what kind of project I can start with > to get my hands on SystemC and TLM. I know there are tons of tutorials, > getting started like materials, open libraries, open platforms and I > believe I can get my head around most of that stuff, but one thing I'd > like to get advice on is how complex should be my first project to make > my learning process more effective. > > I've started proposing modelling with SystemC in my group because we > often lack of a tool to explore the bottle neck of our architectures > and realize about it too late down in the development phase. I've got > granted a 30% of my time for the next 6 months to learn SystemC and TLM > and come up with a reasonably shaped showcase. > > One of our core challenges is mass storage (for space applications), > therefore I thought about modelling a possible architecture involving > NAND Flash storage handled through some processor and high speed data > link. > > Most of the elements of this fictitious architecture are somehow > available on the net and I would have started plugging things together > for a start. > > Does this sound too naive, or is this application too complex to be > achievable in such a short time? > > One critical element in this task would be to make the management > understand how much they should invest in 'training/learning' before > getting some benefit out of it. > > Any pointer/suggestion/comment is highly appreciated, > > Al > -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Thu Aug 1 00:33:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: Sat, 13 Jun 2015 11:52:50 +0000 (UTC) Organization: A noiseless patient Spider Lines: 35 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 13 Jun 2015 11:52:50 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="12069"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX183SDvkXFNUdfFBpsHZihZxcr1rpS9/o0s=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:F3x4V6mfKLuSC2hUBUKNljPf2UA= Xref: news.eternal-september.org comp.lang.vhdl:3790 On Fri, 12 Jun 2015 14:28:29 +0000, alb wrote: > Hi everyeone, last attempt... > > I'm cross-posting here from the SystemC Accellera Forum and > comp.arch.fpga since I *hope* I'm going to receive more feedback here > than there. Since you cross-posted to comp.lang.vhdl, the feedback you might expect is that AnythingC is likely to be too firmly based on a foundation of sand, and therefore an unnecessarily difficult road to hardware. at least that's my opinion, and it's why I do some relatively high level modelling in VHDL. Anything synthesisable via C is also potentially synthesisable via VHDL, with less room for compiler-diagnosable errors. Where this potential isn't translated into practice, we need to nudge the synth tool vendors a little... Where VHDL gives up I use a very similar language, but in which I can for example create arbitrary fixed point types (natively, not via extensions) write generic algorithms, and instantiate them with both float and these fixed types to evaluate accuracy, determine the word lengths required, and so on. That gives me a sound basis for a trivial port to VHDL. It also gives me full object orientation where I need it, and access via import mechanisms to anything written in C or C++. Design-by-contract via pre/postconditions is also available though I haven't used that yet, nor have I used the formal proof extensions, but these are much more attractive options to me than anything I've seen offered by System-C. Unfortunately this doesn't help you with System-C. -- Brian From newsfish@newsfish Thu Aug 1 00:33:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source Date: Sat, 13 Jun 2015 12:05:43 +0000 (UTC) Organization: A noiseless patient Spider Lines: 50 Message-ID: References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 13 Jun 2015 12:05:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="12069"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19aABQLBKRxr6pYc62Go9mf+4zWxylOggQ=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:/wi0UUBQ/6iHU/LUUuTr5VvdP9o= Xref: news.eternal-september.org comp.lang.vhdl:3791 On Fri, 12 Jun 2015 06:39:43 -0700, espen.tallaksen wrote: > According to the Wilson Report (2014 Wilson Research Group Functional > Verification Study) on average 50% of FPGA designers' time is spent on > verification, and almost half of that verification time is spent on > debugging. This means: > > 1. Good reports for unexpected design behaviour is critical. > 2. Good progress reporting is also critical. > 3. Good basic testbench features are required > > Thus we need a library with good functionality for mismatch reporting, > progress reporting and for checks etc. that are needed for every single > testbench; like - checking value against expected - waiting for > something to happen - with a timeout - checking stability of a signal - > waiting for a signal to be stable for a given time (with timeout) > > The only free library library (to my knowledge) to provide all this > functionality is Bitvis Utility Library. It's great to see a resurgence in VHDL tool development! How does it compare with other modern VHDL testbench libraries like OSVVM and Vunit? Especially great to see lively competition between open-source tools, where it sometimes feels like the commercial vendors wish VHDL would die quietly... http://osvvm.org/ https://github.com/LarsAsplund/vunit Have you tried it with GHDL and GTKwave, to keep the whole simulation toolchain open source? https://sourceforge.net/projects/ghdl-updates/ Both the above libraries now work with the leading edge of GHDL, and have pushed its VHDL-2008 support forwards so another GHDL release should happen soon. Tristan, ghdl's main developer, has been especially active lately in making this happen. So, any reports of incompatibilities between Bitvis and GHDL would be welcomed via https://sourceforge.net/p/ghdl-updates/tickets/?source=navbar Thanks, -- Brian From newsfish@newsfish Thu Aug 1 00:33:34 2024 X-Received: by 10.129.128.199 with SMTP id q190mr28345534ywf.44.1434231864241; Sat, 13 Jun 2015 14:44:24 -0700 (PDT) X-Received: by 10.182.44.163 with SMTP id f3mr157177obm.7.1434231864162; Sat, 13 Jun 2015 14:44:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no1064671qgd.1!news-out.google.com!n7ni9344igk.0!nntp.google.com!h15no2746654igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Jun 2015 14:44:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: hands on experience on SystemC From: michael6866 Injection-Date: Sat, 13 Jun 2015 21:44:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3792 My two cents embedded below with "MK>": > at least that's my opinion, and it's why I do some relatively high level= =20 > modelling in VHDL. Anything synthesisable via C is also potentially=20 > synthesisable via VHDL, with less room for compiler-diagnosable errors.= =20 > Where this potential isn't translated into practice, we need to nudge the= =20 > synth tool vendors a little... MK> High level synthesis is a trend. Though there is still a long way to go= , I believe eventually the design methodology will evolve to HLS just as ho= w GL evolved to RTL. Some major EDA vendors are spending more and more effo= rt on developing HLS tools and some already get proven in real projects (se= e CtoS / Stratus for example). I'm not saying how good HLS is today, but le= arning SystemC can definitely give you some fresh ideas on those fancy stuf= f. Moreover, SystemC is not all about HLS. For examples: (1) It gives you the ability for fast prototyping / architecture exploring.= VHDL doesn't give you all the kits required for System level modeling and = the turnaround time for architecture exploring is not short with VHDL. (2) It has faster simulation speed. Although you can do some high level mod= eling with VHDL or Verilog, the simulation speed is not as fast as SystemC.= We've done some experiments on bringing up Linux on an ARM based SoC in si= mulation, with models coded up in SystemC and Verilog individually. One big= reason is the differences between the simulation engines. The VHDL simulat= ion engine almost has a fixed scheduling semantics and accuracy. In general= it cannot give you "coarse granularity" type of simulation (it may look li= ke, but the engine itself is not).=20 (3) It's much easier coding virtual platform with SystemC / TLM. Again, tak= ing the Linux bootup example and consider how complex it would be if modeli= ng all components with VHDL. Yes, you can have some IPs to accelerate the w= ork, but it's still much more complex than using C++. MK> Today it's really a trade-off between accuracy and speed when consideri= ng SystemC vs VHDL/Verilog. There are a lot of places where SystemC can hel= p you the most. Also, there is nothing to prevent you from doing mixed simu= lation. Actually TLM + RTL (some companies call it "soft hybrid") gets pret= ty popular these days. > Where VHDL gives up I use a very similar language, but in which I can for= =20 > example create arbitrary fixed point types (natively, not via extensions)= =20 > write generic algorithms, and instantiate them with both float and these= =20 > fixed types to evaluate accuracy, determine the word lengths required,=20 > and so on.=20 MK> Regarding the fixed point types, it's transparent to the user whether o= r not the type in SystemC is native. For generic programming there is no re= ason why SystemC cannot do it - it's C++ essentially therefore it comes wit= h the best GP tool kits. > It also gives me full object orientation where I need it, and access via= =20 > import mechanisms to anything written in C or C++. Design-by-contract via= =20 > pre/postconditions is also available though I haven't used that yet, nor= =20 > have I used the formal proof extensions, but these are much more=20 > attractive options to me than anything I've seen offered by System-C. MK> Design-by-contract is also achievable in C++ (although may not be that = attractive). For example, the Contract++ is already adopted by Boost. Again= SystemC itself is just a C++ library and there is nothing to prevent you f= rom using other C++ libraries.=20 From newsfish@newsfish Thu Aug 1 00:33:35 2024 X-Received: by 10.182.52.199 with SMTP id v7mr37241770obo.36.1434355856578; Mon, 15 Jun 2015 01:10:56 -0700 (PDT) X-Received: by 10.140.109.35 with SMTP id k32mr341701qgf.34.1434355856473; Mon, 15 Jun 2015 01:10:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no2808103igd.0!news-out.google.com!k20ni1860qgd.0!nntp.google.com!z60no1281913qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Jun 2015 01:10:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.114.130; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.114.130 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Mon, 15 Jun 2015 08:10:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3793 > It's great to see a resurgence in VHDL tool development! >=20 > How does it compare with other modern VHDL testbench libraries like OSVVM= =20 > and Vunit? >=20 > Especially great to see lively competition between open-source tools,=20 > where it sometimes feels like the commercial vendors wish VHDL would die= =20 > quietly... >=20 > http://osvvm.org/ > https://github.com/LarsAsplund/vunit >=20 > Have you tried it with GHDL and GTKwave, to keep the whole simulation=20 > toolchain open source? >=20 > https://sourceforge.net/projects/ghdl-updates/ >=20 > Both the above libraries now work with the leading edge of GHDL, and have= =20 > pushed its VHDL-2008 support forwards so another GHDL release should=20 > happen soon. Tristan, ghdl's main developer, has been especially active= =20 > lately in making this happen. >=20 > So, any reports of incompatibilities between Bitvis and GHDL would be=20 > welcomed via=20 > https://sourceforge.net/p/ghdl-updates/tickets/?source=3Dnavbar >=20 > Thanks, > -- Brian Hi Brian, Bitvis Utility Library (BVUL) is complementary to OSVVM and Vunit - with so= me minor overlaps. The coverage and advanced random gen. of OSVVM and the u= nit test support of Vunit are great in combination with Bitvis Utility Libr= ary's checking/await and log/alert features. The main advantage with our li= brary is that it provides the functionality you need for every single VHDL = testbench independent of verification approach, - with a very low user thre= shold. We will soon make a new release of BVUL, where you can combine the coverage= and random generation of OSVVM seamlessly with BVUL, resulting in a major = improvement for more advanced testbenches. With respect to Vunit, Lars Asplund of Synective Labs (maintainer of Vunit)= stated already in February 2014 that he had used BVUL with Vunit and that = it works perfectly well. BVUL has been tested OK with Riviera Pro (Aldec), Modelsim (Mentor) and Viv= ado Sim (Xilinx). We can check compatibility with GHDL as well. (Currently we support a 2008, 2002 and 93 -version of BVUL, but we will soo= n only continue to develop the 2008 version.) Any feedback on BVUL is appreciated. -Espen From newsfish@newsfish Thu Aug 1 00:33:35 2024 X-Received: by 10.129.104.86 with SMTP id d83mr36415294ywc.12.1434364811506; Mon, 15 Jun 2015 03:40:11 -0700 (PDT) X-Received: by 10.140.19.170 with SMTP id 39mr31771qgh.9.1434364811468; Mon, 15 Jun 2015 03:40:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no1302649qgd.1!news-out.google.com!4ni1697qgh.1!nntp.google.com!z60no1302647qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Jun 2015 03:40:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77978758-969d-4dcc-8c7f-d4469c024425@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Mon, 15 Jun 2015 10:40:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3794 Den m=E5ndag 15 juni 2015 kl. 10:10:59 UTC+2 skrev espen.t...@bitvis.no: > > It's great to see a resurgence in VHDL tool development! > >=20 > > How does it compare with other modern VHDL testbench libraries like OSV= VM=20 > > and Vunit? > >=20 > > Especially great to see lively competition between open-source tools,= =20 > > where it sometimes feels like the commercial vendors wish VHDL would di= e=20 > > quietly... > >=20 > > http://osvvm.org/ > > https://github.com/LarsAsplund/vunit > >=20 > > Have you tried it with GHDL and GTKwave, to keep the whole simulation= =20 > > toolchain open source? > >=20 > > https://sourceforge.net/projects/ghdl-updates/ > >=20 > > Both the above libraries now work with the leading edge of GHDL, and ha= ve=20 > > pushed its VHDL-2008 support forwards so another GHDL release should=20 > > happen soon. Tristan, ghdl's main developer, has been especially active= =20 > > lately in making this happen. > >=20 > > So, any reports of incompatibilities between Bitvis and GHDL would be= =20 > > welcomed via=20 > > https://sourceforge.net/p/ghdl-updates/tickets/?source=3Dnavbar > >=20 > > Thanks, > > -- Brian >=20 > Hi Brian, >=20 > Bitvis Utility Library (BVUL) is complementary to OSVVM and Vunit - with = some minor overlaps. The coverage and advanced random gen. of OSVVM and the= unit test support of Vunit are great in combination with Bitvis Utility Li= brary's checking/await and log/alert features. The main advantage with our = library is that it provides the functionality you need for every single VHD= L testbench independent of verification approach, - with a very low user th= reshold. > We will soon make a new release of BVUL, where you can combine the covera= ge and random generation of OSVVM seamlessly with BVUL, resulting in a majo= r improvement for more advanced testbenches. > With respect to Vunit, Lars Asplund of Synective Labs (maintainer of Vuni= t) stated already in February 2014 that he had used BVUL with Vunit and tha= t it works perfectly well. > BVUL has been tested OK with Riviera Pro (Aldec), Modelsim (Mentor) and V= ivado Sim (Xilinx). We can check compatibility with GHDL as well. > (Currently we support a 2008, 2002 and 93 -version of BVUL, but we will s= oon only continue to develop the 2008 version.) >=20 > Any feedback on BVUL is appreciated. > -Espen Hi Brian and Espen, The logging, the checking, and the unit test running functionality of VUnit= are layers building on top of each other (in that order) and they have a l= oose coupling. This means that it is easy to use the unit test running func= tionality on top of other assertion solutions as well, e.g. plain VHDL asse= rts or BVUL or OVL or OSVVM which also added similar functionality earlier = this year. Integration with the OSVVM functionality is described in https:/= /github.com/LarsAsplund/vunit/blob/master/examples/osvvm_integration/osvvm_= integration.md and the same principle applies to BVUL as well. The layered approach also means that the VUnit logging and checking functio= nality can be used standalone for other verification approaches without the= layer for running unit tests. When used standalone you can choose between = the VHDL-93 or VHDL-200x versions depending on the simulator you have. VUni= t's official support is currently limited to supporting ModelSim and GHDL b= ut that limitation is driven by making the unit test running layer to work = since that layer involves scripting of the simulator. The other layers are = not limited in this way. /Lars From newsfish@newsfish Thu Aug 1 00:33:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 15 Jun 2015 20:19:33 GMT Lines: 51 Message-ID: References: X-Trace: individual.net CNaDJgAkSzo/EnapeBJZMQ2tjnGlrcFSro16/c17OLWOue8G2i X-Orig-Path: not-for-mail Cancel-Lock: sha1:QfshSkk+7G93ogkohwGP8EWsijg= User-Agent: tin/2.2.1-20140504 ("Tober an Righ") (UNIX) (Linux/3.16.0-4-686-pae (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3795 Hi Brian, Brian Drummond wrote: >> I'm cross-posting here from the SystemC Accellera Forum and >> comp.arch.fpga since I *hope* I'm going to receive more feedback here >> than there. > > Since you cross-posted to comp.lang.vhdl, the feedback you might expect > is that AnythingC is likely to be too firmly based on a foundation of > sand, and therefore an unnecessarily difficult road to hardware. Uhm, I'm not sure I've fully grasped what you wanted to say here. Just to clarify my intentions, I'm not looking for synthesizable SystemC, I know enough of VHDL for not needing another language to synthesize what I want to synthesize. My aim here is to leverage more the possibility to perform Architecture exploration. While deciding where to cut the system in pieces you dramatically impose constraints that might be turning into bottlenecks and get your project doomed. [] > Where VHDL gives up I use a very similar language, but in which I can for > example create arbitrary fixed point types (natively, not via extensions) > write generic algorithms, and instantiate them with both float and these > fixed types to evaluate accuracy, determine the word lengths required, > and so on. What kind of language are you referring to? > That gives me a sound basis for a trivial port to VHDL. > > It also gives me full object orientation where I need it, and access via > import mechanisms to anything written in C or C++. Design-by-contract via > pre/postconditions is also available though I haven't used that yet, nor > have I used the formal proof extensions, but these are much more > attractive options to me than anything I've seen offered by System-C. Designing by contract is a paradigm, you can build it in assembler or in any other language. Some of them support it natively, some others through a set of libraries, but the bottom line is still the same. Even if a bit OT, here a nice link (http://dbc.rubyforge.org/) about a ruby utility to parse contracts written in C comments and generate the necessary code compliant to the Design by Contract paradigm. > Unfortunately this doesn't help you with System-C. Discussing always helps, in one way or another! Al From newsfish@newsfish Thu Aug 1 00:33:36 2024 X-Received: by 10.141.23.133 with SMTP id z127mr1415023qhd.5.1434473306780; Tue, 16 Jun 2015 09:48:26 -0700 (PDT) X-Received: by 10.140.88.80 with SMTP id s74mr32569qgd.16.1434473306754; Tue, 16 Jun 2015 09:48:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no1555825qgd.1!news-out.google.com!k20ni2053qgd.0!nntp.google.com!q107no1557319qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jun 2015 09:48:26 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: hands on experience on SystemC From: Lars Asplund Injection-Date: Tue, 16 Jun 2015 16:48:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3796 Hi Al, If the lack of TLM in VHDL is your only reason for looking at other languag= es I recommend that you have a look at the open source com mechanism that w= as added to VUnit a month ago. It implements high-level message passing for= VHDL which you need to do TLM. I should probably describe com in a post of= its own but here are some pointers The user guide for com can be found at https://github.com/LarsAsplund/vunit= /blob/master/vhdl/com/user_guide.md and a testbench example is found at https://github.com/LarsAsplund/vunit/tr= ee/master/examples/com. Com was developed by a number of VUnit community me= mbers. We took our private code and ideas, improved on that, and came up wi= th the solution that you can download. Everything was done in the open so i= f you want to follow the discussion you can have a look at this thread http= s://github.com/LarsAsplund/vunit/issues/23. Com is a separate module in the= VUnit project so it can be used standalone (but we recommend you to use VU= nit anyway :-))=20 From newsfish@newsfish Thu Aug 1 00:33:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 16 Jun 2015 21:30:34 GMT Lines: 41 Message-ID: References: X-Trace: individual.net N9f0PfvKx/IlrDM/NXbqrQxyrxle5O+Nitp3xFq49j3zp5hgZJ X-Orig-Path: not-for-mail Cancel-Lock: sha1:F9EmQzQclYNLUFI0CG8icpQ0aiQ= User-Agent: tin/2.2.1-20140504 ("Tober an Righ") (UNIX) (Linux/3.16.0-4-686-pae (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3797 Hi Lars, Lars Asplund wrote: > If the lack of TLM in VHDL is your only reason for looking at other > languages I recommend that you have a look at the open source com > mechanism that was added to VUnit a month ago. It implements > high-level message passing for VHDL which you need to do TLM. I should > probably describe com in a post of its own but here are some pointers. Thanks for the pointers! While some level of modeling can be done in VHDL, and maybe should be done at that level, you certainly do not want to venture with it when you're facing multiple cores/interfaces interacting with each other. SystemC has been conceived for modeling and especially for providing a simulation platform to run a real algorithm on top, while still permitting performance analysis and architectural exploration. Sure, I can change the size of the bus in my VHDL model and get to the same results, but I suppose it's more efficient to use SystemC rather than VHDL (and believe me, I'm a big fan of VHDL!). On top of it, why using the same language when you can learn a new one? There are potentially new paradigms at your disposal and enriching your vocabulary would only help your reasoning ;-). > > The user guide for com can be found at > https://github.com/LarsAsplund/vunit/blob/master/vhdl/com/user_guide.md > and a testbench example is found at > https://github.com/LarsAsplund/vunit/tree/master/examples/com. Com was > developed by a number of VUnit community members. We took our private > code and ideas, improved on that, and came up with the solution that > you can download. Everything was done in the open so if you want to > follow the discussion you can have a look at this thread > https://github.com/LarsAsplund/vunit/issues/23. Com is a separate > module in the VUnit project so it can be used standalone (but we > recommend you to use VUnit anyway :-)) Thanks again for the pointer! Al From newsfish@newsfish Thu Aug 1 00:33:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 16 Jun 2015 21:50:35 GMT Lines: 68 Message-ID: References: X-Trace: individual.net Bktt/WRpY9jKGQxTnb0ltAUKlGPmZe0un/l929lF5c6+bYAH2J X-Orig-Path: not-for-mail Cancel-Lock: sha1:aEMgEymKs87vaxbI37PuAVgOH28= User-Agent: tin/2.2.1-20140504 ("Tober an Righ") (UNIX) (Linux/3.16.0-4-686-pae (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3798 Hi Michael, I was about to post a reply yesterday when my computer crashed and I lost everything, that's why it took me more than foreseen to shape a followup to your post. Please follow inline. michael6866 wrote: > My two cents embedded below with "MK>": I suggest for the next time you follow some simple quoting rules. Please see here for a nice guideline: http://linux.sgms-centre.com/misc/netiquette.php#quoting [] > MK> High level synthesis is a trend. Though there is still a long way > to go, I believe eventually the design methodology will evolve to HLS > just as how GL evolved to RTL. Some major EDA vendors are spending > more and more effort on developing HLS tools and some already get > proven in real projects (see CtoS / Stratus for example). I'm not > saying how good HLS is today, but learning SystemC can definitely give > you some fresh ideas on those fancy stuff. Moreover, SystemC is not > all about HLS. For examples: I'm not interested at the moment to HLS and even less to the synthesizable subsets of SystemC. I'm more into system architecture and performance analysis. > (2) It has faster simulation speed. [] Beaware of simulation speed comparisons. If you minimize the amount of signals and maximize the number of variables, you should be getting a very nice improve (both in maintainability and interoperability with other models). > (3) It's much easier coding virtual platform with SystemC / TLM. [] I agree, the main reason is to still learn a new language, so that I can 'talk' more clearly! A model is also a type of executable specification, which in my type of environment is rarely implemented, but huge benefits would arise whenever is done. > MK> Today it's really a trade-off between accuracy and speed when > considering SystemC vs VHDL/Verilog. There are a lot of places where > SystemC can help you the most. Also, there is nothing to prevent you > from doing mixed simulation. Actually TLM + RTL (some companies call > it "soft hybrid") gets pretty popular these days. You also need to take into account another factor: model availability. The amount of effort to write a simple model in VHDL vs SystemC is certainly not measureable though, therefore often forgotten. [] >> It also gives me full object orientation where I need it, and access via >> import mechanisms to anything written in C or C++. Design-by-contract via >> pre/postconditions is also available though I haven't used that yet, nor >> have I used the formal proof extensions, but these are much more >> attractive options to me than anything I've seen offered by System-C. > MK> Design-by-contract is also achievable in C++ (although may not be > that attractive). For example, the Contract++ is already adopted by > Boost. Again SystemC itself is just a C++ library and there is nothing > to prevent you from using other C++ libraries. There exist a ruby utility since more than 10 years (http://www.onlamp.com/pub/a/onlamp/2004/10/28/design_by_contract_in_c.html), which inserts C code starting from some markup in the comments. I've never used it but seems to me pretty well done. Al From newsfish@newsfish Thu Aug 1 00:33:36 2024 X-Received: by 10.66.101.40 with SMTP id fd8mr3980507pab.14.1434502299086; Tue, 16 Jun 2015 17:51:39 -0700 (PDT) X-Received: by 10.182.68.51 with SMTP id s19mr33925obt.6.1434502299006; Tue, 16 Jun 2015 17:51:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no4255683igd.0!news-out.google.com!kd3ni8596igb.0!nntp.google.com!h15no4255682igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jun 2015 17:51:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: hands on experience on SystemC From: michael6866 Injection-Date: Wed, 17 Jun 2015 00:51:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 76 Xref: news.eternal-september.org comp.lang.vhdl:3799 On Tuesday, June 16, 2015 at 5:50:37 PM UTC-4, alb wrote: > I suggest for the next time you follow some simple quoting rules. Please > see here for a nice guideline: > http://linux.sgms-centre.com/misc/netiquette.php#quoting Sorry I'm used to the embedded style as that's the one I used at work. Hopefully I'll get it right this time :) > > [] > > MK> High level synthesis is a trend. Though there is still a long way > > to go, I believe eventually the design methodology will evolve to HLS > > just as how GL evolved to RTL. Some major EDA vendors are spending > > more and more effort on developing HLS tools and some already get > > proven in real projects (see CtoS / Stratus for example). I'm not > > saying how good HLS is today, but learning SystemC can definitely give > > you some fresh ideas on those fancy stuff. Moreover, SystemC is not > > all about HLS. For examples: > > I'm not interested at the moment to HLS and even less to the > synthesizable subsets of SystemC. I'm more into system architecture and > performance analysis. Understood. I was replying to Brian. The point is HLS is a powerful technology and it will thrive soon. > > > (2) It has faster simulation speed. [] > > Beaware of simulation speed comparisons. If you minimize the amount of > signals and maximize the number of variables, you should be getting a > very nice improve (both in maintainability and interoperability with > other models). Agree. However even with the same magnitude of signals / variables, SystemC is still much faster. As I mentioned this is because the way the RTL simulation engine works is different than the SystemC kernel. > > > (3) It's much easier coding virtual platform with SystemC / TLM. > [] > > I agree, the main reason is to still learn a new language, so that I can > 'talk' more clearly! A model is also a type of executable specification, > which in my type of environment is rarely implemented, but huge benefits > would arise whenever is done. You're talking about golden reference. In that case there are many choices besides SystemC. Of course SystemC is among the best so it's well worth learning. > > > MK> Today it's really a trade-off between accuracy and speed when > > considering SystemC vs VHDL/Verilog. There are a lot of places where > > SystemC can help you the most. Also, there is nothing to prevent you > > from doing mixed simulation. Actually TLM + RTL (some companies call > > it "soft hybrid") gets pretty popular these days. > > You also need to take into account another factor: model availability. > The amount of effort to write a simple model in VHDL vs SystemC is > certainly not measureable though, therefore often forgotten. Agree. However number of SystemC IP is much less than the RTL one today. The good thing is many companies are starting on the former. > > [] > >> It also gives me full object orientation where I need it, and access via > >> import mechanisms to anything written in C or C++. Design-by-contract via > >> pre/postconditions is also available though I haven't used that yet, nor > >> have I used the formal proof extensions, but these are much more > >> attractive options to me than anything I've seen offered by System-C. > > > MK> Design-by-contract is also achievable in C++ (although may not be > > that attractive). For example, the Contract++ is already adopted by > > Boost. Again SystemC itself is just a C++ library and there is nothing > > to prevent you from using other C++ libraries. > > There exist a ruby utility since more than 10 years > (http://www.onlamp.com/pub/a/onlamp/2004/10/28/design_by_contract_in_c.html), > which inserts C code starting from some markup in the comments. I've > never used it but seems to me pretty well done. Thanks for the Info. However I don't use design by contract. My reply was merely to point out it's achievable in C++ world. > > Al Regards, Michael From newsfish@newsfish Thu Aug 1 00:33:37 2024 X-Received: by 10.68.143.229 with SMTP id sh5mr3815566pbb.11.1434502500899; Tue, 16 Jun 2015 17:55:00 -0700 (PDT) X-Received: by 10.182.19.194 with SMTP id h2mr32711obe.41.1434502500769; Tue, 16 Jun 2015 17:55:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4256581igd.0!news-out.google.com!7ni495igs.0!nntp.google.com!h15no3330129igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jun 2015 17:55:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> Subject: Re: hands on experience on SystemC From: michael6866 Injection-Date: Wed, 17 Jun 2015 00:55:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3800 On Tuesday, June 16, 2015 at 5:50:37 PM UTC-4, alb wrote: > I suggest for the next time you follow some simple quoting rules. Please > see here for a nice guideline: > http://linux.sgms-centre.com/misc/netiquette.php#quoting Sorry I'm used to the embedded style as that's the one I used at work. Hopefully I'll get it right this time :) > > [] > > MK> High level synthesis is a trend. Though there is still a long way > > to go, I believe eventually the design methodology will evolve to HLS > > just as how GL evolved to RTL. Some major EDA vendors are spending > > more and more effort on developing HLS tools and some already get > > proven in real projects (see CtoS / Stratus for example). I'm not > > saying how good HLS is today, but learning SystemC can definitely give > > you some fresh ideas on those fancy stuff. Moreover, SystemC is not > > all about HLS. For examples: > > I'm not interested at the moment to HLS and even less to the > synthesizable subsets of SystemC. I'm more into system architecture and > performance analysis. Understood. I was replying to Brian. The point is HLS is a powerful technology and it will thrive soon. > > > (2) It has faster simulation speed. [] > > Beaware of simulation speed comparisons. If you minimize the amount of > signals and maximize the number of variables, you should be getting a > very nice improve (both in maintainability and interoperability with > other models). Agree. However even with the same magnitude of signals / variables, SystemC is still much faster. As I mentioned this is because the way the RTL simulation engine works is different than the SystemC kernel. > > > (3) It's much easier coding virtual platform with SystemC / TLM. > [] > > I agree, the main reason is to still learn a new language, so that I can > 'talk' more clearly! A model is also a type of executable specification, > which in my type of environment is rarely implemented, but huge benefits > would arise whenever is done. You're talking about golden reference. In that case there are many choices besides SystemC. Of course SystemC is among the best so it's well worth learning. > > > MK> Today it's really a trade-off between accuracy and speed when > > considering SystemC vs VHDL/Verilog. There are a lot of places where > > SystemC can help you the most. Also, there is nothing to prevent you > > from doing mixed simulation. Actually TLM + RTL (some companies call > > it "soft hybrid") gets pretty popular these days. > > You also need to take into account another factor: model availability. > The amount of effort to write a simple model in VHDL vs SystemC is > certainly not measureable though, therefore often forgotten. Agree. However number of SystemC IP is much less than the RTL one today. The good thing is many companies are starting on the former. > > [] > >> It also gives me full object orientation where I need it, and access via > >> import mechanisms to anything written in C or C++. Design-by-contract via > >> pre/postconditions is also available though I haven't used that yet, nor > >> have I used the formal proof extensions, but these are much more > >> attractive options to me than anything I've seen offered by System-C. > > > MK> Design-by-contract is also achievable in C++ (although may not be > > that attractive). For example, the Contract++ is already adopted by > > Boost. Again SystemC itself is just a C++ library and there is nothing > > to prevent you from using other C++ libraries. > > There exist a ruby utility since more than 10 years > (http://www.onlamp.com/pub/a/onlamp/2004/10/28/design_by_contract_in_c.html), > which inserts C code starting from some markup in the comments. I've > never used it but seems to me pretty well done. Thanks for the Info. However I don't use design by contract. My reply was merely to point out it's achievable in C++ world. > > Al Regards, Michael From newsfish@newsfish Thu Aug 1 00:33:37 2024 X-Received: by 10.140.235.204 with SMTP id g195mr5468946qhc.3.1434525398793; Wed, 17 Jun 2015 00:16:38 -0700 (PDT) X-Received: by 10.140.96.137 with SMTP id k9mr77300qge.10.1434525398778; Wed, 17 Jun 2015 00:16:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q107no1660124qgd.0!news-out.google.com!4ni1982qgh.1!nntp.google.com!z60no1658626qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Jun 2015 00:16:38 -0700 (PDT) In-Reply-To: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: hands on experience on SystemC From: Lars Asplund Injection-Date: Wed, 17 Jun 2015 07:16:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2260 X-Received-Body-CRC: 1723880145 Xref: news.eternal-september.org comp.lang.vhdl:3801 Hi Al, Thanks for sharing. The reason for me asking is that the message passing in= VUnit wasn't developed to support TLM for hardware out of the box. It was = developed to enable high-level communication within testbenches, not within= the DUT. In that context we want to be focused on the information to excha= nge and with whom. We don't want to know where our counterparts are located= , we don't want communication to take time, we don't want to be exposed to = FIFOs limiting the communication capacity and so on. These are things that = becomes more interesting when you want to model hardware and it can be adde= d as an extra layer of functionality on top of the "pure" message passing. = Since you're working across the range of abstraction levels I'm interested = to see under what circumstances, if any, you see use cases for TLM in VHDL. A bit off topic... /Lars From newsfish@newsfish Thu Aug 1 00:33:37 2024 X-Received: by 10.70.127.174 with SMTP id nh14mr11444413pdb.8.1434610343205; Wed, 17 Jun 2015 23:52:23 -0700 (PDT) X-Received: by 10.140.20.148 with SMTP id 20mr65754qgj.20.1434610342949; Wed, 17 Jun 2015 23:52:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4857739igd.0!news-out.google.com!k20ni2479qgd.0!nntp.google.com!z60no1863310qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Jun 2015 23:52:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Thu, 18 Jun 2015 06:52:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3802 Just to clarify; VUnit is also independent of the verification approach of = the user. I have personally used to run constrained random verification usi= ng OSVVM, multi hour long end-to-end tests against golden reference data as= well as small directed unit tests. Typically a project would have a bit of= each. In projects I have been involved in where there were 200+ tests my e= stimate was that 60% were constrained random, 30% directed and 10% big end = to end. What makes VUnit different is that it is not just a VHDL library. It tries = to be a complete testing tool for VHDL in which the library features you de= scribe are one important piece of the puzzle. The cornerstones of VUnit are= : 1) Support for dependency scanning and incremental compilation. So that the edit/compile/run cycle is a fast as possible. 2) A VHDL library for checks/asserts/logging that are needed for writing the a= ctual test bench. Procedures for saving/loading test data to/from .csv and = .raw files etc. We also re-distribute OSVVM since it provides additional li= brary capabilities for random number generation, and coverage. 3) A Python command line interface such that tests can be automatically run ei= ther in batch or in GUI with minimal user effort. Such that test can be con= figured to run for all combinations of generic values. Such that tests can = be run in parallel. Such that VHDL testing can be integrated with Continous= Integration environments such as Jenkins.=20 The BVUL fills the role of 2) and could probably replace the corresponding = libraries that were created specifically for VUnit. As Lars Asplund mention= s the checking and logging libraries are orthogonal to other parts of VUnit= making it possible to use BVUL instead of the VUnit builtin checks. Replac= ing the built in parts of VUnit with BVUL has not been something I have inv= estigated that much since I would rather focus on adding missing functional= ity to VUnit rather than replacing existing functionality with something of= another flavor. Although 2) is an important part of the puzzle without 1) and 3) it is just= not as productive since the user has to perform a lot of manual work to ru= n, compile and administer their tests. Many companies have some home-brew v= ariant of 3) of varying quality though. The goal of VUnit was to make peopl= e stop re-inventing the wheel making their proprietary in-house solutions a= nd instead use the man hours to improve something that everyone can use. = =20 // The second main author of VUnit From newsfish@newsfish Thu Aug 1 00:33:38 2024 X-Received: by 10.68.94.35 with SMTP id cz3mr19127155pbb.5.1434707551383; Fri, 19 Jun 2015 02:52:31 -0700 (PDT) X-Received: by 10.140.98.138 with SMTP id o10mr91893qge.33.1434707551119; Fri, 19 Jun 2015 02:52:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no5413284igd.0!news-out.google.com!4ni2206qgh.1!nntp.google.com!z60no2075346qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jun 2015 02:52:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=89.221.115.64; posting-account=pPdiQAoAAABXyXlRIf4K6f14FyZc1g3D NNTP-Posting-Host: 89.221.115.64 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <55275971-1f7c-4322-8e23-266c09863f1a@googlegroups.com> Subject: Qucs stops working when I try to simulate scheme . From: edgars.visockis@gmail.com Injection-Date: Fri, 19 Jun 2015 09:52:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3803 Hi, I have test next week and I've been playing with VHDL language recently= and run into this error which I cant understand, maybe someone can help me= .=20 I'm testing simple generator who generates numbers from 0 to 7. Here is the= code : ----------------------------------------------- package mxx is subtype mytype is integer range 0 to 7; end package; library IEEE; use WORK.mxx.ALL; use IEEE.std_logic_1164.ALL; entity eightval_generators is generic (ti : time :=3D10 ns); port (sk : out mytype); end entity; architecture normala of eightval_generators is begin process begin for i in 0 to 7 loop sk <=3D i; wait for ti;=09 end loop; end process; end architecture; ----------------------------------------------- I have created schematic for code with appropriate output port and my simul= ation type is TimeList Digital simulation. If I change mytype to integer I = don't get error and all works. But for practice I wanted to use subtype and= limit it to my needs and add all of this as package to my project. But thi= s results in error which I would like to clear out . From newsfish@newsfish Thu Aug 1 00:33:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 19 Jun 2015 10:11:53 GMT Lines: 77 Message-ID: References: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> X-Trace: individual.net 8/Q324Clue0dumMC0l01sgzkBNeb+1P7xcpFyIZzdfFF6b8xq+ X-Orig-Path: not-for-mail Cancel-Lock: sha1:Tv/LQT/Z4UKvhQQ0TXYVnjELo6o= User-Agent: tin/2.2.1-20140504 ("Tober an Righ") (UNIX) (Linux/3.16.0-4-686-pae (i686)) Xref: news.eternal-september.org comp.lang.vhdl:3804 Hi Lars, Lars Asplund wrote: [] > Thanks for sharing. The reason for me asking is that the message > passing in VUnit wasn't developed to support TLM for hardware out of > the box. It was developed to enable high-level communication within > testbenches, not within the DUT. I'm not sure to which question or statement you're referring to. I think DUT need to be described with purely non-synthesizable construct that focus on the architecture rather than the details. This model can leverage the TLM message passing mechanism in order to do architecture exploration and allow to build a verification environment. Unfortunately this step is too often tossed away of the development plan to only find ourselves in the weeds too many weeks/months later. Non-synthesizable VHDL is also poorly taught and valued in undergraduate courses, the focus on the synthesizable subset of the language casts some habits into designers that are hard to break and lead eventually to poor perfomance. I've seen professionals writing testbenches as if they were to be synthesized! That's not what the language allows us to do. Likely some libraries and utilities are popping out and maybe help designers to write better simulation environments. > In that context we want to be focused > on the information to exchange and with whom. We don't want to know > where our counterparts are located, we don't want communication to > take time, we don't want to be exposed to FIFOs limiting the > communication capacity and so on. These are things that becomes more > interesting when you want to model hardware and it can be added as an > extra layer of functionality on top of the "pure" message passing. Message passing is an extremely important concept that is often forgotten when you are head down hitting your keyboard to write RTL. Building a function thinking in terms of messages passed from one point to another is a powerful tool that allows to see where these messages interact in the datapath and may help find a better way to avoid bottlenecks. I want/need to focus on the 'what's going on' part of the game, rather than on 'how is going on' and FWIK this is what a 'tool' like SystemC/TLM has been thought for. I believe I can do the same in non-synthesizable VHDL but I'd like to explore new constructs and see what suits the best for what. > Since you're working across the range of abstraction levels I'm > interested to see under what circumstances, if any, you see use cases > for TLM in VHDL. I think about TLM as a methodology rather than a library and what is important here is shifting approach according to the need. I know of a tool (TauhopHLS) which converts vhdl-2008 syntax into synthesizable vhdl-93, with the promise to bridge the gap between an high level modeling and the registers ticking. I haven't used the tool (yet), but 'standardizing' designs through a set of high level constructs is not less than building a libc for hardware! Why would you want to take care about the bits and pieces that happen behind the scenes? Let someone else optimize it for you, someone who knows the target technology better than you can possibly know and focus on the application *you* need to design. Resources in the FPGAs are increasing at an incredible pace and yet there are tons of designers that meticoulously care about the registers and the gates...on a million gates device? Good luck! Anyway, we definitely drifted OT here, but I'll venture in learning SystemC/TLM and see where this path will lead me to ;-). Alan Fitch, who maybe listening here, have pointed me to an incredibly well done tutorial by embecosm: http://www.embecosm.com/resources/appnotes/#EAN1. I'll see where I'll find myself in the end. Al From newsfish@newsfish Thu Aug 1 00:33:38 2024 X-Received: by 10.13.219.75 with SMTP id d72mr174664ywe.4.1434723640012; Fri, 19 Jun 2015 07:20:40 -0700 (PDT) X-Received: by 10.140.85.11 with SMTP id m11mr298511qgd.29.1434723639951; Fri, 19 Jun 2015 07:20:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no2121401qgd.1!news-out.google.com!k20ni2707qgd.0!nntp.google.com!q107no2123054qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jun 2015 07:20:39 -0700 (PDT) In-Reply-To: <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Fri, 19 Jun 2015 14:20:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3805 Hi Olof, I agree that BVUL only covers your item 2 above, but then again item 2 is where you can actually save by far the most hours in a complex FPGA project. Items 1 and 3 are also important, and will save quite a few hours. BVUL is however not just another flavour. BVUL has verbosity control, optional positive acknowledge on checks and some very important additional checks resulting in faster testbench development and faster debugging. We will also very soon integrate BVUL tighter with OSVVM and add even more advanced verification capabilities through UVVM (to be released soon). I think perhaps it could be great if we could cooperate on the combination Vunit and BVUL, so that we could get the best out of two worlds, but we could take that discussion off line ;-) -Espen From newsfish@newsfish Thu Aug 1 00:33:38 2024 X-Received: by 10.50.44.13 with SMTP id a13mr5662594igm.3.1434736970647; Fri, 19 Jun 2015 11:02:50 -0700 (PDT) X-Received: by 10.140.97.33 with SMTP id l30mr259202qge.23.1434736969470; Fri, 19 Jun 2015 11:02:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!h15no4125579igd.0!news-out.google.com!k20ni2729qgd.0!nntp.google.com!q107no2162690qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jun 2015 11:02:49 -0700 (PDT) In-Reply-To: <55275971-1f7c-4322-8e23-266c09863f1a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.125.175.43; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 64.125.175.43 References: <55275971-1f7c-4322-8e23-266c09863f1a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Qucs stops working when I try to simulate scheme . From: Jackie Christman Injection-Date: Fri, 19 Jun 2015 18:02:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3806 Hey check out my course for only $5 - this will help you with VHDL! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=5guys From newsfish@newsfish Thu Aug 1 00:33:39 2024 X-Received: by 10.182.241.105 with SMTP id wh9mr25308516obc.47.1434779902346; Fri, 19 Jun 2015 22:58:22 -0700 (PDT) X-Received: by 10.140.102.172 with SMTP id w41mr343235qge.40.1434779902226; Fri, 19 Jun 2015 22:58:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no5832274igd.0!news-out.google.com!k20ni2788qgd.0!nntp.google.com!z60no2237349qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jun 2015 22:58:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Sat, 20 Jun 2015 05:58:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3807 Espen, first I want to just note that the corresponding libraries in VUnit = also have the features you describe. Secondly, maybe this is down to personal preference but I would not value 1= ) and 3) less than 2). For most projects the majority of test benches do no= t need to be that advanced; check_equal with automatic report of "got vs ex= pected", random number generation, and some simple watchdog or timeout cove= rs 90% of the need.=20 My personal testing preference is that each VHDL entity should have a test = bench achieving full functional coverage. It is important to do this to dri= ve the design into a good partition of loosely coupled and testable entitie= s. Most entities will be small and their corresponding test benches run fas= t and then there is not much need for advanced logging or delayed failure. = In such a situation I have a strong preference for immediate failure on a f= ailing alert/check since when stopping immediately the VHDL call stack can = be emitted at the point of failure. I would rather open the simulator GUI a= nd look at the waveform or single step through the code past the failure, w= hich can be done by just running VUnit command line with the --gui flag. Th= e larger end-to-end tests are also required even using the above philosophy= and in such a situation more advanced logging and delayed alert/check fail= ure can be more useful but still check_equal takes you very far.=20 My experience is that without 1) and 3) many people tend to fall back into = just having the large end-to-end tests since it is such a burden to maintai= n the scripts to handle the small 200+ test cases which would have made the= code base a lot easier to maintain, with fever bugs and more modularity. V= Unit lets you just add a test to your testbench or add a new testbench and = it is automatically part of the test suite due to the test scanner feature.= When writing the test it also lets the user focus completely on their task= allowing them to effortlessly edit/compile/re-run with the just a single c= ommand. With all that said I would be interested in trying to collaborate in some w= ay and I have sent you a personal email. I can just note that we are doing = similar things and to me it seems a shame to fragment a small community by = having multiple competing/exclusive implementations of the same puzzle piec= e. On Friday, June 19, 2015 at 4:20:42 PM UTC+2, espen.t...@bitvis.no wrote: > Hi Olof, >=20 > I agree that BVUL only covers your item 2 above, but then again item 2 is= where you can actually save by far the most hours in a complex FPGA projec= t. Items 1 and 3 are also important, and will save quite a few hours. >=20 > BVUL is however not just another flavour. BVUL has verbosity control, opt= ional positive acknowledge on checks and some very important additional che= cks resulting in faster testbench development and faster debugging. > We will also very soon integrate BVUL tighter with OSVVM and add even mor= e advanced verification capabilities through UVVM (to be released soon). >=20 > I think perhaps it could be great if we could cooperate on the combinatio= n Vunit and BVUL, so that we could get the best out of two worlds, but we c= ould take that discussion off line ;-) >=20 > -Espen From newsfish@newsfish Thu Aug 1 00:33:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source Date: Sat, 20 Jun 2015 10:20:37 +0000 (UTC) Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 20 Jun 2015 10:20:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="9537"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18YQgCPTHkvjy2enU6KI+MPg2w3ZQT74ic=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:8z9QYH4+JxYpOREoOvl0CLFpx1M= Xref: news.eternal-september.org comp.lang.vhdl:3808 On Fri, 19 Jun 2015 07:20:39 -0700, espen.tallaksen wrote: > Hi Olof, > > I agree that BVUL only covers your item 2 above, but then again item 2 > is where you can actually save by far the most hours in a complex FPGA > project. Items 1 and 3 are also important, and will save quite a few > hours. > > I think perhaps it could be great if we could cooperate on the > combination Vunit and BVUL, so that we could get the best out of two > worlds, but we could take that discussion off line ;-) By all means take the details off-line but please summarize the outcome here! Thanks to yourself, Olof and Lars for discussing - and indeed, creating - these useful tools! -- Brian From newsfish@newsfish Thu Aug 1 00:33:39 2024 X-Received: by 10.13.207.1 with SMTP id r1mr26642799ywd.46.1434801044279; Sat, 20 Jun 2015 04:50:44 -0700 (PDT) X-Received: by 10.140.42.161 with SMTP id c30mr90868qga.30.1434801044262; Sat, 20 Jun 2015 04:50:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no2279880qgd.1!news-out.google.com!k20ni2820qgd.0!nntp.google.com!z60no2279879qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jun 2015 04:50:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e76b32f-723c-4e70-a5be-38e6053f68e1@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Sat, 20 Jun 2015 11:50:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3809 I downloaded the BVUL to have a look. It looks very similar to what we have= in VUnit. I noticed the example test bench bitvis_irqc/tb/irqc_tb.vhd coul= d benefit from the VUnit Python/VHDL automation. My interpretation is that = you use log messages with ID_LOG_HDR to visually/textually separate differe= nt independent test cases. I count 8 of those. With VUnit you could have th= ose 8 as actual independent test cases run in different simulations (or opt= ionally all in the same simulation) with individual pass/fail in the test r= eport. An individual specific test can be easily run from command line usin= g wildcard (*) pattern. VUnit would also ensure that each test case got its= own dedicated output folder to gather all simulation artifacts such as the= complete stderr/stdout, wlf and transcript as well as any other user defin= ed outputs such as images other binary data files. =20 On Saturday, June 20, 2015 at 12:21:59 PM UTC+2, Brian Drummond wrote: > On Fri, 19 Jun 2015 07:20:39 -0700, espen.tallaksen wrote: >=20 > > Hi Olof, > >=20 > > I agree that BVUL only covers your item 2 above, but then again item 2 > > is where you can actually save by far the most hours in a complex FPGA > > project. Items 1 and 3 are also important, and will save quite a few > > hours. > >=20 > > I think perhaps it could be great if we could cooperate on the > > combination Vunit and BVUL, so that we could get the best out of two > > worlds, but we could take that discussion off line ;-) >=20 > By all means take the details off-line but please summarize the outcome= =20 > here! >=20 > Thanks to yourself, Olof and Lars for discussing - and indeed, creating -= =20 > these useful tools! >=20 > -- Brian From newsfish@newsfish Thu Aug 1 00:33:40 2024 X-Received: by 10.50.4.34 with SMTP id h2mr10579021igh.8.1434803236450; Sat, 20 Jun 2015 05:27:16 -0700 (PDT) X-Received: by 10.140.19.76 with SMTP id 70mr38034qgg.21.1434803236322; Sat, 20 Jun 2015 05:27:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no138590igd.0!news-out.google.com!k20ni2820qgd.0!nntp.google.com!z60no2284026qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jun 2015 05:27:16 -0700 (PDT) In-Reply-To: <4e76b32f-723c-4e70-a5be-38e6053f68e1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <4e76b32f-723c-4e70-a5be-38e6053f68e1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Sat, 20 Jun 2015 12:27:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3810 I made a small effort to split the irqc_tb.vhd into use separate test using= VUnit. I had some problem with test independence of the "Check irq acknowl= edge and re-enable test" depending on a variable value from the previous "C= heck autonomy for all interrupts" test case but I soon found and fixed it. = I also ensured your _Alert.txt and _Log.txt files ended up in the test spec= ific output folders. I did not need to use any of your hardcoded compile sc= ripts since VUnit figured out the dependencies automatically. The non-verbo= se textual output when running looked like this. (The pass being in green c= olor in a real terminal): Starting irqc_lib.irqc_tb.Check defaults on output ports pass (P=3D1 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check defaults on output po= rts (0.9 seconds) Starting irqc_lib.irqc_tb.Check register defaults and access write read pass (P=3D2 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check register defaults and= access write read (0.3 seconds) Starting irqc_lib.irqc_tb.Check register trigger clear mechanism pass (P=3D3 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check register trigger clea= r mechanism (0.3 seconds) Starting irqc_lib.irqc_tb.Check interrupt sources IER IPR and irq2cpu pass (P=3D4 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check interrupt sources IER= IPR and irq2cpu (0.3 seconds) Starting irqc_lib.irqc_tb.Check autonomy for all interrupts pass (P=3D5 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check autonomy for all inte= rrupts (0.3 seconds) Starting irqc_lib.irqc_tb.Check irq acknowledge and re-enable pass (P=3D6 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check irq acknowledge and r= e-enable (0.3 seconds) Starting irqc_lib.irqc_tb.Check Reset pass (P=3D7 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check Reset (0.3 seconds) =3D=3D=3D=3D Summary =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D pass irqc_lib.irqc_tb.Check defaults on output ports (0.9 se= conds) pass irqc_lib.irqc_tb.Check register defaults and access write read (0.3 se= conds) pass irqc_lib.irqc_tb.Check register trigger clear mechanism (0.3 se= conds) pass irqc_lib.irqc_tb.Check interrupt sources IER IPR and irq2cpu (0.3 se= conds) pass irqc_lib.irqc_tb.Check autonomy for all interrupts (0.3 se= conds) pass irqc_lib.irqc_tb.Check irq acknowledge and re-enable (0.3 se= conds) pass irqc_lib.irqc_tb.Check Reset (0.3 se= conds) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D pass 7 of 7 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Total time was 2.6 seconds Elapsed time was 2.6 seconds =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D All passed! The run.py file used to drive everything looked like this: from os.path import dirname, join from vunit import VUnit root =3D dirname(__file__) ui =3D VUnit.from_argv() bvul_lib =3D ui.add_library("bitvis_util") bvul_lib.add_source_files(join(root, "bitvis_util", "src2008", "*.vhd")) bitvis_vip_spi_lib =3D ui.add_library("bitvis_vip_sbi") bitvis_vip_spi_lib.add_source_files(join(root, "bitvis_vip_sbi", "src", "*.= vhd")) irqc_lib =3D ui.add_library("irqc_lib") irqc_lib.add_source_files(join(root, "bitvis_irqc", "src", "*.vhd")) irqc_lib.add_source_files(join(root, "bitvis_irqc", "tb", "*.vhd")) ui.main() The modified irqc_tb.vhd looked like this: (The name collision with your an= d our log method prevented me from using our VHDL-2008 context for the VUni= t packages forcing me to use them individually to avoid exposing our log): --=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -- Copyright (c) 2015 by Bitvis AS. All rights reserved. -- A free license is hereby granted, free of charge, to any person obtainin= g -- a copy of this VHDL code and associated documentation files (for 'Bitvis= Utility Library'), -- to use, copy, modify, merge, publish and/or distribute - subject to the = following conditions: -- - This copyright notice shall be included as is in all copies or substa= ntial portions of the code and documentation -- - The files included in Bitvis Utility Library may only be used as a pa= rt of this library as a whole -- - The License file may not be modified -- - The calls in the code to the license file ('show_license') may not be= removed or modified. -- - No other conditions whatsoever may be added to those of this License -- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOU= T WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS = FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLA= IM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT O= F OR IN CONNECTION WITH BITVIS UTILITY LIBRARY. --=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ---------------------------------------------------------------------------= --------------- -- VHDL unit : Bitvis IRQC Library : irqc_tb -- -- Description : See dedicated powerpoint presentation and README-file(s) ---------------------------------------------------------------------------= --------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library STD; use std.textio.all; -- library ieee_proposed; -- use ieee_proposed.standard_additions.all; -- use ieee_proposed.std_logic_1164_additions.all; library vunit_lib; use vunit_lib.run_types_pkg.all; use vunit_lib.run_pkg.all; use vunit_lib.run_base_pkg.all; library bitvis_util; use bitvis_util.types_pkg.all; use bitvis_util.string_methods_pkg.all; use bitvis_util.adaptations_pkg.all; use bitvis_util.methods_pkg.all; library bitvis_vip_sbi; use bitvis_vip_sbi.sbi_bfm_pkg.all; use work.irqc_pif_pkg.all; -- Test case entity entity irqc_tb is generic (runner_cfg : runner_cfg_t); end entity; -- Test case architecture architecture func of irqc_tb is -- DSP interface and general control signals signal clk : std_logic :=3D '0'; signal arst : std_logic :=3D '0'; -- CPU interface signal cs : std_logic :=3D '0'; signal addr : unsigned(2 downto 0) :=3D (others =3D> '0'= ); signal wr : std_logic :=3D '0'; signal rd : std_logic :=3D '0'; signal din : std_logic_vector(7 downto 0) :=3D (others =3D> '0'= ); signal dout : std_logic_vector(7 downto 0) :=3D (others =3D> '0'= ); signal rdy : std_logic :=3D '1'; -- Always ready in the same c= lock cycle -- Interrupt related signals signal irq_source : std_logic_vector(C_NUM_SOURCES-1 downto 0) :=3D (o= thers =3D> '0'); signal irq2cpu : std_logic :=3D '0'; signal irq2cpu_ack : std_logic :=3D '0'; signal clock_ena : boolean :=3D false; constant C_CLK_PERIOD : time :=3D 10 ns; procedure clock_gen( signal clock_signal : inout std_logic; signal clock_ena : in boolean; constant clock_period : in time ) is variable v_first_half_clk_period : time :=3D C_CLK_PERIOD / 2; begin loop if not clock_ena then wait until clock_ena; end if; wait for v_first_half_clk_period; clock_signal <=3D not clock_signal; wait for (clock_period - v_first_half_clk_period); clock_signal <=3D not clock_signal; end loop; end; subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0); -- Trim (cut) a given vector to fit the number of irq sources (i.e. pot. = reduce width) function trim( constant source : std_logic_vector; constant num_bits : positive :=3D C_NUM_SOURCES) return t_irq_source is variable v_result : std_logic_vector(source'length-1 downto 0) :=3D sou= rce; begin return v_result(num_bits-1 downto 0); end; -- Fit a given vector to the number of irq sources by masking with zeros = above irq width function fit( constant source : std_logic_vector; constant num_bits : positive :=3D C_NUM_SOURCES) return std_logic_vector is variable v_result : std_logic_vector(source'length-1 downto 0) :=3D (ot= hers =3D> '0'); variable v_source : std_logic_vector(source'length-1 downto 0) :=3D sou= rce; begin v_result(num_bits-1 downto 0) :=3D v_source(num_bits-1 downto 0); return v_result; end; begin -------------------------------------------------------------------------= ---- -- Instantiate DUT -------------------------------------------------------------------------= ---- i_irqc: entity work.irqc port map ( -- DSP interface and general control signals clk =3D> clk, arst =3D> arst, -- CPU interface cs =3D> cs, addr =3D> addr, wr =3D> wr, rd =3D> rd, din =3D> din, dout =3D> dout, -- Interrupt related signals irq_source =3D> irq_source, irq2cpu =3D> irq2cpu, irq2cpu_ack =3D> irq2cpu_ack ); -- Set upt clock generator clock_gen(clk, clock_ena, 10 ns); ------------------------------------------------ -- PROCESS: p_main ------------------------------------------------ p_main: process constant C_SCOPE : string :=3D C_TB_SCOPE_DEFAULT; procedure pulse( signal target : inout std_logic; signal clock_signal : in std_logic; constant num_periods : in natural; constant msg : in string ) is begin if num_periods > 0 then wait until falling_edge(clock_signal); target <=3D '1'; for i in 1 to num_periods loop wait until falling_edge(clock_signal); end loop; else target <=3D '1'; wait for 0 ns; -- Delta cycle only end if; target <=3D '0'; log(ID_SEQUENCER_SUB, msg, C_SCOPE); end; procedure pulse( signal target : inout std_logic_vector; constant pulse_value : in std_logic_vector; signal clock_signal : in std_logic; constant num_periods : in natural; constant msg : in string) is begin if num_periods > 0 then wait until falling_edge(clock_signal); target <=3D pulse_value; for i in 1 to num_periods loop wait until falling_edge(clock_signal); end loop; else target <=3D pulse_value; wait for 0 ns; -- Delta cycle only end if; target(target'range) <=3D (others =3D> '0'); log(ID_SEQUENCER_SUB, "Pulsed to " & to_string(pulse_value, HEX, AS_I= S, INCL_RADIX) & ". " & msg, C_SCOPE); end; -- Log overloads for simplification procedure log( msg : string) is begin log(ID_SEQUENCER, msg, C_SCOPE); end; -- Overloads for PIF BFMs for SBI (Simple Bus Interface) procedure write( constant addr_value : in natural; constant data_value : in std_logic_vector; constant msg : in string) is begin sbi_write(to_unsigned(addr_value, addr'length), data_value, msg, clk, cs, addr, rd, wr, rdy, din, C_CLK_PERIOD, C_SCOPE); end; procedure check( constant addr_value : in natural; constant data_exp : in std_logic_vector; constant alert_level : in t_alert_level; constant msg : in string) is begin sbi_check(to_unsigned(addr_value, addr'length), data_exp, alert_level= , msg, clk, cs, addr, rd, wr, rdy, dout, C_CLK_PERIOD, C_SCOPE); end; procedure set_inputs_passive( dummy : t_void) is begin cs <=3D '0'; addr <=3D (others =3D> '0'); wr <=3D '0'; rd <=3D '0'; din <=3D (others =3D> '0'); irq_source <=3D (others =3D> '0'); irq2cpu_ack <=3D '0'; log(ID_SEQUENCER_SUB, "All inputs set passive", C_SCOPE); end; variable v_time_stamp : time :=3D 0 ns; variable v_irq_mask : std_logic_vector(7 downto 0); variable v_irq_mask_inv : std_logic_vector(7 downto 0); begin test_runner_setup(runner, runner_cfg); -- Use VUnit output path set_log_file_name(output_path(runner_cfg) & "_Log.txt"); set_alert_file_name(output_path(runner_cfg) & "_Alert.txt"); -- Print the configuration to the log report_global_ctrl(VOID); report_msg_id_panel(VOID); enable_log_msg(ALL_MESSAGES); --disable_log_msg(ALL_MESSAGES); --enable_log_msg(ID_LOG_HDR); log(ID_LOG_HDR, "Start Simulation of TB for IRQC", C_SCOPE); ------------------------------------------------------------ set_inputs_passive(VOID); clock_ena <=3D true; -- to start clock generator pulse(arst, clk, 10, "Pulsed reset-signal - active for 10T"); v_time_stamp :=3D now; -- time from which irq2cpu should be stable off= until triggered check_value(C_NUM_SOURCES > 0, FAILURE, "Must be at least 1 interrupt s= ource", C_SCOPE); check_value(C_NUM_SOURCES <=3D 8, TB_WARNING, "This TB is only checking= IRQC with up to 8 interrupt sources", C_SCOPE); while test_suite loop if run("Check defaults on output ports") then check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must be default = inactive", C_SCOPE); check_value(dout, x"00", ERROR, "Register data bus output must be d= efault passive"); elsif run("Check register defaults and access write read") then log("\nChecking Register defaults"); check(C_ADDR_IRR, x"00", ERROR, "IRR default"); check(C_ADDR_IER, x"00", ERROR, "IER default"); check(C_ADDR_IPR, x"00", ERROR, "IPR default"); check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED defaul= t"); log("\nChecking Register Write/Read"); write(C_ADDR_IER, fit(x"55"), "IER"); check(C_ADDR_IER, fit(x"55"), ERROR, "IER pure readback"); write(C_ADDR_IER, fit(x"AA"), "IER"); check(C_ADDR_IER, fit(x"AA"), ERROR, "IER pure readback"); write(C_ADDR_IER, fit(x"00"), "IER"); check(C_ADDR_IER, fit(x"00"), ERROR, "IER pure readback"); elsif run("Check register trigger clear mechanism") then write(C_ADDR_ITR, fit(x"AA"), "ITR : Set interrupts"); check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR"); write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts"); check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR"); write(C_ADDR_ICR, fit(x"71"), "ICR : Clear interrupts"); check(C_ADDR_IRR, fit(x"8E"), ERROR, "IRR"); write(C_ADDR_ICR, fit(x"85"), "ICR : Clear interrupts"); check(C_ADDR_IRR, fit(x"0A"), ERROR, "IRR"); write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts"); check(C_ADDR_IRR, fit(x"5F"), ERROR, "IRR"); write(C_ADDR_ICR, fit(x"5F"), "ICR : Clear interrupts"); check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR"); elsif run("Check interrupt sources IER IPR and irq2cpu") then log("\nChecking interrupts and IRR"); write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts"); pulse(irq_source, trim(x"AA"), clk, 1, "Pulse irq_source 1T"); check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR after irq pulses"); pulse(irq_source, trim(x"01"), clk, 1, "Add more interrupts"); check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses"); pulse(irq_source, trim(x"A1"), clk, 1, "Repeat same interrupts"); check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses"); pulse(irq_source, trim(x"54"), clk, 1, "Add remaining interrupts"); check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR after irq pulses"); write(C_ADDR_ICR, fit(x"AA"), "ICR : Clear half the interrupts"); pulse(irq_source, trim(x"A0"), clk, 1, "Add more interrupts"); check(C_ADDR_IRR, fit(x"F5"), ERROR, "IRR after irq pulses"); write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts"); check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR after clearing all"); log("Checking IER IPR and irq2cpu"); write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts"); write(C_ADDR_IER, fit(x"55"), "IER : Enable some interrupts"); write(C_ADDR_ITR, fit(x"AA"), "ITR : Trigger non-enable interrupts"= ); check(C_ADDR_IPR, fit(x"00"), ERROR, "IPR should not be active"); check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED should= not be active"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Enable main interru= pt to CPU"); check(C_ADDR_IRQ2CPU_ALLOWED, x"01", ERROR, "IRQ2CPU_ALLOWED should= now be active"); check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be in= active", C_SCOPE); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allow= ed on irq2cpu", C_SCOPE); pulse(irq_source, trim(x"01"), clk, 1, "Add a single enabled interr= upt"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt exp= ected immediately", C_SCOPE); v_time_stamp :=3D now; -- from time of stable active irq2cpu check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR should now be active"); check(C_ADDR_IPR, fit(x"01"), ERROR, "IPR should now be active"); log("\nMore details checked in the autonomy section below"); check_value(irq2cpu, '1', ERROR, "Interrupt to CPU must still be ac= tive", C_SCOPE); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allow= ed on irq2cpu", C_SCOPE); elsif run("Check autonomy for all interrupts") then write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts"); write(C_ADDR_IER, fit(x"FF"), "IER : Disable all interrupts"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to = CPU"); for i in 0 to C_NUM_SOURCES-1 loop log(" "); log("- Checking irq_source(" & to_string(i) & ") and all correspo= nding functionality"); log("- - Check interrupt activation not affected by non related i= nterrupts or registers"); v_time_stamp :=3D now; -- from time of stable inactive irq2cpu v_irq_mask :=3D (i =3D> '1', others =3D> '0'); v_irq_mask_inv :=3D (i =3D> '0', others =3D> '1'); write(C_ADDR_IER, v_irq_mask, "IER : Enable selected interrupt"); pulse(irq_source, trim(v_irq_mask_inv), clk, 1, "Pulse all non-en= abled interrupts"); write(C_ADDR_ITR, v_irq_mask_inv, "ITR : Trigger all non-enabled = interrupts"); check(C_ADDR_IRR, fit(v_irq_mask_inv), ERROR, "IRR not yet trigge= red"); check(C_ADDR_IPR, x"00", ERROR, "IPR not yet triggered"); check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be = inactive", C_SCOPE); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes all= owed on irq2cpu", C_SCOPE); pulse(irq_source, trim(v_irq_mask), clk, 1, "Pulse the enabled in= terrupt"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt e= xpected immediately", C_SCOPE); check(C_ADDR_IRR, fit(x"FF"), ERROR, "All IRR triggered"); check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR triggered for selected"= ); log("\n- - Check interrupt deactivation not affected by non relat= ed interrupts or registers"); v_time_stamp :=3D now; -- from time of stable active irq2cpu write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled in= terrupts"); write(C_ADDR_IER, fit(x"FF"), "IER : Enable all interrupts"); write(C_ADDR_IER, v_irq_mask, "IER : Disable non-selected interru= pts"); pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts"); write(C_ADDR_ITR, x"FF", "ITR : Trigger all interrupts"); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes all= owed on irq2cpu (=3D'1')", C_SCOPE); write(C_ADDR_IER, v_irq_mask_inv, "IER : Enable all interrupts bu= t disable selected"); check_value(irq2cpu, '1', ERROR, "Interrupt to CPU still active",= C_SCOPE); check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR still active for all"); write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled in= terrupts"); await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt d= eactivation expected immediately", C_SCOPE); write(C_ADDR_IER, v_irq_mask, "IER : Re-enable selected interrupt= "); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt r= eactivation expected immediately", C_SCOPE); check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR still active for select= ed"); write(C_ADDR_ICR, v_irq_mask, "ICR : Clear selected interrupt"); check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must go inacti= ve", C_SCOPE); check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive"); check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive"); write(C_ADDR_IER, x"00", "IER : Disable all interrupts"); end loop; report_alert_counters(INTERMEDIATE); -- Report intermediate counter= s elsif run("Check irq acknowledge and re-enable") then log("- Activate interrupt"); write(C_ADDR_ITR, x"01", "ICR : Set single upper interrupt"); write(C_ADDR_IER, x"01", "IER : Enable single upper interrupts"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to = CPU"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt act= ivation expected", C_SCOPE); v_time_stamp :=3D now; -- from time of stable active irq2cpu log("\n- Try potential malfunction"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to = CPU again - should not affect anything"); write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should n= ot affect anything"); write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - = should not affect anything"); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allow= ed on irq2cpu (=3D'1')", C_SCOPE); log("\n- Acknowledge and deactivate interrupt"); pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack"); await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt dea= ctivation expected", C_SCOPE); v_time_stamp :=3D now; -- from time of stable inactive irq2cpu log("\n- Test for potential malfunction"); write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Disable int= errupt to CPU again - should not affect anything"); write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - = should not affect anything"); write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should n= ot affect anything"); write(C_ADDR_ITR, x"FF", "ICR : Trigger all interrupts"); write(C_ADDR_IER, x"FF", "IER : Enable all interrupts"); pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts"); pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack"); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allow= ed on irq2cpu (=3D'0')", C_SCOPE); log("\n- Re-/de-activation"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrup= t to CPU"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt rea= ctivation expected", C_SCOPE); write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Deactivate = interrupt to CPU"); await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt dea= ctivation expected", C_SCOPE); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrup= t to CPU"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt rea= ctivation expected", C_SCOPE); elsif run("Check Reset") then log("- Activate all interrupts"); write(C_ADDR_ITR, x"FF", "ICR : Set all interrupts"); write(C_ADDR_IER, x"FF", "IER : Enable all interrupts"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to = CPU"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt act= ivation expected", C_SCOPE); pulse(arst, clk, 1, "Pulse reset"); await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt dea= ctivation", C_SCOPE); check(C_ADDR_IER, x"00", ERROR, "IER all inactive"); check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive"); check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive"); end if; end loop; --=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -- Ending the simulation -----------------------------------------------------------------------= --------------- wait for 1000 ns; -- to allow some time for completion report_alert_counters(FINAL); -- Report final counters and print conclu= sion for simulation (Success/Fail) test_runner_cleanup(runner); wait; -- to stop completely end process p_main; end func; On Saturday, June 20, 2015 at 1:50:45 PM UTC+2, olof.k...@gmail.com wrote: > I downloaded the BVUL to have a look. It looks very similar to what we ha= ve in VUnit. I noticed the example test bench bitvis_irqc/tb/irqc_tb.vhd co= uld benefit from the VUnit Python/VHDL automation. My interpretation is tha= t you use log messages with ID_LOG_HDR to visually/textually separate diffe= rent independent test cases. I count 8 of those. With VUnit you could have = those 8 as actual independent test cases run in different simulations (or o= ptionally all in the same simulation) with individual pass/fail in the test= report. An individual specific test can be easily run from command line us= ing wildcard (*) pattern. VUnit would also ensure that each test case got i= ts own dedicated output folder to gather all simulation artifacts such as t= he complete stderr/stdout, wlf and transcript as well as any other user def= ined outputs such as images other binary data files. =20 >=20 > On Saturday, June 20, 2015 at 12:21:59 PM UTC+2, Brian Drummond wrote: > > On Fri, 19 Jun 2015 07:20:39 -0700, espen.tallaksen wrote: > >=20 > > > Hi Olof, > > >=20 > > > I agree that BVUL only covers your item 2 above, but then again item = 2 > > > is where you can actually save by far the most hours in a complex FPG= A > > > project. Items 1 and 3 are also important, and will save quite a few > > > hours. > > >=20 > > > I think perhaps it could be great if we could cooperate on the > > > combination Vunit and BVUL, so that we could get the best out of two > > > worlds, but we could take that discussion off line ;-) > >=20 > > By all means take the details off-line but please summarize the outcome= =20 > > here! > >=20 > > Thanks to yourself, Olof and Lars for discussing - and indeed, creating= -=20 > > these useful tools! > >=20 > > -- Brian From newsfish@newsfish Thu Aug 1 00:33:40 2024 X-Received: by 10.140.234.150 with SMTP id f144mr26436305qhc.9.1434803280949; Sat, 20 Jun 2015 05:28:00 -0700 (PDT) X-Received: by 10.140.48.11 with SMTP id n11mr346798qga.35.1434803280887; Sat, 20 Jun 2015 05:28:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!q107no2286154qgd.0!news-out.google.com!k20ni2822qgd.0!nntp.google.com!q107no2286149qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jun 2015 05:28:00 -0700 (PDT) In-Reply-To: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5de9dc79-f386-4969-bb72-992724b3fa50@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Sat, 20 Jun 2015 12:28:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3811 P.S My previous post looks best when viewed with a monospace font. From newsfish@newsfish Thu Aug 1 00:33:40 2024 X-Received: by 10.68.195.166 with SMTP id if6mr26987082pbc.6.1434811693338; Sat, 20 Jun 2015 07:48:13 -0700 (PDT) X-Received: by 10.140.81.149 with SMTP id f21mr358718qgd.8.1434811693060; Sat, 20 Jun 2015 07:48:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6012414igd.0!news-out.google.com!k20ni2835qgd.0!nntp.google.com!q107no2309379qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jun 2015 07:48:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <651b8d33-937b-48e3-a463-9335450780f6@googlegroups.com> Subject: Re: hands on experience on SystemC From: Lars Asplund Injection-Date: Sat, 20 Jun 2015 14:48:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3812 Den fredag 19 juni 2015 kl. 12:11:56 UTC+2 skrev alb: Hi Al, > > Thanks for sharing. The reason for me asking is that the message=20 > > passing in VUnit wasn't developed to support TLM for hardware out of=20 > > the box. It was developed to enable high-level communication within=20 > > testbenches, not within the DUT.=20 >=20 > I'm not sure to which question or statement you're referring to.=20 >=20 What I'm saying is that message passing in VUnit wasn't developed to suppor= t design space exploration of the to be synthesized hardware. It was develo= ped to have message passing which takes no time and has no capacity limitat= ions which is very useful within testbenches (outside of the DUT). When we = did this I recognized that it can be used for your purposes as well if supp= ort for those delay and capacity limitations is added. We decided to leave = this for the future to see what users want and when I saw this thread I sta= rted to wonder if the future is here. Anyway, you have time to learn something new so you should. Good luck! /Lars From newsfish@newsfish Thu Aug 1 00:33:41 2024 X-Received: by 10.13.231.133 with SMTP id q127mr54082403ywe.31.1435160719972; Wed, 24 Jun 2015 08:45:19 -0700 (PDT) X-Received: by 10.140.33.76 with SMTP id i70mr297667qgi.14.1435160719864; Wed, 24 Jun 2015 08:45:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z60no3079191qgd.1!news-out.google.com!k20ni3166qgd.0!nntp.google.com!q107no3080944qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jun 2015 08:45:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.94.31.2; posting-account=jtCNBQoAAADZI8arfM1SMrp1bc394Q4R NNTP-Posting-Host: 192.94.31.2 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ef8a71a-87ee-4559-b7c7-5dcf5003e723@googlegroups.com> Subject: Hierarchical References and indexes From: dlp Injection-Date: Wed, 24 Jun 2015 15:45:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 13 Xref: news.eternal-september.org comp.lang.vhdl:3813 Hi, With external names, is there a way to use a generate index to select an instance? That is, gen: for i in 0 to 7 generate foo(i) <= << signal .tb.uut"i".MySig : std_logic >>; end generate; Where "i" should range from uut0 to uut7 ? Thanks dlp From newsfish@newsfish Thu Aug 1 00:33:41 2024 X-Received: by 10.52.72.161 with SMTP id e1mr53946884vdv.14.1435164120431; Wed, 24 Jun 2015 09:42:00 -0700 (PDT) X-Received: by 10.140.93.38 with SMTP id c35mr205394qge.38.1435164120371; Wed, 24 Jun 2015 09:42:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no3090954qgd.1!news-out.google.com!k20ni3172qgd.0!nntp.google.com!z60no3090949qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jun 2015 09:42:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Simplified Testbench Communication with Open Source Message Passing Mechanism From: Lars Asplund Injection-Date: Wed, 24 Jun 2015 16:42:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 7895 X-Received-Body-CRC: 947369722 Xref: news.eternal-september.org comp.lang.vhdl:3814 One of the previous posts (https://groups.google.com/forum/#!topic/comp.lan= g.vhdl/QYoZ_ufMP3g) went off topic to discuss the case for high-level model= ling in VHDL using message passing. This is a post to bring the discussion = on topic again by presenting the VUnit solution to message passing. Are the= re things you would like to see that is not covered by message passing in i= ts purest form? For example, using message passing to model communication i= n hardware which takes time and has capacity limitations. /Lars Summary =3D=3D=3D=3D=3D=3D=3D When your testbench grows to include several concurrent statements like pro= cesses and components surrounding the DUT it becomes important to coordinat= e the verification effort between these statements. This can be as simple a= s using synchronizing events implemented with boolean signals but when comm= unication involves significant information exchange and many modes like asy= nchronous, synchronous, broadcasting, and two-way interaction it becomes mu= ch more challenging. VUnit, the open source unit testing framework for VHDL= , includes a high-level message passing mechanism to handle this complexity (https://github.com/LarsAsplund/vunit/blob/master/vhdl/com/user_= guide.md) Concept =3D=3D=3D=3D=3D=3D=3D In real life we use different modes of communication all the time when maki= ng phone calls, sending emails, and posting status updates on Facebook. We = do this with ease because the services we use let us focus on the informati= on to exchange and with whom. We don't have to know where our counterparts = are located and we don't have to care about infrastructure details like put= ting messages into FIFOs, routing them to the correct destination and so on= . The VUnit message passing mechanism, a.k.a. com, takes this approach to h= igh-level testbench communication and let you communicate using intuitive s= ubprogram calls like send, receive, publish, and request. The next section provides a few examples on how com is used. The complete t= utorial for com can be found at https://github.com/LarsAsplund/vunit/blob/m= aster/vhdl/com/user_guide.md and a testbench example is found at https://gi= thub.com/LarsAsplund/vunit/tree/master/examples/com. Com was developed in t= he open by a number of community members. If you want to see the discussion= s that led to this solution have a look at this thread https://github.com/L= arsAsplund/vunit/issues/23 Examples =3D=3D=3D=3D=3D=3D=3D=3D Inspired by the actor model (https://en.wikipedia.org/?title=3DActor_model)= a statement like a process that wants to communicate creates an actor for = itself variable test_sequencer : actor_t :=3D create("test sequencer"); To communicate with another statement you must find its actor, e.g. variable driver : actor_t :=3D find("driver"); A message can now be sent over the net(work). Any communication problems ar= e reported in the returned send receipt send(net,test_sequencer,driver,"Hello!",receipt); Messages are received, in this case by the driver, with the blocking receiv= e procedure. The received payload can then be processed. Here I'm just prin= ting it. receive(net,driver,message); report message.payload.all; Note that the locations of the actors are hidden, they can be in different = processes in the same file, in different files, or even in the same process= . You don't have to change the communication if you refactor the code such = that actors are moved. No details about the transport of messages are expos= ed other than that there is some sort of net(work) involved. Message passin= g is, in this case, asynchronous, you can send thousands of messages before= the receive procedure is called. The send call takes no time, only delta c= ycles. In this case I'm sending a string message and string is the only datatype c= om natively handles. Other datatypes have to be encoded/decoded to/from str= ing. For example, you can send an integer as encode(my_integer) and receive= it with my_integer :=3D decode(message.payload.all); Encode and decode functions for standard VHDL and IEEE datatypes are provid= ed by com, but more importantly, com will generate these functions for your= custom datatypes as well. For example, if you have a write_mem transaction= defined by a record like this type addr_data_msg_t is record msg_type : addr_data_msg_type_t; addr : integer; data : std_logic_vector(7 downto 0); end record addr_data_msg_t; where msg_type is a custom enumeration with values representing the bus tra= nsactions for which this record is used, e.g. write_mem, then com will prov= ide you with an encode function so you can do send(net,test_sequencer,driver,encode((write_mem, 17, X"A5")),receipt); but there is also a named encode function which makes the code more readabl= e send(net,test_sequencer,driver,write_mem(17, X"A5"),receipt); which you can wrap in a local procedure to get something even more readable write_mem(17, X"A5"); On the receiving side you will have support for parsing messages that arriv= e. They can have different msg_type and can be based on different records receive(net, driver, message); case get_msg_type(message.payload.all) is when write_mem =3D> -- Process write mem transaction when read_mem =3D> -- Process read mem transaction ... So you don't have to do anything other than defining your message types to = get the necessary support functions. If you want to broadcast a message to anyone interested you do publish inst= ead of send and remove the receiver parameter publish(net,test_sequencer,"Hello!",status); Actors interested in these publications have to subscribe to the publishing= actor and then receive messages in the normal way using the receive proced= ure. subscribe(driver,find("test sequencer"),status); You don't have to change anything to the publisher or existing subscribers = if a new actor becomes interested in what's being published and subscribes. Two-way interaction can be handled in a number or ways but the simplest way= to send a request and wait for a reply is request(net,test_sequencer,driver,request_msg,reply_msg); This will return the reply matching the request even if other messages arri= ve while waiting for the reply or requests are handled out of order at the = receiving side. A request can be the basis for a synchronous transaction li= ke read_mem, i.e. the call will return when the data is available. These were a few examples of what you can do. For more examples and details= jump to https://github.com/LarsAsplund/vunit/blob/master/vhdl/com/user_guide.md From newsfish@newsfish Thu Aug 1 00:33:41 2024 X-Received: by 10.50.13.97 with SMTP id g1mr14591962igc.13.1435570004492; Mon, 29 Jun 2015 02:26:44 -0700 (PDT) X-Received: by 10.140.102.66 with SMTP id v60mr153837qge.19.1435570004463; Mon, 29 Jun 2015 02:26:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no2159390igd.0!news-out.google.com!4ni21980qgh.1!nntp.google.com!j5no1085873qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jun 2015 02:26:44 -0700 (PDT) In-Reply-To: <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Mon, 29 Jun 2015 09:26:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3815 Hi Olof, My explanation to why BVUL is not just another flavour was unfortunately fa= r too brief. Let me elaborate a bit without doing any direct comparisons. - BVUL has ID-based verbosity control. Most other systems are priority base= d. Prioritising log-messages may seem like a good idea, but only works for = very basic testbenches. Simple example: What has the higher priority; a mes= sage saying you have received a packet header, or a message saying you have= received a complete packet? Obviously your priorities change from when yo= u debug your receiver, detecting header, address, correct CRC etc to when y= our receiver is properly debugged and you anly want to know that you have r= eceived a correct packet - or even 100 packets.... An ID-based verbosity s= ystem where you enable say ID_PACKET_HDR, ID_PACKET_COMPLETE and ID_PACKET_= DATA separately allows full flexibility and changing your priorities as you= develop your testbench. An ID-based verbosity control system is far easier= to use, as you control things based on functionality, which is just what y= ou want. It may even be used as a priority based system if you really want = to, but not he other way around. - BVUL has positive acknowledge on all checks, so that you may get a messag= e saying that check this and that (detailed info) has been executed and was= OK, and not just an alert if it fails (plus potential counting). The posit= ive acknowledge may of course be turned off. Very few systems have this cap= ability. - BVUL also have some other very useful features that most other libraries = do not have, but I think perhaps the most important aspect of BVUL is the e= xtremely low user threshold. We advice browsing through our provided PPT to= get an overview, but once you have done that - all feedback so far has bee= n that it is dead simple to use. In my experience as a consultant for 20 years now the testbench structure i= s the worst source of time wasting. If we take an average 5000 man hour FPGA development project I would say th= at on average the verification part (say 2500h) could have been reduced by = at least 1000 hours if they had structured their testbenches properly, and = provided good progress reports (logging) and alert handling. The IRQC example is more like a 20 hour project. I have included two bugs i= n the design and presented this at universities and in our course 'FPGA Dev= elopment Best Practices' and shown them the testbench log/alert transcript = only. They have always found the source of the bugs just by looking at the = transcript for less than 30 seconds - with no need for the wave view. The W= ilson report shows that nearly half of the verification time is spent on de= bugging. Then a proper progress report is key to efficiency. For larger designs of course even more so. I have definitely seen that proper regression testing mechanisms is also im= portant, which is why I say that your issues 1 and 3 are in fact also impor= tant, but my experience is that in this 5000 man hour project this would gi= ve an average improvement of say 100 hours, which is also very important. O= f course there are projects where this number is far higher, but similarly = there are projects wasting another 2000-3000 hours due to bad testbench str= ucture. Immediate stop on an error is my preferred way as well for simpler debuggin= g, but having a good progress report prior to the error helps a lot. (Sometimes however you run your test overnight, and then you may want to de= tect more bugs - either by running more separate test cases -e.g. using VUn= it, or by getting further into a test case which is really time consuming b= ecause it needs to be (some tests cannot be cut into short pieces). Again - I really do like the unit testing features of VUnit, and we do need= a structured approach to regression testing. This is why I think it would = have been great to cooperate to make all parts better. (I'll come back to t= hat in a separate response "further down")=20 From newsfish@newsfish Thu Aug 1 00:33:41 2024 X-Received: by 10.42.249.8 with SMTP id mi8mr10214127icb.15.1435570740465; Mon, 29 Jun 2015 02:39:00 -0700 (PDT) X-Received: by 10.140.37.129 with SMTP id r1mr151783qgr.18.1435570740433; Mon, 29 Jun 2015 02:39:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no2168745igd.0!news-out.google.com!4ni22040qgh.1!nntp.google.com!z60no1011733qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jun 2015 02:39:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2bbe9e22-3775-4261-b566-29302210b4ed@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Mon, 29 Jun 2015 09:39:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3816 Hi Brian, You wanted a summary of our off-line discussion on potential cooperation between VUnit and BVUL. I think the very brief version is that we agree to look into collaboration opportunities when they appear, but just now we are not quite there. Olof did however demonstrate the Unit testing capabilities of VUnit, and the fact that BVUL may be used seamlessly with VUnit, without making changes to any of them. -Espen From newsfish@newsfish Thu Aug 1 00:33:42 2024 X-Received: by 10.70.16.101 with SMTP id f5mr20923727pdd.14.1435599472116; Mon, 29 Jun 2015 10:37:52 -0700 (PDT) X-Received: by 10.140.98.138 with SMTP id o10mr71557qge.33.1435599472058; Mon, 29 Jun 2015 10:37:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!j8no1836055igd.0!news-out.google.com!4ni24745qgh.1!nntp.google.com!j5no1245049qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jun 2015 10:37:51 -0700 (PDT) In-Reply-To: <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Mon, 29 Jun 2015 17:37:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 72 Xref: news.eternal-september.org comp.lang.vhdl:3817 Espen,=20 I can agree that lack of proper testbench structure is a big cause of ineff= iciency in a typical FPGA project. I wouldn't say that this is mostly due t= o missing library features but rather that due to lack of software/verifica= tion skills. It quite possible to write a good test bench without any suppo= rting library and also possible to write a poor test bench using a good sup= porting library. People will not learn to write good test benches quickly b= y using either BVUL or VUnit but rather primary by working in teams with pe= ople that possess the skills and secondary by taking verification courses. = Also in my opinion writing good test benches is more of a software skill. T= he people I know that are good at writing test benches also have software e= xperience and the people I know that are worse at it do not have much softw= are experience are are more purely hardware oriented. The libraries provide= d by BVUL/VUnit/OSVVM will provide the good test bench developer with bette= r tools than they would have taken the time to create for themselves and th= at is a still a big benefit. How great that it is possible to use them all = together further increasing the toolbox of the test bench writer.=20 I also agree that debugging is a big time waster. The solution is primarily= to avoid the need for debugging rather than making it easier. First let me= identify two types of debugging:=20 I) The first kind is when a bug is reported in the field and it must be re-= produced. The work performed while reproducing the bug can be called debugg= ing.=20 II) The second kind is when an existing module is extended or modified and = it causes a regression in an existing test. The process of figuring out why= the regression test failed can be called debugging.=20 The road to reducing the need for debugging is the use of a better verifica= tion methodology. By having many small tests that test a small piece of fun= ctionality the debugging effort in II) is greatly reduced. A large module c= an be significantly harder to modify or re-use when it only has a large end= -to-end test compared to when it has many smaller tests or even testw for i= t's sub-modules. Also when having small and quick tests the designer can re= -run the test more often even for smaller modifications, the easiest bug to= find is in the line you just wrote 10 seconds ago. The end-to-end test is = still necessary to ensure that the parts work as a whole but it should only= catch integration issues and not faults in the individual parts.=20 Lots of research and testimonies from software the development world, from = which there are many parallels to FPGA-development and a lot to learn, has = shown that using the method to write many small test of small parts increas= es the quality of the code base. It forces the design to be more modular an= d less tightly coupled with more well defined interfaces. This reduces the = likely-hood to have bugs which cause I) and also reduces the cost of modifi= cation/re-use. I have seen many 3000-line state machines in large modules w= ith only a big end-to-end test which should really have been split up into = multiple smaller parts. Such modules sooner or later just have to be re-wri= tten because they cannot accommodate new functionality. In many complex pro= jects or projects using agile methods the development process is nothing mo= re than a steady stream of modifications making the reduction of their cost= very beneficial. Many companies can also save money from re-using modules = between product families or new products with more or less modifications. I= n my opinion it is good regression testing that facilitates re-use rather t= han any IP-packaging format or similar stuff. So how does the methodology described above relate to VUnit? Well it was cr= eated to facilitate the methodology by significantly reducing the cost of h= aving many tests per test bench and many test benches both from the regress= ion testing use case as well as from a daily coding edit/compile/run use ca= se were a designer wants to quickly re-run multiple tests/test benches for = each small modification. It is by using this methodology, enabled by VUnit,= that a typical project can save a lot of time and dramatically increase qu= ality and re-usability. Just having the VHDL-part of VUnit or BVUL alone co= uld not nearly as well enable the above methodology but it is an important = piece of the puzzle non the less. I finally conclude that any BVUL user could benefit from using VUnit togeth= er with BVUL enabling the above methodology without using the parts of VUni= t that are redundant with BVUL as I have shown in my previous posts. From newsfish@newsfish Thu Aug 1 00:33:42 2024 X-Received: by 10.129.81.70 with SMTP id f67mr27813211ywb.7.1435654220584; Tue, 30 Jun 2015 01:50:20 -0700 (PDT) X-Received: by 10.140.99.44 with SMTP id p41mr50737qge.3.1435654220567; Tue, 30 Jun 2015 01:50:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j5no1467884qga.1!news-out.google.com!w15ni12593qge.0!nntp.google.com!z60no1390312qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 01:50:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Tue, 30 Jun 2015 08:50:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3818 Hi Olof, I final comment from my side. I agree with many of your points, but I think writing a good testbench depe= nds far more on your experience, structure, awareness of ROI (return on inv= estments) of such structure and a good methodology. The quality of this tes= tbench is *the* main key to efficiency and quality. And of course BVUL (or other similar libraires) is just one piece in this p= uzzle. For simple testbenches it is a major piece, but for complex testbenc= hes it is a minor piece, but still a corner stone for other pieces. For com= plex testbenches their structure is by far the most important piece. To ver= ify corner cases you need to be able to control different interfaces simult= aneously in a controlled manner, and for this Verfication components is the= best approach. We will hopefully present a solution for that at FPGAworld = in September with 'UVVM', that handles this in a very structured manner. Ot= her important pieces in this puzzle are constraint random, coverage, scoreb= oards, etc. I still agree that unit testing is also very important, but unfortunately f= or some applications some simulations are time consuming because you just h= ave to run for a long time before your DUT reaches a certain state, and you= have to verify that e.g. lots of different submodules work together as exp= ected. (By comparison verifying for instance the *implementation* of filter= s and sub-filters is dead simple.) Most huge state machines are bad design structure, but I guess that is a di= fferent discussion. (We spend nearly a day on that alone in our course 'FPG= A Development Best Practices'. So I agree this is definitely a problem form= many FPGA projects.)=20 Handling (or not handling) the complex verification scenarios is where lots= of projects are wasting several hundred man hours and sometimes far more t= han thousand man hours - either because they do labtest/patch-iterations fo= r ever or because they don't structure their testbenches sufficiently. And = for this they need methodology, awareness, structure at all levels and debu= g-support. BVUL is just a library that supports this approach very well, bu= t only for the basic logging, alert handling, proper verbosity control, che= cks and awaits. OSVVM is a different library that is excellent for contrain= ed random and coverage. Another library is UVVM (to be released in Septembe= r) that provides a very structured verification component environment and T= LM for a really understandable handling of simultaneous stimuli and checkin= g of multiple interfaces. In fact the combination of these three libraries = provides a unified testbench approach. And they could all work together with VUnit for unit testing :-) From newsfish@newsfish Thu Aug 1 00:33:42 2024 X-Received: by 10.50.128.231 with SMTP id nr7mr23346960igb.11.1435666999793; Tue, 30 Jun 2015 05:23:19 -0700 (PDT) X-Received: by 10.140.91.19 with SMTP id y19mr104273qgd.6.1435666999764; Tue, 30 Jun 2015 05:23:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no2336130igd.0!news-out.google.com!w15ni13172qge.0!nntp.google.com!j5no1530960qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 05:23:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Tue, 30 Jun 2015 12:23:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3819 Hello, Interesting discussion! As Espen mentioned we will take small steps where we find common grounds an= d in the first iteration VUnit will provide better support for coexistence = between the two libraries in addition to the possibilities already existing= . We will provide means to handle the name collision that exists for the lo= g procedures and we will also provide a thoroughly documented example on ho= w coexistence is achieved. I'll get back when this is on Github. Next, I would like to comment on the last few posts. Olof had already said = a lot about the productivity gains with unit testing but this is very impor= tant point so I will add a bit more (and probably repeat a bit) First of all, the productivity gain of unit testing is NOT a result of the = time saved running all your self-testing testbenches automatically rather t= hen opening the GUI, load the testbench, and then hit run for each and ever= y one. It comes because it enables very short code/test cycles so you can s= tart test early and do it frequently. When I say frequently I mean at the p= ace you add bugs to your code which is many times a day (at least I do). Th= is frequency won't happen unless you have a tool chain supporting that. Som= e benefits are: - The obvious one is that the sooner you find the bug the less damage for y= ou and your team. Ideally you should find the bug when the code is still fr= esh in the developer's mind. - When you have a fully automated test environment you also become very res= ponsive to the changes in requirements and design that happens all the time= in most projects. If you can fix these change requests and quickly make su= re that everything still works then you have a competitive edge. Take the V= Unit project as an example. Since it was released about half a year ago 8 c= ontributors have done about 250 commits which added about 30000 lines of so= mething (code and documentation) and removed about 12000 lines. An enhanced= version of the tool is typically made public one or several times a week (= and it's not about continuous bug fixing). Considering that we support seve= ral simulators, VHDL standards, Python versions, and operating systems this= would not be possible to do unless we had test suites verifying the qualit= y of each and every release. Ok, we don't have the many hour tests, synthes= is and place and route but even if you have the release cycle can be very q= uick if you automate - When test becomes such an integral part of what the developer do it also = starts to affect the quality of the code in a positive way. Code that is ha= rd to test is a bad code smell, i.e. an indication of bad quality. This mea= ns that the drive to do low-level testing also enhances the quality at that= level. You may discover these bad smells when testing later at a higher le= vel as well but then it's much harder to correct. Since test drives the des= ign many unit test practioners adopt test-driven design (TDD) where the bas= ic concept is to write the test first and then implement the design that ma= kes that test pass. What I'm saying is that unit testing enables a way of working affecting man= y parts of the project not just verification and that's why it has such an = impact. The effect on project success rates has been showed in research Some words about what we support and what we don't. VUnit also use "ID-based verbosity control" but we don't call it ID but sou= rce. For example, here I'm doing a debug log with no special source: debug("This is a debug message); But I can add a source (ID) if I want: debug("This is a debug message", "Some source name"); If I want to stop messages from "Some source name" to appear on stdout I ca= n add stop_source("Some source name", display_handler, filter); What I done is to add a stop filter to the display handler. I can individua= lly decide what filters to have for the log file (if any) by using the file= _handler instead. The filter returned is there so that it can be removed. I= can add many filters to a handler, have pass filters, filter on log level,= e.g. log all debug messages to file but don't show them on the display. I = can also filter hierarchies. https://github.com/LarsAsplund/vunit/blob/mast= er/examples/logging/logging_example.vhd will show the different capabilitie= s VUnit doesn't support positive acknowledge on the checker/assert/alert leve= l. It hasn't really been asked for but I opened this issue (https://github.= com/LarsAsplund/vunit/issues/53) so that you can support its addition. It's= an easy fix. I think the reason for not normally seeing this among unit te= st frameworks is that it yields a lot of text. For example, the VUnit VHDL = part is verified with 22 test suites containing 280 test cases containing 1= 600 checks/asserts. We keep them public so that you can make your own modif= ications and possibly contribute code and be confident you didn't destroy a= nything (see https://github.com/LarsAsplund/vunit/blob/master/developing.md= ). When developing a piece of code I mostly run the test suite for that cod= e. Such a test suites contains, on average, 13 test cases and 75 checks. A = summary of 13 test cases is a good overview which you might read. 75 "passe= d" is a bit much a may not even fit in your window.=20 When we describe VUnit we usually go directly for the end goal with full au= tomation since that provides the greatest value. However, you can do this i= s smaller steps to set a threshold that fits you. I've seen different appro= aches to start using VUnit depending on project background but here is one = way starting with a pure VHDL testbench which makes it similar to BVUL. For= simplicity I've excluded any real DUT and only test basic VHDL behaviour. library vunit_lib; context vunit_lib.vunit_context; -- Get= all VUnit-related functionality entity tb_comp_lang_vhdl_example is generic ( runner_cfg : runner_cfg_t :=3D runner_cfg_default); -- U= se configuration from script or defaults end entity tb_comp_lang_vhdl_example; architecture test_fixture of tb_comp_lang_vhdl_example is begin -- Normally I would have a DUT, clock generators and so on here =20 test_runner: process is variable filter : log_filter_t; begin test_runner_setup(runner, runner_cfg); -- Set= up with provided configuration logger_init(runner_trace_logger, display_format =3D> raw); -- E= nable runner trace log on display with "raw" format. Only active on file by= default pass_level(runner_trace_logger, info, display_handler, filter); -- Exl= ude details and only display basic info, in this case currently active test= case while test_suite loop -- Loo= p over the set of test cases if run("Test that addition works") then -- Eve= ry if statement branch like this defines a named test case check(1 + 1 =3D 2, "VHDL can't do addition!"); -- U= se various checks for verification elsif run("Test that subtraction works") then check_equal(5 - 3, 2); end if; end loop; info(LF & "=3D=3D=3D Summary =3D=3D=3D"); info(to_string(get_checker_stat)); -- Mak= e an info message of basic statistics test_runner_cleanup(runner); -- Wra= p-up end process test_runner; end; This will result i the following output in Modelsim # Test case: Test that addition works # Test case: Test that subtraction works #=20 # =3D=3D=3D Summary =3D=3D=3D # Checks: 2 # Passed: 2 # Failed: 0 Making this fully automated with Python requires another baby step. Just ad= d this run.py script from vunit import VUnit from os.path import join, dirname ui =3D VUnit.from_argv() lib =3D ui.add_library("lib") lib.add_source_files(join(dirname(__file__), "*.vhd")) ui.main() The three last lines are the most interesting. First create a VHDL library = called lib. Then add all the .vhd files found in the same directory as this= script file (in this case we only have one file). Then call main to run. I= t will find all VHDL files, figure out their dependencies so that they can = be compiled in the correct order and only compile what's needed based on ch= anges. Then it will find all testbenches (only one) and run their test case= s. Just type python run.py and you'll get the following result Starting lib.tb_comp_lang_vhdl_example.Test that addition works pass (P=3D1 S=3D0 F=3D0 T=3D2) lib.tb_comp_lang_vhdl_example.Test that addi= tion works (1 .9 seconds) Starting lib.tb_comp_lang_vhdl_example.Test that subtraction works pass (P=3D2 S=3D0 F=3D0 T=3D2) lib.tb_comp_lang_vhdl_example.Test that subt= raction works (0.5 seconds) =3D=3D=3D=3D Summary =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D pass lib.tb_comp_lang_vhdl_example.Test that addition works (1.9 seconds= ) pass lib.tb_comp_lang_vhdl_example.Test that subtraction works (0.5 seconds= ) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D pass 2 of 2 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D Total time was 2.4 seconds Elapsed time was 2.4 seconds =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D All passed! So it's really not very complicated. From run.py you also get various optio= ns (do python run.py -h to see them all) like running the tests on many par= allel cores and open and run a specific test case in the GUI. /Lars From newsfish@newsfish Thu Aug 1 00:33:42 2024 X-Received: by 10.50.66.146 with SMTP id f18mr24409566igt.11.1435677909005; Tue, 30 Jun 2015 08:25:09 -0700 (PDT) X-Received: by 10.50.66.141 with SMTP id f13mr293529igt.4.1435677908978; Tue, 30 Jun 2015 08:25:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no2455781igd.0!news-out.google.com!a16ni9310ign.0!nntp.google.com!j8no3384066igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 08:25:08 -0700 (PDT) In-Reply-To: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: KJ Injection-Date: Tue, 30 Jun 2015 15:25:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3820 On Friday, June 12, 2015 at 9:39:45 AM UTC-4, espen.t...@bitvis.no wrote: > on average 50% of FPGA designers' time is spent on verification, and=20 > almost half of that verification time is spent on debugging. This means: >=20 > 1. Good reports for unexpected design behaviour is critical. > 2. Good progress reporting is also critical. > 3. Good basic testbench features are required >=20 > Thus we need a library with good functionality for mismatch reporting,=20 > progress reporting and for checks etc. that are needed for every single= =20 > testbench; like=20 Since one can just as easily do all of the above with straight VHDL and be = just as concise or even more so, it does not really follow that what is nee= ded is a 'library with good...'. =20 > - checking value against expected > - waiting for something to happen - with a timeout > - checking stability of a signal > - waiting for a signal to be stable for a given time (with timeout) >=20 > The only free library library (to my knowledge) to provide all this=20 > functionality is Bitvis Utility Library.=20 OK, but the VHDL language provides this as well. >=20 > If this sounds interesting, you should read the below intro. > You can download the library and PPT from=20 > http://bitvis.no/resources/utility-library-download/ without any=20 > registration. Thanks for providing, that in itself is a useful service. My read is that the library is way to low level to be an effective archive = to capture the original intent of the testbench which means that a testbenc= h written using Bitvis will be just as opaque as the testbenches you compla= in about now. As an example of checking register function (from slide 31 o= f the PowerPoint): write(C_ADDR_ITR, x"AA", "ITR : Set interrupts"); check(C_ADDR_IRR, x"AA", ERROR, "IRR"); Some simple observations: - The hard coded constants x"AA" are not independent. Changing one require= s you to change the second one. But this is not controlled by the code in = any way. - Similarly, as one works through the rest of the script, there are other h= idden dependencies that occur. - The expected response of the DUT is implicit (the reading back of data fr= om IRR and expecting it to be the same as what was written into ITR). At f= irst glance, one almost might thought it was an error to write to one regis= ter and expect some other register to read back that same data. The code y= ou have is actually just an undetectable typo away from being a 'write then= read back' test of just ITR (or IRR). - Although this particular test is simply testing the bits somewhat indepen= dently, those bits typically have definitions from a record but here you're= totally ignoring those definitions and turning on and off bits in a byte w= ith no regard for what that bit defines. While OK for a simple read/write = testing as you're showing, there is nothing in Bitvis that would let it sca= le it up to something more general which is what you would want once you ge= t beyond the simple read/write tests. Consider now this could be written i= n vanilla VHDL: -- Let's check operation of the 'This' and 'That' interrupt bits Fpga_Reg.ITR :=3D ( This_Interrupt =3D> "1", That_Interrupt =3D> "1", Reserved =3D> (others =3D> '0') ); reg_write(Fpga_Reg.ITR); Fpga_Reg.IRR :=3D Fpga_Reg.ITR; -- This is the DUT response that is expecte= d=20 Fpga_Reg_Readback.IRR :=3D reg_read; assert (Fpga_Reg.IRR =3D Fpga_Reg_Readback.IRR) report "IRR register did not read back correctly" & LF & "Expected: Fpga_Reg.IRR=3D" & image(Fpga_Reg.IER) & LF & "Actual: Fpga_Reg_Readback.IRR=3D" & image(Fpga_Reg_Readback.IRR) severity ERROR; While the code is wordier, it is also self-documenting. Using the Bitvis li= brary, one would have to dig into a whole lot more design specific detail a= nd documentation (that is outside the scope of the testbench itself) just t= o understand what the testbench is trying to accomplish. With what I've sh= own, that should not be the case. As a bonus, you don't have any of the sh= ortcomings that I pointed out earlier either. Of course the main issue is that Bitvis, since it is attempting to be gener= ic, cannot be design specific, but in order to get good code clarity you do= want the executable code to be design specific. You do want to have execu= table that looks like 'Control_Reg.Fire_The_Gun :=3D "1"' to then have a re= sponse of 'Status_Reg.Off_To_The_Races :=3D "1"', not hard coded hex consta= nts...that then have to change as the 'Off_To_The_Races' bit gets moved fro= m bit 5 to bit 6. Testbench modelling at the top design level should start by modeling the bo= ard that the design will be put into. This then naturally leads to modelin= g the system that the board goes into as well. Following that approach pro= duces a library of parts that can then be reused in other testbenches becau= se they are modeling actual parts, not just something cobbled together to c= ontrol/check interface ABC of design XYZ. It will also produce XYZ design = specific stuff as well. I have yet to have a time when 'verbosity control' was something I would wa= nt. The testbench will stop on an error and I have the complete log file t= hat I need to debug the problem. What you don't mention at all that is use= ful is simply to produce multiple log files. For example, logging transact= ion that occur on a particular interface to a CSV file so that it can be pu= lled up in Excel. Using those interface log files along with the main tran= script log file is a powerful debug aid. I don't want to seem to be too harsh, it's not that I think the library is = 'bad'. Much of what you have is useful info, but the library while it may = improve how some people today write a testbench eventually it will stunt te= stbench development because it does not go far enough to produce maintainab= le code. While I accept that you have found users that find it useful, for= me it would be a big step backwards since it would produce less maintainab= le code and probably take just as long, or longer to develop in the first p= lace. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:43 2024 X-Received: by 10.140.146.133 with SMTP id 127mr29467116qhs.8.1435691352256; Tue, 30 Jun 2015 12:09:12 -0700 (PDT) X-Received: by 10.140.102.66 with SMTP id v60mr276239qge.19.1435691352241; Tue, 30 Jun 2015 12:09:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t90no71380qga.0!news-out.google.com!w15ni14370qge.0!nntp.google.com!t90no71376qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 12:09:12 -0700 (PDT) In-Reply-To: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Tue, 30 Jun 2015 19:09:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 76 X-Original-Bytes: 6330 Xref: news.eternal-september.org comp.lang.vhdl:3821 Kevin, I agree with you that using low level checks in test benches makes them wor= se and hard to maintain. A good test bench will contain a lot of supporting= code to enable the actual test to be as high level as possible and read al= most as a specification.=20 This is why I previously argued that I do not think the check/log library i= s the most important part missing to experienced test bench writers. The de= signer still needs to write a lot of project specific supporting code to ra= ise the abstraction level of the test bench (and design). Many designers wo= uld still write unmaintainable test benches using BVUL/VUnit/OSVVM without = the proper experience. On the other hand the unique features of VUnit such as the Python test runn= ing and compilation automation provides a feature rich and rock solid imple= mentation of something that many VHDL teams re-invent all the time in the f= orm of a pile of scripts of varying quality. Using VUnit the design team ca= n focus entirely on writing their high level test benches while the entire = test running and compilation is managed by VUnit.=20 I can testify that in my latest project we used VUnit to manage well over 2= 00 test cases with test benches automatically configured to run for all gol= den data in a folder and test configured to run with all interesting combin= ations of generics. Many test benches contained multiple tests that were ru= n in individual simulations but that benefited from a shared test bench inf= rastructure. The test cases could be run on Jenkins using multiple machines= and processor cores. The test cases could be opened in the simulator GUI w= ith everything set up by just issuing a command. Just the necessary files w= ere recompiled when re-running. All it took was writing a VUnit run.py file= of about 100 lines where most of the code was related project specifics su= ch as enumerating the golden reference data and creating generic combinatio= ns to configure the multiple test runs of the same test bench/test case.=20 VUnit provides the features that all serious verification efforts need righ= t away without modification and the potential for re-use is the greatest. I= gives every team access to a turn key solution worth several man-months of= work. I should also say that the low level functions found in the VHDL par= t of VUnit as well as BVUL/OSVVM are still useful and saves redoing some re= dundant work but they would not take that many days for the experienced VHD= L designer to re-implement the essential parts of them compared to implemen= ting something comparable to the sophisticated automation features of VUnit= which would not be possible within the budget of a single project. I also should say there are a lot of advanced features of BVUL and especial= ly OSVVM that can be really useful in some situations though that would wou= ld take the average designer many weeks to implement. Although a lot of cod= e has to be design specific due to the static nature of VHDL it is great th= e people have taken the time to make the obviously general parts available = as open source such that they do not need to be re-invented. In general I t= hink the FPGA/VHDL community is too shy of sharing their code and experienc= es compared to the software community. There is also a lack of standardizat= ion in verification tools and libraries compared to the software community = where specific languages have de-facto standard testing tools that everyone= uses. =20 The top two re-usable VHDL library features I tend to use are the check_equ= al procedures of VUnit, the dynamic array type of VUnit, as well as the ran= dom number generation from OSVVM. It does not mean that I use the check_equ= al procedures directly often but rather as part of higher level design spec= ific checking procedures that I create. A higher level checking procedure s= till must sometime contain a primitive check_equal of std_logic_vector, sig= ned, unsigned or integer etc. It is nice not to have to create a "Got XXXX = expected XXXX" message in manual assert statements all the time. Just becau= se there is a primitive method does not mean that you are encouraged to use= it directly. I suspect that the BVUL authors realize this but when showing= examples one does not want to obfuscate the usage to much by showing a sim= ple case. Our VUnit examples are also simplistic for the same reasons.=20 Due to the static nature of VHDL a library can not provide much general fun= ctionality and one must often write redundant code even with 2008 generic p= ackages. Since VUnit is not just a VHDL library but also Python framework w= hich parses the code we can do better in removing the need for redundant co= de by using code generation were packages are scanned for records for which= automatic to_string and check_equal can be generated. We have some such co= de-generation/pre-processing features already and plan to add more as use c= ases are identified. From newsfish@newsfish Thu Aug 1 00:33:43 2024 X-Received: by 10.42.73.70 with SMTP id r6mr31922289icj.30.1435695734376; Tue, 30 Jun 2015 13:22:14 -0700 (PDT) X-Received: by 10.140.85.11 with SMTP id m11mr135170qgd.29.1435695734347; Tue, 30 Jun 2015 13:22:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ff1no165378igc.0!news-out.google.com!w15ni14519qge.0!nntp.google.com!t90no95407qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 13:22:14 -0700 (PDT) In-Reply-To: <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Tue, 30 Jun 2015 20:22:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3822 Hi Kevin, Although I agree that a lot can be done with plain VHDL I still think there= are use cases for both verbosity control and support procedures replacing = assert statements. One place where I think verbosity control is useful is when you have a trac= e log like the one I showed in the previous comment (runner_trace_logger). = I don't want to filter what goes to file because I don't know what will be = interesting before I have the problems that caused me to open the file. The= file may become very large but as you suggest the CSV format (we call it v= erbose_csv) enable you to use the power of your spreadsheet tool to reduce = the file to the interesting parts. During long simulations I may also want = to get some progress from the trace log on stdout but there's no point if I= can't reduce that output to a message pace which I can read. For that I us= e verbosity control on the log level. When it comes to assert statements like the one you mention I think they ca= n be reduced to (here I'm assuming that IRR and ITR are std_logic).=20 check_equal(Fpga_Reg.IRR, Fpga_Reg_Readback.IRR, "IRR register did not read= back correctly"); while still being self-documenting. Given that a check for equality is one = of the most common ones this will save you a lot of redundant typing. In ca= se of an error you will get the following output (level format). ERROR: Equality check failed! Got 1. Expected 0. IRR register did not read = back correctly. Another good thing about standard check and log procedures, at least for us= writing tools, is that they are easier to parse such that you can add code= -related feature not available in VHDL itself. For example, if you enable t= he location preprocessor in your VUnit run script (ui.enable_location_prepr= ocessing()) and the have a log like this info("Some log message"); the output will be like this (verbose format) 0 ps: INFO in (tb_demo.vhd:27): Some log message This is useful when finding things and filtering your CSV file in Excel. A = drawback is that it is the preprocessed file you will see in the simulator = and you my be tempted to edit that one and not the original file. Another issue with convenience procedures like check_equal is that we suppo= rt a commonly used but limited set of data types so if you want to make an = equality check between other types you're back to the plain assert. But to = do the assert in your example you need to define "=3D" and image() for that= type. If you define a to_string() function instead of image() and enable t= he check preprocessing (ui.enable_check_preprocessing()) you can do like th= is check_relation(Fpga_Reg =3D Fpga_Reg_Readback, "Registers did not read back= correctly"); and a failed test will output this ERROR: Relation Fpga_Reg =3D Fpga_Reg_Readback failed! Left is ('1', '1'). = Right is ('1', '0'). Registers did not read back correctly check_relation can be used with any relational operator and type as long as= the operator and to_string() functions are defined. There are some drawbac= ks, primarily if an operand is a function with side effects. This function = is called twice, one time when checking the relation and one time when calc= ulating the error response string. This is not obvious when looking at the = procedure call before it has been preprocessed. For more details see https:= //github.com/LarsAsplund/vunit/blob/master/examples/vhdl/check/check_exampl= e.vhd /Lars From newsfish@newsfish Thu Aug 1 00:33:43 2024 X-Received: by 10.182.48.232 with SMTP id p8mr32351192obn.43.1435721486134; Tue, 30 Jun 2015 20:31:26 -0700 (PDT) X-Received: by 10.140.19.76 with SMTP id 70mr297805qgg.21.1435721486026; Tue, 30 Jun 2015 20:31:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ff1no202523igc.0!news-out.google.com!4ni33175qgh.1!nntp.google.com!t90no144344qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 20:31:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:7113:740f:81a6:3226; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:7113:740f:81a6:3226 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0cad22af-1ab1-45c9-a3a6-1801303777ad@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: KJ Injection-Date: Wed, 01 Jul 2015 03:31:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3823 On Tuesday, June 30, 2015 at 4:22:16 PM UTC-4, Lars Asplund wrote: > Hi Kevin, >=20 > One place where I think verbosity control is useful is when you have a tr= ace=20 > log like the one I showed in the previous comment (runner_trace_logger). = I=20 > don't want to filter what goes to file because I don't know what will be= =20 > interesting before I have the problems that caused me to open the file. Exactly. No filtering. At the point where the sim stops at an assertion, = I have everything I need so there is no need to filter anything. I also do= n't necessarily need to look at everything in the file since I'm debugging = a specific problem. I would look at the transcript window or file for basi= c information, I would look at auxiliary files if necessary but primarily I= will be looking at the signals and variables at the point where the sim st= opped in order to determine why the assertion condition failed. > During long simulations I may also want to get some progress from the tra= ce=20 > log on stdout but there's no point if I can't reduce that output to a mes= sage=20 > pace which I can read. For that I use verbosity control on the log level. For that I simply grab the scroll bar which effectively pauses the window. = Or, if I have the transcript set to go to an output file rather than the G= UI, I simply open the file in a text editor while the sim keeps on running. >=20 > When it comes to assert statements like the one you mention I think they = can=20 > be reduced to (here I'm assuming that IRR and ITR are std_logic).=20 >=20 > check_equal(Fpga_Reg.IRR, Fpga_Reg_Readback.IRR, "IRR register did not re= ad=20 > back correctly"); >=20 Not quite. Your example, which I was following, looked like ITR and IRR we= re both software registers. Both of them looked to be eight bits wide whic= h implies to me, that the individual bits would be defined in a record and = used the way that I was showing. So the comparison between the ITR and IRR= would be between two design specific record types, not just std_logic. This means that your example here of check_equal wouldn't work without firs= t creating an override of check_equal that works with those specific record= types. That's OK, but it means that now when you define new record types,= you'll have to also create a 'check_equal' override. Right now, when I cr= eate a record type, there will typically be overridden functions of to_std_= ulogic_vector, from_std_logic_vector and frequently, but not always image. = Having to add another override for 'check_equal' is more work, so I would = have to be convinced of the value to do so first. Actually, of late, what = I've found to be more useful is a 'diff_image' function that takes two reco= rd type arguments and returns an image only where record elements between t= he two are different. That way, I'm not eyeballing 10 different fields tha= t are the same to weed out the one or two that are different when the asser= tion fails and prints the 'diff_image'. > while still being self-documenting. Given that a check for equality is on= e of=20 > the most common ones this will save you a lot of redundant typing.=20 I agree that wrapping the assertion into a procedure will typically save ty= ping. On the other hand, many times that typing is only actually done one = time within a procedure that may gets called all over the place so the savi= ngs on typing isn't really there. >=20 > Another good thing about standard check and log procedures, at least for = us=20 > writing tools, is that they are easier to parse such that you can add cod= e- > related feature not available in VHDL itself. For example, if you enable = the=20 > location preprocessor in your VUnit run script=20 > (ui.enable_location_preprocessing()) and the have a log like this >=20 > info("Some log message"); >=20 > the output will be like this (verbose format) >=20 > 0 ps: INFO in (tb_demo.vhd:27): Some log message >=20 > This is useful when finding things and filtering your CSV file in Excel. = A=20 > drawback is that it is the preprocessed file you will see in the simulato= r=20 > and you my be tempted to edit that one and not the original file. >=20 We may be talking about different things. Whereas the assertion output log= ging and whatever one puts to the console is one thing, the CSV files I wou= ld typically generate are totally separate files that are not nearly so fre= e form as what would go to the console/transcript window. As an example, there might be a monitor procedure which takes address, data= , read/write commands, wait/ack signals all as inputs and whenever a transa= ction on that bus completes, a new line is written with sim time, address, = command, data. No filtering or simply using Excel's built-in filtering has= always been enough, no pre-processing needed. The one drawback is that Ex= cel locks the file when it opens so one has to either make a copy of the fi= le if the sim is still running, or you have to stop the sim. Otherwise, th= e sim quickly stops because it won't be able to write out that new line. B= ut even that isn't all that bad, because it doesn't actually crash Modelsim= , it just stops the sim on the 'file_open' but the subsequent writes to the= file complete normally (since I don't start the sim then until I have fini= shed looking at the CSV file) so I haven't actually lost anything. It seems= to be an odd, but fortuitous feature/bug of Modelsim. > Another issue with convenience procedures like check_equal is that we sup= port=20 > a commonly used but limited set of data types so if you want to make an= =20 > equality check between other types you're back to the plain assert. I think the better approach as I mentioned earlier would be to override che= ck_equal to work with the custom type. Within that overridden procedure on= e would call the Bitvis library check_equal procedure on the individual ele= ments of the custom type. > But to do the assert in your example you need to define "=3D" and image()= for that type. Yes for 'image', but no you don't for '=3D'. > If you define a to_string() function instead of image() and enable the ch= eck=20 > preprocessing (ui.enable_check_preprocessing()) you can do like this >=20 > check_relation(Fpga_Reg =3D Fpga_Reg_Readback, "Registers did not read ba= ck correctly"); >=20 > and a failed test will output this >=20 > ERROR: Relation Fpga_Reg =3D Fpga_Reg_Readback failed! Left is ('1', '1')= . Right is ('1', '0'). Registers did not read back correctly >=20 I don't see how you can only pass in a Boolean (i.e. "Fpga_Reg =3D Fpga_Reg= _Readback" and have it print out the individual 'left' and 'right' sides of= that comparison. Did you not include something? Looking through the Zip = file from Bitvis, I couldn't find any 'check_relation' so it's not clear to= me what is going on here. > check_relation can be used with any relational operator and type as long = as=20 > the operator and to_string() functions are defined. Again, it's not clear to me what 'check_relation' actually is since it appe= ars to take as input a Boolean and a text string. > For more details see https://github.com/LarsAsplund/vunit/blob/master/exa= mples/vhdl/check/check_example.vhd Unfortunately, that file does not have the source for 'check_relation', onl= y examples (which are essentially like you've shown here) which would not a= llow you to separate the two things that are being compared (i.e. This =3D = That) to report individually on 'This' and 'That'. All you can report on i= s the Boolean that is the result of comparing 'This' with 'That'. Anyway, the bigger issue I thought was the way that the PPT example seemed = to indicate how clean and easy it is to have simple read and write procedur= es that are only working with hard coded constants. The reality is that th= ose hard coded constants would be a maintenance nightmare since they are co= mpletely separated from the underlying design elements. The effect of chan= ging a constant from x"AA" to x"AB" and how that change would then ripple i= nto and affect upcoming statements was not addressed at all. Removing the = design specific elements and working only with std_logic/std_logic_vectors = at the 'higher level' testbench source code level is a mistake and will bec= ome a maintenance nightmare for whoever follows this approach. The proper = place to work with std_logic/std_logic_vectors is only within helper functi= ons and procedures that encapsulate something. The 'higher level' testbenc= h code would only be working with this encapsulating function/procedure so = the fact that it then converts something to std_logic/std_logic_vectors is = just something that happens behind the scenes...which is exactly what you w= ould want. I realize the PPT is taking an easy to understand example so as to focus on= the testbench aspects but that is not an excuse for this kind of oversight= . As a thought experiment, take the PPT example and simply add the conditi= on that certain bits in either ITR or IRR or both will always be 0 even if = they are written as 1 (i.e. the bits are being reserved for future use whic= h is not an uncommon thing). To put that change in, the way I approach it = would involve changes to only the to_std_ulogic_vector, from_std_logic_vect= or functions that I mentioned previously. These functions exist in the sam= e package as the defining record type. Edit those two functions to force 0= on the appropriate bit fields, recompile and you're done. Zero changes at= the testbench level. I could also easily take it a step further and add a= n assertion inside those functions that checks to see if those bit fields r= eally are 0. Now look at what you would have to edit with the PPT source t= hat is shown...a whole bunch of editing of hard coded constants. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:43 2024 X-Received: by 10.67.6.196 with SMTP id cw4mr31782673pad.46.1435728559650; Tue, 30 Jun 2015 22:29:19 -0700 (PDT) X-Received: by 10.140.98.138 with SMTP id o10mr186263qge.33.1435728559394; Tue, 30 Jun 2015 22:29:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ff1no316816igc.0!news-out.google.com!4ni33175qgh.1!nntp.google.com!t90no153865qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 22:29:19 -0700 (PDT) In-Reply-To: <0cad22af-1ab1-45c9-a3a6-1801303777ad@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> <0cad22af-1ab1-45c9-a3a6-1801303777ad@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1157a6ab-68e9-4f58-8c26-4ed280e4fb3d@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Wed, 01 Jul 2015 05:29:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3824 Kevin,=20 Lars is talking about the VUnit procedure check_relation and not anything i= n Bitvis. The reason it looks like it takes a boolean but can show a string= message is that the code is pre-processed by a Python script rewriting the= call. Such pre-processing is an optional feature that can be enabled in VU= nit. As I mentioned in my previous reply to you, since VUnit is not just a = VHDL library but a complete tool it could do things like preprocessing and = code generation on the fly. Code generation of to_string and check_equal on= all records within a package is something that we are thinking about doing= to save redundant code. We are still exploring this area. From newsfish@newsfish Thu Aug 1 00:33:44 2024 X-Received: by 10.129.90.214 with SMTP id o205mr31863437ywb.1.1435731966392; Tue, 30 Jun 2015 23:26:06 -0700 (PDT) X-Received: by 10.140.100.136 with SMTP id s8mr284739qge.2.1435731966355; Tue, 30 Jun 2015 23:26:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!t90no159675qga.0!news-out.google.com!4ni33200qgh.1!nntp.google.com!t90no159673qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 23:26:06 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.121.237.82; posting-account=fZovLAoAAAD3S-AUwPsJor4VbxwCeVmC NNTP-Posting-Host: 80.121.237.82 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Subject: How to generate unique ID for each FPGA using Ring Oscillator PUF From: mubinicyer@gmail.com Injection-Date: Wed, 01 Jul 2015 06:26:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 8218 X-Received-Body-CRC: 1223908378 Xref: news.eternal-september.org comp.lang.vhdl:3825 Hi, I am designing a Physically Uncolonable Function using Ring Oscillator on F= PGA (Spartan6). However, it does not generate uniqe ID for each chip, it ge= nerates exactly same value for different chips. Different ROs must generate= different frequency due to die-imperfection. I will compare those frequenc= ies and generate bits, which should be unique for each chip, since each chi= p has different physicall die-imperfection. First, I generate 16 ROs, each with 51 inverter gates, all of them are conn= ected to two multiplexers, I connected the select inputs of multiplexers wi= th 8-bit dip-switch. Outputs of multiplexers are connected to two 16-bit co= unters. Outputs of counters are connected to a comparator, If first counter= reachs end value (111...11) (if it is faster than second counter) comparat= or gives '1', if second counter is faster than first, comparator gives a '0= '. This generates only one bit. I replicated this design 16-times to genera= te 16-bit response. The first bits of this response (3 downto 0) are connec= ted to 4-leds. I tested the design with 3 different chips, they give exactl= y same respnose, which is not desired. How can I make it in order to have different responses? Thanks. ring_oscillator.vhd: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ring_oscilator is generic (delay: time :=3D 200ps; chain_len: integer :=3D 16); port( rst_i : in std_logic; ro_o : out std_logic); end ring_oscilator; architecture Behavioral of ring_oscilator is signal chain : std_logic_vector(chain_len downto 0); attribute keep: boolean; attribute keep of chain: signal is true; begin --assert chain_len mod 2 =3D 1 report "Length of ring must be an odd number= !" severity failure; gen_chain: for i in 1 to chain_len generate chain(i) <=3D not chain(i-1) after delay; end generate; chain(0) <=3D chain(chain_len) nor rst_i after delay; ro_o <=3D chain(chain_len); end Behavioral; debounce.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity debouncer is generic( counter_size : INTEGER :=3D 19); --counter size (19 bits gives 10.5ms= with 50MHz clock) port( clk_i : in std_logic; --input clock button_i : in std_logic; --input signal to be debounced enable_i : in std_logic; -- for simulation result_o : out std_logic); --debounced signal end debouncer; ARCHITECTURE logic of debouncer is signal flipflops : std_logic_vector(1 downto 0); --input flip flops signal counter_set : std_logic; --sync reset to zero signal counter_out : std_logic_vector(counter_size downto 0) :=3D (others= =3D> '0'); --counter output begin counter_set <=3D flipflops(0) xor flipflops(1); --determine when to sta= rt/reset counter =20 process(clk_i) begin if rising_edge(clk_i) then flipflops(0) <=3D button_i; flipflops(1) <=3D flipflops(0); =09 if enable_i =3D '1' then if(counter_set =3D '1') then --reset counter because in= put is changing counter_out <=3D (others =3D> '0'); elsif(counter_out(counter_size) =3D '0') then --stable input time is not= yet met counter_out <=3D counter_out + 1; else --stable input time is met result_o <=3D flipflops(1); end if; else result_o <=3D button_i; end if; end if; end process; end logic; top.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_misc.ALL; use IEEE.std_logic_unsigned.ALL; use ieee.numeric_std.all; entity top is Generic ( nr_ro : natural :=3D 16; puf_width : natural :=3D 16 ); Port ( =09 shift_i : in std_logic ; --debug dout_o : out std_logic_vector(3 downto 0); --debug =09 sel_i : in std_logic_vector(7 downto 0); --debug=09 clk_i : in STD_LOGIC; rst_i : in STD_LOGIC--;=20 -- puf_out : out STD_LOGIC_VECTOR (puf_width-1 downto 0) ); end top; architecture Behavioral of top is constant c_width : natural :=3D puf_width; constant c_number_of_ro : natural :=3D nr_ro; =20 -----------------------------DEBUG------------------------------------- signal s_sel : std_logic_vector(7 downto 0) :=3D (others =3D> '0'); signal s_dout : std_logic_vector(3 downto 0) :=3D (others =3D> '0'); signal s_shift : std_logic :=3D '0'; signal s_shift_pre : std_logic :=3D '0'; signal s_pulse : std_logic :=3D '0'; =09 signal s_msb : integer range 0 to 16 :=3D 4; -----------------------------------------------------------------------=09 signal s_reset : std_logic :=3D '0'; signal s_finish : std_logic_vector (c_width-1 downto 0):=3D (others =3D>= '0'); signal s_finished : std_logic :=3D '0'; signal s_puf_out : std_logic_vector (c_width-1 downto 0):=3D (others =3D>= '0'); --------------components---------------------------- component puf_bit generic ( nr_ro: natural :=3D c_number_of_ro ); port ( clk_i : in std_logic; rst_i : in std_logic; sel1_i : in unsigned(3 downto 0); sel2_i : in unsigned(3 downto 0); finish_o : out std_logic; puf_bit_o : out std_logic ); end component; component debouncer generic(counter_size : integer :=3D 19); --counter size (19 bits gives 1= 0.5ms with 50MHz clock) port( clk_i : in std_logic; --input clock button_i : in std_logic; --input signal to be debounced enable_i : in std_logic;=20 result_o : out std_logic); --debounced signal end component; begin Generate_PUF: for i in 0 to c_width-1 generate =09 Multiple_Puf_Bits: puf_bit=20 generic map (nr_ro =3D> c_number_of_ro) port map ( clk_i =3D> clk_i,=20 rst_i =3D> s_reset,=20 sel1_i =3D> unsigned(s_sel(3 downto 0)), =20 sel2_i =3D> unsigned(s_sel(7 downto 4)), finish_o =3D> s_finish(i), puf_bit_o =3D> s_puf_out(i) ); end generate; =09 reset_debounce: debouncer generic map (counter_size =3D> 19) port map (clk_i =3D> clk_i, button_i =3D> not rst_i, enable_i =3D> '1'= , result_o =3D> s_reset); --On FPGA board btn is low active =09 btn_debounce: debouncer generic map (counter_size =3D> 19) port map (clk_i =3D> clk_i, button_i =3D> not shift_i, enable_i =3D> '= 1', result_o =3D> s_shift); --On FPGA board btn is low active =09 s_finished <=3D AND_REDUCE(s_finish); ------------ debug-------------------------------- s_sel <=3D sel_i; =20 dout_o <=3D s_puf_out(7 downto 4); ----------------------------------------------=09 end Behavioral; From newsfish@newsfish Thu Aug 1 00:33:44 2024 X-Received: by 10.140.238.201 with SMTP id j192mr32919590qhc.14.1435734960577; Wed, 01 Jul 2015 00:16:00 -0700 (PDT) X-Received: by 10.140.105.10 with SMTP id b10mr291171qgf.26.1435734960559; Wed, 01 Jul 2015 00:16:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!t90no165573qga.0!news-out.google.com!w15ni14608qge.0!nntp.google.com!s91no165563qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jul 2015 00:15:58 -0700 (PDT) In-Reply-To: <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Wed, 01 Jul 2015 07:16:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3826 Hi Kevin, Please see comments below. tirsdag 30. juni 2015 17.25.11 UTC+2 skrev KJ f=F8lgende: > On Friday, June 12, 2015 at 9:39:45 AM UTC-4, espen.t...@bitvis.no wrote: > > on average 50% of FPGA designers' time is spent on verification, and=20 > > almost half of that verification time is spent on debugging. This means= : > >=20 > > 1. Good reports for unexpected design behaviour is critical. > > 2. Good progress reporting is also critical. > > 3. Good basic testbench features are required > >=20 > > Thus we need a library with good functionality for mismatch reporting,= =20 > > progress reporting and for checks etc. that are needed for every single= =20 > > testbench; like=20 >=20 > Since one can just as easily do all of the above with straight VHDL and b= e just as concise or even more so, it does not really follow that what is n= eeded is a 'library with good...'. =20 Anything provided with almost any library can be done with straight vhdl. The point of a support library is 1. Improve overview, readability, maintainability and structure 2. Reduce amount of writing ONLY if all above is satisfied. >=20 > > - checking value against expected > > - waiting for something to happen - with a timeout > > - checking stability of a signal > > - waiting for a signal to be stable for a given time (with timeout) > >=20 > > The only free library library (to my knowledge) to provide all this=20 > > functionality is Bitvis Utility Library.=20 >=20 > OK, but the VHDL language provides this as well. See above comment. >=20 > >=20 > > If this sounds interesting, you should read the below intro. > > You can download the library and PPT from=20 > > http://bitvis.no/resources/utility-library-download/ without any=20 > > registration. >=20 > Thanks for providing, that in itself is a useful service. >=20 > My read is that the library is way to low level to be an effective archiv= e to capture the original intent of the testbench which means that a testbe= nch written using Bitvis will be just as opaque as the testbenches you comp= lain about now. As an example of checking register function (from slide 31= of the PowerPoint): >=20 > write(C_ADDR_ITR, x"AA", "ITR : Set interrupts"); > check(C_ADDR_IRR, x"AA", ERROR, "IRR"); >=20 > Some simple observations: > - The hard coded constants x"AA" are not independent. Changing one requi= res you to change the second one. But this is not controlled by the code i= n any way. Totally agree, but this was not at all the point in this example. The point is you write=20 'write(, , ) rather than lots of signal wiggling and other= vhdl statements. Almost everybody make BFMs (Bus Functional Modules) these days just for tha= t reason. The use of VHDL constants rather than literals is of course recommended, bu= t that was not the point here. > - Similarly, as one works through the rest of the script, there are other= hidden dependencies that occur. Again - this is up to the user. It has nothing to do with using the library= . > - The expected response of the DUT is implicit (the reading back of data = from IRR and expecting it to be the same as what was written into ITR). At= first glance, one almost might thought it was an error to write to one reg= ister and expect some other register to read back that same data. The code= you have is actually just an undetectable typo away from being a 'write th= en read back' test of just ITR (or IRR). I'm not sure I understand what you mean here, but again the DUT has nothing= to do with the library. The functionality of the ITR register is in fact very useful to system debu= gging. There are better ways of doing a write/read test, but again this is not the= point here. The examples here are also used in a course we have, where we later discuss= using constants, records, overloads, procedures calling procedures, etc. > - Although this particular test is simply testing the bits somewhat indep= endently, those bits typically have definitions from a record but here you'= re totally ignoring those definitions and turning on and off bits in a byte= with no regard for what that bit defines. While OK for a simple read/writ= e testing as you're showing, there is nothing in Bitvis that would let it s= cale it up to something more general which is what you would want once you = get beyond the simple read/write tests. Consider now this could be written= in vanilla VHDL: >=20 > -- Let's check operation of the 'This' and 'That' interrupt bits > Fpga_Reg.ITR :=3D > ( > This_Interrupt =3D> "1", > That_Interrupt =3D> "1", > Reserved =3D> (others =3D> '0') > ); > reg_write(Fpga_Reg.ITR); > Fpga_Reg.IRR :=3D Fpga_Reg.ITR; -- This is the DUT response that is expec= ted=20 IRR is not supposed to be the same as ITR. More bits may be set in IRR from= previous interrupts or ITR writes. > Fpga_Reg_Readback.IRR :=3D reg_read; >=20 > assert (Fpga_Reg.IRR =3D Fpga_Reg_Readback.IRR) report > "IRR register did not read back correctly" & LF & > "Expected: Fpga_Reg.IRR=3D" & image(Fpga_Reg.IER) & LF & > "Actual: Fpga_Reg_Readback.IRR=3D" & image(Fpga_Reg_Readback.IRR) > severity ERROR; >=20 > While the code is wordier, it is also self-documenting. Using the Bitvis = library, one would have to dig into a whole lot more design specific detail= and documentation (that is outside the scope of the testbench itself) just= to understand what the testbench is trying to accomplish. With what I've = shown, that should not be the case. As a bonus, you don't have any of the = shortcomings that I pointed out earlier either. The shortcomings is up to the user. Use good constant names, records, etc. Nothing to do with BVUL. The BFM is in fact also not a part of BVUL, but I would definitely recommen= d it rather than using explicit assert statements. A BFM is more readable, easier to maintain, etc. Yes - you do have to understand the functionality of any procedure you use,= but without procedures and functions it is difficult to handle complex tes= tbenches. In this case one has to read somewhere that parameter 1 is addr, = p2 is data and p3 is message, OR you could use explicit parameter mapping. = In fact as long as you use unsigned, std_logic_vector and string respective= ly for these parameters you can't go wrong (other than compile error). There is a powerpoint presentation on how to use the library and the BFMs. = This can be browsed as a file, or you can even watch a 1 hour webinar. Ever= ything should be more obvious then. >=20 > Of course the main issue is that Bitvis, since it is attempting to be gen= eric, cannot be design specific, but in order to get good code clarity you = do want the executable code to be design specific. You do want to have exe= cutable that looks like 'Control_Reg.Fire_The_Gun :=3D "1"' to then have a = response of 'Status_Reg.Off_To_The_Races :=3D "1"', not hard coded hex cons= tants...that then have to change as the 'Off_To_The_Races' bit gets moved f= rom bit 5 to bit 6. BVUL does not stop you from using records. That is your choice.=20 > Testbench modelling at the top design level should start by modeling the = board that the design will be put into. This then naturally leads to model= ing the system that the board goes into as well. Following that approach p= roduces a library of parts that can then be reused in other testbenches bec= ause they are modeling actual parts, not just something cobbled together to= control/check interface ABC of design XYZ. It will also produce XYZ desig= n specific stuff as well. BVUL is only one piece in the puzzle. Please see my post above - starting w= ith 'Hi Olof, I final comment from my side'.=20 >=20 > I have yet to have a time when 'verbosity control' was something I would = want. The testbench will stop on an error and I have the complete log file= that I need to debug the problem. What you don't mention at all that is u= seful is simply to produce multiple log files. For example, logging transa= ction that occur on a particular interface to a CSV file so that it can be = pulled up in Excel. Using those interface log files along with the main tr= anscript log file is a powerful debug aid. For those who do post processing in other tools that is a good approach. There is nothing stopping you from using BVUL that way. For those who want to look at the transcript or a log file directly - verbo= sity control could be very useful. Also ID-based verbosity control allows very simple filtering as you have bo= th the scope and the ID available for that. >=20 > I don't want to seem to be too harsh, it's not that I think the library i= s 'bad'. Much of what you have is useful info, but the library while it ma= y improve how some people today write a testbench eventually it will stunt = testbench development because it does not go far enough to produce maintain= able code. While I accept that you have found users that find it useful, f= or me it would be a big step backwards since it would produce less maintain= able code and probably take just as long, or longer to develop in the first= place. There will always be different opinions and taste, but please spend the tim= e to go through the PPT to see the purpose of some of the features. >=20 > Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:44 2024 X-Received: by 10.182.214.9 with SMTP id nw9mr10439078obc.5.1435736512144; Wed, 01 Jul 2015 00:41:52 -0700 (PDT) X-Received: by 10.140.99.44 with SMTP id p41mr47017qge.3.1435736512034; Wed, 01 Jul 2015 00:41:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!ff1no358233igc.0!news-out.google.com!w15ni14611qge.0!nntp.google.com!t90no169106qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jul 2015 00:41:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1f0ba28b-a7db-4b1c-9455-862000b146ba@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Wed, 01 Jul 2015 07:41:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 170 Xref: news.eternal-september.org comp.lang.vhdl:3827 Hi Kevin In addition to what Olof said Den onsdag 1 juli 2015 kl. 05:31:28 UTC+2 skrev KJ: > On Tuesday, June 30, 2015 at 4:22:16 PM UTC-4, Lars Asplund wrote: > > Hi Kevin, > >=20 > > One place where I think verbosity control is useful is when you have a = trace=20 > > log like the one I showed in the previous comment (runner_trace_logger)= . I=20 > > don't want to filter what goes to file because I don't know what will b= e=20 > > interesting before I have the problems that caused me to open the file. >=20 > Exactly. No filtering. At the point where the sim stops at an assertion= , I have everything I need so there is no need to filter anything. I also = don't necessarily need to look at everything in the file since I'm debuggin= g a specific problem. I would look at the transcript window or file for ba= sic information, I would look at auxiliary files if necessary but primarily= I will be looking at the signals and variables at the point where the sim = stopped in order to determine why the assertion condition failed. >=20 > > During long simulations I may also want to get some progress from the t= race=20 > > log on stdout but there's no point if I can't reduce that output to a m= essage=20 > > pace which I can read. For that I use verbosity control on the log leve= l. >=20 > For that I simply grab the scroll bar which effectively pauses the window= . Or, if I have the transcript set to go to an output file rather than the= GUI, I simply open the file in a text editor while the sim keeps on runnin= g. I guess how you browse for information is much of a personal preference but= what I'm trying to say is that if I can't know in advance what information= that will be interesting I do not filter (and save to file). If I do know = in advance that I want to see that basic progress information among the tho= usands of debug message lines I rather set stdout verbosity than doing that= browsing. >=20 > >=20 > > When it comes to assert statements like the one you mention I think the= y can=20 > > be reduced to (here I'm assuming that IRR and ITR are std_logic).=20 > >=20 > > check_equal(Fpga_Reg.IRR, Fpga_Reg_Readback.IRR, "IRR register did not = read=20 > > back correctly"); > >=20 >=20 > Not quite. Your example, which I was following, looked like ITR and IRR = were both software registers. Both of them looked to be eight bits wide wh= ich implies to me, that the individual bits would be defined in a record an= d used the way that I was showing. So the comparison between the ITR and I= RR would be between two design specific record types, not just std_logic. >=20 > This means that your example here of check_equal wouldn't work without fi= rst creating an override of check_equal that works with those specific reco= rd types. That's OK, but it means that now when you define new record type= s, you'll have to also create a 'check_equal' override. Right now, when I = create a record type, there will typically be overridden functions of to_st= d_ulogic_vector, from_std_logic_vector and frequently, but not always image= . Having to add another override for 'check_equal' is more work, so I woul= d have to be convinced of the value to do so first. Actually, of late, wha= t I've found to be more useful is a 'diff_image' function that takes two re= cord type arguments and returns an image only where record elements between= the two are different. That way, I'm not eyeballing 10 different fields t= hat are the same to weed out the one or two that are different when the ass= ertion fails and prints the 'diff_image'. >=20 > > while still being self-documenting. Given that a check for equality is = one of=20 > > the most common ones this will save you a lot of redundant typing.=20 >=20 > I agree that wrapping the assertion into a procedure will typically save = typing. On the other hand, many times that typing is only actually done on= e time within a procedure that may gets called all over the place so the sa= vings on typing isn't really there. The idea is that check_equal should cover commonly used data types. If you = miss something that you feel is "common" you can create an issue on https:/= /github.com/LarsAsplund/vunit/issues. For other types you can use check_relation which will get some of the work = done for you. >=20 > >=20 > > Another good thing about standard check and log procedures, at least fo= r us=20 > > writing tools, is that they are easier to parse such that you can add c= ode- > > related feature not available in VHDL itself. For example, if you enabl= e the=20 > > location preprocessor in your VUnit run script=20 > > (ui.enable_location_preprocessing()) and the have a log like this > >=20 > > info("Some log message"); > >=20 > > the output will be like this (verbose format) > >=20 > > 0 ps: INFO in (tb_demo.vhd:27): Some log message > >=20 > > This is useful when finding things and filtering your CSV file in Excel= . A=20 > > drawback is that it is the preprocessed file you will see in the simula= tor=20 > > and you my be tempted to edit that one and not the original file. > >=20 >=20 > We may be talking about different things. Whereas the assertion output l= ogging and whatever one puts to the console is one thing, the CSV files I w= ould typically generate are totally separate files that are not nearly so f= ree form as what would go to the console/transcript window. >=20 > As an example, there might be a monitor procedure which takes address, da= ta, read/write commands, wait/ack signals all as inputs and whenever a tran= saction on that bus completes, a new line is written with sim time, address= , command, data. No filtering or simply using Excel's built-in filtering h= as always been enough, no pre-processing needed. The one drawback is that = Excel locks the file when it opens so one has to either make a copy of the = file if the sim is still running, or you have to stop the sim. Otherwise, = the sim quickly stops because it won't be able to write out that new line. = But even that isn't all that bad, because it doesn't actually crash Models= im, it just stops the sim on the 'file_open' but the subsequent writes to t= he file complete normally (since I don't start the sim then until I have fi= nished looking at the CSV file) so I haven't actually lost anything. It see= ms to be an odd, but fortuitous feature/bug of Modelsim. > Sorry for being a bit unclear here. What I meant was that having easy-to-pa= rse procedures like check() instead of assert and log() instead of report m= akes it easier to create preprocessing features like adding location inform= ation (file name and line number) to output messages. VHDL can give you *wh= en* something happened with "now" but not *where* it happen which is also v= ery interesting. You can optionally have this for both logs and checks but = I gave a log example (info("Some log message");) because I think that's whe= re you have the most value. With checks it can add a value if you don't sto= p at the first error but when you do you'll get the same and more informati= on from the call stack. > > For more details see https://github.com/LarsAsplund/vunit/blob/master/e= xamples/vhdl/check/check_example.vhd >=20 > Unfortunately, that file does not have the source for 'check_relation', o= nly examples (which are essentially like you've shown here) which would not= allow you to separate the two things that are being compared (i.e. This = =3D That) to report individually on 'This' and 'That'. All you can report = on is the Boolean that is the result of comparing 'This' with 'That'. >=20 As Olof mentioned the examples in the file are simplified to focus on the f= unctionality of the checks but I wasn't pointing to that. I was pointing at= some of the drawbacks of check_relation which are listed on line 215-217. = If you want to see how checks are implemented you should start here https:/= /github.com/LarsAsplund/vunit/tree/master/vhdl/check and if you want to see= how the preprocessing supporting check_relation works you should go to htt= ps://github.com/LarsAsplund/vunit/blob/master/vunit/check_preprocessor.py Regards, Lars From newsfish@newsfish Thu Aug 1 00:33:44 2024 X-Received: by 10.140.238.201 with SMTP id j192mr34135178qhc.14.1435751132330; Wed, 01 Jul 2015 04:45:32 -0700 (PDT) X-Received: by 10.140.38.180 with SMTP id t49mr324133qgt.9.1435751132311; Wed, 01 Jul 2015 04:45:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!s91no201901qgd.1!news-out.google.com!4ni33209qgh.1!nntp.google.com!s91no201896qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jul 2015 04:45:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:1986:560d:8afa:771c; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:1986:560d:8afa:771c References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: KJ Injection-Date: Wed, 01 Jul 2015 11:45:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3828 On Wednesday, July 1, 2015 at 3:16:04 AM UTC-4, espen.t...@bitvis.no wrote: > > Since one can just as easily do all of the above with straight VHDL and= be=20 > > just as concise or even more so, it does not really follow that what is= =20 > > needed is a 'library with good...'. =20 >=20 > Anything provided with almost any library can be done with straight vhdl. > The point of a support library is > 1. Improve overview, readability, maintainability and structure > 2. Reduce amount of writing ONLY if all above is satisfied. >=20 The examples in the PowerPoint compared with how I showed I would handle th= at same example do not agree with your statement. What I showed was self-d= ocumenting and more maintainable. What I was showing is only 'more writing= ' if you don't consider the additional documentation that would need to be = written to explain the testbench itself. > > Some simple observations: > > - The hard coded constants x"AA" are not independent. Changing one=20 > > requires you to change the second one. But this is not controlled by t= he=20 > > code in any way. >=20 > Totally agree, but this was not at all the point in this example. > The point is you write=20 > 'write(, , ) rather than lots of signal wiggling and oth= er=20 > vhdl statements. > Almost everybody make BFMs (Bus Functional Modules) these days just for t= hat=20 > reason. What I showed in my example was even simpler, no address was required at al= l at the top testbench level. What I showed was: reg_write(Fpga_Reg.ITR);=20 Fpga_Reg_Readback.IRR :=3D reg_read;=20 This is simpler than the Bitvis approach. Now obviously an address at some= point is required, but that address would be in the lower level helper pro= cedure that takes as input an argument of the specified record type. What = Bitvis demonstrated is read/write using std_logic_vectors. While this will= be needed, it should not be used at the top level of the testbench as Bitv= is was advocating. > The use of VHDL constants rather than literals is of course recommended, = but > that was not the point here. The point as I got it was how to use the Bitvis library in a testbench. Wh= at was advocated was using calls to the Bitvis library at the top level of = the testbench. The Bitvis library by itself does not provide the lower lev= el signal twiddling for a particular interface, a user would need to write = that. With my approach they would have to do this as well. At the testben= ch top level, the use of design independent std_logic_vectors as shown by B= itvis provides a less robust, less readable way than my approach which is t= o provide a simpler interface procedure which is explicitly tied to design = specific record definitions. > > - Similarly, as one works through the rest of the script, there are oth= er=20 > > hidden dependencies that occur. >=20 > Again - this is up to the user. It has nothing to do with using the libra= ry. >=20 No, but Bitvis provided the example to show the library. What I was demons= trating is the maintainability problems you will run into if you follow thi= s approach. You showed how easy and clean it is to have read/write procedu= res. I showed a slightly easier and cleaner approach, the main advantage t= hough is that it avoids those maintainability problems. The Bitvis example does not show the mess that would go into computing all = those hard coded constants which is where the mess and hidden dependencies = would make that approach much less maintainable then you seem to think. Wh= ile you can sit back and say the computation of those constants is outside = of the scope of the Bitvis library (and I agree it is), by not showing what= that code would look like using Bitvis and now not comparing it to how I p= ropose it should look, you're trying to avoid the issue. It's not that I d= on't think that Bitvis does what it says, it's that what it does doesn't be= long at the top level of the testbench and since it doesn't really provide = the lowest level of the testbench, it's not clear at what level it really w= ould be useful to me. > > - The expected response of the DUT is implicit (the reading back of dat= a=20 > > from IRR and expecting it to be the same as what was written into ITR).= At=20 > > first glance, one almost might thought it was an error to write to one= =20 > > register and expect some other register to read back that same data. T= he=20 > > code you have is actually just an undetectable typo away from being=20 > > a 'write then read back' test of just ITR (or IRR). >=20 > I'm not sure I understand what you mean here, but again the DUT has nothi= ng=20 > to do with the library. The point is that how the DUT is supposed to respond to something (i.e. the= write to ITR) is something that should be clear in the testbench. I made = that expected response explicit. The Bitvis example did not and actually c= ould be interpreted in a totally different way...because of the way the top= level testbench was written. > The functionality of the ITR register is in fact very useful to system=20 > debugging. Yes it is. > There are better ways of doing a write/read test, but again this is not t= he=20 > point here. The Bitvis example was not a write/read test. It was a functionality test.= You write to one register and expect a response from a different register= . A write/read test would check the response from the same register. > The examples here are also used in a course we have, where we later discu= ss > using constants, records, overloads, procedures calling procedures, etc. OK >=20 > >=20 > > -- Let's check operation of the 'This' and 'That' interrupt bits > > Fpga_Reg.ITR :=3D > > ( > > This_Interrupt =3D> "1", > > That_Interrupt =3D> "1", > > Reserved =3D> (others =3D> '0') > > ); > > reg_write(Fpga_Reg.ITR); > > Fpga_Reg.IRR :=3D Fpga_Reg.ITR; -- This is the DUT response that is exp= ected=20 >=20 > IRR is not supposed to be the same as ITR. More bits may be set in IRR fr= om=20 > previous interrupts or ITR writes. But not at that point in the testbench. The 'more bits' part shows up in a= totally undocumented way further down. With my approach, again that behav= ior would have been self-documenting. With the Bitvis example all that is = provided is a slew of hard coded constants with no code backing up the comp= utation of those constants. > >=20 > > While the code is wordier, it is also self-documenting. Using the Bitvi= s=20 > > library, one would have to dig into a whole lot more design specific de= tail=20 > > and documentation (that is outside the scope of the testbench itself) j= ust=20 > > to understand what the testbench is trying to accomplish. With what I'= ve=20 > > shown, that should not be the case. As a bonus, you don't have any of = the=20 > > shortcomings that I pointed out earlier either. >=20 > The shortcomings is up to the user. Use good constant names, records, etc= . > Nothing to do with BVUL. Agreed that the shortcoming has nothing to do with the library itself. But= the shortcoming will be inherent in anyone who uses that library. However= , if you take a different approach as I showed, you don't have that shortco= ming at all. > The BFM is in fact also not a part of BVUL, but I would definitely recomm= end=20 > it rather than using explicit assert statements. > A BFM is more readable, easier to maintain, etc. But that is not the point. My example also uses bus functional models (reg= _write and reg_read). The assertions are at the higher level. After you d= o that read, did you get the right result. > Yes - you do have to understand the functionality of any procedure you us= e,=20 > but without procedures and functions it is difficult to handle complex=20 > testbenches. In this case one has to read somewhere that parameter 1 is a= ddr,=20 > p2 is data and p3 is message, OR you could use explicit parameter mapping= .=20 If you use the Bitvis library that is...however if you use my approach ther= e is only one parameter to the write which is the register that you want to= write and there are no parameters to the read. It's also just as easy to = have a 'read and compare' procedure which takes only one parameter which is= the expected result. That would hide the assertion statement that you thi= nk is so objectionable. I didn't take my example that far simply because t= he Bitvis example didn't either. > In fact as long as you use unsigned, std_logic_vector and string respecti= vely=20 > for these parameters you can't go wrong (other than compile error). Sure you can, in fact that is exactly where you will go wrong. Here are so= me examples of errors you will have that are completely avoidable in the fi= rst place: - Reading or writing the wrong address (i.e. passing the value of the addre= ss of ITR rather than IRR) - Changing the value of some hard coded constant in one place and not consi= dering what else has to change as a result. What I showed would take that = completely into account. What Bitvis showed was 'well you as the user have= to find and fix those things' >=20 > There is a powerpoint presentation on how to use the library and the BFMs= .=20 > This can be browsed as a file, or you can even watch a 1 hour webinar.=20 > Everything should be more obvious then. Wow...did you not even notice that was where I got the example from in the = first place? > >=20 > > Of course the main issue is that Bitvis, since it is attempting to be= =20 > > generic, cannot be design specific, but in order to get good code clari= ty=20 > > you do want the executable code to be design specific. You do want to = have=20 > > executable that looks like 'Control_Reg.Fire_The_Gun :=3D "1"' to then = have a=20 > > response of 'Status_Reg.Off_To_The_Races :=3D "1"', not hard coded hex= =20 > > constants...that then have to change as the 'Off_To_The_Races' bit gets= =20 > > moved from bit 5 to bit 6. >=20 > BVUL does not stop you from using records. That is your choice.=20 >=20 What I described are the issues you will have if you choose to use somethin= g like the Bitvis approach in the first place. > > I have yet to have a time when 'verbosity control' was something I woul= d=20 > > want. The testbench will stop on an error and I have the complete log = file=20 > > that I need to debug the problem. What you don't mention at all that i= s=20 > > useful is simply to produce multiple log files. For example, logging= =20 > > transaction that occur on a particular interface to a CSV file so that = it=20 > > can be pulled up in Excel. Using those interface log files along with = the=20 > > main transcript log file is a powerful debug aid. >=20 > For those who do post processing in other tools that is a good approach. > There is nothing stopping you from using BVUL that way. > For those who want to look at the transcript or a log file directly -=20 > verbosity control could be very useful. I don't use any post processing tools. I use the output files directly and= I said, have not found verbosity control to be anything that I would want = since I don't know ahead of time what I won't end up needing to look at to = debug a problem...which is the whole reason for generating those output fil= es. >=20 > There will always be different opinions and taste, but please spend the t= ime=20 > to go through the PPT to see the purpose of some of the features. >=20 I did spend the time to go through PPT, and I've posted what I see as short= comings. They are not shortcomings of the Bitvis library itself. They are= shortcomings for anyone who chooses to use the library. However, the idea= s represented (i.e. BFMs, encapsulation, etc.) are good, it's just that try= ing to bundle that idea into a generic library like Bitvis is not such a go= od idea. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Wed, 01 Jul 2015 10:10:47 -0700 Organization: Aioe.org NNTP Server Lines: 6 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3829 On 6/30/2015 11:26 PM, mubinicyer@gmail.com wrote: > Physically Uncolonable Function Please describe what that means. JJS From newsfish@newsfish Thu Aug 1 00:33:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Wed, 01 Jul 2015 14:24:26 -0400 Organization: Alacron, Inc. Lines: 12 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 1 Jul 2015 18:23:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="15523"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18UMsgGwwHLq3/fLpD6+JEyLlJy4Hm1eqk=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:ayjrizklyGYtcrqR4e+RYLhi0NA= Xref: news.eternal-september.org comp.lang.vhdl:3830 John Speth wrote: > On 6/30/2015 11:26 PM, mubinicyer@gmail.com wrote: >> Physically Uncolonable Function > > Please describe what that means. > > JJS Probably means that it is impervious to colonoscopy ;-) -- Gabor From newsfish@newsfish Thu Aug 1 00:33:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Wed, 01 Jul 2015 14:35:45 -0400 Organization: Alacron, Inc. Lines: 35 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 1 Jul 2015 18:34:41 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="19587"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mT6DoHf+LuzX5/A23xMBppIyIhEzgenc=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Cancel-Lock: sha1:HYJgfCn2RnSkyfixhpQusZ9afqg= Xref: news.eternal-september.org comp.lang.vhdl:3831 mubinicyer@gmail.com wrote: > Hi, > > I am designing a Physically Uncolonable Function using Ring Oscillator on FPGA (Spartan6). However, it does not generate uniqe ID for each chip, it generates exactly same value for different chips. Different ROs must generate different frequency due to die-imperfection. I will compare those frequencies and generate bits, which should be unique for each chip, since each chip has different physicall die-imperfection. > > First, I generate 16 ROs, each with 51 inverter gates, all of them are connected to two multiplexers, I connected the select inputs of multiplexers with 8-bit dip-switch. Outputs of multiplexers are connected to two 16-bit counters. Outputs of counters are connected to a comparator, If first counter reachs end value (111...11) (if it is faster than second counter) comparator gives '1', if second counter is faster than first, comparator gives a '0'. This generates only one bit. I replicated this design 16-times to generate 16-bit response. The first bits of this response (3 downto 0) are connected to 4-leds. I tested the design with 3 different chips, they give exactly same respnose, which is not desired. > How can I make it in order to have different responses? > > Thanks. > I think you are working on a faulty premise. While there will be a frequency difference for ring oscillators from device to device, the relative frequency of two such oscillators within any device will probably be similar. A lot of this has to do with routing delays, which cannot be easily matched from one section of the device to another. So even the static timing analysis will probably tell you right off the bat that oscillator "A" has more prop delay in the ring than oscillator "B" and so on. It's not just the LUT count. If you are trying to determine a unique device by measuring some quality of each of 16 distinct regions in the device, you need a more reliable way to make this measurement. If you want to use ring oscillators, I would start by using a fairly long counter to determine the relative speed, and instead of just seeing which one reaches terminal count first, latch the actual value of the other counter when that terminal count is reached. Then look at these relative numbers on a sampling of die to see if there is enough information to find a useful threshold to tell the devices apart. Even then you'd need to look at these values over a range of temperature and voltage conditions to make sure you can "fingerprint" the device reliably using just the process differences. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx27.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150701-2, 01/07/2015), Outbound message X-Antivirus-Status: Clean Lines: 32 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1435780301 86.17.210.161 (Wed, 01 Jul 2015 19:51:41 UTC) NNTP-Posting-Date: Wed, 01 Jul 2015 19:51:41 UTC Organization: virginmedia.com Date: Wed, 01 Jul 2015 20:51:39 +0100 X-Received-Body-CRC: 4093968850 X-Received-Bytes: 2796 Xref: news.eternal-september.org comp.lang.vhdl:3832 On 17/06/2015 01:51, michael6866 wrote: > On Tuesday, June 16, 2015 at 5:50:37 PM UTC-4, alb wrote: ..snip > >> >>> (2) It has faster simulation speed. [] >> >> Beaware of simulation speed comparisons. If you minimize the amount of >> signals and maximize the number of variables, you should be getting a >> very nice improve (both in maintainability and interoperability with >> other models). > Agree. However even with the same magnitude of signals / variables, SystemC is still much faster. As I mentioned this is because the way the RTL simulation engine works is different than the SystemC kernel. It is not, from what I understand the SystemC kernel is very close to the one used in VHDL. For this reason it is very easy for a VHDL engineer to pick up SystemC (leaving the C++ horrors aside) as you get the same signal/variables/process goodness. I am so happy the OSCI developers didn't pick the blocking and unblocking spaghetti model ;-) I am also pretty sure you are incorrect regarding the speed of models with the same number of events. Most vendors (re)use the OSCI reference simulator and although they might have tweaked it a bit it is still miles away from a modern VHDL kernel you find in say Modelsim/Riviera/NCSIM/etc. I have done a simple test were I converted a few simple RTL VHDL models into SystemC (same number of events, same architecture) and compared the speed. The VHDL models were roughly 2-3x faster than SystemC both executed on Modelsim. Regards, Hans www-ht-lab.com From newsfish@newsfish Thu Aug 1 00:33:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe001.ams.xsnews.nl!news.roellig-ltd.de!open-news-network.org!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 02 Jul 2015 06:09:45 -0500 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> In-Reply-To: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 2 Jul 2015 12:09:47 +0100 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: quoted-printable X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: Lines: 19 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-5WkBOFlhtqDYOxK07NG6YS/QkaYi+ujjmpMlQo1sEpnIyv56Naf+dftxwaQiN2GpEifRgkEea2uqFF9!RlO5KjfYZokAGorUbmyz1Az3b4ZFBga2Xl9/eq16z6++F7G+HHZ8U+QjYaIddNPiznwNNQNJjDKc!6T6wiY5Zw8LmGz1GhHNdYdkwCqs= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1747 Xref: news.eternal-september.org comp.lang.vhdl:3833 >wrote in message=20 >news:8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com... >Hi, >I am designing a Physically Uncolonable Function using Ring = Oscillator... Why not just read the random contents of some internal ram as part of = the=20 boot sequence. IME it will contain a random but device specific contents = not=20 dependant on temperature, just manufacturing differences from die to = die. Andy=20 From newsfish@newsfish Thu Aug 1 00:33:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 10:51:12 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 14:49:50 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="16777"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/aAs5Ttgqe+1ZOZswUUAxs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:O2WiOWa2zb8RsuI9VVO8BaCnxj4= Xref: news.eternal-september.org comp.lang.vhdl:3834 On 7/2/2015 7:09 AM, Andy Bennett wrote: > > >> wrote in message >> news:8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com... > >> Hi, > >> I am designing a Physically Uncolonable Function using Ring Oscillator... > > Why not just read the random contents of some internal ram as part of > the boot sequence. IME it will contain a random but device specific > contents not dependant on temperature, just manufacturing differences > from die to die. Why would you expect the power up contents of RAM to depend any more on manufacturing differences than the ring oscillator frequency? -- Rick From newsfish@newsfish Thu Aug 1 00:33:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 11:01:24 -0400 Organization: Alacron, Inc. Lines: 35 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 15:00:33 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="20579"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19fDS74+dpYPMUHnHDoUtykRLUIItPaUEs=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:1KoI1mbj1faPg9UvqBBKPKvuj9g= Xref: news.eternal-september.org comp.lang.vhdl:3835 rickman wrote: > On 7/2/2015 7:09 AM, Andy Bennett wrote: >> >> >>> wrote in message >>> news:8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com... >> >>> Hi, >> >>> I am designing a Physically Uncolonable Function using Ring >>> Oscillator... >> >> Why not just read the random contents of some internal ram as part of >> the boot sequence. IME it will contain a random but device specific >> contents not dependant on temperature, just manufacturing differences >> from die to die. > > Why would you expect the power up contents of RAM to depend any more on > manufacturing differences than the ring oscillator frequency? > A) In xilinx parts, that is very hard to do because the bitstream will load the BRAM contents along with every other storage element in the part. You would need to have special tools and some intimate part knowledge to selectively load the part at configuration. B) Whether or not it depends more or less on manufactuing differences than a ring oscillator, his original method was flawed in that it presumed that the manufacturing differences where the only thing affecting the relative oscillator frequencies. In fact, place and route differences would typically swamp any effect of manufacturing process unless the design were carefully hand routed and replicated. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 11:08:22 -0400 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 15:06:57 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21469"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX181pcZdpRHdqTrF2/eL5DhL" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:UbwQ1+Brq2L5goKqDRhWC8fAi3Q= Xref: news.eternal-september.org comp.lang.vhdl:3836 On 7/2/2015 11:01 AM, GaborSzakacs wrote: > rickman wrote: >> On 7/2/2015 7:09 AM, Andy Bennett wrote: >>> >>> >>>> wrote in message >>>> news:8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com... >>> >>>> Hi, >>> >>>> I am designing a Physically Uncolonable Function using Ring >>>> Oscillator... >>> >>> Why not just read the random contents of some internal ram as part of >>> the boot sequence. IME it will contain a random but device specific >>> contents not dependant on temperature, just manufacturing differences >>> from die to die. >> >> Why would you expect the power up contents of RAM to depend any more >> on manufacturing differences than the ring oscillator frequency? >> > > A) In xilinx parts, that is very hard to do because the bitstream > will load the BRAM contents along with every other storage element > in the part. You would need to have special tools and some intimate > part knowledge to selectively load the part at configuration. I am not sure that is correct. I don't have all the details of every FPGA family memorized, but I do recall reading that someone, somewhere allows block RAM contents to be preserved through configurations as an option in the bit stream. I am pretty sure that was a Xilinx part I read that about. So it is not so much "intimate knowledge" as it is reading the fine manual. > B) Whether or not it depends more or less on manufactuing differences > than a ring oscillator, his original method was flawed in that it > presumed that the manufacturing differences where the only thing > affecting the relative oscillator frequencies. In fact, place and > route differences would typically swamp any effect of manufacturing > process unless the design were carefully hand routed and replicated. I am not debating that. I am asking why anyone would expect the power up contents of RAM to be useful in distinguishing individual parts. The ring oscillator frequency at least has a chance of working if the design method is adapted to deal with the designed in differences. -- Rick From newsfish@newsfish Thu Aug 1 00:33:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 02 Jul 2015 10:22:42 -0500 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> In-Reply-To: Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 2 Jul 2015 16:22:45 +0100 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: quoted-printable X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: Lines: 27 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ttNGnmRVTVk8E2Ia2KE033nntVL6RW2iqcw9V3V5+EGZ65AMpTSnR5z1dUYfuw1EFG8ed24WgzGAmJd!zOZh37UvOZNvpm2M1MUFYMWIdGkmfavEoizAa3OHwo4YZK0L6SVbWoQ7Ybem+UM8a5C9JvRzHt3S!/qiqI4+tWQ7oackqhXt84nheN6Y= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2297 Xref: news.eternal-september.org comp.lang.vhdl:3837 On 7/2/2015 11:01 AM, GaborSzakacs wrote: > rickman wrote: >I am not debating that. I am asking why anyone would expect the power = up=20 >contents of RAM to be useful in distinguishing individual parts. The = ring=20 >oscillator frequency at least has a chance of working if the design = method=20 >is adapted to deal with the designed in differences. I don't know about Xilinx parts, but certainly Altera Cyclone and = Stratix=20 parts have the option of configuring RAM at power up with a don't care=20 option, and at the same time you configure the RAM so write is = permanently=20 held low you can treat it as unconfigured ROM - it will not be loaded = from=20 flash at power up and will contain random values due to manufacturing=20 tolerances. As I said before, IME the values are consistant from power = up to=20 power up. Andy. From newsfish@newsfish Thu Aug 1 00:33:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 11:28:54 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 15:27:29 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="26222"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX196f7UCl5nzWXdYne0qf1V6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:vm/4bprHW+lNJf7hMndG9hqyVvg= Xref: news.eternal-september.org comp.lang.vhdl:3838 On 7/2/2015 11:22 AM, Andy Bennett wrote: > > On 7/2/2015 11:01 AM, GaborSzakacs wrote: >> rickman wrote: > >> I am not debating that. I am asking why anyone would expect the power >> up contents of RAM to be useful in distinguishing individual parts. >> The ring oscillator frequency at least has a chance of working if the >> design method is adapted to deal with the designed in differences. > > I don't know about Xilinx parts, but certainly Altera Cyclone and > Stratix parts have the option of configuring RAM at power up with a > don't care option, and at the same time you configure the RAM so write > is permanently held low you can treat it as unconfigured ROM - it will > not be loaded from flash at power up and will contain random values due > to manufacturing tolerances. As I said before, IME the values are > consistant from power up to power up. But have you tested that the contents depend on "manufacturing tolerances"? I can see where the contents of the RAM would also be more dependent on design differences than manufacturing tolerances. -- Rick From newsfish@newsfish Thu Aug 1 00:33:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 02 Jul 2015 11:34:17 -0500 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> In-Reply-To: Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 2 Jul 2015 17:34:20 +0100 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: quoted-printable X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> Lines: 28 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-hXGG1vsTMKr6vrX3l7UmkwNGjJYVfbs0EJlFi5s0mBb/5BCo8IfpsZTqwE7A3z9FASkHJCx7OCYUEGJ!zeVbGDFhBmAtvSUUQ/imE/eFeTKfjtTbmnXTKWsrjTheGgtObRYXwkUj57FjqOJzRIadZWkzjMYS!ZdEQhRl66qAsyzoBGXHWvxE9nYg= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2343 Xref: news.eternal-september.org comp.lang.vhdl:3839 "rickman" wrote in message news:mn3l91$pje$1@dont-email.me... On 7/2/2015 11:22 AM, Andy Bennett wrote: > > On 7/2/2015 11:01 AM, GaborSzakacs wrote: >> rickman wrote: > >But have you tested that the contents depend on "manufacturing = tolerances"?=20 >I can see where the contents of the RAM would also be more dependent on = >design differences than manufacturing tolerances. Not sure what you mean by design differences - the RAM blocks are = defined=20 blocks on the silicon, not synthesised from the logic array. I have only tested the same FPGA design (mine) on the same FPGA part = type=20 across a number of different parts and got random RAM contents between=20 parts, but the same contents for each part over multiple power ups and=20 temperatures. I have not investigated further. Andy=20 From newsfish@newsfish Thu Aug 1 00:33:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 12:51:05 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 16:49:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14231"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX180G953fxe/ttxCZaz2msFv" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> Cancel-Lock: sha1:T5m8FeniWtnNEu9ZDgMAob+49Io= Xref: news.eternal-september.org comp.lang.vhdl:3840 On 7/2/2015 12:34 PM, Andy Bennett wrote: > > > "rickman" wrote in message news:mn3l91$pje$1@dont-email.me... > > On 7/2/2015 11:22 AM, Andy Bennett wrote: >> >> On 7/2/2015 11:01 AM, GaborSzakacs wrote: >>> rickman wrote: >> > >> But have you tested that the contents depend on "manufacturing >> tolerances"? I can see where the contents of the RAM would also be >> more dependent on design differences than manufacturing tolerances. > > Not sure what you mean by design differences - the RAM blocks are > defined blocks on the silicon, not synthesised from the logic array. > I have only tested the same FPGA design (mine) on the same FPGA part > type across a number of different parts and got random RAM contents > between parts, but the same contents for each part over multiple power > ups and temperatures. > I have not investigated further. If what you have seen is accurate across the various product lines and production batches, then a checksum or CRC on a block RAM should serve as a useful fingerprint. I would be very concerned that this finger print would be 100% repeatable. If it depends on manufacturing tolerances I would expect there to be a finite possibility of one or more bits being on the hairy edge and some small amount of noise determining the resting state rather than the device specifics. I guess it might be better to just record the entire block content and allowing for some small number of bits changing from read to read. -- Rick From newsfish@newsfish Thu Aug 1 00:33:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 16:25:53 -0400 Organization: Alacron, Inc. Lines: 43 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 20:25:04 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="1115"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18MZC/1Gzp531UhrRPdpsvuxyrTiO94zaQ=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:Izzy2rWamv7rLHgoVw0EJWKVjDI= Xref: news.eternal-september.org comp.lang.vhdl:3841 rickman wrote: > On 7/2/2015 12:34 PM, Andy Bennett wrote: >> >> >> "rickman" wrote in message news:mn3l91$pje$1@dont-email.me... >> >> On 7/2/2015 11:22 AM, Andy Bennett wrote: >>> >>> On 7/2/2015 11:01 AM, GaborSzakacs wrote: >>>> rickman wrote: >>> >> >>> But have you tested that the contents depend on "manufacturing >>> tolerances"? I can see where the contents of the RAM would also be >>> more dependent on design differences than manufacturing tolerances. >> >> Not sure what you mean by design differences - the RAM blocks are >> defined blocks on the silicon, not synthesised from the logic array. >> I have only tested the same FPGA design (mine) on the same FPGA part >> type across a number of different parts and got random RAM contents >> between parts, but the same contents for each part over multiple power >> ups and temperatures. >> I have not investigated further. > > If what you have seen is accurate across the various product lines and > production batches, then a checksum or CRC on a block RAM should serve > as a useful fingerprint. I would be very concerned that this finger > print would be 100% repeatable. If it depends on manufacturing > tolerances I would expect there to be a finite possibility of one or > more bits being on the hairy edge and some small amount of noise > determining the resting state rather than the device specifics. > > I guess it might be better to just record the entire block content and > allowing for some small number of bits changing from read to read. > On the other hand, I have to wonder why you need this functionality on an older Spartan 3 part. All the newer Xilinx series including Spartan 3A DSP have a serial number ("Device DNA") built in to provide a reliable mechanism to lock a design to a particular part. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 04 Jul 2015 12:47:07 GMT Lines: 16 Message-ID: <5597d5ca$0$1586$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 374328bc.news.astraweb.com X-Trace: DXC=Coc6YjV:h>iJRZZkg^aP1jL?0kYOcDh@j]WEZ@Q1WnGeE3=kG9hhb7bHI6bY5_;LhiEBe]G`V^KXg\X\Za@iJeXm9O\=`f7CS1d Xref: news.eternal-september.org comp.lang.vhdl:3842 On Thu, 02 Jul 2015 16:25:53 -0400, GaborSzakacs wrote: > On the other hand, I have to wonder why you need this functionality on > an older Spartan 3 part. All the newer Xilinx series including Spartan > 3A DSP have a serial number ("Device DNA") built in to provide a > reliable mechanism to lock a design to a particular part. >From Virtex 7 onwards, Xilinx Device DNA is not guaranteed to be unique - up to 32 devices can have the same serial number (Reference: UG470). Presumably this came from a desire to improve yield and reduce costs, rather than from a desire to make it completely useless to designers. I believe the older devices (up to and including V6) are still safe. Regards, Allan From newsfish@newsfish Thu Aug 1 00:33:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> <5597d5ca$0$1586$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 04 Jul 2015 17:31:23 GMT Lines: 48 Message-ID: <5598186b$0$1674$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: cfb3845c.news.astraweb.com X-Trace: DXC=NUm5^ICWTod]`e1HJ8=:?`L?0kYOcDh@jO13VQ=noH4ih:BbU8OZ3AmHI6bY5_;LhiEBe]G`V^KXg\X\Za@iJeXm=fLB\mo4W1b Xref: news.eternal-september.org comp.lang.vhdl:3843 On Sat, 04 Jul 2015 12:47:07 +0000, Allan Herriman wrote: > On Thu, 02 Jul 2015 16:25:53 -0400, GaborSzakacs wrote: > >> On the other hand, I have to wonder why you need this functionality on >> an older Spartan 3 part. All the newer Xilinx series including Spartan >> 3A DSP have a serial number ("Device DNA") built in to provide a >> reliable mechanism to lock a design to a particular part. > > From Virtex 7 onwards, Xilinx Device DNA is not guaranteed to be unique > - > up to 32 devices can have the same serial number (Reference: UG470). > Presumably this came from a desire to improve yield and reduce costs, > rather than from a desire to make it completely useless to designers. > > I believe the older devices (up to and including V6) are still safe. Correction (after I re-read some documentation): The Spartan 3A devices have a 57 bit number, a 55 bits slice of which is guaranteed to be unique. (Reference: UG332) The Xilinx V6 devices have a 64 bit number that is *not* guaranteed to be unique, and can be read out over JTAG. A 57 bit slice of the 64 bit number (also not guaranteed to be unique) can be read out inside the FPGA. The remaining 7 bits are described as "reserved". (Reference: UG360) The Xilinx V7 devices have a 64 bit number that is unique, and can be read out over JTAG. A 57 bit slice of the 64 bit number can be read out inside the FPGA. That 57 bit slice is *not* guaranteed to be unique. (Reference: UG470) Xilinx Ultrascale (and presumably Ultrascale Plus) devices have a longer (96 bit) sequence that is unique, and all 96 bits can be read out inside the FPGA. (Reference: UG570) BTW, they use efuse technology, and are programmed at the factory. The Spartan 3A ones are guaranteed for 10 years or 30 million read cycles. Regards, Allan From newsfish@newsfish Thu Aug 1 00:33:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: First steps using VUnit Date: Sun, 05 Jul 2015 01:23:20 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 4 Jul 2015 23:22:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3a996b8dd3a472e8b1724458c31fcf8d"; logging-data="3211"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18l+tfNcaubfvkXoG/nu70P" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 Cancel-Lock: sha1:e0k3mre9fwvK9iTiye6F29/X+Yc= Xref: news.eternal-september.org comp.lang.vhdl:3844 Hello, in the last few weeks I read much about VUnit and so I wanted to make some experiences. I cloned VUnit form Github and tried to run the example "tb_example". But when running the run.py script, using "python run.py -v lib.tb_example*", I get the following error message: Traceback (most recent call last): File "run.py", line 2, in from vunit import VUnit ImportError: No module named vunit I tried to add the vunit path to PYTHONPATH enviroment, but this also gives me the same error message. I'm using Python 2.7.5 but I'm an absolutly noob (this is the first time, I ever have called python in my console ;)). So can someone give me a hint what I'm doing wrong? I read the user_guide.md on Github page a several times, but I can't find the missing information I need to get the example running. Thanks a lot, Tobias From newsfish@newsfish Thu Aug 1 00:33:49 2024 X-Received: by 10.52.114.37 with SMTP id jd5mr1466269vdb.2.1436080885865; Sun, 05 Jul 2015 00:21:25 -0700 (PDT) X-Received: by 10.140.102.66 with SMTP id v60mr564432qge.19.1436080885804; Sun, 05 Jul 2015 00:21:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m107no171060qgd.1!news-out.google.com!4ni53551qgh.1!nntp.google.com!w90no504505qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Jul 2015 00:21:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> Subject: Re: First steps using VUnit From: Lars Asplund Injection-Date: Sun, 05 Jul 2015 07:21:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:3845 Hi Tobias, What is your PYTHONPATH pointing to? It should point to the top directory in which you have the vunit, vhdl, examples directories and not to the vunit directory one level down. Regards, Lars From newsfish@newsfish Thu Aug 1 00:33:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: First steps using VUnit Date: Sun, 05 Jul 2015 11:03:35 +0200 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 5 Jul 2015 09:02:11 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="55b24bab51ed7fd1d5eadb079c167ef4"; logging-data="30670"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/3Cqz08QHa5nyyG9vsD9H0" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> Cancel-Lock: sha1:onqx3mgL5S0Spkx1ckYyKFyd5uo= Xref: news.eternal-september.org comp.lang.vhdl:3846 Am 05.07.2015 um 09:21 schrieb Lars Asplund: > Hi Tobias, > > What is your PYTHONPATH pointing to? It should point to the top directory in which you have the vunit, vhdl, examples directories and not to the vunit directory one level down. > > Regards, > > Lars > Hey Lars, thanks a lot, it is working now. I tried everything except your solution. Maybe you can add this information to the user_guide.md, then it's clear for Python noobs how to get VUnit starting. Best regards, Tobias From newsfish@newsfish Thu Aug 1 00:33:50 2024 X-Received: by 10.52.114.37 with SMTP id jd5mr2598789vdb.2.1436099642368; Sun, 05 Jul 2015 05:34:02 -0700 (PDT) X-Received: by 10.140.106.247 with SMTP id e110mr402629qgf.7.1436099642308; Sun, 05 Jul 2015 05:34:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m107no255801qgd.1!news-out.google.com!w15ni22819qge.0!nntp.google.com!m107no255796qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Jul 2015 05:34:02 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: First steps using VUnit From: Lars Asplund Injection-Date: Sun, 05 Jul 2015 12:34:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1686 X-Received-Body-CRC: 2213371889 Xref: news.eternal-september.org comp.lang.vhdl:3847 Hi Tobias, I made an addition to the user guide to make this clear. Thanks for pointin= g that out. Don't hesitate to get back with more questions if you have trou= ble with Python. Most VHDL developers have no Python experience so it's imp= ortant that our documentation covers the basics to get started. Once you're= up and running you really don't need that much Python skills. Making basic= run scripts is a copy/paste exercise from the given examples. Best Regards, Lars From newsfish@newsfish Thu Aug 1 00:33:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: First steps using VUnit Date: Mon, 6 Jul 2015 10:28:06 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 6 Jul 2015 08:25:48 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f6d85d2002bb0fd91efb8c1e7e8d917a"; logging-data="7143"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++LyALhAeUIyaMPdlXawmD" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1 In-Reply-To: Cancel-Lock: sha1:UGlxffPo8fgftiXHFkv6huON0Ss= Xref: news.eternal-september.org comp.lang.vhdl:3848 Am 05.07.2015 um 14:34 schrieb Lars Asplund: > Hi Tobias, > > I made an addition to the user guide to make this clear. Thanks for pointing that out. Don't hesitate to get back with more questions if you have trouble with Python. Most VHDL developers have no Python experience so it's important that our documentation covers the basics to get started. Once you're up and running you really don't need that much Python skills. Making basic run scripts is a copy/paste exercise from the given examples. > > Best Regards, > Lars > Hi Lars, thanks a lot for updating the user guide. I think it contains every information which is needed to get a first example running. Now I'm at the point where I have a Jenkins Server which run the VUnit regression tests on every commit. After the run I can see the JUnit reports, so I think the beginning is done. The next step will be to run a multiple regression test of a huge design. I also saw on the Github page, that there is a discussion how VUnit can be integrated better into Sigasi. When this also works smoothly, I will setup a CI server in our firm. Best regards, Tobias From newsfish@newsfish Thu Aug 1 00:33:51 2024 X-Received: by 10.182.186.67 with SMTP id fi3mr69131721obc.49.1436188721218; Mon, 06 Jul 2015 06:18:41 -0700 (PDT) X-Received: by 10.140.35.170 with SMTP id n39mr167554qgn.0.1436188721179; Mon, 06 Jul 2015 06:18:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!wf20no645079igc.0!news-out.google.com!4ni66258qgh.1!nntp.google.com!w90no947923qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 6 Jul 2015 06:18:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.138.132.22; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 79.138.132.22 References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> Subject: Re: First steps using VUnit From: Lars Asplund Injection-Date: Mon, 06 Jul 2015 13:18:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3849 Hi Tobias, Seems like you have very good progress! You say that you have a huge design to test. Does this means that test time= is an issue for you? You might have seen the -p option that allow you to r= un test cases in parallel on several cores. There are also discussions with= other VUnit users to do load balancing between slaves using Jenkins plugin= s. Btw, do you have ideas for what you want from a Sigasi integration? If so, = please join the discussion here https://github.com/LarsAsplund/vunit/issues= /18. Best Regards,=20 Lars From newsfish@newsfish Thu Aug 1 00:33:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Mon, 06 Jul 2015 09:27:06 -0400 Organization: Alacron, Inc. Lines: 56 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> <5597d5ca$0$1586$c3e8da3$5496439d@news.astraweb.com> <5598186b$0$1674$c3e8da3$5496439d@news.astraweb.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 6 Jul 2015 13:27:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="5668"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/YFL0AlS/UmaFZBtmp6qYofL3woHewRbc=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <5598186b$0$1674$c3e8da3$5496439d@news.astraweb.com> Cancel-Lock: sha1:a42CRP4F5LACbIjnp7aRy5FExpM= Xref: news.eternal-september.org comp.lang.vhdl:3850 Allan Herriman wrote: > On Sat, 04 Jul 2015 12:47:07 +0000, Allan Herriman wrote: > >> On Thu, 02 Jul 2015 16:25:53 -0400, GaborSzakacs wrote: >> >>> On the other hand, I have to wonder why you need this functionality on >>> an older Spartan 3 part. All the newer Xilinx series including Spartan >>> 3A DSP have a serial number ("Device DNA") built in to provide a >>> reliable mechanism to lock a design to a particular part. >> From Virtex 7 onwards, Xilinx Device DNA is not guaranteed to be unique >> - >> up to 32 devices can have the same serial number (Reference: UG470). >> Presumably this came from a desire to improve yield and reduce costs, >> rather than from a desire to make it completely useless to designers. >> >> I believe the older devices (up to and including V6) are still safe. > > > Correction (after I re-read some documentation): > > > The Spartan 3A devices have a 57 bit number, a 55 bits slice of which is > guaranteed to be unique. (Reference: UG332) > > > The Xilinx V6 devices have a 64 bit number that is *not* guaranteed to be > unique, and can be read out over JTAG. A 57 bit slice of the 64 bit > number (also not guaranteed to be unique) can be read out inside the > FPGA. The remaining 7 bits are described as "reserved". (Reference: > UG360) > > > The Xilinx V7 devices have a 64 bit number that is unique, and can be > read out over JTAG. A 57 bit slice of the 64 bit number can be read out > inside the FPGA. That 57 bit slice is *not* guaranteed to be unique. > (Reference: UG470) > > > Xilinx Ultrascale (and presumably Ultrascale Plus) devices have a longer > (96 bit) sequence that is unique, and all 96 bits can be read out inside > the FPGA. (Reference: UG570) > > > BTW, they use efuse technology, and are programmed at the factory. The > Spartan 3A ones are guaranteed for 10 years or 30 million read cycles. > > Regards, > Allan Spartan 6 and I believe V6 also have a limit on read cycles. This was fixed for 7-series parts. It's actually quite easy to run into the read cycle limit if you are not careful and make code that reads it continuously rather than just once after configuration. -- Gabor From newsfish@newsfish Thu Aug 1 00:33:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: First steps using VUnit Date: Mon, 6 Jul 2015 17:00:07 +0200 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 6 Jul 2015 14:57:50 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f6d85d2002bb0fd91efb8c1e7e8d917a"; logging-data="29990"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18u5nYv8qs/So6No1Q1i2yW" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1 In-Reply-To: <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> Cancel-Lock: sha1:5UBkuLUObdYDD94PsOhUc3NdLhs= Xref: news.eternal-september.org comp.lang.vhdl:3851 Hi Lars, > Seems like you have very good progress! > Yes, I'm a bit suprised that everything went so fast ;) > You say that you have a huge design to test. Does this means that test time is an issue for you? You might have seen the -p option that allow you to run test cases in parallel on several cores. There are also discussions with other VUnit users to do load balancing between slaves using Jenkins plugins. Yes test time is absolutly an issue, but this depends on my IPs. These are mainly for video algorithm and thereore I have to simulate a complete frame, which can't parallelize effectivly. But I can try to run the same IP using different regression setups in parallel. I have to find out if this is possible with my Modelsim license. If I remember correctly there can only run one Modelsim instance at the same time. > Btw, do you have ideas for what you want from a Sigasi integration? If so, please join the discussion here https://github.com/LarsAsplund/vunit/issues/18. I think what Phillipe mentioned is the right way. For me as Sigasi user, this means I would have to drag the VUnit folder into eclipse, right-click on the needed VHDL source files (i.e. vunit/vhdl/200x) and set them as library vunit_lib. Two clicks and VUnit is ready to use with Sigasi. Now I have to choose the correct VUnit files for "linking" in the right library, which is pretty annoying. Maybe when I'm a bit more in this topic I can give you some suggestions for improvements. The guys from Sigasi seem to me also very interested in improving their software. The fusion of both can lead to an easy to use regression suite without limitations in complexity. Best regards, Tobias From newsfish@newsfish Thu Aug 1 00:33:51 2024 X-Received: by 10.66.246.193 with SMTP id xy1mr4036643pac.44.1436258345180; Tue, 07 Jul 2015 01:39:05 -0700 (PDT) X-Received: by 10.140.47.68 with SMTP id l62mr35941qga.42.1436258345135; Tue, 07 Jul 2015 01:39:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!wf20no1210799igc.0!news-out.google.com!4ni73753qgh.1!nntp.google.com!w90no1255697qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Jul 2015 01:39:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.138.134.188; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 79.138.134.188 References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: First steps using VUnit From: Lars Asplund Injection-Date: Tue, 07 Jul 2015 08:39:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2876 X-Received-Body-CRC: 1203559508 Xref: news.eternal-september.org comp.lang.vhdl:3852 Den m=E5ndag 6 juli 2015 kl. 16:59:17 UTC+2 skrev Tobias Baumann: > Hi Lars, >=20 > > Seems like you have very good progress! > > >=20 > Yes, I'm a bit suprised that everything went so fast ;) >=20 > > You say that you have a huge design to test. Does this means that test = time is an issue for you? You might have seen the -p option that allow you = to run test cases in parallel on several cores. There are also discussions = with other VUnit users to do load balancing between slaves using Jenkins pl= ugins. >=20 > Yes test time is absolutly an issue, but this depends on my IPs. These=20 > are mainly for video algorithm and thereore I have to simulate a=20 > complete frame, which can't parallelize effectivly. But I can try to run= =20 > the same IP using different regression setups in parallel. I have to=20 > find out if this is possible with my Modelsim license. If I remember=20 > correctly there can only run one Modelsim instance at the same=20 Running in parallel with different setups is a good idea. Once you have tha= t you can ask yourself if all these tests need to run with the full frame s= ize. You can also select to run a subset of the tests on every commit and t= hen let the rest run over night. As you might have seen we also support GHDL to avoid that licence problem. = We've had good support from the GHDL to make this happen. The updated versi= on is yet to be released as a binary so you need to build from source. Best Regards,=20 Lars From newsfish@newsfish Thu Aug 1 00:33:52 2024 X-Received: by 10.66.190.41 with SMTP id gn9mr5392222pac.2.1436280606863; Tue, 07 Jul 2015 07:50:06 -0700 (PDT) X-Received: by 10.140.102.66 with SMTP id v60mr60351qge.19.1436280606776; Tue, 07 Jul 2015 07:50:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.glorb.com!wf20no1472880igc.0!news-out.google.com!4ni76218qgh.1!nntp.google.com!m107no1053412qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Jul 2015 07:50:06 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.150.32.12; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 83.150.32.12 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Subject: Register map auto-generation From: Leonardo Capossio Injection-Date: Tue, 07 Jul 2015 14:50:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3853 Hello, I wonder if anyone knows an open-source processor or a generic progr= am that will generate a register map for a given embedded processor (Z80-co= py or OpenRisc or similar) and architecture in both VHDL and C (header file= s or library files with addresses) ? From newsfish@newsfish Thu Aug 1 00:33:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!81.171.118.61.MISMATCH!peer01.fr7!news.highwinds-media.com!post01.fr7!fx11.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Register map auto-generation References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> In-Reply-To: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150707-0, 07/07/2015), Outbound message X-Antivirus-Status: Clean Lines: 18 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1436285817 86.17.210.161 (Tue, 07 Jul 2015 16:16:57 UTC) NNTP-Posting-Date: Tue, 07 Jul 2015 16:16:57 UTC Organization: virginmedia.com Date: Tue, 07 Jul 2015 17:16:55 +0100 X-Received-Body-CRC: 2110237940 X-Received-Bytes: 1722 Xref: news.eternal-september.org comp.lang.vhdl:3854 On 07/07/2015 15:50, Leonardo Capossio wrote: > Hello, I wonder if anyone knows an open-source processor or a generic program that will generate a register map for a given embedded processor (Z80-copy or OpenRisc or similar) and architecture in both VHDL and C (header files or library files with addresses) ? > Not 100% sure what you are after but if you want to generate RTL and associated c files from some register specifications then have a look at IDesignSpec, you can download a free version from cnet, http://download.cnet.com/IDesignSpec-for-Word-2007-2010/3000-20418_4-75728342.html There might be later versions available on the Agnisys website, Good luck, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:33:52 2024 X-Received: by 10.13.254.131 with SMTP id o125mr12899186ywf.56.1436366968658; Wed, 08 Jul 2015 07:49:28 -0700 (PDT) X-Received: by 10.140.38.180 with SMTP id t49mr156816qgt.9.1436366968601; Wed, 08 Jul 2015 07:49:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!w90no1729707qge.0!news-out.google.com!4ni79758qgh.1!nntp.google.com!w90no1729702qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 8 Jul 2015 07:49:28 -0700 (PDT) In-Reply-To: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Register map auto-generation From: Chris Higgs Injection-Date: Wed, 08 Jul 2015 14:49:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 8 Xref: news.eternal-september.org comp.lang.vhdl:3855 On Tuesday, 7 July 2015 15:50:09 UTC+1, Leonardo Capossio wrote: > Hello, I wonder if anyone knows an open-source processor or a generic pro= gram that will generate a register map for a given embedded processor (Z80-= copy or OpenRisc or similar) and architecture in both VHDL and C (header fi= les or library files with addresses)? Do you already have the registers defined in machine readable format? You could take a look at AirHDL from Guy Eschemann: http://airhdl.com/ From newsfish@newsfish Thu Aug 1 00:33:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.freenet.ag!feeder2.ecngs.de!ecngs!feeder.ecngs.de!81.171.118.61.MISMATCH!peer01.fr7!news.highwinds-media.com!post01.fr7!fx16.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Register map auto-generation References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-Antivirus: avast! (VPS 150708-0, 08/07/2015), Outbound message X-Antivirus-Status: Clean Lines: 27 Message-ID: <3rcnx.21161$wM2.3993@fx16.am4> NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1436373823 86.17.210.161 (Wed, 08 Jul 2015 16:43:43 UTC) NNTP-Posting-Date: Wed, 08 Jul 2015 16:43:43 UTC Organization: virginmedia.com Date: Wed, 08 Jul 2015 17:43:41 +0100 X-Received-Body-CRC: 3765655758 X-Received-Bytes: 2295 Xref: news.eternal-september.org comp.lang.vhdl:3856 On 08/07/2015 15:49, Chris Higgs wrote: > On Tuesday, 7 July 2015 15:50:09 UTC+1, Leonardo Capossio wrote: >> Hello, I wonder if anyone knows an open-source processor or a generic program that will generate a register map for a given embedded processor (Z80-copy or OpenRisc or similar) and architecture in both VHDL and C (header files or library files with addresses)? > > Do you already have the registers defined in machine readable format? > > You could take a look at AirHDL from Guy Eschemann: http://airhdl.com/ > Hi Chris, Looks like an interesting tool although the usage terms seems a bit harsh: In these terms and conditions, your user content means material (including without limitation text, images, audio material, video material and audio-visual material) that you submit to this website, for whatever purpose. You grant to airhdl.com a worldwide, irrevocable, non-exclusive, royalty-free license to use, reproduce, adapt, publish, translate and distribute your user content in any existing or future media. You also grant to airhdl.com the right to sub-license these rights, and the right to bring an action for infringement of these rights. Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:33:53 2024 X-Received: by 10.70.35.34 with SMTP id e2mr18738958pdj.6.1436438206917; Thu, 09 Jul 2015 03:36:46 -0700 (PDT) X-Received: by 10.140.99.44 with SMTP id p41mr227065qge.3.1436438206659; Thu, 09 Jul 2015 03:36:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i4no328690ige.0!news-out.google.com!w15ni32278qge.0!nntp.google.com!m107no1577610qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Jul 2015 03:36:46 -0700 (PDT) In-Reply-To: <3rcnx.21161$wM2.3993@fx16.am4> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> <3rcnx.21161$wM2.3993@fx16.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Register map auto-generation From: Chris Higgs Injection-Date: Thu, 09 Jul 2015 10:36:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 12 Xref: news.eternal-september.org comp.lang.vhdl:3857 Greetings Hans! On Wednesday, 8 July 2015 17:43:46 UTC+1, HT-Lab wrote: > > Looks like an interesting tool although the usage terms seems a bit harsh I don't use AirHDL in anger as we have internal tools for that purpose, however I am enjoying the gradual acceptance of hosted tools. I agree that the privacy policy is off-putting. It appears that they're generated from some standard template[1] which may not be ideally suited to this use case. I've CC'd Guy, perhaps he can comment. [1] http://www.privacypolicyonline.com From newsfish@newsfish Thu Aug 1 00:33:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Carry Save Adder (CSA) Verilog code Date: Thu, 9 Jul 2015 17:47:46 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 10 Message-ID: References: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3858 Irhamish wrote: > need 3 to 2 compresser..!! with figures Carry save adders are just ordinary full adders. It is how you wire them up that matters. I would put a full adder in a module, oops, entity, and then reference that the appropriate number of times. -- glen From newsfish@newsfish Thu Aug 1 00:33:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: WORK Date: Thu, 9 Jul 2015 17:52:53 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 14 Message-ID: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3859 I don't understand the use of WORK in VHDL. I have a large module, well entity in VHDL, that references many other entities without any problem. But then I wanted one of those to reference an entity, and got errors from Xilinx ISE. The fix seems to be to put WORK. in front of the entity name. Am I supposed to put WORK. in front of all the entity refernces? I am more used to verilog, but structural VHDL isn't all that different from structural verilog, if you change a few words. -- glen From newsfish@newsfish Thu Aug 1 00:33:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Thu, 9 Jul 2015 17:58:52 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 29 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3860 fl wrote: > On Saturday, May 23, 2015 at 8:20:47 PM UTC-7, rickman wrote: (snip) >> I have always found block diagrams to be my friend and to help me >> understand all the relationships between modules. An FFT is actually >> easy to implement once you understand how they work. They often need >> pipelining to make them run fast. I have never found pipelining of a >> linear flow to be difficult. Do you have feedback paths that make your >> design more complex? What else are you using other than FFTs? > Thanks, Rick. I can imagine it could be more difficult when there is > feedback for a high speed module. FFT has a simple, regular structure. > For me, I am still in the phase of FFT. I know FFT and its coding in C, > even in assembly code. I do not have time to finish a VHDL FFT yet. > The main difficulties are about the memory addressing, twiddle coef > selection etc. > Yes, I need to be patient to work on these interconnect between memory, > twiddle and multipliers. My favorite use for FPGAs is systolic array processors. I think you can make a systolic array for FFT, but haven't actually tried to do it. Once you figure it out, they are easy to write and debug. -- glen From newsfish@newsfish Thu Aug 1 00:33:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Thu, 09 Jul 2015 14:05:09 -0400 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 Jul 2015 18:05:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="17683"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wL/N8SEzCUFqYJ7y9LVHv" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:cPWF2pWuAyTcpSfT+FOm/IEgTeY= Xref: news.eternal-september.org comp.lang.vhdl:3862 On 7/9/2015 1:58 PM, glen herrmannsfeldt wrote: > fl wrote: >> On Saturday, May 23, 2015 at 8:20:47 PM UTC-7, rickman wrote: > > (snip) >>> I have always found block diagrams to be my friend and to help me >>> understand all the relationships between modules. An FFT is actually >>> easy to implement once you understand how they work. They often need >>> pipelining to make them run fast. I have never found pipelining of a >>> linear flow to be difficult. Do you have feedback paths that make your >>> design more complex? What else are you using other than FFTs? > >> Thanks, Rick. I can imagine it could be more difficult when there is >> feedback for a high speed module. FFT has a simple, regular structure. >> For me, I am still in the phase of FFT. I know FFT and its coding in C, >> even in assembly code. I do not have time to finish a VHDL FFT yet. >> The main difficulties are about the memory addressing, twiddle coef >> selection etc. >> Yes, I need to be patient to work on these interconnect between memory, >> twiddle and multipliers. > > My favorite use for FPGAs is systolic array processors. > > I think you can make a systolic array for FFT, but haven't > actually tried to do it. > > Once you figure it out, they are easy to write and debug. > > -- glen A systolic array is useful when you have a *lot* of work to be done and it can be broken into units that allow the data to flow through the processors. I'm probably not doing justice to the "proper" definition. I think this type of design is not very common and is rather specialized. What applications have you found that utilized systolic processing? -- Rick From newsfish@newsfish Thu Aug 1 00:33:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: WORK Date: Thu, 09 Jul 2015 14:19:53 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 Jul 2015 18:18:33 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="17683"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+yXv21WMTkjFw/ZfXNpKMc" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:qbpCQLX1sVk9BBe1QMpl7XjVI/o= Xref: news.eternal-september.org comp.lang.vhdl:3863 On 7/9/2015 1:52 PM, glen herrmannsfeldt wrote: > I don't understand the use of WORK in VHDL. > > I have a large module, well entity in VHDL, that references > many other entities without any problem. But then I wanted > one of those to reference an entity, and got errors from Xilinx ISE. > > The fix seems to be to put WORK. in front of the entity name. > > Am I supposed to put WORK. in front of all the entity refernces? > > I am more used to verilog, but structural VHDL isn't all that > different from structural verilog, if you change a few words. Work is the default working directory of the tools where all the code that is not specifically assigned to a library/package resides. I won't say I am overly familiar with all the details of using libraries. I often just mess with stuff until it works. But I don't recall ever having to add "work" to the name of an entity for the tools to find it. Perhaps you have tweaked something that changed the default? -- Rick From newsfish@newsfish Thu Aug 1 00:33:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: WORK Date: Thu, 09 Jul 2015 14:30:32 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 Jul 2015 18:29:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22857"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/vNpX/XQntixi8hEbktcXn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:ipXEBjZxxAmhyVfJpCqBw49bnTo= Xref: news.eternal-september.org comp.lang.vhdl:3864 On 7/9/2015 2:19 PM, rickman wrote: > On 7/9/2015 1:52 PM, glen herrmannsfeldt wrote: >> I don't understand the use of WORK in VHDL. >> >> I have a large module, well entity in VHDL, that references >> many other entities without any problem. But then I wanted >> one of those to reference an entity, and got errors from Xilinx ISE. >> >> The fix seems to be to put WORK. in front of the entity name. >> >> Am I supposed to put WORK. in front of all the entity refernces? >> >> I am more used to verilog, but structural VHDL isn't all that >> different from structural verilog, if you change a few words. > > Work is the default working directory of the tools where all the code > that is not specifically assigned to a library/package resides. I won't > say I am overly familiar with all the details of using libraries. I > often just mess with stuff until it works. But I don't recall ever > having to add "work" to the name of an entity for the tools to find it. > Perhaps you have tweaked something that changed the default? BTW, is this a Maynard G Krebs thread? WORK!!?? -- Rick From newsfish@newsfish Thu Aug 1 00:33:55 2024 X-Received: by 10.66.121.79 with SMTP id li15mr21239589pab.12.1436466837654; Thu, 09 Jul 2015 11:33:57 -0700 (PDT) X-Received: by 10.50.23.71 with SMTP id k7mr476613igf.6.1436466837620; Thu, 09 Jul 2015 11:33:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.glorb.com!qs7no3145889igc.0!news-out.google.com!t2ni5579igk.0!nntp.google.com!qs7no3145879igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Jul 2015 11:33:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <60e03e31-1ef5-45d9-a327-7e89f8b884ca@googlegroups.com> Subject: Re: WORK From: KJ Injection-Date: Thu, 09 Jul 2015 18:33:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3865 On Thursday, July 9, 2015 at 1:52:57 PM UTC-4, glen herrmannsfeldt wrote: > I don't understand the use of WORK in VHDL. > > I have a large module, well entity in VHDL, that references > many other entities without any problem. But then I wanted > one of those to reference an entity, and got errors from Xilinx ISE. > > The fix seems to be to put WORK. in front of the entity name. > > Am I supposed to put WORK. in front of all the entity refernces? > Yes. To instantiate entity xyz directly you would type: My_Thingy : entity work.xyz port map(...); The other way is to define a component in which case you would instantiate the component this way: My_Thingy : xyz port map(...); But creating a component is busy work that can lead to other problems. Better to use the direct entity instantiation as shown in the first example. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:33:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: WORK Date: Thu, 9 Jul 2015 20:44:58 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 45 Message-ID: References: <60e03e31-1ef5-45d9-a327-7e89f8b884ca@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3866 KJ wrote: > On Thursday, July 9, 2015 at 1:52:57 PM UTC-4, glen herrmannsfeldt wrote: >> I don't understand the use of WORK in VHDL. >> I have a large module, well entity in VHDL, that references >> many other entities without any problem. But then I wanted >> one of those to reference an entity, and got errors from Xilinx ISE. (snip) >> Am I supposed to put WORK. in front of all the entity refernces? > Yes. To instantiate entity xyz directly you would type: > My_Thingy : entity work.xyz port map(...); > The other way is to define a component in which case you would > instantiate the component this way: > My_Thingy : xyz port map(...); > But creating a component is busy work that can lead to other > problems. Better to use the direct entity instantiation as shown > in the first example. Yes, I first learned component, but quickly found out about entity and is so much easier. (Though I often put in a comment explaining the ports so I don't forget.) It seems to work for the first level without work. but not deeper. The Xilinx explanation compares it to Java's this, which you normally don't need to put in front of every variable and method reference. It sounds like work is supposed to be the default. It seems that Xilinx uses a different parser for Spartan 6, which is part of the explanation for why this recently came up. Can I say: library work; and get around needing it for each one? thanks, -- glen From newsfish@newsfish Thu Aug 1 00:33:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Thu, 9 Jul 2015 20:49:27 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 29 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3867 rickman wrote: (snip, I wrote) >> My favorite use for FPGAs is systolic array processors. >> I think you can make a systolic array for FFT, but haven't >> actually tried to do it. >> Once you figure it out, they are easy to write and debug. (snip) > A systolic array is useful when you have a *lot* of work to be done and > it can be broken into units that allow the data to flow through the > processors. I'm probably not doing justice to the "proper" definition. > I think this type of design is not very common and is rather > specialized. What applications have you found that utilized systolic > processing? I have used it for dynamic programming for DNA and protein sequence comparison. There are nice algorithms for computing alignment scores including insertions and deletions using dynamic programming. (The algorithm used by unix diff was first used for protein sequence comparison, and later for diff.) I believe that convolution and FIR filters also make nice systolic arrays, I am not so sure about IIR, though. -- glen From newsfish@newsfish Thu Aug 1 00:33:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Thu, 09 Jul 2015 17:44:40 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 Jul 2015 21:43:16 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="4747"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18d73/Di++Tmyh/lOkMdEi6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:tSJPyjoLHdbWUkLr8gOoqiR0s3g= Xref: news.eternal-september.org comp.lang.vhdl:3868 On 7/9/2015 4:49 PM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip, I wrote) >>> My favorite use for FPGAs is systolic array processors. > >>> I think you can make a systolic array for FFT, but haven't >>> actually tried to do it. > >>> Once you figure it out, they are easy to write and debug. > > (snip) >> A systolic array is useful when you have a *lot* of work to be done and >> it can be broken into units that allow the data to flow through the >> processors. I'm probably not doing justice to the "proper" definition. > >> I think this type of design is not very common and is rather >> specialized. What applications have you found that utilized systolic >> processing? > > I have used it for dynamic programming for DNA and protein > sequence comparison. There are nice algorithms for computing > alignment scores including insertions and deletions using > dynamic programming. (The algorithm used by unix diff was first > used for protein sequence comparison, and later for diff.) > > I believe that convolution and FIR filters also make nice systolic > arrays, I am not so sure about IIR, though. Yeah, I work on protein sequence comparison nearly every day.. lol Yes, I'd say that was a rather specialized application. Do they still use FPGAs for that or have they moved on to GPUs? I remember *many* years ago when the buzzword was "workstations". Not sure who it was, but I think someone at NIH was working on providing molecular interaction simulations using 3D joysticks with force feedback. I never heard if they continued the research. So I don't know if they had any problems with computing power or not. I am pretty sure it was not pursued enough to have a general solution and instead only simulated specific molecules that had been entered into the system. This could have used systolic processing at that time, but by now would be pretty easy on a GPU I am sure. -- Rick From newsfish@newsfish Thu Aug 1 00:33:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Fri, 10 Jul 2015 00:38:02 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 41 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3869 rickman wrote: (snip, I wrote) >> I have used it for dynamic programming for DNA and protein >> sequence comparison. There are nice algorithms for computing >> alignment scores including insertions and deletions using >> dynamic programming. (The algorithm used by unix diff was first >> used for protein sequence comparison, and later for diff.) >> I believe that convolution and FIR filters also make nice systolic >> arrays, I am not so sure about IIR, though. > Yeah, I work on protein sequence comparison nearly every day.. lol > Yes, I'd say that was a rather specialized application. > Do they still use FPGAs for that or have they moved on to GPUs? For the usual problems, it is fixed point add/subtract with a small number of bits. It is very efficient in an FPGA, and not so good in GPU. Sequencers some years ago could generate 1e9 base/day, and they might be much faster now. Dynamic programming is O(N**2) (which is pretty good when you include insertion and deletion), but that means 2e19 add/subtract per day to compare against one human genome. Eight bits, or maybe only five or six, is enough. But for HMM calculations, floating point is sometimes better. > I remember *many* years ago when the buzzword was "workstations". Not > sure who it was, but I think someone at NIH was working on providing > molecular interaction simulations using 3D joysticks with force > feedback. I never heard if they continued the research. So I don't > know if they had any problems with computing power or not. I am pretty > sure it was not pursued enough to have a general solution and instead > only simulated specific molecules that had been entered into the system. > This could have used systolic processing at that time, but by now > would be pretty easy on a GPU I am sure. -- glen From newsfish@newsfish Thu Aug 1 00:33:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: WORK Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 10 Jul 2015 10:57:07 GMT Lines: 80 Message-ID: <559fa503$0$2754$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: c56e0cd4.news.astraweb.com X-Trace: DXC=>P>[Q?5kHNhJRZZkg^aP1jL?0kYOcDh@jZD3?OaX:Skmh:BbU8OZ3Am I don't understand the use of WORK in VHDL. > > I have a large module, well entity in VHDL, that references many other > entities without any problem. But then I wanted one of those to > reference an entity, and got errors from Xilinx ISE. > > The fix seems to be to put WORK. in front of the entity name. > > Am I supposed to put WORK. in front of all the entity refernces? > > I am more used to verilog, but structural VHDL isn't all that different > from structural verilog, if you change a few words. >From a 2002 comp.lang.vhdl post of mine ... [In an entity instantiation] entity 'E' will need to be qualified in some way. I know of three ways: 1. library lib; -- not needed if 'lib' is work use lib.E; ... label : entity E generic map ( ... 2. library lib; -- not needed if 'lib' is work use lib.all; -- 'all' picks up E (and possibly other stuff) ... label : entity E generic map ( ... 3. library lib; -- not needed if 'lib' is work ... label : entity lib.E generic map ( ... All three methods should work in any 1993 (or later) compliant VHDL compiler. Method 3 is by far the most popular. Also, most designers only use one library, so the entity instantiation will typically look like: label : entity work.E generic map ( ... It's also possible to specify an architecture, e.g. label : entity lib.E(A) generic map ( ... would select architecture "A" of entity "E" in the library "lib". This is handy in testbenches if you want to instantiate two different architectures for the same entity, without needing to use a configuration. I rarely use component instantiations, but when I do, I include the (optional) component keyword to make them stand out in my source code, e.g. label : component E generic map ( ... Regards, Allan From newsfish@newsfish Thu Aug 1 00:33:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: WORK Newsgroups: comp.lang.vhdl References: <559fa503$0$2754$c3e8da3$76491128@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 10 Jul 2015 11:06:43 GMT Lines: 83 Message-ID: <559fa743$0$2754$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 67c9fe51.news.astraweb.com X-Trace: DXC==RUHg@438ceF1iA^=`ZUjbL?0kYOcDh@jZD3?OaX:Skmh:BbU8OZ3Am On Thu, 09 Jul 2015 17:52:53 +0000, glen herrmannsfeldt wrote: > >> I don't understand the use of WORK in VHDL. >> >> I have a large module, well entity in VHDL, that references many other >> entities without any problem. But then I wanted one of those to >> reference an entity, and got errors from Xilinx ISE. >> >> The fix seems to be to put WORK. in front of the entity name. >> >> Am I supposed to put WORK. in front of all the entity refernces? >> >> I am more used to verilog, but structural VHDL isn't all that different >> from structural verilog, if you change a few words. > > > > From a 2002 comp.lang.vhdl post of mine ... > > > [In an entity instantiation] entity 'E' will need to be qualified in > some way. I know of three ways: > > 1. > library lib; -- not needed if 'lib' is work use lib.E; > ... > label : entity E > generic map ( > ... > > 2. > library lib; -- not needed if 'lib' is work use lib.all; -- 'all' > picks up E (and possibly other stuff) > ... > label : entity E > generic map ( > ... > > 3. > library lib; -- not needed if 'lib' is work ... > label : entity lib.E > generic map ( > ... > > > All three methods should work in any 1993 (or later) compliant VHDL > compiler. Method 3 is by far the most popular. Also, most designers > only use one library, so the entity instantiation will typically look > like: > > label : entity work.E > generic map ( > ... > > > It's also possible to specify an architecture, e.g. > > label : entity lib.E(A) > generic map ( > ... > > would select architecture "A" of entity "E" in the library "lib". This > is handy in testbenches if you want to instantiate two different > architectures for the same entity, without needing to use a > configuration. > > > I rarely use component instantiations, but when I do, I include the > (optional) component keyword to make them stand out in my source code, > e.g. > > label : component E > generic map ( > ... > Pan's word wrap strikes again. Those use clauses were meant to be on new lines. Allan From newsfish@newsfish Thu Aug 1 00:33:57 2024 X-Received: by 10.66.237.2 with SMTP id uy2mr27591538pac.11.1436542717942; Fri, 10 Jul 2015 08:38:37 -0700 (PDT) X-Received: by 10.50.23.71 with SMTP id k7mr66384igf.6.1436542717907; Fri, 10 Jul 2015 08:38:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!qs7no3497521igc.0!news-out.google.com!a16ni14013ign.0!nntp.google.com!i4no649099ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Jul 2015 08:38:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.186; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.186 References: <60e03e31-1ef5-45d9-a327-7e89f8b884ca@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: WORK From: Jim Lewis Injection-Date: Fri, 10 Jul 2015 15:38:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 7 Xref: news.eternal-september.org comp.lang.vhdl:3872 One motivation to use component instantiation is they can be configured with a configuration declaration. In a testbench, this allows you to remove components from a simulation when they are not in use, and hence, do core level simulations using a chip level testbench. My goal is the reduction of the number of unique testbench frameworks I need to support. It is planned to revise configurations to allow the architecture of direct entity instances (the one you prefer without component declarations) to be configured, but it will take time to get it into the standard and then more time to get it in a simulator. Jim From newsfish@newsfish Thu Aug 1 00:33:58 2024 X-Received: by 10.182.24.70 with SMTP id s6mr27480334obf.42.1436551658192; Fri, 10 Jul 2015 11:07:38 -0700 (PDT) X-Received: by 10.140.101.22 with SMTP id t22mr328398qge.32.1436551658058; Fri, 10 Jul 2015 11:07:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!qs7no3550608igc.0!news-out.google.com!w15ni32387qge.0!nntp.google.com!z61no154512qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Jul 2015 11:07:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <60e03e31-1ef5-45d9-a327-7e89f8b884ca@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: WORK From: Andy Injection-Date: Fri, 10 Jul 2015 18:07:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3873 There are additional options for "configuring" entities without using compo= nents using 93 - 2008 versions of VHDL. They all require that the entity in= stantiation in the design code NOT specify the architecture (optional, in p= arentheses after the entity name). When elaborated, if no architecture is specified in the entity instantiatio= n, the most recently analyzed architecture for the entity will be used. Thu= s, if for simulation, you analyze (compiled) a new architecture for an enti= ty, AFTER the original architecture is analyzed, the new architecture will = be used for the entity in the simulation.=20 Such an architecture may be completely different (empty/benign/broken, gate= level, behavioral, etc.) than the original architecture. Such an architecture can also re-instantiate the entity with the original a= rchitecture by specifying the original architecture with its entity instant= iation. I call this a "wrapper" architecture. A wrapper architecture can ef= fectively alter the generic map, assert conditions on intefaces and even mo= dify interface behavior (such as forcing output data to X when the valid si= gnal is not asserted). A wrapper architecture can also conditionally do the= se things based on a generic value, using if-generate statements as needed. In practice such "configurations" are managed through compile scripts rathe= r than a configuration unit. Sometimes it is easier to just bite the bullet= and use configurations & components, but for limited cases, it is easier t= o manage the compile scripts. Or, just wait until vhdl 201x. BTW, "work" provides a library-name-independent method of specifying that a= needed resource can be found in the same library which contains the refere= ncing unit. This provides independence from the name of the library. This a= llows, among other ways, the same library code to be compiled into differen= t libraries, with different names, and referenced separately for different/= duplicate purposes. Imagine a design that uses a package do declare a bunch= of "global" signals, but you want to run a simulation that includes more t= han one copy of the design, but those global signals can't be shared betwee= n both copies. Compile one copy of the design into one library, and another= copy into another library, and their "global" signals will be local to eac= h design copy. Andy From newsfish@newsfish Thu Aug 1 00:33:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: ROM, how? Date: Sat, 11 Jul 2015 13:27:16 +0300 Organization: Aioe.org NNTP Server Lines: 5 Message-ID: NNTP-Posting-Host: HIL1RaQAV9ekVSPTby4cHg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1 X-Notice: Filtered by postfilter v. 0.8.2 X-Mozilla-News-Host: news://nntp.aioe.org:119 Xref: news.eternal-september.org comp.lang.vhdl:3874 Hello: how to instantiate a ROM with its content in a test-bench? thanks From newsfish@newsfish Thu Aug 1 00:33:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: ROM, how? Date: Sat, 11 Jul 2015 23:50:29 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 36 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3875 Maurice SAAB wrote: > how to instantiate a ROM with its content in a test-bench? I don't know about test bench, but I do ROM with a constant array: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- for the unsigned type entity i3601 is port ( Q : out std_logic_vector(3 downto 0); A : in std_logic_vector(7 downto 0); CS1, CS2 : in std_logic); end entity i3601; architecture i3601 of i3601 is type ROM is array(0 to 255) of std_logic_vector(3 downto 0); constant ROM1: ROM := ( X"1", X"2", X"3", OTHERS => X"0"); begin Q <= ROM1(to_integer(unsigned(A))) when (CS1 or CS2)='0' else X"F"; end architecture i3601; Having the OTHERS => X"0" at the end, even if you fill the whole array, allows the last element to have a trailing comma. C allows array initialization to have a trailing comma, but not VDHL. For some reason that I don't know, you have to use type. Just declaring a constant of the appropriate type doesn't work. -- glen From newsfish@newsfish Thu Aug 1 00:33:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: IN and OUT of the same entity? Date: Sat, 11 Jul 2015 23:58:34 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 22 Message-ID: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3876 I have a design that gets errors from Xilinx ISE, which looks fine to me. It connects IN and OUT ports together: signal y105: std_logic; a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, y105, open, OUTON, vcc, OUTON, vcc, y108e); The first y105 is an IN to N109, the second is OUT. ISE says: "Line 531: Formal has no actual or default value." and is the port of the first y105. There is a similar error when another instantiation also uses IN and OUT ports, but not exactly the same way. It seems to me a strange restriction. Is it supposed to do that? -- glen From newsfish@newsfish Thu Aug 1 00:33:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sat, 11 Jul 2015 20:23:15 -0400 Organization: A noiseless patient Spider Lines: 31 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 12 Jul 2015 00:21:49 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="23812"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190dWyaUUSIW14HpKtQbapp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:CkSHNfdJGjJ/aXZgVPABeExLaIU= Xref: news.eternal-september.org comp.lang.vhdl:3877 On 7/11/2015 7:58 PM, glen herrmannsfeldt wrote: > I have a design that gets errors from Xilinx ISE, which looks > fine to me. It connects IN and OUT ports together: > > signal y105: std_logic; > > a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, > y105, open, OUTON, vcc, OUTON, vcc, y108e); > > > The first y105 is an IN to N109, the second is OUT. > > ISE says: "Line 531: Formal has no actual or default value." > > and is the port of the first y105. > > There is a similar error when another instantiation also uses > IN and OUT ports, but not exactly the same way. > > It seems to me a strange restriction. Is it supposed to do that? I think that depends on what you have inside the entity. Do you have the same connection inside? lol just kidding I'm not clear on what you are coding. Is this an entity declaration? I see the entity keyword, but this is not the syntax for an entity declaration. Is this something I missed in VHDL 2008? -- Rick From newsfish@newsfish Thu Aug 1 00:33:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 03:30:14 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 21 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3878 glen herrmannsfeldt wrote: > I have a design that gets errors from Xilinx ISE, which looks > fine to me. It connects IN and OUT ports together: > a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, > y105, open, OUTON, vcc, OUTON, vcc, y108e); > The first y105 is an IN to N109, the second is OUT. > ISE says: "Line 531: Formal has no actual or default value." OK, maybe this was obvious to everyone else, but the file is pretty big and I didn't notice. I forgot to say "port map". I have no idea what it thinks it does, but it complains about the third signal, j1. No obvious message like "you idiot, you forgot to say PORT MAP:. thanks, all. -- glen From newsfish@newsfish Thu Aug 1 00:34:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 02:03:03 -0400 Organization: A noiseless patient Spider Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 12 Jul 2015 06:01:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="4630"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Ev/ApYVvX/qzfprZaO6K5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:mMzj4RqPRzECxKprJLk0kAmLXYo= Xref: news.eternal-september.org comp.lang.vhdl:3879 On 7/11/2015 11:30 PM, glen herrmannsfeldt wrote: > glen herrmannsfeldt wrote: >> I have a design that gets errors from Xilinx ISE, which looks >> fine to me. It connects IN and OUT ports together: > >> a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, >> y105, open, OUTON, vcc, OUTON, vcc, y108e); > >> The first y105 is an IN to N109, the second is OUT. > >> ISE says: "Line 531: Formal has no actual or default value." > > OK, maybe this was obvious to everyone else, but the file is > pretty big and I didn't notice. I forgot to say "port map". > > I have no idea what it thinks it does, but it complains about > the third signal, j1. No obvious message like "you idiot, you forgot > to say PORT MAP:. > > thanks, all. Lol, I thought it was messed up but I didn't want to assume I was right and you were wrong. It has been well over a year since I've written any VHDL and maybe a lot longer than that. Glad you figured it out. Compilers can be pretty retarded about reporting what is really wrong. I'm still not clear on the entity part. The keyword "entity" needs to be removed too, right? You are using positional association in your association list. I always use named association. It is more to type, but prevents some types of hard to find mistakes and might help the tools report better error messages. It is not hard to use an editor macro to create the named association list for a component instantiation and some tools will create it for you. I make it from the port declaration of the entity. That is one of the "issues" of VHDL... the excessive typing.... or do I want to say incessant as in, "I can't take the incessant beating of the jungle drums!" or in this case, "I can't take the incessant typing of the Smith Corona!" -- Rick From newsfish@newsfish Thu Aug 1 00:34:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 09:17:41 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 59 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3880 rickman wrote: (snip, I wrote) >>> a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, >>> y105, open, OUTON, vcc, OUTON, vcc, y108e); (snip, then I wrote) >> OK, maybe this was obvious to everyone else, but the file is >> pretty big and I didn't notice. I forgot to say "port map". (snip) > Lol, I thought it was messed up but I didn't want to assume I was right > and you were wrong. It has been well over a year since I've written any > VHDL and maybe a lot longer than that. Glad you figured it out. > Compilers can be pretty retarded about reporting what is really wrong. I am more used to verilog, but if I put the VHDL words in the right place, it mostly works. I mostly write structural verilog, and so now structural VHDL. > I'm still not clear on the entity part. The keyword "entity" > needs to be removed too, right? No, the word entity is right. I didn't completely figure it out, but there is component and entity, where entity has the keyword. > You are using positional association in your association list. I always > use named association. It is more to type, but prevents some types of > hard to find mistakes and might help the tools report better error > messages. It is not hard to use an editor macro to create the named > association list for a component instantiation and some tools will > create it for you. I make it from the port declaration of the entity. > That is one of the "issues" of VHDL... the excessive typing.... or do I > want to say incessant as in, "I can't take the incessant beating of the > jungle drums!" or in this case, "I can't take the incessant typing of > the Smith Corona!" The design is based on a TTL design, so the entities are TTL ICs. I thought about the other way, but in either case I need to go carefully through the design and verify the ports. There are a lot of 74109 and 74161, so once I figure out the order for each, I just have to verify them. The signal names are the original names, which often don't mean much to me. Sometiems I have to make a name, mostly for TTL gates. (I use entity for everything except simple gates, and the VHDL equivalent of continuous assignment for gates.) In most cases, I put the output ports first, then the input ports. The 74109 is a dual FF, so it is out then in for the first, and out then in for the second. -- glen From newsfish@newsfish Thu Aug 1 00:34:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 13:42:59 -0400 Organization: A noiseless patient Spider Lines: 94 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 12 Jul 2015 17:41:33 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="8364"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX189PveUQqkZ1FUNxVFWr4Pr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:iRHHQk0AVAZVnibCMBZlToelzPc= Xref: news.eternal-september.org comp.lang.vhdl:3881 On 7/12/2015 5:17 AM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip, I wrote) > >>>> a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, >>>> y105, open, OUTON, vcc, OUTON, vcc, y108e); > > (snip, then I wrote) >>> OK, maybe this was obvious to everyone else, but the file is >>> pretty big and I didn't notice. I forgot to say "port map". > > (snip) > >> Lol, I thought it was messed up but I didn't want to assume I was right >> and you were wrong. It has been well over a year since I've written any >> VHDL and maybe a lot longer than that. Glad you figured it out. >> Compilers can be pretty retarded about reporting what is really wrong. > > I am more used to verilog, but if I put the VHDL words in the > right place, it mostly works. > > I mostly write structural verilog, and so now structural VHDL. So why are you using VHDL instead of Verilog? I've wanted to learn Verilog for some time now, but when I am doing paid work I stick to what I know. I haven't done a "for fun" HDL project in a while so I haven't done much with Verilog. >> I'm still not clear on the entity part. The keyword "entity" >> needs to be removed too, right? > > No, the word entity is right. > > I didn't completely figure it out, but there is component and > entity, where entity has the keyword. "Entity" is used to define the parameter list of an entity. It seems I was unaware that it can also be used in a component instantiation when you wish to skip having a component declaration. A component declaration is like a function prototype in C, it defines the interface for local use. By adding the keyword "entity" to the component instantiation it eliminates the need for the component declaration. However, this is now called an "entity" instantiation and will not work with configurations... very complex... >> You are using positional association in your association list. I always >> use named association. It is more to type, but prevents some types of >> hard to find mistakes and might help the tools report better error >> messages. It is not hard to use an editor macro to create the named >> association list for a component instantiation and some tools will >> create it for you. I make it from the port declaration of the entity. >> That is one of the "issues" of VHDL... the excessive typing.... or do I >> want to say incessant as in, "I can't take the incessant beating of the >> jungle drums!" or in this case, "I can't take the incessant typing of >> the Smith Corona!" > > The design is based on a TTL design, so the entities are TTL ICs. Should I assume this means the parameters are in pin number order? Sounds like spice, but that doesn't make it good. You can still use named association. > I thought about the other way, but in either case I need to go > carefully through the design and verify the ports. There are a > lot of 74109 and 74161, so once I figure out the order for each, > I just have to verify them. The signal names are the original > names, which often don't mean much to me. Sometiems I have to > make a name, mostly for TTL gates. (I use entity for everything > except simple gates, and the VHDL equivalent of continuous > assignment for gates.) > > In most cases, I put the output ports first, then the input ports. > The 74109 is a dual FF, so it is out then in for the first, > and out then in for the second. If you use pin number based names for the TTL entities, you could use named association which would make the verification trivial, well, assuming you are copying this from a pin number oriented list of some sort. Otherwise, why use TTL devices? P01 => ralph, P02 => betty, ... You may be unpleasantly surprised at how easy it is to make a mistake using positional association. -- Rick From newsfish@newsfish Thu Aug 1 00:34:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 20:11:57 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 83 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3882 rickman wrote: (snip, I wrote) >> I am more used to verilog, but if I put the VHDL words in the >> right place, it mostly works. >> I mostly write structural verilog, and so now structural VHDL. > So why are you using VHDL instead of Verilog? I've wanted to learn > Verilog for some time now, but when I am doing paid work I stick to what > I know. I haven't done a "for fun" HDL project in a while so I haven't > done much with Verilog. It wasn't my choice. >>> I'm still not clear on the entity part. The keyword "entity" >>> needs to be removed too, right? >> No, the word entity is right. >> I didn't completely figure it out, but there is component and >> entity, where entity has the keyword. > "Entity" is used to define the parameter list of an entity. It seems I > was unaware that it can also be used in a component instantiation when > you wish to skip having a component declaration. A component > declaration is like a function prototype in C, it defines the interface > for local use. By adding the keyword "entity" to the component > instantiation it eliminates the need for the component declaration. > However, this is now called an "entity" instantiation and will not work > with configurations... very complex... I think that is the way I understand it. Since verilog doesn't require the declaration, I didn't think that VHDL should. Then I found out about entity and used that. I still have comments explaining the order, the way I want to read them. >>> You are using positional association in your association list. I always >>> use named association. It is more to type, but prevents some types of >>> hard to find mistakes and might help the tools report better error >>> messages. (snip) >> The design is based on a TTL design, so the entities are TTL ICs. > Should I assume this means the parameters are in pin number order? > Sounds like spice, but that doesn't make it good. You can still use > named association. No, they aren't in that order on the original. I choose the order that I like. (snip) >> In most cases, I put the output ports first, then the input ports. >> The 74109 is a dual FF, so it is out then in for the first, >> and out then in for the second. > If you use pin number based names for the TTL entities, you could use > named association which would make the verification trivial, well, > assuming you are copying this from a pin number oriented list of some > sort. Otherwise, why use TTL devices? > P01 => ralph, > P02 => betty, > ... > You may be unpleasantly surprised at how easy it is to make a mistake > using positional association. I have been doing Fortran and C programming for years, and I know that it can be a problem. But we live with it in those cases. (Fortran now allows for names, but most don't use them. But it didn't when I first started.) -- glen From newsfish@newsfish Thu Aug 1 00:34:01 2024 X-Received: by 10.50.25.233 with SMTP id f9mr13690665igg.8.1436737303229; Sun, 12 Jul 2015 14:41:43 -0700 (PDT) X-Received: by 10.50.62.10 with SMTP id u10mr1460igr.12.1436737303207; Sun, 12 Jul 2015 14:41:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!qs7no4370568igc.0!news-out.google.com!t2ni8559igk.0!nntp.google.com!qs7no4370563igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 12 Jul 2015 14:41:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.5.154.164; posting-account=8oCTNQoAAACLdX6nA43RerI2nCrfLpJE NNTP-Posting-Host: 185.5.154.164 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <898bd013-12a3-447e-89c5-e61e79bb245b@googlegroups.com> Subject: Re: How to instantiate a verilog block inside a VHDL entity? From: ABFAROUK Injection-Date: Sun, 12 Jul 2015 21:41:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3883 Instantiating a Verilog Module in a VHDL Design Unit In a mixed language design, you can instantiate a Verilog module in a VHDL design unit. To Instantiate a Verilog Module in a VHDL Design Unit Declare a VHDL component with the same name as the Verilog module (respecting case sensitivity) that you want to instantiate. For example, COMPONENT FD PORT ( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC ); END COMPONENT; Use named association to instantiate the Verilog module. For example, UUT : FD PORT MAP( Q => O, D => I, C => CLK); Since Verilog is case sensitive, named associations and the local port names that you use in the component declaration must match the case of the corresponding Verilog port names. On Monday, February 17, 2014 at 12:03:27 PM UTC+3, thunder wrote: > Hello > > > My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block. > > QS: Is it possible to instantiate a verilog block inside a VHDL block? > QS: If the answer to the above question is yes, how to achieve this? > > Thanks in advance > > JO From newsfish@newsfish Thu Aug 1 00:34:01 2024 X-Received: by 10.66.149.67 with SMTP id ty3mr17460198pab.24.1436738477614; Sun, 12 Jul 2015 15:01:17 -0700 (PDT) X-Received: by 10.140.94.166 with SMTP id g35mr439433qge.1.1436738477375; Sun, 12 Jul 2015 15:01:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!qs7no4375949igc.0!news-out.google.com!w15ni32550qge.0!nntp.google.com!e109no491964qge.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 12 Jul 2015 15:01:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.216.14.34; posting-account=8oCTNQoAAACLdX6nA43RerI2nCrfLpJE NNTP-Posting-Host: 37.216.14.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to instantiate a verilog block inside a VHDL entity? From: ABFAROUK Injection-Date: Sun, 12 Jul 2015 22:01:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3884 and on the conterary: Instantiating a VHDL Module in a Verilog Design Unit In a mixed language design, you can instantiate a VHDL module in a Vesign design unit. To Instantiate a VHDL Module in a Verilog Design Unit Instantiate the VHDL entity as if it were a Verilog module. For example, module testbench ; wire in, clk; wire out; FD FD1( .Q(Q_OUT), .C(CLK); .D(A); ); On Monday, February 17, 2014 at 12:03:27 PM UTC+3, thunder wrote: > Hello > > > My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block. > > QS: Is it possible to instantiate a verilog block inside a VHDL block? > QS: If the answer to the above question is yes, how to achieve this? > > Thanks in advance > > JO From newsfish@newsfish Thu Aug 1 00:34:01 2024 X-Received: by 10.182.219.225 with SMTP id pr1mr46661117obc.23.1436820199145; Mon, 13 Jul 2015 13:43:19 -0700 (PDT) X-Received: by 10.140.85.11 with SMTP id m11mr497451qgd.29.1436820199118; Mon, 13 Jul 2015 13:43:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!pg9no429180igb.0!news-out.google.com!4ni80201qgh.1!nntp.google.com!z61no744888qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 13 Jul 2015 13:43:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=181.168.151.94; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 181.168.151.94 References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Register map auto-generation From: Leonardo Capossio Injection-Date: Mon, 13 Jul 2015 20:43:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 22 Xref: news.eternal-september.org comp.lang.vhdl:3885 On Tuesday, July 7, 2015 at 1:17:00 PM UTC-3, HT-Lab wrote: > On 07/07/2015 15:50, Leonardo Capossio wrote: > > Hello, I wonder if anyone knows an open-source processor or a generic p= rogram that will generate a register map for a given embedded processor (Z8= 0-copy or OpenRisc or similar) and architecture in both VHDL and C (header = files or library files with addresses) ? > > >=20 > Not 100% sure what you are after but if you want to generate RTL and=20 > associated c files from some register specifications then have a look at= =20 > IDesignSpec, you can download a free version from cnet, >=20 > http://download.cnet.com/IDesignSpec-for-Word-2007-2010/3000-20418_4-7572= 8342.html >=20 > There might be later versions available on the Agnisys website, >=20 > Good luck, > Hans > www.ht-lab.com Thanks, I was looking for something like this. From newsfish@newsfish Thu Aug 1 00:34:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: Register map auto-generation Date: Tue, 14 Jul 2015 10:26:38 +0200 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 14 Jul 2015 08:23:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f6d85d2002bb0fd91efb8c1e7e8d917a"; logging-data="26931"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++gA9CXgyIWb9bnYJwwTPQ" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1 In-Reply-To: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Cancel-Lock: sha1:Pq6Vx0YXS+5GN9rdsBn/THHM8KM= Xref: news.eternal-september.org comp.lang.vhdl:3886 Am 07.07.2015 um 16:50 schrieb Leonardo Capossio: > Hello, I wonder if anyone knows an open-source processor or a generic program that will generate a register map for a given embedded processor (Z80-copy or OpenRisc or similar) and architecture in both VHDL and C (header files or library files with addresses) ? > Hi, here we have the same problem, but no tool satisfied our needs. So we designed something own on MySQL and PHP base, which can be imported directly into Excel Sheets via "MySQL for Excel". Redards, Tobias From newsfish@newsfish Thu Aug 1 00:34:02 2024 X-Received: by 10.129.81.201 with SMTP id f192mr37522415ywb.37.1437467539364; Tue, 21 Jul 2015 01:32:19 -0700 (PDT) X-Received: by 10.50.79.137 with SMTP id j9mr238255igx.15.1437467539335; Tue, 21 Jul 2015 01:32:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z61no2355424qge.0!news-out.google.com!a16ni24133ign.0!nntp.google.com!pg9no2655808igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jul 2015 01:32:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=118.70.129.184; posting-account=2xiWIAoAAAARmmv1zwxT-I9-ZqoxLA0D NNTP-Posting-Host: 118.70.129.184 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> Subject: convert from verilog to vhdl From: Mat18111992 Injection-Date: Tue, 21 Jul 2015 08:32:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 78 Xref: news.eternal-september.org comp.lang.vhdl:3887 Hello everyone. I had a code for fixed point division by Verilog. I tried to rewrite it with VHDL but not successfull. Can somebody help me? Thanks so much. module division #( //Parameterized values parameter Q = 4, // number of fraction bits parameter N = 8 ) ( input [N-1:0] i_dividend, input [N-1:0] i_divisor, input i_start, input i_clk, output [N-1:0] o_quotient_out, output o_complete, output o_overflow ); reg [2*N+Q-3:0] reg_working_quotient;// Our working copy of the quotient reg [N-1:0] reg_quotient; // Final quotient reg [N-2+Q:0] reg_working_dividend;// Working copy of the dividend reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor reg [$clog2(N-1+Q):0] reg_count; reg reg_done; // Computation completed flag reg reg_sign; // The quotient's sign bit reg reg_overflow; // Overflow flag initial reg_done = 1'b1; initial reg_overflow = 1'b0; initial reg_sign = 1'b0; initial reg_working_quotient = 0; initial reg_quotient = 0; initial reg_working_dividend = 0; initial reg_working_divisor = 0; initial reg_count = 0; assign o_quotient_out[N-2:0] = reg_quotient[N-2:0];//division results assign o_quotient_out[N-1] = reg_sign; //The sign of the quotient assign o_complete = reg_done; assign o_overflow = reg_overflow; always @( posedge i_clk ) begin if( reg_done && i_start ) begin //This is our startup condition reg_done<=1'b0; reg_count<=N+Q-1; reg_working_quotient<=0; reg_working_dividend<=0; reg_working_divisor<=0; reg_overflow <= (i_divisor[N-2:0])?1'b0:1'b1;// check divisor =0 or !=0 reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; end else if(!reg_done) begin reg_working_divisor <= reg_working_divisor >> 1; if(reg_working_dividend >= reg_working_divisor) begin reg_working_quotient[reg_count<=1'b1; reg_working_dividend <= reg_working_dividend - reg_working_divisor; end if(!(reg_count | 0)) begin //count = 0 reg_done<=1'b1; reg_quotient <= reg_working_quotient; reg_overflow <= (reg_working_quotient[2*N+Q-3:N]) ? 1'b1 : 1'b0; end else reg_count <= reg_count - 1; end end endmodule From newsfish@newsfish Thu Aug 1 00:34:03 2024 X-Received: by 10.66.199.71 with SMTP id ji7mr38014242pac.23.1437476700004; Tue, 21 Jul 2015 04:05:00 -0700 (PDT) X-Received: by 10.140.102.172 with SMTP id w41mr516252qge.40.1437476699952; Tue, 21 Jul 2015 04:04:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!209.85.213.215.MISMATCH!pg9no2693427igb.0!news-out.google.com!b31ni277qge.0!nntp.google.com!69no1015660qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jul 2015 04:04:59 -0700 (PDT) In-Reply-To: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: convert from verilog to vhdl From: Thomas Stanka Injection-Date: Tue, 21 Jul 2015 11:04:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3888 Am Dienstag, 21. Juli 2015 10:32:22 UTC+2 schrieb Mat18111992: > Hello everyone. I had a code for fixed point division by Verilog. I tried to rewrite it with VHDL but not successfull. Can somebody help me? Thanks so much. Are you looking for someone to write the same code in VHDL? Than it helps to write something about the amount of money you like to spend. If you like to have free help, you might get more information when asking specific questions. Maybe add your VHDL code as well and present the points where you had trouble. Or start with concrete points you need help with. Quick and dirty: Open Synthesis tool, read verilog, perform synthesis and write out vhdl. regards, Thomas From newsfish@newsfish Thu Aug 1 00:34:03 2024 X-Received: by 10.52.189.7 with SMTP id ge7mr10261650vdc.6.1437479633368; Tue, 21 Jul 2015 04:53:53 -0700 (PDT) X-Received: by 10.50.138.70 with SMTP id qo6mr259397igb.5.1437479633334; Tue, 21 Jul 2015 04:53:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z61no2386924qge.0!news-out.google.com!t2ni17228igk.0!nntp.google.com!pg9no2704979igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jul 2015 04:53:52 -0700 (PDT) In-Reply-To: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=118.70.129.184; posting-account=2xiWIAoAAAARmmv1zwxT-I9-ZqoxLA0D NNTP-Posting-Host: 118.70.129.184 References: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <76c0f83e-61a9-4c65-9a06-99cd42ab6664@googlegroups.com> Subject: Re: convert from verilog to vhdl From: Mat18111992 Injection-Date: Tue, 21 Jul 2015 11:53:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 4922 X-Received-Body-CRC: 987902038 Xref: news.eternal-september.org comp.lang.vhdl:3889 Thanks Thomas. Here are VHDL code and testbench of mine. When I run simulation, I get an error :"Fatal: (vsim-3420) Array lengths do not match. Left is 11 (10 downto 0). Right is 18 (17 downto 0)." Can you give me some indication? Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --use ieee.math_real.all; entity division_m is generic( INPUT_WIDTH : integer :=8; FRAC : integer :=4); port ( clk : in std_logic; reset : in std_logic; dividend : in signed(INPUT_WIDTH-1 downto 0); divisor : in signed(INPUT_WIDTH-1 downto 0); quotient : out signed(INPUT_WIDTH-1 downto 0) --overflow : out std_logic ) ; end entity ; -- division_m architecture behavior of division_m is begin divider : process( clk, reset ) variable dividend_reg : signed(INPUT_WIDTH+FRAC-2 downto 0); variable divisor_reg : signed(2*INPUT_WIDTH+FRAC-3 downto 0); variable quotient_reg : signed(2*INPUT_WIDTH+FRAC-3 downto 0); begin if rising_edge(clk) then if reset = '1' then quotient <= (others => '0'); else dividend_reg := dividend(INPUT_WIDTH-2 downto 0)&(FRAC-1 downto 0 =>'0'); divisor_reg := divisor(INPUT_WIDTH-2 downto 0)&(INPUT_WIDTH+FRAC-2 downto 0 => '0'); for i in INPUT_WIDTH+FRAC-1 downto 0 loop divisor_reg := divisor_reg sll 1; if (dividend_reg >= divisor_reg) then quotient_reg(i) := '1'; dividend_reg := dividend_reg - divisor_reg; else quotient_reg(i) := '0'; end if ; end loop ; quotient(INPUT_WIDTH-1) <= dividend(INPUT_WIDTH-1) xor divisor(INPUT_WIDTH-1); quotient(INPUT_WIDTH-2 downto 0) <= quotient_reg(INPUT_WIDTH-2 downto 0); end if ; end if ; end process ; -- divider end architecture ; -- behavior Testbench: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity division_m_tb is end division_m_tb; architecture behavioral of division_m_tb is component division_m generic ( INPUT_WIDTH : integer; FRAC : integer); port ( clk : in std_logic; reset : in std_logic; dividend : in signed(INPUT_WIDTH-1 downto 0); divisor : in signed(INPUT_WIDTH-1 downto 0); quotient : out signed(INPUT_WIDTH-1 downto 0)); end component; -- component generics constant INPUT_WIDTH : integer := 8; constant FRAC : integer := 4; -- component ports signal reset : std_logic; signal dividend : signed(INPUT_WIDTH-1 downto 0); signal divisor : signed(INPUT_WIDTH-1 downto 0); signal quotient : signed(INPUT_WIDTH-1 downto 0); -- clock signal clk : std_logic := '1'; begin -- behavioral -- component instantiation DUT : division_m generic map ( INPUT_WIDTH => INPUT_WIDTH, FRAC => FRAC) port map ( clk => clk, reset => reset, dividend => dividend, divisor => divisor, quotient => quotient); -- clock generation clk <= not clk after 10 ns; -- waveform generation WaveGen_Proc : process begin --signal assignments reset <= '1'; --data_in <= (others => '0'); wait for 20 ns; wait until rising_edge(clk); reset <= '0'; dividend <= "01110000"; --7 divisor <= "00100000"; --2 wait until rising_edge(clk); dividend <= "01001000"; --4,5 divisor <= "00100000"; --2 wait until rising_edge(clk); dividend <= "01011000"; --5,5 divisor <= "00101100"; --2,75 wait until rising_edge(clk); dividend <= "01101110"; --6,875 divisor <= "00110000"; --3 --wait until rising_edge(clk); --data_in <= (others => '0'); wait; end process WaveGen_Proc; end behavioral; From newsfish@newsfish Thu Aug 1 00:34:03 2024 X-Received: by 10.13.200.67 with SMTP id k64mr38041124ywd.54.1437487586841; Tue, 21 Jul 2015 07:06:26 -0700 (PDT) X-Received: by 10.140.91.182 with SMTP id z51mr159472qgd.5.1437487586817; Tue, 21 Jul 2015 07:06:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z61no2408353qge.0!news-out.google.com!4ni81702qgh.1!nntp.google.com!z61no2408348qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jul 2015 07:06:26 -0700 (PDT) In-Reply-To: <76c0f83e-61a9-4c65-9a06-99cd42ab6664@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> <76c0f83e-61a9-4c65-9a06-99cd42ab6664@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: convert from verilog to vhdl From: Thomas Stanka Injection-Date: Tue, 21 Jul 2015 14:06:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3890 Am Dienstag, 21. Juli 2015 13:53:56 UTC+2 schrieb Mat18111992: > Thanks Thomas. > Here are VHDL code and testbench of mine. When I run simulation, I get an error :"Fatal: (vsim-3420) Array lengths do not match. Left is 11 (10 downto 0). Right is 18 (17 downto 0)." Can you give me some indication? You missed to post the line number for that error. Open editor go to that line number. You will see there something like Left <= Right ( might be ":=" for variables insterad of "<=") with Left beeing vector of 11 bit and right of 18 bit width. This is impossible in VHDL (and common mistake). In your code Divisor and Quotient are good candidates for 18 bit width. regards Thomas From newsfish@newsfish Thu Aug 1 00:34:03 2024 X-Received: by 10.182.240.233 with SMTP id wd9mr1516878obc.45.1437555768202; Wed, 22 Jul 2015 02:02:48 -0700 (PDT) X-Received: by 10.50.50.228 with SMTP id f4mr1220igo.0.1437555768168; Wed, 22 Jul 2015 02:02:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no1234796igg.0!news-out.google.com!a16ni25097ign.0!nntp.google.com!pg9no2976162igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jul 2015 02:02:47 -0700 (PDT) In-Reply-To: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=118.70.129.184; posting-account=2xiWIAoAAAARmmv1zwxT-I9-ZqoxLA0D NNTP-Posting-Host: 118.70.129.184 References: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <407608ee-7af7-44cd-8319-88dc8fd4661c@googlegroups.com> Subject: Re: convert from verilog to vhdl From: Mat18111992 Injection-Date: Wed, 22 Jul 2015 09:02:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3891 Thomas. Below is the code I have rewritten to implement pipelined module fixed-point division. Signal quotient_reg was calculated correctly but when I use the assignment sentence : " quotient(INPUT_WIDTH-2 downto 0) <= std_logic_vector(quotient_reg(INPUT_WIDTH-2 downto 0));" The output signal (quotient) is not correct, it get unknown value. How I fix this error? Thanks again!! Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity division is generic( INPUT_WIDTH : integer :=8; FRAC : integer :=4); port ( clk : in std_logic; reset : in std_logic; dividend : in std_logic_vector(INPUT_WIDTH-1 downto 0); divisor : in std_logic_vector(INPUT_WIDTH-1 downto 0); quotient : out std_logic_vector(INPUT_WIDTH-1 downto 0) ) ; end entity ; -- division architecture behavior of division is constant N : integer := INPUT_WIDTH+FRAC-1; constant K : integer := 2*INPUT_WIDTH+FRAC-3; type dividend_array is array (0 to N) of unsigned(K downto 0); type divisor_array is array (0 to N) of unsigned(K downto 0); signal dividend_reg : dividend_array; signal divisor_reg : divisor_array; signal quotient_reg : std_logic_vector(N-1 downto 0); begin divider : process( clk, reset ) variable tmp : unsigned(K downto 0); begin if rising_edge(clk) then if reset = '1' then quotient <= (others => '0'); quotient_reg <= (others => '0'); dividend_reg <= (others =>(others => '0')); divisor_reg <= (others =>(others => '0')); else dividend_reg(N) <= (K downto N => '0') & unsigned(dividend(INPUT_WIDTH-2 downto 0)) & (FRAC-1 downto 0 =>'0'); divisor_reg(N) <= unsigned(divisor(INPUT_WIDTH-2 downto 0)) & (N-1 downto 0 => '0'); quotient_reg <= (others => '0'); for i in N-1 downto 0 loop tmp := '0'&divisor_reg(i+1)(K downto 1); if (std_logic_vector(dividend_reg(i+1)) >= std_logic_vector(tmp)) then quotient_reg(i) <= '1'; dividend_reg(i) <= dividend_reg(i+1) - tmp; divisor_reg(i) <= '0'&divisor_reg(i+1)(K downto 1); else quotient_reg(i) <= '0'; dividend_reg(i) <= dividend_reg(i+1); divisor_reg(i) <= '0'&divisor_reg(i+1)(K downto 1); end if ; end loop; end if ; end if ; end process ; -- divider quotient(INPUT_WIDTH-1) <= dividend(INPUT_WIDTH-1) xor divisor(INPUT_WIDTH-1); quotient(INPUT_WIDTH-2 downto 0) <= std_logic_vector(quotient_reg(INPUT_WIDTH-2 downto 0)); end architecture ; -- behavior Testbench: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity division_tb is end division_tb; architecture behavioral of division_tb is component division generic ( INPUT_WIDTH : integer; FRAC : integer); port ( clk : in std_logic; reset : in std_logic; dividend : in std_logic_vector(INPUT_WIDTH-1 downto 0); divisor : in std_logic_vector(INPUT_WIDTH-1 downto 0); quotient : out std_logic_vector(INPUT_WIDTH-1 downto 0)); end component; -- component generics constant INPUT_WIDTH : integer := 8; constant FRAC : integer := 4; -- component ports signal reset : std_logic; signal dividend : std_logic_vector(INPUT_WIDTH-1 downto 0); signal divisor : std_logic_vector(INPUT_WIDTH-1 downto 0); signal quotient : std_logic_vector(INPUT_WIDTH-1 downto 0); -- clock signal clk : std_logic := '1'; begin -- behavioral -- component instantiation DUT : division generic map ( INPUT_WIDTH => INPUT_WIDTH, FRAC => FRAC) port map ( clk => clk, reset => reset, dividend => dividend, divisor => divisor, quotient => quotient); -- clock generation clk <= not clk after 10 ns; -- waveform generation: execute 7/2=3.5 WaveGen_Proc : process begin --signal assignments reset <= '1'; --data_in <= (others => '0'); wait for 20 ns; wait until rising_edge(clk); reset <= '0'; dividend <= "01110000"; --7 divisor <= "00100000"; --2 wait; end process WaveGen_Proc; end behavioral; From newsfish@newsfish Thu Aug 1 00:34:04 2024 X-Received: by 10.129.111.132 with SMTP id k126mr1860535ywc.10.1437560726762; Wed, 22 Jul 2015 03:25:26 -0700 (PDT) X-Received: by 10.140.97.55 with SMTP id l52mr27346qge.36.1437560726701; Wed, 22 Jul 2015 03:25:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!69no1214777qgl.1!news-out.google.com!4ni81753qgh.1!nntp.google.com!z61no2577985qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jul 2015 03:25:26 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=147.156.81.119; posting-account=NlPq2woAAAA-uXcyqWpX4ngsDfFAtgcq NNTP-Posting-Host: 147.156.81.119 References: <7c961a05-b447-4910-94b4-9f690a23571d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94a082f2-4df5-4a36-ab23-d54c3a757cb2@googlegroups.com> Subject: Re: Can we log internal signals from a testbench in VHDL? From: luutey@gmail.com Injection-Date: Wed, 22 Jul 2015 10:25:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:3892 Hi Ralf, I had a similar problem and your solution solved it. Thanks. :) From newsfish@newsfish Thu Aug 1 00:34:04 2024 X-Received: by 10.107.170.25 with SMTP id t25mr1899362ioe.18.1437560860346; Wed, 22 Jul 2015 03:27:40 -0700 (PDT) X-Received: by 10.140.99.44 with SMTP id p41mr28322qge.3.1437560860210; Wed, 22 Jul 2015 03:27:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!f3no1268756igg.0!news-out.google.com!4ni81752qgh.1!nntp.google.com!69no1215215qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jul 2015 03:27:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=147.156.81.119; posting-account=NlPq2woAAAA-uXcyqWpX4ngsDfFAtgcq NNTP-Posting-Host: 147.156.81.119 References: <7c961a05-b447-4910-94b4-9f690a23571d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <973acfae-7973-4be0-a18a-4845a836e140@googlegroups.com> Subject: Re: Can we log internal signals from a testbench in VHDL? From: Bare-Metal Injection-Date: Wed, 22 Jul 2015 10:27:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3893 On Friday, November 9, 2012 at 8:23:29 AM UTC+1, Ralf Hildebrandt wrote: > Hi py! > > > This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer? > > Declare a signal in a package - a "global" signal. Write to this signal > inside your subcomponent, read this signal wherever you want. All you > need is to include this package in all components where you read/write > this signal. > > To make this subcomponent synthesizeable use > -- pragma translate_off > ... your problemativ VHDL code here ... > -- pragma translate_off > > As an alternative you can use a "shared variable". This can be written > from several locations while the signal should be written only from one > location. > > Ralf Hi Ralf, I had a similar problem and your solution solved it. Thanks. :) From newsfish@newsfish Thu Aug 1 00:34:04 2024 X-Received: by 10.182.213.166 with SMTP id nt6mr9001878obc.3.1437666217648; Thu, 23 Jul 2015 08:43:37 -0700 (PDT) X-Received: by 10.140.96.137 with SMTP id k9mr188417qge.10.1437666217620; Thu, 23 Jul 2015 08:43:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!pg9no3378628igb.0!news-out.google.com!4ni81865qgh.1!nntp.google.com!69no1481498qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 23 Jul 2015 08:43:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=151.40.190.158; posting-account=AXSUuQoAAACXwhXPPNv87DD39TdEGi6i NNTP-Posting-Host: 151.40.190.158 References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> <1d6ce218-34fc-41b5-845e-a9754bfee291@t7g2000vbj.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7bc89abb-8b05-4b09-b02d-cb0650267004@googlegroups.com> Subject: Re: Generate statement with varying signal width From: Andrea Campera Injection-Date: Thu, 23 Jul 2015 15:43:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3894 Hello guys, i saw it is an old topic but i'm struggling with such a problem in these days and unfortunately i saw no answer to Matt's question. The problem is this can be done with Verilog (at least > 2005). you can access variables declared in a generate statement using label.variable. There are lots of recursive structures with variable data size, and i guess VHDL can not easily provide a way to describe them. I tried to use hierarchinal names with VHDL 2008 but i was not able to find a way to reference a signal from another loop iteration. here is an example in Verilog (sorry for no indentation) genvar i; generate for(i=0;i Subject: About fpga board From: abdrhblushi@gmail.com Injection-Date: Mon, 27 Jul 2015 03:32:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3895 Hi I am working with group research in college We work on fpga board we finish coding on matlab now we want convert this code to vhdl i knew about the feature that matlab allow me to convert but as what i read it is for small code or not? i dont have any previous knowledge about this board also i am not dealing a lot with assimbly language, so i want ask How long it will take to learn vhdl virelog language? And is there any tool or way could help to convert code? From newsfish@newsfish Thu Aug 1 00:34:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Sun, 26 Jul 2015 23:52:21 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 Jul 2015 03:50:53 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25848"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199908qSXwm1Mq9wX9V5IQa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> Cancel-Lock: sha1:syoUQkaheA1IxHrrndRjg/gNsK4= Xref: news.eternal-september.org comp.lang.vhdl:3896 On 7/26/2015 11:32 PM, abdrhblushi@gmail.com wrote: > Hi > > I am working with group research in college We work on fpga board we > finish coding on matlab now we want convert this code to vhdl i knew > about the feature that matlab allow me to convert but as what i read > it is for small code or not? i dont have any previous knowledge about > this board also i am not dealing a lot with assimbly language, > > so i want ask How long it will take to learn vhdl virelog language? > And is there any tool or way could help to convert code? Verilog and VHDL are two separate HDLs (Hardware Description Language) for the same job. Asking how long it will take to learn them is like asking, "how long is a piece of string?" That will depend on you. Is your class a coding class or a hardware design class? If the purpose is to learn an HDL what are you having trouble with? If the purpose is to learn to design hardware, then why do you need to learn an HDL? Can't Matlab pump out an HDL file? -- Rick From newsfish@newsfish Thu Aug 1 00:34:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Mon, 27 Jul 2015 06:31:24 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 37 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3897 abdrhblushi@gmail.com wrote: > I am working with group research in college > We work on fpga board we finish coding on matlab now we > want convert this code to vhdl i knew about the feature that matlab > allow me to convert but as what i read it is for small code or not? > i dont have any previous knowledge about this board also i am > not dealing a lot with assimbly language, Why do you want to convert to VHDL for an FPGA? You don't say at all what kind of algorithm it is, which can make a big difference. Usually you do it to make it faster, but you don't say how fast it needs to be. > so i want ask > How long it will take to learn vhdl virelog language? If you understand digital logic, have wired up TTL gates to make working systems, then it won't take very long, If you haven't, then a long time. > And is there any tool or way could help to convert code? There might be, but you don't want to use it if it does. FPGA implementations of algorithms are usually different from Matlab implementations. If you don't understand the details of the algorithms, there is no use in doing it. (Note that you can implement a processor in the FPGA, then run Matlab on that processor. That likely isn't the reason to use the FPGA or VHDL.) -- glen From newsfish@newsfish Thu Aug 1 00:34:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Finally! A Completely Open Complete FPGA Toolchain Date: Mon, 27 Jul 2015 12:34:21 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 Jul 2015 16:32:50 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13669"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+k5lcbBQQJni2tQOEeZBiK" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 Cancel-Lock: sha1:eaJxT9m+XUdZtvjecmw85I0TNfs= Xref: news.eternal-september.org comp.arch.fpga:8263 comp.lang.vhdl:3898 comp.lang.verilog:1166 I am very impressed. I was reading about Antti's incredibly tiny FPGA project board and saw a mention of a FOSS FPGA toolchain. Not just the compiler, but the entire bitstream generation! http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas-that-small/ Several people have built on each other's work to provide "a fully open source Verilog to bitstream development tool chain for the Lattice iCE40LP with support for more devices in the works." http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/ https://github.com/cseed/arachne-pnr I haven't tried any of it yet, but I am very impressed that they are reverse engineering the devices so that they can generate bit streams and not rely on the vendor. -- Rick From newsfish@newsfish Thu Aug 1 00:34:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Mon, 27 Jul 2015 13:25:18 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 Jul 2015 17:23:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3607"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qX5G9+U00DRBO2r6NvscX" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:q51eqYRtzoWUMOrj8ScJ+KQG6G0= Xref: news.eternal-september.org comp.arch.fpga:8264 comp.lang.vhdl:3899 comp.lang.verilog:1167 On 7/27/2015 12:34 PM, rickman wrote: > I am very impressed. I was reading about Antti's incredibly tiny FPGA > project board and saw a mention of a FOSS FPGA toolchain. Not just the > compiler, but the entire bitstream generation! > > http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas-that-small/ > > > Several people have built on each other's work to provide "a fully open > source Verilog to bitstream development tool chain for the Lattice > iCE40LP with support for more devices in the works." > > http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/ > > https://github.com/cseed/arachne-pnr > > I haven't tried any of it yet, but I am very impressed that they are > reverse engineering the devices so that they can generate bit streams > and not rely on the vendor. I found another link relating to the tools called "IceStorm". http://www.clifford.at/icestorm/ -- Rick From newsfish@newsfish Thu Aug 1 00:34:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 27 Jul 2015 12:57:12 -0500 From: Tim Wescott Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Mon, 27 Jul 2015 12:57:12 -0500 Lines: 32 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-tfOwO5oKwqItXbQefmcDdF9yE28vOGJm7v+vw2HpDne/k0XHUIkyVY/M+kGrj3FqMwX5OoaVSo4COpx!a8FqR+R4AIk8g46vlDeGlbiB252XhlRd7/k3EjDG9QwVTY9yCnZvnrsk7pGj/yecnbo0WpoDjbfs X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2258 X-Received-Bytes: 2370 X-Received-Body-CRC: 2447858364 Xref: news.eternal-september.org comp.arch.fpga:8265 comp.lang.vhdl:3900 comp.lang.verilog:1168 On Mon, 27 Jul 2015 12:34:21 -0400, rickman wrote: > I am very impressed. I was reading about Antti's incredibly tiny FPGA > project board and saw a mention of a FOSS FPGA toolchain. Not just the > compiler, but the entire bitstream generation! > > http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas- that-small/ > > Several people have built on each other's work to provide "a fully open > source Verilog to bitstream development tool chain for the Lattice > iCE40LP with support for more devices in the works." > > http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/ > > https://github.com/cseed/arachne-pnr > > I haven't tried any of it yet, but I am very impressed that they are > reverse engineering the devices so that they can generate bit streams > and not rely on the vendor. Kewl. It'll be even more kewl if it shames the vendors into being open with their bitstream specifications. I have no idea why they seem to feel this needs to be held so close to their chests. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com From newsfish@newsfish Thu Aug 1 00:34:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Mon, 27 Jul 2015 14:30:34 -0400 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 Jul 2015 18:29:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="20847"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+iAhN1wfQLe63UDEmb1Bg+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:8AAkuFZmch7faNs0+X8rM5kgedg= Xref: news.eternal-september.org comp.arch.fpga:8266 comp.lang.vhdl:3901 comp.lang.verilog:1169 On 7/27/2015 1:57 PM, Tim Wescott wrote: > On Mon, 27 Jul 2015 12:34:21 -0400, rickman wrote: > >> I am very impressed. I was reading about Antti's incredibly tiny FPGA >> project board and saw a mention of a FOSS FPGA toolchain. Not just the >> compiler, but the entire bitstream generation! >> >> http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas- > that-small/ >> >> Several people have built on each other's work to provide "a fully open >> source Verilog to bitstream development tool chain for the Lattice >> iCE40LP with support for more devices in the works." >> >> http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/ >> >> https://github.com/cseed/arachne-pnr >> >> I haven't tried any of it yet, but I am very impressed that they are >> reverse engineering the devices so that they can generate bit streams >> and not rely on the vendor. > > Kewl. > > It'll be even more kewl if it shames the vendors into being open with > their bitstream specifications. I have no idea why they seem to feel > this needs to be held so close to their chests. I seriously doubt this will ever happen. They have all done this nearly 100% of the time and I'm sure they are convinced it is the best way to do business. From what they have said their concern is that with open source tools their hardware will be subject to "problems" caused by poor tools. Or maybe they limit access to chip features through the tools which they couldn't do with FOSS tools. I seem to recall someone ranting that a line of Altera parts had some devices which were labeled as smaller chips but would load and run a bitstream for a larger part. I expect this would show up quickly and clearly if the tools were FOSS. Those who have been in this business long enough may remember the line of parts Xilinx made specifically to support an open bit stream. It was popular with academia and a number of papers were written about researchy things you might do with it. I'm not sure what Xilinx's motive was for producing these chips, but they dropped the line and crushed the molds. I'm pretty sure there is no mention of these parts anywhere on their site now. Or did I only dream all of that? -- Rick From newsfish@newsfish Thu Aug 1 00:34:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "Tomas D." Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Mon, 27 Jul 2015 21:01:31 +0100 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Injection-Date: Mon, 27 Jul 2015 19:59:58 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9163fd05fabfda4407ad86bfb650ef6a"; logging-data="9725"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/RuwkaQ500IajQzOX90ivR" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 Cancel-Lock: sha1:EZvlXqhQc2RoQsHiB8mWB8xlhrE= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.arch.fpga:8267 comp.lang.vhdl:3902 comp.lang.verilog:1170 > Those who have been in this business long enough may remember the line of > parts Xilinx made specifically to support an open bit stream. It was > popular with academia and a number of papers were written about researchy > things you might do with it. I'm not sure what Xilinx's motive was for > producing these chips, but they dropped the line and crushed the molds. > I'm pretty sure there is no mention of these parts anywhere on their site > now. Or did I only dream all of that? Maybe you will also be interested in this: https://recon.cx/2015/slides/recon2015-18-andrew-zonenberg-From-Silicon-to-Compiler.pdf Tomas D. From newsfish@newsfish Thu Aug 1 00:34:07 2024 X-Received: by 10.182.230.3 with SMTP id su3mr31862503obc.6.1438044069440; Mon, 27 Jul 2015 17:41:09 -0700 (PDT) X-Received: by 10.140.96.137 with SMTP id k9mr493197qge.10.1438044069283; Mon, 27 Jul 2015 17:41:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no3754802igg.0!news-out.google.com!4ni82402qgh.1!nntp.google.com!69no2334689qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 27 Jul 2015 17:41:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.40.1.190; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 37.40.1.190 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Tue, 28 Jul 2015 00:41:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3903 The story was that we had AES(advance encryption standard) algorithm and we= want to put it in fpga board to use it in our college, the problem now i t= ry to implement some example of code to test the board but i faced difficul= ty and i felt that i am on the middel of the ocean and i forget to swim. I = am thinking to take courses but it not available in my country or college,= and i have to finish the work within two=A0month From newsfish@newsfish Thu Aug 1 00:34:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Mon, 27 Jul 2015 21:27:01 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 Jul 2015 01:25:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3099"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ftkpzr2eO9s9kWPPZW9CS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> Cancel-Lock: sha1:Uy4lScYU5JNXh3Gj5EpCYod7/kY= Xref: news.eternal-september.org comp.lang.vhdl:3904 On 7/27/2015 8:41 PM, abdrhblushi@gmail.com wrote: > The story was that we had AES(advance encryption standard) algorithm > and we want to put it in fpga board to use it in our college, the > problem now i try to implement some example of code to test the board > but i faced difficulty and i felt that i am on the middel of the > ocean and i forget to swim. I am thinking to take courses but it not > available in my country or college, and i have to finish the work > within two month Rather than fight the FPGA which can be a PITA, run your code on the simulator. You should be able to input and output files for the data you want to decrypt/encrypt. You can watch every value in every part of the design without needing to place probes. If the simulation works ok then you need to look for issues related to the possible errors that won't show in simulation. These errors are checked for in other ways or are usually avoided by paying attention to the few specific details involved such as clock domain crossing. But the simulation is the starting point. A friend used to have the email tag line, "If the dead in tombs are entombed, are the dead in crypts encrypted?" -- Rick From newsfish@newsfish Thu Aug 1 00:34:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Tue, 28 Jul 2015 01:41:07 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 27 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3905 abdrhblushi@gmail.com wrote: > The story was that we had AES(advance encryption standard) > algorithm and we want to put it in fpga board to use it in > our college, the problem now i try to implement some example > of code to test the board but i faced difficulty and i felt > that i am on the middel of the ocean and i forget to swim. It is usual to feel lost at the beginning of learning something new, so don't worry about that. But you do need to learn to think about wires and signals, if you haven't before. You can do this separate from learning VHDL. Have you done any electronic projects before? Analog or digital? > I am thinking to take courses but it not available in my > country or college, and i have to finish the work within > twomonth There should be some Coursera courses that cover enough. -- glen From newsfish@newsfish Thu Aug 1 00:34:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 28 Jul 2015 10:06:48 +0000 (UTC) Organization: A noiseless patient Spider Lines: 48 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 28 Jul 2015 10:06:48 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="22833"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19zX8UWf483O79UzPk/+rHoux6eZ1mFzRc=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:acqp4WTKaoSl8IkY+ct/V6VvHzY= Xref: news.eternal-september.org comp.arch.fpga:8268 comp.lang.vhdl:3906 comp.lang.verilog:1171 On Mon, 27 Jul 2015 14:30:34 -0400, rickman wrote: > On 7/27/2015 1:57 PM, Tim Wescott wrote: >> On Mon, 27 Jul 2015 12:34:21 -0400, rickman wrote: >> >>> I am very impressed. I was reading about Antti's incredibly tiny FPGA >>> project board and saw a mention of a FOSS FPGA toolchain. Not just >>> the compiler, but the entire bitstream generation! >>> http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40- fpgas/ > Excellent! Though I'm not surprised it's Lattice, I vaguely recall looking through an early (pre-2000) toolchain of theirs and thinking the details were closer to the surface than with other vendors. > Those who have been in this business long enough may remember the line > of parts Xilinx made specifically to support an open bit stream. It was > popular with academia and a number of papers were written about > researchy things you might do with it. I'm not sure what Xilinx's > motive was for producing these chips, but they dropped the line and > crushed the molds. I'm pretty sure there is no mention of these parts > anywhere on their site now. Or did I only dream all of that? Indeed you didn't dream the XC6200 series. It wasn't so much that Xilinx developed them, as they bought the company that did (Algotronics or Algotronix I think, based in Edinburgh). Presumably they bought them for tech in general or possibly some key patents rather than the specific device family. Which was something of a dead end in other respects, too fine grained (I believe' 1 gate, 1FF per CLB). Much simpler and more regular, but wouldn't scale too well to million-CLB devices dominated by routing, where the XC4000 and later devices would give the same capacity with a much smaller and cheaper die. I think it was that simple regular structure that made opening the bitstream format attractive, as well as killing the device long-term. You may also recall a company that successfully reverse-engineered the bitstream for Xilinx devices, and started to market their own independent toolchain. Yup, Xilinx bought them too. But their name lives on in the .ncd (neocad) file extension. -- Brian From newsfish@newsfish Thu Aug 1 00:34:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 28 Jul 2015 13:32:39 -0400 Organization: A noiseless patient Spider Lines: 87 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 Jul 2015 17:31:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="16270"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xzUbYmDPK2Hk64jDJ+HKl" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:l/DK0/nGcVkS2kBrOw9PbcWeIXo= Xref: news.eternal-september.org comp.arch.fpga:8269 comp.lang.vhdl:3907 comp.lang.verilog:1172 On 7/28/2015 6:06 AM, Brian Drummond wrote: > On Mon, 27 Jul 2015 14:30:34 -0400, rickman wrote: > >> On 7/27/2015 1:57 PM, Tim Wescott wrote: >>> On Mon, 27 Jul 2015 12:34:21 -0400, rickman wrote: >>> >>>> I am very impressed. I was reading about Antti's incredibly tiny FPGA >>>> project board and saw a mention of a FOSS FPGA toolchain. Not just >>>> the compiler, but the entire bitstream generation! > >>>> http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40- > fpgas/ >> > > Excellent! Though I'm not surprised it's Lattice, I vaguely recall > looking through an early (pre-2000) toolchain of theirs and thinking the > details were closer to the surface than with other vendors. > >> Those who have been in this business long enough may remember the line >> of parts Xilinx made specifically to support an open bit stream. It was >> popular with academia and a number of papers were written about >> researchy things you might do with it. I'm not sure what Xilinx's >> motive was for producing these chips, but they dropped the line and >> crushed the molds. I'm pretty sure there is no mention of these parts >> anywhere on their site now. Or did I only dream all of that? > > Indeed you didn't dream the XC6200 series. It wasn't so much that Xilinx > developed them, as they bought the company that did (Algotronics or > Algotronix I think, based in Edinburgh). Presumably they bought them for > tech in general or possibly some key patents rather than the specific > device family. > > Which was something of a dead end in other respects, too fine grained (I > believe' 1 gate, 1FF per CLB). Much simpler and more regular, but > wouldn't scale too well to million-CLB devices dominated by routing, > where the XC4000 and later devices would give the same capacity with a > much smaller and cheaper die. > > I think it was that simple regular structure that made opening the > bitstream format attractive, as well as killing the device long-term. > > You may also recall a company that successfully reverse-engineered the > bitstream for Xilinx devices, and started to market their own independent > toolchain. It has been a very long time, but I don't think NeoCAD was spitting out bitstreams for Xilinx parts where they? I may not remember it right, but I thought their claim to fame was their router which did a better job than the Xilinx tools which is why Xilinx bought them. Rather than bury the NeoCAD tools and moving on, they shipped the NeoCAD tools as their main tool. They reverse engineered the routing I know. I guess it wouldn't be so hard to figure out the bit stream too. I recall that NeoCAD was supporting other companies because they realized what a large job it was to write their own tools. So other new entries to the market used NeoCAD as their only tool. There were clauses in place to give them rights to the software if NeoCAD was bought by a competitor, which is what happened. I'm not sure that was much solace since they all ended up having to support their own software at that point which is what they were trying to get away from. > Yup, Xilinx bought them too. But their name lives on in the .ncd (neocad) > file extension. I seem to recall having the NeoCAD tools for some product other than Xilinx. It may be the ORCA devices which Lucent produced with their license from Xilinx. Not an XC4000 clone, but used Xilinx patents with similar functionality. I seem to recall they had the first CLBs where all components were not equivalent. Lattice does that in several of their FPGA lines now that they have the Lucent FPGA products and Xilinx licenses. I recall that Altera has terms in their software to limit what you can do with the bit stream. If you want to make an ASIC you *have* to come to them. That killed a company who was providing exactly that service, bit stream to ASIC. Do all the FPGA makers do that? I would think that alone would be reason enough to reverse engineer the bit stream. That company could then produce the bit stream themselves which would retain the 1:1 relation between your verified FPGA design and the ASIC. Maybe that is why FPGA companies don't want FOSS tools? It would take away their ASIC business. Is that very popular anymore? I haven't seen it promoted in years. -- Rick From newsfish@newsfish Thu Aug 1 00:34:09 2024 X-Received: by 10.182.219.225 with SMTP id pr1mr35979769obc.23.1438108519356; Tue, 28 Jul 2015 11:35:19 -0700 (PDT) X-Received: by 10.140.109.132 with SMTP id l4mr563096qgf.15.1438108519214; Tue, 28 Jul 2015 11:35:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!pg9no4787198igb.0!news-out.google.com!4ni82491qgh.1!nntp.google.com!69no2480418qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Jul 2015 11:35:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.40.3.82; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 37.40.3.82 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Tue, 28 Jul 2015 18:35:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3908 There is no way back so i will make more effort to learn it in two months, what are your advices and guidelines for me? I will be thankful From newsfish@newsfish Thu Aug 1 00:34:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Tue, 28 Jul 2015 18:53:17 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 14 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3909 abdrhblushi@gmail.com wrote: > There is no way back so i will make more effort to learn it > in two months, what are your advices and guidelines for me? > I will be thankful What have you done before? It is hard to say much without knowing that. Have you built any electronic circuits? Even simple ones? Have you worked at all with TTL circuits? -- glen From newsfish@newsfish Thu Aug 1 00:34:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 28 Jul 2015 13:59:38 -0500 Date: Tue, 28 Jul 2015 19:59:38 +0100 From: Jan Coombs > Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Message-ID: <20150728195938.5dcc9e5e@HP-6550b> References: X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 46 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ZHjtYtKJ1EnGJ1L5oI4NAm3pgUIe3ZwMtmT0qdKl1MLrp5JXHrWfUOkkCf2u45dvtG0bx1fmEWPE8PE!0nNaGzKrUkYR5t7nkVcdOv49L9o1dGRioyrHr48mkLoi7ELV4D9IgKvYXLhz8qIOwszL/dQSi5sD!CUVE X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3101 Xref: news.eternal-september.org comp.arch.fpga:8271 comp.lang.vhdl:3910 comp.lang.verilog:1173 On Tue, 28 Jul 2015 13:32:39 -0400 rickman wrote: > I recall that NeoCAD was supporting other companies because > they realized what a large job it was to write their own > tools. So other new entries to the market used NeoCAD as > their only tool. There were clauses in place to give them > rights to the software if NeoCAD was bought by a competitor, > which is what happened. I'm not sure that was much solace > since they all ended up having to support their own software > at that point which is what they were trying to get away from. > > > Yup, Xilinx bought them too. But their name lives on in > > the .ncd (neocad) file extension. > > I seem to recall having the NeoCAD tools for some product > other than Xilinx. It may be the ORCA devices which Lucent > produced with their license from Xilinx. Not an XC4000 clone, > but used Xilinx patents with similar functionality. I seem to > recall they had the first CLBs where all components were not > equivalent. Lattice does that in several of their FPGA lines > now that they have the Lucent FPGA products and Xilinx > licenses. And NeoCAD is still around: ************************************************************ ** Lattice Synthesis Engine ** ************************************************************ synthesis -f "spi12_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.4.0.80 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. Tue Jul 28 19:53:33 2015 Jan Coombs -- email valid, else fix dots and hyphen jan4clf2014@murrayhyphenmicroftdotcodotuk From newsfish@newsfish Thu Aug 1 00:34:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!buffer1.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 28 Jul 2015 14:55:48 -0500 Date: Tue, 28 Jul 2015 20:55:48 +0100 From: Jan Coombs > Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Message-ID: <20150728205548.1ede5368@HP-6550b> References: X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 49 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-3NtGAmJJf8k81iwYYqlsCWv2q2V+bVeAi2p+mfATetLI1NNnahOlYd1GTzefKXawAaVsFZKFB+19itB!M0K+2IxM3TfRcejuRDJqeqww9OeCgQw3Z/KpLNxnc6I+pQJF755dXUXTDmnxFXKqlIvYlGq+UdW2!BgfR X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3104 Xref: news.eternal-september.org comp.arch.fpga:8272 comp.lang.vhdl:3911 comp.lang.verilog:1174 On Tue, 28 Jul 2015 10:06:48 +0000 (UTC) Brian Drummond wrote: > On Mon, 27 Jul 2015 14:30:34 -0400, rickman wrote: > > > Those who have been in this business long enough may > > remember the line of parts Xilinx made specifically to > > support an open bit stream. [...] I'm pretty sure there > > is no mention of these parts anywhere on their site now. Or > > did I only dream all of that? > > Indeed you didn't dream the XC6200 series. It wasn't so much > that Xilinx developed them, as they bought the company that > did (Algotronics or Algotronix I think, based in Edinburgh). > Presumably they bought them for tech in general or possibly > some key patents rather than the specific device family. > > Which was something of a dead end in other respects, too fine > grained (I believe' 1 gate, 1FF per CLB). Much simpler and > more regular, but wouldn't scale too well to million-CLB > devices dominated by routing, where the XC4000 and later > devices would give the same capacity with a much smaller and > cheaper die. How about half a half a LUT or FF per CLB then? The Microsemi "IGLOO nano Low Power Flash" FPGAs are very similar in size and capability to the Lattice iCE40 range, except: The basic building block is either a flop or a LUT3 equivalent circuit, and these are then grouped into 8x8 blocks. [1] Innovation seems to come from smaller companies: as Lattice inherited the iCE40 series from SiliconBlue, Microsemi got the IGLOO parts from Actel, and the technology seen even earlier with ConcurrentLogic. An open-source toolchain for the IGLOO parts could be an unusually powerful tool in the hands of a creative designer. Jan Coombs -- [1] pg 73 of http://www.microsemi.com/document-portal/doc_view/130695-igloo-nano-low-power-flash-fpgas-datasheet email valid, else fix dots and hyphen jan4clf2014@murrayhyphenmicroftdotcodotuk From newsfish@newsfish Thu Aug 1 00:34:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 28 Jul 2015 16:10:51 -0400 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: <20150728205548.1ede5368@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 Jul 2015 20:09:35 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="23684"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18eE2hl2yKD92Yzz4jhXKEe" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <20150728205548.1ede5368@HP-6550b> Cancel-Lock: sha1:6a3AATpwz2MeHeyOw3tuL7NruYM= Xref: news.eternal-september.org comp.arch.fpga:8273 comp.lang.vhdl:3912 comp.lang.verilog:1175 On 7/28/2015 3:55 PM, Jan Coombs On Tue, 28 Jul 2015 10:06:48 +0000 (UTC) > Brian Drummond wrote: > >> On Mon, 27 Jul 2015 14:30:34 -0400, rickman wrote: >> >>> Those who have been in this business long enough may >>> remember the line of parts Xilinx made specifically to >>> support an open bit stream. [...] I'm pretty sure there >>> is no mention of these parts anywhere on their site now. Or >>> did I only dream all of that? >> >> Indeed you didn't dream the XC6200 series. It wasn't so much >> that Xilinx developed them, as they bought the company that >> did (Algotronics or Algotronix I think, based in Edinburgh). >> Presumably they bought them for tech in general or possibly >> some key patents rather than the specific device family. >> >> Which was something of a dead end in other respects, too fine >> grained (I believe' 1 gate, 1FF per CLB). Much simpler and >> more regular, but wouldn't scale too well to million-CLB >> devices dominated by routing, where the XC4000 and later >> devices would give the same capacity with a much smaller and >> cheaper die. > > How about half a half a LUT or FF per CLB then? > > The Microsemi "IGLOO nano Low Power Flash" FPGAs are very > similar in size and capability to the Lattice iCE40 range, > except: > > The basic building block is either a flop or a LUT3 equivalent > circuit, and these are then grouped into 8x8 blocks. [1] > > Innovation seems to come from smaller companies: as Lattice > inherited the iCE40 series from SiliconBlue, I wouldn't say Lattice "inherited" the iCE40 family. That was what they bought, the rest of the SiBlue company came for free. > Microsemi > got the IGLOO parts from Actel, and the technology seen > even earlier with ConcurrentLogic. I don't think Concurrent Logic ended up in the hands of Actel. I know they were bought by Atmel and died a very slow death of being unfunded. I received training from the guy at Atmel who was the champion of that line. They never made an effort to keep up with process technology advances to reduce the costs. That said, I expect they knew the way to go was something more like the Xilinx/Altera routes. The fine grained architecture without routing resources just won't work for larger designs. As Xilinx used to say, "We sell you the routing and give you the logic for free." > An open-source toolchain for the IGLOO parts could be an > unusually powerful tool in the hands of a creative designer. I have looked at the Igloo parts but never been impressed. Why would an open source tool chain improve them or any other part? -- Rick From newsfish@newsfish Thu Aug 1 00:34:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!buffer1.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 29 Jul 2015 04:50:08 -0500 Date: Wed, 29 Jul 2015 10:50:09 +0100 From: Jan Coombs > Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Message-ID: <20150729105009.412968bf@HP-6550b> References: <20150728205548.1ede5368@HP-6550b> X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 31 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-x6X3iApQ5fwLBgy9DCcnYY72BW60vj9FeSsUpC5MSI62h2LXdsQzr0zw3N8bDdeCCrEkC65TZgS2lkb!8ICMvSaN5IfirGlR+RtCfA/HvHJlRBXU63fOUCBkvzqGMaCF7tRLdk8EkpuuvlNRH0cMFy5eP9Q4!ANAk X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2261 Xref: news.eternal-september.org comp.arch.fpga:8274 comp.lang.vhdl:3913 comp.lang.verilog:1176 On Tue, 28 Jul 2015 16:10:51 -0400 rickman wrote: > On 7/28/2015 3:55 PM, Jan Coombs > An open-source toolchain for the IGLOO parts could be an > > unusually powerful tool in the hands of a creative designer. > > I have looked at the Igloo parts but never been impressed. > Why would an open source tool chain improve them or any other > part? Because open source tools allow exploration of techniques which are restricted using regular tools. a) iCE40 - see rest of thread. (Note suggestion to buy 3 iCE40 sticks if using IceStorm, one or more parts might die during (mal?)practice) b) IGLOO - because you would then be able to create complex logic without the noise or random signal states inherent in using lookup tables. One possibility might be asynchronous logic. c) [others] no idea, unless they are close relatives of the above parts. (like ProASIC3) Jan Coombs -- email valid, else fix dots and hyphen jan4clf2014@murrayhyphenmicroftdotcodotuk From newsfish@newsfish Thu Aug 1 00:34:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Wed, 29 Jul 2015 12:32:08 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 29 Jul 2015 16:30:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3011"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Yd4AKQEc4YZGTN+KUCzKA" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <20150729105009.412968bf@HP-6550b> Cancel-Lock: sha1:reopWSWsLrX5ewW8ATNx0Z6YROU= Xref: news.eternal-september.org comp.arch.fpga:8276 comp.lang.vhdl:3914 comp.lang.verilog:1177 On 7/29/2015 5:50 AM, Jan Coombs On Tue, 28 Jul 2015 16:10:51 -0400 > rickman wrote: > >> On 7/28/2015 3:55 PM, Jan Coombs >> An open-source toolchain for the IGLOO parts could be an >>> unusually powerful tool in the hands of a creative designer. >> >> I have looked at the Igloo parts but never been impressed. >> Why would an open source tool chain improve them or any other >> part? > > Because open source tools allow exploration of techniques which > are restricted using regular tools. I'm not sure what this means. What "techniques" are restricted by the vendor's tools? Are we talking about techniques that are useful in a design environment or research? > a) iCE40 - see rest of thread. (Note suggestion to buy 3 iCE40 > sticks if using IceStorm, one or more parts might die during > (mal?)practice) I thoought I had read the thread. What did I miss? All I've seen is that there are alternative tools available that may or may not be as good as the vendor's tools. Other than not having to fight the licensing, what improvement do the alternative tools provide? > b) IGLOO - because you would then be able to create complex > logic without the noise or random signal states inherent in > using lookup tables. One possibility might be asynchronous > logic. ??? What logic won't the Igloo tools create? Sounds like I clearly need to avoid the Microsemi parts. > c) [others] no idea, unless they are close relatives of the > above parts. (like ProASIC3) ok -- Rick From newsfish@newsfish Thu Aug 1 00:34:11 2024 X-Received: by 10.13.245.6 with SMTP id e6mr43333840ywf.27.1438192775030; Wed, 29 Jul 2015 10:59:35 -0700 (PDT) X-Received: by 10.140.37.129 with SMTP id r1mr620134qgr.18.1438192774973; Wed, 29 Jul 2015 10:59:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z61no4022151qge.0!news-out.google.com!4ni82620qgh.1!nntp.google.com!z61no4022150qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Jul 2015 10:59:34 -0700 (PDT) In-Reply-To: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2a02:1812:510:7f00:896:b5f0:24ad:b755; posting-account=Y8jO5woAAABQjiGcTkoIyOEHis_U9pYB NNTP-Posting-Host: 2a02:1812:510:7f00:896:b5f0:24ad:b755 References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Register map auto-generation From: jan Injection-Date: Wed, 29 Jul 2015 17:59:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: news.eternal-september.org comp.lang.vhdl:3915 Maybe this: https://github.com/oddball/ipxact2systemverilog A Open-Source Python script to covert IP-XACT to VHDL/SystemVerilog/PDF/... From newsfish@newsfish Thu Aug 1 00:34:11 2024 X-Received: by 10.182.79.165 with SMTP id k5mr9117159obx.38.1438455234092; Sat, 01 Aug 2015 11:53:54 -0700 (PDT) X-Received: by 10.140.21.74 with SMTP id 68mr81683qgk.16.1438455234022; Sat, 01 Aug 2015 11:53:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!f3no6023622igg.0!news-out.google.com!b31ni3247qge.0!nntp.google.com!69no3292107qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 1 Aug 2015 11:53:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.154.147.82; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 85.154.147.82 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sat, 01 Aug 2015 18:53:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3916 I didn't do any thaings of what you said, but i am ready to do any things to be in the true way to learn it From newsfish@newsfish Thu Aug 1 00:34:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Sat, 01 Aug 2015 15:26:38 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Aug 2015 19:25:05 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="28283"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zg4/0ptUBpqvR7ZINo6W2" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> Cancel-Lock: sha1:RE/i2N5aaAzq9zp215sCWl2LuA0= Xref: news.eternal-september.org comp.lang.vhdl:3917 On 8/1/2015 2:53 PM, abdrhblushi@gmail.com wrote: > I didn't do any thaings of what you said, but i am ready to do any things to be in the true way to learn it Are you familiar with programming languages? Which ones and how much? A software designer came to this group once asking for help writing a "Hello world" program in HDL. Many of us told him it would be a difficult job if he didn't learn to "think" in hardware. I spent some time coaching him a bit and he had no trouble at all doing what he needed to do. Turns out you can write HDL similar to software as long as you observe a few basic rules. So this might not be such a difficult task if you can get Matlab to spit out some working code like C for example. Doesn't Matlab spit out an HDL though? I'm pretty sure I've heard of that. First think you need to do is to pick a starting point. I think working from the Matlab code is the last option you should pursue. -- Rick From newsfish@newsfish Thu Aug 1 00:34:12 2024 X-Received: by 10.50.8.1 with SMTP id n1mr9930709iga.1.1438459027017; Sat, 01 Aug 2015 12:57:07 -0700 (PDT) X-Received: by 10.140.20.21 with SMTP id 21mr87748qgi.9.1438459026948; Sat, 01 Aug 2015 12:57:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!f3no6049172igg.0!news-out.google.com!b31ni3263qge.0!nntp.google.com!z61no4666259qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 1 Aug 2015 12:57:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.154.147.82; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 85.154.147.82 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sat, 01 Aug 2015 19:57:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 5 Xref: news.eternal-september.org comp.lang.vhdl:3918 I am good in java I understand the logic of it very well So i will do what you said then i will return to show you the result and what i understand, now i have final exam after finishing i will try it.. Thank you very much for your help From newsfish@newsfish Thu Aug 1 00:34:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Sat, 01 Aug 2015 19:56:41 -0400 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Aug 2015 23:55:07 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="20107"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+cvcvr6rxUjs7WBVktHm9+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Cancel-Lock: sha1:lPb8sEQIRTM5pynhYQsgT9zGIxU= Xref: news.eternal-september.org comp.lang.vhdl:3919 On 8/1/2015 3:57 PM, abdrhblushi@gmail.com wrote: > I am good in java > I understand the logic of it very well > > So i will do what you said then i will return to show you the result and what i understand, now i have final exam after finishing i will try it.. Showing me Java won't mean much to me as I don't write or read it. I am pretty sure MatLab will translate your Matlab code to an HDL. Why not use that for a first pass. We can help you massage that code to make it work the way you want I expect. Likely easier than trying to teach you HDL from your understanding of Java. -- Rick From newsfish@newsfish Thu Aug 1 00:34:12 2024 X-Received: by 10.66.185.195 with SMTP id fe3mr2514638pac.13.1438686503190; Tue, 04 Aug 2015 04:08:23 -0700 (PDT) X-Received: by 10.140.81.38 with SMTP id e35mr28900qgd.3.1438686503095; Tue, 04 Aug 2015 04:08:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no7301757igg.0!news-out.google.com!78ni5929qge.1!nntp.google.com!69no3798786qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Aug 2015 04:08:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.140.141.107; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.140.141.107 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Tue, 04 Aug 2015 11:08:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3920 It is good idea i will send all codes that i want to convert to your email, please send it for me, My email: abdrhblushi@gmail.com With regards From newsfish@newsfish Thu Aug 1 00:34:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Tue, 04 Aug 2015 12:35:27 -0400 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 4 Aug 2015 16:33:52 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="1669"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+JKkCFVYAfOmyIgiX+ABKs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:ReUzuZa0+7PhsLjU5FZgMXCYs+w= Xref: news.eternal-september.org comp.lang.vhdl:3921 On 8/4/2015 7:08 AM, abdrhblushi@gmail.com wrote: > It is good idea i will send all codes that i want to convert to your email, please send it for me, > My email: abdrhblushi@gmail.com What type of code do you have? -- Rick From newsfish@newsfish Thu Aug 1 00:34:13 2024 X-Received: by 10.13.229.198 with SMTP id o189mr3993399ywe.36.1438707422344; Tue, 04 Aug 2015 09:57:02 -0700 (PDT) X-Received: by 10.140.97.55 with SMTP id l52mr56226qge.36.1438707422287; Tue, 04 Aug 2015 09:57:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z61no5224448qge.0!news-out.google.com!78ni6270qge.1!nntp.google.com!z61no5224445qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Aug 2015 09:57:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.242.139.195; posting-account=nUlK9goAAACu3kqCZ7wyRXwYlqENGl59 NNTP-Posting-Host: 109.242.139.195 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: implement galois polynomial mod From: Parfa Injection-Date: Tue, 04 Aug 2015 16:57:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:3922 Hi, I am quite new in VHDL, I Would like to ask if anybody could help me with implementing an synthesizable modulo operator between a fixed sized (128 bits) galois polynomial and a variable sized (8-128 bits) galois polynomial. From newsfish@newsfish Thu Aug 1 00:34:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: implement galois polynomial mod Date: Tue, 4 Aug 2015 17:52:53 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 12 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3923 Parfa wrote: > Hi, I am quite new in VHDL, > I Would like to ask if anybody could help me with implementing > an synthesizable modulo operator between a fixed sized (128 bits) > galois polynomial and a variable sized (8-128 bits) galois polynomial. Probably not, but it is important to know how fast it has to be, and whether or not it can be pipelined. -- glen From newsfish@newsfish Thu Aug 1 00:34:14 2024 X-Received: by 10.66.237.2 with SMTP id uy2mr4679195pac.11.1438716598131; Tue, 04 Aug 2015 12:29:58 -0700 (PDT) X-Received: by 10.140.36.170 with SMTP id p39mr66940qgp.28.1438716598082; Tue, 04 Aug 2015 12:29:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no7523563igg.0!news-out.google.com!78ni6447qge.1!nntp.google.com!69no3886752qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Aug 2015 12:29:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.242.139.195; posting-account=nUlK9goAAACu3kqCZ7wyRXwYlqENGl59 NNTP-Posting-Host: 109.242.139.195 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: implement galois polynomial mod From: Parfa Injection-Date: Tue, 04 Aug 2015 19:29:58 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3924 =CE=A4=CE=B7 =CE=A4=CF=81=CE=AF=CF=84=CE=B7, 4 =CE=91=CF=85=CE=B3=CE=BF=CF= =8D=CF=83=CF=84=CE=BF=CF=85 2015 - 7:57:06 =CE=BC.=CE=BC. UTC+3, =CE=BF =CF= =87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Parfa =CE=AD=CE=B3=CF=81=CE=B1=CF= =88=CE=B5: > Hi, I am quite new in VHDL, I Would like to ask if anybody could help me = with implementing an synthesizable modulo operator between a fixed sized (1= 28 bits) galois polynomial and a variable sized (8-128 bits) galois polynom= ial. Is something like "Reed Solomon Encoder" the answer? From newsfish@newsfish Thu Aug 1 00:34:14 2024 X-Received: by 10.107.38.11 with SMTP id m11mr4877641iom.15.1438718864115; Tue, 04 Aug 2015 13:07:44 -0700 (PDT) X-Received: by 10.140.97.199 with SMTP id m65mr64766qge.29.1438718864047; Tue, 04 Aug 2015 13:07:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!pg9no7076010igb.0!news-out.google.com!78ni6464qge.1!nntp.google.com!z61no5258247qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Aug 2015 13:07:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.140.178.39; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.140.178.39 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Tue, 04 Aug 2015 20:07:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3925 Matlab code From newsfish@newsfish Thu Aug 1 00:34:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Aleksandar Kuktin Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 4 Aug 2015 23:05:00 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 15 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> NNTP-Posting-Host: NcDLOX2QlKEv0KECGquTJw.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: Pan/0.135 (Tomorrow I'll Wake Up and Scald Myself with Tea; Unknown) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.arch.fpga:8307 comp.lang.vhdl:3926 comp.lang.verilog:1179 On Wed, 29 Jul 2015 12:32:08 -0400, rickman wrote: > On 7/29/2015 5:50 AM, Jan Coombs > a) iCE40 - see rest of thread. (Note suggestion to buy 3 iCE40 sticks >> if using IceStorm, one or more parts might die during (mal?)practice) > > I thoought I had read the thread. What did I miss? All I've seen is > that there are alternative tools available that may or may not be as > good as the vendor's tools. Other than not having to fight the > licensing, what improvement do the alternative tools provide? Hackability. If you have an itch, you can scratch it yourself with FOSS tools. If you discover a bug, you can fix it yourself. If you want to repurpose, optimize or otherwise change the tool, you can do it with FOSS. From newsfish@newsfish Thu Aug 1 00:34:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 04 Aug 2015 19:46:38 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 4 Aug 2015 23:45:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="7679"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/XZK0S1ByBvFP8DPDYHX3K" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:PJ2sbzX5tDTOGTyd8dhrC4Kli6A= Xref: news.eternal-september.org comp.arch.fpga:8309 comp.lang.vhdl:3927 comp.lang.verilog:1180 On 8/4/2015 7:05 PM, Aleksandar Kuktin wrote: > On Wed, 29 Jul 2015 12:32:08 -0400, rickman wrote: > >> On 7/29/2015 5:50 AM, Jan Coombs >>> a) iCE40 - see rest of thread. (Note suggestion to buy 3 iCE40 sticks >>> if using IceStorm, one or more parts might die during (mal?)practice) >> >> I thoought I had read the thread. What did I miss? All I've seen is >> that there are alternative tools available that may or may not be as >> good as the vendor's tools. Other than not having to fight the >> licensing, what improvement do the alternative tools provide? > > Hackability. If you have an itch, you can scratch it yourself with FOSS > tools. If you discover a bug, you can fix it yourself. If you want to > repurpose, optimize or otherwise change the tool, you can do it with FOSS. That's great. But only important to a small few. I use tools to get work done. I have zero interest in digging into the code of the tools without a real need. I have not found any bugs in the vendor's tools that would make me want to spend weeks learning how they work in the, most likely, vain hope that I could fix them. I think FOSS is great and I am very happy to see that finally happen in an end to end toolchain for an FPGA. But it is statements like this that I don't understand, "An open-source toolchain for the IGLOO parts could be an unusually powerful tool in the hands of a creative designer", or this "Because open source tools allow exploration of techniques which are restricted using regular tools." Not trying to give anyone grief. I'd just like to understand what people expect to happen with FOSS that isn't happening with the vendor's closed, but free tools. -- Rick From newsfish@newsfish Thu Aug 1 00:34:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Tue, 04 Aug 2015 19:47:30 -0400 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 4 Aug 2015 23:45:56 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="7679"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18bwqZ6WdaZiqtcRYxB7CzL" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:KSg4zmGZ7+q0uBBg4vtDEySVvDM= Xref: news.eternal-september.org comp.lang.vhdl:3928 On 8/4/2015 4:07 PM, abdrhblushi@gmail.com wrote: > Matlab code Have you asked Matlab to convert your design to an HDL yet? -- Rick From newsfish@newsfish Thu Aug 1 00:34:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: implement galois polynomial mod Date: Wed, 5 Aug 2015 12:29:08 +0000 (UTC) Organization: A noiseless patient Spider Lines: 18 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 5 Aug 2015 12:29:08 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="32182"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/7aM/4OjsaQgFeuLZatKI7bVIqelhAh64=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:vGEwTgiodKJy5RjBPmDxPnlOrx8= Xref: news.eternal-september.org comp.lang.vhdl:3929 On Tue, 04 Aug 2015 12:29:57 -0700, Parfa wrote: > Τη Τρίτη, 4 Αυγούστου 2015 - 7:57:06 μ.μ. UTC+3, ο χρήστης Parfa έγραψε: >> Hi, I am quite new in VHDL, I Would like to ask if anybody could help >> me with implementing an synthesizable modulo operator between a fixed >> sized (128 bits) galois polynomial and a variable sized (8-128 bits) >> galois polynomial. > > Is something like "Reed Solomon Encoder" the answer? At this level, the question has nothing whatsoever to do with VHDL, so find generic answers (not language-specific) to the question. Actually translating from a proven answer into VHDL is likely to be relatively easy, so don't worry about VHDL yet. Any questions about that translation are likely to be answerable here. -- Brian From newsfish@newsfish Thu Aug 1 00:34:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 5 Aug 2015 12:32:20 +0000 (UTC) Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 5 Aug 2015 12:32:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="32182"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/6lvrReY9ZLpIl5c44xWD0a0P42xGcFMM=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:P0rqXp1ki6Q49DW2DuwA19xvzGU= Xref: news.eternal-september.org comp.lang.vhdl:3930 On Tue, 04 Aug 2015 19:47:30 -0400, rickman wrote: > On 8/4/2015 4:07 PM, abdrhblushi@gmail.com wrote: >> Matlab code > > Have you asked Matlab to convert your design to an HDL yet? That requires an expensive additional tool, strangely called called "HDL Coder", and last time I looked it generated hilariously awful VHDL. It's probably easier to convert from Matlab to VHDL by hand that work with HDL Coder's output... -- Brian From newsfish@newsfish Thu Aug 1 00:34:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 5 Aug 2015 19:45:34 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 25 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3931 Brian Drummond wrote: > On Tue, 04 Aug 2015 19:47:30 -0400, rickman wrote: (snip) >> Have you asked Matlab to convert your design to an HDL yet? > That requires an expensive additional tool, strangely called called "HDL > Coder", and last time I looked it generated hilariously awful VHDL. It's > probably easier to convert from Matlab to VHDL by hand that work with HDL > Coder's output... That is what I would expect. Well, there is an easy way, which is to generate code for a soft processor in ROM, and then generate VHDL for the processor. Many years ago, I had some perl programs that ran too slow (1 MB/min). I found a perl2c converter, converted to C, and found it was just as slow. The converter generates the internal code that perl uses, and the interpreter for that code. Often the useful hardware implementation of an algorithm is completely different from the usual software implementations. It is unusual for tools to figure that out. -- glen From newsfish@newsfish Thu Aug 1 00:34:17 2024 X-Received: by 10.70.41.102 with SMTP id e6mr8487133pdl.10.1438805861248; Wed, 05 Aug 2015 13:17:41 -0700 (PDT) X-Received: by 10.140.28.2 with SMTP id 2mr35607qgy.9.1438805861164; Wed, 05 Aug 2015 13:17:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!f3no8042990igg.0!news-out.google.com!78ni7944qge.1!nntp.google.com!69no4098539qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Aug 2015 13:17:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.161.45.40; posting-account=pVZ58AoAAAAu_AZao2TMTkPLIgfi-fRU NNTP-Posting-Host: 86.161.45.40 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Finally! A Completely Open Complete FPGA Toolchain From: Jezmo Injection-Date: Wed, 05 Aug 2015 20:17:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 5 Xref: news.eternal-september.org comp.lang.vhdl:3932 Its the usual fantasy of the open source community that somehow open source= tools will open up unheard of advantages because you can fiddle with and p= robably break the sourcecode. It never happensin real life and like rick iI= have yet to see anything obviously broken in the code produced by major ve= ndors and I have no desire to spend months working out the inner workings o= f a program which has taken hundreds of man years to write. From newsfish@newsfish Thu Aug 1 00:34:17 2024 X-Received: by 10.50.43.231 with SMTP id z7mr1060018igl.7.1438806823380; Wed, 05 Aug 2015 13:33:43 -0700 (PDT) X-Received: by 10.140.106.247 with SMTP id e110mr134643qgf.7.1438806823311; Wed, 05 Aug 2015 13:33:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no8050390igg.0!news-out.google.com!78ni7944qge.1!nntp.google.com!69no4101382qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Aug 2015 13:33:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.161.45.40; posting-account=pVZ58AoAAAAu_AZao2TMTkPLIgfi-fRU NNTP-Posting-Host: 86.161.45.40 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <717b37df-bd92-45ce-bc94-6600e872a27e@googlegroups.com> Subject: Finally! A Completely Open Complete FPGA Toolchain From: Jezmo Injection-Date: Wed, 05 Aug 2015 20:33:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3933 As a working engineer ive got designs to produce, my boss would not be plea= sed if I told him I was going to spend a month adding functionality to a lo= gic synthesis tool. Most FOSS advocates are software kiddies who have never= grown up and hang on every word of people such as Stallman From newsfish@newsfish Thu Aug 1 00:34:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 05 Aug 2015 17:00:25 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 20:58:54 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13365"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+OOx8NUiTH+VY4dIJzUJYI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:9tAmFxhLIabQWKyA9euU9OoSAZM= Xref: news.eternal-september.org comp.lang.vhdl:3934 On 8/5/2015 3:45 PM, glen herrmannsfeldt wrote: > > Often the useful hardware implementation of an algorithm is > completely different from the usual software implementations. > It is unusual for tools to figure that out. That is pretty obvious if you give it a bit of thought. A CPU running software is a *HUGE* finite state machine (FSM) with the memory containing the majority of the state along with the fewer registers in the CPU. The memory contents are all accessed through a very large multiplexer and operations on this FSM are time multiplexed and controlled by a program stored in memory. In an FPGA or ASIC the logic can all be designed in parallel with the much less happening sequentially. The design could be done in the same way with the very large multiplexers. The program can be done with logic rather than a stored program, but the access to the large FSM still requires a lot of multiplexers. So while it is possible to duplicate the actual CPU in an FPGA, it is seldom the best way to utilize an FPGA. The same problem can be implemented with a lot fewer gates by tailoring the algorithm to take advantage of the parallel nature of the FPGA and only implementing the specific data paths required by the problem. The generic CPU gains efficiency by the repetition of the regular arrays in memory which can be made both small and cheap but only with a sequential algorithm. -- Rick From newsfish@newsfish Thu Aug 1 00:34:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Wed, 05 Aug 2015 17:08:50 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <717b37df-bd92-45ce-bc94-6600e872a27e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 21:07:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14353"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190JME24sV6zRYprcR/Do2h" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <717b37df-bd92-45ce-bc94-6600e872a27e@googlegroups.com> Cancel-Lock: sha1:JtHTsYUvTauXxTKxM9eOf2nVvFk= Xref: news.eternal-september.org comp.lang.vhdl:3935 On 8/5/2015 4:33 PM, Jezmo wrote: > As a working engineer ive got designs to produce, my boss would not be pleased if I told him I was going to spend a month adding functionality to a logic synthesis tool. Most FOSS advocates are software kiddies who have never grown up and hang on every word of people such as Stallman I'm not sure I would make any statement like that. I think FOSS is more important or at least more useful in software because it can be a complete package. With hardware it is a bit harder because the hardware itself can be difficult to make accessible in the same way. Regardless, I am not trying to argue with anyone. I was asking for a clarification of what people expect from having open source tools. -- Rick From newsfish@newsfish Thu Aug 1 00:34:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 5 Aug 2015 21:22:33 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 42 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3936 rickman wrote: (snip, I wrote) >> Often the useful hardware implementation of an algorithm is >> completely different from the usual software implementations. >> It is unusual for tools to figure that out. > That is pretty obvious if you give it a bit of thought. A CPU running > software is a *HUGE* finite state machine (FSM) with the memory > containing the majority of the state along with the fewer registers in > the CPU. The memory contents are all accessed through a very large > multiplexer and operations on this FSM are time multiplexed and > controlled by a program stored in memory. In one of these newsgroups, a year or two ago, I called microprocessors the biggest waste of transistors, for this reason. These days, billions of transistors to funnel data through a (small number) of thousand transistor ALUs, and back out again. With systolic arrays, it is often not hard to chain together a large number of arithmetic blocks, each operating every clock cycle. > In an FPGA or ASIC the logic can all be designed in parallel with the > much less happening sequentially. The design could be done in the same > way with the very large multiplexers. The program can be done with > logic rather than a stored program, but the access to the large FSM > still requires a lot of multiplexers. So while it is possible to > duplicate the actual CPU in an FPGA, it is seldom the best way to > utilize an FPGA. The same problem can be implemented with a lot fewer > gates by tailoring the algorithm to take advantage of the parallel > nature of the FPGA and only implementing the specific data paths > required by the problem. The generic CPU gains efficiency by the > repetition of the regular arrays in memory which can be made both small > and cheap but only with a sequential algorithm. There is the assumption that some things can be done in parallel, but yes. -- glen From newsfish@newsfish Thu Aug 1 00:34:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder1.news.weretis.net!news.solani.org!.POSTED!not-for-mail From: Philipp Klaus Krause Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Wed, 05 Aug 2015 23:30:53 +0200 Organization: solani.org Lines: 43 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Trace: solani.org 1438810252 27887 eJwFwQkBwDAIA0BLLU8GcoAS/xJ254qL+QwOczpZdhwPUKV19mxJRe0boa5SrAsRSdg92vkDL4kRkw== (5 Aug 2015 21:30:52 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Wed, 5 Aug 2015 21:30:52 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.7.0 X-User-ID: eJwFwYEBwDAEBMCVPJ5mHCT2H6F3tEBMejCcy211hajvvdn5pJAjizDZPp/pufZSMZgqkv0DE9MQ5g== In-Reply-To: Cancel-Lock: sha1:CrMgWvf3fJbqA/FyqyIiWEY5Mmc= X-NNTP-Posting-Host: eJwFwYEBwDAEBMCVSP7RcRD2H6F3vKbWDqOBy9XKuEuMnehFb1ZPrIrAJz2FqE/lRRJ2Hn8s1xFX Xref: news.eternal-september.org comp.arch.fpga:8310 comp.lang.vhdl:3937 comp.lang.verilog:1181 On 05.08.2015 01:46, rickman wrote: > On 8/4/2015 7:05 PM, Aleksandar Kuktin wrote: >> >> Hackability. If you have an itch, you can scratch it yourself with FOSS >> tools. If you discover a bug, you can fix it yourself. If you want to >> repurpose, optimize or otherwise change the tool, you can do it with >> FOSS. > > That's great. But only important to a small few. I use tools to get > work done. I have zero interest in digging into the code of the tools > without a real need. I have not found any bugs in the vendor's tools > that would make me want to spend weeks learning how they work in the, > most likely, vain hope that I could fix them. > > I think FOSS is great and I am very happy to see that finally happen in > an end to end toolchain for an FPGA. But it is statements like this > that I don't understand, "An open-source toolchain for the IGLOO parts > could be an unusually powerful tool in the hands of a creative > designer", or this "Because open source tools allow exploration of > techniques which are restricted using regular tools." > > Not trying to give anyone grief. I'd just like to understand what > people expect to happen with FOSS that isn't happening with the vendor's > closed, but free tools. > Same thing that's happening with compilers all the time. Just a personal example: A log time ago I decided to make a few games for the ColecoVision console. The ColecoVision uses a Z80, and at the tie all the other homebrew game developers used an old DOS eval version of IAR within Windows. I used the free sdcc compiler. Not always being happy with the generated code I started improving it, ad later became the maintainer of the Z80 port. A few years ago I joined the group for theory of computer science at the univesity in Frankfurt as a PhD student. I found that I could apply graph structure theory in compiler construction. This resulted in some quite unusual optimizations in SDCC currently not found in any other compiler. Philipp From newsfish@newsfish Thu Aug 1 00:34:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Wed, 05 Aug 2015 18:50:11 -0400 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 22:48:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="9073"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Sivq91JD13kVyCFo6igWt" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:L2ZgX6lxLYJC+DgSicHPAFX2iR4= Xref: news.eternal-september.org comp.arch.fpga:8311 comp.lang.vhdl:3938 comp.lang.verilog:1182 On 8/5/2015 5:30 PM, Philipp Klaus Krause wrote: > On 05.08.2015 01:46, rickman wrote: >> On 8/4/2015 7:05 PM, Aleksandar Kuktin wrote: >>> >>> Hackability. If you have an itch, you can scratch it yourself with FOSS >>> tools. If you discover a bug, you can fix it yourself. If you want to >>> repurpose, optimize or otherwise change the tool, you can do it with >>> FOSS. >> >> That's great. But only important to a small few. I use tools to get >> work done. I have zero interest in digging into the code of the tools >> without a real need. I have not found any bugs in the vendor's tools >> that would make me want to spend weeks learning how they work in the, >> most likely, vain hope that I could fix them. >> >> I think FOSS is great and I am very happy to see that finally happen in >> an end to end toolchain for an FPGA. But it is statements like this >> that I don't understand, "An open-source toolchain for the IGLOO parts >> could be an unusually powerful tool in the hands of a creative >> designer", or this "Because open source tools allow exploration of >> techniques which are restricted using regular tools." >> >> Not trying to give anyone grief. I'd just like to understand what >> people expect to happen with FOSS that isn't happening with the vendor's >> closed, but free tools. >> > > Same thing that's happening with compilers all the time. > > Just a personal example: > A log time ago I decided to make a few games for the ColecoVision > console. The ColecoVision uses a Z80, and at the tie all the other > homebrew game developers used an old DOS eval version of IAR within > Windows. I used the free sdcc compiler. Not always being happy with the > generated code I started improving it, ad later became the maintainer of > the Z80 port. > A few years ago I joined the group for theory of computer science at the > univesity in Frankfurt as a PhD student. I found that I could apply > graph structure theory in compiler construction. This resulted in some > quite unusual optimizations in SDCC currently not found in any other > compiler. I think this is the point some are making. The examples of the utility of FOSS often point to more obscure examples which impact a relatively small number of users. I appreciate the fact that being able to tinker with the tools can be very useful to a few. But those few must have the need as well as the ability. With hardware development both are less likely to happen. Maybe I just don't have enough imagination. -- Rick From newsfish@newsfish Thu Aug 1 00:34:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 05 Aug 2015 18:58:03 -0400 Organization: A noiseless patient Spider Lines: 61 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 22:56:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="10092"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Laq0u8116h1ryMoOSQ4q3" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:CJlB8QTR5VU+ZnoUnq+B/cNbWZQ= Xref: news.eternal-september.org comp.lang.vhdl:3939 On 8/5/2015 5:22 PM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip, I wrote) >>> Often the useful hardware implementation of an algorithm is >>> completely different from the usual software implementations. >>> It is unusual for tools to figure that out. > >> That is pretty obvious if you give it a bit of thought. A CPU running >> software is a *HUGE* finite state machine (FSM) with the memory >> containing the majority of the state along with the fewer registers in >> the CPU. The memory contents are all accessed through a very large >> multiplexer and operations on this FSM are time multiplexed and >> controlled by a program stored in memory. > > In one of these newsgroups, a year or two ago, I called > microprocessors the biggest waste of transistors, for this reason. > > These days, billions of transistors to funnel data through a > (small number) of thousand transistor ALUs, and back out again. A very efficient use of the ALU while wasting so many elements in the memory mux. In reality the comparison is cost vs. the application needs. Often the things that need to be done can be done sequentially, even when they appear to be done in parallel. So while an FPGA may more fully utilize the transistor count, it often wastes the performance capabilities of those transistors while a CPU more fully exploits them. > With systolic arrays, it is often not hard to chain together a > large number of arithmetic blocks, each operating every clock cycle. > >> In an FPGA or ASIC the logic can all be designed in parallel with the >> much less happening sequentially. The design could be done in the same >> way with the very large multiplexers. The program can be done with >> logic rather than a stored program, but the access to the large FSM >> still requires a lot of multiplexers. So while it is possible to >> duplicate the actual CPU in an FPGA, it is seldom the best way to >> utilize an FPGA. The same problem can be implemented with a lot fewer >> gates by tailoring the algorithm to take advantage of the parallel >> nature of the FPGA and only implementing the specific data paths >> required by the problem. The generic CPU gains efficiency by the >> repetition of the regular arrays in memory which can be made both small >> and cheap but only with a sequential algorithm. > > There is the assumption that some things can be done in parallel, > but yes. Perhaps "parallel" is not the best term. In hardware they would be called concurrent. That doesn't mean the output of one isn't the input of another. It just means the two operations are working at the same time on separate hardware whether or not they are actually doing anything useful all the time. There are many ways to compare solutions to computing needs. Many like the familiarity of CPUs (every problem looks like a nail) while others like the flexibility of FPGAs (Swiss army knife). -- Rick From newsfish@newsfish Thu Aug 1 00:34:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 5 Aug 2015 23:50:45 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 50 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3940 rickman wrote: (snip, I wrote) >> In one of these newsgroups, a year or two ago, I called >> microprocessors the biggest waste of transistors, for this reason. >> These days, billions of transistors to funnel data through a >> (small number) of thousand transistor ALUs, and back out again. > A very efficient use of the ALU while wasting so many elements in the > memory mux. In reality the comparison is cost vs. the application > needs. Often the things that need to be done can be done sequentially, > even when they appear to be done in parallel. So while an FPGA may more > fully utilize the transistor count, it often wastes the performance > capabilities of those transistors while a CPU more fully exploits them. Yes. I was thinking about using either a microprocessor or FPGA to build a digital clock. In either case, a large fraction of the time there is nothing to do. (That is, relative to the switch rate.) Our home computers spend most of the time not doing anything useful. >> With systolic arrays, it is often not hard to chain together a >> large number of arithmetic blocks, each operating every clock cycle. >>> In an FPGA or ASIC the logic can all be designed in parallel with the >>> much less happening sequentially. The design could be done in the same >>> way with the very large multiplexers. The program can be done with >>> logic rather than a stored program, but the access to the large FSM >>> still requires a lot of multiplexers. (snip) >> There is the assumption that some things can be done in parallel, >> but yes. > Perhaps "parallel" is not the best term. In hardware they would be > called concurrent. That doesn't mean the output of one isn't the input > of another. It just means the two operations are working at the same > time on separate hardware whether or not they are actually doing > anything useful all the time. > There are many ways to compare solutions to computing needs. Many like > the familiarity of CPUs (every problem looks like a nail) while others > like the flexibility of FPGAs (Swiss army knife). Interesting way to say it. -- glen From newsfish@newsfish Thu Aug 1 00:34:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 05 Aug 2015 20:00:57 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 23:59:25 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22222"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18V807dWXQrexTnx5sra637" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:C9G8E8j820TXjwX8zaejCWDlf+8= Xref: news.eternal-september.org comp.lang.vhdl:3941 On 8/5/2015 7:50 PM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip, I wrote) >>> In one of these newsgroups, a year or two ago, I called >>> microprocessors the biggest waste of transistors, for this reason. > >>> These days, billions of transistors to funnel data through a >>> (small number) of thousand transistor ALUs, and back out again. > >> A very efficient use of the ALU while wasting so many elements in the >> memory mux. In reality the comparison is cost vs. the application >> needs. Often the things that need to be done can be done sequentially, >> even when they appear to be done in parallel. So while an FPGA may more >> fully utilize the transistor count, it often wastes the performance >> capabilities of those transistors while a CPU more fully exploits them. > > Yes. I was thinking about using either a microprocessor or FPGA > to build a digital clock. In either case, a large fraction of the > time there is nothing to do. (That is, relative to the switch rate.) Does the clock need to do anything special? Why a custom clock? >> There are many ways to compare solutions to computing needs. Many like >> the familiarity of CPUs (every problem looks like a nail) while others >> like the flexibility of FPGAs (Swiss army knife). > > Interesting way to say it. Sometimes it is hard to find a reasonable analogy. This one is as good as any I guess. Analogies have lots of compression, only so much fidelity. How's that for a metaphor? -- Rick From newsfish@newsfish Thu Aug 1 00:34:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Aleksandar Kuktin Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Sat, 8 Aug 2015 16:42:36 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 66 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> NNTP-Posting-Host: ahs5SQI0OQwb4BmKmMxtWg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: Pan/0.135 (Tomorrow I'll Wake Up and Scald Myself with Tea; Unknown) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.arch.fpga:8325 comp.lang.vhdl:3942 comp.lang.verilog:1183 The quoted post has beed turned upside-down for the purposes of my typing. On Wed, 05 Aug 2015 18:50:11 -0400, rickman wrote: > Maybe I just don't have enough imagination. A distinct possibility. On Wed, 05 Aug 2015 18:50:11 -0400, rickman wrote: > On 8/5/2015 5:30 PM, Philipp Klaus Krause wrote: >> On 05.08.2015 01:46, rickman wrote: >>> On 8/4/2015 7:05 PM, Aleksandar Kuktin wrote: >>>> >>>> Hackability. If you have an itch, you can scratch it yourself with >>>> FOSS tools. If you discover a bug, you can fix it yourself. If you >>>> want to repurpose, optimize or otherwise change the tool, you can do >>>> it with FOSS. >>> >>> That's great. But only important to a small few. Few matter. How many ISA designers are there? Yet, if they get good tools that let them creatively hack out the solution, we're all better of. Same with random dudes banging on some FPGA somewhere. You never know where the next thing you want will appear, and having good peer-reviewed tools creates more potential for good stuff to be made. >>> I use tools to get work done. I have zero interest in digging into >>> the code of the tools without a real need. I have not found any bugs >>> in the vendor's tools that would make me want to spend weeks learning >>> how they work in the, most likely, vain hope that I could fix them. Maybe you just didn't try hard enough? Maybe you did but didn't notice you found a gaping bug in vendor tools. >>> Not trying to give anyone grief. I'd just like to understand what >>> people expect to happen with FOSS that isn't happening with the >>> vendor's closed, but free tools. Maybe you would be able to generate a FPGA handheld device that can reconfigure itself on the fly. Like a smartphone^H^H^H^H^H^H^H^H^H^H PDA^H^H^H trikoder that runs on some energy-efficient MIPS and that has a scriptable (meaning CLI) synthesizer that you can feed random Verilog sources and then instantiate an Ethernet device so you can jack yourself in while at home, a FM radio to listen to while driving down the road, a TV receiver with HDMA output so you can view the news and maybe a vibrator or something for the evening. Anyway, that's what I want to have and can't right now but COULD have with FOSS tools (since I'm not gonna use QEMU to instantiate a VM so I could synthesize on my phone). >> This resulted in some quite unusual optimizations in SDCC currently >> not found in any other compiler. Okay, now we need to check out SDCC. > I think this is the point some are making. The examples of the utility > of FOSS often point to more obscure examples which impact a relatively > small number of users. I appreciate the fact that being able to tinker > with the tools can be very useful to a few. But those few must have the > need as well as the ability. > With hardware development both are less likely to happen. But they will happen nevertheless. From newsfish@newsfish Thu Aug 1 00:34:20 2024 X-Received: by 10.50.142.39 with SMTP id rt7mr8145094igb.5.1439141425119; Sun, 09 Aug 2015 10:30:25 -0700 (PDT) X-Received: by 10.140.96.138 with SMTP id k10mr172128qge.18.1439141424996; Sun, 09 Aug 2015 10:30:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!se8no1087996igc.0!news-out.google.com!78ni9027qge.1!nntp.google.com!69no4677791qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Aug 2015 10:30:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.135.41.219; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.135.41.219 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sun, 09 Aug 2015 17:30:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3943 I tried to convert it but i face many difficulties: with small code i done it without problem, but with more complexity code i found a lot of errors From newsfish@newsfish Thu Aug 1 00:34:20 2024 X-Received: by 10.50.178.165 with SMTP id cz5mr8155766igc.10.1439141425295; Sun, 09 Aug 2015 10:30:25 -0700 (PDT) X-Received: by 10.140.47.80 with SMTP id l74mr110542qga.42.1439141425175; Sun, 09 Aug 2015 10:30:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-03.inet.qwest.net!news.glorb.com!se8no1088002igc.0!news-out.google.com!78ni9030qge.1!nntp.google.com!z61no6041603qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Aug 2015 10:30:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.135.41.219; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.135.41.219 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0db7e6e7-3dec-429b-af4a-121f08f5ef13@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sun, 09 Aug 2015 17:30:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3944 I tried to convert it but i face many difficulties: with small code i done it without problem, but with more complexity code i found a lot of errors From newsfish@newsfish Thu Aug 1 00:34:20 2024 X-Received: by 10.129.111.132 with SMTP id k126mr15883846ywc.10.1439141994826; Sun, 09 Aug 2015 10:39:54 -0700 (PDT) X-Received: by 10.140.20.147 with SMTP id 19mr155621qgj.20.1439141994788; Sun, 09 Aug 2015 10:39:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z61no6042543qge.0!news-out.google.com!78ni9030qge.1!nntp.google.com!z61no6042540qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Aug 2015 10:39:54 -0700 (PDT) In-Reply-To: <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.135.41.219; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.135.41.219 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sun, 09 Aug 2015 17:39:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: news.eternal-september.org comp.lang.vhdl:3945 I have this feature "HDL Coder" but as what i said i found a lot of errors and tired from tying without got any result. From newsfish@newsfish Thu Aug 1 00:34:20 2024 X-Received: by 10.68.238.74 with SMTP id vi10mr25131348pbc.9.1439304160896; Tue, 11 Aug 2015 07:42:40 -0700 (PDT) X-Received: by 10.140.81.38 with SMTP id e35mr278170qgd.3.1439304160654; Tue, 11 Aug 2015 07:42:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!se8no1983760igc.0!news-out.google.com!78ni9206qge.1!nntp.google.com!69no317381qgi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 11 Aug 2015 07:42:40 -0700 (PDT) In-Reply-To: <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: About fpga board From: Thomas Stanka Injection-Date: Tue, 11 Aug 2015 14:42:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3946 Am Sonntag, 9. August 2015 19:39:57 UTC+2 schrieb abdrh...@gmail.com: > I have this feature "HDL=20 > Coder" but as what i said i found a lot of errors and tired from tying wi= thout got any result. I know how to read and detected that there is a library containing books, w= hat can I do to transplantate a human heart within 2 months? The only reasonable answer is to spend your time finding an expert to do th= is task.=20 Two month is an extrem small time to bring an unspecified project from Matl= ab to FPGA. Depending on the constraints, even a group of experts might hav= e trouble with this task. Ofc if you design is "Hello World"-Style, we can = help you teaching yourself to do this within 2 months, but as you already w= rote you lack fundamental prerequisites and detected your problem is more c= omplex than a simple example. regards Thomas From newsfish@newsfish Thu Aug 1 00:34:21 2024 X-Received: by 10.141.28.206 with SMTP id f197mr4680291qhe.10.1439371937962; Wed, 12 Aug 2015 02:32:17 -0700 (PDT) X-Received: by 10.140.20.56 with SMTP id 53mr266997qgi.9.1439371937948; Wed, 12 Aug 2015 02:32:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!69no545002qgi.0!news-out.google.com!b31ni6180qge.0!nntp.google.com!y105no14692qge.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 Aug 2015 02:32:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.135.47.199; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.135.47.199 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94785a02-8002-4ebb-93a3-0fc5fa39bb6a@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Wed, 12 Aug 2015 09:32:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3947 I understood what you said , I need long time to learn it, but yes i said t= hat i will learn it in two month, by that i mean i want to do this task wit= hin two month, but as what i understand from discussion it is also difficul= t, also the problem i cant send shot screen to this group, to allow you to = know what i am doing and what is the problem i faced, i am here because i n= eed help to do this task, it is clear that who are in this group have good = knowledge in fpga board, anyone feel he can help me please make me know tha= t by sending email on=20 abdrhblushi@gmail.com With regards From newsfish@newsfish Thu Aug 1 00:34:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Fri, 14 Aug 2015 22:46:02 -0400 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 15 Aug 2015 02:44:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="23795"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19T7cKEKJgQC42KDd2c+vQv" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:GdkOdUfoalZhZYwKnfoWQJ829gQ= Xref: news.eternal-september.org comp.lang.vhdl:3948 On 8/11/2015 10:42 AM, Thomas Stanka wrote: > Am Sonntag, 9. August 2015 19:39:57 UTC+2 schrieb abdrh...@gmail.com: >> I have this feature "HDL >> Coder" but as what i said i found a lot of errors and tired from tying without got any result. > > I know how to read and detected that there is a library containing books, what can I do to transplantate a human heart within 2 months? > > The only reasonable answer is to spend your time finding an expert to do this task. > Two month is an extrem small time to bring an unspecified project from Matlab to FPGA. Depending on the constraints, even a group of experts might have trouble with this task. Ofc if you design is "Hello World"-Style, we can help you teaching yourself to do this within 2 months, but as you already wrote you lack fundamental prerequisites and detected your problem is more complex than a simple example. I think the difficulty of coding HDL is a bit overstated. I think anyone with familiarity with coding in general can port a matlab program to an FPGA in two months. -- Rick From newsfish@newsfish Thu Aug 1 00:34:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Sat, 15 Aug 2015 04:27:19 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 28 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3949 rickman wrote: > On 8/11/2015 10:42 AM, Thomas Stanka wrote: (snip) >> Two month is an extrem small time to bring an unspecified >> project from Matlab to FPGA. Depending on the constraints, >> even a group of experts might have trouble with this task. >> Ofc if you design is "Hello World"-Style, we can help you >> teaching yourself to do this within 2 months, but as you >> already wrote you lack fundamental prerequisites and detected >> your problem is more complex than a simple example. > I think the difficulty of coding HDL is a bit overstated. I think > anyone with familiarity with coding in general can port a > matlab program to an FPGA in two months. Some people who are good at writing sequential software have a hard time thinking in terms of hardware and writing HDL. There are many things that can be written in Matlab that are easy to write in HDL, and many that are hard. Some might not be hard, but are hard if you want them to run fast, which is often the reason for a hardware implementation. -- glen From newsfish@newsfish Thu Aug 1 00:34:22 2024 X-Received: by 10.129.74.3 with SMTP id x3mr807913ywa.34.1439812413670; Mon, 17 Aug 2015 04:53:33 -0700 (PDT) X-Received: by 10.140.25.144 with SMTP id 16mr7761qgt.41.1439812413652; Mon, 17 Aug 2015 04:53:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!69no1628857qgi.0!news-out.google.com!78ni14231qge.1!nntp.google.com!y105no1099077qge.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Aug 2015 04:53:33 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <89930d0c-f240-41a9-b201-3c2d1fb34f95@googlegroups.com> Subject: Re: About fpga board From: Thomas Stanka Injection-Date: Mon, 17 Aug 2015 11:53:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3950 Am Samstag, 15. August 2015 04:46:05 UTC+2 schrieb rickman: > I think the difficulty of coding HDL is a bit overstated. I think > anyone with familiarity with coding in general can port a matlab program > to an FPGA in two months. That clearly depends on difficulty of design, which none of us can tell. Converting something well structured or very small projects will often take less than 2 months. But matlab from people knowing nothing about digital design tend to be in the other complexity class. I saw FPGA designs for which 2 months were not enough to bring ready verified RTL (written by experienced designer) to functioning bitstream because of hard constraints. regards, Thomas From newsfish@newsfish Thu Aug 1 00:34:22 2024 X-Received: by 10.107.28.2 with SMTP id c2mr7221955ioc.16.1439921993642; Tue, 18 Aug 2015 11:19:53 -0700 (PDT) X-Received: by 10.182.116.197 with SMTP id jy5mr54485obb.24.1439921993540; Tue, 18 Aug 2015 11:19:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!se8no6049515igc.0!news-out.google.com!o13ni16197igw.0!nntp.google.com!x6no1841674igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Aug 2015 11:19:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:282:900:3419:543d:1533:f14f:4757; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 2601:282:900:3419:543d:1533:f14f:4757 References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? From: kevin.m.neilson@gmail.com Injection-Date: Tue, 18 Aug 2015 18:19:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3951 This is one of the most nonsensical things I've ever heard. From newsfish@newsfish Thu Aug 1 00:34:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? Date: Tue, 18 Aug 2015 19:05:58 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 16 Message-ID: References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3952 kevin.m.neilson@gmail.com wrote: > This is one of the most nonsensical things I've ever heard. Is this supposed to be a question? OK, my news reader cuts of the subject line. If you put something in the subject line related to the question, also put it in the message. For most uses, you want a specific width. A better question is why std_logic instead of bit. (And why does std_logic have to be so long, and have a _ in it.) -- glen From newsfish@newsfish Thu Aug 1 00:34:23 2024 X-Received: by 10.182.142.72 with SMTP id ru8mr7742630obb.47.1439928718246; Tue, 18 Aug 2015 13:11:58 -0700 (PDT) X-Received: by 10.182.114.196 with SMTP id ji4mr56478obb.11.1439928718219; Tue, 18 Aug 2015 13:11:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!x6no1873106igd.0!news-out.google.com!o13ni16208igw.0!nntp.google.com!x6no1873105igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Aug 2015 13:11:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51049893-e2c3-4d93-afa4-425686c77924@googlegroups.com> Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? From: KJ Injection-Date: Tue, 18 Aug 2015 20:11:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1815 X-Received-Body-CRC: 3984828630 Xref: news.eternal-september.org comp.lang.vhdl:3953 On Tuesday, August 18, 2015 at 3:06:02 PM UTC-4, glen herrmannsfeldt wrote: > kev....neilson@gmail.... wrote: > > > This is one of the most nonsensical things I've ever heard. > > Is this supposed to be a question? > > OK, my news reader cuts of the subject line. If you put something > in the subject line related to the question, also put it in the message. > It was a question (asked and answered) back in Feb 2013 when the thread was first started...no idea what today's post is supposed to be about. KJ From newsfish@newsfish Thu Aug 1 00:34:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? Date: Tue, 18 Aug 2015 20:21:51 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 18 Message-ID: References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> <51049893-e2c3-4d93-afa4-425686c77924@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3954 KJ wrote: (snip, I wrote) >> OK, my news reader cuts of the subject line. If you put something >> in the subject line related to the question, also put it in the message. > It was a question (asked and answered) back in Feb 2013 when the > thread was first started...no idea what today's post is supposed > to be about. As I mostly write for synthesis, and not simulation, I have wondered why use std_logic instead of bit. My newsreader cut of the subject until I did the reply, when I saw the whole subject. It does sometimes bother me that VHDL makes the conversion between bit_vector and unsigned so complicated. (Compared to verilog.) -- glen From newsfish@newsfish Thu Aug 1 00:34:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? Date: Tue, 18 Aug 2015 16:28:02 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> <51049893-e2c3-4d93-afa4-425686c77924@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 18 Aug 2015 20:26:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="303e81565e2b5fa7258cbfe788d7b00f"; logging-data="14051"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Y1Lu8S54+07O6qrMX/W0b" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:38k1gYygUrKzjnHgg+H95PAmJ0c= Xref: news.eternal-september.org comp.lang.vhdl:3955 On 8/18/2015 4:21 PM, glen herrmannsfeldt wrote: > KJ wrote: > > (snip, I wrote) >>> OK, my news reader cuts of the subject line. If you put something >>> in the subject line related to the question, also put it in the message. > >> It was a question (asked and answered) back in Feb 2013 when the >> thread was first started...no idea what today's post is supposed >> to be about. > > As I mostly write for synthesis, and not simulation, I have wondered > why use std_logic instead of bit. My newsreader cut of the subject > until I did the reply, when I saw the whole subject. > > It does sometimes bother me that VHDL makes the conversion between > bit_vector and unsigned so complicated. (Compared to verilog.) VHDL lets you make it a simple function call. You just need to create the function. -- Rick From newsfish@newsfish Thu Aug 1 00:34:23 2024 X-Received: by 10.68.230.100 with SMTP id sx4mr6612917pbc.4.1440164148500; Fri, 21 Aug 2015 06:35:48 -0700 (PDT) X-Received: by 10.50.66.129 with SMTP id f1mr54061igt.4.1440164148463; Fri, 21 Aug 2015 06:35:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!se8no7701965igc.0!news-out.google.com!nt1ni10918igb.0!nntp.google.com!x6no2910786igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Aug 2015 06:35:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> <51049893-e2c3-4d93-afa4-425686c77924@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <470db89a-ba52-4a18-bc39-c7cd40ea6dc2@googlegroups.com> Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? From: Andy Injection-Date: Fri, 21 Aug 2015 13:35:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3956 On Tuesday, August 18, 2015 at 3:21:56 PM UTC-5, glen herrmannsfeldt wrote: > > It does sometimes bother me that VHDL makes the conversion between > bit_vector and unsigned so complicated. (Compared to verilog.) > > -- glen Use numeric_bit or numeric_bit_unsigned packages from the IEEE library. The latter defines arithmetic operators and conversions to/from integer for bit_vector. The former defines signed/unsigned types as unconstrained arrays of bit, closely related (and easily converted) to bit_vector, along with to/from integer conversion and arithmetic operators. All standard IEEE HVDL since 2008. Andy From newsfish@newsfish Thu Aug 1 00:34:24 2024 X-Received: by 10.182.29.70 with SMTP id i6mr7525351obh.27.1440178407154; Fri, 21 Aug 2015 10:33:27 -0700 (PDT) X-Received: by 10.50.147.39 with SMTP id th7mr90127igb.12.1440178407132; Fri, 21 Aug 2015 10:33:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!se8no7825601igc.0!news-out.google.com!nt1ni11079igb.0!nntp.google.com!x6no2994162igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Aug 2015 10:33:26 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=178.61.0.144; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 178.61.0.144 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ae05f82-6d7f-49f9-9b00-1da23034e98c@googlegroups.com> Subject: Re: C\C++ to VHDL Converter From: ahmedablak0@gmail.com Injection-Date: Fri, 21 Aug 2015 17:33:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3957 On Tuesday, September 17, 2002 at 12:27:21 PM UTC+3, DJohn wrote: > Hi all VHDL experts, > Is there any tools which can convert a C\C++ source file to VHDL . For > example If I have a C source code for a MP3 decoder , Can any tool can > convert it into VHDL equivalent. There is some facility in FPGA Advantage to > generate a wrapper VHDL for a C File , what exactly is that ? Does that > mean I can synthesize a C\C++ file by creating a VHDL Wrapper. > Please help Take a look at Handel-C. All you have to do is to rewrite couple of statements so that Handel-C compiles and generates VHDL, Verilog, EDIF, and SystemC for you. Use Mentor Graphic DK Design Suite 5. From newsfish@newsfish Thu Aug 1 00:34:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? Date: Fri, 21 Aug 2015 14:16:00 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <20130221101935.684c8a5c@rg.highlandtechnology.com> <1443d209-9f02-4550-b9dd-e141899701c0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 21 Aug 2015 18:14:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5409ba4ff362da07b493a33fe9fa84b5"; logging-data="26548"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1813x4L3OxZLbPv861KalBa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <1443d209-9f02-4550-b9dd-e141899701c0@googlegroups.com> Cancel-Lock: sha1:r+V3C7kO2JVPAhxaMfaJ7hvHQE0= Xref: news.eternal-september.org comp.lang.vhdl:3958 On 2/22/2013 11:40 AM, kevin.neilson@xilinx.com wrote: > This is the idea I'm getting. I haven't gotten a good answer about > why I should ever use slv, and I'm getting the idea it's only still > around because of inertia. The responses seem to be: > 1. SLV is better *because* of its limitations. You *could* use > signed/unsigned, but why, when you could use something that does even > less? > 2. But wait: with the new 2008 libraries, SLV is about as > good as signed/unsigned. (So why not just use signed/unsigned?) > 3. Other cores like CoreGen cores will use SLV, so you have to also in > order to interface them. (This is valid, although I try to avoid > CoreGen when possible, and I can always convert, possibly even in the > instantiation with 2008.) I don't really understand your questions. Why do you care what others think of the various types? I can assure you that there is no "intent" to the types other than what they *can* be used for. I have discussed similar issues with some of the people who worked on the VHDL standard and they aren't thinking of all the details of how you will want to use the language. Their intent was to give a framework within which you can do *lots* of things with minimal limitations but lots of protection. -- Rick From newsfish@newsfish Thu Aug 1 00:34:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "Tomas D." Newsgroups: comp.lang.vhdl Subject: Re: C\C++ to VHDL Converter Date: Sat, 22 Aug 2015 15:40:29 +0100 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <0ae05f82-6d7f-49f9-9b00-1da23034e98c@googlegroups.com> Injection-Date: Sat, 22 Aug 2015 14:38:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="d2848e2cfbf3375876b534c8a8ca5fdd"; logging-data="31444"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19s2D6wG9kH1u3UjS1zwlgw" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 Cancel-Lock: sha1:+KZYa0neZm8QgwIDa/GL9H+ldBs= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:3959 wrote in message news:0ae05f82-6d7f-49f9-9b00-1da23034e98c@googlegroups.com... > On Tuesday, September 17, 2002 at 12:27:21 PM UTC+3, DJohn wrote: >> Hi all VHDL experts, >> Is there any tools which can convert a C\C++ source file to VHDL . For >> example If I have a C source code for a MP3 decoder , Can any tool can >> convert it into VHDL equivalent. There is some facility in FPGA Advantage >> to >> generate a wrapper VHDL for a C File , what exactly is that ? Does that >> mean I can synthesize a C\C++ file by creating a VHDL Wrapper. >> Please help > > Take a look at Handel-C. All you have to do is to rewrite couple of > statements so that Handel-C compiles and generates VHDL, Verilog, EDIF, > and SystemC for you. Use Mentor Graphic DK Design Suite 5. Why not to have a look at Vivado HLS? Altera also has something, that will be available soon. From newsfish@newsfish Thu Aug 1 00:34:25 2024 X-Received: by 10.50.3.97 with SMTP id b1mr18290137igb.10.1440410689025; Mon, 24 Aug 2015 03:04:49 -0700 (PDT) X-Received: by 10.50.79.137 with SMTP id j9mr218914igx.15.1440410689009; Mon, 24 Aug 2015 03:04:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!se8no9362804igc.0!news-out.google.com!nt1ni13533igb.0!nntp.google.com!se8no9362800igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Aug 2015 03:04:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <818ec8f7-3658-47e4-982d-3c7c9db17083@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Mon, 24 Aug 2015 10:04:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3960 Hi, I've now added an example and made some smaller modification to simplify us= ing BVUL check and logging functionality with VUnit. The example testbench = (https://github.com/LarsAsplund/vunit/blob/bitvis-utility-library-integrati= on/examples/vhdl/bvul_integration/test/tb_bvul_integration.vhd) has a lot o= f comments so you can just read it to get the basic idea. If you have any c= omments you can post them with the BVUL integration issue (https://github.c= om/LarsAsplund/vunit/issues/54) or comment the code itself (https://github.= com/LarsAsplund/vunit/commit/ccd6ec83e3ff95d3518834eb9864298769621f47). The best way is of course to test it out for real. If you're new to VUnit y= ou can download and run the example like this git clone https://github.com/LarsAsplund/vunit.git cd vunit git checkout bitvis-utility-library-integration cd examples\vhdl\bvul_integration python run.py -b If you want to start out just using your simulator like you're used to you = can compile everything with the run script. python run.py -b --comp= ile In the bvul_integration directory you'll find vunit_out which contains the = compiled output. For example, vunit_out/modelsim is the directory to go to = if you're using ModelSim. The testbench is compiled into library lib.=20 The example is currently on its own branch, I will leave it there for a whi= le to see if there are any comments. After that I'll merge it to the VUnit = mainline. /Lars From newsfish@newsfish Thu Aug 1 00:34:25 2024 X-Received: by 10.13.203.77 with SMTP id n74mr22073590ywd.35.1440411012499; Mon, 24 Aug 2015 03:10:12 -0700 (PDT) X-Received: by 10.50.79.193 with SMTP id l1mr221426igx.2.1440411012398; Mon, 24 Aug 2015 03:10:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!69no3202584qgi.0!news-out.google.com!nt1ni13533igb.0!nntp.google.com!se8no9365147igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Aug 2015 03:10:11 -0700 (PDT) In-Reply-To: <818ec8f7-3658-47e4-982d-3c7c9db17083@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> <818ec8f7-3658-47e4-982d-3c7c9db17083@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Mon, 24 Aug 2015 10:10:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:3961 Note that you need a Github account to be able to create comments. /Lars From newsfish@newsfish Thu Aug 1 00:34:26 2024 X-Received: by 10.50.164.133 with SMTP id yq5mr3489665igb.1.1440690275897; Thu, 27 Aug 2015 08:44:35 -0700 (PDT) X-Received: by 10.50.22.103 with SMTP id c7mr97643igf.13.1440690275806; Thu, 27 Aug 2015 08:44:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.glorb.com!u8no1072252igq.0!news-out.google.com!nt1ni16645igb.0!nntp.google.com!u8no1072241igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Aug 2015 08:44:35 -0700 (PDT) In-Reply-To: <916391a6-2482-430d-9766-f1807b3139fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=101.222.169.101; posting-account=Z5mP8goAAAC1q1CatkgJob_1UBro830S NNTP-Posting-Host: 101.222.169.101 References: <916391a6-2482-430d-9766-f1807b3139fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: ethernet on spartan 3an From: lavanya.vlsi@gmail.com Injection-Date: Thu, 27 Aug 2015 15:44:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3962 Hello... Im lavanya working on ethernet of spartan 3 series .. I need the reference design of your code for my interfacing with my module in project.. Please u have also some questions but if i have reference design den i can work with my ip core code... Im also using a RTL code gof ethernet...i have completed its but im facing no communication between PC and FPGA Please kindly provide a referece code to me. Thanks & regards Lavanya From newsfish@newsfish Thu Aug 1 00:34:26 2024 X-Received: by 10.129.71.10 with SMTP id u10mr32269593ywa.51.1441236551960; Wed, 02 Sep 2015 16:29:11 -0700 (PDT) X-Received: by 10.50.221.104 with SMTP id qd8mr25357igc.1.1441236551912; Wed, 02 Sep 2015 16:29:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z77no346892qge.1!news-out.google.com!nt1ni22621igb.0!nntp.google.com!kq10no857259igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Sep 2015 16:29:11 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.31.106.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: "N." Injection-Date: Wed, 02 Sep 2015 23:29:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 25 Xref: news.eternal-september.org comp.lang.vhdl:3963 Hello, I'm trying to port a very old design that had formerly used the deprecated = STD_LOGIC_ARITH library with the new NUMERIC_STD library.=20 The old design has a substantial amount of unsigned additions of the follow= ing format :=20 c_slv <=3D a_slv + b_slv; or=20 c_slv <=3D a_slv + 10; I realize I should probably go through all of the code and recast it all to= "unsigned" to make it play nice with numeric_std, but was curious if it wa= s still acceptable in industry to use STD_LOGIC_UNSIGNED library with NUMER= IC_STD. As far as I can tell, it doesn't look like the overloaded functions= will conflict at all. PS: VHDL-2008 doesn't play nice with my current tools (ISE), so using NUMER= IC_STD_UNSIGNED is out. Thanks. From newsfish@newsfish Thu Aug 1 00:34:26 2024 X-Received: by 10.66.122.102 with SMTP id lr6mr43713356pab.44.1441286436858; Thu, 03 Sep 2015 06:20:36 -0700 (PDT) X-Received: by 10.50.28.19 with SMTP id x19mr159240igg.16.1441286436815; Thu, 03 Sep 2015 06:20:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no825495igb.0!news-out.google.com!nt1ni23135igb.0!nntp.google.com!kq10no1102915igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Sep 2015 06:20:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.75.45; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.75.45 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: Jim Lewis Injection-Date: Thu, 03 Sep 2015 13:20:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3964 std_logic_unsigned will work fine with Numeric_std. Actually for a little humor, there are conflicts between std_logic_arith an= d std_logic_unsigned which cause ambiguity that do not exist in numeric_std= . Hence, not only does it work with numeric_std, it works better with nume= ric_std than with std_logic_arith. :) My rule for RTL is that if it is math, it should be in either type signed o= r unsigned. =20 I also try to keep a pragmatic rule for updates and do not change old code = unless it uses type unsigned or signed as a port or something internal to i= t is changing and there value to switching to the numeric_std package - ie:= this block is going to be around for quite some time in the future. From newsfish@newsfish Thu Aug 1 00:34:27 2024 X-Received: by 10.52.107.106 with SMTP id hb10mr25543640vdb.1.1441292246461; Thu, 03 Sep 2015 07:57:26 -0700 (PDT) X-Received: by 10.50.152.6 with SMTP id uu6mr174800igb.4.1441292246423; Thu, 03 Sep 2015 07:57:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no472133qge.0!news-out.google.com!nt1ni23183igb.0!nntp.google.com!kq10no1145240igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Sep 2015 07:57:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.35.35.35 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <05177f6e-3595-4590-9570-403e1359dc1a@googlegroups.com> Subject: Re: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: "N." Injection-Date: Thu, 03 Sep 2015 14:57:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3965 On Thursday, September 3, 2015 at 8:20:39 AM UTC-5, Jim Lewis wrote: > std_logic_unsigned will work fine with Numeric_std. >=20 > Actually for a little humor, there are conflicts between std_logic_arith = and std_logic_unsigned which cause ambiguity that do not exist in numeric_s= td. Hence, not only does it work with numeric_std, it works better with nu= meric_std than with std_logic_arith. :) >=20 > My rule for RTL is that if it is math, it should be in either type signed= or unsigned. =20 >=20 > I also try to keep a pragmatic rule for updates and do not change old cod= e unless it uses type unsigned or signed as a port or something internal to= it is changing and there value to switching to the numeric_std package - i= e: this block is going to be around for quite some time in the future. Thanks Jim.=20 My design's ports are still set at std_logic and std_logic_vector, mainly d= ue to the fact that the numerous cores I'm using generated by CoreGen are s= till using this convention. I will think about converting the math related = ports to unsigned/signed for future designs. BTW, I enjoyed your write-up on VHDL math tricks :) Very good reference. From newsfish@newsfish Thu Aug 1 00:34:27 2024 X-Received: by 10.107.32.212 with SMTP id g203mr472828iog.25.1441305242766; Thu, 03 Sep 2015 11:34:02 -0700 (PDT) X-Received: by 10.50.50.101 with SMTP id b5mr199836igo.12.1441305242709; Thu, 03 Sep 2015 11:34:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no5022igb.0!news-out.google.com!f6ni14igi.0!nntp.google.com!kq10no5017igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Sep 2015 11:34:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c97d2e0-49ab-45f9-9c70-c6654841f8d2@googlegroups.com> Subject: Re: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: Andy Injection-Date: Thu, 03 Sep 2015 18:34:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3966 On Thursday, September 3, 2015 at 8:20:39 AM UTC-5, Jim Lewis wrote: > My rule for RTL is that if it is math, it should be in either type signed or unsigned. Agreed, and I would add the IEEE VHDL fixed point types (ufixed or sfixed) and floating point type (float) to that list. Andy From newsfish@newsfish Thu Aug 1 00:34:27 2024 X-Received: by 10.107.157.11 with SMTP id g11mr4235035ioe.7.1441384418065; Fri, 04 Sep 2015 09:33:38 -0700 (PDT) X-Received: by 10.50.30.197 with SMTP id u5mr71123igh.5.1441384418049; Fri, 04 Sep 2015 09:33:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!kq10no516469igb.0!news-out.google.com!nt1ni919igb.0!nntp.google.com!kq10no516463igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Sep 2015 09:33:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f818d03-2cc1-41ad-bc18-65bb417b8af7@googlegroups.com> Subject: PSL syntax help From: niv Injection-Date: Fri, 04 Sep 2015 16:33:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 33 Xref: news.eternal-september.org comp.lang.vhdl:3967 Hi, I'm trying to get a PSL vunit to work, but having some trouble (as usual)! (I'm using Modelsim 10.1d) The vunit is as follows: vunit interface_check (iface(struct)) { default clock is clk; assert never {wren AND fifo_full}; -- works OK. assert never {rden AND fifo_empty}; -- works OK. assert always (req -> next[2](gnt)); -- works OK. assert always (req -> next[3](gnt)); -- works OK. assert always (req -> next[4](gnt)); -- works OK. assert always (req -> next[5](gnt)); -- works OK. -- BUT, I should be able to replace above 4 lines with something like: assert always (req -> next[*2..5](gnt)); -- which does not compile. -- OR assert always (req -> next[*2:5](gnt)); -- which does not compile. } Could someone please explain what I'm doing wrong? I've tried all sorts of minor variations, but can't get the composite assertion to compile. Regards, Niv. From newsfish@newsfish Thu Aug 1 00:34:28 2024 X-Received: by 10.182.241.72 with SMTP id wg8mr5367365obc.2.1441399634701; Fri, 04 Sep 2015 13:47:14 -0700 (PDT) X-Received: by 10.50.66.205 with SMTP id h13mr93349igt.10.1441399634644; Fri, 04 Sep 2015 13:47:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!kq10no546571igb.0!news-out.google.com!f6ni1090igi.0!nntp.google.com!kq10no642674igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Sep 2015 13:47:13 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.210.224.219; posting-account=2PprfAoAAADxNzeuAYJhBnpsN-StXr74 NNTP-Posting-Host: 197.210.224.219 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Subject: pls i need a vhdl code for a 16bit slicer From: Aderemi Injection-Date: Fri, 04 Sep 2015 20:47:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3968 pls i need a vhdl code for a 16bit slicer From newsfish@newsfish Thu Aug 1 00:34:28 2024 X-Received: by 10.50.50.179 with SMTP id d19mr8556904igo.6.1441456997982; Sat, 05 Sep 2015 05:43:17 -0700 (PDT) X-Received: by 10.50.72.16 with SMTP id z16mr26985igu.8.1441456997925; Sat, 05 Sep 2015 05:43:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!kq10no916131igb.0!news-out.google.com!f6ni1733igi.0!nntp.google.com!kq10no730602igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Sep 2015 05:43:17 -0700 (PDT) In-Reply-To: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:f074:1ce8:5191:5aa; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:f074:1ce8:5191:5aa References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: pls i need a vhdl code for a 16bit slicer From: KJ Injection-Date: Sat, 05 Sep 2015 12:43:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 7 Xref: news.eternal-september.org comp.lang.vhdl:3969 On Friday, September 4, 2015 at 4:47:18 PM UTC-4, Aderemi wrote: > pls i need a vhdl code for a 16bit slicer Code can be found in a file that is typically opened with a text editor. Without you providing any real requirements, don't expect to get any sort of useful feedback from anybody. Kevin From newsfish@newsfish Thu Aug 1 00:34:28 2024 X-Received: by 10.107.159.132 with SMTP id i126mr2526319ioe.23.1441465169389; Sat, 05 Sep 2015 07:59:29 -0700 (PDT) X-Received: by 10.50.122.103 with SMTP id lr7mr16078igb.10.1441465169334; Sat, 05 Sep 2015 07:59:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!kq10no969076igb.0!news-out.google.com!f6ni1813igi.0!nntp.google.com!kq10no771022igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Sep 2015 07:59:28 -0700 (PDT) In-Reply-To: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.226.127.233; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 83.226.127.233 References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a6d815f-775f-4305-8cb8-1b5d4c916983@googlegroups.com> Subject: pls i need a vhdl code for a 16bit slicer From: olof.kraigher@gmail.com Injection-Date: Sat, 05 Sep 2015 14:59:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 5 Xref: news.eternal-september.org comp.lang.vhdl:3970 It is unlikely that someone will help you with such a vague question. You m= ake an impression of being a student that is either way over your head or s= imply lazy or both. In either case getting the code will not help you more = than possibly cheat an assignment. To be employable in the future you actua= lly need to learn something. If you do not realize this you are wasting you= r time. From newsfish@newsfish Thu Aug 1 00:34:29 2024 X-Received: by 10.107.19.153 with SMTP id 25mr9037004iot.24.1441465237690; Sat, 05 Sep 2015 08:00:37 -0700 (PDT) X-Received: by 10.50.12.69 with SMTP id w5mr124652igb.13.1441465237623; Sat, 05 Sep 2015 08:00:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!enother.net!enother.net!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!kq10no771440igb.0!news-out.google.com!f6ni1813igi.0!nntp.google.com!kq10no771429igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Sep 2015 08:00:36 -0700 (PDT) In-Reply-To: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.226.127.233; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 83.226.127.233 References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: pls i need a vhdl code for a 16bit slicer From: olof.kraigher@gmail.com Injection-Date: Sat, 05 Sep 2015 15:00:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1551 X-Received-Body-CRC: 4221742351 Xref: news.eternal-september.org comp.lang.vhdl:3971 It is unlikely that someone will help you with such a vague question. You m= ake an impression of being a student that is either way over your head or s= imply lazy or both. In either case getting the code will not help you more = than possibly cheat an assignment. To be employable in the future you actua= lly need to learn something. If you do not realize this you are wasting you= r time. From newsfish@newsfish Thu Aug 1 00:34:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: pls i need a vhdl code for a 16bit slicer Date: Sat, 5 Sep 2015 11:49:50 -0400 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 5 Sep 2015 15:48:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="17625"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX188c+eOzCFDuEg39azBbTxW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Cancel-Lock: sha1:uVyCwXW/w2zrHpiBwr0bWNPjPYs= Xref: news.eternal-september.org comp.lang.vhdl:3972 On 9/4/2015 4:47 PM, Aderemi wrote: > > > pls i need a vhdl code for a 16bit slicer I have code for a VHDL 16 bit dicer, but not for the slicer. -- Rick From newsfish@newsfish Thu Aug 1 00:34:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: pls i need a vhdl code for a 16bit slicer Date: Sat, 5 Sep 2015 17:06:03 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 16 Message-ID: References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:3973 rickman wrote: > On 9/4/2015 4:47 PM, Aderemi wrote: >> pls i need a vhdl code for a 16bit slicer > I have code for a VHDL 16 bit dicer, but not for the slicer. And I suppose it came from Ronco? I am pretty sure they sell the slicer, too. https://en.wikipedia.org/wiki/Ronco (and who remembers the Bass-o-matic? -- glen From newsfish@newsfish Thu Aug 1 00:34:30 2024 X-Received: by 10.52.30.163 with SMTP id t3mr13725972vdh.14.1441553849512; Sun, 06 Sep 2015 08:37:29 -0700 (PDT) X-Received: by 10.50.41.34 with SMTP id c2mr154670igl.1.1441553849468; Sun, 06 Sep 2015 08:37:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no1170118qge.1!news-out.google.com!f6ni2823igi.0!nntp.google.com!kq10no1425592igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Sep 2015 08:37:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.177.48.161; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.177.48.161 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: bknpk@hotmail.com Injection-Date: Sun, 06 Sep 2015 15:37:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3974 On Thursday, September 3, 2015 at 2:29:19 AM UTC+3, N. wrote: > Hello, >=20 > I'm trying to port a very old design that had formerly used the deprecate= d STD_LOGIC_ARITH library with the new NUMERIC_STD library.=20 >=20 > The old design has a substantial amount of unsigned additions of the foll= owing format :=20 >=20 > c_slv <=3D a_slv + b_slv; >=20 > or=20 >=20 > c_slv <=3D a_slv + 10; >=20 ... use ieee.STD_LOGIC_UNSIGNED."+"; ... learn_cnti <=3D=20 --load mem_do(43 downto 40) when fsm_ps(c_loc_read1) =3D '1' else --increment std_logic_vector(unsigned(learn_cntq) + "0001") when=20 fsm_ps(c_loc_ave0) =3D '1'=20 else learn_cntq; ... For more info see vhdl examples at http://bknpk.ddns.net/my_web/MiscellaneousHW/MiscellaneousHW.html >=20 > I realize I should probably go through all of the code and recast it all = to "unsigned" to make it play nice with numeric_std, but was curious if it = was still acceptable in industry to use STD_LOGIC_UNSIGNED library with NUM= ERIC_STD. As far as I can tell, it doesn't look like the overloaded functio= ns will conflict at all. >=20 >=20 > PS: VHDL-2008 doesn't play nice with my current tools (ISE), so using NUM= ERIC_STD_UNSIGNED is out. >=20 > Thanks. From newsfish@newsfish Thu Aug 1 00:34:30 2024 X-Received: by 10.107.158.84 with SMTP id h81mr17718174ioe.15.1441609197928; Sun, 06 Sep 2015 23:59:57 -0700 (PDT) X-Received: by 10.50.79.137 with SMTP id j9mr174981igx.15.1441609197906; Sun, 06 Sep 2015 23:59:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no1693891igb.0!news-out.google.com!nt1ni3282igb.0!nntp.google.com!kq10no1263033igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Sep 2015 23:59:57 -0700 (PDT) In-Reply-To: <7c961a05-b447-4910-94b4-9f690a23571d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.23.60.4; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 185.23.60.4 References: <7c961a05-b447-4910-94b4-9f690a23571d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9fc04b7a-f8a7-4113-8051-a85d1dc68382@googlegroups.com> Subject: Re: Can we log internal signals from a testbench in VHDL? From: bknpk@hotmail.com Injection-Date: Mon, 07 Sep 2015 06:59:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3975 You can build your own. ... use STD.textio.all; use IEEE.STD_LOGIC_TEXTIO.all; ... write(my_line, string'("presState ")); write(my_line, string'(STATETYPE'image(presState))); write(my_line, string'(" at ")); write(my_line, now); writeline(output, my_line); For more details see http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_print_debug_tip.html To print instance path: 1.if(newByte = '1') then 2. write (my_line, string'("path ")); 3. write (my_line, clk'path_name);--short .... http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_path_name_print.html On Friday, November 9, 2012 at 6:08:07 AM UTC+2, py wrote: > Hi, > > At the end of a test, I would like to collect some stat in the following manner: > > assert false report "Max counter is " & str(counter_value) severity note > > This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer? I heard that for verilog, it is possible to reference internal signal like outer_layer.inner_layer.signal_name > > > Thanks From newsfish@newsfish Thu Aug 1 00:34:30 2024 X-Received: by 10.182.213.73 with SMTP id nq9mr8710795obc.33.1441646038885; Mon, 07 Sep 2015 10:13:58 -0700 (PDT) X-Received: by 10.50.77.39 with SMTP id p7mr196270igw.7.1441646038824; Mon, 07 Sep 2015 10:13:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!kq10no1471331igb.0!news-out.google.com!nt1ni3702igb.0!nntp.google.com!kq10no1960327igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Sep 2015 10:13:58 -0700 (PDT) In-Reply-To: <6f818d03-2cc1-41ad-bc18-65bb417b8af7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <6f818d03-2cc1-41ad-bc18-65bb417b8af7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0711915a-6221-4732-ac9a-f7566258f464@googlegroups.com> Subject: Re: PSL syntax help From: niv Injection-Date: Mon, 07 Sep 2015 17:13:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3976 Figured out I was using the Verilog syntax... [*2..5] should be [*2 to 5] for VHDL. (Doh!) However, I get assertion fails with: assert always (req -> next[*2 to 5](gnt)); -- compiles OK but gets assertion error or even with: assert always (req -> next gnt[*2 to 5]); Not sure which is the correct syntax for what I need to combine the 4 working assertions into a single one?? Any help most welcome. From newsfish@newsfish Thu Aug 1 00:34:31 2024 X-Received: by 10.13.239.197 with SMTP id y188mr25784157ywe.0.1441732428562; Tue, 08 Sep 2015 10:13:48 -0700 (PDT) X-Received: by 10.50.111.43 with SMTP id if11mr243602igb.1.1441732428495; Tue, 08 Sep 2015 10:13:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no1651234qge.0!news-out.google.com!nt1ni4586igb.0!nntp.google.com!kq10no2470632igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Sep 2015 10:13:47 -0700 (PDT) In-Reply-To: <0711915a-6221-4732-ac9a-f7566258f464@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <6f818d03-2cc1-41ad-bc18-65bb417b8af7@googlegroups.com> <0711915a-6221-4732-ac9a-f7566258f464@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: PSL syntax help From: niv Injection-Date: Tue, 08 Sep 2015 17:13:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3977 assert always (req -> next_a[2 to 5](gnt)); This does thejob. (Phew)! From newsfish@newsfish Thu Aug 1 00:34:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: ISCAS 95 Date: Sat, 12 Sep 2015 21:59:37 +0300 Organization: A noiseless patient Spider Lines: 2 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 12 Sep 2015 18:57:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="30967"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Hb8asIXkV8B1iLSvqFN05KAH7QauVufg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:HPfofOjg/xd2CqnBhJlY9+3d7pw= Xref: news.eternal-september.org comp.lang.vhdl:3978 Do you know where I can download these benchmarks, preferably in RTL VHD? I would appreciate any other combinatorial benchmarks. From newsfish@newsfish Thu Aug 1 00:34:31 2024 X-Received: by 10.182.233.195 with SMTP id ty3mr33227826obc.44.1443096538290; Thu, 24 Sep 2015 05:08:58 -0700 (PDT) X-Received: by 10.50.134.169 with SMTP id pl9mr177706igb.13.1443096538269; Thu, 24 Sep 2015 05:08:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no9045435igb.0!news-out.google.com!n2ni10426igy.0!nntp.google.com!kq10no8580189igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 05:08:57 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Result is U From: zhangth1991@gmail.com Injection-Date: Thu, 24 Sep 2015 12:08:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3979 Hi, I have a question about the behavioral code of multiplier. I used two generate loops but after calculation, the output is Undesigned. Anyone can help me? The code is as followed: --multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Multiplier_VHDL is GENERIC (WIDTH:INTEGER); PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); end entity Multiplier_VHDL; architecture Behavioral of Multiplier_VHDL is signal a_temp:std_logic_vector(width-1 downto 0); signal a_temp_1:std_logic_vector(width-1 downto 0); signal a_temp_2:std_logic_vector(width-1 downto 0); signal cout_a:std_logic_vector(width-1 downto 0); signal b_temp:std_logic_vector(width-1 downto 0); signal b_temp_1:std_logic_vector(width-1 downto 0); signal b_temp_2:std_logic_vector(width-1 downto 0); signal cout_b:std_logic_vector(width-1 downto 0); signal y_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal y_ready:std_logic_vector(2*width-1 downto 0); signal cin:std_logic_vector(2*width downto 0); signal cout:std_logic_vector(2*width-1 downto 0); signal mid_temp_a:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); begin --inverse calculation of a iteration_a1: for i in 0 to width-1 generate a_temp_1(i)<= not a(i); end generate iteration_a1; a_temp_2(0)<=a_temp_1(0) xor '1'; cout_a(0)<=a_temp_1(0) and '1'; iteration_a2: for i in 1 to width-1 generate a_temp_2(i)<=a_temp_1(i) xor cout_a(i-1); cout_a(i)<=a_temp_1(i) and cout_a(i-1); end generate iteration_a2; a_temp<=a when a(width-1)='0' else a_temp_2; --inverse calculation of b iteration_b1: for i in 0 to width-1 generate b_temp_1(i)<= not b(i); end generate iteration_b1; b_temp_2(0)<=b_temp_1(0) xor '1'; cout_b(0)<=b_temp_1(0) and '1'; iteration_b2: for i in 1 to width-1 generate b_temp_2(i)<=b_temp_1(i) xor cout_b(i-1); cout_b(i)<=b_temp_1(i) and cout_b(i-1); end generate iteration_b2; b_temp<=b when b(width-1)='0' else b_temp_2; mid_temp_a(width-1 downto 0)<=a_temp; iteration_out: for i in 0 to width-1 generate cin(0)<='0'; mid_temp_a<=mid_temp_a(2*width-2 downto 0) & '0'; mid_temp<=mid_temp_a when b(i)='1' else (others=>'0') when b(i)='0'; iteration_in: --y_temp is a while mid_temp is b for j in 0 to 2*width-1 generate y_ready1(j)<=y_temp(j) xor mid_temp(j) xor cin(j); cout(j)<=(y_temp(j) and mid_temp(j)) or (y_temp(j) and cin(j)) or (cin(j) and mid_temp(j)); cin(j+1)<=cout(j); end generate iteration_in; y_temp<=y_ready1; end generate iteration_out; y<=y_ready; end architecture Behavioral; From newsfish@newsfish Thu Aug 1 00:34:32 2024 X-Received: by 10.13.222.196 with SMTP id h187mr913648ywe.0.1443117654215; Thu, 24 Sep 2015 11:00:54 -0700 (PDT) X-Received: by 10.50.66.144 with SMTP id f16mr38360igt.14.1443117654148; Thu, 24 Sep 2015 11:00:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no3963230qge.0!news-out.google.com!n2ni10681igy.0!nntp.google.com!kq10no9317957igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 11:00:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <219e2304-6fa4-4b07-a992-4c27f70cb8f2@googlegroups.com> Subject: VUnit, the Free and Open Source Unit Testing Framework for VHDL, Now Supports Active-HDL and Riviera-PRO From: Lars Asplund Injection-Date: Thu, 24 Sep 2015 18:00:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3980 Two weeks ago we got our partner licenses from Aldec and now we've released= a new VUnit version supporting both Active-HDL and Riviera-PRO (in additio= n to ModelSim and GHDL). You can find more information here https://www.lin= kedin.com/pulse/short-introduction-vunit-lars-asplund or go directly to htt= ps://github.com/LarsAsplund/vunit to download your copy or just do $ git clone https://github.com/LarsAsplund/vunit.git $ cd vunit $ python setup.py install to get started. /Lars From newsfish@newsfish Thu Aug 1 00:34:32 2024 X-Received: by 10.13.213.215 with SMTP id x206mr1062966ywd.7.1443119624318; Thu, 24 Sep 2015 11:33:44 -0700 (PDT) X-Received: by 10.50.77.70 with SMTP id q6mr381388igw.4.1443119624287; Thu, 24 Sep 2015 11:33:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no3977773qge.0!news-out.google.com!z4ni952ign.0!nntp.google.com!kq10no8915313igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 11:33:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Subject: Multiplier using 1 bit full adder problem From: zhangth1991@gmail.com Injection-Date: Thu, 24 Sep 2015 18:33:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3803 X-Received-Body-CRC: 2194389024 Xref: news.eternal-september.org comp.lang.vhdl:3981 I have a problem , when I execute my code, the output is undesigned. Anyone can help me? My code is as followed --multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Multiplier_VHDL is GENERIC (WIDTH:INTEGER); PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); end entity Multiplier_VHDL; architecture Behavioral of Multiplier_VHDL is signal a_temp:std_logic_vector(width-1 downto 0); signal a_temp_1:std_logic_vector(width-1 downto 0); signal a_temp_2:std_logic_vector(width-1 downto 0); signal cout_a:std_logic_vector(width-1 downto 0); signal b_temp:std_logic_vector(width-1 downto 0); signal b_temp_1:std_logic_vector(width-1 downto 0); signal b_temp_2:std_logic_vector(width-1 downto 0); signal cout_b:std_logic_vector(width-1 downto 0); signal y_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal y_ready:std_logic_vector(2*width-1 downto 0); signal cin:std_logic_vector(2*width downto 0); signal cout:std_logic_vector(2*width-1 downto 0); signal mid_temp_a:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); begin --inverse calculation of a iteration_a1: for i in 0 to width-1 generate a_temp_1(i)<= not a(i); end generate iteration_a1; a_temp_2(0)<=a_temp_1(0) xor '1'; cout_a(0)<=a_temp_1(0) and '1'; iteration_a2: for i in 1 to width-1 generate a_temp_2(i)<=a_temp_1(i) xor cout_a(i-1); cout_a(i)<=a_temp_1(i) and cout_a(i-1); end generate iteration_a2; a_temp<=a when a(width-1)='0' else a_temp_2; --inverse calculation of b iteration_b1: for i in 0 to width-1 generate b_temp_1(i)<= not b(i); end generate iteration_b1; b_temp_2(0)<=b_temp_1(0) xor '1'; cout_b(0)<=b_temp_1(0) and '1'; iteration_b2: for i in 1 to width-1 generate b_temp_2(i)<=b_temp_1(i) xor cout_b(i-1); cout_b(i)<=b_temp_1(i) and cout_b(i-1); end generate iteration_b2; b_temp<=b when b(width-1)='0' else b_temp_2; mid_temp_a(width-1 downto 0)<=a_temp; iteration_out: for i in 0 to width-1 generate cin(0)<='0'; mid_temp_a<=mid_temp_a(2*width-2 downto 0) & '0'; mid_temp<=mid_temp_a when b(i)='1' else (others=>'0') when b(i)='0'; iteration_in: --y_temp is a while mid_temp is b for j in 0 to 2*width-1 generate y_ready1(j)<=y_temp(j) xor mid_temp(j) xor cin(j); cout(j)<=(y_temp(j) and mid_temp(j)) or (y_temp(j) and cin(j)) or (cin(j) and mid_temp(j)); cin(j+1)<=cout(j); end generate iteration_in; y_temp<=y_ready1; end generate iteration_out; y<=y_ready; end architecture Behavioral; From newsfish@newsfish Thu Aug 1 00:34:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder problem Date: Thu, 24 Sep 2015 16:50:33 -0400 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Sep 2015 20:48:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="87b10dc1a89c821d7d807dd85a2825be"; logging-data="18806"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX193MeCU331Dr24BrsdhOlPS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Cancel-Lock: sha1:+Id2rnVBvKqvCSom3reJ0EOu9u8= Xref: news.eternal-september.org comp.lang.vhdl:3982 On 9/24/2015 2:33 PM, zhangth1991@gmail.com wrote: > I have a problem , when I execute my code, the output is undesigned. Of course your output is designed. You must be looking at the output wrong. > Anyone can help me? My code is as followed > --multiplier > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity Multiplier_VHDL is > GENERIC (WIDTH:INTEGER); > PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); > end entity Multiplier_VHDL; > > architecture Behavioral of Multiplier_VHDL is > > signal a_temp:std_logic_vector(width-1 downto 0); > signal a_temp_1:std_logic_vector(width-1 downto 0); > signal a_temp_2:std_logic_vector(width-1 downto 0); > signal cout_a:std_logic_vector(width-1 downto 0); > > signal b_temp:std_logic_vector(width-1 downto 0); > signal b_temp_1:std_logic_vector(width-1 downto 0); > signal b_temp_2:std_logic_vector(width-1 downto 0); > signal cout_b:std_logic_vector(width-1 downto 0); > signal y_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal y_ready:std_logic_vector(2*width-1 downto 0); > signal cin:std_logic_vector(2*width downto 0); > signal cout:std_logic_vector(2*width-1 downto 0); > signal mid_temp_a:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > > begin > --inverse calculation of a > iteration_a1: > for i in 0 to width-1 generate > a_temp_1(i)<= not a(i); > end generate iteration_a1; > a_temp_2(0)<=a_temp_1(0) xor '1'; > cout_a(0)<=a_temp_1(0) and '1'; > iteration_a2: > for i in 1 to width-1 generate > a_temp_2(i)<=a_temp_1(i) xor cout_a(i-1); > cout_a(i)<=a_temp_1(i) and cout_a(i-1); > end generate iteration_a2; > a_temp<=a when a(width-1)='0' else > a_temp_2; > --inverse calculation of b > iteration_b1: > for i in 0 to width-1 generate > b_temp_1(i)<= not b(i); > end generate iteration_b1; > b_temp_2(0)<=b_temp_1(0) xor '1'; > cout_b(0)<=b_temp_1(0) and '1'; > iteration_b2: > for i in 1 to width-1 generate > b_temp_2(i)<=b_temp_1(i) xor cout_b(i-1); > cout_b(i)<=b_temp_1(i) and cout_b(i-1); > end generate iteration_b2; > b_temp<=b when b(width-1)='0' else > b_temp_2; > mid_temp_a(width-1 downto 0)<=a_temp; > > iteration_out: > for i in 0 to width-1 generate > cin(0)<='0'; > mid_temp_a<=mid_temp_a(2*width-2 downto 0) & '0'; > mid_temp<=mid_temp_a when b(i)='1' else > (others=>'0') when b(i)='0'; > iteration_in: > --y_temp is a while mid_temp is b > for j in 0 to 2*width-1 generate > y_ready1(j)<=y_temp(j) xor mid_temp(j) xor cin(j); > cout(j)<=(y_temp(j) and mid_temp(j)) or (y_temp(j) and cin(j)) or (cin(j) and mid_temp(j)); > cin(j+1)<=cout(j); > end generate iteration_in; > y_temp<=y_ready1; > > end generate iteration_out; > y<=y_ready; > > > > > > > end architecture Behavioral; -- Rick From newsfish@newsfish Thu Aug 1 00:34:33 2024 X-Received: by 10.66.100.233 with SMTP id fb9mr1571900pab.24.1443128375229; Thu, 24 Sep 2015 13:59:35 -0700 (PDT) X-Received: by 10.50.136.163 with SMTP id qb3mr393313igb.12.1443128375158; Thu, 24 Sep 2015 13:59:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!kq10no9443055igb.0!news-out.google.com!n2ni10802igy.0!nntp.google.com!kq10no9032420igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 13:59:34 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> Subject: Re: Multiplier using 1 bit full adder problem From: zhangth1991@gmail.com Injection-Date: Thu, 24 Sep 2015 20:59:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1153 X-Received-Body-CRC: 404930816 Xref: news.eternal-september.org comp.lang.vhdl:3983 no, the output is U all the time From newsfish@newsfish Thu Aug 1 00:34:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder problem Date: Thu, 24 Sep 2015 17:37:56 -0400 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Sep 2015 21:36:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="87b10dc1a89c821d7d807dd85a2825be"; logging-data="30890"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ILM1QaOYLepB/YpkiWeWo" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> Cancel-Lock: sha1:Pm2mQ/f/AOhS1tHdD51UrzLZhYk= Xref: news.eternal-september.org comp.lang.vhdl:3984 On 9/24/2015 4:59 PM, zhangth1991@gmail.com wrote: > no, the output is U all the time Have you traced it back through the logic? Where does the U originate? -- Rick From newsfish@newsfish Thu Aug 1 00:34:33 2024 X-Received: by 10.13.230.214 with SMTP id p205mr3241863ywe.57.1443158472841; Thu, 24 Sep 2015 22:21:12 -0700 (PDT) X-Received: by 10.50.77.70 with SMTP id q6mr6253igw.4.1443158472771; Thu, 24 Sep 2015 22:21:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no4141936qge.0!news-out.google.com!n2ni11169igy.0!nntp.google.com!kq10no9269183igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 22:21:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <03072ae3-7e59-44a1-8ed5-21b3aeaa8bc3@googlegroups.com> Subject: Re: Multiplier using 1 bit full adder problem From: zhangth1991@gmail.com Injection-Date: Fri, 25 Sep 2015 05:21:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1366 X-Received-Body-CRC: 1160190088 Xref: news.eternal-september.org comp.lang.vhdl:3985 I think it is caused by the iteration_in, because before I use the inner iteration, the output is generated. Now the output is U after the first change of a and b From newsfish@newsfish Thu Aug 1 00:34:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx34.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Multiplier using 1 bit full adder problem References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150924-1, 24/09/2015), Outbound message X-Antivirus-Status: Clean Lines: 96 Message-ID: NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1443169248 81.109.142.154 (Fri, 25 Sep 2015 08:20:48 UTC) NNTP-Posting-Date: Fri, 25 Sep 2015 08:20:48 UTC Organization: virginmedia.com Date: Fri, 25 Sep 2015 09:20:45 +0100 X-Received-Body-CRC: 937365260 X-Received-Bytes: 4293 Xref: news.eternal-september.org comp.lang.vhdl:3986 On 24/09/2015 19:33, zhangth1991@gmail.com wrote: > I have a problem , when I execute my code, the output is undesigned. Anyone can help me? My code is as followed > --multiplier > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity Multiplier_VHDL is > GENERIC (WIDTH:INTEGER); > PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); > end entity Multiplier_VHDL; > > architecture Behavioral of Multiplier_VHDL is > > signal a_temp:std_logic_vector(width-1 downto 0); > signal a_temp_1:std_logic_vector(width-1 downto 0); > signal a_temp_2:std_logic_vector(width-1 downto 0); > signal cout_a:std_logic_vector(width-1 downto 0); > > signal b_temp:std_logic_vector(width-1 downto 0); > signal b_temp_1:std_logic_vector(width-1 downto 0); > signal b_temp_2:std_logic_vector(width-1 downto 0); > signal cout_b:std_logic_vector(width-1 downto 0); > signal y_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal y_ready:std_logic_vector(2*width-1 downto 0); > signal cin:std_logic_vector(2*width downto 0); > signal cout:std_logic_vector(2*width-1 downto 0); > signal mid_temp_a:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > > begin > --inverse calculation of a > iteration_a1: > for i in 0 to width-1 generate > a_temp_1(i)<= not a(i); > end generate iteration_a1; > a_temp_2(0)<=a_temp_1(0) xor '1'; > cout_a(0)<=a_temp_1(0) and '1'; > iteration_a2: > for i in 1 to width-1 generate > a_temp_2(i)<=a_temp_1(i) xor cout_a(i-1); As a quick guess I would say you may be hitting the longest static prefix issue. Have a look at section 4.2.13 of the VHDL FAQ: https://tams.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html Good luck, Hans www.ht-lab.com > cout_a(i)<=a_temp_1(i) and cout_a(i-1); > end generate iteration_a2; > a_temp<=a when a(width-1)='0' else > a_temp_2; > --inverse calculation of b > iteration_b1: > for i in 0 to width-1 generate > b_temp_1(i)<= not b(i); > end generate iteration_b1; > b_temp_2(0)<=b_temp_1(0) xor '1'; > cout_b(0)<=b_temp_1(0) and '1'; > iteration_b2: > for i in 1 to width-1 generate > b_temp_2(i)<=b_temp_1(i) xor cout_b(i-1); > cout_b(i)<=b_temp_1(i) and cout_b(i-1); > end generate iteration_b2; > b_temp<=b when b(width-1)='0' else > b_temp_2; > mid_temp_a(width-1 downto 0)<=a_temp; > > iteration_out: > for i in 0 to width-1 generate > cin(0)<='0'; > mid_temp_a<=mid_temp_a(2*width-2 downto 0) & '0'; > mid_temp<=mid_temp_a when b(i)='1' else > (others=>'0') when b(i)='0'; > iteration_in: > --y_temp is a while mid_temp is b > for j in 0 to 2*width-1 generate > y_ready1(j)<=y_temp(j) xor mid_temp(j) xor cin(j); > cout(j)<=(y_temp(j) and mid_temp(j)) or (y_temp(j) and cin(j)) or (cin(j) and mid_temp(j)); > cin(j+1)<=cout(j); > end generate iteration_in; > y_temp<=y_ready1; > > end generate iteration_out; > y<=y_ready; > > end architecture Behavioral; > From newsfish@newsfish Thu Aug 1 00:34:34 2024 X-Received: by 10.107.167.134 with SMTP id q128mr4788228ioe.6.1443183116082; Fri, 25 Sep 2015 05:11:56 -0700 (PDT) X-Received: by 10.50.77.39 with SMTP id p7mr17110igw.7.1443183116015; Fri, 25 Sep 2015 05:11:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no9857521igb.0!news-out.google.com!n2ni11471igy.0!nntp.google.com!kq10no9561358igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 05:11:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Result is U From: Thomas Stanka Injection-Date: Fri, 25 Sep 2015 12:11:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3987 Am Donnerstag, 24. September 2015 14:09:02 UTC+2 schrieb zhang...@gmail.com: > Hi, > I have a question about the behavioral code of multiplier. I used two generate loops but after calculation, the output is Undesigned. Anyone can help me? The code is as followed: [..] > y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); [..] > y<=y_ready; There is no statement that assigns a value to y_ready. I would debug this by having a look to all internal signals. That often helps identifying the signal that is root cause of 'U'. bye Thomas From newsfish@newsfish Thu Aug 1 00:34:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder problem Date: Fri, 25 Sep 2015 10:10:28 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> <03072ae3-7e59-44a1-8ed5-21b3aeaa8bc3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Sep 2015 14:08:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="17378"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/o73Xdz696P+CQgnONPkWT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <03072ae3-7e59-44a1-8ed5-21b3aeaa8bc3@googlegroups.com> Cancel-Lock: sha1:31W3xTMlESKNh2SnAnoLoXnZ/wU= Xref: news.eternal-september.org comp.lang.vhdl:3988 On 9/25/2015 1:21 AM, zhangth1991@gmail.com wrote: > I think it is caused by the iteration_in, because before I use the inner iteration, the output is generated. Now the output is U after the first change of a and b To be honest, I've never tried debugging generated code, mainly because I seldom write generated code. Why are you writing generated code rather than much simpler straight VHDL? For example, instead of four lines of generated code iteration_a1: could just be... a_temp_1 <= not a; iteration_a2: could be... a_temp_2 <= a_temp_1 xor (cout_a(width-2 downto 0) & '1'); cout_a <= a_temp_1 and (cout_a(width-2 downto 0) & '1'); Isn't this much simpler? What is the source of information on how to construct your logic? Do you have equations or a verbal description of how it is supposed to work? -- Rick From newsfish@newsfish Thu Aug 1 00:34:35 2024 X-Received: by 10.129.46.197 with SMTP id u188mr4734868ywu.22.1443191149212; Fri, 25 Sep 2015 07:25:49 -0700 (PDT) X-Received: by 10.50.8.42 with SMTP id o10mr27200iga.7.1443191149177; Fri, 25 Sep 2015 07:25:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no4324528qge.0!news-out.google.com!z4ni1766ign.0!nntp.google.com!kq10no9946790igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 07:25:48 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> Subject: Question of ' From: fl Injection-Date: Fri, 25 Sep 2015 14:25:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3989 Hi, VHDL grammar is still not easy to me. I see this line on a forum: architecture lut of bit_count is subtype lutin is std_logic_vector (3 downto 0); subtype lutout is std_logic_vector (2 downto 0); type lut00 is array (natural range 0 to 15) of lutout; constant bitcount: lut00 := ( "000", "001", "001", "010", "011", "010", "010", "011", "001", "010", "010", "011", "010", "011", "011", "100" ); signal temp: std_logic_vector (2 downto 0); begin temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) ); .... it has an error: Illegal type conversion to lutin (operand type is not known). I know the correct answer is: temp <= bitcount( TO_INTEGER ( unsigned (lutin'(a&b&c&d) ) ) ); but I don't know the detail rule on understanding it. Online search ' gives predefined attribute. Obviously here is not an attribute. What function of ' is here? Thanks, From newsfish@newsfish Thu Aug 1 00:34:35 2024 X-Received: by 10.13.215.74 with SMTP id z71mr4995557ywd.26.1443193231331; Fri, 25 Sep 2015 08:00:31 -0700 (PDT) X-Received: by 10.50.79.193 with SMTP id l1mr31002igx.2.1443193231257; Fri, 25 Sep 2015 08:00:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!feed.news.qwest.net!mpls-nntp-01.inet.qwest.net!216.166.98.85.MISMATCH!border2.nntp.dca1.giganews.com!nntp.giganews.com!v79no4340755qge.0!news-out.google.com!z4ni1796ign.0!nntp.google.com!kq10no9976145igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 08:00:30 -0700 (PDT) In-Reply-To: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.36.208.72; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 217.36.208.72 References: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e41e71e-50dc-4534-95cd-6bdff653d4a2@googlegroups.com> Subject: Re: Question of ' From: Jim Lewis Injection-Date: Fri, 25 Sep 2015 15:00:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: news.eternal-september.org comp.lang.vhdl:3990 > I know the correct answer is: > temp <= bitcount( TO_INTEGER ( unsigned (lutin'(a&b&c&d) ) ) ); > > > but I don't know the detail rule on understanding it. Online search ' gives > predefined attribute. Obviously here is not an attribute. What function of ' > is here? Here it is a type qualifier that identifies the type of the expression. If a,b,c,d are all std_ulogic or std_logic, then you could have simplified this to: temp <= bitcount( TO_INTEGER ( unsigned'(a&b&c&d) ) ); Jim From newsfish@newsfish Thu Aug 1 00:34:35 2024 X-Received: by 10.31.108.28 with SMTP id h28mr5062453vkc.4.1443194426259; Fri, 25 Sep 2015 08:20:26 -0700 (PDT) X-Received: by 10.50.22.7 with SMTP id z7mr32176ige.15.1443194426223; Fri, 25 Sep 2015 08:20:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no4350385qge.1!news-out.google.com!z4ni1807ign.0!nntp.google.com!kq10no9992632igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 08:20:25 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: std_ulogic_vector and std_logic_vector From: fl Injection-Date: Fri, 25 Sep 2015 15:20:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:3991 Hi, I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of ABCD. If it is std_logic_vector, there are more cases to consider. I know general input would have type std_logic_vector. My question is whether there is a simple way to convert std_logic_vector to std_ulogic_vector? Thanks, library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Number_of_Ones is port ( --- mapped 3=a, 2=b, 1=c, 0=d abcd : in std_ulogic_vector(3 downto 0); -- mapped x=2, y=1, z=0 xyz : out std_ulogic_vector(2 downto 0); ); end entity; architecture any of Number_of_Ones is begin process (abcd) is begin case abcd of --ABCD|XYZ when "0000" => xyz <= "000"; when "0001" => xyz <= "001"; when "0010" => xyz <= "001"; when "0011" => xyz <= "010"; when "0100" => xyz <= "011"; when "0101" => xyz <= "010"; when "0110" => xyz <= "010"; when "0111" => xyz <= "011"; when "1000" => xyz <= "001"; when "1001" => xyz <= "010"; when "1010" => xyz <= "010"; when "1011" => xyz <= "011"; when "1100" => xyz <= "010"; when "1101" => xyz <= "011"; when "1110" => xyz <= "011"; when "1111" => xyz <= "100"; end case; end process; From newsfish@newsfish Thu Aug 1 00:34:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question of ' Date: Fri, 25 Sep 2015 11:50:26 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Sep 2015 15:48:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="8458"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18wjO7Pq35vXKFpWuQOVmV3" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> Cancel-Lock: sha1:PtoJNc+/4iiczOdRV9KPlPlKf2E= Xref: news.eternal-september.org comp.lang.vhdl:3992 On 9/25/2015 10:25 AM, fl wrote: > Hi, > > VHDL grammar is still not easy to me. I see this line on a forum: > > > architecture lut of bit_count is > subtype lutin is std_logic_vector (3 downto 0); > subtype lutout is std_logic_vector (2 downto 0); > type lut00 is array (natural range 0 to 15) of lutout; > constant bitcount: lut00 := ( > "000", "001", "001", "010", > "011", "010", "010", "011", > "001", "010", "010", "011", > "010", "011", "011", "100" > ); > > signal temp: std_logic_vector (2 downto 0); > begin > temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) ); Is "bitcount" supposed to actually be a bit count? It's not. bitcount(4) should be "001", no? -- Rick From newsfish@newsfish Thu Aug 1 00:34:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: std_ulogic_vector and std_logic_vector Date: Fri, 25 Sep 2015 11:58:02 -0400 Organization: A noiseless patient Spider Lines: 75 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Sep 2015 15:56:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10232"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jlQhsZc93Tp/X0iFJClP5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:j6zymciTeD12uBfU9jCHiY/raTc= Xref: news.eternal-september.org comp.lang.vhdl:3993 On 9/25/2015 11:20 AM, fl wrote: > Hi, > I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of > ABCD. If it is std_logic_vector, there are more cases to consider. I believe std_ulogic_vector and std_logic_vector have the same value range. The difference is the result when signals are driven by multiple drivers. If you want to preclude the possibilities of inferring multiple drivers you can use std_ulogic_vector and errors will be flagged when multiple drivers are on the sane signal. With std_logic_vector the value goes to U or X, but no error is flagged in simulation. I'm not sure how synthesis handles multiple drivers on std_ulogic_vector signals. > I know general input would have type std_logic_vector. > > My question is whether there is a simple way to convert std_logic_vector to > std_ulogic_vector? Yeah.... std_logic_signal <= std_ulogic_signal; --- or --- xyz <= some expression of (std_logic'std_ulogic_signal); I believe these two logic types are completely interchangeable. > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity Number_of_Ones is > port ( > --- mapped 3=a, 2=b, 1=c, 0=d > abcd : in std_ulogic_vector(3 downto 0); > -- mapped x=2, y=1, z=0 > xyz : out std_ulogic_vector(2 downto 0); > ); > end entity; > > architecture any of Number_of_Ones is > begin > > process (abcd) is > begin > case abcd of > --ABCD|XYZ > when "0000" => xyz <= "000"; > when "0001" => xyz <= "001"; > when "0010" => xyz <= "001"; > when "0011" => xyz <= "010"; > when "0100" => xyz <= "011"; > when "0101" => xyz <= "010"; > when "0110" => xyz <= "010"; > when "0111" => xyz <= "011"; > when "1000" => xyz <= "001"; > when "1001" => xyz <= "010"; > when "1010" => xyz <= "010"; > when "1011" => xyz <= "011"; > when "1100" => xyz <= "010"; > when "1101" => xyz <= "011"; > when "1110" => xyz <= "011"; > when "1111" => xyz <= "100"; > end case; > end process; I think this also has the error for when "0100". -- Rick From newsfish@newsfish Thu Aug 1 00:34:36 2024 X-Received: by 10.129.99.131 with SMTP id x125mr5974233ywb.42.1443205484794; Fri, 25 Sep 2015 11:24:44 -0700 (PDT) X-Received: by 10.50.66.205 with SMTP id h13mr49908igt.10.1443205484765; Fri, 25 Sep 2015 11:24:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-03.inet.qwest.net!216.166.98.85.MISMATCH!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z77no4430846qge.1!news-out.google.com!n2ni11749igy.0!nntp.google.com!kq10no9882567igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 11:24:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Subject: Re: std_ulogic_vector and std_logic_vector From: KJ Injection-Date: Fri, 25 Sep 2015 18:24:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 18 Xref: news.eternal-september.org comp.lang.vhdl:3994 On Friday, September 25, 2015 at 11:20:29 AM UTC-4, fl wrote: > Hi, > I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of > ABCD. If it is std_logic_vector, there are more cases to consider. > That's not true. There are exactly the same number of cases. I think you may be confusing with bit_vector. > My question is whether there is a simple way to convert std_logic_vector to > std_ulogic_vector? > signal my_sulv: std_ulogic_vector(...); signal my_slv: std_logic_vector(...); ... my_sulv <= std_ulogic_vector(my_slv); my_slv <= std_logic_vector(my_sulv); Kevin Jennings From newsfish@newsfish Thu Aug 1 00:34:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: std_ulogic_vector and std_logic_vector Date: Fri, 25 Sep 2015 17:18:15 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Sep 2015 21:16:18 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="87b10dc1a89c821d7d807dd85a2825be"; logging-data="21395"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/nYCUZOrSw8J93VZG4JgHa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Cancel-Lock: sha1:uYsLVUtq4TpnvVaCTcf35j1Mc88= Xref: news.eternal-september.org comp.lang.vhdl:3995 On 9/25/2015 2:24 PM, KJ wrote: > On Friday, September 25, 2015 at 11:20:29 AM UTC-4, fl wrote: >> Hi, >> I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of >> ABCD. If it is std_logic_vector, there are more cases to consider. >> > > That's not true. There are exactly the same number of cases. I think you may be confusing with bit_vector. > >> My question is whether there is a simple way to convert std_logic_vector to >> std_ulogic_vector? >> > > signal my_sulv: std_ulogic_vector(...); > signal my_slv: std_logic_vector(...); > .... > my_sulv <= std_ulogic_vector(my_slv); > my_slv <= std_logic_vector(my_sulv); Those would be conversion functions and I don't think they exist for those types. Those types are "closely related" and require no conversion or type specification to convert. In essence they can be mixed as if they were the same type. Am I wrong? -- Rick From newsfish@newsfish Thu Aug 1 00:34:37 2024 X-Received: by 10.66.236.41 with SMTP id ur9mr7871085pac.12.1443240671025; Fri, 25 Sep 2015 21:11:11 -0700 (PDT) X-Received: by 10.50.92.7 with SMTP id ci7mr70990igb.4.1443240670994; Fri, 25 Sep 2015 21:11:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no10220185igb.0!news-out.google.com!z4ni2330ign.0!nntp.google.com!kq10no10220182igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 21:11:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:e811:23d2:8b8:b8f; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:e811:23d2:8b8:b8f References: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: std_ulogic_vector and std_logic_vector From: KJ Injection-Date: Sat, 26 Sep 2015 04:11:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:3996 On Friday, September 25, 2015 at 5:18:19 PM UTC-4, rickman wrote: > Those would be conversion functions and I don't think they exist for=20 > those types. Those types are "closely related" and require no=20 > conversion or type specification to convert. In essence they can be=20 > mixed as if they were the same type. >=20 > Am I wrong? >=20 Like any good question, the answer is 'It depends'. For std_logic_vector and std_ulogic_vector, prior to VHDL-2008, you were wr= ong, the two are not closely related types. They are separate types so you= need a type conversion to go from one to the other. With VHDL-2008, you a= re correct that no type conversion is required. For std_logic and std_ulogic you never needed a conversion function because= std_logic is defined to be a subtype of std_ulogic. This is the way that = std_logic_vector should have been defined in the first place...VHDL-2008 c= orrected that (finally). Kevin Jennings From newsfish@newsfish Thu Aug 1 00:34:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: std_ulogic_vector and std_logic_vector Date: Sat, 26 Sep 2015 00:27:11 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Sep 2015 04:25:13 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="87b10dc1a89c821d7d807dd85a2825be"; logging-data="29914"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19lHK6rzzRNQqPn+4UELzuC" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:yz0n5tansrZtHY6P7kHIElKRwpQ= Xref: news.eternal-september.org comp.lang.vhdl:3997 On 9/26/2015 12:11 AM, KJ wrote: > On Friday, September 25, 2015 at 5:18:19 PM UTC-4, rickman wrote: >> Those would be conversion functions and I don't think they exist for >> those types. Those types are "closely related" and require no >> conversion or type specification to convert. In essence they can be >> mixed as if they were the same type. >> >> Am I wrong? >> > > Like any good question, the answer is 'It depends'. > > For std_logic_vector and std_ulogic_vector, prior to VHDL-2008, you were wrong, the two are not closely related types. They are separate types so you need a type conversion to go from one to the other. With VHDL-2008, you are correct that no type conversion is required. > > For std_logic and std_ulogic you never needed a conversion function because std_logic is defined to be a subtype of std_ulogic. This is the way that std_logic_vector should have been defined in the first place...VHDL-2008 corrected that (finally). I'll have to take your word for it. I don't have any of my books with me and I'm too lazy to look this up on the Internet. :) -- Rick From newsfish@newsfish Thu Aug 1 00:34:38 2024 X-Received: by 10.13.223.129 with SMTP id i123mr13613492ywe.33.1443351484202; Sun, 27 Sep 2015 03:58:04 -0700 (PDT) X-Received: by 10.50.77.39 with SMTP id p7mr105907igw.7.1443351484174; Sun, 27 Sep 2015 03:58:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no5140546qge.0!news-out.google.com!z4ni3669ign.0!nntp.google.com!kq10no11381364igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Sep 2015 03:58:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6dfb986a-4a61-49ec-9cc0-1c6b18719955@googlegroups.com> Subject: Re: Question of ' From: fl Injection-Date: Sun, 27 Sep 2015 10:58:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2119 X-Received-Body-CRC: 41372844 Xref: news.eternal-september.org comp.lang.vhdl:3998 On Friday, September 25, 2015 at 11:50:31 AM UTC-4, rickman wrote: > On 9/25/2015 10:25 AM, fl wrote: > > Hi, > > > > VHDL grammar is still not easy to me. I see this line on a forum: > > > > > > architecture lut of bit_count is > > subtype lutin is std_logic_vector (3 downto 0); > > subtype lutout is std_logic_vector (2 downto 0); > > type lut00 is array (natural range 0 to 15) of lutout; > > constant bitcount: lut00 := ( > > "000", "001", "001", "010", > > "011", "010", "010", "011", > > "001", "010", "010", "011", > > "010", "011", "011", "100" > > ); > > > > signal temp: std_logic_vector (2 downto 0); > > begin > > temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) ); > > Is "bitcount" supposed to actually be a bit count? It's not. > bitcount(4) should be "001", no? > > -- > > Rick Rick: You are right. The original code on the table of bitcount(4) and other entries was wrong. Thanks, From newsfish@newsfish Thu Aug 1 00:34:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: std_ulogic_vector and std_logic_vector Date: Sun, 27 Sep 2015 14:37:54 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Sep 2015 18:36:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="14438"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ixsn6X4pJak/NPLHn2Wpq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:GqV3ZfEQFqG/+I5imtUB5mk4ErU= Xref: news.eternal-september.org comp.lang.vhdl:3999 On 9/26/2015 12:27 AM, rickman wrote: > On 9/26/2015 12:11 AM, KJ wrote: >> On Friday, September 25, 2015 at 5:18:19 PM UTC-4, rickman wrote: >>> Those would be conversion functions and I don't think they exist for >>> those types. Those types are "closely related" and require no >>> conversion or type specification to convert. In essence they can be >>> mixed as if they were the same type. >>> >>> Am I wrong? >>> >> >> Like any good question, the answer is 'It depends'. >> >> For std_logic_vector and std_ulogic_vector, prior to VHDL-2008, you >> were wrong, the two are not closely related types. They are separate >> types so you need a type conversion to go from one to the other. With >> VHDL-2008, you are correct that no type conversion is required. >> >> For std_logic and std_ulogic you never needed a conversion function >> because std_logic is defined to be a subtype of std_ulogic. This is >> the way that std_logic_vector should have been defined in the first >> place...VHDL-2008 corrected that (finally). > > I'll have to take your word for it. I don't have any of my books with > me and I'm too lazy to look this up on the Internet. :) I finally got un-lazy and looked it up. The individual signals std_ulogic and std_logic do not require any sort of conversion. The _vector versions did. I seldom (ever actually) use std_ulogic so I didn't remember the distinction between the single signal and the vector signals. VHDL is complicated enough it is easy to forget details. -- Rick From newsfish@newsfish Thu Aug 1 00:34:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question of ' Date: Sun, 27 Sep 2015 14:38:38 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> <6dfb986a-4a61-49ec-9cc0-1c6b18719955@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Sep 2015 18:36:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="14438"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Pui7Wxa66TXXzWsK3+PRD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <6dfb986a-4a61-49ec-9cc0-1c6b18719955@googlegroups.com> Cancel-Lock: sha1:jO5Oegyf1/aCj+gRTf4vUKFqWMI= Xref: news.eternal-september.org comp.lang.vhdl:4000 On 9/27/2015 6:58 AM, fl wrote: > On Friday, September 25, 2015 at 11:50:31 AM UTC-4, rickman wrote: >> On 9/25/2015 10:25 AM, fl wrote: >>> Hi, >>> >>> VHDL grammar is still not easy to me. I see this line on a forum: >>> >>> >>> architecture lut of bit_count is >>> subtype lutin is std_logic_vector (3 downto 0); >>> subtype lutout is std_logic_vector (2 downto 0); >>> type lut00 is array (natural range 0 to 15) of lutout; >>> constant bitcount: lut00 := ( >>> "000", "001", "001", "010", >>> "011", "010", "010", "011", >>> "001", "010", "010", "011", >>> "010", "011", "011", "100" >>> ); >>> >>> signal temp: std_logic_vector (2 downto 0); >>> begin >>> temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) ); >> >> Is "bitcount" supposed to actually be a bit count? It's not. >> bitcount(4) should be "001", no? >> >> -- >> >> Rick > > Rick: > You are right. The original code on the table of bitcount(4) and other > entries was wrong. Thanks, Hey, that's what code reviews are for. :) -- Rick From newsfish@newsfish Thu Aug 1 00:34:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Review of Data Type Issues Date: Sun, 27 Sep 2015 15:08:32 -0400 Organization: A noiseless patient Spider Lines: 36 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Sep 2015 19:06:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="22209"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19kMmqANY0wfVGSTe5MoEs5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:No7CJ/1X83L6W7fCztKLMHQsPEM= Xref: news.eternal-september.org comp.lang.vhdl:4001 I have trouble remembering the various ways of interchanging data types. I know there are three different methods that apply in different situations, but I have a hard time remembering them all because I don't code as often as I used to. 1) Conversions using functions Between unrelated types. Requires an explicit function. Example - Unsigned to Integer, to_integer(U) 2) Typecast Between related types (same base type, same index type if vector). Syntax looks like a function. Not needed for closely related types. Example - Unsigned to signed, signed('0' & X_uv) 3) Type qualifier Specifies type when unclear. String arrays can be a number of types, so require a qualifier to indicate the type. There can be multiple overloaded functions with the same input types but different return types, again a qualifier is required to resolve the issue. Example - Z_sv <= A_sv + signed'("1010") ; I think this lists the ways that types are converted or indicated. Just trying to refresh my memory. -- Rick From newsfish@newsfish Thu Aug 1 00:34:39 2024 X-Received: by 10.66.90.196 with SMTP id by4mr16792690pab.44.1443407088749; Sun, 27 Sep 2015 19:24:48 -0700 (PDT) X-Received: by 10.50.77.39 with SMTP id p7mr121905igw.7.1443407088678; Sun, 27 Sep 2015 19:24:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!kq10no12066138igb.0!news-out.google.com!n2ni14092igy.0!nntp.google.com!kq10no12066133igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Sep 2015 19:24:47 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Question about 'Actual expression is not globally static' From: fl Injection-Date: Mon, 28 Sep 2015 02:24:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4002 Hi, I remember that I see a code writing on part signal with 'not' logic as: instance_name : complexMul0 port map ( ar => not(ar), ai => ai, br => br, bi => bi, clk => CK, pr => pr, pi => pi); Today, when I write the above style and simulate with Modelsim, it gives error: (vcom-1436) Actual expression (prefix expression) of formal "ar" is not globally static. Could you help me on explain what 'globally static' is? What VHDL standard allow/dis-allow 'not' logic prefix? Thanks From newsfish@newsfish Thu Aug 1 00:34:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Question about 'Actual expression is not globally static' Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 28 Sep 2015 11:45:20 GMT Lines: 58 Message-ID: <5609284f$0$2852$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: c8bf766b.news.astraweb.com X-Trace: DXC=kWk8NINX0A86fPZ:J:\J]3<:Wm\C]Q?P_PdAA< Xref: news.eternal-september.org comp.lang.vhdl:4003 On Sun, 27 Sep 2015 19:24:47 -0700, fl wrote: > Hi, > > I remember that I see a code writing on part signal with 'not' logic as: > > > instance_name : complexMul0 > port map ( > ar => not(ar), > ai => ai, > br => br, > bi => bi, > clk => CK, > pr => pr, > pi => pi); > > > Today, when I write the above style and simulate with Modelsim, it gives > error: > > (vcom-1436) Actual expression (prefix expression) of formal "ar" is not > globally static. > > > > Could you help me on explain what 'globally static' is? > What VHDL standard allow/dis-allow 'not' logic prefix? Add quotes around the not like this instead: port map ( ar => "not"(ar), ai => ai, br => br, You are not allowed to use general expressions in a port map, however you are allowed to use function calls with at most one signal argument. This allows type conversions, etc. but not general purpose logic expressions of multiple signals. I'm not sure why they decided on this limitation. The "" quotes made a difference by turning an expression (which is illegal) into a function call (which is legal). Globally static roughly means that a name can be resolved at elaboration time. C.f. locally static, which roughly means that a name can be resolved at compilation time. If the compiler is saying that something isn't globally static, then it still can't work out what to do even after elaboration. I feel that Modelsim could have given a better error message in this case. Regards, Allan From newsfish@newsfish Thu Aug 1 00:34:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!81.171.118.62.MISMATCH!peer02.fr7!news.highwinds-media.com!post02.fr7!fx18.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Question about 'Actual expression is not globally static' References: <5609284f$0$2852$c3e8da3$76491128@news.astraweb.com> Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <5609284f$0$2852$c3e8da3$76491128@news.astraweb.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150928-0, 28/09/2015), Outbound message X-Antivirus-Status: Clean Lines: 79 Message-ID: NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1443446545 81.109.142.154 (Mon, 28 Sep 2015 13:22:25 UTC) NNTP-Posting-Date: Mon, 28 Sep 2015 13:22:25 UTC Organization: virginmedia.com Date: Mon, 28 Sep 2015 14:22:25 +0100 X-Received-Body-CRC: 1165426853 X-Received-Bytes: 3329 Xref: news.eternal-september.org comp.lang.vhdl:4004 On 28/09/2015 12:45, Allan Herriman wrote: > On Sun, 27 Sep 2015 19:24:47 -0700, fl wrote: > >> Hi, >> >> I remember that I see a code writing on part signal with 'not' logic as: >> >> >> instance_name : complexMul0 >> port map ( >> ar => not(ar), >> ai => ai, >> br => br, >> bi => bi, >> clk => CK, >> pr => pr, >> pi => pi); >> >> >> Today, when I write the above style and simulate with Modelsim, it gives >> error: >> >> (vcom-1436) Actual expression (prefix expression) of formal "ar" is not >> globally static. >> >> >> >> Could you help me on explain what 'globally static' is? >> What VHDL standard allow/dis-allow 'not' logic prefix? > > > Add quotes around the not like this instead: > > > port map ( > ar => "not"(ar), > ai => ai, > br => br, > > > You are not allowed to use general expressions in a port map, however > you are allowed to use function calls with at most one signal argument. > This allows type conversions, etc. but not general purpose logic > expressions of multiple signals. I'm not sure why they decided on this > limitation. > > The "" quotes made a difference by turning an expression (which is > illegal) into a function call (which is legal). > > Globally static roughly means that a name can be resolved at elaboration > time. C.f. locally static, which roughly means that a name can be > resolved at compilation time. > If the compiler is saying that something isn't globally static, then it > still can't work out what to do even after elaboration. > > I feel that Modelsim could have given a better error message in this case. > Just use verror (cmd prompt or modelsim transcript) to get more info: D:\>verror 1436 vcom Message # 1436: VHDL 1993 through VHDL 2002 allowed an expression to be associated with a formal port in a port map as long as the expression was globally static and the port was of mode IN. VHDL 2008 now allows non-static expressions as well. Use the -2008 switch to vcom to enable this feature. [DOC: IEEE Std 1076-2002 VHDL LRM - 1.1.1.2 Ports] [DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clause] Regards, Hans www.ht-lab.com > Regards, > Allan > From newsfish@newsfish Thu Aug 1 00:34:40 2024 X-Received: by 10.66.252.6 with SMTP id zo6mr18192531pac.29.1443447677967; Mon, 28 Sep 2015 06:41:17 -0700 (PDT) X-Received: by 10.50.66.205 with SMTP id h13mr145264igt.10.1443447677891; Mon, 28 Sep 2015 06:41:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no12278394igb.0!news-out.google.com!z4ni4868ign.0!nntp.google.com!kq10no12278393igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Sep 2015 06:41:17 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: What differences are for type qualifier and type casting? From: fl Injection-Date: Mon, 28 Sep 2015 13:41:17 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4005 Hi, I see the following on a tutorial, but it is not clear about the difference= s=20 between type qualifier and type casting. How do I use either one from "1010" and B_slv? Thanks, =E2=97=8F VHDL type qualifier (type_name') is a mechanism that specifies th= e type of an operand or return value of a subprogram (or operator). Z_sv <=3D A_sv + signed'("1010") ;=20 =E2=97=8F Without ', it is type casting. Use type casting for: Z_sv <=3D A_sv + signed(B_slv) ;=20 From newsfish@newsfish Thu Aug 1 00:34:41 2024 X-Received: by 10.129.76.9 with SMTP id z9mr19013535ywa.35.1443457473215; Mon, 28 Sep 2015 09:24:33 -0700 (PDT) X-Received: by 10.50.111.138 with SMTP id ii10mr61457igb.0.1443457473160; Mon, 28 Sep 2015 09:24:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no5715762qge.1!news-out.google.com!n2ni14652igy.0!nntp.google.com!kq10no12670945igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Sep 2015 09:24:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What differences are for type qualifier and type casting? From: fl Injection-Date: Mon, 28 Sep 2015 16:24:33 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4006 On Monday, September 28, 2015 at 9:41:21 AM UTC-4, fl wrote: > Hi, >=20 > I see the following on a tutorial, but it is not clear about the differen= ces=20 > between type qualifier and type casting. >=20 > How do I use either one from "1010" and B_slv? >=20 > Thanks, >=20 >=20 > =E2=97=8F VHDL type qualifier (type_name') is a mechanism that specifies = the type > of an operand or return value of a subprogram (or operator). > Z_sv <=3D A_sv + signed'("1010") ;=20 >=20 > =E2=97=8F Without ', it is type casting. Use type casting for: > Z_sv <=3D A_sv + signed(B_slv) ; After read previous posts of KJ and Rick, I am clear about my question now.= Types are now and then confusing. From newsfish@newsfish Thu Aug 1 00:34:41 2024 X-Received: by 10.67.3.137 with SMTP id bw9mr19576180pad.4.1443458017907; Mon, 28 Sep 2015 09:33:37 -0700 (PDT) X-Received: by 10.50.112.4 with SMTP id im4mr148155igb.1.1443458017874; Mon, 28 Sep 2015 09:33:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no12425914igb.0!news-out.google.com!z4ni4979ign.0!nntp.google.com!kq10no12680954igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Sep 2015 09:33:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4cbc80be-939f-4b38-8b4c-0088ecdd04d0@googlegroups.com> Subject: Why do conversion functions need to be self defined in a project? From: fl Injection-Date: Mon, 28 Sep 2015 16:33:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4007 Hi, I have a Matlab generated VHDL code project. It has such functions defined in the testbench package. I am just curious about why these looks frequent used functions need to write in such a project. It makes the test bench file very long, not friendly reading to me. Are there some similar functions out there accessible to me? Or, is there some reasons left to the designer to do by themselves? Thanks, -- Functions FUNCTION to_integer( x : IN std_logic) RETURN integer; FUNCTION to_hex( x : IN std_logic) RETURN string; FUNCTION to_hex( x : IN std_logic_vector) RETURN string; FUNCTION to_hex( x : IN bit_vector ) RETURN string; FUNCTION to_hex( x : IN signed ) RETURN string; FUNCTION to_hex( x : IN unsigned ) RETURN string; FUNCTION to_hex( x : IN real ) RETURN string; FUNCTION SLICE( x : IN bit_vector; slice : In Integer) RETURN std_logic_vector; From newsfish@newsfish Thu Aug 1 00:34:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What differences are for type qualifier and type casting? Date: Mon, 28 Sep 2015 13:59:40 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 28 Sep 2015 17:57:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="13611"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18WwaryKL6Yf+/WFk292jkD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:iC8pDBTAziu1187qoV2J6bXrWAA= Xref: news.eternal-september.org comp.lang.vhdl:4008 On 9/28/2015 12:24 PM, fl wrote: > On Monday, September 28, 2015 at 9:41:21 AM UTC-4, fl wrote: >> Hi, >> >> I see the following on a tutorial, but it is not clear about the differences >> between type qualifier and type casting. >> >> How do I use either one from "1010" and B_slv? >> >> Thanks, >> >> >> ● VHDL type qualifier (type_name') is a mechanism that specifies the type >> of an operand or return value of a subprogram (or operator). >> Z_sv <= A_sv + signed'("1010") ; >> >> ● Without ', it is type casting. Use type casting for: >> Z_sv <= A_sv + signed(B_slv) ; > > After read previous posts of KJ and Rick, I am clear about my question now. Types are now and then confusing. Lol! That is like saying Godzilla was a rather large lizard! -- Rick From newsfish@newsfish Thu Aug 1 00:34:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Why do conversion functions need to be self defined in a project? Date: Tue, 29 Sep 2015 09:20:35 +0000 (UTC) Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <4cbc80be-939f-4b38-8b4c-0088ecdd04d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 29 Sep 2015 09:20:35 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="15535"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/iRnFyN14R7xEYvwjTvBgU1sNjE6+7vMM=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:Th7vS7rZBTkf1UcfsNE8oe7E3qo= Xref: news.eternal-september.org comp.lang.vhdl:4009 On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote: > Hi, > > I have a Matlab generated VHDL code project. It has such functions > defined in the testbench package. I am just curious about why these > looks frequent used functions need to write in such a project. It makes > the test bench file very long, not friendly reading to me. Put them in a utilities package so they don't clutter up the testbench. > Are there some similar functions out there accessible to me? Or, is > there some reasons left to the designer to do by themselves? There are libraries of functions to aid testing out there. www.osvvm.org supports constrained random verification https://github.com/LarsAsplund/vunit supports unit testing. Both of these have utilities to simplify reporting, which may cover your needs. However http://bitvis.no/resources/utility-library-download/ may be exactly what you are asking for. -- Brian From newsfish@newsfish Thu Aug 1 00:34:42 2024 X-Received: by 10.13.203.76 with SMTP id n73mr2646510ywd.15.1443541312055; Tue, 29 Sep 2015 08:41:52 -0700 (PDT) X-Received: by 10.50.66.144 with SMTP id f16mr239247igt.14.1443541312028; Tue, 29 Sep 2015 08:41:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!au2pb.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no6169784qge.0!news-out.google.com!z4ni5936ign.0!nntp.google.com!kq10no13637895igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 08:41:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Subject: Does if need else absolutely for synthesis to avoid latch? From: fl Injection-Date: Tue, 29 Sep 2015 15:41:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2250 X-Received-Body-CRC: 1478306846 Xref: news.eternal-september.org comp.lang.vhdl:4010 Hi, I remember that it is said that if must have an else to avoid latch in the synthesis process. I just begin working on a new, would-be large project. In order to do it gradually, I do a pure functional simulation first. The following code works for the simulation, but I don't find a way to add else for the if loop having '**' lines. The intention is to make the counter begins after an external signal 'start' changes to '1', which is expected the pulse width is just one clock cycle. When 'start' is '1', the last cnt <= cnt+1 runs. Then, 'start' is '0', but cnt /= x"00". The first cnt <= cnt+1 will run. Perhaps you expects have better idea to write this, even if my code works. I would rather to hear from you. Thanks, ........................... type START01 is range 0 to 1 ; signal start_var : START01 := 0; signal cnt : unsigned(7 downto 0) := (others => '0'); start_var <= start; p_start: process (clk, reset) begin if (clk'event and clk = '1') then if reset = '1' then cnt <= x"00"; elsif start_var = 0 then ** if cnt /= x"00" then cnt <= cnt + 1; ** end if; else cnt <= cnt + 1; end if; end if; end process; From newsfish@newsfish Thu Aug 1 00:34:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Does if need else absolutely for synthesis to avoid latch? Date: Tue, 29 Sep 2015 11:58:02 -0400 Organization: Alacron, Inc. Lines: 63 Message-ID: References: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Sep 2015 15:57:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="19033"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199Lzb6lAmgpIPlEAmWb+YYWOb6734aECY=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Cancel-Lock: sha1:AdphoCmYH9lV/v/6aEg76U41FDE= Xref: news.eternal-september.org comp.lang.vhdl:4011 fl wrote: > Hi, > > I remember that it is said that if must have an else to avoid latch in the > synthesis process. I just begin working on a new, would-be large project. > In order to do it gradually, I do a pure functional simulation first. > The following code works for the simulation, but I don't find a way to add > else for the if loop having '**' lines. > > The intention is to make the counter begins after an external signal 'start' > changes to '1', which is expected the pulse width is just one clock cycle. > When 'start' is '1', the last cnt <= cnt+1 runs. Then, 'start' is '0', but > cnt /= x"00". The first cnt <= cnt+1 will run. > > > Perhaps you expects have better idea to write this, even if my code works. > I would rather to hear from you. > > Thanks, > > > ........................... > type START01 is range 0 to 1 ; > > signal start_var : START01 := 0; > signal cnt : unsigned(7 downto 0) := (others => '0'); > > start_var <= start; > p_start: process (clk, reset) > begin > if (clk'event and clk = '1') then > if reset = '1' then > cnt <= x"00"; > elsif start_var = 0 then > ** if cnt /= x"00" then > cnt <= cnt + 1; > ** end if; > else > cnt <= cnt + 1; > end if; > end if; > end process; > Latches are only created in a combinatorial process. Inside the if (clk`event ..., you are in a clocked process. So instead you will infer edge-triggered flip-flops. In this context there is no need to code an else for every if. It is assumed that the flip-flop will hold its current state if there is no else condition, and that's in fact what you want. Other than that, I would think the code more readable if you changed the order to look more like "if start is asserted then count up, else if count is not zero count up." The way you coded it does the same thing, but seems like it's backwards to the way one would normally think of it, i.e. you coded "if start is not asserted then count up only if count is not zero, otherwise count up." In the end, it's most likely you who will re-visit this code some time down the road and scratch your head trying to figure out what it does. -- Gabor From newsfish@newsfish Thu Aug 1 00:34:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why do conversion functions need to be self defined in a project? Date: Tue, 29 Sep 2015 12:00:12 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <4cbc80be-939f-4b38-8b4c-0088ecdd04d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Sep 2015 15:58:16 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="19377"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/qUF2zxBv9kfxE2Sqa3Ppa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:S27micn/ViJ85+jI45nlqPmkIB8= Xref: news.eternal-september.org comp.lang.vhdl:4012 On 9/29/2015 5:20 AM, Brian Drummond wrote: > On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote: > >> Hi, >> >> I have a Matlab generated VHDL code project. It has such functions >> defined in the testbench package. I am just curious about why these >> looks frequent used functions need to write in such a project. It makes >> the test bench file very long, not friendly reading to me. > > Put them in a utilities package so they don't clutter up the testbench. > >> Are there some similar functions out there accessible to me? Or, is >> there some reasons left to the designer to do by themselves? > > There are libraries of functions to aid testing out there. > > www.osvvm.org supports constrained random verification > https://github.com/LarsAsplund/vunit supports unit testing. > > Both of these have utilities to simplify reporting, which may cover your > needs. > > However http://bitvis.no/resources/utility-library-download/ may be > exactly what you are asking for. I think the OP is using a utility to generate a test bench and it is adding the various functions which are *not* part of any of the conventional packages. So they stick them in the main file of the test bench. If he moves these functions to a package he will need to do the same work every time he generates the test bench again. -- Rick From newsfish@newsfish Thu Aug 1 00:34:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Does if need else absolutely for synthesis to avoid latch? Date: Tue, 29 Sep 2015 12:12:15 -0400 Organization: A noiseless patient Spider Lines: 58 Message-ID: References: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Sep 2015 16:10:18 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="22350"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/VlLIbQo/4ZNzjLQkmcww1" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Cancel-Lock: sha1:t7QZPXHnDdweAaZnpKGiyaT9I3c= Xref: news.eternal-september.org comp.lang.vhdl:4013 On 9/29/2015 11:41 AM, fl wrote: > Hi, > > I remember that it is said that if must have an else to avoid latch in the > synthesis process. I just begin working on a new, would-be large project. > In order to do it gradually, I do a pure functional simulation first. > The following code works for the simulation, but I don't find a way to add > else for the if loop having '**' lines. > > The intention is to make the counter begins after an external signal 'start' > changes to '1', which is expected the pulse width is just one clock cycle. > When 'start' is '1', the last cnt <= cnt+1 runs. Then, 'start' is '0', but > cnt /= x"00". The first cnt <= cnt+1 will run. > > > Perhaps you expects have better idea to write this, even if my code works. > I would rather to hear from you. > > Thanks, > > > ............................ > type START01 is range 0 to 1 ; > > signal start_var : START01 := 0; > signal cnt : unsigned(7 downto 0) := (others => '0'); > > start_var <= start; > p_start: process (clk, reset) > begin > if (clk'event and clk = '1') then > if reset = '1' then > cnt <= x"00"; > elsif start_var = 0 then > ** if cnt /= x"00" then > cnt <= cnt + 1; > ** end if; > else > cnt <= cnt + 1; > end if; > end if; > end process; The rule about latch generation only applies to code that is *not* within a clocked IF statement. The lack of the ELSE clause or an equivalent assignment implies that the previous value of the signal is retained. This infers a FF of some sort. In a clocked IF statement a clocked register is already inferred, so no harm. BTW, you should use the function rising_edge(clk) rather than the explicit term (clk'event and clk = '1'). The above code within the clocked IF statement will run on such transitions as 'H' to '1' and 'U' to '1'. Also it is just easier to read rising_edge(clk). Ditto falling_edge(clk). -- Rick From newsfish@newsfish Thu Aug 1 00:34:44 2024 X-Received: by 10.31.178.196 with SMTP id b187mr83741vkf.3.1443560733885; Tue, 29 Sep 2015 14:05:33 -0700 (PDT) X-Received: by 10.50.66.144 with SMTP id f16mr18597igt.14.1443560733842; Tue, 29 Sep 2015 14:05:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no6302503qge.1!news-out.google.com!z4ni6202ign.0!nntp.google.com!kq10no13914860igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 14:05:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> Subject: Question about setting signal value From: fl Injection-Date: Tue, 29 Sep 2015 21:05:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4014 Hi, When I run a simulation VHDL code, there is a out of range fatal error. The signal source is from below code. corner0 is 111.5 while DINar_corner is 111.9. The division result should be below 1. Now the console output is: # ** Note: The value of 'corner0' is 1.119000e+002 # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 # ** Note: The value of 'DINar_corner' is 1.115000e+002 # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 # ** Note: The value of 'Cout' is -1.000000e+308 # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 I think that Cout should be the correct value after the process updates the signal value. But the other module which accespts Cout of below code, still sees Cout's value as -1.000000e+308. This results an out of range error. What is wrong in my code and signal value understanding? Thanks a lot to you. ............. p1: process (clk) variable tmp_XP, tmp_X : real; begin if (clk'event and clk = '1') then if reset = '1' then ar <= 0.0; ai <= 0.0; br <= 0.0; bi <= 0.0; else if cnt < x"02" then if cnt = x"00" then corner0 <= DINar_corner; elsif abs(corner0) < abs(DINar_corner) then corner0_q_real <= corner0/DINar_corner; Cout <= corner0_q_real; report "The value of 'corner0' is " & real'image(corner0); report "The value of 'DINar_corner' is " & real'image(DINar_corner); report "The value of 'Cout' is " & real'image(corner0_q_real); Sout <= 1; else corner0_q_real <= DINar_corner/corner0; Cout <= corner0_q_real; report "The value of 'Cout' is " & real'image(corner0_q_real); Sout <= 0; end if; else corner0_q_real <= DINar_corner/corner0; end if; From newsfish@newsfish Thu Aug 1 00:34:44 2024 X-Received: by 10.107.131.73 with SMTP id f70mr949243iod.18.1443563092531; Tue, 29 Sep 2015 14:44:52 -0700 (PDT) X-Received: by 10.50.13.38 with SMTP id e6mr275143igc.5.1443563092508; Tue, 29 Sep 2015 14:44:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no13939621igb.0!news-out.google.com!n2ni15887igy.0!nntp.google.com!kq10no13492478igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 14:44:51 -0700 (PDT) In-Reply-To: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> Subject: Re: Question about setting signal value From: fl Injection-Date: Tue, 29 Sep 2015 21:44:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4015 On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote: > Hi, > > When I run a simulation VHDL code, there is a out of range fatal error. The > signal source is from below code. corner0 is 111.5 while DINar_corner is > 111.9. The division result should be below 1. Now the console output is: > # ** Note: The value of 'corner0' is 1.119000e+002 > # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > # ** Note: The value of 'DINar_corner' is 1.115000e+002 > # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > # ** Note: The value of 'Cout' is -1.000000e+308 > # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > > I think that Cout should be the correct value after the process updates the > signal value. But the other module which accespts Cout of below code, still > sees Cout's value as -1.000000e+308. This results an out of range error. > > > What is wrong in my code and signal value understanding? > > > Thanks a lot to you. > > > > ............. > p1: process (clk) > variable tmp_XP, tmp_X : real; > begin > if (clk'event and clk = '1') then > if reset = '1' then > ar <= 0.0; ai <= 0.0; > br <= 0.0; bi <= 0.0; > else > if cnt < x"02" then > if cnt = x"00" then > corner0 <= DINar_corner; > elsif abs(corner0) < abs(DINar_corner) then > corner0_q_real <= corner0/DINar_corner; > Cout <= corner0_q_real; > report "The value of 'corner0' is " & real'image(corner0); > report "The value of 'DINar_corner' is " & real'image(DINar_corner); > report "The value of 'Cout' is " & real'image(corner0_q_real); > Sout <= 1; > else > corner0_q_real <= DINar_corner/corner0; > Cout <= corner0_q_real; > report "The value of 'Cout' is " & real'image(corner0_q_real); > Sout <= 0; > end if; > else > corner0_q_real <= DINar_corner/corner0; > end if; It is found that when I replace below one line to the two lines in previous post, it has no fatal error any more. I originally added one temporary signal for observation. It really delays one clock for the value. It was bug. Thanks, Cout <= -DINar_corner/corner0; From newsfish@newsfish Thu Aug 1 00:34:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question about setting signal value Date: Tue, 29 Sep 2015 18:30:50 -0400 Organization: A noiseless patient Spider Lines: 75 Message-ID: References: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Sep 2015 22:28:58 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="23219"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX192wqRXhG1cFYkeYg3AmtXh" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> Cancel-Lock: sha1:UBCxroi13Vxs3WEMReVCE0SfEK8= Xref: news.eternal-september.org comp.lang.vhdl:4016 On 9/29/2015 5:44 PM, fl wrote: > On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote: >> Hi, >> >> When I run a simulation VHDL code, there is a out of range fatal error. The >> signal source is from below code. corner0 is 111.5 while DINar_corner is >> 111.9. The division result should be below 1. Now the console output is: >> # ** Note: The value of 'corner0' is 1.119000e+002 >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >> # ** Note: The value of 'DINar_corner' is 1.115000e+002 >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >> # ** Note: The value of 'Cout' is -1.000000e+308 >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >> >> I think that Cout should be the correct value after the process updates the >> signal value. But the other module which accespts Cout of below code, still >> sees Cout's value as -1.000000e+308. This results an out of range error. >> >> >> What is wrong in my code and signal value understanding? >> >> >> Thanks a lot to you. >> >> >> >> ............. >> p1: process (clk) >> variable tmp_XP, tmp_X : real; >> begin >> if (clk'event and clk = '1') then >> if reset = '1' then >> ar <= 0.0; ai <= 0.0; >> br <= 0.0; bi <= 0.0; >> else >> if cnt < x"02" then >> if cnt = x"00" then >> corner0 <= DINar_corner; >> elsif abs(corner0) < abs(DINar_corner) then >> corner0_q_real <= corner0/DINar_corner; >> Cout <= corner0_q_real; >> report "The value of 'corner0' is " & real'image(corner0); >> report "The value of 'DINar_corner' is " & real'image(DINar_corner); >> report "The value of 'Cout' is " & real'image(corner0_q_real); >> Sout <= 1; >> else >> corner0_q_real <= DINar_corner/corner0; >> Cout <= corner0_q_real; >> report "The value of 'Cout' is " & real'image(corner0_q_real); >> Sout <= 0; >> end if; >> else >> corner0_q_real <= DINar_corner/corner0; >> end if; > > It is found that when I replace below one line to the two lines in previous > post, it has no fatal error any more. I originally added one temporary > signal for observation. It really delays one clock for the value. It was > bug. > Thanks, > > Cout <= -DINar_corner/corner0; Yes, this statement inside the clocked conditional results in a 1 clock cycle delay, or actually more since it is in the ELSE clause while the rest of the code is in the THEN part of the IF cnt < x"02" statement. I think it would work fine if you made the Cout <= -DINar_corner/corner0; statement a concurrent statement outside of the process. Then it will be updated as soon as the values of DINar_corner and corner0 are updated. -- Rick From newsfish@newsfish Thu Aug 1 00:34:45 2024 X-Received: by 10.68.132.1 with SMTP id oq1mr757553pbb.12.1443571996580; Tue, 29 Sep 2015 17:13:16 -0700 (PDT) X-Received: by 10.50.176.200 with SMTP id ck8mr27084igc.3.1443571996537; Tue, 29 Sep 2015 17:13:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no14021442igb.0!news-out.google.com!z4ni6359ign.0!nntp.google.com!kq10no14021433igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 17:13:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <35e118e4-6179-4d0e-a632-bef93d8ad40f@googlegroups.com> Subject: Re: Question about setting signal value From: fl Injection-Date: Wed, 30 Sep 2015 00:13:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4017 On Tuesday, September 29, 2015 at 6:31:01 PM UTC-4, rickman wrote: > On 9/29/2015 5:44 PM, fl wrote: > > On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote: > >> Hi, > >> > >> When I run a simulation VHDL code, there is a out of range fatal error. The > >> signal source is from below code. corner0 is 111.5 while DINar_corner is > >> 111.9. The division result should be below 1. Now the console output is: > >> # ** Note: The value of 'corner0' is 1.119000e+002 > >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > >> # ** Note: The value of 'DINar_corner' is 1.115000e+002 > >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > >> # ** Note: The value of 'Cout' is -1.000000e+308 > >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > >> > >> I think that Cout should be the correct value after the process updates the > >> signal value. But the other module which accespts Cout of below code, still > >> sees Cout's value as -1.000000e+308. This results an out of range error. > >> > >> > >> What is wrong in my code and signal value understanding? > >> > >> > >> Thanks a lot to you. > >> > >> > >> > >> ............. > >> p1: process (clk) > >> variable tmp_XP, tmp_X : real; > >> begin > >> if (clk'event and clk = '1') then > >> if reset = '1' then > >> ar <= 0.0; ai <= 0.0; > >> br <= 0.0; bi <= 0.0; > >> else > >> if cnt < x"02" then > >> if cnt = x"00" then > >> corner0 <= DINar_corner; > >> elsif abs(corner0) < abs(DINar_corner) then > >> corner0_q_real <= corner0/DINar_corner; > >> Cout <= corner0_q_real; > >> report "The value of 'corner0' is " & real'image(corner0); > >> report "The value of 'DINar_corner' is " & real'image(DINar_corner); > >> report "The value of 'Cout' is " & real'image(corner0_q_real); > >> Sout <= 1; > >> else > >> corner0_q_real <= DINar_corner/corner0; > >> Cout <= corner0_q_real; > >> report "The value of 'Cout' is " & real'image(corner0_q_real); > >> Sout <= 0; > >> end if; > >> else > >> corner0_q_real <= DINar_corner/corner0; > >> end if; > > > > It is found that when I replace below one line to the two lines in previous > > post, it has no fatal error any more. I originally added one temporary > > signal for observation. It really delays one clock for the value. It was > > bug. > > Thanks, > > > > Cout <= -DINar_corner/corner0; > > Yes, this statement inside the clocked conditional results in a 1 clock > cycle delay, or actually more since it is in the ELSE clause while the > rest of the code is in the THEN part of the IF cnt < x"02" statement. > > I think it would work fine if you made the > Cout <= -DINar_corner/corner0; > statement a concurrent statement outside of the process. Then it will > be updated as soon as the values of DINar_corner and corner0 are updated. > > -- > > Rick Thanks. But there is another reciprocal case at the 'if' clause: corner0_q_real <= corner0/DINar_corner; which are conditioned on the two data absolute value (ABS) comparison. From newsfish@newsfish Thu Aug 1 00:34:45 2024 X-Received: by 10.182.106.228 with SMTP id gx4mr797636obb.34.1443572440249; Tue, 29 Sep 2015 17:20:40 -0700 (PDT) X-Received: by 10.50.112.4 with SMTP id im4mr27504igb.1.1443572440173; Tue, 29 Sep 2015 17:20:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no13559865igb.0!news-out.google.com!n2ni15991igy.0!nntp.google.com!kq10no13559859igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 17:20:39 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Subject: Could you explain this 'assert' description? From: fl Injection-Date: Wed, 30 Sep 2015 00:20:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4018 Hi, I learn 'assert' on this link: http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html I don't understand what this passage talks about: "If the message clause is ommited, a default message is output. The severity level and the name of the design unit containing the relevant assert statement may also be output" For this example line: assert not OVERFLOW) report "Accumulator overflowed" severity failure; "If the message clause is ommited" means remove "report "Accumulator overflowed" severity failure;"? What is your opinion on this? Thanks, From newsfish@newsfish Thu Aug 1 00:34:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question about setting signal value Date: Tue, 29 Sep 2015 22:37:00 -0400 Organization: A noiseless patient Spider Lines: 101 Message-ID: References: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> <35e118e4-6179-4d0e-a632-bef93d8ad40f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Sep 2015 02:35:09 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="28234"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/F3njTo7mAKwfUTiTieC3y" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <35e118e4-6179-4d0e-a632-bef93d8ad40f@googlegroups.com> Cancel-Lock: sha1:g6BPMy36PjN2S3lXW7zpT8s9bS4= Xref: news.eternal-september.org comp.lang.vhdl:4019 On 9/29/2015 8:13 PM, fl wrote: > On Tuesday, September 29, 2015 at 6:31:01 PM UTC-4, rickman wrote: >> On 9/29/2015 5:44 PM, fl wrote: >>> On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote: >>>> Hi, >>>> >>>> When I run a simulation VHDL code, there is a out of range fatal error. The >>>> signal source is from below code. corner0 is 111.5 while DINar_corner is >>>> 111.9. The division result should be below 1. Now the console output is: >>>> # ** Note: The value of 'corner0' is 1.119000e+002 >>>> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >>>> # ** Note: The value of 'DINar_corner' is 1.115000e+002 >>>> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >>>> # ** Note: The value of 'Cout' is -1.000000e+308 >>>> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >>>> >>>> I think that Cout should be the correct value after the process updates the >>>> signal value. But the other module which accespts Cout of below code, still >>>> sees Cout's value as -1.000000e+308. This results an out of range error. >>>> >>>> >>>> What is wrong in my code and signal value understanding? >>>> >>>> >>>> Thanks a lot to you. >>>> >>>> >>>> >>>> ............. >>>> p1: process (clk) >>>> variable tmp_XP, tmp_X : real; >>>> begin >>>> if (clk'event and clk = '1') then >>>> if reset = '1' then >>>> ar <= 0.0; ai <= 0.0; >>>> br <= 0.0; bi <= 0.0; >>>> else >>>> if cnt < x"02" then >>>> if cnt = x"00" then >>>> corner0 <= DINar_corner; >>>> elsif abs(corner0) < abs(DINar_corner) then >>>> corner0_q_real <= corner0/DINar_corner; >>>> Cout <= corner0_q_real; >>>> report "The value of 'corner0' is " & real'image(corner0); >>>> report "The value of 'DINar_corner' is " & real'image(DINar_corner); >>>> report "The value of 'Cout' is " & real'image(corner0_q_real); >>>> Sout <= 1; >>>> else >>>> corner0_q_real <= DINar_corner/corner0; >>>> Cout <= corner0_q_real; >>>> report "The value of 'Cout' is " & real'image(corner0_q_real); >>>> Sout <= 0; >>>> end if; >>>> else >>>> corner0_q_real <= DINar_corner/corner0; >>>> end if; >>> >>> It is found that when I replace below one line to the two lines in previous >>> post, it has no fatal error any more. I originally added one temporary >>> signal for observation. It really delays one clock for the value. It was >>> bug. >>> Thanks, >>> >>> Cout <= -DINar_corner/corner0; >> >> Yes, this statement inside the clocked conditional results in a 1 clock >> cycle delay, or actually more since it is in the ELSE clause while the >> rest of the code is in the THEN part of the IF cnt < x"02" statement. >> >> I think it would work fine if you made the >> Cout <= -DINar_corner/corner0; >> statement a concurrent statement outside of the process. Then it will >> be updated as soon as the values of DINar_corner and corner0 are updated. >> >> -- >> >> Rick > > Thanks. But there is another reciprocal case at the 'if' clause: > > corner0_q_real <= corner0/DINar_corner; > > which are conditioned on the two data absolute value (ABS) comparison. Ok then make it a when clause corner0_q_real <= corner0/DINar_corner when abs(corner0) < abs(DINar_corner) else DINar_corner/corner0; Or you can have two signals with one used in each part of the IF statement. The point is it needs to be combinatorial logic rather than sequential. Another way of doing it is to use a variable, but it can't be used outside the process unless you assign it to a signal and that largely defeats the purpose of using it to monitor the value. -- Rick From newsfish@newsfish Thu Aug 1 00:34:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Could you explain this 'assert' description? Date: Tue, 29 Sep 2015 22:40:33 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Sep 2015 02:38:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="28788"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+xieUA9rKlxtLunIt3rdB+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Cancel-Lock: sha1:IR7tgI2IRNLAdYvPRhXwCVm33+g= Xref: news.eternal-september.org comp.lang.vhdl:4020 On 9/29/2015 8:20 PM, fl wrote: > Hi, > > I learn 'assert' on this link: > > > > http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html > > > I don't understand what this passage talks about: > > "If the message clause is ommited, a default message is output. The severity > level and the name of the design unit containing the relevant assert > statement may also be output" > > > For this example line: > > assert not OVERFLOW) report "Accumulator overflowed" severity failure; > > > "If the message clause is ommited" means remove "report "Accumulator > overflowed" severity failure;"? Yes, they are saying if you omit the report it will still print a default report with basic info like the line number, severity level and time. I don't know what is "required" by VHDL in this default report, but this is what I have seen simulators do. In fact, the default report is made even if you indicate a report. Your report is just added to the default. Try it, you'll see what your tool does. -- Rick From newsfish@newsfish Thu Aug 1 00:34:46 2024 X-Received: by 10.129.70.6 with SMTP id t6mr1669849ywa.5.1443588400430; Tue, 29 Sep 2015 21:46:40 -0700 (PDT) X-Received: by 10.50.79.136 with SMTP id j8mr292820igx.16.1443588400396; Tue, 29 Sep 2015 21:46:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no6394837qge.0!news-out.google.com!n2ni16168igy.0!nntp.google.com!kq10no13619104igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 21:46:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.75.45; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.75.45 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Review of Data Type Issues From: Jim Lewis Injection-Date: Wed, 30 Sep 2015 04:46:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3200 X-Received-Body-CRC: 644093104 Xref: news.eternal-september.org comp.lang.vhdl:4021 Some small clarifications: 1) Type Conversion Functions > > Between unrelated types. Requires an explicit function. > > Example - Unsigned to Integer, to_integer(U) > 2) Type Conversions (what many of us also call type casting) >From 1076-2008, Section 9.3.6, p 137 Explicit type conversions are allowed between closely related types. In particular, a type is closely related to itself. Other types are closely related only under the following conditions: -- Abstract numeric types -- Any abstract numeric type is closely related to any other abstract numeric type. -- Array types--Two array types are closely related if and only if the types have the same dimensionality and the element types are closely related\ No other types are closely related. > Example - Unsigned to signed, signed('0' & X_uv) > > 3) Type qualifier > > Specifies type when unclear. String arrays can be a number of types, so > require a qualifier to indicate the type. There can be multiple > overloaded functions with the same input types but different return > types, again a qualifier is required to resolve the issue. > > Example - Z_sv <= A_sv + signed'("1010") ; 4) Automatic Type Conversion: Two types convert automatically when both are subtypes of the same type. Combine this with every type is a subtype of itself, and you can conclude that two types will convert automatically when one is a subtype of the other. Hence, std_ulogic automatically converts to std_logic. Also in VHDL-2008, std_logic_vector is defined as: subtype std_logic_vector is {resolved} std_ulogic_vector ; Hence, in VHDL-2008, these two also convert automatically. This implies that in VHDL-2008 if you have an old package that includes overloading for both std_ulogic_vector and std_logic_vector, you need to remove one of them or it becomes ambiguous. > > I think this lists the ways that types are converted or indicated. > > Just trying to refresh my memory. The VHDL Tricks of the Trade (from which you borrowed examples) is still available at: http://synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf Jim From newsfish@newsfish Thu Aug 1 00:34:46 2024 X-Received: by 10.107.163.80 with SMTP id m77mr3645312ioe.0.1443614055286; Wed, 30 Sep 2015 04:54:15 -0700 (PDT) X-Received: by 10.50.45.100 with SMTP id l4mr54274igm.9.1443614055215; Wed, 30 Sep 2015 04:54:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no14424360igb.0!news-out.google.com!z4ni6825ign.0!nntp.google.com!kq10no14424351igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 04:54:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Subject: What is one element of a signed array? From: fl Injection-Date: Wed, 30 Sep 2015 11:54:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4022 Hi, After a few progress on VHDL type conversion, I have new difficulties on the element access of an unsigned array. Please see the below example. How can I get the element of rs_SUM_RESULT ? I find this is wrong: bit0 <= rs_SUM_RESULT(1); Thanks for the kind replies. ................. signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); signal bit0 : bit; From newsfish@newsfish Thu Aug 1 00:34:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Why do conversion functions need to be self defined in a project? Date: Wed, 30 Sep 2015 11:59:40 +0000 (UTC) Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <4cbc80be-939f-4b38-8b4c-0088ecdd04d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 30 Sep 2015 11:59:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="31264"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/obODJUw/AF7sKP5etZlWpywb5atMXfo4=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:nMfU7y2GvyfMTzMgfoyqdB3GJT4= Xref: news.eternal-september.org comp.lang.vhdl:4023 On Tue, 29 Sep 2015 12:00:12 -0400, rickman wrote: > On 9/29/2015 5:20 AM, Brian Drummond wrote: >> On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote: >> >>> Hi, >>> >>> I have a Matlab generated VHDL code project. It has such functions >>> defined in the testbench package. I am just curious about why these >>> looks frequent used functions need to write in such a project. It >>> makes the test bench file very long, not friendly reading to me. >> >> Put them in a utilities package so they don't clutter up the testbench. > I think the OP is using a utility to generate a test bench and it is > adding the various functions which are *not* part of any of the > conventional packages. So they stick them in the main file of the test > bench. If he moves these functions to a package he will need to do the > same work every time he generates the test bench again. Ah, then he has a Matlab problem rather than a VHDL problem. Hopefully someone else can help. -- Brian From newsfish@newsfish Thu Aug 1 00:34:47 2024 X-Received: by 10.13.224.132 with SMTP id j126mr2867894ywe.13.1443614716072; Wed, 30 Sep 2015 05:05:16 -0700 (PDT) X-Received: by 10.50.143.4 with SMTP id sa4mr54909igb.15.1443614716042; Wed, 30 Sep 2015 05:05:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no6542986qge.0!news-out.google.com!z4ni6830ign.0!nntp.google.com!kq10no14435602igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 05:05:15 -0700 (PDT) In-Reply-To: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <92e4f30a-b191-4959-b64a-67e409261b77@googlegroups.com> Subject: Re: What is one element of a signed array? From: fl Injection-Date: Wed, 30 Sep 2015 12:05:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4024 On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: > Hi, > > After a few progress on VHDL type conversion, I have new difficulties on > the element access of an unsigned array. Please see the below example. > > How can I get the element of rs_SUM_RESULT ? > > I find this is wrong: > bit0 <= rs_SUM_RESULT(1); > > > Thanks for the kind replies. > > ................. > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); > signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); > signal bit0 : bit; Using to_bit seems to work in my previous post. But for convert rs_SUM_RESULT to BYTE, I don't see a simple way yet. They are different types and widths. What is your method? Thanks, type BYTE is array (0 to 7) of BIT; signal sig_byte : BYTE; signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); From newsfish@newsfish Thu Aug 1 00:34:47 2024 X-Received: by 10.13.242.134 with SMTP id b128mr3235081ywf.7.1443617048775; Wed, 30 Sep 2015 05:44:08 -0700 (PDT) X-Received: by 10.50.65.66 with SMTP id v2mr57664igs.5.1443617048706; Wed, 30 Sep 2015 05:44:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z77no6558467qge.1!news-out.google.com!n2ni16519igy.0!nntp.google.com!kq10no13912281igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 05:44:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> Subject: Where does the XOR come to play? From: fl Injection-Date: Wed, 30 Sep 2015 12:44:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: news.eternal-september.org comp.lang.vhdl:4025 Hi, I am working on a LUT in a project. The input entries are signed. In order to same memory, only positive entries are considered in the LUT. Thus, negative input is first converted to positive data. Then, the result is converted back to negative. These input data is 2's complementary format. On the original paper, it had the following description. I am still new to FPGA. I am not clear about where and how to use 'XOR' in the process. Could you explain it to me? Thanks a lot. Further reduction in the memory size is achieved by storing only positive values in the LUT. The sign of the division result can be evaluated by an XOR gate. From newsfish@newsfish Thu Aug 1 00:34:48 2024 From: "Michael Kellett" Newsgroups: comp.lang.vhdl Subject: Re: Where does the XOR come to play? Date: wed, 30 sep 2015 14:51:19 +0100 Message-ID: Content-Type: text/plain; charset="iso-8859-1" References: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> X-Newsreader: UseNeXT 5.64 Organization: Welcome to Aviteo Ltd DE Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsreader4.netcologne.de!news.netcologne.de!feeder1.xsusenet.com!feeder.usenet.farm!94.232.116.13.MISMATCH!feed.xsnews.nl!border03.ams.xsnews.nl!feeder03.ams.xsnews.nl!abp002.ams.xsnews.nl!usenext.xennanews.com!not-for-mail Lines: 30 Injection-Date: Wed, 30 Sep 2015 15:51:34 +0200 Injection-Info: usenext.xennanews.com; mail-complaints-to="usenext@xennanews.com" Xref: news.eternal-september.org comp.lang.vhdl:4026 fl: > Hi, > > I am working on a LUT in a project. The input entries are signed. In order to > same memory, only positive entries are considered in the LUT. Thus, negative > input is first converted to positive data. Then, the result is converted back > to negative. These input data is 2's complementary format. > > On the original paper, it had the following description. I am still new to > FPGA. I am not clear about where and how to use 'XOR' in the process. > > Could you explain it to me? Thanks a lot. > > > > Further reduction in the memory size is achieved by storing only positive > values in the LUT. The sign of the division result can be evaluated by an XOR > gate. XORing the signs of the multiplier and multiplicand to get the sign of the answer ? MK From newsfish@newsfish Thu Aug 1 00:34:48 2024 X-Received: by 10.13.223.129 with SMTP id i123mr3873601ywe.33.1443629483719; Wed, 30 Sep 2015 09:11:23 -0700 (PDT) X-Received: by 10.50.147.100 with SMTP id tj4mr344215igb.2.1443629483682; Wed, 30 Sep 2015 09:11:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z77no6640609qge.1!news-out.google.com!z4ni7007ign.0!nntp.google.com!kq10no14630996igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 09:11:22 -0700 (PDT) In-Reply-To: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What is one element of a signed array? From: KJ Injection-Date: Wed, 30 Sep 2015 16:11:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 19 Xref: news.eternal-september.org comp.lang.vhdl:4027 On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: > Hi, >=20 > After a few progress on VHDL type conversion, I have new difficulties on > the element access of an unsigned array. Please see the below example. >=20 > How can I get the element of rs_SUM_RESULT ? >=20 > I find this is wrong: > bit0 <=3D rs_SUM_RESULT(1); >=20 You haven't said what you're trying to do nor have you said in what way you= are finding something 'wrong'. I can guess that because you call the sign= al 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for what= ever reason you've selected bit 1 instead. bit0 <=3D rs_SUM_RESULT(0); Kevin From newsfish@newsfish Thu Aug 1 00:34:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Where does the XOR come to play? Date: Wed, 30 Sep 2015 15:56:28 -0400 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Sep 2015 19:54:35 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="25131"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+E7VW/SheDnTWi246rjgjl" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> Cancel-Lock: sha1:FcnbJLzRy9hbCSnfsUGd9jTxAz4= Xref: news.eternal-september.org comp.lang.vhdl:4028 On 9/30/2015 8:44 AM, fl wrote: > Hi, > > I am working on a LUT in a project. The input entries are signed. In order to > same memory, only positive entries are considered in the LUT. Thus, negative > input is first converted to positive data. Then, the result is converted back > to negative. These input data is 2's complementary format. > > On the original paper, it had the following description. I am still new to > FPGA. I am not clear about where and how to use 'XOR' in the process. > > Could you explain it to me? Thanks a lot. > > > > Further reduction in the memory size is achieved by storing only positive > values in the LUT. The sign of the division result can be evaluated by an XOR > gate. Are you doing a division by LUT? What are the sizes of your input operands? The sign of the output will be the XOR of the sign of the two inputs to a division, just as Michael indicated for a multiplication. -- Rick From newsfish@newsfish Thu Aug 1 00:34:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is one element of a signed array? Date: Wed, 30 Sep 2015 16:01:05 -0400 Organization: A noiseless patient Spider Lines: 45 Message-ID: References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> <92e4f30a-b191-4959-b64a-67e409261b77@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Sep 2015 19:59:12 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="26420"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+D+7ZTLqlCLWjad92rIy9d" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <92e4f30a-b191-4959-b64a-67e409261b77@googlegroups.com> Cancel-Lock: sha1:ry+V+eC4asuEhZHDP1nTcfRIw6U= Xref: news.eternal-september.org comp.lang.vhdl:4029 On 9/30/2015 8:05 AM, fl wrote: > On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: >> Hi, >> >> After a few progress on VHDL type conversion, I have new difficulties on >> the element access of an unsigned array. Please see the below example. >> >> How can I get the element of rs_SUM_RESULT ? >> >> I find this is wrong: >> bit0 <= rs_SUM_RESULT(1); >> >> >> Thanks for the kind replies. >> >> ................. >> signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); >> signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); >> signal bit0 : bit; > > Using to_bit seems to work in my previous post. But for convert > rs_SUM_RESULT to BYTE, I don't see a simple way yet. They are different > types and widths. What is your method? > Thanks, > > > > > type BYTE is array (0 to 7) of BIT; > signal sig_byte : BYTE; > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); This begs the question of why you need to use a bit type? They don't do anything the signed type won't do. I don't think there are any standard conversion routines for signed or unsigned to a bit vector. You will need to write one. It is just a function that takes a signed value as input and returns a bit vector with the same width. It will need a loop that assigns each bit one at a time using the conversion you found for the single bit. The input and output can be unconstrained which means it will work for any width of data. -- Rick From newsfish@newsfish Thu Aug 1 00:34:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Where does the XOR come to play? Date: Wed, 30 Sep 2015 21:20:30 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 25 Message-ID: References: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4030 fl wrote: > I am working on a LUT in a project. The input entries are signed. > In order to same memory, only positive entries are considered > in the LUT. Thus, negative input is first converted to positive data. > Then, the result is converted back to negative. > These input data is 2's complementary format. > On the original paper, it had the following description. > I am still new to FPGA. I am not clear about where and how > to use 'XOR' in the process. > Could you explain it to me? Thanks a lot. Sounds like you need a twos complement absolute value. If the input value is positive, it is fine. If negative, invert all the bits (with XOR) and add one. In the end, to convert back to twos complement, if the result should be negative invert the bits (XOR again) and add one. -- glen From newsfish@newsfish Thu Aug 1 00:34:49 2024 X-Received: by 10.129.57.9 with SMTP id g9mr5991153ywa.19.1443664555785; Wed, 30 Sep 2015 18:55:55 -0700 (PDT) X-Received: by 10.50.143.4 with SMTP id sa4mr4051igb.15.1443664555759; Wed, 30 Sep 2015 18:55:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no6833744qge.0!news-out.google.com!z4ni7410ign.0!nntp.google.com!kq10no15023293igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 18:55:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What is one element of a signed array? From: fl Injection-Date: Thu, 01 Oct 2015 01:55:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4031 On Wednesday, September 30, 2015 at 12:11:28 PM UTC-4, KJ wrote: > On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: > > Hi, > >=20 > > After a few progress on VHDL type conversion, I have new difficulties o= n > > the element access of an unsigned array. Please see the below example. > >=20 > > How can I get the element of rs_SUM_RESULT ? > >=20 > > I find this is wrong: > > bit0 <=3D rs_SUM_RESULT(1); > >=20 >=20 > You haven't said what you're trying to do nor have you said in what way y= ou are finding something 'wrong'. I can guess that because you call the si= gnal 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for wh= atever reason you've selected bit 1 instead. >=20 > bit0 <=3D rs_SUM_RESULT(0); >=20 > Kevin Excuse me. I didn't say the question clearly.=20 My original intention was to convert array larger or smaller to BYTE. It was inspired from an online code. With rickman's new post, I know the=20 less important role of bit vector. The conversion is to use a for loop on= =20 bit level. That's all to my question. With several VHDL type coding projects, I feel it is clear and manageable after several tryings on it in the past. Thanks, you folks.=20 type BYTE is array (0 to 7) of BIT; signal sig_byte : BYTE; signal rs_SUM_RESULT : signed(4 downto 0) :=3D (others =3D> '0');=20 rs_SUM_RESULT From newsfish@newsfish Thu Aug 1 00:34:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is one element of a signed array? Date: Wed, 30 Sep 2015 23:40:16 -0400 Organization: A noiseless patient Spider Lines: 57 Message-ID: References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 1 Oct 2015 03:38:26 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="17740"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18kyvOkO56Ddj/hyG1AQmOw" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:MrghEdnOVbK699LxEFSMuG+cM0E= Xref: news.eternal-september.org comp.lang.vhdl:4032 On 9/30/2015 9:55 PM, fl wrote: > On Wednesday, September 30, 2015 at 12:11:28 PM UTC-4, KJ wrote: >> On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: >>> Hi, >>> >>> After a few progress on VHDL type conversion, I have new difficulties on >>> the element access of an unsigned array. Please see the below example. >>> >>> How can I get the element of rs_SUM_RESULT ? >>> >>> I find this is wrong: >>> bit0 <= rs_SUM_RESULT(1); >>> >> >> You haven't said what you're trying to do nor have you said in what way you are finding something 'wrong'. I can guess that because you call the signal 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for whatever reason you've selected bit 1 instead. >> >> bit0 <= rs_SUM_RESULT(0); >> >> Kevin > > Excuse me. I didn't say the question clearly. > My original intention was to convert array larger or smaller to BYTE. > It was inspired from an online code. With rickman's new post, I know the > less important role of bit vector. The conversion is to use a for loop on > bit level. That's all to my question. With several VHDL type coding > projects, I feel it is clear and manageable after several tryings on it in > the past. Thanks, you folks. > > > > type BYTE is array (0 to 7) of BIT; > signal sig_byte : BYTE; > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); > rs_SUM_RESULT Not sure if your post was cut off. I never use bits, so I am not so familiar with that data type, but it seems the std_logic_1164 library has conversion functions between bit or bit_vector and std_logic or std_logic_vector respectively. That would make a conversion with signed and unsigned trivial without using looping or making your own function. Are these problems homework for a class? If so, I think you are getting the right kind of advice to help you see the solution rather than just being given the answers. BTW, BYTE can be defined this way too... type BYTE is bit_vector (7 downto 0); This will work with all the conversion functions while I'm not sure if your BYTE declaration will. Like I said, I'm a bit rusty with this stuff. -- Rick From newsfish@newsfish Thu Aug 1 00:34:50 2024 X-Received: by 10.107.134.150 with SMTP id q22mr8183177ioi.31.1443698634283; Thu, 01 Oct 2015 04:23:54 -0700 (PDT) X-Received: by 10.50.66.144 with SMTP id f16mr22756igt.14.1443698634214; Thu, 01 Oct 2015 04:23:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no15218303igb.0!news-out.google.com!z4ni7795ign.0!nntp.google.com!kq10no15218293igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2015 04:23:53 -0700 (PDT) In-Reply-To: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1e3d47f7-8a4c-43a9-88be-5e0c95366367@googlegroups.com> Subject: Re: What is one element of a signed array? From: Thomas Stanka Injection-Date: Thu, 01 Oct 2015 11:23:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4033 Am Mittwoch, 30. September 2015 13:54:19 UTC+2 schrieb fl: [..] > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); > signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); > signal bit0 : bit; This depends on _your_ definition of signed. All standardised definitions use (un)signed as vector of std_logic. so the code would work if bit0 is of type std_logic, should even work with std_ulogic. Else you need to convert the result of singedSignal(1) to bit before assigning to a bit value. From newsfish@newsfish Thu Aug 1 00:34:50 2024 X-Received: by 10.50.122.2 with SMTP id lo2mr2982671igb.2.1443710917228; Thu, 01 Oct 2015 07:48:37 -0700 (PDT) X-Received: by 10.50.4.70 with SMTP id i6mr41110igi.12.1443710917163; Thu, 01 Oct 2015 07:48:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!kq10no15313846igb.0!news-out.google.com!n2ni17574igy.0!nntp.google.com!kq10no15313838igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2015 07:48:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> <03072ae3-7e59-44a1-8ed5-21b3aeaa8bc3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Multiplier using 1 bit full adder problem From: zhangth1991@gmail.com Injection-Date: Thu, 01 Oct 2015 14:48:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1419 X-Received-Body-CRC: 115681467 Xref: news.eternal-september.org comp.lang.vhdl:4034 It is a vector multiplier which use a full adder. And we should judge if a or b is positive and negative to get correct answer. From newsfish@newsfish Thu Aug 1 00:34:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: What is one element of a signed array? Date: Thu, 1 Oct 2015 15:57:07 +0000 (UTC) Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 1 Oct 2015 15:57:07 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0a3c9f09d5246ee6d0bbab9a3b7899b1"; logging-data="18761"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19d8Nkd7xV22Rdh0wj5MYy3" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:YYhnN07/iEsv5EjnlWp+JDPv1zQ= Xref: news.eternal-september.org comp.lang.vhdl:4035 On Wed, 30 Sep 2015 04:54:14 -0700, fl wrote: > Hi, > > After a few progress on VHDL type conversion, I have new difficulties on > the element access of an unsigned array. Please see the below example. > > How can I get the element of rs_SUM_RESULT ? > > I find this is wrong: > bit0 <= rs_SUM_RESULT(1); > > > Thanks for the kind replies. > > ................. > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); > signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); > signal bit0 : bit; Assuming that you're using the signed/unsigned from ieee.numeric_std? std_logic. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:34:51 2024 X-Received: by 10.50.43.233 with SMTP id z9mr3542795igl.9.1443719070081; Thu, 01 Oct 2015 10:04:30 -0700 (PDT) X-Received: by 10.50.143.12 with SMTP id sa12mr15411igb.7.1443719070064; Thu, 01 Oct 2015 10:04:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no14655995igb.0!news-out.google.com!z4ni8040ign.0!nntp.google.com!kq10no15372150igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2015 10:04:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Multiplier using 1 bit full adder From: zhangth1991@gmail.com Injection-Date: Thu, 01 Oct 2015 17:04:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4036 I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me? My code is as followed --multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Multiplier_VHDL is GENERIC (WIDTH:INTEGER); PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); end entity Multiplier_VHDL; architecture Behavioral of Multiplier_VHDL is signal a_temp:std_logic_vector(width-1 downto 0); signal b_temp:std_logic_vector(width-1 downto 0); signal mid:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal cout_mid:std_logic_vector(2*width downto 0):=(others=>'0'); signal y_temp:std_logic_vector(2*width-1 downto 0); begin proc_multiplier1: process(a_temp,b_temp) begin a_temp<=a; b_temp<=b; calculation_out: for i in 0 to width-1 loop if b_temp(i)='1' then mid(width-1+i downto i)<=a_temp; end if; calculation_in: for j in 0 to 2*width-1 loop y_temp(j)<=mid_temp(j) xor mid(j) xor cout_mid(j); cout_mid(j+1)<=(mid_temp(j) and mid(j)) or (mid_temp(j) and cout_mid(j)) or (cout_mid(j) and mid(j)); end loop calculation_in; mid_temp<=y_temp; cout_mid<=(others=>'0'); mid<=(others=>'0'); end loop calculation_out; end process; y<=y_temp; end architecture Behavioral; There is a warning message Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf From newsfish@newsfish Thu Aug 1 00:34:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder Date: Thu, 1 Oct 2015 13:38:26 -0400 Organization: A noiseless patient Spider Lines: 69 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 1 Oct 2015 17:36:28 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="519"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ZkKLd6mDhwHt0hLgUraVb" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:TMWweKa/mbdTf/axYWlaIJBhElQ= Xref: news.eternal-september.org comp.lang.vhdl:4037 On 10/1/2015 1:04 PM, zhangth1991@gmail.com wrote: > I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me? > > My code is as followed > --multiplier > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity Multiplier_VHDL is > GENERIC (WIDTH:INTEGER); > PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); > end entity Multiplier_VHDL; > > architecture Behavioral of Multiplier_VHDL is > signal a_temp:std_logic_vector(width-1 downto 0); > signal b_temp:std_logic_vector(width-1 downto 0); > signal mid:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal cout_mid:std_logic_vector(2*width downto 0):=(others=>'0'); > signal y_temp:std_logic_vector(2*width-1 downto 0); > begin > proc_multiplier1: > process(a_temp,b_temp) > begin > a_temp<=a; > b_temp<=b; > calculation_out: > for i in 0 to width-1 loop > if b_temp(i)='1' then > mid(width-1+i downto i)<=a_temp; > end if; > calculation_in: > for j in 0 to 2*width-1 loop > y_temp(j)<=mid_temp(j) xor mid(j) xor cout_mid(j); > cout_mid(j+1)<=(mid_temp(j) and mid(j)) or (mid_temp(j) and cout_mid(j)) or (cout_mid(j) and mid(j)); > end loop calculation_in; > mid_temp<=y_temp; > cout_mid<=(others=>'0'); > mid<=(others=>'0'); > end loop calculation_out; > > end process; > > y<=y_temp; > > end architecture Behavioral; > > There is a warning message > Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf I don't know what this warning is about. Any chance you have two copies of the simulator running? I don't understand your code. I see one error. Your process sensitivity list includes two signals that are updated within the process. I think you meant to use a and b in the sensitivity list, no? You need to run your code in the simulator and explore the various signals to see if the code is doing what you need. Posting code here to look for some silly mistakes is ok, but no one is likely to debug your code for you. I'm not even sure how it is supposed to work. You seem to have a lot of extraneous signals for a simple multiplier. -- Rick From newsfish@newsfish Thu Aug 1 00:34:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder Date: Thu, 01 Oct 2015 14:28:16 -0400 Organization: Alacron, Inc. Lines: 21 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 1 Oct 2015 18:26:18 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="12021"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/A7elSeu5Vf7/egah6Bic5afVGRdTENVM=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:JAozhjvbdZGH09RP2iZO5ra8lCo= Xref: news.eternal-september.org comp.lang.vhdl:4038 zhangth1991@gmail.com wrote: > I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me? > > My code is as followed [code snipped] > There is a warning message > Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf That warning is something I've run into a lot with ModelSim, especially older versions. It probably has nothing to do with your problems, as ModelSim will simply create a WLF file with some random name and use it instead of "vsim.wlf" I seem to recall this happens after you have run some number of different projects and not cleaned up the old vsim.wlf files. By the way, these files can get quite large and it is usually worth it to remove them when you are done with a project to reclaim the disk space. -- Gabor From newsfish@newsfish Thu Aug 1 00:34:52 2024 X-Received: by 10.50.79.234 with SMTP id m10mr2649511igx.5.1443773259471; Fri, 02 Oct 2015 01:07:39 -0700 (PDT) X-Received: by 10.50.28.19 with SMTP id x19mr41030igg.16.1443773259392; Fri, 02 Oct 2015 01:07:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no14804901igb.0!news-out.google.com!n2ni18230igy.0!nntp.google.com!kq10no15615731igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 2 Oct 2015 01:07:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ab578b2-956a-41cb-8f2a-cfaf07b3480a@googlegroups.com> Subject: Re: Multiplier using 1 bit full adder From: zhangth1991@gmail.com Injection-Date: Fri, 02 Oct 2015 08:07:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4039 The problem is I dont know why I cannot assign y<=y_temp when a and b change the value From newsfish@newsfish Thu Aug 1 00:34:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer02.fr7!news.highwinds-media.com!post02.fr7!fx33.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Multiplier using 1 bit full adder References: Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 151001-2, 01/10/2015), Outbound message X-Antivirus-Status: Clean Lines: 31 Message-ID: <78rPx.23670$LT7.1399@fx33.am4> NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1443774083 81.109.142.154 (Fri, 02 Oct 2015 08:21:23 UTC) NNTP-Posting-Date: Fri, 02 Oct 2015 08:21:23 UTC Organization: virginmedia.com Date: Fri, 2 Oct 2015 09:21:19 +0100 X-Received-Body-CRC: 1773550843 X-Received-Bytes: 2341 Xref: news.eternal-september.org comp.lang.vhdl:4040 On 01/10/2015 18:04, zhangth1991@gmail.com wrote: .. > > There is a warning message > Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf > This happens when your simulation crashes, it sets a lock bit in the vsim.wlf file which prevents Modelsim from overwriting it (vsim.wlf is the default name). You can load the vsim.wlf file (vsim -view vsim.wlf) and see what lead to the crash (or get close to it). You need to delete the vsim.wlf file as Modelsim will continue to create new wlfxxxx files until the file is deleted, Hans www.ht-lab.com 02/10/2015 09:18 1,387 transcript 03/09/2015 20:21 49,152 vsim.wlf 03/11/2005 12:21 1,105 wave.do 04/09/2015 17:38 786,432 wlft1sddnc 06/09/2015 20:52 57,344 wlftgbhqzx 10/09/2015 11:35 540,672 wlftiqcymw 16/09/2015 15:17 57,344 wlftq4i743 09/09/2015 17:54 778,240 wlftq5mdd3 08/09/2015 17:44 49,152 wlftqe9ds1 05/09/2015 12:55 57,344 wlftr57znr 27/08/2015 13:59 work 16/11/2005 15:11 34 zoom.tcl 27 File(s) 2,949,498 bytes 4 Dir(s) 487,531,675,648 bytes free From newsfish@newsfish Thu Aug 1 00:34:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder Date: Fri, 02 Oct 2015 09:26:39 -0400 Organization: Alacron, Inc. Lines: 15 Message-ID: References: <4ab578b2-956a-41cb-8f2a-cfaf07b3480a@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 2 Oct 2015 13:24:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="6214"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/NYSLb4TYLd9Xo+niZOFIxPLmwJlg+oZI=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <4ab578b2-956a-41cb-8f2a-cfaf07b3480a@googlegroups.com> Cancel-Lock: sha1:/XlJmE4K1O2T08hQmf39b7CMFOY= Xref: news.eternal-september.org comp.lang.vhdl:4041 zhangth1991@gmail.com wrote: > The problem is I dont know why I cannot assign y<=y_temp when a and b change the value For simulation, only items in the process sensitivity will "change the value." In your main process, you only have a_temp and b_temp in the sensitivity list. Since these are only assigned within the process, and the process needs them to change in order to actually run, then the process never triggers and all your outputs remain undefined. You need to have a and b in the sensitivity list to trigger the process. Also it is likely that you really wanted a_temp and b_temp to be variables rather than signals. -- Gabor From newsfish@newsfish Thu Aug 1 00:34:53 2024 X-Received: by 10.129.70.6 with SMTP id t6mr14178766ywa.5.1443797417632; Fri, 02 Oct 2015 07:50:17 -0700 (PDT) X-Received: by 10.50.28.19 with SMTP id x19mr63300igg.16.1443797417598; Fri, 02 Oct 2015 07:50:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no7171920qge.0!news-out.google.com!n2ni18498igy.0!nntp.google.com!kq10no14907280igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 2 Oct 2015 07:50:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.99.250.19; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 141.99.250.19 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> Subject: VHDL From: fwetie@googlemail.com Injection-Date: Fri, 02 Oct 2015 14:50:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 8955 X-Received-Body-CRC: 2066400661 Xref: news.eternal-september.org comp.lang.vhdl:4042 hello, please i am looking for someone who can help me to solve my pb. this is my code : Bonjour a tous, je cherche de l'aide pour mon projet sur VHDL: mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. voici mes codes: --------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity Lane is port ( FPP_CLK_IN : IN std_logic; FPP_FROM_CORE : IN std_logic; DATA_IN : IN std_logic; FPP_SEC_EN : IN std_logic; FPP_TURN_SEL : IN std_logic; FPP_CORE_SEL : IN std_logic; FPP_REGP_BYP : IN std_logic; FPP_SOURCE_SEL : IN std_logic; FPP_REGN_BYP : IN std_logic; FPP_PRI_EN : IN std_logic; Primary_Port : INOUT std_logic; Secondary_Port : INOUT std_logic; FPP_TO_CORE : OUT std_logic; DATA_OUT : OUT std_logic ); end Lane; architecture archLane of Lane is component Buf port ( A : IN std_logic; Y : OUT std_logic ); end component; component BufX port ( A : IN std_logic; en : in std_logic; Y : OUT std_logic ); end component; component Mux port ( Sel : IN std_logic; E : IN std_logic; F : IN std_logic; Z : OUT std_logic ); end component; component FlipFlopP port ( CLK : IN std_logic; D : IN std_logic; Q : OUT std_logic ); end component; component FlipFlopN port ( CLK : IN std_logic; D : IN std_logic; Q : OUT std_logic ); end component; signal Sec_buf_in_to_Mux6 : std_logic; signal Sel_BufX_in_to_Mux3 : std_logic; signal Sec_Pri_Buf_IN_TO_MUX6 :std_logic; signal Sec_Pri_BufY_IN_TO_MUX1 : std_logic; signal sig_from_Mux1_ff1_to_Mux3_ff3 : std_logic; signal sig_from_Mux1_to_FF1 : std_logic; signal sig_from_Mux5_to_FF2_Mux2 :std_logic; signal sig_from_FF2_to_Mux2 : std_logic; signal sig_from_Mux3_to_FF3 : std_logic; signal sig_from_Mux4_to_Mux5 : std_logic; signal FPP_TO_CORE_INT : std_logic; begin FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE Sec_Buf_In : Buf port map ( A => Secondary_Port, Y => Sec_buf_in_to_Mux6); Sec_BufX_Out : BufX port map ( A => Sel_BufX_in_to_Mux3, en => FPP_SEC_EN , Y => Secondary_Port); Pri_Buf_In : Buf port map ( A => Primary_Port, Y => Sec_Pri_Buf_IN_TO_MUX6); Pri_BufX_Out : BufX port map ( A => Sec_Pri_BufY_IN_TO_MUX1, en => FPP_PRI_EN, Y => Primary_Port); MUX1 : Mux port map ( E => Sig_from_Mux1_ff1_to_Mux3_ff3, F => sig_from_Mux1_to_FF1, Z => Sec_Pri_BufY_IN_TO_MUX1, Sel => FPP_REGN_BYP); MUX2 : Mux port map ( E => sig_from_Mux5_to_FF2_Mux2, F => sig_from_FF2_to_Mux2, Z => DATA_OUT, Sel => FPP_REGP_BYP ); MUX3 : Mux port map ( E => sig_from_Mux1_ff1_to_Mux3_ff3, F => sig_from_Mux3_to_FF3, Z => Sel_BufX_in_to_Mux3, Sel => FPP_REGN_BYP ); MUX4 : Mux port map ( E => DATA_IN, F => FPP_FROM_CORE, Z => sig_from_Mux4_to_Mux5, Sel => FPP_TURN_SEL ); MUX5 : Mux port map ( E => sig_from_Mux4_to_Mux5, F => FPP_TO_CORE_INT, Z => sig_from_Mux5_to_FF2_Mux2, Sel => FPP_CORE_SEL ); MUX6 : Mux port map ( E => Sec_buf_in_to_Mux6, F => Sec_pri_buf_in_to_Mux6, Z => FPP_TO_CORE_INT, Sel => FPP_SOURCE_SEL ); Flipflop1 : FlipFlopN port map ( Q => sig_from_Mux1_ff1_to_Mux3_ff3, D => sig_from_Mux1_to_FF1, CLK => FPP_CLK_IN ); Flipflop2 : FlipFlopP port map ( Q => sig_from_Mux5_to_FF2_Mux2, D => sig_from_FF2_to_Mux2, CLK => FPP_CLK_IN ); Flipflop3 : FlipFlopN port map ( Q => sig_from_Mux1_ff1_to_Mux3_ff3, D => sig_from_Mux3_to_FF3, CLK => FPP_CLK_IN ); end archLane; et mon testbench library ieee; use ieee.std_logic_1164.all; entity testPrimToSecCase1 is end testPrimToSecCase1; architecture archPrimToSecTest of testPrimToSecCase1 is component Lane Port ( FPP_CLK_IN : IN std_logic; FPP_FROM_CORE : IN std_logic; DATA_IN : IN std_logic; FPP_SEC_EN : IN std_logic; FPP_TURN_SEL : IN std_logic; FPP_CORE_SEL : IN std_logic; FPP_REGP_BYP : IN std_logic; FPP_SOURCE_SEL : IN std_logic; FPP_REGN_BYP : IN std_logic; FPP_PRI_EN : IN std_logic; Primary_Port : INOUT std_logic; Secondary_Port : INOUT std_logic; DATA_OUT : OUT std_logic; FPP_TO_CORE : OUT std_logic ); end component; signal S_FPP_CLK_IN : std_logic; signal S_FPP_FROM_CORE : std_logic; signal S_DATA_IN : std_logic; signal S_FPP_SEC_EN : std_logic; signal S_FPP_TURN_SEL : std_logic; signal S_FPP_CORE_SEL : std_logic; signal S_FPP_REGP_BYP : std_logic; signal S_FPP_SOURCE_SEL : std_logic; signal S_FPP_REGN_BYP : std_logic; signal S_FPP_PRI_EN : std_logic; signal S_Primary_Port : std_logic; signal S_Secondary_Port : std_logic; signal s_FPP_TO_CORE_INT : std_logic; FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE begin U : Lane port map ( S_FPP_CLK_IN, S_FPP_FROM_CORE, S_DATA_IN, S_FPP_SEC_EN, S_FPP_TURN_SEL, S_FPP_CORE_SEL, S_FPP_REGP_BYP, S_FPP_SOURCE_SEL, S_FPP_REGN_BYP, S_FPP_PRI_EN, S_Primary_Port, S_Secondary_Port ); processClock : process begin S_FPP_CLK_IN <= '0'; wait for 10 ns; S_FPP_CLK_IN <= '1'; wait for 10 ns; end process processClock; Stimuli : process begin S_FPP_FROM_CORE <= '0'; S_DATA_IN <= '0'; S_FPP_SEC_EN <= '0'; S_FPP_TURN_SEL <= '0'; S_FPP_CORE_SEL <= '0'; S_FPP_REGP_BYP <= '0'; S_FPP_SOURCE_SEL <= '0'; S_FPP_REGN_BYP <= '0'; S_FPP_PRI_EN <= '0'; S_Primary_Port <= '0'; S_Secondary_Port <= '0'; wait until S_FPP_CLK_IN <= '1'; S_FPP_FROM_CORE <= '-'; S_DATA_IN <= '-'; S_FPP_SEC_EN <= '1'; S_FPP_TURN_SEL <= '-'; S_FPP_CORE_SEL <= '1'; S_FPP_REGP_BYP <= '0'; S_FPP_SOURCE_SEL <= '0'; S_FPP_REGN_BYP <= '0'; S_FPP_PRI_EN <= '0'; wait until S_FPP_CLK_IN <= '1'; S_Primary_Port <= '0'; wait until S_FPP_CLK_IN <= '1'; S_Secondary_Port <= '1'; wait until S_FPP_CLK_IN <= '1'; end process Stimuli; end archPrimToSecTest; i am looking for sombody to correct my testbench. thanks you for your help. Franck From newsfish@newsfish Thu Aug 1 00:34:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: VHDL Date: Fri, 02 Oct 2015 15:20:11 -0400 Organization: Alacron, Inc. Lines: 66 Message-ID: References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 2 Oct 2015 19:18:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="26755"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+3jtCFSZG0pfXXf2LcPEINEQce3TaIj78=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> Cancel-Lock: sha1:mBVNf05T9wAoGt27Jza7tKGFswY= Xref: news.eternal-september.org comp.lang.vhdl:4043 fwetie@googlemail.com wrote: > hello, > please i am looking for someone who can help me to solve my pb. > this is my code : > > Bonjour a tous, > je cherche de l'aide pour mon projet sur VHDL: > mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > voici mes codes: > [snip] > Stimuli : process > begin > > S_FPP_FROM_CORE <= '0'; > S_DATA_IN <= '0'; > S_FPP_SEC_EN <= '0'; > S_FPP_TURN_SEL <= '0'; > S_FPP_CORE_SEL <= '0'; > S_FPP_REGP_BYP <= '0'; > S_FPP_SOURCE_SEL <= '0'; > S_FPP_REGN_BYP <= '0'; > S_FPP_PRI_EN <= '0'; > S_Primary_Port <= '0'; > S_Secondary_Port <= '0'; > > wait until S_FPP_CLK_IN <= '1'; > > S_FPP_FROM_CORE <= '-'; > S_DATA_IN <= '-'; > S_FPP_SEC_EN <= '1'; > S_FPP_TURN_SEL <= '-'; > S_FPP_CORE_SEL <= '1'; > S_FPP_REGP_BYP <= '0'; > S_FPP_SOURCE_SEL <= '0'; > S_FPP_REGN_BYP <= '0'; > S_FPP_PRI_EN <= '0'; > > wait until S_FPP_CLK_IN <= '1'; > > S_Primary_Port <= '0'; > wait until S_FPP_CLK_IN <= '1'; > > S_Secondary_Port <= '1'; > wait until S_FPP_CLK_IN <= '1'; > > > end process Stimuli; > > end archPrimToSecTest; > i am looking for sombody to correct my testbench. > thanks you for your help. > Franck Well, you didn't give much of a description of why the testbench does not function correctly, but my guess is that you wanted to wait for edges of the clock and not levels. Also it's unlikely that you want to wait for a clock signal to be "less than or equal to 1" even if you did want to check for a level. Probably something like wait until rising_edge (S_FPP_CLK_IN); -- Gabor From newsfish@newsfish Thu Aug 1 00:34:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder Date: Fri, 2 Oct 2015 16:42:21 -0400 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <4ab578b2-956a-41cb-8f2a-cfaf07b3480a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 2 Oct 2015 20:40:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="13053"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18A/Xe6tqekeY8n5zSvOPfU" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:HUGRhP9WsL+ZNcYxTB8A/OFTW7E= Xref: news.eternal-september.org comp.lang.vhdl:4044 On 10/2/2015 9:26 AM, GaborSzakacs wrote: > zhangth1991@gmail.com wrote: >> The problem is I dont know why I cannot assign y<=y_temp when a and b >> change the value > > For simulation, only items in the process sensitivity > will "change the value." In your main process, you > only have a_temp and b_temp in the sensitivity list. > Since these are only assigned within the process, and > the process needs them to change in order to actually > run, then the process never triggers and all your outputs > remain undefined. You need to have a and b in the sensitivity > list to trigger the process. Also it is likely that you really > wanted a_temp and b_temp to be variables rather than signals. I've already told him his sensitivity list is wrong. Maybe he didn't see my message. a_temp and b_temp really aren't needed. They are never reassigned, so they are just duplicates of a and b. He should just use a and b in the expressions instead of a_temp and b_temp. I'm not sure what he is doing with this code actually. He seems to be intending a bit serial adder, but rather than describing a shifter with a one bit adder, he is describing a standard parallel addition, one bit at a time, without a clock. -- Rick From newsfish@newsfish Thu Aug 1 00:34:54 2024 X-Received: by 10.182.29.40 with SMTP id g8mr16593319obh.27.1443861329993; Sat, 03 Oct 2015 01:35:29 -0700 (PDT) X-Received: by 10.50.45.100 with SMTP id l4mr12024igm.9.1443861329967; Sat, 03 Oct 2015 01:35:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no16047456igb.0!news-out.google.com!n2ni19199igy.0!nntp.google.com!kq10no15080436igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Oct 2015 01:35:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.152.155.140; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 88.152.155.140 References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL From: fwetie@googlemail.com Injection-Date: Sat, 03 Oct 2015 08:35:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4045 Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: > fwetie@googlemail.com wrote: > > hello, > > please i am looking for someone who can help me to solve my pb. > > this is my code : > > > > Bonjour a tous, > > je cherche de l'aide pour mon projet sur VHDL: > > mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > > voici mes codes: > > > > [snip] > > > Stimuli : process > > begin > > > > S_FPP_FROM_CORE <= '0'; > > S_DATA_IN <= '0'; > > S_FPP_SEC_EN <= '0'; > > S_FPP_TURN_SEL <= '0'; > > S_FPP_CORE_SEL <= '0'; > > S_FPP_REGP_BYP <= '0'; > > S_FPP_SOURCE_SEL <= '0'; > > S_FPP_REGN_BYP <= '0'; > > S_FPP_PRI_EN <= '0'; > > S_Primary_Port <= '0'; > > S_Secondary_Port <= '0'; > > > > wait until S_FPP_CLK_IN <= '1'; > > > > S_FPP_FROM_CORE <= '-'; > > S_DATA_IN <= '-'; > > S_FPP_SEC_EN <= '1'; > > S_FPP_TURN_SEL <= '-'; > > S_FPP_CORE_SEL <= '1'; > > S_FPP_REGP_BYP <= '0'; > > S_FPP_SOURCE_SEL <= '0'; > > S_FPP_REGN_BYP <= '0'; > > S_FPP_PRI_EN <= '0'; > > > > wait until S_FPP_CLK_IN <= '1'; > > > > S_Primary_Port <= '0'; > > wait until S_FPP_CLK_IN <= '1'; > > > > S_Secondary_Port <= '1'; > > wait until S_FPP_CLK_IN <= '1'; > > > > > > end process Stimuli; > > > > end archPrimToSecTest; > > i am looking for sombody to correct my testbench. > > thanks you for your help. > > Franck > > Well, you didn't give much of a description of why the testbench does > not function correctly, but my guess is that you wanted to wait for > edges of the clock and not levels. Also it's unlikely that you > want to wait for a clock signal to be "less than or equal to 1" > even if you did want to check for a level. Probably something like > > wait until rising_edge (S_FPP_CLK_IN); > > -- > Gabor danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response Franck From newsfish@newsfish Thu Aug 1 00:34:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Date: Sat, 3 Oct 2015 06:29:48 -0400 Organization: A noiseless patient Spider Lines: 77 Message-ID: References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 3 Oct 2015 10:27:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="22486"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+TXQCCuuD3zaa0lUxqxR+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:bNBX0NzYvqAg9m/KUkuSsjg8/HY= Xref: news.eternal-september.org comp.lang.vhdl:4046 On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: > Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: >> fwetie@googlemail.com wrote: >>> hello, >>> please i am looking for someone who can help me to solve my pb. >>> this is my code : >>> >>> Bonjour a tous, >>> je cherche de l'aide pour mon projet sur VHDL: >>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. >>> voici mes codes: >>> >> >> [snip] >> >>> Stimuli : process >>> begin >>> >>> S_FPP_FROM_CORE <= '0'; >>> S_DATA_IN <= '0'; >>> S_FPP_SEC_EN <= '0'; >>> S_FPP_TURN_SEL <= '0'; >>> S_FPP_CORE_SEL <= '0'; >>> S_FPP_REGP_BYP <= '0'; >>> S_FPP_SOURCE_SEL <= '0'; >>> S_FPP_REGN_BYP <= '0'; >>> S_FPP_PRI_EN <= '0'; >>> S_Primary_Port <= '0'; >>> S_Secondary_Port <= '0'; >>> >>> wait until S_FPP_CLK_IN <= '1'; >>> >>> S_FPP_FROM_CORE <= '-'; >>> S_DATA_IN <= '-'; >>> S_FPP_SEC_EN <= '1'; >>> S_FPP_TURN_SEL <= '-'; >>> S_FPP_CORE_SEL <= '1'; >>> S_FPP_REGP_BYP <= '0'; >>> S_FPP_SOURCE_SEL <= '0'; >>> S_FPP_REGN_BYP <= '0'; >>> S_FPP_PRI_EN <= '0'; >>> >>> wait until S_FPP_CLK_IN <= '1'; >>> >>> S_Primary_Port <= '0'; >>> wait until S_FPP_CLK_IN <= '1'; >>> >>> S_Secondary_Port <= '1'; >>> wait until S_FPP_CLK_IN <= '1'; >>> >>> >>> end process Stimuli; >>> >>> end archPrimToSecTest; >>> i am looking for sombody to correct my testbench. >>> thanks you for your help. >>> Franck >> >> Well, you didn't give much of a description of why the testbench does >> not function correctly, but my guess is that you wanted to wait for >> edges of the clock and not levels. Also it's unlikely that you >> want to wait for a clock signal to be "less than or equal to 1" >> even if you did want to check for a level. Probably something like >> >> wait until rising_edge (S_FPP_CLK_IN); >> >> -- >> Gabor > > danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response > Franck What do you see in your simulation? -- Rick From newsfish@newsfish Thu Aug 1 00:34:55 2024 X-Received: by 10.67.24.39 with SMTP id if7mr5075694pad.24.1444052057354; Mon, 05 Oct 2015 06:34:17 -0700 (PDT) X-Received: by 10.50.4.70 with SMTP id i6mr90236igi.12.1444052057313; Mon, 05 Oct 2015 06:34:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no15650267igb.0!news-out.google.com!n2ni21275igy.0!nntp.google.com!kq10no16977223igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Oct 2015 06:34:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.99.250.19; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 141.99.250.19 References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> Subject: Re: VHDL From: fwetie@googlemail.com Injection-Date: Mon, 05 Oct 2015 13:34:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4047 Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: > On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: > > Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: > >> fwetie@googlemail.com wrote: > >>> hello, > >>> please i am looking for someone who can help me to solve my pb. > >>> this is my code : > >>> > >>> Bonjour a tous, > >>> je cherche de l'aide pour mon projet sur VHDL: > >>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > >>> voici mes codes: > >>> > >> > >> [snip] > >> > >>> Stimuli : process > >>> begin > >>> > >>> S_FPP_FROM_CORE <= '0'; > >>> S_DATA_IN <= '0'; > >>> S_FPP_SEC_EN <= '0'; > >>> S_FPP_TURN_SEL <= '0'; > >>> S_FPP_CORE_SEL <= '0'; > >>> S_FPP_REGP_BYP <= '0'; > >>> S_FPP_SOURCE_SEL <= '0'; > >>> S_FPP_REGN_BYP <= '0'; > >>> S_FPP_PRI_EN <= '0'; > >>> S_Primary_Port <= '0'; > >>> S_Secondary_Port <= '0'; > >>> > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_FPP_FROM_CORE <= '-'; > >>> S_DATA_IN <= '-'; > >>> S_FPP_SEC_EN <= '1'; > >>> S_FPP_TURN_SEL <= '-'; > >>> S_FPP_CORE_SEL <= '1'; > >>> S_FPP_REGP_BYP <= '0'; > >>> S_FPP_SOURCE_SEL <= '0'; > >>> S_FPP_REGN_BYP <= '0'; > >>> S_FPP_PRI_EN <= '0'; > >>> > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_Primary_Port <= '0'; > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_Secondary_Port <= '1'; > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> > >>> end process Stimuli; > >>> > >>> end archPrimToSecTest; > >>> i am looking for sombody to correct my testbench. > >>> thanks you for your help. > >>> Franck > >> > >> Well, you didn't give much of a description of why the testbench does > >> not function correctly, but my guess is that you wanted to wait for > >> edges of the clock and not levels. Also it's unlikely that you > >> want to wait for a clock signal to be "less than or equal to 1" > >> even if you did want to check for a level. Probably something like > >> > >> wait until rising_edge (S_FPP_CLK_IN); > >> > >> -- > >> Gabor > > > > danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response > > Franck > > What do you see in your simulation? > > -- > > Rick hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving. library ieee; use ieee.std_logic_1164.all; entity testPrimToSecCase1 is end testPrimToSecCase1; architecture archPrimToSecTest of testPrimToSecCase1 is component Lane Port ( FPP_CLK_IN : IN std_logic; FPP_FROM_CORE : IN std_logic; -- (j) DATA_IN : IN std_logic; -- (K) FPP_SEC_EN : IN std_logic; -- (b) FPP_TURN_SEL : IN std_logic; -- (c) FPP_CORE_SEL : IN std_logic; -- (d) FPP_REGP_BYP : IN std_logic; -- (e) FPP_SOURCE_SEL : IN std_logic; -- (f) FPP_REGN_BYP : IN std_logic; -- (g) FPP_PRI_EN : IN std_logic; -- (h) Primary_Port : INOUT std_logic; -- (i) Secondary_Port : INOUT std_logic; -- (a) DATA_OUT : OUT std_logic; FPP_TO_CORE : OUT std_logic ); end component; ----------------------- INPUT ------------------ signal S_FPP_CLK_IN : std_logic; signal S_FPP_FROM_CORE : std_logic; -- (j) signal S_DATA_IN : std_logic; -- (K) signal S_FPP_SEC_EN : std_logic; -- (b) signal S_FPP_TURN_SEL : std_logic; -- (c) signal S_FPP_CORE_SEL : std_logic; -- (d) signal S_FPP_REGP_BYP : std_logic; -- (e) signal S_FPP_SOURCE_SEL : std_logic; -- (f) signal S_FPP_REGN_BYP : std_logic; -- (g) signal S_FPP_PRI_EN : std_logic; -- (h) -------------- InOutput ------------------------ signal S_Primary_Port : std_logic; -- (i) signal S_Secondary_Port : std_logic; -- (a) ----------------- OUTPUT ----------------------- signal S_FPP_TO_CORE_INT : std_logic; signal S_DATA_OUT : std_logic; -- (k) --FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE begin -- Komponent Instanzierung mit Verdrahtung U : Lane port map ( S_FPP_CLK_IN, S_FPP_FROM_CORE, -- j S_DATA_IN, -- k S_FPP_SEC_EN, -- b S_FPP_TURN_SEL, -- c S_FPP_CORE_SEL, -- d S_FPP_REGP_BYP, -- e S_FPP_SOURCE_SEL, -- f S_FPP_REGN_BYP, -- g S_FPP_PRI_EN, -- h S_Primary_Port, -- i S_Secondary_Port, -- a S_DATA_OUT, S_FPP_TO_CORE_INT ); processClock : process begin S_FPP_CLK_IN <= '0'; wait for 10 ns; S_FPP_CLK_IN <= '1'; wait for 10 ns; end process processClock; Stimuli : process begin S_FPP_FROM_CORE <= '0'; -- j S_DATA_IN <= '0'; -- k S_FPP_SEC_EN <= '0'; -- b S_FPP_TURN_SEL <= '0'; -- c S_FPP_CORE_SEL <= '0'; -- d S_FPP_REGP_BYP <= '0'; -- e S_FPP_SOURCE_SEL <= '0'; -- f S_FPP_REGN_BYP <= '0'; -- g S_FPP_PRI_EN <= '0'; -- h S_Primary_Port <= ''; -- i S_Secondary_Port <= '0'; -- a wait until S_FPP_CLK_IN <= '1'; S_FPP_FROM_CORE <= '-'; -- j S_DATA_IN <= '-'; -- k S_FPP_SEC_EN <= '1'; -- b S_FPP_TURN_SEL <= '-'; -- c S_FPP_CORE_SEL <= '1'; -- d S_FPP_REGP_BYP <= '0'; -- e S_FPP_SOURCE_SEL <= '0'; -- f S_FPP_REGN_BYP <= '0'; -- g S_FPP_PRI_EN <= '0'; -- h --wait until S_FPP_CLK_IN <= '1'; S_Primary_Port <= '0'; wait until S_FPP_CLK_IN <= '0'; S_Primary_Port <= '1'; wait until S_FPP_CLK_IN <= '1'; end process Stimuli; end archPrimToSecTest; From newsfish@newsfish Thu Aug 1 00:34:55 2024 X-Received: by 10.182.80.193 with SMTP id t1mr26693257obx.0.1444053243981; Mon, 05 Oct 2015 06:54:03 -0700 (PDT) X-Received: by 10.50.23.38 with SMTP id j6mr114173igf.15.1444053243946; Mon, 05 Oct 2015 06:54:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no15657040igb.0!news-out.google.com!n2ni21291igy.0!nntp.google.com!kq10no16985970igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Oct 2015 06:54:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.99.250.19; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 141.99.250.19 References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL From: fwetie@googlemail.com Injection-Date: Mon, 05 Oct 2015 13:54:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4048 Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: > On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: > > Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: > >> fwetie@googlemail.com wrote: > >>> hello, > >>> please i am looking for someone who can help me to solve my pb. > >>> this is my code : > >>> > >>> Bonjour a tous, > >>> je cherche de l'aide pour mon projet sur VHDL: > >>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > >>> voici mes codes: > >>> > >> > >> [snip] > >> > >>> Stimuli : process > >>> begin > >>> > >>> S_FPP_FROM_CORE <= '0'; > >>> S_DATA_IN <= '0'; > >>> S_FPP_SEC_EN <= '0'; > >>> S_FPP_TURN_SEL <= '0'; > >>> S_FPP_CORE_SEL <= '0'; > >>> S_FPP_REGP_BYP <= '0'; > >>> S_FPP_SOURCE_SEL <= '0'; > >>> S_FPP_REGN_BYP <= '0'; > >>> S_FPP_PRI_EN <= '0'; > >>> S_Primary_Port <= '0'; > >>> S_Secondary_Port <= '0'; > >>> > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_FPP_FROM_CORE <= '-'; > >>> S_DATA_IN <= '-'; > >>> S_FPP_SEC_EN <= '1'; > >>> S_FPP_TURN_SEL <= '-'; > >>> S_FPP_CORE_SEL <= '1'; > >>> S_FPP_REGP_BYP <= '0'; > >>> S_FPP_SOURCE_SEL <= '0'; > >>> S_FPP_REGN_BYP <= '0'; > >>> S_FPP_PRI_EN <= '0'; > >>> > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_Primary_Port <= '0'; > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_Secondary_Port <= '1'; > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> > >>> end process Stimuli; > >>> > >>> end archPrimToSecTest; > >>> i am looking for sombody to correct my testbench. > >>> thanks you for your help. > >>> Franck > >> > >> Well, you didn't give much of a description of why the testbench does > >> not function correctly, but my guess is that you wanted to wait for > >> edges of the clock and not levels. Also it's unlikely that you > >> want to wait for a clock signal to be "less than or equal to 1" > >> even if you did want to check for a level. Probably something like > >> > >> wait until rising_edge (S_FPP_CLK_IN); > >> > >> -- > >> Gabor > > > > danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response > > Franck > > What do you see in your simulation? > > -- > > Rick hello Rick how can i sent you the file. I try without success. From newsfish@newsfish Thu Aug 1 00:34:55 2024 X-Received: by 10.107.7.87 with SMTP id 84mr27775355ioh.9.1444053347155; Mon, 05 Oct 2015 06:55:47 -0700 (PDT) X-Received: by 10.50.143.4 with SMTP id sa4mr92179igb.15.1444053347118; Mon, 05 Oct 2015 06:55:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!kq10no15657599igb.0!news-out.google.com!z4ni11912ign.0!nntp.google.com!kq10no15657593igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Oct 2015 06:55:46 -0700 (PDT) In-Reply-To: <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.99.250.19; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 141.99.250.19 References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c41abda-8fca-4d69-9af8-a3376b3c3ceb@googlegroups.com> Subject: Re: VHDL From: fwetie@googlemail.com Injection-Date: Mon, 05 Oct 2015 13:55:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 228 Xref: news.eternal-september.org comp.lang.vhdl:4049 Am Montag, 5. Oktober 2015 15:34:21 UTC+2 schrieb fwe...@googlemail.com: > Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: > > On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: > > > Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: > > >> fwetie@googlemail.com wrote: > > >>> hello, > > >>> please i am looking for someone who can help me to solve my pb. > > >>> this is my code : > > >>> > > >>> Bonjour a tous, > > >>> je cherche de l'aide pour mon projet sur VHDL: > > >>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > > >>> voici mes codes: > > >>> > > >> > > >> [snip] > > >> > > >>> Stimuli : process > > >>> begin > > >>> > > >>> S_FPP_FROM_CORE <= '0'; > > >>> S_DATA_IN <= '0'; > > >>> S_FPP_SEC_EN <= '0'; > > >>> S_FPP_TURN_SEL <= '0'; > > >>> S_FPP_CORE_SEL <= '0'; > > >>> S_FPP_REGP_BYP <= '0'; > > >>> S_FPP_SOURCE_SEL <= '0'; > > >>> S_FPP_REGN_BYP <= '0'; > > >>> S_FPP_PRI_EN <= '0'; > > >>> S_Primary_Port <= '0'; > > >>> S_Secondary_Port <= '0'; > > >>> > > >>> wait until S_FPP_CLK_IN <= '1'; > > >>> > > >>> S_FPP_FROM_CORE <= '-'; > > >>> S_DATA_IN <= '-'; > > >>> S_FPP_SEC_EN <= '1'; > > >>> S_FPP_TURN_SEL <= '-'; > > >>> S_FPP_CORE_SEL <= '1'; > > >>> S_FPP_REGP_BYP <= '0'; > > >>> S_FPP_SOURCE_SEL <= '0'; > > >>> S_FPP_REGN_BYP <= '0'; > > >>> S_FPP_PRI_EN <= '0'; > > >>> > > >>> wait until S_FPP_CLK_IN <= '1'; > > >>> > > >>> S_Primary_Port <= '0'; > > >>> wait until S_FPP_CLK_IN <= '1'; > > >>> > > >>> S_Secondary_Port <= '1'; > > >>> wait until S_FPP_CLK_IN <= '1'; > > >>> > > >>> > > >>> end process Stimuli; > > >>> > > >>> end archPrimToSecTest; > > >>> i am looking for sombody to correct my testbench. > > >>> thanks you for your help. > > >>> Franck > > >> > > >> Well, you didn't give much of a description of why the testbench does > > >> not function correctly, but my guess is that you wanted to wait for > > >> edges of the clock and not levels. Also it's unlikely that you > > >> want to wait for a clock signal to be "less than or equal to 1" > > >> even if you did want to check for a level. Probably something like > > >> > > >> wait until rising_edge (S_FPP_CLK_IN); > > >> > > >> -- > > >> Gabor > > > > > > danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response > > > Franck > > > > What do you see in your simulation? > > > > -- > > > > Rick > hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving. > > library ieee; > use ieee.std_logic_1164.all; > > entity testPrimToSecCase1 is > end testPrimToSecCase1; > > architecture archPrimToSecTest of testPrimToSecCase1 is > > component Lane > Port ( > FPP_CLK_IN : IN std_logic; > > FPP_FROM_CORE : IN std_logic; -- (j) > > DATA_IN : IN std_logic; -- (K) > > FPP_SEC_EN : IN std_logic; -- (b) > > FPP_TURN_SEL : IN std_logic; -- (c) > > FPP_CORE_SEL : IN std_logic; -- (d) > > FPP_REGP_BYP : IN std_logic; -- (e) > > FPP_SOURCE_SEL : IN std_logic; -- (f) > > FPP_REGN_BYP : IN std_logic; -- (g) > > FPP_PRI_EN : IN std_logic; -- (h) > > Primary_Port : INOUT std_logic; -- (i) > > Secondary_Port : INOUT std_logic; -- (a) > > DATA_OUT : OUT std_logic; > > FPP_TO_CORE : OUT std_logic > ); > end component; > > ----------------------- INPUT ------------------ > signal S_FPP_CLK_IN : std_logic; > > signal S_FPP_FROM_CORE : std_logic; -- (j) > > signal S_DATA_IN : std_logic; -- (K) > > signal S_FPP_SEC_EN : std_logic; -- (b) > > signal S_FPP_TURN_SEL : std_logic; -- (c) > > signal S_FPP_CORE_SEL : std_logic; -- (d) > > signal S_FPP_REGP_BYP : std_logic; -- (e) > > signal S_FPP_SOURCE_SEL : std_logic; -- (f) > > signal S_FPP_REGN_BYP : std_logic; -- (g) > > signal S_FPP_PRI_EN : std_logic; -- (h) > > -------------- InOutput ------------------------ > signal S_Primary_Port : std_logic; -- (i) > > signal S_Secondary_Port : std_logic; -- (a) > > ----------------- OUTPUT ----------------------- > signal S_FPP_TO_CORE_INT : std_logic; > > signal S_DATA_OUT : std_logic; -- (k) > > --FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE > > begin > > -- Komponent Instanzierung mit Verdrahtung > > U : Lane > port map ( > S_FPP_CLK_IN, > > S_FPP_FROM_CORE, -- j > S_DATA_IN, -- k > S_FPP_SEC_EN, -- b > S_FPP_TURN_SEL, -- c > S_FPP_CORE_SEL, -- d > S_FPP_REGP_BYP, -- e > S_FPP_SOURCE_SEL, -- f > S_FPP_REGN_BYP, -- g > S_FPP_PRI_EN, -- h > S_Primary_Port, -- i > S_Secondary_Port, -- a > S_DATA_OUT, > S_FPP_TO_CORE_INT > ); > > > processClock : process > begin > > S_FPP_CLK_IN <= '0'; > wait for 10 ns; > S_FPP_CLK_IN <= '1'; > wait for 10 ns; > > end process processClock; > > Stimuli : process > begin > > S_FPP_FROM_CORE <= '0'; -- j > S_DATA_IN <= '0'; -- k > S_FPP_SEC_EN <= '0'; -- b > S_FPP_TURN_SEL <= '0'; -- c > S_FPP_CORE_SEL <= '0'; -- d > S_FPP_REGP_BYP <= '0'; -- e > S_FPP_SOURCE_SEL <= '0'; -- f > S_FPP_REGN_BYP <= '0'; -- g > S_FPP_PRI_EN <= '0'; -- h > S_Primary_Port <= ''; -- i > S_Secondary_Port <= '0'; -- a > > wait until S_FPP_CLK_IN <= '1'; > > S_FPP_FROM_CORE <= '-'; -- j > S_DATA_IN <= '-'; -- k > S_FPP_SEC_EN <= '1'; -- b > S_FPP_TURN_SEL <= '-'; -- c > S_FPP_CORE_SEL <= '1'; -- d > S_FPP_REGP_BYP <= '0'; -- e > S_FPP_SOURCE_SEL <= '0'; -- f > S_FPP_REGN_BYP <= '0'; -- g > S_FPP_PRI_EN <= '0'; -- h > > --wait until S_FPP_CLK_IN <= '1'; > > S_Primary_Port <= '0'; > wait until S_FPP_CLK_IN <= '0'; > > S_Primary_Port <= '1'; > wait until S_FPP_CLK_IN <= '1'; > > > end process Stimuli; > > end archPrimToSecTest; is there anyway to sent you the file? From newsfish@newsfish Thu Aug 1 00:34:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: VHDL Date: Mon, 05 Oct 2015 10:36:20 -0400 Organization: Alacron, Inc. Lines: 245 Message-ID: References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 5 Oct 2015 14:34:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="18979"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zymqJDoa9BhrMkgkkZoWFiLoMyX1kc0A=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> Cancel-Lock: sha1:A4q8iIzNZmLZa7NoOrme3V3I2bg= Xref: news.eternal-september.org comp.lang.vhdl:4050 fwetie@googlemail.com wrote: > Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: >> On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: >>> Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: >>>> fwetie@googlemail.com wrote: >>>>> hello, >>>>> please i am looking for someone who can help me to solve my pb. >>>>> this is my code : >>>>> >>>>> Bonjour a tous, >>>>> je cherche de l'aide pour mon projet sur VHDL: >>>>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. >>>>> voici mes codes: >>>>> >>>> [snip] >>>> >>>>> Stimuli : process >>>>> begin >>>>> >>>>> S_FPP_FROM_CORE <= '0'; >>>>> S_DATA_IN <= '0'; >>>>> S_FPP_SEC_EN <= '0'; >>>>> S_FPP_TURN_SEL <= '0'; >>>>> S_FPP_CORE_SEL <= '0'; >>>>> S_FPP_REGP_BYP <= '0'; >>>>> S_FPP_SOURCE_SEL <= '0'; >>>>> S_FPP_REGN_BYP <= '0'; >>>>> S_FPP_PRI_EN <= '0'; >>>>> S_Primary_Port <= '0'; >>>>> S_Secondary_Port <= '0'; >>>>> >>>>> wait until S_FPP_CLK_IN <= '1'; >>>>> >>>>> S_FPP_FROM_CORE <= '-'; >>>>> S_DATA_IN <= '-'; >>>>> S_FPP_SEC_EN <= '1'; >>>>> S_FPP_TURN_SEL <= '-'; >>>>> S_FPP_CORE_SEL <= '1'; >>>>> S_FPP_REGP_BYP <= '0'; >>>>> S_FPP_SOURCE_SEL <= '0'; >>>>> S_FPP_REGN_BYP <= '0'; >>>>> S_FPP_PRI_EN <= '0'; >>>>> >>>>> wait until S_FPP_CLK_IN <= '1'; >>>>> >>>>> S_Primary_Port <= '0'; >>>>> wait until S_FPP_CLK_IN <= '1'; >>>>> >>>>> S_Secondary_Port <= '1'; >>>>> wait until S_FPP_CLK_IN <= '1'; >>>>> >>>>> >>>>> end process Stimuli; >>>>> >>>>> end archPrimToSecTest; >>>>> i am looking for sombody to correct my testbench. >>>>> thanks you for your help. >>>>> Franck >>>> Well, you didn't give much of a description of why the testbench does >>>> not function correctly, but my guess is that you wanted to wait for >>>> edges of the clock and not levels. Also it's unlikely that you >>>> want to wait for a clock signal to be "less than or equal to 1" >>>> even if you did want to check for a level. Probably something like >>>> >>>> wait until rising_edge (S_FPP_CLK_IN); >>>> >>>> -- >>>> Gabor >>> danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response >>> Franck >> What do you see in your simulation? >> >> -- >> >> Rick > hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving. > > library ieee; > use ieee.std_logic_1164.all; > > entity testPrimToSecCase1 is > end testPrimToSecCase1; > > architecture archPrimToSecTest of testPrimToSecCase1 is > > component Lane > Port ( > FPP_CLK_IN : IN std_logic; > > FPP_FROM_CORE : IN std_logic; -- (j) > > DATA_IN : IN std_logic; -- (K) > > FPP_SEC_EN : IN std_logic; -- (b) > > FPP_TURN_SEL : IN std_logic; -- (c) > > FPP_CORE_SEL : IN std_logic; -- (d) > > FPP_REGP_BYP : IN std_logic; -- (e) > > FPP_SOURCE_SEL : IN std_logic; -- (f) > > FPP_REGN_BYP : IN std_logic; -- (g) > > FPP_PRI_EN : IN std_logic; -- (h) > > Primary_Port : INOUT std_logic; -- (i) > > Secondary_Port : INOUT std_logic; -- (a) > > DATA_OUT : OUT std_logic; > > FPP_TO_CORE : OUT std_logic > ); > end component; > > ----------------------- INPUT ------------------ > signal S_FPP_CLK_IN : std_logic; > > signal S_FPP_FROM_CORE : std_logic; -- (j) > > signal S_DATA_IN : std_logic; -- (K) > > signal S_FPP_SEC_EN : std_logic; -- (b) > > signal S_FPP_TURN_SEL : std_logic; -- (c) > > signal S_FPP_CORE_SEL : std_logic; -- (d) > > signal S_FPP_REGP_BYP : std_logic; -- (e) > > signal S_FPP_SOURCE_SEL : std_logic; -- (f) > > signal S_FPP_REGN_BYP : std_logic; -- (g) > > signal S_FPP_PRI_EN : std_logic; -- (h) > > -------------- InOutput ------------------------ > signal S_Primary_Port : std_logic; -- (i) > > signal S_Secondary_Port : std_logic; -- (a) > > ----------------- OUTPUT ----------------------- > signal S_FPP_TO_CORE_INT : std_logic; > > signal S_DATA_OUT : std_logic; -- (k) > > --FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE > > begin > > -- Komponent Instanzierung mit Verdrahtung > > U : Lane > port map ( > S_FPP_CLK_IN, > > S_FPP_FROM_CORE, -- j > S_DATA_IN, -- k > S_FPP_SEC_EN, -- b > S_FPP_TURN_SEL, -- c > S_FPP_CORE_SEL, -- d > S_FPP_REGP_BYP, -- e > S_FPP_SOURCE_SEL, -- f > S_FPP_REGN_BYP, -- g > S_FPP_PRI_EN, -- h > S_Primary_Port, -- i > S_Secondary_Port, -- a > S_DATA_OUT, > S_FPP_TO_CORE_INT > ); > > > processClock : process > begin > > S_FPP_CLK_IN <= '0'; > wait for 10 ns; > S_FPP_CLK_IN <= '1'; > wait for 10 ns; > > end process processClock; > > Stimuli : process > begin > > S_FPP_FROM_CORE <= '0'; -- j > S_DATA_IN <= '0'; -- k > S_FPP_SEC_EN <= '0'; -- b > S_FPP_TURN_SEL <= '0'; -- c > S_FPP_CORE_SEL <= '0'; -- d > S_FPP_REGP_BYP <= '0'; -- e > S_FPP_SOURCE_SEL <= '0'; -- f > S_FPP_REGN_BYP <= '0'; -- g > S_FPP_PRI_EN <= '0'; -- h > S_Primary_Port <= ''; -- i > S_Secondary_Port <= '0'; -- a > > wait until S_FPP_CLK_IN <= '1'; > > S_FPP_FROM_CORE <= '-'; -- j > S_DATA_IN <= '-'; -- k > S_FPP_SEC_EN <= '1'; -- b > S_FPP_TURN_SEL <= '-'; -- c > S_FPP_CORE_SEL <= '1'; -- d > S_FPP_REGP_BYP <= '0'; -- e > S_FPP_SOURCE_SEL <= '0'; -- f > S_FPP_REGN_BYP <= '0'; -- g > S_FPP_PRI_EN <= '0'; -- h > > --wait until S_FPP_CLK_IN <= '1'; > > S_Primary_Port <= '0'; > wait until S_FPP_CLK_IN <= '0'; > > S_Primary_Port <= '1'; > wait until S_FPP_CLK_IN <= '1'; > > > end process Stimuli; > > end archPrimToSecTest; You still have a problematic wait in your "Stimuli" process: wait until S_FPP_CLK_IN <= '1'; This literaly means "wait until S_FPP_CLK_IN is less than or equal to 1" and since the clock will only have values 0 or 1, it will always be true. Therefore the wait does not actually delay the next set of assignments until the clock is high, rather it happens immediately at time zero. Furthermore this sort of wait is problematic when you are trying to stimulate a clocked process and want to ensure that the stimulus happens a "delta" delay after the rising clock edge. You should really wait for an event. either: wait until S_FPP_CLK_IN'event and S_FPP_CLK_IN = '1'; or: wait until rising_edge (S_FPP_CLK_IN); -- Gabor From newsfish@newsfish Thu Aug 1 00:34:56 2024 X-Received: by 10.50.43.233 with SMTP id z9mr3074591igl.9.1444250670783; Wed, 07 Oct 2015 13:44:30 -0700 (PDT) X-Received: by 10.50.20.73 with SMTP id l9mr82144ige.2.1444250670719; Wed, 07 Oct 2015 13:44:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!kq10no18145261igb.0!news-out.google.com!n2ni23521igy.0!nntp.google.com!kq10no16459166igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 7 Oct 2015 13:44:29 -0700 (PDT) In-Reply-To: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=179.215.205.247; posting-account=HmYrCQoAAACjE_F53xA8_mML1hYdaSqp NNTP-Posting-Host: 179.215.205.247 References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Exponential code in VHDL From: maurolarrat@gmail.com Injection-Date: Wed, 07 Oct 2015 20:44:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4051 Em quarta-feira, 27 de julho de 2011 06:19:26 UTC-3, Zaid Al-Hilli escreveu: > Hi all, > > I am about implementing a VHDL code but I am facing problem, I have an > exponential operation and I want to run that code op an FPGA board!! > > Generally speaking the assignment is: X = (1 / (1+ exp((y + 87.8) / > 8.5))); > > Would you please help me in that? > > Many thanks in advance... > > Zaid Use Elliott function, also known as fast sigmoid function. It will solve your problem. From newsfish@newsfish Thu Aug 1 00:34:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Date: Wed, 7 Oct 2015 17:01:30 -0400 Organization: A noiseless patient Spider Lines: 239 Message-ID: References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> <1c41abda-8fca-4d69-9af8-a3376b3c3ceb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 7 Oct 2015 20:59:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="7b80060806273f26e05ba36fc8912472"; logging-data="25273"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+LHfHJzCzcdiy7NZz9fql7" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <1c41abda-8fca-4d69-9af8-a3376b3c3ceb@googlegroups.com> Cancel-Lock: sha1:1H2Bd1fT1uel2Y7Mxc/fEjdY/4w= Xref: news.eternal-september.org comp.lang.vhdl:4052 On 10/5/2015 9:55 AM, fwetie@googlemail.com wrote: > Am Montag, 5. Oktober 2015 15:34:21 UTC+2 schrieb fwe...@googlemail.com: >> Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: >>> On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: >>>> Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: >>>>> fwetie@googlemail.com wrote: >>>>>> hello, >>>>>> please i am looking for someone who can help me to solve my pb. >>>>>> this is my code : >>>>>> >>>>>> Bonjour a tous, >>>>>> je cherche de l'aide pour mon projet sur VHDL: >>>>>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. >>>>>> voici mes codes: >>>>>> >>>>> >>>>> [snip] >>>>> >>>>>> Stimuli : process >>>>>> begin >>>>>> >>>>>> S_FPP_FROM_CORE <= '0'; >>>>>> S_DATA_IN <= '0'; >>>>>> S_FPP_SEC_EN <= '0'; >>>>>> S_FPP_TURN_SEL <= '0'; >>>>>> S_FPP_CORE_SEL <= '0'; >>>>>> S_FPP_REGP_BYP <= '0'; >>>>>> S_FPP_SOURCE_SEL <= '0'; >>>>>> S_FPP_REGN_BYP <= '0'; >>>>>> S_FPP_PRI_EN <= '0'; >>>>>> S_Primary_Port <= '0'; >>>>>> S_Secondary_Port <= '0'; >>>>>> >>>>>> wait until S_FPP_CLK_IN <= '1'; >>>>>> >>>>>> S_FPP_FROM_CORE <= '-'; >>>>>> S_DATA_IN <= '-'; >>>>>> S_FPP_SEC_EN <= '1'; >>>>>> S_FPP_TURN_SEL <= '-'; >>>>>> S_FPP_CORE_SEL <= '1'; >>>>>> S_FPP_REGP_BYP <= '0'; >>>>>> S_FPP_SOURCE_SEL <= '0'; >>>>>> S_FPP_REGN_BYP <= '0'; >>>>>> S_FPP_PRI_EN <= '0'; >>>>>> >>>>>> wait until S_FPP_CLK_IN <= '1'; >>>>>> >>>>>> S_Primary_Port <= '0'; >>>>>> wait until S_FPP_CLK_IN <= '1'; >>>>>> >>>>>> S_Secondary_Port <= '1'; >>>>>> wait until S_FPP_CLK_IN <= '1'; >>>>>> >>>>>> >>>>>> end process Stimuli; >>>>>> >>>>>> end archPrimToSecTest; >>>>>> i am looking for sombody to correct my testbench. >>>>>> thanks you for your help. >>>>>> Franck >>>>> >>>>> Well, you didn't give much of a description of why the testbench does >>>>> not function correctly, but my guess is that you wanted to wait for >>>>> edges of the clock and not levels. Also it's unlikely that you >>>>> want to wait for a clock signal to be "less than or equal to 1" >>>>> even if you did want to check for a level. Probably something like >>>>> >>>>> wait until rising_edge (S_FPP_CLK_IN); >>>>> >>>>> -- >>>>> Gabor >>>> >>>> danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response >>>> Franck >>> >>> What do you see in your simulation? >>> >>> -- >>> >>> Rick >> hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving. >> >> library ieee; >> use ieee.std_logic_1164.all; >> >> entity testPrimToSecCase1 is >> end testPrimToSecCase1; >> >> architecture archPrimToSecTest of testPrimToSecCase1 is >> >> component Lane >> Port ( >> FPP_CLK_IN : IN std_logic; >> >> FPP_FROM_CORE : IN std_logic; -- (j) >> >> DATA_IN : IN std_logic; -- (K) >> >> FPP_SEC_EN : IN std_logic; -- (b) >> >> FPP_TURN_SEL : IN std_logic; -- (c) >> >> FPP_CORE_SEL : IN std_logic; -- (d) >> >> FPP_REGP_BYP : IN std_logic; -- (e) >> >> FPP_SOURCE_SEL : IN std_logic; -- (f) >> >> FPP_REGN_BYP : IN std_logic; -- (g) >> >> FPP_PRI_EN : IN std_logic; -- (h) >> >> Primary_Port : INOUT std_logic; -- (i) >> >> Secondary_Port : INOUT std_logic; -- (a) >> >> DATA_OUT : OUT std_logic; >> >> FPP_TO_CORE : OUT std_logic >> ); >> end component; >> >> ----------------------- INPUT ------------------ >> signal S_FPP_CLK_IN : std_logic; >> >> signal S_FPP_FROM_CORE : std_logic; -- (j) >> >> signal S_DATA_IN : std_logic; -- (K) >> >> signal S_FPP_SEC_EN : std_logic; -- (b) >> >> signal S_FPP_TURN_SEL : std_logic; -- (c) >> >> signal S_FPP_CORE_SEL : std_logic; -- (d) >> >> signal S_FPP_REGP_BYP : std_logic; -- (e) >> >> signal S_FPP_SOURCE_SEL : std_logic; -- (f) >> >> signal S_FPP_REGN_BYP : std_logic; -- (g) >> >> signal S_FPP_PRI_EN : std_logic; -- (h) >> >> -------------- InOutput ------------------------ >> signal S_Primary_Port : std_logic; -- (i) >> >> signal S_Secondary_Port : std_logic; -- (a) >> >> ----------------- OUTPUT ----------------------- >> signal S_FPP_TO_CORE_INT : std_logic; >> >> signal S_DATA_OUT : std_logic; -- (k) >> >> --FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE >> >> begin >> >> -- Komponent Instanzierung mit Verdrahtung >> >> U : Lane >> port map ( >> S_FPP_CLK_IN, >> >> S_FPP_FROM_CORE, -- j >> S_DATA_IN, -- k >> S_FPP_SEC_EN, -- b >> S_FPP_TURN_SEL, -- c >> S_FPP_CORE_SEL, -- d >> S_FPP_REGP_BYP, -- e >> S_FPP_SOURCE_SEL, -- f >> S_FPP_REGN_BYP, -- g >> S_FPP_PRI_EN, -- h >> S_Primary_Port, -- i >> S_Secondary_Port, -- a >> S_DATA_OUT, >> S_FPP_TO_CORE_INT >> ); >> >> >> processClock : process >> begin >> >> S_FPP_CLK_IN <= '0'; >> wait for 10 ns; >> S_FPP_CLK_IN <= '1'; >> wait for 10 ns; >> >> end process processClock; >> >> Stimuli : process >> begin >> >> S_FPP_FROM_CORE <= '0'; -- j >> S_DATA_IN <= '0'; -- k >> S_FPP_SEC_EN <= '0'; -- b >> S_FPP_TURN_SEL <= '0'; -- c >> S_FPP_CORE_SEL <= '0'; -- d >> S_FPP_REGP_BYP <= '0'; -- e >> S_FPP_SOURCE_SEL <= '0'; -- f >> S_FPP_REGN_BYP <= '0'; -- g >> S_FPP_PRI_EN <= '0'; -- h >> S_Primary_Port <= ''; -- i >> S_Secondary_Port <= '0'; -- a >> >> wait until S_FPP_CLK_IN <= '1'; >> >> S_FPP_FROM_CORE <= '-'; -- j >> S_DATA_IN <= '-'; -- k >> S_FPP_SEC_EN <= '1'; -- b >> S_FPP_TURN_SEL <= '-'; -- c >> S_FPP_CORE_SEL <= '1'; -- d >> S_FPP_REGP_BYP <= '0'; -- e >> S_FPP_SOURCE_SEL <= '0'; -- f >> S_FPP_REGN_BYP <= '0'; -- g >> S_FPP_PRI_EN <= '0'; -- h >> >> --wait until S_FPP_CLK_IN <= '1'; >> >> S_Primary_Port <= '0'; >> wait until S_FPP_CLK_IN <= '0'; >> >> S_Primary_Port <= '1'; >> wait until S_FPP_CLK_IN <= '1'; >> >> >> end process Stimuli; >> >> end archPrimToSecTest; > > is there anyway to sent you the file? I don't want you to send me the file so I can debug your code. I want you to look at the simulation results and understand what you see. I will help you understand if you tell me what you don't understand or ask questions. -- Rick From newsfish@newsfish Thu Aug 1 00:34:57 2024 X-Received: by 10.66.249.100 with SMTP id yt4mr8188038pac.42.1444342935034; Thu, 08 Oct 2015 15:22:15 -0700 (PDT) X-Received: by 10.50.77.70 with SMTP id q6mr94814igw.4.1444342934991; Thu, 08 Oct 2015 15:22:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!kq10no18655451igb.0!news-out.google.com!z4ni15254ign.0!nntp.google.com!kq10no16811441igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 8 Oct 2015 15:22:14 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5abf3445-1212-4ec5-991c-645d31e4507b@googlegroups.com> Subject: Re: Exponential code in VHDL From: michael6866 Injection-Date: Thu, 08 Oct 2015 22:22:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4053 On Wednesday, October 7, 2015 at 4:44:34 PM UTC-4, mauro...@gmail.com wrote: > Em quarta-feira, 27 de julho de 2011 06:19:26 UTC-3, Zaid Al-Hilli escreveu: > > Hi all, > > > > I am about implementing a VHDL code but I am facing problem, I have an > > exponential operation and I want to run that code op an FPGA board!! > > > > Generally speaking the assignment is: X = (1 / (1+ exp((y + 87.8) / > > 8.5))); > > > > Would you please help me in that? > > > > Many thanks in advance... > > > > Zaid > > Use Elliott function, also known as fast sigmoid function. It will solve your problem. Why do you want to bring an ancient thread up... From newsfish@newsfish Thu Aug 1 00:34:57 2024 X-Received: by 10.140.150.206 with SMTP id 197mr25388065qhw.0.1444675760038; Mon, 12 Oct 2015 11:49:20 -0700 (PDT) X-Received: by 10.50.78.225 with SMTP id e1mr156835igx.0.1444675759963; Mon, 12 Oct 2015 11:49:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z77no9202216qge.1!news-out.google.com!z4ni19067ign.0!nntp.google.com!kq10no20421473igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Oct 2015 11:49:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=75.78.166.8; posting-account=1MLwSAoAAACZMvKd3RIo1qYTMmqjCBWr NNTP-Posting-Host: 75.78.166.8 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c3d4880-38e6-41e4-9250-f8cfc78465ba@googlegroups.com> Subject: Xilinx XC4VLX40-10FFG1148C - Available New From: mvarman@gmail.com Injection-Date: Mon, 12 Oct 2015 18:49:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 10 Xref: news.eternal-september.org comp.lang.vhdl:4054 I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. The ICs are in original sealed envelope (not opened). Reference: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1491-ND Please let me know whether anyone will by interested to buy this from me. Thanks Mahendra Varman From newsfish@newsfish Thu Aug 1 00:34:57 2024 X-Received: by 10.129.154.137 with SMTP id r131mr30680645ywg.0.1444769791217; Tue, 13 Oct 2015 13:56:31 -0700 (PDT) X-Received: by 10.50.164.201 with SMTP id ys9mr23724igb.13.1444769791140; Tue, 13 Oct 2015 13:56:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z77no9437512qge.1!news-out.google.com!n2ni29327igy.0!nntp.google.com!kq10no20931082igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Oct 2015 13:56:30 -0700 (PDT) In-Reply-To: <8c3d4880-38e6-41e4-9250-f8cfc78465ba@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.198.93.234; posting-account=siWI1goAAADCu904SmsHiBYIWw1g2Ocr NNTP-Posting-Host: 117.198.93.234 References: <8c3d4880-38e6-41e4-9250-f8cfc78465ba@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <86a7d6d1-77a9-494d-9148-7859493680ea@googlegroups.com> Subject: Re: Xilinx XC4VLX40-10FFG1148C - Available New From: iamalien Injection-Date: Tue, 13 Oct 2015 20:56:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1605 X-Received-Body-CRC: 2210225640 Xref: news.eternal-september.org comp.lang.vhdl:4055 On Tuesday, October 13, 2015 at 12:19:25 AM UTC+5:30, mva...@gmail.com wrote: > I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. > The ICs are in original sealed envelope (not opened). > > Reference: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1491-ND > > Please let me know whether anyone will by interested to buy this from > me. > > Thanks > > Mahendra Varman only ICs or is there a development board too? From newsfish@newsfish Thu Aug 1 00:34:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 16 Oct 2015 04:36:49 -0500 From: aadi Subject: creating program Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: fc54be3c-b935-4e6a-a6c9-a610175bed0c Message-ID: Date: Fri, 16 Oct 2015 04:36:49 -0500 Lines: 5 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-fcvZcbQlrEg+Vd3HjgJ4w1TIiMsmdr9NzmTytQJV0XPTPA7oYZIAl3TnQS96Mtfh+OS7Xe4827Ss7Ok!cuTHLAWvVjb0cAOSXGCZQgCVhNb89l4gY52yClU/3jO84PqtxR3/+SsXQohL0uBnnnZE15R4TVrz!Z8Q= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1121 Xref: news.eternal-september.org comp.lang.vhdl:4056 i have learned every aspect of VHDL but i still can't exersise it to make complex program. i need a code for data encryption standard and also for key generation. but i can't get a single way to do so plzz help me From newsfish@newsfish Thu Aug 1 00:34:58 2024 X-Received: by 10.182.241.10 with SMTP id we10mr12719883obc.24.1444991828353; Fri, 16 Oct 2015 03:37:08 -0700 (PDT) X-Received: by 10.50.43.195 with SMTP id y3mr82612igl.1.1444991828330; Fri, 16 Oct 2015 03:37:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no22048410igb.0!news-out.google.com!z4ni22683ign.0!nntp.google.com!kq10no19028746igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 03:37:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:d9fa:c1c2:945e:ca59; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:d9fa:c1c2:945e:ca59 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: KJ Injection-Date: Fri, 16 Oct 2015 10:37:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4057 On Friday, October 16, 2015 at 5:36:53 AM UTC-4, aadi wrote: > i have learned every aspect of VHDL but i still can't exersise it to make complex program. > i need a code for data encryption standard and also for key generation. but i can't get a single way to do so > plzz help me Stating what you say you 'need' and not showing what you've 'done' doesn't typically motivate anybody to help. Some suggestions: - Post some code for people to review and comment - Pay somebody to write the code for you - English may not be your first language, but 'plzz' is not even close to 'please'...it's closer to 'pizza'. Showing some bit of professionalism is often useful Kevin From newsfish@newsfish Thu Aug 1 00:34:58 2024 X-Received: by 10.182.126.228 with SMTP id nb4mr12072676obb.19.1444995261463; Fri, 16 Oct 2015 04:34:21 -0700 (PDT) X-Received: by 10.50.115.70 with SMTP id jm6mr87130igb.5.1444995261440; Fri, 16 Oct 2015 04:34:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no19046399igb.0!news-out.google.com!z4ni22710ign.0!nntp.google.com!kq10no22071114igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 04:34:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Thomas Stanka Injection-Date: Fri, 16 Oct 2015 11:34:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4058 Am Freitag, 16. Oktober 2015 11:36:53 UTC+2 schrieb aadi: > i have learned every aspect of VHDL but i still can't exersise it to make complex program. > i need a code for data encryption standard and also for key generation. but i can't get a single way to do so > plzz help me In general, it is agreed that writing a "Program" requires you to have Software and Compiler that generates a Program out of your Software. VHDL is mainly a hardware description language, I know no Compiler allowing you to generate a executeable out of VHDL, instead you will find several Simulators, that allow you to simulate the Code you wrote. If you have learned every aspect of VHDL this is nothing new for you, so your problem should be with the data encryption, not with HDL descripton itself, so you might ask in a group dealing with encyption standard. A VHDL code for DES can easily take some man-month work force. If you need easy way register by open cores and download the DES core from there. In this group you should provide specific questions in order to receive specific answers. regards Thomas From newsfish@newsfish Thu Aug 1 00:34:59 2024 X-Received: by 10.66.160.135 with SMTP id xk7mr14311386pab.28.1445022331638; Fri, 16 Oct 2015 12:05:31 -0700 (PDT) X-Received: by 10.50.13.38 with SMTP id e6mr161996igc.5.1445022331591; Fri, 16 Oct 2015 12:05:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no22234302igb.0!news-out.google.com!n2ni32143igy.0!nntp.google.com!kq10no22234291igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 12:05:30 -0700 (PDT) In-Reply-To: <86a7d6d1-77a9-494d-9148-7859493680ea@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=75.78.166.8; posting-account=1MLwSAoAAACZMvKd3RIo1qYTMmqjCBWr NNTP-Posting-Host: 75.78.166.8 References: <8c3d4880-38e6-41e4-9250-f8cfc78465ba@googlegroups.com> <86a7d6d1-77a9-494d-9148-7859493680ea@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Xilinx XC4VLX40-10FFG1148C - Available New From: mvarman@gmail.com Injection-Date: Fri, 16 Oct 2015 19:05:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4059 On Tuesday, October 13, 2015 at 3:56:37 PM UTC-5, iamalien wrote: > On Tuesday, October 13, 2015 at 12:19:25 AM UTC+5:30, mva...@gmail.com wrote: > > I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. > > The ICs are in original sealed envelope (not opened). > > > > Reference: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1491-ND > > > > Please let me know whether anyone will by interested to buy this from > > me. > > > > Thanks > > > > Mahendra Varman > > only ICs or is there a development board too? Only ICs From newsfish@newsfish Thu Aug 1 00:34:59 2024 X-Received: by 10.68.165.5 with SMTP id yu5mr14211419pbb.1.1445023906236; Fri, 16 Oct 2015 12:31:46 -0700 (PDT) X-Received: by 10.50.131.164 with SMTP id on4mr166224igb.8.1445023906193; Fri, 16 Oct 2015 12:31:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no22244404igb.0!news-out.google.com!z4ni23052ign.0!nntp.google.com!kq10no19162949igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 12:31:45 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Subject: Strange 'X' values. From: Ilya Kalistru Injection-Date: Fri, 16 Oct 2015 19:31:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4060 Good day. I came across a strange behavior in my project and can't understand it. May= be you could explain it to me. I've reduced it to the point where it still persists. I've tried to ask on the xilinx forum but it looks like that that forum more engaged to help me avoid that proble= m then explain what is going on here... Here is the code entity test is Port ( Clock : in std_logic; Dev_Linked : in std_logic_vector(0 downto 0); R_CHCS : out std_logic_vector(1 downto 0):=3D"01" ); end entity test; architecture Behavioral of test is begin R_CHCS_proc : process (Clock) is begin if rising_edge(Clock) then for i in 0 to 0 loop R_CHCS(i * 2) <=3D '0'; end loop; end if; end process R_CHCS_proc; R_CHCS(1) <=3D Dev_Linked(0) when rising_edge(Clock); end Behavioral; On the first clock cycle R_CHCS becomes "X0". And I don't know why. On Xili= nx forum say that "Questa also gives the same output" and it's not a bug of= the simulator and it's because each process makes it's own driver for CHC= S and it gives 'X' value. But it doesn't make sense for me because if I rem= ove unnecessary loop in R_CHCS_proc this problem disappears, and it is noth= ing to do with processes. Maybe someone could explain this to me? From newsfish@newsfish Thu Aug 1 00:35:00 2024 X-Received: by 10.13.202.13 with SMTP id m13mr5780994ywd.57.1445032856084; Fri, 16 Oct 2015 15:00:56 -0700 (PDT) X-Received: by 10.50.131.164 with SMTP id on4mr183533igb.8.1445032856055; Fri, 16 Oct 2015 15:00:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!5no1600162qgg.0!news-out.google.com!z4ni23141ign.0!nntp.google.com!kq10no22295737igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 15:00:55 -0700 (PDT) In-Reply-To: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.76.131; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.76.131 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46d2e97c-2e25-4d12-b4ff-d8a98cb91457@googlegroups.com> Subject: Re: Strange 'X' values. From: Jim Lewis Injection-Date: Fri, 16 Oct 2015 22:00:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4061 >From www.eda.org/comp.lang.vhdl/FAQ1.html: 4.2.13 Signal Drivers ... Further, VHDL needs to be able to statically (that is, during static elabo= ration) determine all drivers of a signal, in order to create a static netw= ork topology. A driver is created for the longest static prefix of each tar= get signal. During elaboration the compiler analyzes the target of each sig= nal assignment statement to determine the smallest portion of the signal th= at can be statically determined as being driven by the concurrent statement= . For example, the following model is erroneous, as both the process "p" an= d the concurrent signal assignment both drive "sig(3)", an unresolved signa= l. architecture behave of test is signal sig : bit_vector(0 TO 7); constant c : integer :=3D 3; begin p: process (sig) begin for i in 1 to 1 loop sig(i) <=3D '1'; -- signal assignment statement end loop; end process; sig(c) <=3D '1'; -- concurrent signal assignment driving -- "sig(3)" end behave;=20 In this example, the longest static prefix of the target of the assignment = statement "sig(i) <=3D '1'" is the entire signal "sig", since "sig" is a st= atic signal name and "i" is a loop constant and hence not static. Consequen= tly, "p" has a driver for the entire signal "sig", although actuality only = "sig(1)" will be driven by the process. Further, the longest static prefix = of the concurrent signal assignment is "sig(3)", since "c" is a statically = elaborated constant equal to 3. Hence, an error message should be generated= to the effect that several processes are driving "sig(3)". From newsfish@newsfish Thu Aug 1 00:35:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Fri, 16 Oct 2015 20:19:57 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Oct 2015 00:17:54 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="31484"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Jy7fRLJ/n6eNXqECLZI1G" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Cancel-Lock: sha1:wdz8U4SjYyfGbjqk/DqngPxgdCQ= Xref: news.eternal-september.org comp.lang.vhdl:4062 On 10/16/2015 3:31 PM, Ilya Kalistru wrote: > Good day. > I came across a strange behavior in my project and can't understand it. Maybe you could explain it to me. > I've reduced it to the point where it still persists. > I've tried to ask on the xilinx forum > but it looks like that that forum more engaged to help me avoid that problem then explain what is going on here... > Here is the code > > entity test is > Port ( > Clock : in std_logic; > Dev_Linked : in std_logic_vector(0 downto 0); > R_CHCS : out std_logic_vector(1 downto 0):="01" > ); > end entity test; > > architecture Behavioral of test is > begin > > R_CHCS_proc : process (Clock) is > begin > if rising_edge(Clock) then > for i in 0 to 0 loop > R_CHCS(i * 2) <= '0'; > end loop; > end if; > end process R_CHCS_proc; > > R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); > > end Behavioral; > > On the first clock cycle R_CHCS becomes "X0". And I don't know why. On Xilinx forum say that "Questa also gives the same output" and it's not a bug of the simulator and it's because each process makes it's own driver for CHCS and it gives 'X' value. But it doesn't make sense for me because if I remove unnecessary loop in R_CHCS_proc this problem disappears, and it is nothing to do with processes. > > Maybe someone could explain this to me? I think Jim gave you an explanation even if it is a bit hard to understand. VHDL has a lot of things like that. The basic rule is "don't do that". I can't say I see any reason why you would want to do that. Why not just include the assignment to bit 1 of R_CHCS in the same clocked process as the other assignment to R_CHCS? Rick -- Rick From newsfish@newsfish Thu Aug 1 00:35:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Sat, 17 Oct 2015 00:27:27 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 20 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4063 aadi wrote: > i have learned every aspect of VHDL but i still can't exersise it > to make complex program. I started VHDL, and though I have never written a 'program' in it, I have designed some fairly complicated logic that actually works. I won't claim to undestand even half of VHDL, as they are adding to it faster than I can learn, and faster than the systems I use it with can keep up. (I had some years of verilog before, but only learned a small fraction of VHDL before I knew enough to start writing it.) > i need a code for data encryption standard and also for key generation. > but i can't get a single way to do so Do remember that VHDL is not a software programming language. -- glen From newsfish@newsfish Thu Aug 1 00:35:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Sat, 17 Oct 2015 00:35:57 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 45 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4064 rickman wrote: > On 10/16/2015 3:31 PM, Ilya Kalistru wrote: >> I came across a strange behavior in my project and can't understand it. >> Maybe you could explain it to me. (snip) >> R_CHCS_proc : process (Clock) is >> begin >> if rising_edge(Clock) then >> for i in 0 to 0 loop >> R_CHCS(i * 2) <= '0'; >> end loop; >> end if; >> end process R_CHCS_proc; >> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); (snip) >> On the first clock cycle R_CHCS becomes "X0". (snip) > I think Jim gave you an explanation even if it is a bit hard to > understand. VHDL has a lot of things like that. The basic rule is > "don't do that". I can't say I see any reason why you would want to do > that. Why not just include the assignment to bit 1 of R_CHCS in the > same clocked process as the other assignment to R_CHCS? Yes. For each signal, use either the process form or the non-process (verilog calls it continuous assignment) form, but don't mix them. In verilog, you have to declare reg or wire, so you have to decide early which way you want to go. VHDL doesn't have that, but you still have to get it right. It might work if you put the second one in its own process, but it has to be in one. Also, I didn't know that you could use rising_edge(clock) outside of process, but then again, I never even thought to try it. -- glen From newsfish@newsfish Thu Aug 1 00:35:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Fri, 16 Oct 2015 21:17:36 -0400 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Oct 2015 01:15:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="7641"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+P1LaHvFBz8REl566TUSno" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:TT6hBMbNWB4dRgXqzcjMpUOJshw= Xref: news.eternal-september.org comp.lang.vhdl:4065 On 10/16/2015 8:35 PM, glen herrmannsfeldt wrote: > rickman wrote: >> On 10/16/2015 3:31 PM, Ilya Kalistru wrote: >>> I came across a strange behavior in my project and can't understand it. >>> Maybe you could explain it to me. > > (snip) > >>> R_CHCS_proc : process (Clock) is >>> begin >>> if rising_edge(Clock) then >>> for i in 0 to 0 loop >>> R_CHCS(i * 2) <= '0'; >>> end loop; >>> end if; >>> end process R_CHCS_proc; > >>> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); > > (snip) > >>> On the first clock cycle R_CHCS becomes "X0". > > (snip) > >> I think Jim gave you an explanation even if it is a bit hard to >> understand. VHDL has a lot of things like that. The basic rule is >> "don't do that". I can't say I see any reason why you would want to do >> that. Why not just include the assignment to bit 1 of R_CHCS in the >> same clocked process as the other assignment to R_CHCS? > > Yes. For each signal, use either the process form or the non-process > (verilog calls it continuous assignment) form, but don't mix them. > > In verilog, you have to declare reg or wire, so you have to decide early > which way you want to go. VHDL doesn't have that, but you still have to > get it right. > > It might work if you put the second one in its own process, but it has > to be in one. > > Also, I didn't know that you could use rising_edge(clock) outside > of process, but then again, I never even thought to try it. I've seen this discussed, making a clocked process from a concurrent statement. But I've never tried it myself. I want to say I've read that it will work, but perhaps not in all tools. There is a synthesis VHDL spec if I am not mistaken and I bet this isn't in it. -- Rick From newsfish@newsfish Thu Aug 1 00:35:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Why VHDL? Date: Fri, 16 Oct 2015 21:24:16 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Oct 2015 01:22:14 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="8713"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+oJpup/uyTGPpjaghoEvgH" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:mC2PGhaEyQQqV+Y9SY75LypuTBc= Xref: news.eternal-september.org comp.lang.vhdl:4066 comp.lang.verilog:1209 I'm not looking to start a VHDL vs. Verilog argument, but I was puzzled by Glen's comment in the VHDL group that he learned Verilog first before using VHDL. Am I correct in assuming you used VHDL because a customer required it? I learned VHDL, although not well, then went to work for a comms company who used Verilog. I never went to school for Verilog and never really bought a book. So I don't feel comfortable using it even though I have coded in it. On the other hand, after many years of VHDL, I won't say I've ever gotten "comfortable" with it. I've just learned to live with it. Part of the reason I haven't switched to Verilog is that I've never found a good book for it. In fact when I have asked in the Verilog group I'm told there *isn't* one. Buy "good" I mean one that covers all the pitfalls well. At least with VHDL it tells you you've screwed up. I'm curious who here has learned both and why? Which do you prefer and why? -- Rick From newsfish@newsfish Thu Aug 1 00:35:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Sat, 17 Oct 2015 07:21:33 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 58 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4067 comp.lang.verilog:1210 In comp.lang.vhdl rickman wrote: > I'm not looking to start a VHDL vs. Verilog argument, but I was puzzled > by Glen's comment in the VHDL group that he learned Verilog first before > using VHDL. Am I correct in assuming you used VHDL because a customer > required it? That is about right. > I learned VHDL, although not well, then went to work for a comms company > who used Verilog. I never went to school for Verilog and never really > bought a book. So I don't feel comfortable using it even though I have > coded in it. I started about 1993. I was told that C programmers usually like verilog, others I worked with were using it, so I did to. I bought both Thomas and Moorby's book, and the Sternhiem, Singh, Madhavan, and Trivedi book. There might not have been many books back then. Those two, and some Xilinx software to run designs through, and I started writing down logic designs pretty soon. I also did some simulations with Veriwell. Not so many years ago, I was working with an existing design that was done using a mix of schematic capture, VHDL, and AHDL (that is, Altera), and wrote mine in verilog. I had to be able to read the VHDL, but didn't need to write it. > On the other hand, after many years of VHDL, I won't say > I've ever gotten "comfortable" with it. I've just learned to live with > it. Part of the reason I haven't switched to Verilog is that I've never > found a good book for it. In fact when I have asked in the Verilog > group I'm told there *isn't* one. Buy "good" I mean one that covers all > the pitfalls well. At least with VHDL it tells you you've screwed up. Many useful verilog features are new to VHDL, some too new for the version of tools that I use. Even more, they are different for different FPGA chips with the same version of tools. (Specifically, Spartan 3 vs. Spartan 6.) Strange. > I'm curious who here has learned both and why? Which do you prefer and > why? Most verilog operators are similar to C operators, so that helps some. A few times, not so many, I have used & in VHDL when I meant AND. I still prefer verilog, but I figured out how to write most of the things I need from verilog into VHDL. Verilog style concatenations are still too new to VHDL. The result is a fair number of signals that are only needed to combine or separate signals to/from a vector. VHDL is a little wordier than I like, but it isn't so hard to live with. I will like it better when VHDL 2008 is supported, where I rarely complained about the features in verilog 95. -- glen From newsfish@newsfish Thu Aug 1 00:35:02 2024 X-Received: by 10.50.62.49 with SMTP id v17mr8149530igr.1.1445075007345; Sat, 17 Oct 2015 02:43:27 -0700 (PDT) X-Received: by 10.50.124.69 with SMTP id mg5mr94183igb.10.1445075007289; Sat, 17 Oct 2015 02:43:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!feed.news.qwest.net!mpls-nntp-03.inet.qwest.net!216.166.98.85.MISMATCH!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!kq10no22525601igb.0!news-out.google.com!z4ni23657ign.0!nntp.google.com!kq10no19354314igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Oct 2015 02:43:26 -0700 (PDT) In-Reply-To: <46d2e97c-2e25-4d12-b4ff-d8a98cb91457@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> <46d2e97c-2e25-4d12-b4ff-d8a98cb91457@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2d43de1f-dcea-4fa8-88be-cf583d30c3cf@googlegroups.com> Subject: Re: Strange 'X' values. From: Ilya Kalistru Injection-Date: Sat, 17 Oct 2015 09:43:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:4068 Jim Lewis, thank you for your reply and a link to a good resource. From newsfish@newsfish Thu Aug 1 00:35:02 2024 X-Received: by 10.107.163.80 with SMTP id m77mr17831128ioe.0.1445075493415; Sat, 17 Oct 2015 02:51:33 -0700 (PDT) X-Received: by 10.50.164.167 with SMTP id yr7mr215690igb.2.1445075493399; Sat, 17 Oct 2015 02:51:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no19356416igb.0!news-out.google.com!n2ni32733igy.0!nntp.google.com!kq10no22528783igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Oct 2015 02:51:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b6230a9-a201-4434-bfda-caf958f21142@googlegroups.com> Subject: Re: Strange 'X' values. From: Ilya Kalistru Injection-Date: Sat, 17 Oct 2015 09:51:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4069 On Saturday, October 17, 2015 at 3:20:03 AM UTC+3, rickman wrote: > On 10/16/2015 3:31 PM, Ilya Kalistru wrote: > > Good day. > > I came across a strange behavior in my project and can't understand it.= Maybe you could explain it to me. > > I've reduced it to the point where it still persists. > > I've tried to ask on the xilinx forum > > but it looks like that that forum more engaged to help me avoid that pr= oblem then explain what is going on here... > > Here is the code > > > > entity test is > > Port ( > > Clock : in std_logic; > > Dev_Linked : in std_logic_vector(0 downto 0); > > R_CHCS : out std_logic_vector(1 downto 0):=3D"01" > > ); > > end entity test; > > > > architecture Behavioral of test is > > begin > > > > R_CHCS_proc : process (Clock) is > > begin > > if rising_edge(Clock) then > > for i in 0 to 0 loop > > R_CHCS(i * 2) <=3D '0'; > > end loop; > > end if; > > end process R_CHCS_proc; > > > > R_CHCS(1) <=3D Dev_Linked(0) when rising_edge(Clock); > > > > end Behavioral; > > > > On the first clock cycle R_CHCS becomes "X0". And I don't know why. On = Xilinx forum say that "Questa also gives the same output" and it's not a bu= g of the simulator and it's because each process makes it's own driver for = CHCS and it gives 'X' value. But it doesn't make sense for me because if I= remove unnecessary loop in R_CHCS_proc this problem disappears, and it is = nothing to do with processes. > > > > Maybe someone could explain this to me? >=20 > I think Jim gave you an explanation even if it is a bit hard to=20 > understand. VHDL has a lot of things like that. The basic rule is=20 > "don't do that". I can't say I see any reason why you would want to do= =20 > that. Why not just include the assignment to bit 1 of R_CHCS in the=20 > same clocked process as the other assignment to R_CHCS? >=20 > Rick >=20 > --=20 >=20 > Rick I just came across this strange thing and I became curious what it is and w= hy. I just want to understand VHDL better. Originally it was written in a such way in attempt to separate different ma= tters in different processes to make code more readable and assign differen= t resets to this different matters. (there were a problems with huge fanout= of a reset signal and failed timings as a result). From newsfish@newsfish Thu Aug 1 00:35:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Sat, 17 Oct 2015 09:58:43 +0000 (UTC) Organization: A noiseless patient Spider Lines: 19 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 17 Oct 2015 09:58:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="16691"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mGF5Kj9rFX46ZmjCSy71+HfRXwrlPmlA=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:7zGKlMUwdNZpSGV6qlvZ3QHFNn8= Xref: news.eternal-september.org comp.lang.vhdl:4070 comp.lang.verilog:1212 On Sat, 17 Oct 2015 07:21:33 +0000, glen herrmannsfeldt wrote: > > VHDL is a little wordier than I like, but it isn't so hard to live with. > I will like it better when VHDL 2008 is supported, where I rarely > complained about the features in verilog 95. > > -- glen You may be pleased to know that ghdl at version 0.33 supports a lot more of VHDL-2008 than previously. Enough to run Jim's OSVVM suite. Its source release was last week. There aren't builds for all OS/ distributions yet, so some people will still have to build from source, or wait... https://sourceforge.net/projects/ghdl-updates/ -- Brian From newsfish@newsfish Thu Aug 1 00:35:03 2024 X-Received: by 10.107.37.206 with SMTP id l197mr2105344iol.17.1445076461903; Sat, 17 Oct 2015 03:07:41 -0700 (PDT) X-Received: by 10.50.43.195 with SMTP id y3mr216271igl.1.1445076461887; Sat, 17 Oct 2015 03:07:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no19360769igb.0!news-out.google.com!n2ni32733igy.0!nntp.google.com!kq10no22533610igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Oct 2015 03:07:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Strange 'X' values. From: Ilya Kalistru Injection-Date: Sat, 17 Oct 2015 10:07:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4071 On Saturday, October 17, 2015 at 3:36:00 AM UTC+3, glen herrmannsfeldt wrote: > rickman wrote: > > On 10/16/2015 3:31 PM, Ilya Kalistru wrote: > >> I came across a strange behavior in my project and can't understand it. > >> Maybe you could explain it to me. > > (snip) > > >> R_CHCS_proc : process (Clock) is > >> begin > >> if rising_edge(Clock) then > >> for i in 0 to 0 loop > >> R_CHCS(i * 2) <= '0'; > >> end loop; > >> end if; > >> end process R_CHCS_proc; > > >> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); > > (snip) > > >> On the first clock cycle R_CHCS becomes "X0". > > (snip) > > > I think Jim gave you an explanation even if it is a bit hard to > > understand. VHDL has a lot of things like that. The basic rule is > > "don't do that". I can't say I see any reason why you would want to do > > that. Why not just include the assignment to bit 1 of R_CHCS in the > > same clocked process as the other assignment to R_CHCS? > > Yes. For each signal, use either the process form or the non-process > (verilog calls it continuous assignment) form, but don't mix them. > > In verilog, you have to declare reg or wire, so you have to decide early > which way you want to go. VHDL doesn't have that, but you still have to > get it right. > > It might work if you put the second one in its own process, but it has > to be in one. > > Also, I didn't know that you could use rising_edge(clock) outside > of process, but then again, I never even thought to try it. > > > -- glen Thank you for your advice. As for rising_edge(clock) outside of process, I met it somewhere and I found that it's good way to save few lines of code when you need something simple. Later I met this document http://www.synthworks.com/papers/VHDL_RTL_Synthesis_Standard_HDLCON_2002.pdf in which this way to make a register is also described. It works well with xilinx; I've been using it for several years. From newsfish@newsfish Thu Aug 1 00:35:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Sat, 17 Oct 2015 11:02:52 -0400 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Oct 2015 15:00:48 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="19141"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18QWPO+AEdkns8bal721HQu" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:MufWc2q4utA6AKNccf9yk9gQGUE= Xref: news.eternal-september.org comp.lang.vhdl:4072 comp.lang.verilog:1213 On 10/17/2015 3:21 AM, glen herrmannsfeldt wrote: > In comp.lang.vhdl rickman wrote: >> I'm not looking to start a VHDL vs. Verilog argument, but I was puzzled >> by Glen's comment in the VHDL group that he learned Verilog first before >> using VHDL. Am I correct in assuming you used VHDL because a customer >> required it? > > That is about right. > >> I learned VHDL, although not well, then went to work for a comms company >> who used Verilog. I never went to school for Verilog and never really >> bought a book. So I don't feel comfortable using it even though I have >> coded in it. > > I started about 1993. I was told that C programmers usually like > verilog, others I worked with were using it, so I did to. > > I bought both Thomas and Moorby's book, and the Sternhiem, Singh, > Madhavan, and Trivedi book. There might not have been many books > back then. Those two, and some Xilinx software to run designs > through, and I started writing down logic designs pretty soon. I will look into those references. My thing is I don't remember what I read as well as I used to. I'd like a book with the important stuff explicitly stated in a well organized manner so I can refer to it easily. Most importantly I want spelled out the various assumptions of Verilog code. I know there are things that are done with arithmetic that the user needs to understand. I found I could download the Thomas and Moorby book. The Doulos pages are often good, if not a great reference to return to. In this case I find the text runs off the screen without a scrollbar. To get it all on the page I have to shrink the text quite a bit. My old eyes don't like that. I wonder where that scrollbar has gotten to? > I also did some simulations with Veriwell. Is that more useful than the simulation tools from the FPGA vendors? >> On the other hand, after many years of VHDL, I won't say >> I've ever gotten "comfortable" with it. I've just learned to live with >> it. Part of the reason I haven't switched to Verilog is that I've never >> found a good book for it. In fact when I have asked in the Verilog >> group I'm told there *isn't* one. Buy "good" I mean one that covers all >> the pitfalls well. At least with VHDL it tells you you've screwed up. > > Many useful verilog features are new to VHDL, some too new for the > version of tools that I use. Even more, they are different for different > FPGA chips with the same version of tools. (Specifically, Spartan 3 vs. > Spartan 6.) Strange. By too new and "different" you mean some tools support some features which differ between the tools? So far I haven't found a VHDL 2008 feature I wanted to use that wasn't supported. It would be useful to have a chart of the features and the tools. With the restrictions on the tool licenses, I wonder if that would violate any by making and posting such a feature list? >> I'm curious who here has learned both and why? Which do you prefer and >> why? > > Most verilog operators are similar to C operators, so that helps some. > A few times, not so many, I have used & in VHDL when I meant AND. > > I still prefer verilog, but I figured out how to write most of the > things I need from verilog into VHDL. > > Verilog style concatenations are still too new to VHDL. The result is > a fair number of signals that are only needed to combine or separate > signals to/from a vector. I haven't found that. Have a ready example? > VHDL is a little wordier than I like, but it isn't so hard to live with. > I will like it better when VHDL 2008 is supported, where I rarely > complained about the features in verilog 95. I think calling VHDL "wordy" is like calling the Pope Catholic. I use it, but the typing is a PITA to the point I have regular expressions written in my boiler plate for converting between port declarations, instantiations and signal lists. Nicer would be an editor that could do much of that automatically... use a signal and the editor adds it to the signals list. Add a component instantiation and you just type the name and the full port map is added with "name => name" for each signal in the port list. I've touted the advantages of the strong typing used in VHDL, but I've never completely accepted that it is a big advantage. So I'm ready to give Verilog a try if I can find it less painful than all the typing I'd have to do to keep using VHDL. -- Rick From newsfish@newsfish Thu Aug 1 00:35:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Sat, 17 Oct 2015 19:10:47 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 29 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4073 comp.lang.verilog:1215 In comp.lang.vhdl rickman wrote: (snip) >> I also did some simulations with Veriwell. > Is that more useful than the simulation tools from the FPGA vendors? That was in the days before A and X had free versions. I was part of a discussion at FCCM 95 suggesting that companies should have free versions of the tools, and affordable (small) FPGAs. In my high school and college days, TTL chips were affordable enough to buy, design simple logic circuits and build them. A big reason for that was that enough were used in the computer industry to keep the economy of scale large, and prices low. I suspected in 1995 that as computers went more to VLSI, that TTL would go away. It seems that 20 years later, it is still fairly easy to get, and afford, TTL, but maybe not in 20 more years. (Though as I understand it, the usual undergrad digital logic course is now taught with simulation and no actual circuits.) If you just want a simple simulation, though, Veriwell is a fine choice. -- glen From newsfish@newsfish Thu Aug 1 00:35:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Sun, 18 Oct 2015 02:00:02 -0400 Organization: A noiseless patient Spider Lines: 73 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> <7b6230a9-a201-4434-bfda-caf958f21142@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 18 Oct 2015 05:57:59 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="02e5de92ffe817d22ea5761a436dd6e8"; logging-data="23793"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Ya5GgPI72ts5ffjP5n6sE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <7b6230a9-a201-4434-bfda-caf958f21142@googlegroups.com> Cancel-Lock: sha1:qe+rXmxvR9dmfwyrAS0w03mIX+g= Xref: news.eternal-september.org comp.lang.vhdl:4074 On 10/17/2015 5:51 AM, Ilya Kalistru wrote: > On Saturday, October 17, 2015 at 3:20:03 AM UTC+3, rickman wrote: >> On 10/16/2015 3:31 PM, Ilya Kalistru wrote: >>> Good day. I came across a strange behavior in my project and >>> can't understand it. Maybe you could explain it to me. I've >>> reduced it to the point where it still persists. I've tried to >>> ask on the xilinx forum but it looks like that that forum more >>> engaged to help me avoid that problem then explain what is going >>> on here... Here is the code >>> >>> entity test is Port ( Clock : in std_logic; Dev_Linked : in >>> std_logic_vector(0 downto 0); R_CHCS : out std_logic_vector(1 >>> downto 0):="01" ); end entity test; >>> >>> architecture Behavioral of test is begin >>> >>> R_CHCS_proc : process (Clock) is begin if rising_edge(Clock) >>> then for i in 0 to 0 loop R_CHCS(i * 2) <= '0'; end loop; end >>> if; end process R_CHCS_proc; >>> >>> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); >>> >>> end Behavioral; >>> >>> On the first clock cycle R_CHCS becomes "X0". And I don't know >>> why. On Xilinx forum say that "Questa also gives the same output" >>> and it's not a bug of the simulator and it's because each process >>> makes it's own driver for CHCS and it gives 'X' value. But it >>> doesn't make sense for me because if I remove unnecessary loop in >>> R_CHCS_proc this problem disappears, and it is nothing to do with >>> processes. >>> >>> Maybe someone could explain this to me? >> >> I think Jim gave you an explanation even if it is a bit hard to >> understand. VHDL has a lot of things like that. The basic rule >> is "don't do that". I can't say I see any reason why you would >> want to do that. Why not just include the assignment to bit 1 of >> R_CHCS in the same clocked process as the other assignment to >> R_CHCS? >> >> Rick >> >> -- >> >> Rick > > I just came across this strange thing and I became curious what it is > and why. I just want to understand VHDL better. > > Originally it was written in a such way in attempt to separate > different matters in different processes to make code more readable > and assign different resets to this different matters. (there were a > problems with huge fanout of a reset signal and failed timings as a > result). I guess the question then is, if these two signals need to be differentiated, why are they separate bits in the same vector? Make them separate signals and you can express their assignments totally separately. The common reset signal often does not meet any timing spec. It is better to design your circuits so that the timing on the reset does not matter. Any sequential logic that must leave the reset state together should use a common synchronization signal controlling the exit from reset. This often results in much smaller nets since the reset exit requirement is usually a local one rather than global. If it is global, then you will need a common control with multiple output FFs as repeaters so the fan out of each copy is not so great. -- Rick From newsfish@newsfish Thu Aug 1 00:35:04 2024 X-Received: by 10.129.4.203 with SMTP id 194mr2070921ywe.33.1445156961351; Sun, 18 Oct 2015 01:29:21 -0700 (PDT) X-Received: by 10.50.13.38 with SMTP id e6mr266751igc.5.1445156961320; Sun, 18 Oct 2015 01:29:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no10325180qge.1!news-out.google.com!n2ni33599igy.0!nntp.google.com!kq10no22904793igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 18 Oct 2015 01:29:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> <7b6230a9-a201-4434-bfda-caf958f21142@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Strange 'X' values. From: Ilya Kalistru Injection-Date: Sun, 18 Oct 2015 08:29:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4075 > I guess the question then is, if these two signals need to be=20 > differentiated, why are they separate bits in the same vector? Make=20 > them separate signals and you can express their assignments totally=20 > separately. I had similar thoughts just after reading of your comments to my post. R_C= HCS is a register which indicates states of a coprocessor for a CPU and dif= ferent bits of it have different meanings. So, in this case I should have d= ifferent signals for different indicators and then I should concatenate the= m in R_CHCS. I would have done that if it had been my code, but I am just t= rying to fix my colleague's code. > The common reset signal often does not meet any timing spec. It is=20 > better to design your circuits so that the timing on the reset does not= =20 > matter. Any sequential logic that must leave the reset state together=20 > should use a common synchronization signal controlling the exit from=20 > reset. This often results in much smaller nets since the reset exit=20 > requirement is usually a local one rather than global. If it is global,= =20 > then you will need a common control with multiple output FFs as=20 > repeaters so the fan out of each copy is not so great. it's exactly how I fixed this problem. > --=20 >=20 > Rick From newsfish@newsfish Thu Aug 1 00:35:04 2024 X-Received: by 10.68.131.104 with SMTP id ol8mr24762796pbb.4.1445242096562; Mon, 19 Oct 2015 01:08:16 -0700 (PDT) X-Received: by 10.50.129.10 with SMTP id ns10mr145783igb.0.1445242096489; Mon, 19 Oct 2015 01:08:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no23316709igb.0!news-out.google.com!z4ni25521ign.0!nntp.google.com!kq10no23316706igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 Oct 2015 01:08:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.168.206.17; posting-account=jGbtbQoAAADhdS75pUrt6RwP8xfugXhe NNTP-Posting-Host: 122.168.206.17 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Subject: C code for conversion instead of programming. From: Rajeev Varshney Injection-Date: Mon, 19 Oct 2015 08:08:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4076 Hello every1, I have a doubt about C code conversion. Can someone help me regard this. I am in RTL design. and I am getting some calls in that people ask , Howdo you use c? As programming or Conversion. Can someone please let me know about this. Or refer any document regard it. where is application for c code conversion for hdl. and any help regard this topic ..I am unable to understand, what actually they ask for. From newsfish@newsfish Thu Aug 1 00:35:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Mon, 19 Oct 2015 10:16:42 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 27 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4077 Rajeev Varshney wrote: > I have a doubt about C code conversion. Can someone help me > regard this. I am in RTL design. and I am getting some calls in > that people ask , Howdo you use c? As programming or Conversion. > Can someone please let me know about this. > Or refer any document regard it. Personally, I don't recommend using C as an HDL, but it might depend on what you are doing. verilog uses the C operators, so it is fairly easy for C programmers who know about digital logic design to learn to write. The designs I work on are so different from what anyone would do in C, that I don't see using C. > where is application for c code conversion for hdl. and any > help regard this topic ..I am unable to understand, > what actually they ask for. What are you actually trying to do? That makes a big difference in how you should do it. -- glen From newsfish@newsfish Thu Aug 1 00:35:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Mon, 19 Oct 2015 10:52:07 -0400 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 19 Oct 2015 14:50:02 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="79905ffb271791baaa8cf379f6c3d6ce"; logging-data="21882"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18GwRiQKnU/SwLLnr5FUM3H" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:+FDSkdqe65zKt/pJQxfwkftlgDc= Xref: news.eternal-september.org comp.lang.vhdl:4078 comp.lang.verilog:1217 On 10/17/2015 3:10 PM, glen herrmannsfeldt wrote: > In comp.lang.vhdl rickman wrote: > > (snip) > >>> I also did some simulations with Veriwell. > >> Is that more useful than the simulation tools from the FPGA vendors? > > That was in the days before A and X had free versions. > > I was part of a discussion at FCCM 95 suggesting that companies > should have free versions of the tools, and affordable (small) > FPGAs. Thank you on both those accounts. I have always felt FPGAs could be sold more like MCUs in many packages and with lots of variations of included I/O features. But the FPGA vendors still like their primary markets of comms where most of the need is for larger and faster devices. Unlike car companies where the money is made on the products for the average buyer, FPGAs are marketed to higher end buyers with extreme needs. I guess in general they do better selling to a few large customers rather than lots of small ones. Maybe the MCU market is just plain different in that regard with most of the profit coming from the many, many small quantity users across the board of device complexity. > In my high school and college days, TTL chips were affordable enough > to buy, design simple logic circuits and build them. A big reason > for that was that enough were used in the computer industry to keep > the economy of scale large, and prices low. > > I suspected in 1995 that as computers went more to VLSI, that TTL > would go away. It seems that 20 years later, it is still fairly > easy to get, and afford, TTL, but maybe not in 20 more years. Much TTL is getting harder to buy. There are still many basic functions available, but there used to be a wide assortment of specialized functions, many of which are no longer sold in any of the TTL/CMOS families. > (Though as I understand it, the usual undergrad digital logic course > is now taught with simulation and no actual circuits.) > > If you just want a simple simulation, though, Veriwell is a fine choice. I don't mind the vendor tools. Many years ago I had learned a bit of Modelsim and ordered the low end Lattice tools with Modelsim. At that point you still had to pay Lattice for a package with a simulator. A month later when they shipped, it came with the Aldec simulator which I knew nothing about. I had a COW and talked to half a dozen reps on the phone which got me nowhere. When I fired up the tool I found there was little difference and could use the tool pretty well so I cooled off and got to work. Heck, at that time Modelsim had a memory leak that would crash it every so often and this tool worked without crashing so I was actually better off. lol So I'm happy with the simulators from the vendors although I haven't used Xilinx tools in a while. I read a lot lately about their schizoid nature. -- Rick From newsfish@newsfish Thu Aug 1 00:35:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Mon, 19 Oct 2015 10:58:04 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 19 Oct 2015 14:56:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="79905ffb271791baaa8cf379f6c3d6ce"; logging-data="23612"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19JRkGHhFBFJZ+i8w7D0L5B" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Cancel-Lock: sha1:pcD0pOEU66SvWT5gFG4cDicynYg= Xref: news.eternal-september.org comp.lang.vhdl:4079 On 10/19/2015 4:08 AM, Rajeev Varshney wrote: > Hello every1, > I have a doubt about C code conversion. Can someone help me regard this. I am in RTL design. and I am getting some calls in that people ask , Howdo you use c? As programming or Conversion. > Can someone please let me know about this. Or refer any document regard it. > > > where is application for c code conversion for hdl. and any help regard this topic ..I am unable to understand, what actually they ask for. There are C to hardware compilers. But I think, like any HDL, for your code to be synthesizable it has to be written according to a style guide. Even in VHDL or Verilog, you can write code that will simulate, but won't be synthesizable. Much more so in C. Here is a like to a discussion of C tools for FPGAs. http://stackoverflow.com/questions/8988629/can-you-program-fpgas-in-c-like-languages This Wikipedia article has a list of potential tools. https://en.wikipedia.org/wiki/C_to_HDL -- Rick From newsfish@newsfish Thu Aug 1 00:35:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Mon, 19 Oct 2015 22:25:47 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 22 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4080 rickman wrote: > On 10/19/2015 4:08 AM, Rajeev Varshney wrote: >> I have a doubt about C code conversion. Can someone help me >> regard this. I am in RTL design. and I am getting some calls >> in that people ask , Howdo you use c? >> As programming or Conversion. (snip) > There are C to hardware compilers. But I think, like any HDL, for your > code to be synthesizable it has to be written according to a style > guide. Even in VHDL or Verilog, you can write code that will simulate, > but won't be synthesizable. Much more so in C. I have thought that a tool that would compile a program to some intermediate code, and also generate logic for an efficient interpreter of that code, could be useful. That is, a soft processor optimized for the code at hand. -- glen From newsfish@newsfish Thu Aug 1 00:35:06 2024 X-Received: by 10.50.62.68 with SMTP id w4mr1340471igr.13.1445313146964; Mon, 19 Oct 2015 20:52:26 -0700 (PDT) X-Received: by 10.50.131.162 with SMTP id on2mr24582igb.4.1445313146910; Mon, 19 Oct 2015 20:52:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no23782676igb.0!news-out.google.com!z4ni26261ign.0!nntp.google.com!kq10no23782667igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 Oct 2015 20:52:26 -0700 (PDT) In-Reply-To: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.168.178.15; posting-account=jGbtbQoAAADhdS75pUrt6RwP8xfugXhe NNTP-Posting-Host: 122.168.178.15 References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> Subject: Re: C code for conversion instead of programming. From: Rajeev Varshney Injection-Date: Tue, 20 Oct 2015 03:52:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4081 Hello, Thanks you for your valueable suggestion..... After reading your responses, I have question that why people ask for c to hdl. Also last year I came to know some technology specialist that upcoming hardware will be based on clanguages. I s it related to something 7Series FPGA. From newsfish@newsfish Thu Aug 1 00:35:06 2024 X-Received: by 10.31.149.200 with SMTP id x191mr1279122vkd.14.1445322851676; Mon, 19 Oct 2015 23:34:11 -0700 (PDT) X-Received: by 10.50.30.102 with SMTP id r6mr404647igh.3.1445322851636; Mon, 19 Oct 2015 23:34:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m48no356797qgd.0!news-out.google.com!n2ni35576igy.0!nntp.google.com!kq10no23826212igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 Oct 2015 23:34:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.23.60.4; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 185.23.60.4 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c94c43f-6681-4088-a876-17692af9d843@googlegroups.com> Subject: Re: creating program From: bknpk@hotmail.com Injection-Date: Tue, 20 Oct 2015 06:34:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1708 X-Received-Body-CRC: 2972710380 Xref: news.eternal-september.org comp.lang.vhdl:4082 On Friday, October 16, 2015 at 12:36:53 PM UTC+3, aadi wrote: > i have learned every aspect of VHDL but i still can't exersise it to make complex program. > i need a code for data encryption standard and also for key generation. but i can't get a single way to do so > plzz help me You may want to see some examples. A simple UART project http://bknpk.ddns.net/my_web/MiscellaneousHW/UART/uart_tx_1.html A more complex design based on some free open IP stack. It also synthesized with Xilinx free XST and simulated with post NGD net-list. All is done with the free VHDL simulator GHDL http://bknpk.ddns.net/my_web/IP_STACK/start_1.html From newsfish@newsfish Thu Aug 1 00:35:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Tue, 20 Oct 2015 04:22:28 -0400 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 20 Oct 2015 08:20:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="2576"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/R6vsLkmV3fvRHAGDgsfkx" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:8izYjPJdt57NgCb4JzL1bC8N400= Xref: news.eternal-september.org comp.lang.vhdl:4083 On 10/19/2015 6:25 PM, glen herrmannsfeldt wrote: > rickman wrote: >> On 10/19/2015 4:08 AM, Rajeev Varshney wrote: > >>> I have a doubt about C code conversion. Can someone help me >>> regard this. I am in RTL design. and I am getting some calls >>> in that people ask , Howdo you use c? >>> As programming or Conversion. > > (snip) > >> There are C to hardware compilers. But I think, like any HDL, for your >> code to be synthesizable it has to be written according to a style >> guide. Even in VHDL or Verilog, you can write code that will simulate, >> but won't be synthesizable. Much more so in C. > > I have thought that a tool that would compile a program to some > intermediate code, and also generate logic for an efficient > interpreter of that code, could be useful. > > That is, a soft processor optimized for the code at hand. Perhaps, but how much better than just buying an already optimized hard IP processor like an ARM or an x86 of some flavor? Sure soft processors have uses, but the work involved in designing such a tool to automatically produce machine code and a processor from C code would be a lot more than can be justified I'd bet, but who knows? It may just be the lack of a perceived market. Maybe this would be a good university research project? -- Rick From newsfish@newsfish Thu Aug 1 00:35:07 2024 X-Received: by 10.182.181.3 with SMTP id ds3mr1838423obc.5.1445333509807; Tue, 20 Oct 2015 02:31:49 -0700 (PDT) X-Received: by 10.50.85.47 with SMTP id e15mr30267igz.9.1445333509786; Tue, 20 Oct 2015 02:31:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no20227616igb.0!news-out.google.com!n2ni35709igy.0!nntp.google.com!kq10no23895661igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 02:31:49 -0700 (PDT) In-Reply-To: <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: C code for conversion instead of programming. From: Thomas Stanka Injection-Date: Tue, 20 Oct 2015 09:31:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4084 Am Dienstag, 20. Oktober 2015 05:52:30 UTC+2 schrieb Rajeev Varshney: > After reading your responses, I have question that why people ask for c t= o hdl. You should ask this to the person asking you. In general you might have a C based simulation model and like to easy excha= nge pure software with your design model written in C to verify the design = will behave like expected. In C you use usually cycle based simulation inst= ead of time based (ns,ps,..) simulation. Cycle based simulation ignores som= e effects but simulations run significant faster. Additionally there is no = simulator providing the same simulation speed, than any C-executeable.=20 On the contrary ask any specialist who likes to sell you C based hardware d= esign, how to scope with 10 clock domains that are asynchronous to each oth= er in C and how to access existing design IP written in Verilog.=20 bye Thomas From newsfish@newsfish Thu Aug 1 00:35:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Tue, 20 Oct 2015 09:49:42 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 28 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4085 rickman wrote: (snip on C as an HDL) (then I wrote) >> I have thought that a tool that would compile a program to some >> intermediate code, and also generate logic for an efficient >> interpreter of that code, could be useful. >> That is, a soft processor optimized for the code at hand. > Perhaps, but how much better than just buying an already optimized hard > IP processor like an ARM or an x86 of some flavor? Sure soft processors > have uses, but the work involved in designing such a tool to > automatically produce machine code and a processor from C code would be > a lot more than can be justified I'd bet, but who knows? It may just be > the lack of a perceived market. Maybe this would be a good university > research project? I haven't looked in detail how the usual soft processors work. It wouldn't seem so hard to compile the C, see which instructions the code actually used, then remove instructions from the soft processor that weren't used. That should be much less work than the synthesis tools themselves. -- glen From newsfish@newsfish Thu Aug 1 00:35:08 2024 X-Received: by 10.107.159.132 with SMTP id i126mr3392909ioe.23.1445350373004; Tue, 20 Oct 2015 07:12:53 -0700 (PDT) X-Received: by 10.50.103.69 with SMTP id fu5mr71162igb.5.1445350372986; Tue, 20 Oct 2015 07:12:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no24013354igb.0!news-out.google.com!n2ni35889igy.0!nntp.google.com!kq10no24013344igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 07:12:52 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.117.144; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.117.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Why does Modelsim insist so many bits for a multiplication? From: fl Injection-Date: Tue, 20 Oct 2015 14:12:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4086 Hi, I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter unsigned or signed number. When I try it with Modelsim, I find that it insists the result be 10-bit. Otherwise, it issues a warning. Could you explain what rule behind Modelsim to give such a warning? Thanks, ---------------- architecture behave of example_signed_unsigned is signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); signal rs_SUB_RESULT : signed(4 downto 0) := (others => '0'); signal ru_SUB_RESULT : unsigned(4 downto 0) := (others => '0'); signal rs_mpy_RESULT : signed(9 downto 0) := (others => '0'); signal ru_mpy_RESULT : unsigned(9 downto 0) := (others => '0'); begin -- Purpose: Add two numbers. Does both the signed and unsigned -- addition for demonstration. This process is synthesizable. p_SUM : process (i_clk, i_rst_l) begin if i_rst_l = '0' then -- asynchronous reset (active low) rs_SUM_RESULT <= (others => '0'); ru_SUM_RESULT <= (others => '0'); elsif rising_edge(i_clk) then ru_SUM_RESULT <= unsigned(i_a) + unsigned(i_b); rs_SUM_RESULT <= signed(i_a) + signed(i_b); end if; end process p_SUM; p_mpy0 : process (i_clk, i_rst_l) begin if i_rst_l = '0' then -- asynchronous reset (active low) rs_mpy_RESULT <= (others => '0'); ru_mpy_RESULT <= (others => '0'); elsif rising_edge(i_clk) then ru_mpy_RESULT <= unsigned(i_a) * unsigned(i_b); rs_mpy_RESULT <= signed(i_a) * signed(i_b); end if; end process p_mpy0; From newsfish@newsfish Thu Aug 1 00:35:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!bloom-beacon.mit.edu!bloom-beacon.mit.edu!panix!newsfeed-00.mathworks.com!news.mathworks.com!not-for-mail From: Tim McBrayer Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 10:38:08 -0400 Organization: The MathWorks, Inc. Lines: 23 Message-ID: References: NNTP-Posting-Host: tmcbraye-deb7-64.dhcp.mathworks.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: newscl01ah.mathworks.com 1445351888 16858 172.28.219.76 (20 Oct 2015 14:38:08 GMT) X-Complaints-To: news@mathworks.com NNTP-Posting-Date: Tue, 20 Oct 2015 14:38:08 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Icedove/24.5.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:4087 On 10/20/2015 10:12 AM, fl wrote: > Hi, > > I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter > unsigned or signed number. When I try it with Modelsim, I find that it > insists the result be 10-bit. Otherwise, it issues a warning. Your 9-bit product assumption is the problem; 9 bits are not enough to store 5 bits * 5 bits at full precision. It requires 10 bits. Take the simplest example, multiplying two unsigned 5-bit numbers. 2^5 has range 0 to 31. Max value of multiplication: 31 * 31 = 961 Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: 2^10 - 1 = 1023 Thus, 5 bits * 5 bits requires 10 bits for a full precision result. -- Tim McBrayer MathWorks From newsfish@newsfish Thu Aug 1 00:35:08 2024 X-Received: by 10.107.28.67 with SMTP id c64mr2321707ioc.1.1445356178348; Tue, 20 Oct 2015 08:49:38 -0700 (PDT) X-Received: by 10.50.57.17 with SMTP id e17mr63603igq.2.1445356178332; Tue, 20 Oct 2015 08:49:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no24059364igb.0!news-out.google.com!n2ni35970igy.0!nntp.google.com!kq10no20340615igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 08:49:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.117.144; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.117.144 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why does Modelsim insist so many bits for a multiplication? From: fl Injection-Date: Tue, 20 Oct 2015 15:49:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4088 On Tuesday, October 20, 2015 at 10:38:12 AM UTC-4, Tim McBrayer wrote: > On 10/20/2015 10:12 AM, fl wrote: > > Hi, > > > > I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter > > unsigned or signed number. When I try it with Modelsim, I find that i= t > > insists the result be 10-bit. Otherwise, it issues a warning. >=20 >=20 > Your 9-bit product assumption is the problem; 9 bits are not enough to st= ore 5 bits * 5=20 > bits at full precision. It requires 10 bits. >=20 > Take the simplest example, multiplying two unsigned 5-bit numbers. 2^5 ha= s range 0 to 31. >=20 > Max value of multiplication: 31 * 31 =3D 961 >=20 > Max unsigned 9-bit value: 2^9 - 1 =3D 511 > Max unsigned 10-bit value: 2^10 - 1 =3D 1023 >=20 > Thus, 5 bits * 5 bits requires 10 bits for a full precision result. > --=20 > Tim McBrayer > MathWorks Thanks. You said is correct for unsigned number multiplication. I just verify that it is correct for signed number multiplication. But the puzzling thing is that there are such examples on the web: Q15 multiplies Q15, the result is Q31. There is a sign extension bit. I always clip the= =20 MSB of the multiplication result, then often round to 16-bit.=20 Thanks for your article. Now I am puzzling on fixed point multiplication wh= en thinking about the multiplication product. First of all, Q.x format coul= d be signed, or unsigned number, is it right? After reading other online docs, I put it here to rephrase my question: Then, for signed numbers Q.a and Q.b, the product is Q.(a+b). Q.a has to us= e (a+1) bit to represent it. Q.b has to use (b+1) bit to represent it too. = So, the result has one redundant sign extension bit. When I write VHDL code= , Modelsim insists on using 10-bit result for two signed integers Q5.0 mult= iplies Q5.0. Why does it not consider sign extension bit? From newsfish@newsfish Thu Aug 1 00:35:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:11:40 +0000 (UTC) Organization: A noiseless patient Spider Lines: 67 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Oct 2015 16:11:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0a3c9f09d5246ee6d0bbab9a3b7899b1"; logging-data="14940"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18r8ic31AivblicvGh6Cv+G" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:vr/JCbrdhVBUGRCP9PHF56Y/l+A= Xref: news.eternal-september.org comp.lang.vhdl:4089 On Tue, 20 Oct 2015 08:49:37 -0700, fl wrote: > On Tuesday, October 20, 2015 at 10:38:12 AM UTC-4, Tim McBrayer wrote: >> On 10/20/2015 10:12 AM, fl wrote: >> > Hi, >> > >> > I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >> > unsigned or signed number. When I try it with Modelsim, I find that >> > it insists the result be 10-bit. Otherwise, it issues a warning. >> >> >> Your 9-bit product assumption is the problem; 9 bits are not enough to >> store 5 bits * 5 bits at full precision. It requires 10 bits. >> >> Take the simplest example, multiplying two unsigned 5-bit numbers. 2^5 >> has range 0 to 31. >> >> Max value of multiplication: 31 * 31 = 961 >> >> Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: 2^10 >> - 1 = 1023 >> >> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >> -- >> Tim McBrayer MathWorks > > Thanks. You said is correct for unsigned number multiplication. I just > verify that it is correct for signed number multiplication. But the > puzzling thing is that there are such examples on the web: Q15 > multiplies Q15, the result is Q31. There is a sign extension bit. I > always clip the MSB of the multiplication result, then often round to > 16-bit. > > Thanks for your article. Now I am puzzling on fixed point multiplication > when thinking about the multiplication product. First of all, Q.x format > could be signed, or unsigned number, is it right? > > After reading other online docs, I put it here to rephrase my question: > Then, for signed numbers Q.a and Q.b, the product is Q.(a+b). Q.a has to > use (a+1) bit to represent it. Q.b has to use (b+1) bit to represent it > too. So, the result has one redundant sign extension bit. When I write > VHDL code, Modelsim insists on using 10-bit result for two signed > integers Q5.0 multiplies Q5.0. Why does it not consider sign extension > bit? Because the "sign extension bit" is not redundant information in exactly one case. In your format -1 is represented 1.0000. 1.0000 * 1.0000 = -1 * -1 = 1 = 01.00000000. Also, this is why I loathe Q notation; no one ever quite follows what it means. Instead I use Ux.y and Sx.y. A signed number with a total of 5 bits and a range of [-1, 1) is S1.4. 1 integer bit (with a value of -1) and 4 fractional bits of values 1/2, 1/4, 1/8, and 1/16. When you multiply it's trivially simple to track the binary point; you add integer bits together and you add fractional bits together. S1.4 * S1.4 = S2.8, or to be completely explicit: S1.4 [-1,1) * S1.4 [-1,1) = S2.8 [-1,1]. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:35:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:21:03 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 27 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4090 Tim McBrayer wrote: > On 10/20/2015 10:12 AM, fl wrote: >> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >> unsigned or signed number. When I try it with Modelsim, I find that it >> insists the result be 10-bit. Otherwise, it issues a warning. > Your 9-bit product assumption is the problem; 9 bits are not enough > to store 5 bits * 5 bits at full precision. It requires 10 bits. > Take the simplest example, multiplying two unsigned 5-bit numbers. > 2^5 has range 0 to 31. > Max value of multiplication: 31 * 31 = 961 > Max unsigned 9-bit value: 2^9 - 1 = 511 > Max unsigned 10-bit value: 2^10 - 1 = 1023 > Thus, 5 bits * 5 bits requires 10 bits for a full precision result. But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. The real question is what VHDL says about it. The verilog rules for add are funny, and many get it wrong. -- glen From newsfish@newsfish Thu Aug 1 00:35:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:58:02 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 37 Message-ID: References: Injection-Date: Tue, 20 Oct 2015 16:58:02 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="19757"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1898mYyiUxOeo30gYww8CQr" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:eX6XBo4n+h528nmBniTn5Ke0/1Q= Xref: news.eternal-september.org comp.lang.vhdl:4091 In article , glen herrmannsfeldt wrote: >Tim McBrayer wrote: >> On 10/20/2015 10:12 AM, fl wrote: > >>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >>> unsigned or signed number. When I try it with Modelsim, I find that it >>> insists the result be 10-bit. Otherwise, it issues a warning. > >> Your 9-bit product assumption is the problem; 9 bits are not enough >> to store 5 bits * 5 bits at full precision. It requires 10 bits. > >> Take the simplest example, multiplying two unsigned 5-bit numbers. >> 2^5 has range 0 to 31. > >> Max value of multiplication: 31 * 31 = 961 > >> Max unsigned 9-bit value: 2^9 - 1 = 511 >> Max unsigned 10-bit value: 2^10 - 1 = 1023 > >> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. > >But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. Glen - huh? The (max negative) * (max negative) case does NOT fit in 9 bits for signed either. (-16)*(-16) = 256 = 'b01_0000_0000 you need 10 bits - you need the sign bit at the output too. Or I'm missing your point? Regards, Mark From newsfish@newsfish Thu Aug 1 00:35:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:14:18 -0400 Organization: A noiseless patient Spider Lines: 74 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 20 Oct 2015 20:12:12 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10369"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Li7dEhv+BrgJHFW3PYQJE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:S4OaaGiRNKMjVy1YOOxzMR3FvFY= Xref: news.eternal-september.org comp.lang.vhdl:4092 On 10/20/2015 12:11 PM, Rob Gaddi wrote: > On Tue, 20 Oct 2015 08:49:37 -0700, fl wrote: > >> On Tuesday, October 20, 2015 at 10:38:12 AM UTC-4, Tim McBrayer wrote: >>> On 10/20/2015 10:12 AM, fl wrote: >>>> Hi, >>>> >>>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >>>> unsigned or signed number. When I try it with Modelsim, I find that >>>> it insists the result be 10-bit. Otherwise, it issues a warning. >>> >>> >>> Your 9-bit product assumption is the problem; 9 bits are not enough to >>> store 5 bits * 5 bits at full precision. It requires 10 bits. >>> >>> Take the simplest example, multiplying two unsigned 5-bit numbers. 2^5 >>> has range 0 to 31. >>> >>> Max value of multiplication: 31 * 31 = 961 >>> >>> Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: 2^10 >>> - 1 = 1023 >>> >>> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >>> -- >>> Tim McBrayer MathWorks >> >> Thanks. You said is correct for unsigned number multiplication. I just >> verify that it is correct for signed number multiplication. But the >> puzzling thing is that there are such examples on the web: Q15 >> multiplies Q15, the result is Q31. There is a sign extension bit. I >> always clip the MSB of the multiplication result, then often round to >> 16-bit. >> >> Thanks for your article. Now I am puzzling on fixed point multiplication >> when thinking about the multiplication product. First of all, Q.x format >> could be signed, or unsigned number, is it right? >> >> After reading other online docs, I put it here to rephrase my question: >> Then, for signed numbers Q.a and Q.b, the product is Q.(a+b). Q.a has to >> use (a+1) bit to represent it. Q.b has to use (b+1) bit to represent it >> too. So, the result has one redundant sign extension bit. When I write >> VHDL code, Modelsim insists on using 10-bit result for two signed >> integers Q5.0 multiplies Q5.0. Why does it not consider sign extension >> bit? > > Because the "sign extension bit" is not redundant information in exactly > one case. In your format -1 is represented 1.0000. 1.0000 * 1.0000 = -1 > * -1 = 1 = 01.00000000. > > Also, this is why I loathe Q notation; no one ever quite follows what it > means. Instead I use Ux.y and Sx.y. A signed number with a total of 5 > bits and a range of [-1, 1) is S1.4. 1 integer bit (with a value of -1) > and 4 fractional bits of values 1/2, 1/4, 1/8, and 1/16. > > When you multiply it's trivially simple to track the binary point; you > add integer bits together and you add fractional bits together. S1.4 * > S1.4 = S2.8, or to be completely explicit: > > S1.4 [-1,1) * S1.4 [-1,1) = S2.8 [-1,1]. Now I'm lost. 5 bit signed integers would be -16 to 15. Max range of the product would be from -16 * -16 yielding -256 which is a 9 bit signed number, no? My understanding is that you need 1 bit for the sign and n-1 bits for the significands (or whatever they are called). So the product will be able to eliminate one of the sign bits and use 2 * (n-1) + 1 or 2n - 1 bits total. Your notation of the product, S2.8 implies there is a larger range in the product than [-1,1), no? The product will be S1.8 I think. -- Rick From newsfish@newsfish Thu Aug 1 00:35:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:15:20 -0400 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 20 Oct 2015 20:13:13 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10369"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+r3I3P1iEE3nRI52CnVeRD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:0LbXBzVwx5qxzIzakXPm37ZGYXo= Xref: news.eternal-september.org comp.lang.vhdl:4093 On 10/20/2015 12:21 PM, glen herrmannsfeldt wrote: > Tim McBrayer wrote: >> On 10/20/2015 10:12 AM, fl wrote: > >>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >>> unsigned or signed number. When I try it with Modelsim, I find that it >>> insists the result be 10-bit. Otherwise, it issues a warning. > >> Your 9-bit product assumption is the problem; 9 bits are not enough >> to store 5 bits * 5 bits at full precision. It requires 10 bits. > >> Take the simplest example, multiplying two unsigned 5-bit numbers. >> 2^5 has range 0 to 31. > >> Max value of multiplication: 31 * 31 = 961 > >> Max unsigned 9-bit value: 2^9 - 1 = 511 >> Max unsigned 10-bit value: 2^10 - 1 = 1023 > >> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. > > But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. > > The real question is what VHDL says about it. > > The verilog rules for add are funny, and many get it wrong. That is what I've read and why I'm looking for a book that explains this clearly before I commit to using Verilog. -- Rick From newsfish@newsfish Thu Aug 1 00:35:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:20:40 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Oct 2015 20:18:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="12002"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+tXTr+vQpUcMkbX2Yv2Imc" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:MChPlZIRxbN1Gkz8Gdn+DO4B8NU= Xref: news.eternal-september.org comp.lang.vhdl:4094 On 10/20/2015 12:58 PM, Mark Curry wrote: > In article , > glen herrmannsfeldt wrote: >> Tim McBrayer wrote: >>> On 10/20/2015 10:12 AM, fl wrote: >> >>>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >>>> unsigned or signed number. When I try it with Modelsim, I find that it >>>> insists the result be 10-bit. Otherwise, it issues a warning. >> >>> Your 9-bit product assumption is the problem; 9 bits are not enough >>> to store 5 bits * 5 bits at full precision. It requires 10 bits. >> >>> Take the simplest example, multiplying two unsigned 5-bit numbers. >>> 2^5 has range 0 to 31. >> >>> Max value of multiplication: 31 * 31 = 961 >> >>> Max unsigned 9-bit value: 2^9 - 1 = 511 >>> Max unsigned 10-bit value: 2^10 - 1 = 1023 >> >>> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >> >> But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. > > Glen - huh? The (max negative) * (max negative) case does NOT fit > in 9 bits for signed either. > > (-16)*(-16) = 256 = 'b01_0000_0000 > you need 10 bits - you need the sign bit at the output too. > > Or I'm missing your point? Opps, I was thinking 1_0000_0000 would be a negative value, duh. Now I remember that this is the defining case for multiplication and requires the full 2n bits... just as Rob said. If your data is for any reason limited to (2^(n-1)-1) then one less bit is needed for the product. Such is the case if an unsigned value was negated to produce the signed value. I don't get his product notation becoming S2.8 rather than S1.9 though. If the range of the result is [-1,1) there is still only one bit left of the binary point, or am I wrong about that too, lol? -- Rick From newsfish@newsfish Thu Aug 1 00:35:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 20:32:53 +0000 (UTC) Organization: A noiseless patient Spider Lines: 38 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Oct 2015 20:32:53 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0a3c9f09d5246ee6d0bbab9a3b7899b1"; logging-data="14940"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18RNmuFRq/4kYbE4MioqZDg" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:kSSnB3NiATUF5wsDlBFhd6AlFG8= Xref: news.eternal-september.org comp.lang.vhdl:4095 On Tue, 20 Oct 2015 16:14:18 -0400, rickman wrote: > On 10/20/2015 12:11 PM, Rob Gaddi wrote: >> On Tue, 20 Oct 2015 08:49:37 -0700, fl wrote: >> >> Also, this is why I loathe Q notation; no one ever quite follows what >> it means. Instead I use Ux.y and Sx.y. A signed number with a total >> of 5 bits and a range of [-1, 1) is S1.4. 1 integer bit (with a value >> of -1) and 4 fractional bits of values 1/2, 1/4, 1/8, and 1/16. >> >> When you multiply it's trivially simple to track the binary point; you >> add integer bits together and you add fractional bits together. S1.4 * >> S1.4 = S2.8, or to be completely explicit: >> >> S1.4 [-1,1) * S1.4 [-1,1) = S2.8 [-1,1]. > > Now I'm lost. 5 bit signed integers would be -16 to 15. Max range of > the product would be from -16 * -16 yielding -256 which is a 9 bit > signed number, no? My understanding is that you need 1 bit for the sign > and n-1 bits for the significands (or whatever they are called). So the > product will be able to eliminate one of the sign bits and use 2 * (n-1) > + 1 or 2n - 1 bits total. > Nope. -16 * -16 = +256. 01_0000_0000b if you're in 2's compliment and thus the MSB has a negative value. > Your notation of the product, S2.8 implies there is a larger range in > the product than [-1,1), no? The product will be S1.8 I think. There is a larger range in the product, it's [-1, 1]. The inclusion of +1 as a possibility is a righteous pain in the ass and requires you be willing to give up an entire bit to its existence if you can't preclude it. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:35:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 20:46:32 +0000 (UTC) Organization: A noiseless patient Spider Lines: 66 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Oct 2015 20:46:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0a3c9f09d5246ee6d0bbab9a3b7899b1"; logging-data="14940"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19vDwMST037gBSF4/5dTqSj" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:LSGmI+PF/HjapYMtoQIM/kavxaY= Xref: news.eternal-september.org comp.lang.vhdl:4096 On Tue, 20 Oct 2015 16:20:40 -0400, rickman wrote: > On 10/20/2015 12:58 PM, Mark Curry wrote: >> In article , >> glen herrmannsfeldt wrote: >>> Tim McBrayer wrote: >>>> On 10/20/2015 10:12 AM, fl wrote: >>> >>>>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no >>>>> matter >>>>> unsigned or signed number. When I try it with Modelsim, I find >>>>> that it insists the result be 10-bit. Otherwise, it issues a >>>>> warning. >>> >>>> Your 9-bit product assumption is the problem; 9 bits are not enough >>>> to store 5 bits * 5 bits at full precision. It requires 10 bits. >>> >>>> Take the simplest example, multiplying two unsigned 5-bit numbers. >>>> 2^5 has range 0 to 31. >>> >>>> Max value of multiplication: 31 * 31 = 961 >>> >>>> Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: >>>> 2^10 - 1 = 1023 >>> >>>> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >>> >>> But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. >> >> Glen - huh? The (max negative) * (max negative) case does NOT fit in 9 >> bits for signed either. >> >> (-16)*(-16) = 256 = 'b01_0000_0000 you need 10 bits - you need the sign >> bit at the output too. >> >> Or I'm missing your point? > > Opps, I was thinking 1_0000_0000 would be a negative value, duh. Now I > remember that this is the defining case for multiplication and requires > the full 2n bits... just as Rob said. If your data is for any reason > limited to ±(2^(n-1)-1) then one less bit is needed for the product. > Such is the case if an unsigned value was negated to produce the signed > value. > > I don't get his product notation becoming S2.8 rather than S1.9 though. > If the range of the result is [-1,1) there is still only one bit left > of the binary point, or am I wrong about that too, lol? Nope. The LSB in S1.4 was 2^-4 = 1/16. The LSB of the product, therefore is 1/256, 2^-8. Likewise, as you pointed out, the representation of +1 is 01.0000_0000b, i.e. 2^0. The representation of -1 therefore is 11.0000_0000b, -(2^1) + 2^0 = -2 + 1 = -1. The total representable range is [-2,2), but if you get there from the product of two S1.4 numbers on [-1,1) then you've got a number that is S2.8 [-1,1]. So the number is, by virtue of what it actually represents, not capable of using the entire range representable by its format. That S/U notation, and actually carrying along explicit ranging information, is why I can write fixed-point code that is right the first time these days. God knows I didn't get any smarter, I just started using a notation that is so explicit and bloody stupid that it shouts your mistakes from the rafters. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:35:11 2024 X-Received: by 10.129.88.87 with SMTP id m84mr4997816ywb.0.1445382813429; Tue, 20 Oct 2015 16:13:33 -0700 (PDT) X-Received: by 10.50.85.47 with SMTP id e15mr137459igz.9.1445382813397; Tue, 20 Oct 2015 16:13:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c107no447168qgd.1!news-out.google.com!n2ni36247igy.0!nntp.google.com!kq10no20480223igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 16:13:32 -0700 (PDT) In-Reply-To: <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: C code for conversion instead of programming. From: michael6866 Injection-Date: Tue, 20 Oct 2015 23:13:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4097 On Monday, October 19, 2015 at 11:52:30 PM UTC-4, Rajeev Varshney wrote: > Hello, >=20 >=20 > Thanks you for your valueable suggestion..... > After reading your responses, I have question that why people ask for c t= o hdl. > Also last year I came to know some technology specialist that=20 > upcoming hardware will be based on clanguages. > I s it related to something 7Series FPGA. It's not necessary in C. Some other high level programming languages are po= ssible as well, for example SystemC (there is also a standardization effort= on the synthesizable subset going on). The reason to model in such kind of= languages is mainly 1) speed up simulation 2) start SoC verification early= . Now that you have the verified C model ready, it's normal to think why no= t convert it to HDL automatically.=20 High level synthesis is a trend. Eventually it will arrive just like how de= sign methodology evolved from gate level to RTL. Many large companies are t= rying that and some of them been benefited from HLS already (excuse me but = I cannot expose the names of the customers). If you're looking for more inf= ormation, you can keep an eye on 1) Stratus from Cadence, mainly focused on= SystemC 2) Catapult C from Calypto (now acquired by Mentor) By the way, the opposite direction also exists - that is to convert a synth= esizable HDL to C/C++ automatically. In that case the goal is merely speedu= p. One such example is ARM Cortex cores. They provide you cycle-accurate C+= + models which are derived from RTL (the process is largely done by compile= r tools from Synopsys) Michael From newsfish@newsfish Thu Aug 1 00:35:11 2024 X-Received: by 10.182.196.34 with SMTP id ij2mr887598obc.24.1445395132111; Tue, 20 Oct 2015 19:38:52 -0700 (PDT) X-Received: by 10.50.43.229 with SMTP id z5mr163353igl.8.1445395132092; Tue, 20 Oct 2015 19:38:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no24317610igb.0!news-out.google.com!n2ni36406igy.0!nntp.google.com!kq10no24317600igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 19:38:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.117.144; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.117.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Question about std_logic variable compared with '0' From: fl Injection-Date: Wed, 21 Oct 2015 02:38:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4098 Hi, I never took a VHDL class, although I read a book for some time. Recently I have some progress. Some conceptual questions pop up occasionally. I find understanding these questions help me writing good code. 'in2sel' is the entity input port. I am curious about ( in2sel > '0' ). I guess in2sel should be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-determined order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' mean? i.e. the comparing is on what category? Is it an integer subtype? Or something else? I don't find the solution after a web search. Hopefully someone gives me an interpretation or hint. Thanks, in2sel : IN std_logic; in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; From newsfish@newsfish Thu Aug 1 00:35:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Wed, 21 Oct 2015 00:24:40 -0400 Organization: A noiseless patient Spider Lines: 70 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Wed, 21 Oct 2015 04:22:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="28271"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1993XNavo394jUCumdcss8w" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:ftjTYw6iNriSS1LwO4VRRoegYcg= Xref: news.eternal-september.org comp.lang.vhdl:4099 On 10/20/2015 4:46 PM, Rob Gaddi wrote: > On Tue, 20 Oct 2015 16:20:40 -0400, rickman wrote: > >> On 10/20/2015 12:58 PM, Mark Curry wrote: >>> In article , >>> glen herrmannsfeldt wrote: >>>> Tim McBrayer wrote: >>>>> On 10/20/2015 10:12 AM, fl wrote: >>>> >>>>>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no >>>>>> matter >>>>>> unsigned or signed number. When I try it with Modelsim, I find >>>>>> that it insists the result be 10-bit. Otherwise, it issues a >>>>>> warning. >>>> >>>>> Your 9-bit product assumption is the problem; 9 bits are not enough >>>>> to store 5 bits * 5 bits at full precision. It requires 10 bits. >>>> >>>>> Take the simplest example, multiplying two unsigned 5-bit numbers. >>>>> 2^5 has range 0 to 31. >>>> >>>>> Max value of multiplication: 31 * 31 = 961 >>>> >>>>> Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: >>>>> 2^10 - 1 = 1023 >>>> >>>>> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >>>> >>>> But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. >>> >>> Glen - huh? The (max negative) * (max negative) case does NOT fit in 9 >>> bits for signed either. >>> >>> (-16)*(-16) = 256 = 'b01_0000_0000 you need 10 bits - you need the sign >>> bit at the output too. >>> >>> Or I'm missing your point? >> >> Opps, I was thinking 1_0000_0000 would be a negative value, duh. Now I >> remember that this is the defining case for multiplication and requires >> the full 2n bits... just as Rob said. If your data is for any reason >> limited to ±(2^(n-1)-1) then one less bit is needed for the product. >> Such is the case if an unsigned value was negated to produce the signed >> value. >> >> I don't get his product notation becoming S2.8 rather than S1.9 though. >> If the range of the result is [-1,1) there is still only one bit left >> of the binary point, or am I wrong about that too, lol? > > Nope. The LSB in S1.4 was 2^-4 = 1/16. The LSB of the product, > therefore is 1/256, 2^-8. Likewise, as you pointed out, the > representation of +1 is 01.0000_0000b, i.e. 2^0. The representation of > -1 therefore is 11.0000_0000b, -(2^1) + 2^0 = -2 + 1 = -1. The total > representable range is [-2,2), but if you get there from the product of > two S1.4 numbers on [-1,1) then you've got a number that is S2.8 [-1,1]. > So the number is, by virtue of what it actually represents, not capable > of using the entire range representable by its format. > > That S/U notation, and actually carrying along explicit ranging > information, is why I can write fixed-point code that is right the first > time these days. God knows I didn't get any smarter, I just started > using a notation that is so explicit and bloody stupid that it shouts > your mistakes from the rafters. Ok, thanks. This was a useful example. I guess I haven't actually used this sort of calculation before. -- Rick From newsfish@newsfish Thu Aug 1 00:35:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Wed, 21 Oct 2015 00:30:08 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 21 Oct 2015 04:28:01 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="29526"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wv9R3YkRCW0x09AUI7r99" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:s5ggzZ9+B3KmVGM2j2EKI9qtXb4= Xref: news.eternal-september.org comp.lang.vhdl:4100 On 10/20/2015 5:49 AM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip on C as an HDL) > (then I wrote) > >>> I have thought that a tool that would compile a program to some >>> intermediate code, and also generate logic for an efficient >>> interpreter of that code, could be useful. > >>> That is, a soft processor optimized for the code at hand. > >> Perhaps, but how much better than just buying an already optimized hard >> IP processor like an ARM or an x86 of some flavor? Sure soft processors >> have uses, but the work involved in designing such a tool to >> automatically produce machine code and a processor from C code would be >> a lot more than can be justified I'd bet, but who knows? It may just be >> the lack of a perceived market. Maybe this would be a good university >> research project? > > I haven't looked in detail how the usual soft processors work. > > It wouldn't seem so hard to compile the C, see which instructions > the code actually used, then remove instructions from the soft > processor that weren't used. That should be much less work than > the synthesis tools themselves. Removing instructions from a processor usually doesn't accomplish much unless it is a big ugly brute maybe. Most of the logic in soft processors is data path and instruction fetch rather than instruction decode. So unless removing instructions allow you to reduce some part of the data path it doesn't accomplish a lot. At least that has been my experience. But then most of my work has been with processors of my own design with some examination of a few RISC CPUs like MicroBlaze and LatticeMico32. My designs were all stack processors which were intended to minimize the logic used as a primary goal. -- Rick From newsfish@newsfish Thu Aug 1 00:35:12 2024 X-Received: by 10.129.134.129 with SMTP id w123mr5987618ywf.17.1445404922760; Tue, 20 Oct 2015 22:22:02 -0700 (PDT) X-Received: by 10.50.124.69 with SMTP id mg5mr422188igb.10.1445404922724; Tue, 20 Oct 2015 22:22:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!kq10no20534681igb.0!news-out.google.com!z4ni27311ign.0!nntp.google.com!kq10no24380093igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 22:22:02 -0700 (PDT) In-Reply-To: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.23.60.4; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 185.23.60.4 References: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Could you explain this 'assert' description? From: bknpk@hotmail.com Injection-Date: Wed, 21 Oct 2015 05:22:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2472 X-Received-Body-CRC: 3257491668 Xref: news.eternal-september.org comp.lang.vhdl:4101 On Wednesday, September 30, 2015 at 3:20:42 AM UTC+3, fl wrote: > Hi, > > I learn 'assert' on this link: > > > > http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html > > > I don't understand what this passage talks about: > > "If the message clause is ommited, a default message is output. The severity > level and the name of the design unit containing the relevant assert > statement may also be output" > > > For this example line: > > assert not OVERFLOW) report "Accumulator overflowed" severity failure; > > > "If the message clause is ommited" means remove "report "Accumulator > overflowed" severity failure;"? > > > What is your opinion on this? > > Thanks, The assert statement of VHDL, can be used for simulation stop. This can be in a simple case like just a normal simulation end or a fatal error detection, by the verification test-bench. 2.If the simulation is let run after a fatal error occurs, the debug time may become longer in order to isolate the exact point of failure. While this is obvious, in some cases this rule is ignored. Typical example follows. 3.The simulation stop is done using the VHDL assert statement. examples are at http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_stop_on_error.html http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_test_ctrl_process.html From newsfish@newsfish Thu Aug 1 00:35:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question about std_logic variable compared with '0' Date: Wed, 21 Oct 2015 01:26:37 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 21 Oct 2015 05:24:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="5169"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18SnYwtLG6aOp8Tt7Ev2E1P" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:Jmdq6mh4Wk1KbOZilcXnKCEna3s= Xref: news.eternal-september.org comp.lang.vhdl:4102 On 10/20/2015 10:38 PM, fl wrote: > Hi, > > I never took a VHDL class, although I read a book for some time. Recently I > have some progress. Some conceptual questions pop up occasionally. I find > understanding these questions help me writing good code. 'in2sel' is the > entity input port. I am curious about ( in2sel > '0' ). I guess in2sel should > be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-determined > order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' mean? > i.e. the comparing is on what category? Is it an integer subtype? Or something > else? I don't find the solution after a web search. Hopefully someone gives > me an interpretation or hint. > > > Thanks, > > > in2sel : IN std_logic; > > in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; In VHDL the operator > is an arithmetic comparison. This sort of comparison is not defined for std_logic that I am aware of. If you mean comparisons such as arithmetic > for std_logic_vector (which would be "000" rather than '0') there are definitions of the > operation on this data type. You can assign the std_logic_vector to a signed or unsigned type defined in the NUMERIC_STD library. This will let you do the arithmetic comparison on the signed or unsigned value. Or you can use the new VHDL-2008 standard arithmetic package, IEEE.Numeric_Std_Unsigned. I have not used it myself, but I believe it defines unsigned arithmetic for std_logic_vector types. I see some mention of a similar library, IEEE.Numeric_Std_signed, but some pages say there is only the unsigned library. If you really want the std_logic type, you can convert the many values of std_logic to a 1 or 0 using to_01(). Then you can just use the equality comparison which *is* defined for std_logic as the returned value will be either a 1 or a 0 always. But this still may not be what you want if the input is a 'W', 'X', 'Z', '-' or 'U'. You can also define your own comparison or conversion operators. -- Rick From newsfish@newsfish Thu Aug 1 00:35:13 2024 X-Received: by 10.68.131.193 with SMTP id oo1mr6721470pbb.6.1445417694602; Wed, 21 Oct 2015 01:54:54 -0700 (PDT) X-Received: by 10.50.103.69 with SMTP id fu5mr187274igb.5.1445417694567; Wed, 21 Oct 2015 01:54:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no20599493igb.0!news-out.google.com!z4ni27442ign.0!nntp.google.com!kq10no20599489igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Oct 2015 01:54:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question about std_logic variable compared with '0' From: Thomas Stanka Injection-Date: Wed, 21 Oct 2015 08:54:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4103 Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl: > in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today. In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition. TYPE color IS (red, green, yellow); -- yellow>green>red There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic. From newsfish@newsfish Thu Aug 1 00:35:13 2024 X-Received: by 10.68.138.233 with SMTP id qt9mr6958711pbb.11.1445423236833; Wed, 21 Oct 2015 03:27:16 -0700 (PDT) X-Received: by 10.50.6.40 with SMTP id x8mr109590igx.0.1445423236802; Wed, 21 Oct 2015 03:27:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no24559125igb.0!news-out.google.com!z4ni27526ign.0!nntp.google.com!kq10no24559114igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Oct 2015 03:27:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.117.144; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.117.144 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question about std_logic variable compared with '0' From: fl Injection-Date: Wed, 21 Oct 2015 10:27:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4104 On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote: > Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl: > > > in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; > > Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today. > > In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition. > > TYPE color IS (red, green, yellow); -- yellow>green>red > > There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic. The code in my original post is generated from Matlab. I rewrite it in a simplest VHDL module using it with a test bench. There is no compiling error either. This kind of module generally is inside of (called from) other module. With your replies, the comparison is on the enumerated type of std_logic, which is in the IEEE package. Can we think it has been determined i.e. a consistent result will always be got? Use to_01() should work, though a little extra code. It should have a simple way for such a situation. From newsfish@newsfish Thu Aug 1 00:35:14 2024 X-Received: by 10.66.144.164 with SMTP id sn4mr7905706pab.9.1445432648634; Wed, 21 Oct 2015 06:04:08 -0700 (PDT) X-Received: by 10.50.61.132 with SMTP id p4mr215506igr.1.1445432648599; Wed, 21 Oct 2015 06:04:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no20709110igb.0!news-out.google.com!z4ni27629ign.0!nntp.google.com!kq10no24663084igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Oct 2015 06:04:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51ff883e-95c2-4ce7-8074-3233c1b4a648@googlegroups.com> Subject: Re: Question about std_logic variable compared with '0' From: KJ Injection-Date: Wed, 21 Oct 2015 13:04:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4105 On Tuesday, October 20, 2015 at 10:38:57 PM UTC-4, fl wrote: > 'in2sel' is the > entity input port. I am curious about ( in2sel > '0' ). I guess in2sel sh= ould > be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-deter= mined > order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' = mean? > i.e. the comparing is on what category? Is it an integer subtype? Or some= thing > else? I don't find the solution after a web search. Hopefully someone giv= es=20 > me an interpretation or hint. >=20 Since insel is type std_logic and std_logic is an enumeration type, the int= erpretation of > or < is whether the value is to the left or to the right = of the other value in the definition of the enumeration type list. The def= inition of std_ulogic is type STD_ULOGIC is ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance =20 'W', -- Weak Unknown 'L', -- Weak 0 =20 'H', -- Weak 1 =20 '-' -- Don't care ); Type std_logic is just the resolved subtype form of std_ulogic, so it will = have the same values as std_ulogic. The ordering of the literals that make= up the enumeration is from left to right so 'U' is to the left of 'X' (as = an example). An enumeration is considered 'greater' if it is to the right = of another so 'X' is considered to be greater than 'U' so the expression 'X= ' > 'U' returns the boolean value of True. Similarly, since '1' is to the = right of '0', an expression that boils down to '1' > '0' would result in th= e boolean value of True. In your case, you have "insel > '0'", so the foll= owing values for insel will all be true: '1', 'Z', 'W', 'L', 'H', '-'. There is no numeric interpretation of > or < going on here because the comp= arison is not between anything that has a numeric value. VHDL allows for e= numeration types to be defined and there are good use cases for where you w= ould like to evaluate to see if some signal is > or < some other signal or = constant that is also the same enumeration type. The code generated by Mat= lab would likely not be considered one of those 'good' use cases but rememb= er the Matlab program itself is a program, not a person. Probably a more c= learly written way to express that line of code would be the following. in2_im0 <=3D dmut_im WHEN ( in2sel =3D '1' ) ELSE dim_signed; Here the =3D is used rather than > and now suddenly there should be no conf= usion and yet =3D, > and < are all very familiar comparison operators. The= difference here is while it is easy to understand that =3D simply means th= e same, unless you what an enumeration type is, there may be confusion abou= t > or <. But that confusion probably does not exist if you ask yourself t= o compare strings so that they can be sorted (i.e. "def" > "abc"). Here yo= u're comparing strings and the 'greater' string would be sorted after the o= ther one. Now consider that strings are simply arrays of characters and VH= DL defines characters as an enumeration in package standard. type CHARACTER is ( NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,=20 BS, HT, LF, VT, FF, CR, SO, SI,=20 DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,=20 CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,=20 ... etc ... Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:14 2024 X-Received: by 10.182.215.226 with SMTP id ol2mr7804605obc.11.1445433055563; Wed, 21 Oct 2015 06:10:55 -0700 (PDT) X-Received: by 10.50.50.179 with SMTP id d19mr215486igo.7.1445433055543; Wed, 21 Oct 2015 06:10:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no24666377igb.0!news-out.google.com!z4ni27629ign.0!nntp.google.com!kq10no24666370igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Oct 2015 06:10:55 -0700 (PDT) In-Reply-To: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <27434335-4a96-473b-82e3-35cfc43fd58f@googlegroups.com> Subject: Re: Could you explain this 'assert' description? From: KJ Injection-Date: Wed, 21 Oct 2015 13:10:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4106 On Tuesday, September 29, 2015 at 8:20:42 PM UTC-4, fl wrote: > Hi, > > > I don't understand what this passage talks about: > > "If the message clause is ommited, a default message is output. The severity > level and the name of the design unit containing the relevant assert > statement may also be output" > The line of code in file D:/Projects/Test.vhd assert 1 < 0 severity ERROR; Will produce the following output in Modelsim # ** Error: Assertion violation. # Time: 0 ns Iteration: 0 Process: /tb_ulpi_link/line__252 File: D:/Projects/Test.vhd Kevin From newsfish@newsfish Thu Aug 1 00:35:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Wed, 21 Oct 2015 16:59:11 +0300 Organization: An impatient and LOUD arachnid Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain Injection-Info: mx02.eternal-september.org; posting-host="afd436d54299ec52d915a4a2551e1d6f"; logging-data="9936"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Ugod0itX+JJIu8yQl0G1y" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) Cancel-Lock: sha1:lMJFGzZ8392+kOHb2I+qHm7wrIk= sha1:pQ3SxJFecdEAXJFNM8JSViIIMgA= Xref: news.eternal-september.org comp.lang.vhdl:4107 comp.lang.verilog:1219 rickman writes: > I'm curious who here has learned both and why? Which do you prefer > and why? I learned some VHDL in school then went to work at telecoms company. There the old school POTS and related stuff was done in Verilog and the new fangled cellular radio stuff was in VHDL. I don't really know why. I worked with the POTS stuff first and used mostly Verilog and then later moved to the radio stuff but as the project manager didn't want to learn VHDL everyone in my team used Verilog. By that time simulation and synthesis tools didn't care so it was no problem to do mixed language. After that job, which ended in 2002, it's been pretty exlusively VHDL for me. European thing I suppose. One IP company I consulted at even went so far as to have us write code in VHDL which they would then put through a Verilog converter before shipping to customers in Asia or somewhere who wanted Verilog. I don't really have a preference between either but... As a fresh graduate I liked the simplicity and freedom of Verilog (and C) and really didn't like the bewildering mess of types in VHDL and the required type conversions. Or the seeming need to write things in triplicate (entity, component, instance). Thankfully there's direct instantiation which eliminates the need for components and then the Emacs VHDL mode makes instantiating and declaring signals a snap. As I've gotten older I've come to like Python quite a lot and these days I really like strong typing and explicit type conversions. I also maintain some old code and now scoff at the use of std_arith to do arithmetic on std_logic_vectors. Now the way of thinking that goes like "anything, even binary literals to avoid having to call type conversions" just seems stupid. Then again, readability is in the eye of the beholder. I was just reminded of this the other week... Well, the state of support for VHDL 2008 is a constant annoyance. I work on Altera parts without access to a third party synthesis tool and Quartus hasn't progressed at all with VHDL 2008 support in the last five years or so while Modelsim and Questa (which I do have access to) have. I think Xilinx Vivado is about the same? So the smaller guys (Lattice and Microsemi) are maybe offering better tools now since they bundle Synplify. If they still do, haven't checked. From newsfish@newsfish Thu Aug 1 00:35:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question about std_logic variable compared with '0' Date: Wed, 21 Oct 2015 16:10:29 -0400 Organization: A noiseless patient Spider Lines: 36 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 21 Oct 2015 20:08:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="6214"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18/7UjrTW5r5w1jqS9KSVmS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:/xPxVNNkVTKomCxa7NyNKC3P1hM= Xref: news.eternal-september.org comp.lang.vhdl:4108 On 10/21/2015 6:27 AM, fl wrote: > On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote: >> Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl: >> >>> in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; >> >> Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today. >> >> In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition. >> >> TYPE color IS (red, green, yellow); -- yellow>green>red >> >> There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic. > > The code in my original post is generated from Matlab. I rewrite it in a > simplest VHDL module using it with a test bench. There is no compiling error > either. This kind of module generally is inside of (called from) other > module. With your replies, the comparison is on the enumerated type of > std_logic, which is in the IEEE package. Can we think it has been determined > i.e. a consistent result will always be got? > > Use to_01() should work, though a little extra code. > > It should have a simple way for such a situation. If you are trying to work with synthesized code from Matlab, why do you care about the contents as long as it works? Or are you just trying to learn more about VHDL by studying this example (if a poor one). Clearly the code in2sel > '0' will work if they never allow the value of in2sel to be anything other than '1' or '0'. Even so, it is awkward code. It should have just been ins2sel = '1' instead. -- Rick From newsfish@newsfish Thu Aug 1 00:35:15 2024 X-Received: by 10.129.154.205 with SMTP id r196mr8557315ywg.48.1445500910950; Thu, 22 Oct 2015 01:01:50 -0700 (PDT) X-Received: by 10.50.33.73 with SMTP id p9mr249268igi.4.1445500910919; Thu, 22 Oct 2015 01:01:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m48no789645qgd.0!news-out.google.com!z4ni28421ign.0!nntp.google.com!kq10no21087416igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Oct 2015 01:01:50 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <080b9955-2b8b-45bd-b9b6-0417f400dfab@googlegroups.com> Subject: Re: Question about std_logic variable compared with '0' From: Thomas Stanka Injection-Date: Thu, 22 Oct 2015 08:01:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4109 Am Mittwoch, 21. Oktober 2015 12:27:20 UTC+2 schrieb fl: > On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote: > > > in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; > > > > Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today. > > The code in my original post is generated from Matlab. So kick it, its name is Matlab :). This code will most likely work well with some preconditions, but will not have the intended behavior when applying full range of std_logic => bad reuseability. Maybe Matlab will claim, that reuseability is not their business. As Rickman and KJ allready pointed out, the code would be functional and far better readable with using "=" for single bit compare function. On the plus side, you learned some new aspect of VHDL with this code line. bye Thomas From newsfish@newsfish Thu Aug 1 00:35:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 23 Oct 2015 02:48:36 -0500 From: aadi Subject: Re: creating program Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: ecfba588-526b-4469-aa16-60624fb6f261 References: Message-ID: Date: Fri, 23 Oct 2015 02:48:36 -0500 Lines: 82 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-njYFrX3oTVC7vlyS1mFqTUhQDaX8PBpK5VH1MJhq0pf1C0ymzVi+UbdbWe15LOZIHdkxkD6XsoIvEKp!DRywJylL5o3xpKRTNk6x9Yup1lCKjjt7qlwSKqsBMgQYPkND4kQwYefqwr/Y/Ha3WMZLT1ge0m9d!7Gc= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4181 Xref: news.eternal-september.org comp.lang.vhdl:4110 Thanks Kevin for your comment. Well here is my code its running only for one round but my mentor told me to change it into a behavioural code and not to use for loop. key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 10 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 11 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 12 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 13 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 14 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 15 => if (decipher = '1') then key_l(0 to 27) <= key_l(27) & key_l(0 to 26); key_r(0 to 27) <= key_r(27) & key_r(0 to 26); else key_l(0 to 27) <= key_l(1 to 27) & key_l(0); key_r(0 to 27) <= key_r(1 to 27) & key_r(0); end if; when others => end case; end if; end process Key; cntrl: process (clk, dirtn) variable count : integer range 0 to 15:=0; begin if (rising_edge(clk) and clk='1') then if decipher = '0' then if (dirtn='1') then count:= count+ 1; counter<=count; else if decipher = '1' then count:= count- 1; counter<=count; end if; end if; end if; end if; end process cntrl; end behavioural; From newsfish@newsfish Thu Aug 1 00:35:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Re: Why VHDL? Date: Tue, 27 Oct 2015 17:06:17 -0400 Organization: A noiseless patient Spider Lines: 89 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 27 Oct 2015 21:04:09 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="3887"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190ROz50XWy0HBSSge8iPui" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:GHQ3JTq/8cYfKuogQvu0Vg3/aCI= Xref: news.eternal-september.org comp.lang.verilog:1231 comp.lang.vhdl:4111 On 10/27/2015 3:21 PM, Mark Curry wrote: > In article , rickman wrote: >> On 10/27/2015 12:26 PM, Mark Curry wrote: >>> In article , Anssi Saari wrote: >>>> Kevin Neilson writes: >>>> >>>>> I wish somebody would write a comprehensive guide to conversions in >>>>> VHDL. I had one once but lost it. >>>> >>>> There's the 2003 PDF by Jim Lewis of Synthworks titled "VHDL Math Tricks >>>> of the Trade" >>>> (http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf) which >>>> is pretty good. It covers both the old std_arith stuff and current >>>> numeric_std stuff. >>>> >>>> For a quick reference, there're lots of images floating around that >>>> cover the common conversions. Like this one: >>>> http://www.bitweenie.com/wp-content/uploads/2013/02/vhdl-type-conversions.png >>>> >>>>> Every time I write something in that infernal language I can't >>>>> remember how to convert unsigned into integer or whatever. Sometimes >>>>> it takes a double conversion. >>>> >>>> I dunno, it seems to me to_integer and to_unsigned are pretty easy to >>>> remember. >>> >>> Anssi - Thanks very much for the links. >>> >>> I think todays designers must be able to work with either VHDL or Verilog. >>> These language wars are over. >>> > > >> In my "book" anyone who discusses std_logic_arith is so far out of date >> they don't deserve serious respect. There literally is *no* reason to >> learn anything about std_logic_arith and its kin unless you are trying >> to maintain code so old the processes used to implement it are no longer >> around. >> >> The reasons to avoid std_logic_arith are many and well known. This is > > Noted - but as a verilog user, I don't know what those reasons are. > I do trust you, and other VHDL experts and will certainly follow > the suggestions. Like I said, I remembered there was a > strong suggestion to NOT use one of them. I'll try and > cement that in my head "don't use std_logic_arith"... To be honest, it has been so long that I don't remember all of the reasons. One that I recall is that with these packages you can't use signed and unsigned at the same time. These packages don't define new types, they define operators for SLV to implement signed or unsigned arithmetic. Adding both signed and unsigned packages gives you multiple operators for the same data types... which do you get? I know there are other issues with them as well, so they are best forgotten. In addition to numeric_std, there are new packages for signed and unsigned arithmetic on SLV, (std_logic_signed and std_logic_unsigned). These new packages will have the same issue of not working together since they define the same operator on the same types, but otherwise will work ok. I just use signed and unsigned types from the std_numeric library. Life is good. >> the sort of info I'd like to have on Verilog. I understand there are >> default rules of how many thing operate in Verilog, but they are hard to >> find out about. That is what I would like in a Verilog book. > > As a verilog user, it's all obvious to me :) > Actually, if I had a suggestion, it just be Cliff's oldy but goody: > http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf > > It's still relevant today, IMHO. Not sure if this is what you're > looking for, but it's golden. > > Cliff's got many other great papers up on his website. I've seen some of this before. I was mostly referring to the issues of arithmetic. I believe Verilog has defaults for how the various details of bit growth etc are handled. If you aren't aware of what is happening you can have invisible trouble. In VHDL you have *very* visible trouble for nearly anything you do wrong. lol Crossposting to the VHDL group since this is as much about that as Verilog. -- Rick From newsfish@newsfish Thu Aug 1 00:35:16 2024 X-Received: by 10.107.47.219 with SMTP id v88mr29027816iov.25.1446023441540; Wed, 28 Oct 2015 02:10:41 -0700 (PDT) X-Received: by 10.50.8.68 with SMTP id p4mr35001iga.8.1446023441524; Wed, 28 Oct 2015 02:10:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no31135618igb.0!news-out.google.com!fs1ni785igb.0!nntp.google.com!kq10no31135615igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Oct 2015 02:10:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9febdcc3-0775-43ab-8f40-8f84669c398e@googlegroups.com> Subject: Re: Why VHDL? From: Thomas Stanka Injection-Date: Wed, 28 Oct 2015 09:10:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4112 Am Dienstag, 27. Oktober 2015 22:06:23 UTC+1 schrieb rickman: > On 10/27/2015 3:21 PM, Mark Curry wrote: > To be honest, it has been so long that I don't remember all of the=20 > reasons. =20 [..] > I know there are other issues with them as well, so they are best=20 > forgotten. The major issue with std_logic_arith and similar (std_logic_unsigned,...) i= s that they are NOT standardized. They are tool dependend (original from Sy= nopsys) and from LRM point of view illegal extensions to libray IEEE, as th= is library shall contain only standarized packages. If simulation and synthesis result for these packages differ, you have nobo= dy to complain about (beside the code autor, who dares to use non standard)= . > In addition to numeric_std, there are new packages for signed and=20 > unsigned arithmetic on SLV, (std_logic_signed and std_logic_unsigned).=20 > These new packages will have the same issue of not working together=20 > since they define the same operator on the same types, but otherwise=20 > will work ok. I just use signed and unsigned types from the std_numeric= =20 > library. Life is good. Std_logic_unsigned and std_logic_signed are not "new packages" compared to = numeric_std, they are extensions from Synopsys for the std_logic_arith and= usually used in combination with arith with similar issues than arith alon= e.=20 regards, Thomas From newsfish@newsfish Thu Aug 1 00:35:16 2024 X-Received: by 10.31.148.206 with SMTP id w197mr38986731vkd.9.1446033993342; Wed, 28 Oct 2015 05:06:33 -0700 (PDT) X-Received: by 10.50.142.66 with SMTP id ru2mr57851igb.3.1446033993268; Wed, 28 Oct 2015 05:06:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!c107no2912759qgd.1!news-out.google.com!fs1ni883igb.0!nntp.google.com!i2no22141igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Oct 2015 05:06:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.113.175.178; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 80.113.175.178 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Wed, 28 Oct 2015 12:06:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1539 X-Received-Body-CRC: 3053702156 Xref: news.eternal-september.org comp.lang.vhdl:4113 Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi: > i have learned every aspect of VHDL but i still can't exersise it to make complex program. It's VHDL, not C or Java. VHDL is a description, not a program. > i need a code for data encryption standard and also for key generation. but i can't get a single way to do so What is the question ? The're plenty of open sources VHDL examples available, lots of them on opencores. Igmar From newsfish@newsfish Thu Aug 1 00:35:17 2024 X-Received: by 10.13.248.68 with SMTP id i65mr25908346ywf.39.1446042250261; Wed, 28 Oct 2015 07:24:10 -0700 (PDT) X-Received: by 10.50.57.17 with SMTP id e17mr86189igq.2.1446042250178; Wed, 28 Oct 2015 07:24:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!c107no2937693qgd.1!news-out.google.com!fs1ni1009igb.0!nntp.google.com!i2no83624igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Oct 2015 07:24:09 -0700 (PDT) In-Reply-To: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.4.178.90; posting-account=kidwfQoAAAAfI20wQGXIy9JZVTNSnVqm NNTP-Posting-Host: 108.4.178.90 References: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <50c49191-139f-4b9f-96c4-6b429235ee1b@googlegroups.com> Subject: Re: [GHDL] Solution to --> primary unit "std_logic_arith" not found in library "ieee" From: elkniwt@gmail.com Injection-Date: Wed, 28 Oct 2015 14:24:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4114 On Friday, September 13, 2013 at 11:38:51 AM UTC-4, Christiano wrote: > If anyone has had this problem, just do this: > ghdl -a --ieee=synopsys x.vhd Thanks, this helped me out with some source over which I have no control. From newsfish@newsfish Thu Aug 1 00:35:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Wed, 28 Oct 2015 12:29:32 -0400 Organization: A noiseless patient Spider Lines: 23 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 Oct 2015 16:27:23 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="7631"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/lRE6lXqcLIEVE8ZHmMsIu" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> Cancel-Lock: sha1:dAhJj+sFj+f17lDvKvyzeS/aO6U= Xref: news.eternal-september.org comp.lang.vhdl:4115 On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: > Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi: >> i have learned every aspect of VHDL but i still can't exersise it to make complex program. > > It's VHDL, not C or Java. VHDL is a description, not a program. That's not very fair. VHDL is used to describe hardware, but it is a perfectly good programming language too. That is how we use it for test benches. >> i need a code for data encryption standard and also for key generation. but i can't get a single way to do so > > What is the question ? The're plenty of open sources VHDL examples available, lots of them on opencores. > > > Igmar > -- Rick From newsfish@newsfish Thu Aug 1 00:35:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [GHDL] Solution to --> primary unit "std_logic_arith" not found in library "ieee" Date: Wed, 28 Oct 2015 12:33:38 -0400 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 Oct 2015 16:31:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="10154"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/9Sb98L3oEX4ARymWM3HnD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Cancel-Lock: sha1:nY6lx7dafpoaHIVF7BP6M97nSNk= Xref: news.eternal-september.org comp.lang.vhdl:4116 On 9/13/2013 11:38 AM, Christiano wrote: > If anyone has had this problem, just do this: > ghdl -a --ieee=synopsys x.vhd Better yet, use numeric_std rather than std_logic_arith. I did a little digging and found that because std_logic_arith was not a standard, each vendor produced their own, different, version. That is reason enough to not use it. -- Rick From newsfish@newsfish Thu Aug 1 00:35:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Wed, 28 Oct 2015 22:39:51 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 28 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4117 rickman wrote: > On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: (snip on VHDL and programs) >> It's VHDL, not C or Java. VHDL is a description, not a program. > That's not very fair. VHDL is used to describe hardware, but it is a > perfectly good programming language too. That is how we use it for test > benches. I think I also don't like the use of the word 'program' even in the case of test benches. To me, program has too much implication of sequential execution (even in the case of parallel programming) that I think some other word should be used. I might use design, which I think works in the case of hardware and test benches, which both need to be designed, if not described. Though test benches could also be described, even if they aren't hardware. (But the idea of a test bench comes from the days when they were hardware, even furniture.) -- glen From newsfish@newsfish Thu Aug 1 00:35:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why VHDL? Date: Thu, 29 Oct 2015 01:26:29 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <9febdcc3-0775-43ab-8f40-8f84669c398e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 29 Oct 2015 05:24:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="31030"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GNpPLg9JghNum8m3dJUqW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <9febdcc3-0775-43ab-8f40-8f84669c398e@googlegroups.com> Cancel-Lock: sha1:IpxXgbJ55r22Xl+PNxZpPI9Nxms= Xref: news.eternal-september.org comp.lang.vhdl:4118 On 10/28/2015 5:10 AM, Thomas Stanka wrote: > Am Dienstag, 27. Oktober 2015 22:06:23 UTC+1 schrieb rickman: >> On 10/27/2015 3:21 PM, Mark Curry wrote: To be honest, it has been >> so long that I don't remember all of the reasons. > [..] >> I know there are other issues with them as well, so they are best >> forgotten. > > The major issue with std_logic_arith and similar > (std_logic_unsigned,...) is that they are NOT standardized. They are > tool dependend (original from Synopsys) and from LRM point of view > illegal extensions to libray IEEE, as this library shall contain only > standarized packages. If simulation and synthesis result for these > packages differ, you have nobody to complain about (beside the code > autor, who dares to use non standard). > >> In addition to numeric_std, there are new packages for signed and >> unsigned arithmetic on SLV, (std_logic_signed and >> std_logic_unsigned). These new packages will have the same issue of >> not working together since they define the same operator on the >> same types, but otherwise will work ok. I just use signed and >> unsigned types from the std_numeric library. Life is good. > > Std_logic_unsigned and std_logic_signed are not "new packages" > compared to numeric_std, they are extensions from Synopsys for the > std_logic_arith and usually used in combination with arith with > similar issues than arith alone. Yes, sorry, I got my names mixed up. I meant to say "numeric_std_unsigned and numeric_std_signed". I'm actually not sure how widely these are supported. I only find 1600 hits on a google search for numeric_std_unsigned and only about 100 for numeric_std_signed. But I find them both mentioned as part of VHDL-2008 at the Doulos site, so I figure they know what they are talking about... maybe. -- Rick From newsfish@newsfish Thu Aug 1 00:35:18 2024 X-Received: by 10.50.134.199 with SMTP id pm7mr6805687igb.0.1446121754704; Thu, 29 Oct 2015 05:29:14 -0700 (PDT) X-Received: by 10.50.67.179 with SMTP id o19mr58721igt.3.1446121754648; Thu, 29 Oct 2015 05:29:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no563895igv.0!news-out.google.com!z4ni39791ign.0!nntp.google.com!i2no389869igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 Oct 2015 05:29:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=39.32.8.43; posting-account=272ktwoAAAA5_lGBEoh_tKUi3Dy5L9Ix NNTP-Posting-Host: 39.32.8.43 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Verilog programing query From: mahmedqureshi.maq@gmail.com Injection-Date: Thu, 29 Oct 2015 12:29:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4119 I am new to verilog programming. I have a assignment in which we are asked to make a 32 bit, 64 deep register file and store in it a set of 32 bit instructions. However, these instruction are going to be instantiated in the test bench and not in the module. I have so far been unable to store these instructions in my register. Any ideas about how i may solve this problem? Thanks From newsfish@newsfish Thu Aug 1 00:35:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Verilog programing query Date: Thu, 29 Oct 2015 12:36:16 -0400 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 29 Oct 2015 16:34:05 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="7839"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/mgp78DxDLMas7JSF8kADw" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:7+VLVomG7u3jZPtHDQ31HzjGEzE= Xref: news.eternal-september.org comp.lang.vhdl:4120 On 10/29/2015 8:29 AM, mahmedqureshi.maq@gmail.com wrote: > I am new to verilog programming. I have a assignment in which we are asked to make a 32 bit, 64 deep register file and store in it a set of 32 bit instructions. > However, these instruction are going to be instantiated in the test bench and not in the module. I have so far been unable to store these instructions in my register. Any ideas about how i may solve this problem? > Thanks I'm not sure why you are asking how to write Verilog code in a VHDL group. But to answer your question I suspect your professor wants you to use arrays to implement the register file. Then you simply need to initialize them to the instruction values. -- Rick From newsfish@newsfish Thu Aug 1 00:35:19 2024 X-Received: by 10.107.136.19 with SMTP id k19mr11661951iod.5.1446297413849; Sat, 31 Oct 2015 06:16:53 -0700 (PDT) X-Received: by 10.50.33.73 with SMTP id p9mr59963igi.4.1446297413828; Sat, 31 Oct 2015 06:16:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!i2no1659285igv.0!news-out.google.com!fs1ni3917igb.0!nntp.google.com!i2no1149318igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 31 Oct 2015 06:16:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Sat, 31 Oct 2015 13:16:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 14 X-Received-Bytes: 1906 X-Received-Body-CRC: 576785471 Xref: news.eternal-september.org comp.lang.vhdl:4121 Op woensdag 28 oktober 2015 17:29:38 UTC+1 schreef rickman: > On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: > > Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi: > >> i have learned every aspect of VHDL but i still can't exersise it to make complex program. > > > > It's VHDL, not C or Java. VHDL is a description, not a program. > > That's not very fair. VHDL is used to describe hardware, but it is a > perfectly good programming language too. That is how we use it for test > benches. That's not it's primary goal. That the language allows it, sure, but that doesn't mean it's build for that. Doing C or VHDL requires a totally different mindset. Igmar From newsfish@newsfish Thu Aug 1 00:35:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Sun, 1 Nov 2015 02:19:30 -0500 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 1 Nov 2015 07:17:19 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c9f1f81c5b43c89873758a99614bbf4a"; logging-data="26980"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/qxPnIzbbMlJA6OBX/cJDq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:N/YYQKs0Lf9uLP7BcfJ2LV6onG8= Xref: news.eternal-september.org comp.lang.vhdl:4122 On 10/28/2015 6:39 PM, glen herrmannsfeldt wrote: > rickman wrote: >> On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: > > (snip on VHDL and programs) > >>> It's VHDL, not C or Java. VHDL is a description, not a program. > >> That's not very fair. VHDL is used to describe hardware, but it is a >> perfectly good programming language too. That is how we use it for test >> benches. > > I think I also don't like the use of the word 'program' even in > the case of test benches. > > To me, program has too much implication of sequential execution > (even in the case of parallel programming) that I think some other > word should be used. > > I might use design, which I think works in the case of hardware > and test benches, which both need to be designed, if not described. > > Though test benches could also be described, even if they aren't > hardware. > > (But the idea of a test bench comes from the days when they were > hardware, even furniture.) I just call it "code". -- Rick From newsfish@newsfish Thu Aug 1 00:35:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Sun, 1 Nov 2015 02:27:27 -0500 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 1 Nov 2015 07:25:16 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c9f1f81c5b43c89873758a99614bbf4a"; logging-data="28714"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wvFg9zIB8VHkEj2FEX5Ew" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Cancel-Lock: sha1:8dwa5dE3rtq9++NeAmrvOD4WZt0= Xref: news.eternal-september.org comp.lang.vhdl:4123 On 10/31/2015 9:16 AM, Igmar Palsenberg wrote: > Op woensdag 28 oktober 2015 17:29:38 UTC+1 schreef rickman: >> On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: >>> Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi: >>>> i have learned every aspect of VHDL but i still can't exersise it to make complex program. >>> >>> It's VHDL, not C or Java. VHDL is a description, not a program. >> >> That's not very fair. VHDL is used to describe hardware, but it is a >> perfectly good programming language too. That is how we use it for test >> benches. > > That's not it's primary goal. That the language allows it, sure, but that doesn't mean it's build for that. Doing C or VHDL requires a totally different mindset. I think your distinction is pointless. You said "VHDL is a description, not a program" and I have you an example when this is not true. End of discussion for me. As to the "mindset", there was a software designer who wanted to code an FPGA in VHDL and came here asking for advice. We told him about how he needed to adjust his thinking to design hardware and not code software. I wrote to him personally to explain why this was important and came close to getting some consulting time with his firm. In the end his bosses had faith that he could do a good job and so he wrote the code himself, without any trouble. I learned that although I was a hardware person who was able to more easily think about the hardware I was designing as gates and register, this is *not* required, rather you *can* write VHDL as a sequential language as long as you understand the various processes were all in parallel. Parallel processes are not unique to hardware. The really funny part was that the guy talked his bosses into sending me a small check for the time I spent helping him while I insisted that was just the cost of marketing for me and it was not needed. Not very often I tell customers to *not* pay me. Lol -- Rick From newsfish@newsfish Thu Aug 1 00:35:20 2024 X-Received: by 10.107.12.88 with SMTP id w85mr21401308ioi.32.1446497924380; Mon, 02 Nov 2015 12:58:44 -0800 (PST) X-Received: by 10.50.8.68 with SMTP id p4mr247505iga.8.1446497924363; Mon, 02 Nov 2015 12:58:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no1801656igv.0!news-out.google.com!fs1ni6065igb.0!nntp.google.com!i2no1801645igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Nov 2015 12:58:43 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Andy Injection-Date: Mon, 02 Nov 2015 20:58:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4124 Any coder worth his salt must know his/her compiler, be it C or VHDL. For HDLs, that typically means we need to know 2 different compilers (simulator and synthesis tools). Even in purely sequential languages, the best compilers optimize the object code for the processor's inherent parallel execution capabilities based on dependencies, the same as a VHDL synthesis tool does for sequential code in processes and subprograms. I agree that there are times (e.g. synchronization boundaries) where we need to code very close to the HW we need. But at other times, coding for behavior (think throughput and clock cycles of latency) rather than HW (think gates and registers), solves more problems (will the HW behave the way we want?) Otherwise, we leave 90% of the synthesis tool's capability on the table (we do its job for it by darn near coding a netlist). Andy From newsfish@newsfish Thu Aug 1 00:35:20 2024 X-Received: by 10.13.223.72 with SMTP id i69mr26341467ywe.28.1446618203255; Tue, 03 Nov 2015 22:23:23 -0800 (PST) X-Received: by 10.50.77.70 with SMTP id q6mr461246igw.4.1446618203230; Tue, 03 Nov 2015 22:23:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!c107no4842152qgd.1!news-out.google.com!z4ni45809ign.0!nntp.google.com!i2no2745750igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Nov 2015 22:23:22 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1163446a-15b6-41a4-845d-8bd141f7a5dd@googlegroups.com> Subject: Re: creating program From: goouse99@gmail.com Injection-Date: Wed, 04 Nov 2015 06:23:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 104 Xref: news.eternal-september.org comp.lang.vhdl:4125 Am Freitag, 23. Oktober 2015 09:48:40 UTC+2 schrieb aadi: > Thanks Kevin for your comment. > Well here is my code its running only for one round but my mentor told me to change it into a behavioural code and not to use for loop. > > > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 10 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 11 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 12 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 13 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 14 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 15 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(27) & key_l(0 to 26); > key_r(0 to 27) <= key_r(27) & key_r(0 to 26); > else > key_l(0 to 27) <= key_l(1 to 27) & key_l(0); > key_r(0 to 27) <= key_r(1 to 27) & key_r(0); > end if; > when others => > end case; > end if; > > end process Key; > > cntrl: process (clk, dirtn) > variable count : integer range 0 to 15:=0; > begin > > if (rising_edge(clk) and clk='1') then > if decipher = '0' then > if (dirtn='1') then > count:= count+ 1; > counter<=count; > else > if decipher = '1' then > count:= count- 1; > counter<=count; > end if; > end if; > end if; > end if; > end process cntrl; > end behavioural; Hi, just some hint for the case selection: If you have a number of when branches with identical statements you can combine them into one branch: e.g.: when 10 to 14 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; Nonsequential selection values can be grouped using an or symbol: like this: when 2 | 5 | 17 => -- do something look here for more details: http://vhdl.renerta.com/mobile/source/vhd00014.htm Have a nice synthesis Eilert From newsfish@newsfish Thu Aug 1 00:35:21 2024 X-Received: by 10.66.160.165 with SMTP id xl5mr5296813pab.33.1446620618718; Tue, 03 Nov 2015 23:03:38 -0800 (PST) X-Received: by 10.50.33.73 with SMTP id p9mr22143igi.4.1446620618647; Tue, 03 Nov 2015 23:03:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no2752020igv.0!news-out.google.com!z4ni45867ign.0!nntp.google.com!i2no2752012igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Nov 2015 23:03:38 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.101.18.209; posting-account=M-xIwgoAAABy7eXiPM8pdSh8Pv2NZhsR NNTP-Posting-Host: 46.101.18.209 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Low Cost FPGA Development Board: From: posedgegroup@gmail.com Injection-Date: Wed, 04 Nov 2015 07:03:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4126 Low Cost FPGA Development Board: Posedge-One FPGA Develop Board 3D view: http://posedge.ir/upload/posedgeOne3D.pdf features: - Xilinx Spartan6-LX9 - USB On-Board Programer (Full support with Xilinx softwares) - 4 Mb SRAM - USB 2.0 (Speed: 10 MB/s) - 64 Mbit Flash memory - 48 I/O - 24 MHz Oscillator Hardware guide: http://posedge.ir/posedgeone_hardware_guide/ From newsfish@newsfish Thu Aug 1 00:35:21 2024 X-Received: by 10.66.192.234 with SMTP id hj10mr1946993pac.28.1446654291759; Wed, 04 Nov 2015 08:24:51 -0800 (PST) X-Received: by 10.50.25.131 with SMTP id c3mr113486igg.6.1446654291724; Wed, 04 Nov 2015 08:24:51 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no4107381igv.0!news-out.google.com!z4ni46377ign.0!nntp.google.com!i2no4107370igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Nov 2015 08:24:51 -0800 (PST) In-Reply-To: <1163446a-15b6-41a4-845d-8bd141f7a5dd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <1163446a-15b6-41a4-845d-8bd141f7a5dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Andy Injection-Date: Wed, 04 Nov 2015 16:24:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4127 Excellent suggestion. You can define an integer subtype with the appropriate range (and a descriptive name) to use in the choice expression, or to select a slice of an array. I use an "_range" suffix on such subtype names. subtype active_range is integer range 10 to 14; ... when active_range => ... "downto" direction also works for case choice expressions. It must match the array index direction when used to index an array. subtype status_range is integer range 7 downto 0; ... status := data_word(status_range); ... You can also use such a subtype in a loop indexing scheme: for i in status_range loop ... Andy From newsfish@newsfish Thu Aug 1 00:35:21 2024 X-Received: by 10.182.52.132 with SMTP id t4mr24581183obo.16.1447069847953; Mon, 09 Nov 2015 03:50:47 -0800 (PST) X-Received: by 10.50.6.40 with SMTP id x8mr487157igx.0.1447069847925; Mon, 09 Nov 2015 03:50:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no1092167igv.0!news-out.google.com!l1ni988igd.0!nntp.google.com!i2no1712511igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Nov 2015 03:50:47 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.113.175.178; posting-account=jBunWwoAAADJaACRgWrdsgmliB-LzsaC NNTP-Posting-Host: 80.113.175.178 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: igmar.palsenberg@boostermedia.com Injection-Date: Mon, 09 Nov 2015 11:50:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4128 On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote: > I think your distinction is pointless. You said "VHDL is a description, > not a program" and I have you an example when this is not true. End of > discussion for me. Fine. That doesn't mean you're right. > As to the "mindset", there was a software designer who wanted to code an > FPGA in VHDL and came here asking for advice. We told him about how he > needed to adjust his thinking to design hardware and not code software. > I wrote to him personally to explain why this was important and came > close to getting some consulting time with his firm. In the end his > bosses had faith that he could do a good job and so he wrote the code > himself, without any trouble. It's a whole different thing, assuming the end result ends up on a FPGA. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc. With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype. > I learned that although I was a hardware person who was able to more > easily think about the hardware I was designing as gates and register, > this is *not* required, rather you *can* write VHDL as a sequential > language as long as you understand the various processes were all in > parallel. Parallel processes are not unique to hardware. I doubt that still works for a *very* large design. On software, the OS handes a lot for you. No cache flushes, no memory barriers, etc. Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story. Igmar From newsfish@newsfish Thu Aug 1 00:35:22 2024 X-Received: by 10.13.204.19 with SMTP id o19mr139528ywd.7.1447124667319; Mon, 09 Nov 2015 19:04:27 -0800 (PST) X-Received: by 10.50.225.70 with SMTP id ri6mr582771igc.9.1447124667289; Mon, 09 Nov 2015 19:04:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f78no706096qge.1!news-out.google.com!l1ni1675igd.0!nntp.google.com!i2no2059320igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Nov 2015 19:04:26 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Tue, 10 Nov 2015 03:04:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4154 X-Received-Body-CRC: 404324227 Xref: news.eternal-september.org comp.lang.vhdl:4129 On Monday, November 9, 2015 at 5:50:51 AM UTC-6, igmar.pa...@boostermedia.c= om wrote: > It's a whole different thing, assuming the end result ends up on a FPGA. = Software is sequenced, around datastructures. VHDL is not sequenced, and do= esn't have thing software has : Lock issues, memory alignment issues, etc.= =20 >=20 Really? You think a modern SW compiler doesn't tweak your sequence to take = advantage of the processor's capabilities. Whether it's SW or HW: coder, kn= ow thy compiler!=20 And who says data structures are exclusive to SW? Oh, you mean they aren't = available in Verilog? Use a better language! > With software, you attach a debugger, and you can step through. With VHDL= , it's not that simple. So yes, I call this a different mindset. If you thi= nk like a software programmer, you'll sooner or later end up with a non-wor= king, hard to debug prototype. So you don't use the debugger to set breakpoints and step through complex R= TL? I guess maybe not if you code too close to the edif. Been developing FPGAs in VHDL like SW (enlightened by digital HW circuit de= sign experience) for 20+ years now. Have fewer problems than when I tried t= o code netlists, doing the synthesis tool's job for it. Sure it's not _exac= tly_ like SW, but many, many principles of SW development are highly applic= able to RTL. > I doubt that still works for a *very* large design. On software, the OS h= andes a lot for you. No cache flushes, no memory barriers, etc.=20 I would beg to differ. Very large designs are where SW approaches make the = most sense and benefit. The larger the design (and body of code), the harde= r it is to maintain if you don't think about it like SW. Cache flushes are not unique to SW. The OS is just more SW. So we need to w= rite a little more code to do that in RTL. >=20 > Can a programmer while VHDL code ? Sure. But there is a huge different be= tween good and "it works". Every monkey can write PHP code, but writing goo= d, maintainable code is a different story. Yes there is a difference between SW and HW, nobody is denying that. But I'= ve reviewed, maintained, and debugged too many RTL designs written too clos= e to the netlist level not to recognize the benefits of SW approach to RTL. You have to know where to pay attention to the HW (async clock boundaries a= re a big chunk). Then handle that close to the HW level, but encapsulate it= into a few reusable entities (like system calls to the OS in SW) and then = concentrate on the function, throughput and latency of the rest of the desi= gn. On a multi-person team, only one or two need to deal with the low level= stuff, the rest can design at a much higher level, where the behavior of t= he code is critical. Andy From newsfish@newsfish Thu Aug 1 00:35:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Tue, 10 Nov 2015 03:15:11 -0500 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 10 Nov 2015 08:12:54 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10912"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Mmtoj6jA7qKY9atDqS/4P" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:Kf2okAETBJ2DWGDhHdBcw7Ij7h0= Xref: news.eternal-september.org comp.lang.vhdl:4130 On 11/9/2015 6:50 AM, igmar.palsenberg@boostermedia.com wrote: > On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote: > >> I think your distinction is pointless. You said "VHDL is a description, >> not a program" and I have you an example when this is not true. End of >> discussion for me. > > Fine. That doesn't mean you're right. ??? You don't make sense. I give you an example of VHDL that is a program as used everyday and you reject that??? >> As to the "mindset", there was a software designer who wanted to code an >> FPGA in VHDL and came here asking for advice. We told him about how he >> needed to adjust his thinking to design hardware and not code software. >> I wrote to him personally to explain why this was important and came >> close to getting some consulting time with his firm. In the end his >> bosses had faith that he could do a good job and so he wrote the code >> himself, without any trouble. > > It's a whole different thing, assuming the end result ends up on a FPGA. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc. I don't think you understand VHDL. VHDL has sequential code, that is what a process it. > With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype. Huh??? I use single stepping with VHDL at times. Normally it isn't that useful because there is so much parallelism, things tend to jump around as one process stops and another starts... same as software on a processor with interrupts or multitasking. >> I learned that although I was a hardware person who was able to more >> easily think about the hardware I was designing as gates and register, >> this is *not* required, rather you *can* write VHDL as a sequential >> language as long as you understand the various processes were all in >> parallel. Parallel processes are not unique to hardware. > > I doubt that still works for a *very* large design. On software, the OS handes a lot for you. No cache flushes, no memory barriers, etc. > > Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story. I'm not sure what you are going on about. You started by saying "VHDL is a description, not a program." Now you seem to be splitting all manner of hairs and calling programmers "monkeys". Why don't we agree to disagree? -- Rick From newsfish@newsfish Thu Aug 1 00:35:22 2024 X-Received: by 10.31.147.149 with SMTP id v143mr1492775vkd.14.1447313801660; Wed, 11 Nov 2015 23:36:41 -0800 (PST) X-Received: by 10.50.3.41 with SMTP id 9mr844480igz.7.1447313801626; Wed, 11 Nov 2015 23:36:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f78no93366qge.1!news-out.google.com!l1ni1556igd.0!nntp.google.com!i2no660789igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Nov 2015 23:36:40 -0800 (PST) In-Reply-To: <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Thu, 12 Nov 2015 07:36:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4131 Op dinsdag 10 november 2015 04:04:31 UTC+1 schreef Andy: > On Monday, November 9, 2015 at 5:50:51 AM UTC-6, igmar.pa...@boostermedia= .com wrote: > > It's a whole different thing, assuming the end result ends up on a FPGA= . Software is sequenced, around datastructures. VHDL is not sequenced, and = doesn't have thing software has : Lock issues, memory alignment issues, etc= .=20 > >=20 > Really? You think a modern SW compiler doesn't tweak your sequence to tak= e advantage of the processor's capabilities. Whether it's SW or HW: coder, = know thy compiler!=20 Sure.=20 > And who says data structures are exclusive to SW? Oh, you mean they aren'= t > available in Verilog? Use a better language! Datastructures come at a price. In software the're cheap, in hardware the'r= e less cheap. I need to think harder in VHDL about the structure in general= . I find myself far less limited in software (which is also a potential pro= blem, if you ask me)=20 =20 > > With software, you attach a debugger, and you can step through. With VH= DL, it's not that simple. So yes, I call this a different mindset. If you t= hink like a software programmer, you'll sooner or later end up with a non-w= orking, hard to debug prototype. >=20 > So you don't use the debugger to set breakpoints and step through complex= RTL? I guess maybe not if you code too close to the edif. I did that on old Altera software. I failed at the latest version, still ne= ed to look into that. In IntelliJ, it just attach and it works (c). > Been developing FPGAs in VHDL like SW (enlightened by digital HW circuit = design experience) for 20+ years now. Have fewer problems than when I tried= to code netlists, doing the synthesis tool's job for it. Sure it's not _ex= actly_ like SW, but many, many principles of SW development are highly appl= icable to RTL. True. I have 20+ in software, not in hardware. Getting up-to-speed on VHDL = again, which I last used at the university (that was 15 years ago). > > I doubt that still works for a *very* large design. On software, the OS= handes a lot for you. No cache flushes, no memory barriers, etc.=20 >=20 > I would beg to differ. Very large designs are where SW approaches make th= e most sense and benefit. The larger the design (and body of code), the har= der it is to maintain if you don't think about it like SW. In what sense ? Cutting it up in the right modules you mean ? I especially = found the VHDL variable vs signals confusing, and that fact that it looks s= equential, but isn't. > Cache flushes are not unique to SW. The OS is just more SW. So we need to= write a little more code to do that in RTL. I haven't reached that point yet :) > >=20 > > Can a programmer while VHDL code ? Sure. But there is a huge different = between good and "it works". Every monkey can write PHP code, but writing g= ood, maintainable code is a different story. >=20 > Yes there is a difference between SW and HW, nobody is denying that. But = I've reviewed, maintained, and debugged too many RTL designs written too cl= ose to the netlist level not to recognize the benefits of SW approach to RT= L. >=20 > You have to know where to pay attention to the HW (async clock boundaries= are a big chunk). Then handle that close to the HW level, but encapsulate = it into a few reusable entities (like system calls to the OS in SW) and the= n concentrate on the function, throughput and latency of the rest of the de= sign. On a multi-person team, only one or two need to deal with the low lev= el stuff, the rest can design at a much higher level, where the behavior of= the code is critical. I'm still struggling testing in VHDL. With software, I'm more confortable := Junit, gtest, mockito, pick one or combine them. That's getting harder in the modern async works : Akka for example is messa= ge based, high-parallel. I'm looking at vunit for VHDL at the moment, but it's still a bit confusing= : Waveform in, waveform out. With software it's value in, value out. Igmar From newsfish@newsfish Thu Aug 1 00:35:23 2024 X-Received: by 10.182.236.225 with SMTP id ux1mr11718126obc.2.1447314075698; Wed, 11 Nov 2015 23:41:15 -0800 (PST) X-Received: by 10.50.61.236 with SMTP id t12mr96682igr.8.1447314075677; Wed, 11 Nov 2015 23:41:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no662064igv.0!news-out.google.com!l1ni1581igd.0!nntp.google.com!i2no2069383igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Nov 2015 23:41:14 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Thu, 12 Nov 2015 07:41:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4132 Op dinsdag 10 november 2015 09:15:13 UTC+1 schreef rickman: > On 11/9/2015 6:50 AM, igmar.palsenberg@boostermedia.com wrote: > > On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote: > > > >> I think your distinction is pointless. You said "VHDL is a descriptio= n, > >> not a program" and I have you an example when this is not true. End o= f > >> discussion for me. > > > > Fine. That doesn't mean you're right. >=20 > ??? You don't make sense. I give you an example of VHDL that is a=20 > program as used everyday and you reject that??? >=20 >=20 > >> As to the "mindset", there was a software designer who wanted to code = an > >> FPGA in VHDL and came here asking for advice. We told him about how h= e > >> needed to adjust his thinking to design hardware and not code software= . > >> I wrote to him personally to explain why this was important and cam= e > >> close to getting some consulting time with his firm. In the end his > >> bosses had faith that he could do a good job and so he wrote the code > >> himself, without any trouble. > > > > It's a whole different thing, assuming the end result ends up on a FPGA= . Software is sequenced, around datastructures. VHDL is not sequenced, and = doesn't have thing software has : Lock issues, memory alignment issues, etc= . >=20 > I don't think you understand VHDL. VHDL has sequential code, that is=20 > what a process it. But all of t hem run parallel. With software, it's the other way around. > > With software, you attach a debugger, and you can step through. With VH= DL, it's not that simple. So yes, I call this a different mindset. If you t= hink like a software programmer, you'll sooner or later end up with a non-w= orking, hard to debug prototype. >=20 > Huh??? I use single stepping with VHDL at times. Normally it isn't=20 > that useful because there is so much parallelism, things tend to jump=20 > around as one process stops and another starts... same as software on a= =20 > processor with interrupts or multitasking. That's also getting more common in software these days. Ever tried debuggin= g a 1M messages / second Akka application ? I've used Altera's Max Plus II, that only had waveforms. Hooking a real sim= ulator up with Quartus failed for me. I might try the Xilinx tools, see if = I have better luck with them. =20 > > Can a programmer while VHDL code ? Sure. But there is a huge different = between good and "it works". Every monkey can write PHP code, but writing g= ood, maintainable code is a different story. >=20 > I'm not sure what you are going on about. You started by saying "VHDL=20 > is a description, not a program." Now you seem to be splitting all=20 > manner of hairs and calling programmers "monkeys". I was trying to point out there is a difference between getting something t= o work, and actually understanding it. I failed at that :) Igmar From newsfish@newsfish Thu Aug 1 00:35:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Thu, 12 Nov 2015 11:32:41 -0500 Organization: A noiseless patient Spider Lines: 125 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Nov 2015 16:30:24 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="8907"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18rh7baIp81tSRwCYHbXwhg" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> Cancel-Lock: sha1:zy8bWrF1vwQW2p21GNsx3zh3HcM= Xref: news.eternal-september.org comp.lang.vhdl:4133 On 11/12/2015 2:36 AM, Igmar Palsenberg wrote: > Op dinsdag 10 november 2015 04:04:31 UTC+1 schreef Andy: >> On Monday, November 9, 2015 at 5:50:51 AM UTC-6, >> igmar.pa...@boostermedia.com wrote: >>> It's a whole different thing, assuming the end result ends up on >>> a FPGA. Software is sequenced, around datastructures. VHDL is not >>> sequenced, and doesn't have thing software has : Lock issues, >>> memory alignment issues, etc. >>> >> Really? You think a modern SW compiler doesn't tweak your sequence >> to take advantage of the processor's capabilities. Whether it's SW >> or HW: coder, know thy compiler! > > Sure. > >> And who says data structures are exclusive to SW? Oh, you mean they >> aren't > available in Verilog? Use a better language! > > Datastructures come at a price. In software the're cheap, in hardware > the're less cheap. I need to think harder in VHDL about the structure > in general. I find myself far less limited in software (which is also > a potential problem, if you ask me) I use data structures often in hardware, RAM, FIFO, stacks, arrays, etc. >>> With software, you attach a debugger, and you can step through. >>> With VHDL, it's not that simple. So yes, I call this a different >>> mindset. If you think like a software programmer, you'll sooner >>> or later end up with a non-working, hard to debug prototype. >> >> So you don't use the debugger to set breakpoints and step through >> complex RTL? I guess maybe not if you code too close to the edif. > > I did that on old Altera software. I failed at the latest version, > still need to look into that. In IntelliJ, it just attach and it > works (c). > >> Been developing FPGAs in VHDL like SW (enlightened by digital HW >> circuit design experience) for 20+ years now. Have fewer problems >> than when I tried to code netlists, doing the synthesis tool's job >> for it. Sure it's not _exactly_ like SW, but many, many principles >> of SW development are highly applicable to RTL. > > True. I have 20+ in software, not in hardware. Getting up-to-speed on > VHDL again, which I last used at the university (that was 15 years > ago). Any questions or issues? I think the hard part of VHDL is the strong typing which is very similar to Ada and that is no longer hard to me so it's all easy other than dealing with my requirements for the problem. >>> I doubt that still works for a *very* large design. On software, >>> the OS handes a lot for you. No cache flushes, no memory >>> barriers, etc. >> >> I would beg to differ. Very large designs are where SW approaches >> make the most sense and benefit. The larger the design (and body of >> code), the harder it is to maintain if you don't think about it >> like SW. > > In what sense ? Cutting it up in the right modules you mean ? I > especially found the VHDL variable vs signals confusing, and that > fact that it looks sequential, but isn't. Any time you need to break a problem down to parallel tasks in software it gets *much* more difficult. In VHDL this is not so much an issue. The sequential part of VHDL (processes) are *exactly* like software when you use variables. Signals are only different in that they are not updated until the process stops. This is because of the fact that signals are intended to model hardware with delays. So all signal assignments are made with a delta delay as a minimum which is zero time (think infinitesimal in math) and so won't happen until the process ends. All statements in a process happen without time advancing, even delta time. >> Cache flushes are not unique to SW. The OS is just more SW. So we >> need to write a little more code to do that in RTL. > > I haven't reached that point yet :) > >>> >>> Can a programmer while VHDL code ? Sure. But there is a huge >>> different between good and "it works". Every monkey can write PHP >>> code, but writing good, maintainable code is a different story. >> >> Yes there is a difference between SW and HW, nobody is denying >> that. But I've reviewed, maintained, and debugged too many RTL >> designs written too close to the netlist level not to recognize the >> benefits of SW approach to RTL. >> >> You have to know where to pay attention to the HW (async clock >> boundaries are a big chunk). Then handle that close to the HW >> level, but encapsulate it into a few reusable entities (like system >> calls to the OS in SW) and then concentrate on the function, >> throughput and latency of the rest of the design. On a multi-person >> team, only one or two need to deal with the low level stuff, the >> rest can design at a much higher level, where the behavior of the >> code is critical. > > I'm still struggling testing in VHDL. With software, I'm more > confortable : Junit, gtest, mockito, pick one or combine them. That's > getting harder in the modern async works : Akka for example is > message based, high-parallel. I guess it has been awhile since I've done C development. I've never heard of these tools. Mostly my software is done in Forth. > I'm looking at vunit for VHDL at the moment, but it's still a bit > confusing : Waveform in, waveform out. With software it's value in, > value out. VHDL has built in testing tools. ASSERT statements are how I do it. There are other features provided by system Verilog that are even fancier I hear. Even so, it's not about waveforms really. Its about inputs and outputs. VHDL describes the inputs. VHDL verifies the outputs. Waveforms are for viewing by the user when you have a problem. -- Rick From newsfish@newsfish Thu Aug 1 00:35:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Thu, 12 Nov 2015 11:40:41 -0500 Organization: A noiseless patient Spider Lines: 88 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Nov 2015 16:38:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10852"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18kh5XMLYe2PoEHWgPMnOzE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Cancel-Lock: sha1:pjHa8RLsGEsJaGAt/Qt14bXfFnE= Xref: news.eternal-september.org comp.lang.vhdl:4134 On 11/12/2015 2:41 AM, Igmar Palsenberg wrote: > Op dinsdag 10 november 2015 09:15:13 UTC+1 schreef rickman: >> On 11/9/2015 6:50 AM, igmar.palsenberg@boostermedia.com wrote: >>> On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote: >>> >>>> I think your distinction is pointless. You said "VHDL is a >>>> description, not a program" and I have you an example when this >>>> is not true. End of discussion for me. >>> >>> Fine. That doesn't mean you're right. >> >> ??? You don't make sense. I give you an example of VHDL that is >> a program as used everyday and you reject that??? >> >> >>>> As to the "mindset", there was a software designer who wanted >>>> to code an FPGA in VHDL and came here asking for advice. We >>>> told him about how he needed to adjust his thinking to design >>>> hardware and not code software. I wrote to him personally to >>>> explain why this was important and came close to getting some >>>> consulting time with his firm. In the end his bosses had faith >>>> that he could do a good job and so he wrote the code himself, >>>> without any trouble. >>> >>> It's a whole different thing, assuming the end result ends up on >>> a FPGA. Software is sequenced, around datastructures. VHDL is not >>> sequenced, and doesn't have thing software has : Lock issues, >>> memory alignment issues, etc. >> >> I don't think you understand VHDL. VHDL has sequential code, that >> is what a process it. > > But all of t hem run parallel. With software, it's the other way > around. Processes run in parallel in both VHDL and in software. In software your process may be *hugely* complex doing many, many things in each one. Partly that's because there is a huge overhead for setting up and managing each process in software. In VHDL a process has no overhead in the implementation. I'm not sure how complex process management is in simulation. I've not heard it is a problem though. The speed problems in simulation often come from the data structures. Integers are faster than std_logic, et. al. >>> With software, you attach a debugger, and you can step through. >>> With VHDL, it's not that simple. So yes, I call this a different >>> mindset. If you think like a software programmer, you'll sooner >>> or later end up with a non-working, hard to debug prototype. >> >> Huh??? I use single stepping with VHDL at times. Normally it >> isn't that useful because there is so much parallelism, things tend >> to jump around as one process stops and another starts... same as >> software on a processor with interrupts or multitasking. > > That's also getting more common in software these days. Ever tried > debugging a 1M messages / second Akka application ? > > I've used Altera's Max Plus II, that only had waveforms. Hooking a > real simulator up with Quartus failed for me. I might try the Xilinx > tools, see if I have better luck with them. I've worked with Max +II. Debugging in VHDL is built in. ASSERT is a great tool. Waveforms are for user exploration when a bug is found. >>> Can a programmer while VHDL code ? Sure. But there is a huge >>> different between good and "it works". Every monkey can write PHP >>> code, but writing good, maintainable code is a different story. >> >> I'm not sure what you are going on about. You started by saying >> "VHDL is a description, not a program." Now you seem to be >> splitting all manner of hairs and calling programmers "monkeys". > > I was trying to point out there is a difference between getting > something to work, and actually understanding it. I failed at that > :) I've seen that many times. I've even done it when required. Sometimes you don't have the time to "understand" something if you just need a simple fix. BTW, I can't write PHP code. I don't even know what it is, so obviously I'm not a monkey. ;) -- Rick From newsfish@newsfish Thu Aug 1 00:35:23 2024 X-Received: by 10.50.136.199 with SMTP id qc7mr1162360igb.13.1447347648949; Thu, 12 Nov 2015 09:00:48 -0800 (PST) X-Received: by 10.50.78.164 with SMTP id c4mr159492igx.4.1447347648924; Thu, 12 Nov 2015 09:00:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no875098igv.0!news-out.google.com!l1ni2017igd.0!nntp.google.com!i2no875086igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Nov 2015 09:00:48 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Thu, 12 Nov 2015 17:00:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4135 > Processes run in parallel in both VHDL and in software. That can only be done if : a) You have multiple cores / processors b) You have an OS that supports it If either of them are not met, it all runs sequential. > In software your > process may be *hugely* complex doing many, many things in each one. > Partly that's because there is a huge overhead for setting up and > managing each process in software. In VHDL a process has no overhead in > the implementation. I'm not sure how complex process management is in > simulation. I've not heard it is a problem though. The speed problems in > simulation often come from the data structures. Integers are faster than > std_logic, et. al. I don't expect that simulation runs at fullspeed. Similar tools in software usually also have an overhead. > > I've used Altera's Max Plus II, that only had waveforms. Hooking a > > real simulator up with Quartus failed for me. I might try the Xilinx > > tools, see if I have better luck with them. > > I've worked with Max +II. Debugging in VHDL is built in. ASSERT is a > great tool. Waveforms are for user exploration when a bug is found. Hmm.. I never saw it. On the other hand : That was 15 years ago. > > I was trying to point out there is a difference between getting > > something to work, and actually understanding it. I failed at that > > :) > > I've seen that many times. I've even done it when required. Sometimes > you don't have the time to "understand" something if you just need a > simple fix. I personally don't like that myself. > BTW, I can't write PHP code. I don't even know what it is, so obviously > I'm not a monkey. ;) Advise : Keep it that way :) Igmar From newsfish@newsfish Thu Aug 1 00:35:24 2024 X-Received: by 10.66.157.37 with SMTP id wj5mr14043441pab.30.1447348236824; Thu, 12 Nov 2015 09:10:36 -0800 (PST) X-Received: by 10.50.6.40 with SMTP id x8mr365540igx.0.1447348236760; Thu, 12 Nov 2015 09:10:36 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no878198igv.0!news-out.google.com!l1ni2025igd.0!nntp.google.com!i2no2222033igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Nov 2015 09:10:36 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Thu, 12 Nov 2015 17:10:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4136 > > Datastructures come at a price. In software the're cheap, in hardware > > the're less cheap. I need to think harder in VHDL about the structure > > in general. I find myself far less limited in software (which is also > > a potential problem, if you ask me) > > I use data structures often in hardware, RAM, FIFO, stacks, arrays, etc. Is that always synthesizable ? > >>> With software, you attach a debugger, and you can step through. > >>> With VHDL, it's not that simple. So yes, I call this a different > >>> mindset. If you think like a software programmer, you'll sooner > >>> or later end up with a non-working, hard to debug prototype. > >> > >> So you don't use the debugger to set breakpoints and step through > >> complex RTL? I guess maybe not if you code too close to the edif. > > > > I did that on old Altera software. I failed at the latest version, > > still need to look into that. In IntelliJ, it just attach and it > > works (c). > > > >> Been developing FPGAs in VHDL like SW (enlightened by digital HW > >> circuit design experience) for 20+ years now. Have fewer problems > >> than when I tried to code netlists, doing the synthesis tool's job > >> for it. Sure it's not _exactly_ like SW, but many, many principles > >> of SW development are highly applicable to RTL. > > > > True. I have 20+ in software, not in hardware. Getting up-to-speed on > > VHDL again, which I last used at the university (that was 15 years > > ago). > > Any questions or issues? I think the hard part of VHDL is the strong > typing which is very similar to Ada and that is no longer hard to me so > it's all easy other than dealing with my requirements for the problem. I'm used to languages with strong typing. I consider that a big plus myself, especially if you have a decent compiler that warns you when things look weird. > > In what sense ? Cutting it up in the right modules you mean ? I > > especially found the VHDL variable vs signals confusing, and that > > fact that it looks sequential, but isn't. > > Any time you need to break a problem down to parallel tasks in software > it gets *much* more difficult. In VHDL this is not so much an issue. > > The sequential part of VHDL (processes) are *exactly* like software when > you use variables. Signals are only different in that they are not > updated until the process stops. This is because of the fact that > signals are intended to model hardware with delays. So all signal > assignments are made with a delta delay as a minimum which is zero time > (think infinitesimal in math) and so won't happen until the process > ends. All statements in a process happen without time advancing, even > delta time. Clear. I find debugging programs with a large number of thread a huge PITA. Is something goes wrong, it's sometimes nearly impossible to trace, especially since debuggers change behaviour (read : timing). > > I'm still struggling testing in VHDL. With software, I'm more > > confortable : Junit, gtest, mockito, pick one or combine them. That's > > getting harder in the modern async works : Akka for example is > > message based, high-parallel. > > I guess it has been awhile since I've done C development. I've never > heard of these tools. Mostly my software is done in Forth. I've never done that. Only C, C++, Pascal, PHP, Java, Scala, Python and bash. > > I'm looking at vunit for VHDL at the moment, but it's still a bit > > confusing : Waveform in, waveform out. With software it's value in, > > value out. > > VHDL has built in testing tools. ASSERT statements are how I do it. > There are other features provided by system Verilog that are even > fancier I hear. Even so, it's not about waveforms really. Its about > inputs and outputs. VHDL describes the inputs. VHDL verifies the > outputs. Waveforms are for viewing by the user when you have a problem. Well, take for example the LD A, 0xFF Z80 instruction. That roughly does : 1) Fetch instruction byte from PC and increase PC 2) Fetch operands from PC, and increase PC 3) Move operand to A register 4) Increase PC How do you test that ? You also want to test timing, since on a real Z80, this instruction takes a fixed amount of time (no pipeline, no cache, no prefetching, no nothing). I would say confirm each step, but I'm still working that out. Regards, Igmar From newsfish@newsfish Thu Aug 1 00:35:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Thu, 12 Nov 2015 15:45:42 -0500 Organization: A noiseless patient Spider Lines: 122 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Nov 2015 20:43:26 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="9210"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18L+F3Z1/b1rgAi93IUm9Nj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:BdJvjoHQ4pS3p3mGejGnRT77mBg= Xref: news.eternal-september.org comp.lang.vhdl:4137 On 11/12/2015 12:10 PM, Igmar Palsenberg wrote: > >>> Datastructures come at a price. In software the're cheap, in hardware >>> the're less cheap. I need to think harder in VHDL about the structure >>> in general. I find myself far less limited in software (which is also >>> a potential problem, if you ask me) >> >> I use data structures often in hardware, RAM, FIFO, stacks, arrays, etc. > > Is that always synthesizable ? They are if you describe them with synthesizable code. There is nothing special about any of them that a compiler can't understand. It's all just logic. >>>>> With software, you attach a debugger, and you can step through. >>>>> With VHDL, it's not that simple. So yes, I call this a different >>>>> mindset. If you think like a software programmer, you'll sooner >>>>> or later end up with a non-working, hard to debug prototype. >>>> >>>> So you don't use the debugger to set breakpoints and step through >>>> complex RTL? I guess maybe not if you code too close to the edif. >>> >>> I did that on old Altera software. I failed at the latest version, >>> still need to look into that. In IntelliJ, it just attach and it >>> works (c). >>> >>>> Been developing FPGAs in VHDL like SW (enlightened by digital HW >>>> circuit design experience) for 20+ years now. Have fewer problems >>>> than when I tried to code netlists, doing the synthesis tool's job >>>> for it. Sure it's not _exactly_ like SW, but many, many principles >>>> of SW development are highly applicable to RTL. >>> >>> True. I have 20+ in software, not in hardware. Getting up-to-speed on >>> VHDL again, which I last used at the university (that was 15 years >>> ago). >> >> Any questions or issues? I think the hard part of VHDL is the strong >> typing which is very similar to Ada and that is no longer hard to me so >> it's all easy other than dealing with my requirements for the problem. > > I'm used to languages with strong typing. I consider that a big plus myself, especially if you have a decent compiler that warns you when things look weird. I like it in some cases, but until more recently it was a PITA to try to use as it requires a lot more typing. I am will to give Verilog a shot if I can find a good book. >>> In what sense ? Cutting it up in the right modules you mean ? I >>> especially found the VHDL variable vs signals confusing, and that >>> fact that it looks sequential, but isn't. >> >> Any time you need to break a problem down to parallel tasks in software >> it gets *much* more difficult. In VHDL this is not so much an issue. >> >> The sequential part of VHDL (processes) are *exactly* like software when >> you use variables. Signals are only different in that they are not >> updated until the process stops. This is because of the fact that >> signals are intended to model hardware with delays. So all signal >> assignments are made with a delta delay as a minimum which is zero time >> (think infinitesimal in math) and so won't happen until the process >> ends. All statements in a process happen without time advancing, even >> delta time. > > Clear. I find debugging programs with a large number of thread a huge PITA. Is something goes wrong, it's sometimes nearly impossible to trace, especially since debuggers change behaviour (read : timing). Delta delays get around repeatability issues while Verilog can be a killer because of them. If you are single stepping to debug code you are most likely doing it wrong. That is a poor technique in nearly any language. >>> I'm still struggling testing in VHDL. With software, I'm more >>> confortable : Junit, gtest, mockito, pick one or combine them. That's >>> getting harder in the modern async works : Akka for example is >>> message based, high-parallel. >> >> I guess it has been awhile since I've done C development. I've never >> heard of these tools. Mostly my software is done in Forth. > > I've never done that. Only C, C++, Pascal, PHP, Java, Scala, Python and bash. > >>> I'm looking at vunit for VHDL at the moment, but it's still a bit >>> confusing : Waveform in, waveform out. With software it's value in, >>> value out. >> >> VHDL has built in testing tools. ASSERT statements are how I do it. >> There are other features provided by system Verilog that are even >> fancier I hear. Even so, it's not about waveforms really. Its about >> inputs and outputs. VHDL describes the inputs. VHDL verifies the >> outputs. Waveforms are for viewing by the user when you have a problem. > > Well, take for example the LD A, 0xFF Z80 instruction. That roughly does : > > 1) Fetch instruction byte from PC and increase PC > 2) Fetch operands from PC, and increase PC > 3) Move operand to A register > 4) Increase PC > > How do you test that ? You also want to test timing, since on a real Z80, this instruction takes a fixed amount of time (no pipeline, no cache, no prefetching, no nothing). > > I would say confirm each step, but I'm still working that out. Again, you only care about inputs and outputs. Make the opcode available at the last point in time it can be read by the timing spec or model the memory as its own function (which you then need to verify). I don't know that the timing of internal events is required other than clock cycle alignment. Even then it is hard to test internal features other than functionally. So execute the next instruction to read the A register and read it out. That also verifies the PC increment. Test it as you would a Z80 chip. I believe I have found ways to read internal signals of modules in VHDL. I think this is a simulator feature rather than a language feature though. Verilog supports this directly. What issues are you concerned about? -- Rick From newsfish@newsfish Thu Aug 1 00:35:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Thu, 12 Nov 2015 15:51:17 -0500 Organization: A noiseless patient Spider Lines: 76 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Nov 2015 20:49:00 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10702"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+KOeas3/aXCnWdvXWluzlo" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:XHoHQxbpjN6dtcxInIFeMmnp1t4= Xref: news.eternal-september.org comp.lang.vhdl:4138 On 11/12/2015 12:00 PM, Igmar Palsenberg wrote: > >> Processes run in parallel in both VHDL and in software. > > That can only be done if : > > a) You have multiple cores / processors Neither VHDL nor single processors actually run processes in parallel. The processor is time multiplexed to run one process at a time. But I'm sure you know that. > b) You have an OS that supports it Yeah... so? > If either of them are not met, it all runs sequential. So??? Even with multiple processors multiprocessing has all the same issues. >> In software your process may be *hugely* complex doing many, many >> things in each one. Partly that's because there is a huge overhead >> for setting up and managing each process in software. In VHDL a >> process has no overhead in the implementation. I'm not sure how >> complex process management is in simulation. I've not heard it is a >> problem though. The speed problems in simulation often come from >> the data structures. Integers are faster than std_logic, et. al. > > I don't expect that simulation runs at fullspeed. Similar tools in > software usually also have an overhead. > >>> I've used Altera's Max Plus II, that only had waveforms. Hooking >>> a real simulator up with Quartus failed for me. I might try the >>> Xilinx tools, see if I have better luck with them. >> >> I've worked with Max +II. Debugging in VHDL is built in. ASSERT >> is a great tool. Waveforms are for user exploration when a bug is >> found. > > Hmm.. I never saw it. On the other hand : That was 15 years ago. ASSERT has been part of VHDL from the beginning. Read up on test benches. Simulating hardware by generating waveforms manually and looking at the outputs is a PITA. >>> I was trying to point out there is a difference between getting >>> something to work, and actually understanding it. I failed at >>> that :) >> >> I've seen that many times. I've even done it when required. >> Sometimes you don't have the time to "understand" something if you >> just need a simple fix. > > I personally don't like that myself. There are lots of things about work I don't like. But the job is to do the job, not make myself happy... well, not all the time. >> BTW, I can't write PHP code. I don't even know what it is, so >> obviously I'm not a monkey. ;) > > Advise : Keep it that way :) > > > Igmar > -- Rick From newsfish@newsfish Thu Aug 1 00:35:24 2024 X-Received: by 10.107.135.150 with SMTP id r22mr16070729ioi.24.1447373176824; Thu, 12 Nov 2015 16:06:16 -0800 (PST) X-Received: by 10.50.57.84 with SMTP id g20mr3938igq.3.1447373176778; Thu, 12 Nov 2015 16:06:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no2381325igv.0!news-out.google.com!f6ni520igq.0!nntp.google.com!i2no1094217igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Nov 2015 16:06:16 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Fri, 13 Nov 2015 00:06:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4139 Data Structures (records, arrays, etc.) can be custom defined, and as long = as they boil down to synthesizable types (Boolean, integer, enumerated type= s, std_logic, etc.) it all synthesizes. But they can sure make passing data= around a lot easier.=20 I took a couple of Ada programming classes shortly after I started using VH= DL, and it helped a lot. Just like Ada, VHDL functions and procedures can b= e defined to perform common functionality (combinatorial) that can be calle= d sequentially, rather than using a separate entity/architecture that must = be concurrently instantiated and communicated with. Things like Hamming/ECC= encoding/decoding functions are much easier to use than entities to do the= same thing. These functions can be defined inside another subprogram, a pr= ocess, or inside an architecture or a package, depending on how widely they= need to be used. Use variables for data that does not need to leave the process. Then assign= signals with the variables to send to another process/entity. That works m= uch better in that the description is then purely sequential, just like SW.= You just have to make sure you don't put too much behavior in one cycle of= latency. And if the logic won't meet the clock period, then add a register (a clock = cycle of latency in the process behavior) before and/or after the subprogra= m call and enable retiming optimization.=20 Subprograms work really well with state machines, since you can call the su= bprogram right there in the state, rather than setup an interface to some o= ther entity or process. Just remember that VHDL subprograms have no static = variables, so if your procedure needs to remember something from one call t= o the next, it needs to be passed (an inout data structure parameter works = well here). Otherwise, if you declare a procedure in a process, anything de= clared beforehand in the same process is also visible inside the procedure.= And signals/ports that are visible to the process are visible inside the p= rocedure too! That can cut down a lot on how much you have to explicitly pa= ss in/out of a procedure with each call. This way, it is easy to describe a= n entire state machine, in one subprogram. The trick is, rather than thinking registers with so many gates between the= m, think in terms of clock cycles of latency (iterations of the clocked pro= cess's inherent "forever" loop). Try not to put too much serial work in any= one clock cycle. How much is too much depends on the device and the clock = rate. As far as testing, we use a continuous integration flow with Jenkins. Our t= estbenches are 100% self-checking (waveforms are for debugging only), and u= se constrained-random stimulus, while monitoring all DUT outputs for compar= ison in scoreboards with an untimed reference model. Coverage models for th= e stimulus ensure we cover what we need to cover in terms of functionality.= This can all be done in SystemVerilog using UVM, or in VHDL using OSVVM. W= e do not do unit level testing. We may use test versions of DUT entities to= make it easier to get to an internal entity's functionality, but we always= use the DUT interface to simplify the stimulus application (drivers) and r= esponse capture (monitors). The scoreboards hook up to the monitors, not th= e DUT, and to the reference model. Monitors can also verify interface proto= cols, without having to know anything about the stimulus or expected respon= se. Hope this helps, Andy From newsfish@newsfish Thu Aug 1 00:35:25 2024 X-Received: by 10.13.194.197 with SMTP id e188mr27434908ywd.24.1447608589879; Sun, 15 Nov 2015 09:29:49 -0800 (PST) X-Received: by 10.50.112.201 with SMTP id is9mr225977igb.10.1447608589847; Sun, 15 Nov 2015 09:29:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no3596394igv.0!news-out.google.com!f6ni3414igq.0!nntp.google.com!i2no3099872igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Nov 2015 09:29:48 -0800 (PST) In-Reply-To: <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4251716a-cba9-43b3-863a-32348cbcb026@googlegroups.com> Subject: Re: creating program From: Lars Asplund Injection-Date: Sun, 15 Nov 2015 17:29:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4140 @rickman > > I'm looking at vunit for VHDL at the moment, but it's still a bit > > confusing : Waveform in, waveform out. With software it's value in, > > value out. > > VHDL has built in testing tools. ASSERT statements are how I do it. VUnit doesn't replace the assert statement, it builds on top of it. So VUnit starts where plain VHDL test support stops. Regards, Lars From newsfish@newsfish Thu Aug 1 00:35:25 2024 X-Received: by 10.107.153.146 with SMTP id b140mr28307724ioe.30.1447613850572; Sun, 15 Nov 2015 10:57:30 -0800 (PST) X-Received: by 10.50.78.164 with SMTP id c4mr228773igx.4.1447613850555; Sun, 15 Nov 2015 10:57:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!i2no3634442igv.0!news-out.google.com!f6ni3478igq.0!nntp.google.com!i2no3156445igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Nov 2015 10:57:29 -0800 (PST) In-Reply-To: <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Lars Asplund Injection-Date: Sun, 15 Nov 2015 18:57:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 72 Xref: news.eternal-september.org comp.lang.vhdl:4141 @Andy =20 > As far as testing, we use a continuous integration flow with Jenkins. Our= testbenches are 100% self-checking (waveforms are for debugging only), and= use constrained-random stimulus, while monitoring all DUT outputs for comp= arison in scoreboards with an untimed reference model. Coverage models for = the stimulus ensure we cover what we need to cover in terms of functionalit= y. This can all be done in SystemVerilog using UVM, or in VHDL using OSVVM.= We do not do unit level testing. We may use test versions of DUT entities = to make it easier to get to an internal entity's functionality, but we alwa= ys use the DUT interface to simplify the stimulus application (drivers) and= response capture (monitors). The scoreboards hook up to the monitors, not = the DUT, and to the reference model. Monitors can also verify interface pro= tocols, without having to know anything about the stimulus or expected resp= onse. When I promote the use of VUnit it's usually very easy when people have a p= revious experience with unit testing tools for SW. They know what to expect= and they know that they want it. It seems to me that you may have such exp= erience but decided to do only top level testing anyway. That makes me a bi= t curious about the reasons. Are you working as a verification engineer, RT= L designer, or both? Anyway, it might be interesting for you to know that VUnit doesn't know wha= t a unit is, it doesn't care about your test strategy as long as your testb= enches are self-checking, and it has support for Jenkins integration. So if= you wrap your testbench in this library vunit_lib; context vunit_lib.vunit_context; entity tb_example is generic (runner_cfg : runner_cfg_t); end entity; architecture tb of tb_example is begin main : process begin test_runner_setup(runner, runner_cfg); -- Put whatever your "main process" is doing here test_runner_cleanup(runner); -- Simulation ends here end process; -- Put your DUT, scoreboards, monitors, reference models here end architecture; and create a python script (run.py) like this from vunit import VUnit vu =3D VUnit.from_argv() lib =3D vu.add_library("lib") lib.add_source_files("*.vhd") # Create as many libraries as needed and add source files to them vu.main() and do python run.py -x test_report.xml from the command line you will have something that (assuming you're using M= odelSim, Riviera-PRO, Active-HDL or GHDL) compiles your source files in dep= endency order based on what has been modified. The script then finds and ru= ns your testbench(es) and generates a test report on "Jenkins format" Regards, Lars From newsfish@newsfish Thu Aug 1 00:35:25 2024 X-Received: by 10.50.142.103 with SMTP id rv7mr5908583igb.2.1447658562889; Sun, 15 Nov 2015 23:22:42 -0800 (PST) X-Received: by 10.50.98.67 with SMTP id eg3mr27440igb.1.1447658562852; Sun, 15 Nov 2015 23:22:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no3459540igv.0!news-out.google.com!l1ni5989igd.0!nntp.google.com!i2no3806216igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Nov 2015 23:22:41 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.113.175.178; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 80.113.175.178 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Mon, 16 Nov 2015 07:22:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4142 > > I'm used to languages with strong typing. I consider that a big plus myself, especially if you have a decent compiler that warns you when things look weird. > > I like it in some cases, but until more recently it was a PITA to try to > use as it requires a lot more typing. I am will to give Verilog a shot > if I can find a good book. In my experience, a good IDE can help. Sigasi helps a lot, it also has features that at least the Quartus editor doesn't have. > >>> In what sense ? Cutting it up in the right modules you mean ? I > >>> especially found the VHDL variable vs signals confusing, and that > >>> fact that it looks sequential, but isn't. > >> > >> Any time you need to break a problem down to parallel tasks in software > >> it gets *much* more difficult. In VHDL this is not so much an issue. > >> > >> The sequential part of VHDL (processes) are *exactly* like software when > >> you use variables. Signals are only different in that they are not > >> updated until the process stops. This is because of the fact that > >> signals are intended to model hardware with delays. So all signal > >> assignments are made with a delta delay as a minimum which is zero time > >> (think infinitesimal in math) and so won't happen until the process > >> ends. All statements in a process happen without time advancing, even > >> delta time. > > > > Clear. I find debugging programs with a large number of thread a huge PITA. Is something goes wrong, it's sometimes nearly impossible to trace, especially since debuggers change behaviour (read : timing). > > Delta delays get around repeatability issues while Verilog can be a > killer because of them. If you are single stepping to debug code you > are most likely doing it wrong. That is a poor technique in nearly any > language. Personally, I use logging to a file a lot. And breakpoints on certain points, mainly in async code. > >>> I'm still struggling testing in VHDL. With software, I'm more > >>> confortable : Junit, gtest, mockito, pick one or combine them. That's > >>> getting harder in the modern async works : Akka for example is > >>> message based, high-parallel. > >> > >> I guess it has been awhile since I've done C development. I've never > >> heard of these tools. Mostly my software is done in Forth. > > > > I've never done that. Only C, C++, Pascal, PHP, Java, Scala, Python and bash. > > > >>> I'm looking at vunit for VHDL at the moment, but it's still a bit > >>> confusing : Waveform in, waveform out. With software it's value in, > >>> value out. > >> > >> VHDL has built in testing tools. ASSERT statements are how I do it. > >> There are other features provided by system Verilog that are even > >> fancier I hear. Even so, it's not about waveforms really. Its about > >> inputs and outputs. VHDL describes the inputs. VHDL verifies the > >> outputs. Waveforms are for viewing by the user when you have a problem. > > > > Well, take for example the LD A, 0xFF Z80 instruction. That roughly does : > > > > 1) Fetch instruction byte from PC and increase PC > > 2) Fetch operands from PC, and increase PC > > 3) Move operand to A register > > 4) Increase PC > > > > How do you test that ? You also want to test timing, since on a real Z80, this instruction takes a fixed amount of time (no pipeline, no cache, no prefetching, no nothing). > > > > I would say confirm each step, but I'm still working that out. > > Again, you only care about inputs and outputs. Make the opcode > available at the last point in time it can be read by the timing spec or > model the memory as its own function (which you then need to verify). I > don't know that the timing of internal events is required other than > clock cycle alignment. Even then it is hard to test internal features > other than functionally. So execute the next instruction to read the A > register and read it out. That also verifies the PC increment. Test it > as you would a Z80 chip. I'll just start trying. The Z80 is pretty simple, that makes it a lot easier to get started with. Good exercise. > I believe I have found ways to read internal signals of modules in VHDL. > I think this is a simulator feature rather than a language feature > though. Verilog supports this directly. > > What issues are you concerned about? I normally test internals (in software, that is), since it will make determining what broke easier then just testing the public interfaces. I probably just need to get started, and not think about this to much. Igmar From newsfish@newsfish Thu Aug 1 00:35:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!weretis.net!feeder4.news.weretis.net!ecngs!testfeeder.ecngs.de!81.171.118.62.MISMATCH!peer02.fr7!news.highwinds-media.com!post02.fr7!fx41.am4.POSTED!not-for-mail X-Mozilla-News-Host: news://news.virginmedia.com:119 Reply-To: hans64@htminuslab.com Newsgroups: comp.lang.vhdl From: HT-Lab Subject: keywords versus language complexity User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 151116-0, 16/11/2015), Outbound message X-Antivirus-Status: Clean Lines: 9 Message-ID: NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1447671150 81.109.142.154 (Mon, 16 Nov 2015 10:52:30 UTC) NNTP-Posting-Date: Mon, 16 Nov 2015 10:52:30 UTC Organization: virginmedia.com Date: Mon, 16 Nov 2015 10:52:29 +0000 X-Received-Body-CRC: 3877743601 X-Received-Bytes: 1239 Xref: news.eternal-september.org comp.lang.vhdl:4143 For those who haven't seen this article (edacafe.com): http://www10.edacafe.com/blogs/realintent/2015/11/12/is-systemverilog-the-cobol-of-electronic-design/ Regarding the stackoverflow question, I counted 129 reserved words in VHDL (14 for PSL, excluded VHPI), which is not bad ;-) Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:35:26 2024 X-Received: by 10.182.97.38 with SMTP id dx6mr31793189obb.29.1447682508109; Mon, 16 Nov 2015 06:01:48 -0800 (PST) X-Received: by 10.50.72.72 with SMTP id b8mr281210igv.2.1447682508049; Mon, 16 Nov 2015 06:01:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no3683158igv.0!news-out.google.com!f6ni4266igq.0!nntp.google.com!i2no3954861igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 16 Nov 2015 06:01:47 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: keywords versus language complexity From: Chris Higgs Injection-Date: Mon, 16 Nov 2015 14:01:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4144 Another proxy for complexity - language specification length: http://www.fivecomputers.com/language-specification-length.html From newsfish@newsfish Thu Aug 1 00:35:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!peer01.fr7!news.highwinds-media.com!post01.fr7!fx46.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: keywords versus language complexity References: Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 151116-0, 16/11/2015), Outbound message X-Antivirus-Status: Clean Lines: 26 Message-ID: NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1447691491 81.109.142.154 (Mon, 16 Nov 2015 16:31:31 UTC) NNTP-Posting-Date: Mon, 16 Nov 2015 16:31:31 UTC Organization: virginmedia.com Date: Mon, 16 Nov 2015 16:31:30 +0000 X-Received-Body-CRC: 3128994999 X-Received-Bytes: 2199 Xref: news.eternal-september.org comp.lang.vhdl:4145 On 16/11/2015 14:01, Chris Higgs wrote: > Another proxy for complexity - language specification length: http://www.fivecomputers.com/language-specification-length.html > Hi Chris, Yes the LRM could also be a good indicator of language complexity. I just checked a draft 1076-2008 standard which comes in at 636 pages, however, if I take the VHPI part out (the largest section) and the BNF pages then we end up with about 290 pages of pure VHDL goodness. Which again is not bad compared to SV distilled 899 pages (according to your link). I actually mentioned the article as most of us don't realise the pain parser and tool developers have to go through to support all the esoteric feature mentioned in an LRM. SV is clearly a complex language and with the small user base you will pay through the nose for tools that fully support it. We are lucky to have Jim Lewis driving the next VHDL standard so I am sure VHDL will remain lean and mean (well at least in terms of RTL standards ;-) Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:35:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Mon, 16 Nov 2015 12:40:31 -0500 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 16 Nov 2015 17:38:10 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="dd8e7b5935e95133fd5dec46ea2fab06"; logging-data="23063"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19G9RsRJSRYKVtxxhI3JJSb" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> Cancel-Lock: sha1:cW6A2ModdL6kwyEcV6izF3cT5fw= Xref: news.eternal-september.org comp.lang.vhdl:4146 On 11/16/2015 2:22 AM, Igmar Palsenberg wrote: > >>> I'm used to languages with strong typing. I consider that a big plus myself, especially if you have a decent compiler that warns you when things look weird. >> >> I like it in some cases, but until more recently it was a PITA to try to >> use as it requires a lot more typing. I am will to give Verilog a shot >> if I can find a good book. > > In my experience, a good IDE can help. Sigasi helps a lot, it also has features that at least the Quartus editor doesn't have. I've heard a lot of good about Emacs in this regard. >>>>> In what sense ? Cutting it up in the right modules you mean ? I >>>>> especially found the VHDL variable vs signals confusing, and that >>>>> fact that it looks sequential, but isn't. >>>> >>>> Any time you need to break a problem down to parallel tasks in software >>>> it gets *much* more difficult. In VHDL this is not so much an issue. >>>> >>>> The sequential part of VHDL (processes) are *exactly* like software when >>>> you use variables. Signals are only different in that they are not >>>> updated until the process stops. This is because of the fact that >>>> signals are intended to model hardware with delays. So all signal >>>> assignments are made with a delta delay as a minimum which is zero time >>>> (think infinitesimal in math) and so won't happen until the process >>>> ends. All statements in a process happen without time advancing, even >>>> delta time. >>> >>> Clear. I find debugging programs with a large number of thread a huge PITA. Is something goes wrong, it's sometimes nearly impossible to trace, especially since debuggers change behaviour (read : timing). >> >> Delta delays get around repeatability issues while Verilog can be a >> killer because of them. If you are single stepping to debug code you >> are most likely doing it wrong. That is a poor technique in nearly any >> language. > > Personally, I use logging to a file a lot. And breakpoints on certain points, mainly in async code. That requires a lot of manual work. If you are trying to find a problem it can be useful. But for verification it is better to automate the process. >>>>> I'm still struggling testing in VHDL. With software, I'm more >>>>> confortable : Junit, gtest, mockito, pick one or combine them. That's >>>>> getting harder in the modern async works : Akka for example is >>>>> message based, high-parallel. >>>> >>>> I guess it has been awhile since I've done C development. I've never >>>> heard of these tools. Mostly my software is done in Forth. >>> >>> I've never done that. Only C, C++, Pascal, PHP, Java, Scala, Python and bash. >>> >>>>> I'm looking at vunit for VHDL at the moment, but it's still a bit >>>>> confusing : Waveform in, waveform out. With software it's value in, >>>>> value out. >>>> >>>> VHDL has built in testing tools. ASSERT statements are how I do it. >>>> There are other features provided by system Verilog that are even >>>> fancier I hear. Even so, it's not about waveforms really. Its about >>>> inputs and outputs. VHDL describes the inputs. VHDL verifies the >>>> outputs. Waveforms are for viewing by the user when you have a problem. >>> >>> Well, take for example the LD A, 0xFF Z80 instruction. That roughly does : >>> >>> 1) Fetch instruction byte from PC and increase PC >>> 2) Fetch operands from PC, and increase PC >>> 3) Move operand to A register >>> 4) Increase PC >>> >>> How do you test that ? You also want to test timing, since on a real Z80, this instruction takes a fixed amount of time (no pipeline, no cache, no prefetching, no nothing). >>> >>> I would say confirm each step, but I'm still working that out. >> >> Again, you only care about inputs and outputs. Make the opcode >> available at the last point in time it can be read by the timing spec or >> model the memory as its own function (which you then need to verify). I >> don't know that the timing of internal events is required other than >> clock cycle alignment. Even then it is hard to test internal features >> other than functionally. So execute the next instruction to read the A >> register and read it out. That also verifies the PC increment. Test it >> as you would a Z80 chip. > > I'll just start trying. The Z80 is pretty simple, that makes it a lot easier to get started with. Good exercise. > >> I believe I have found ways to read internal signals of modules in VHDL. >> I think this is a simulator feature rather than a language feature >> though. Verilog supports this directly. >> >> What issues are you concerned about? > > I normally test internals (in software, that is), since it will make determining what broke easier then just testing the public interfaces. > I probably just need to get started, and not think about this to much. Ok -- Rick From newsfish@newsfish Thu Aug 1 00:35:27 2024 X-Received: by 10.129.96.134 with SMTP id u128mr13500779ywb.40.1448054854783; Fri, 20 Nov 2015 13:27:34 -0800 (PST) X-Received: by 10.50.97.38 with SMTP id dx6mr121134igb.9.1448054854743; Fri, 20 Nov 2015 13:27:34 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!b51no1083761qgf.0!news-out.google.com!f6ni8529igq.0!nntp.google.com!i2no5531229igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Nov 2015 13:27:33 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.140.203.78; posting-account=iESOMQoAAACXEEKUmGCCRrNO_51JL7Al NNTP-Posting-Host: 86.140.203.78 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <59d21b01-b6bc-43b4-bbc8-1e078f89927b@googlegroups.com> Subject: Re: creating program From: pault.eg@googlemail.com Injection-Date: Fri, 20 Nov 2015 21:27:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5412 X-Received-Body-CRC: 1168188575 Xref: news.eternal-september.org comp.lang.vhdl:4147 On Sunday, November 15, 2015 at 6:57:33 PM UTC, Lars Asplund wrote: > @Andy > =20 > > As far as testing, we use a continuous integration flow with Jenkins. O= ur testbenches are 100% self-checking (waveforms are for debugging only), a= nd use constrained-random stimulus, while monitoring all DUT outputs for co= mparison in scoreboards with an untimed reference model. Coverage models fo= r the stimulus ensure we cover what we need to cover in terms of functional= ity. This can all be done in SystemVerilog using UVM, or in VHDL using OSVV= M. We do not do unit level testing. We may use test versions of DUT entitie= s to make it easier to get to an internal entity's functionality, but we al= ways use the DUT interface to simplify the stimulus application (drivers) a= nd response capture (monitors). The scoreboards hook up to the monitors, no= t the DUT, and to the reference model. Monitors can also verify interface p= rotocols, without having to know anything about the stimulus or expected re= sponse. >=20 > When I promote the use of VUnit it's usually very easy when people have a= previous experience with unit testing tools for SW. They know what to expe= ct and they know that they want it. It seems to me that you may have such e= xperience but decided to do only top level testing anyway. That makes me a = bit curious about the reasons. Are you working as a verification engineer, = RTL designer, or both? >=20 > Anyway, it might be interesting for you to know that VUnit doesn't know w= hat a unit is, it doesn't care about your test strategy as long as your tes= tbenches are self-checking, and it has support for Jenkins integration. So = if you wrap your testbench in this >=20 > library vunit_lib; > context vunit_lib.vunit_context; >=20 > entity tb_example is > generic (runner_cfg : runner_cfg_t); > end entity; >=20 > architecture tb of tb_example is > begin > main : process > begin > test_runner_setup(runner, runner_cfg); >=20 > -- Put whatever your "main process" is doing here >=20 > test_runner_cleanup(runner); -- Simulation ends here > end process; >=20 > -- Put your DUT, scoreboards, monitors, reference models here >=20 > end architecture; >=20 > and create a python script (run.py) like this >=20 > from vunit import VUnit > vu =3D VUnit.from_argv() > lib =3D vu.add_library("lib") > lib.add_source_files("*.vhd") >=20 > # Create as many libraries as needed and add source files to them >=20 > vu.main() >=20 > and do >=20 > python run.py -x test_report.xml >=20 > from the command line you will have something that (assuming you're using= ModelSim, Riviera-PRO, Active-HDL or GHDL) compiles your source files in d= ependency order based on what has been modified. The script then finds and = runs your testbench(es) and generates a test report on "Jenkins format" >=20 > Regards, >=20 > Lars Hmmm, I don't really do too much with this now, but there are echos in what= you are doing with what I was doing with this: http://www.p-code.org/ttask.html For automatic checking I was just logging to files with this: http://www.p-code.org/tbmsgs.html As you can see that's pretty basic, the VHDL code is here: http://www.p-code.org/tbmsgs.fossil/artifact/19271c770959048b There is also a verilog version of that if you root around. I see you are using vunit as a build tool as well as the testing framework.= I did that different, as I kept the build system separate. Well, as much a= s I could, because the build system scans log files and prints a summary if= it finds tbmsgs messages. But that can be easily changed with customized e= xtensions (see bottom of first link). From newsfish@newsfish Thu Aug 1 00:35:27 2024 X-Received: by 10.140.171.137 with SMTP id r131mr7656118qhr.5.1448308961482; Mon, 23 Nov 2015 12:02:41 -0800 (PST) X-Received: by 10.50.78.134 with SMTP id b6mr362912igx.4.1448308961449; Mon, 23 Nov 2015 12:02:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!b51no1681477qgf.0!news-out.google.com!f6ni11368igq.0!nntp.google.com!mv3no835575igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Nov 2015 12:02:40 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81852379-c448-4f2d-8149-65266d494bc3@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Mon, 23 Nov 2015 20:02:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4148 On Sunday, November 15, 2015 at 12:57:33 PM UTC-6, Lars Asplund wrote: > @Andy > When I promote the use of VUnit it's usually very easy when people have a= previous experience with unit testing tools for SW. They know what to expe= ct and they know that they want it. It seems to me that you may have such e= xperience but decided to do only top level testing anyway. That makes me a = bit curious about the reasons. Are you working as a verification engineer, = RTL designer, or both? Mostly design, but some verification experience.=20 Perhaps I should say, we use unit level testing, but only at the top (desig= n) level! Under SW testing standards, we test using the production compiler= on representative production HW, or as close as practical. Simulation and = modeling are forms of analysis, not testing, strictly speaking.=20 Given that the simulator and synthesis, place & route tool are very differe= nt "compilers", and the simulation server bears no resemblance to the targe= t HW, the only way to perform testing is by using verification systems that= capture stimulus & DUT response from simulation(s), and then play that sti= mulus against the real programmed FPGA while comparing the FPGA's response = to the simulation response, using Aldec CTS for example. So, if we have to show, under a SW test approach, how all of our verificati= on coverage goals are met, on representative HW, then we have to attain tha= t coverage by stimulating the RTL at the top level during simulation. Then = we replay that stimulus to the programmed device, and show that the DUT res= ponse was the same as simulated. Note that the simulation showed the respon= se met requirements. Other than speeding up some simulations, there is no advantage for us in lo= wer level unit testing (directly stimulating/monitoring a lower level modul= e at its ports). We still have to test it via the top level (device) interf= ace. There are still some functional coverage items we cannot cover at the = hardware level, especially things that require "white box" verification, li= ke FSM illegal state recovery, internal memory EDAC, etc. Andy From newsfish@newsfish Thu Aug 1 00:35:27 2024 X-Received: by 10.140.240.193 with SMTP id l184mr19549158qhc.4.1448309648654; Mon, 23 Nov 2015 12:14:08 -0800 (PST) X-Received: by 10.50.2.6 with SMTP id 6mr364522igq.5.1448309648615; Mon, 23 Nov 2015 12:14:08 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!b51no1686814qgf.0!news-out.google.com!f6ni11381igq.0!nntp.google.com!mv3no1408925igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Nov 2015 12:14:08 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Andy Injection-Date: Mon, 23 Nov 2015 20:14:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2581 X-Received-Body-CRC: 75580551 Xref: news.eternal-september.org comp.lang.vhdl:4149 On Monday, November 16, 2015 at 11:40:32 AM UTC-6, rickman wrote: > On 11/16/2015 2:22 AM, Igmar Palsenberg wrote: > > In my experience, a good IDE can help. Sigasi helps a lot, it also has = features that at least the Quartus editor doesn't have. >=20 > I've heard a lot of good about Emacs in this regard. >=20 Even the free version of Sigasi is incredibly useful, if you (and your empl= oyer) can tolerate the mandatory talk-back feature in the free version. And= the paid version has LOTS more features. IDE's that are truly language awa= re are extremely valuable.=20 For example, even in the free version, you can set Sigasi to fontify subpro= gram names differently than other text. If it cannot find a matching subpro= gram within scope, WITH MATCHING ARUMENT SIGNATURE, it won't fontify it, te= lling you immediately that you either misspelled it, or misused it with you= r arguments/types.=20 Andy From newsfish@newsfish Thu Aug 1 00:35:28 2024 X-Received: by 10.50.36.34 with SMTP id n2mr16307441igj.8.1448315649038; Mon, 23 Nov 2015 13:54:09 -0800 (PST) X-Received: by 10.50.79.233 with SMTP id m9mr82890igx.8.1448315648981; Mon, 23 Nov 2015 13:54:08 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no1499403igc.0!news-out.google.com!f6ni11442igq.0!nntp.google.com!mv3no1499393igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Nov 2015 13:54:08 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.139.53.224; posting-account=bEKMqAoAAABkm6h82MvoNJf2KpS09xnf NNTP-Posting-Host: 213.139.53.224 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: instruction set behavioural implementation From: kliga Injection-Date: Mon, 23 Nov 2015 21:54:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4150 I have an instruction set of 16 instructions each instruction has its own format, first 4 bits for the op code if opcode =0000 then add if opcode =0001 then sub i need to write vhdl code in xilinix (behavioral code) for this instruction set. please i need help. From newsfish@newsfish Thu Aug 1 00:35:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: instruction set behavioural implementation Date: Mon, 23 Nov 2015 17:10:52 -0500 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 23 Nov 2015 22:08:32 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="30877"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+UciXIi8XD4cLTieTfkMBj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:p+YzftCDwiPriEoVbw4f3UHzDa0= Xref: news.eternal-september.org comp.lang.vhdl:4151 On 11/23/2015 4:54 PM, kliga wrote: > I have an instruction set of 16 instructions > each instruction has its own format, first 4 bits for the op code > if opcode =0000 then add > if opcode =0001 then sub > > i need to write vhdl code in xilinix (behavioral code) for this instruction set. > > please i need help. What does your text book say? What logical units does your design have? Do you understand what a processor is supposed to do? Do you know how to code in VHDL? -- Rick From newsfish@newsfish Thu Aug 1 00:35:28 2024 X-Received: by 10.129.136.68 with SMTP id y65mr29421855ywf.53.1448360650808; Tue, 24 Nov 2015 02:24:10 -0800 (PST) X-Received: by 10.50.134.69 with SMTP id pi5mr415822igb.5.1448360650775; Tue, 24 Nov 2015 02:24:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f78no1914350qge.1!news-out.google.com!f6ni11933igq.0!nntp.google.com!mv3no1248680igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Nov 2015 02:24:10 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.78.98.142; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 87.78.98.142 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8ac33f4a-c921-4637-8314-4a3b890cc8da@googlegroups.com> Subject: Re: instruction set behavioural implementation From: Nikolaos Kavvadias Injection-Date: Tue, 24 Nov 2015 10:24:10 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4152 Hi kliga=20 if you really mean it to use a behavioral model for your processor, you wil= l probably end-up with an ASMD/FSMD kind of design. You might consult my be= havioral model for MU0 (7-/8-instruction very-simple 16-bit processor) from= : https://github.com/nkkav/mu0/blob/master/rtl/vhdl/mu0_behav.vhd You will see the concept; introducing initial contents to memory, decoding = and execution of each behavior. The entire mu0 project is here: https://github.com/nkkav/mu0/ Best regards Nikolaos Kavvadias =CE=A4=CE=B7 =CE=94=CE=B5=CF=85=CF=84=CE=AD=CF=81=CE=B1, 23 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2015 - 11:10:56 =CE=BC.=CE=BC. UTC+= 1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 rickman =CE=AD=CE=B3= =CF=81=CE=B1=CF=88=CE=B5: > On 11/23/2015 4:54 PM, kliga wrote: > > I have an instruction set of 16 instructions > > each instruction has its own format, first 4 bits for the op code > > if opcode =3D0000 then add > > if opcode =3D0001 then sub > > > > i need to write vhdl code in xilinix (behavioral code) for this instruc= tion set. > > > > please i need help. >=20 > What does your text book say? What logical units does your design have?= =20 > Do you understand what a processor is supposed to do? Do you know how= =20 > to code in VHDL? >=20 > --=20 >=20 > Rick From newsfish@newsfish Thu Aug 1 00:35:29 2024 X-Received: by 10.129.83.85 with SMTP id h82mr40499385ywb.0.1448557343152; Thu, 26 Nov 2015 09:02:23 -0800 (PST) X-Received: by 10.50.79.233 with SMTP id m9mr66714igx.8.1448557343124; Thu, 26 Nov 2015 09:02:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!f78no3046898qge.1!news-out.google.com!f6ni13953igq.0!nntp.google.com!mv3no3293300igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Nov 2015 09:02:22 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> Subject: Re: creating program From: Lars Asplund Injection-Date: Thu, 26 Nov 2015 17:02:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 55 Xref: news.eternal-september.org comp.lang.vhdl:4153 @Andy Different standards have different opinions on unit testing and to what ext= ent unit test results can be used to prove correctness of a design. Even if= you're allowed to use them you might be required to motivate why the resul= ts gained from a test run in a non-product environment is valid for the rea= l thing as well. Anyway, the key value of unit testing isn't in building test coverage, it's= in the productivity and design quality boost. A fully automated unit test = methodology enables short code/test cycles such that a developer can test f= requently and start to test early. With early and continuous feedback it's = much easier to keep the work on track considering that most people produce = bugs, misinterpret requirements and make bad design decisions on a daily ba= sis. If you only test at the system level you can't test early and frequent= ly, partly because there is a delay before there is a system level to test = at all, partly because there is a delay before an already existing system i= s compatible with your new piece of code, and partly because system level t= esting is slower. There are number of problems with this and the significan= ce depends on project size=20 1. A bug discovered late might not affect you much if it's something as sim= ple as a faulty value of a constant. But if the bug reveals a design flaw t= here is a risk that you have had the time to add a considerable amount of c= ode based on that design and have to make significant changes. 2. A bug released to be integrated with other code before system testing ca= n take place can cause significant harm. We all know this but here are some= personal experiences. After you release your bug there is a delay before t= he code is used at all because not all teams are synchronized. When the cod= e is used and the bug starts to show people spend time debugging their own = code and there is delay before the bug report finds its way to your team. O= nce there it's often incomplete, information is missing to recreate and deb= ug the problem. Meanwhile team schedules are slipping and workarounds are a= dded to not stop progress. Once the root cause has been fixed and the worka= rounds can be removed it turns out that newly written code depends on these= workarounds so more work is needed before development can proceed smoothly= . Unfortunately, a workaround was part of a customer release and now they r= ely on it which becomes apparent when you make the next release. They are n= ot willing to take the consequences of removing that workaround on short no= tice so you end up supporting two different variants. At some point, often = much later, all dependencies on the workaround are gone. Someone finds the = FIXME in the code but the memory of why it was introduced is gone or in the= heads of people no longer available. Potentially dead code is bad practice= so it has to be investigated to decide if it can be removed or not. And so= on... In the same way that the lint support of Sigasi adds value by providing con= tinuous feedback based on static code analysis unit testing adds value by p= roviding continuous feedback based on dynamic code analysis. Testing at unit level also drives design. Creating test cases for the units= forces you to think about clear functional responsibilities for that unit.= This promotes strong cohesion of the unit and loose coupling to other unit= s which are signs of a good (readable and maintainable) design. /Lars From newsfish@newsfish Thu Aug 1 00:35:29 2024 X-Received: by 10.107.19.41 with SMTP id b41mr59817171ioj.5.1448911072225; Mon, 30 Nov 2015 11:17:52 -0800 (PST) X-Received: by 10.50.153.76 with SMTP id ve12mr78971igb.4.1448911072207; Mon, 30 Nov 2015 11:17:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no8311040igc.0!news-out.google.com!l1ni639igd.0!nntp.google.com!mv3no8311036igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Nov 2015 11:17:51 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.139.53.195; posting-account=bEKMqAoAAABkm6h82MvoNJf2KpS09xnf NNTP-Posting-Host: 213.139.53.195 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2d3eba50-4c0d-43ad-8af0-7dfc0148f78a@googlegroups.com> Subject: 16 bit risc processor in VHDL From: kliga Injection-Date: Mon, 30 Nov 2015 19:17:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4154 Hi, I need to write behavioral VHDL code for RISC instruction set that contains 8 instructions of each length is 16 bits. there are 3 types of instructions for these 8 instructions the 3 MSB of each instruction is for operation code. i am using xilinx ISE. this is sample of my code, i need your help library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity alu is generic ( MAXWIDTH : integer := 16; MAXDEPTH : integer := 12 ); end alu; architecture Behavioral of alu is -- CONSTANTS DECLARATION constant ADD : std_logic_vector(2 downto 0) := "000"; constant ADDI : std_logic_vector(2 downto 0) := "001"; constant NND : std_logic_vector(2 downto 0) := "010"; constant LUI : std_logic_vector(2 downto 0) := "011"; constant SW : std_logic_vector(2 downto 0) := "100"; constant LW : std_logic_vector(2 downto 0) := "101"; constant BEQ : std_logic_vector(2 downto 0) := "110"; constant JALR : std_logic_vector(2 downto 0) := "111"; -- SIGNALS DECLARATION signal opcode : std_logic_vector(MAXWIDTH-1 downto MAXWIDTH-3); signal regA : std_logic_vector(MAXWIDTH-4 downto MAXWIDTH-6); signal regB : std_logic_vector(MAXWIDTH-7 downto MAXWIDTH-5); signal regC : std_logic_vector(MAXWIDTH-14 downto 0); signal imm7: std_logic_vector(MAXWIDTH-10 downto 0); signal imm10: std_logic_vector(MAXWIDTH-7 downto 0); signal pc_reg : std_logic_vector(MAXWIDTH-1 downto 0); signal pc_next : std_logic_vector(MAXWIDTH-1 downto 0); signal ir_reg : std_logic_vector(MAXWIDTH-1 downto 0); signal ir_next : std_logic_vector(MAXWIDTH-1 downto 0); signal acc_reg : std_logic_vector(MAXWIDTH-1 downto 0); signal acc_next : std_logic_vector(MAXWIDTH-1 downto 0); begin process ( pc_reg, pc_next, ir_reg, ir_next, acc_reg, acc_next ) variable opcode_v : std_logic_vector(2 downto 0); begin opcode <= ir_reg(MAXWIDTH-1 downto MAXWIDTH-3); regA <= ir_reg(MAXWIDTH-4 downto MAXWIDTH-6); regB <= ir_reg(MAXWIDTH-7 downto MAXWIDTH-5); regC <= ir_reg(MAXWIDTH-14 downto 0); imm7 <= ir_reg(MAXWIDTH-10 downto 0); imm10 <= ir_reg(MAXWIDTH-7 downto 0); opcode_v := opcode; case (opcode_v) is when ADD => regA <= regB + regC; when NND => regA <= regB nand regC; when others => pc_next <= pc_reg; end case; end process; end Behavioral From newsfish@newsfish Thu Aug 1 00:35:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: 16 bit risc processor in VHDL Date: Mon, 30 Nov 2015 20:26:04 -0000 (UTC) Organization: A noiseless patient Spider Lines: 23 Message-ID: References: <2d3eba50-4c0d-43ad-8af0-7dfc0148f78a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 30 Nov 2015 20:26:04 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="e1519d2450e35d4c7974a956276402c0"; logging-data="23296"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Vv32sN9AH0mVyD8ep2Z85" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:JvvhAOKtaSo1rnQwIFcnkkBPxDk= Xref: news.eternal-september.org comp.lang.vhdl:4155 On Mon, 30 Nov 2015 11:17:51 -0800, kliga wrote: > Hi, > I need to write behavioral VHDL code for RISC instruction set that > contains 8 instructions of each length is 16 bits. > there are 3 types of instructions for these 8 instructions the 3 MSB of > each instruction is for operation code. > i am using xilinx ISE. > > this is sample of my code, i need your help library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.numeric_std.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > If you're using numeric_std (which you should be) then you can't also use std_logic_arith and std_logic_unsigned (which have been the wrong answer for over 20 years now.) -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:35:30 2024 X-Received: by 10.98.0.204 with SMTP id 195mr4486293pfa.3.1449601824229; Tue, 08 Dec 2015 11:10:24 -0800 (PST) X-Received: by 10.50.57.100 with SMTP id h4mr538066igq.6.1449601824158; Tue, 08 Dec 2015 11:10:24 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.us.feeder.erje.net!xmission!news.glorb.com!mv3no10608199igc.0!news-out.google.com!f6ni17171igq.0!nntp.google.com!mv3no13486352igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Dec 2015 11:10:23 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=107.182.231.192; posting-account=f7L0LgoAAAA8JEaIfr01EpmKIY2GRrE2 NNTP-Posting-Host: 107.182.231.192 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d31cfc2-7902-4fef-a23a-847bb3d9e3ce@googlegroups.com> Subject: Problem in ALUControl From: Muhammadreza Haghiri Injection-Date: Tue, 08 Dec 2015 19:10:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4156 I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v When I want to compile it, verilog says : ALUControl.v:4: syntax error ALUControl.v:4: error: Invalid variable list in port declaration. What's wrong in 4th line? From newsfish@newsfish Thu Aug 1 00:35:30 2024 X-Received: by 10.13.194.197 with SMTP id e188mr5345786ywd.24.1449613017661; Tue, 08 Dec 2015 14:16:57 -0800 (PST) X-Received: by 10.50.155.8 with SMTP id vs8mr169387igb.10.1449613017592; Tue, 08 Dec 2015 14:16:57 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!b51no7303244qgf.0!news-out.google.com!l1ni838igd.0!nntp.google.com!mv3no13557877igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Dec 2015 14:16:57 -0800 (PST) In-Reply-To: <0d31cfc2-7902-4fef-a23a-847bb3d9e3ce@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=207.47.14.74; posting-account=uuodZAoAAADTv7OvvFk6il3y1Zhg_eZG NNTP-Posting-Host: 207.47.14.74 References: <0d31cfc2-7902-4fef-a23a-847bb3d9e3ce@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Problem in ALUControl From: Gunjan Injection-Date: Tue, 08 Dec 2015 22:16:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1600 X-Received-Body-CRC: 1539981173 Xref: news.eternal-september.org comp.lang.vhdl:4157 On Tuesday, December 8, 2015 at 11:10:27 AM UTC-8, Muhammadreza Haghiri wrote: > I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v > > When I want to compile it, verilog says : > > ALUControl.v:4: syntax error > ALUControl.v:4: error: Invalid variable list in port declaration. > > What's wrong in 4th line? Your 4th line should be as follows output reg [3:0] ALUCtl; //the reg keyword should be after output and not after the size. From newsfish@newsfish Thu Aug 1 00:35:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Problem in ALUControl Date: Tue, 08 Dec 2015 18:08:30 -0500 Organization: Alacron, Inc. Lines: 40 Message-ID: References: <0d31cfc2-7902-4fef-a23a-847bb3d9e3ce@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 8 Dec 2015 23:06:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="11294"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19lmHWWxmQJtWGBSvCaYeOyuQM9X2Ik0j4=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.24) Gecko/20100228 Thunderbird/2.0.0.24 Mnenhy/0.7.6.666 In-Reply-To: Cancel-Lock: sha1:UYjiKe0nMobG/yz88qjM+MOHW+0= Xref: news.eternal-september.org comp.lang.vhdl:4158 Gunjan wrote: > On Tuesday, December 8, 2015 at 11:10:27 AM UTC-8, Muhammadreza Haghiri wrote: >> I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v >> >> When I want to compile it, verilog says : >> >> ALUControl.v:4: syntax error >> ALUControl.v:4: error: Invalid variable list in port declaration. >> >> What's wrong in 4th line? > > > Your 4th line should be as follows > > output reg [3:0] ALUCtl; //the reg keyword should be after output and not after the size. Some other notes: always case (FuncCode) 32: ALUCt1 <= 2; . . . This process has no sensitivity list, which will hang in simulation. In addition, all assignments are non-blocking. This makes no difference to synthesis, however it will probably cause simulation to crash due to memory usage for continuously scheduling the same assignments. At least that's been my experience with ModelSim. I'd suggest writing this like: always @* // Implied sensitivity list equivalent to always @ (FuncCode) case (FuncCode) 32: ALUCt1 = 2; // Blocking assignments are appropriate for combinatorial process . . . default: ALUCt1 = 7; endcase -- Gabor From newsfish@newsfish Thu Aug 1 00:35:31 2024 X-Received: by 10.66.145.193 with SMTP id sw1mr4558124pab.5.1449660341336; Wed, 09 Dec 2015 03:25:41 -0800 (PST) X-Received: by 10.50.30.201 with SMTP id u9mr230114igh.4.1449660341298; Wed, 09 Dec 2015 03:25:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no13755308igc.0!news-out.google.com!f6ni17793igq.0!nntp.google.com!mv3no13755298igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Dec 2015 03:25:40 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.94.233.214; posting-account=bGNCQgoAAAAsD7_lm_EVb4Tntq0BG1_k NNTP-Posting-Host: 134.94.233.214 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7af283d4-336f-4f5c-9c4d-fff4f99526e1@googlegroups.com> Subject: Error in converting code to VHDL From: Jamil Hayder Injection-Date: Wed, 09 Dec 2015 11:25:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4159 Hi, Can some one please help out.Thanks. I am trying to convert below code to VHDL using HDL Coder but getting error. The HDL Coder Block file is also attached .Please can you have a look on it and see whats the mistake in block diagram. x1=[1 2 3 4 5 6 7 8 9]; x2=[3 4 5 6 7 8 9 2 1]; n=length(x1); xc=zeros(2*n-1,1); for i=1:2*n-1 if(i>n) j1=1; k1=2*n-i; j2=i-n+1; k2=n; else j1=n-i+1; k1=n; j2=1; k2=i; end xc(i)=sum(conj(x1(j1:k1)).*x2(j2:k2)); end xc=flipud(xc); Error: Cannot connect to model 'prc4'; please try Update Diagram (Ctrl-D). Error due to multiple causes. Errors occurred during parsing of MATLAB function 'MATLAB Function'(#24) Error in port widths or dimensions. Output port 1 of 'prc4/MATLAB Function/u' is a one dimensional vector with 1 elements. From newsfish@newsfish Thu Aug 1 00:35:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Error in converting code to VHDL Date: Wed, 9 Dec 2015 17:44:21 -0000 (UTC) Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <7af283d4-336f-4f5c-9c4d-fff4f99526e1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 9 Dec 2015 17:44:21 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="28921"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/rUaQBTCJyLAj85Pkw4Pe1qqicdcC4MxY=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:cBUfRSRAne9RGV4V3shwgzcCt6I= Xref: news.eternal-september.org comp.lang.vhdl:4160 On Wed, 09 Dec 2015 03:25:40 -0800, Jamil Hayder wrote: > Hi, Can some one please help out.Thanks. I am trying to convert below > code to VHDL using HDL Coder but getting error. The HDL Coder Block file > is also attached .Please can you have a look on it and see whats the > mistake in block diagram. > > x1=[1 2 3 4 5 6 7 8 9]; > x2=[3 4 5 6 7 8 9 2 1]; etc > > Error: > > Cannot connect to model 'prc4'; please try Update Diagram (Ctrl-D). Since there is no "prc4" in the posted code I doubt that anyone is going to be able to help. However judging by the other message: > Error in port widths or dimensions. Output port 1 of 'prc4/MATLAB > Function/u' is a one dimensional vector with 1 elements. it looks like something in the typeless mess of Matlab code is confusing HDL Coder. You may need to do some explicit type conversions somewhere to resolve the problem. -- Brian From newsfish@newsfish Thu Aug 1 00:35:31 2024 X-Received: by 10.31.169.141 with SMTP id s135mr16567351vke.11.1449866403266; Fri, 11 Dec 2015 12:40:03 -0800 (PST) X-Received: by 10.50.50.148 with SMTP id c20mr211808igo.9.1449866403230; Fri, 11 Dec 2015 12:40:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f78no7875954qge.1!news-out.google.com!f6ni20050igq.0!nntp.google.com!mv3no14873390igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Dec 2015 12:40:02 -0800 (PST) In-Reply-To: <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Andy Injection-Date: Fri, 11 Dec 2015 20:40:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4161 On Thursday, November 26, 2015 at 11:02:27 AM UTC-6, Lars Asplund wrote: > @Andy >=20 > Different standards have different opinions on unit testing and to what e= xtent unit test results can be used to prove correctness of a design. Even = if you're allowed to use them you might be required to motivate why the res= ults gained from a test run in a non-product environment is valid for the r= eal thing as well. >=20 > If you only test at the system level you can't test early and frequently,= partly because there is a delay before there is a system level to test at = all, partly because there is a delay before an already existing system is c= ompatible with your new piece of code, and partly because system level test= ing is slower. There are number of problems with this and the significance = depends on project size=20 >=20 ... > /Lars Lars, Sorry it's been a while... First off, when I say "system level" I mean "FPGA level". With that in mind= ... We don't wait for the whole system to be anywhere near complete before we t= est. See Jim Lewis' paper "Accelerating Verification Through Pr= e-Use of System-Level Testbench Components". We use this approach to get un= its integrated into a partially implemented system & test early, with no wa= sted time developing unit level tests that won't need to be used again. The dificulty in unit level testing is the quantity of unique interfaces fo= r all the units, and all the monitors, drivers and often-unique transaction= s required for them. By developing the units in a sensible order to allow a= testbench with a system-level interface to exercise the functionality prov= ided by lower level units, we can test early and often with one TB <-> DUT = interface, drivers, monitors, etc. This approach also makes it easier to refine the system architecture for im= proved performance, utilization, functionality, etc. because our verificati= on is immune to changes in unit level interfaces that change with the archi= tecture. Andy From newsfish@newsfish Thu Aug 1 00:35:32 2024 X-Received: by 10.182.112.233 with SMTP id it9mr18113627obb.45.1449891855010; Fri, 11 Dec 2015 19:44:15 -0800 (PST) X-Received: by 10.50.78.232 with SMTP id e8mr238483igx.6.1449891854970; Fri, 11 Dec 2015 19:44:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no14977372igc.0!news-out.google.com!l1ni620igd.0!nntp.google.com!mv3no14977371igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Dec 2015 19:44:14 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> Subject: Question regarding a clock divider algorithm From: michael6866 Injection-Date: Sat, 12 Dec 2015 03:44:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4162 Hi, I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: clkd_div = DFF_R1 | DFF_F5 Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? Thanks, Michael From newsfish@newsfish Thu Aug 1 00:35:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question regarding a clock divider algorithm Date: Sat, 12 Dec 2015 02:41:25 -0500 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 12 Dec 2015 07:38:54 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="16764"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX188xiTRfGinu+m5qEmoLMIZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> Cancel-Lock: sha1:q3jrGnAYoFd9sNj6E58tkiF8uLU= Xref: news.eternal-september.org comp.lang.vhdl:4163 On 12/11/2015 10:44 PM, michael6866 wrote: > Hi, > > I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: > > 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" > 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. > 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. > 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: > clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) > > I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: > clkd_div = DFF_R1 | DFF_F5 > > Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? I haven't analyzed the algorithm in detail, but it sounds like they *are* attempting to approach a 50% duty cycle. ((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will produce a pulse two clock cycles wide starting on the falling edge of cycle 5. That is 4.5 clock cycles from rising edge of the first pulse to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6 are pulses that cover the transition of the other two inputs to those pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not too far from 50%. Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges of the pulses, but the duty cycle will only be 2/9 or 22.2%. -- Rick From newsfish@newsfish Thu Aug 1 00:35:32 2024 X-Received: by 10.107.151.78 with SMTP id z75mr19885853iod.31.1449936303814; Sat, 12 Dec 2015 08:05:03 -0800 (PST) X-Received: by 10.50.28.20 with SMTP id x20mr271672igg.3.1449936303798; Sat, 12 Dec 2015 08:05:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no15187236igc.0!news-out.google.com!f6ni20857igq.0!nntp.google.com!mv3no11670833igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 12 Dec 2015 08:05:02 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> Subject: Re: Question regarding a clock divider algorithm From: michael6866 Injection-Date: Sat, 12 Dec 2015 16:05:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4164 On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote: > On 12/11/2015 10:44 PM, michael6866 wrote: > > Hi, > > > > I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: > > > > 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" > > 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. > > 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. > > 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: > > clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) > > > > I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: > > clkd_div = DFF_R1 | DFF_F5 > > > > Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? > > I haven't analyzed the algorithm in detail, but it sounds like they > *are* attempting to approach a 50% duty cycle. > > ((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide > starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will > produce a pulse two clock cycles wide starting on the falling edge of > cycle 5. That is 4.5 clock cycles from rising edge of the first pulse > to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6 > are pulses that cover the transition of the other two inputs to those > pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not > too far from 50%. > > Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges > of the pulses, but the duty cycle will only be 2/9 or 22.2%. > > -- > > Rick Hi Rick, Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? Michael From newsfish@newsfish Thu Aug 1 00:35:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question regarding a clock divider algorithm Date: Sat, 12 Dec 2015 12:03:52 -0500 Organization: A noiseless patient Spider Lines: 57 Message-ID: References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 12 Dec 2015 17:01:20 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="b5ace21dac962f67a10de6fe9a7b4cc1"; logging-data="3581"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ZeA7MFEuj9KFw5rmx6XJ4" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> Cancel-Lock: sha1:FNj82xg55Z3oW48aaL5WaTiTLJI= Xref: news.eternal-september.org comp.lang.vhdl:4165 On 12/12/2015 11:05 AM, michael6866 wrote: > On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote: >> On 12/11/2015 10:44 PM, michael6866 wrote: >>> Hi, >>> >>> I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: >>> >>> 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" >>> 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. >>> 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. >>> 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: >>> clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) >>> >>> I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: >>> clkd_div = DFF_R1 | DFF_F5 >>> >>> Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? >> >> I haven't analyzed the algorithm in detail, but it sounds like they >> *are* attempting to approach a 50% duty cycle. >> >> ((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide >> starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will >> produce a pulse two clock cycles wide starting on the falling edge of >> cycle 5. That is 4.5 clock cycles from rising edge of the first pulse >> to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6 >> are pulses that cover the transition of the other two inputs to those >> pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not >> too far from 50%. >> >> Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges >> of the pulses, but the duty cycle will only be 2/9 or 22.2%. >> >> -- >> >> Rick > > Hi Rick, > > Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? Oscillator outputs are never exactly 50%. Even on crystal oscillators and such the duty cycle is often specified to be in the range of 45/55 to 55/45. To get closer to 50% you can use a 2x rate and divide by 2 with a FF, but even that will have some skew due to the asymmetry of the drive. Getting close to a 50% duty cycle can matter to some circuits depending on how they are designed. If you can't get close to 50% then you need to use a circuit independent of duty cycle. You asked why that design was the way it was. I expect it was driving something where the duty cycle mattered. -- Rick From newsfish@newsfish Thu Aug 1 00:35:33 2024 X-Received: by 10.129.0.212 with SMTP id 203mr15811249ywa.19.1449940152577; Sat, 12 Dec 2015 09:09:12 -0800 (PST) X-Received: by 10.50.57.84 with SMTP id g20mr274988igq.3.1449940152547; Sat, 12 Dec 2015 09:09:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!g67no85400qgd.1!news-out.google.com!f6ni20912igq.0!nntp.google.com!mv3no15210100igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 12 Dec 2015 09:09:11 -0800 (PST) In-Reply-To: <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1270d936-204c-4de5-977e-5f4d06d64699@googlegroups.com> Subject: Re: Question regarding a clock divider algorithm From: KJ Injection-Date: Sat, 12 Dec 2015 17:09:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1692 X-Received-Body-CRC: 2418047743 Xref: news.eternal-september.org comp.lang.vhdl:4166 On Saturday, December 12, 2015 at 11:05:07 AM UTC-5, michael6866 wrote: > But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? > Duty cycle is usually only important if the part receiving the signal has a minimum high or low pulse time requirement. Maybe you can meet the requirement with a 44% duty cycle, but not a 22% duty cycle as an example. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Szakacs Newsgroups: comp.lang.vhdl Subject: Re: Question regarding a clock divider algorithm Date: Sat, 12 Dec 2015 12:23:57 -0500 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> <1270d936-204c-4de5-977e-5f4d06d64699@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 12 Dec 2015 17:21:43 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9bd0ba8c53fd0f12dc2ce700b744f948"; logging-data="8108"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ZAuYj9Y6DJWbnnj/Nmf3x" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <1270d936-204c-4de5-977e-5f4d06d64699@googlegroups.com> Cancel-Lock: sha1:4GqHzdc6omuHPY76pBZrM2GLhfI= Xref: news.eternal-september.org comp.lang.vhdl:4167 On 12/12/2015 12:09 PM, KJ wrote: > On Saturday, December 12, 2015 at 11:05:07 AM UTC-5, michael6866 wrote: >> But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? >> > Duty cycle is usually only important if the part receiving the signal has a minimum high or low pulse time requirement. Maybe you can meet the requirement with a 44% duty cycle, but not a 22% duty cycle as an example. > > Kevin Jennings > It's also important if you use both clock edges like for DDR interfaces. This 2/9 clock circuit is duty cyle dependent as well. Any input clock deviation from 50% introduces jitter on the output clocks, since the time from one edge to the next depends on opposite input clock edges. If you wanted to take the output of this circuit and use both edges, e.g. to multiply by 2/9 again, the output of that circuit will be jittery even given a 50% input clock and no asymmetry in the clock divider itself. -- Gabor From newsfish@newsfish Thu Aug 1 00:35:34 2024 X-Received: by 10.182.20.242 with SMTP id q18mr3389419obe.2.1449951074901; Sat, 12 Dec 2015 12:11:14 -0800 (PST) X-Received: by 10.50.134.69 with SMTP id pi5mr282125igb.5.1449951074882; Sat, 12 Dec 2015 12:11:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!mv3no11730227igc.0!news-out.google.com!f6ni21027igq.0!nntp.google.com!mv3no15277658igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 12 Dec 2015 12:11:13 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46ac0d08-5859-43c4-8c11-68e2f24dbfcd@googlegroups.com> Subject: Re: Question regarding a clock divider algorithm From: michael6866 Injection-Date: Sat, 12 Dec 2015 20:11:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 4496 X-Received-Body-CRC: 260085835 Xref: news.eternal-september.org comp.lang.vhdl:4168 On Saturday, December 12, 2015 at 12:03:53 PM UTC-5, rickman wrote: > On 12/12/2015 11:05 AM, michael6866 wrote: > > On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote: > >> On 12/11/2015 10:44 PM, michael6866 wrote: > >>> Hi, > >>> > >>> I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: > >>> > >>> 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" > >>> 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. > >>> 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. > >>> 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: > >>> clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) > >>> > >>> I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: > >>> clkd_div = DFF_R1 | DFF_F5 > >>> > >>> Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? > >> > >> I haven't analyzed the algorithm in detail, but it sounds like they > >> *are* attempting to approach a 50% duty cycle. > >> > >> ((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide > >> starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will > >> produce a pulse two clock cycles wide starting on the falling edge of > >> cycle 5. That is 4.5 clock cycles from rising edge of the first pulse > >> to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6 > >> are pulses that cover the transition of the other two inputs to those > >> pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not > >> too far from 50%. > >> > >> Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges > >> of the pulses, but the duty cycle will only be 2/9 or 22.2%. > >> > >> -- > >> > >> Rick > > > > Hi Rick, > > > > Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? > > Oscillator outputs are never exactly 50%. Even on crystal oscillators > and such the duty cycle is often specified to be in the range of 45/55 > to 55/45. To get closer to 50% you can use a 2x rate and divide by 2 > with a FF, but even that will have some skew due to the asymmetry of the > drive. > > Getting close to a 50% duty cycle can matter to some circuits depending > on how they are designed. If you can't get close to 50% then you need > to use a circuit independent of duty cycle. > > You asked why that design was the way it was. I expect it was driving > something where the duty cycle mattered. > > -- > > Rick Thanks Rick (and Kevin and Gabor). The paper itself doesn't mention any other module it drives. It's only about the clock divider itself. But I think your explanation makes sense. Michael From newsfish@newsfish Thu Aug 1 00:35:34 2024 X-Received: by 10.31.160.210 with SMTP id j201mr44948097vke.1.1450384163222; Thu, 17 Dec 2015 12:29:23 -0800 (PST) X-Received: by 10.50.114.163 with SMTP id jh3mr147163igb.1.1450384163190; Thu, 17 Dec 2015 12:29:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!95no12273qgm.0!news-out.google.com!l1ni6409igd.0!nntp.google.com!mv3no17513272igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Dec 2015 12:29:22 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.234.122.12; posting-account=fU5vggoAAADRS9PxgZdxgAofsoUGMF84 NNTP-Posting-Host: 73.234.122.12 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Subject: Am looking for arcitecture of below code as a Finite State Machine (Urgent) From: disturbedspace1@gmail.com Injection-Date: Thu, 17 Dec 2015 20:29:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4169 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; ENTITY debounce IS PORT(pb, clock_100Hz : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END debounce; ARCHITECTURE a OF debounce IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL PREVIOUS : STD_LOGIC; BEGIN -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. -- Debounce clock should be approximately 10ms process begin wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); SHIFT_PB(3) <= NOT PB; If SHIFT_PB(3 Downto 0)="0000" THEN PB_DEBOUNCED <= '0'; PREVIOUS <= '0'; ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN PB_DEBOUNCED <= '1'; PREVIOUS <= '1'; ELSE PB_DEBOUNCED <= PREVIOUS; End if; end process; end a; From newsfish@newsfish Thu Aug 1 00:35:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Thu, 17 Dec 2015 21:04:34 -0500 Organization: A noiseless patient Spider Lines: 103 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Dec 2015 02:02:04 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="3603"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+G8UlUTGuGGmG+P92Vl0zy" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Cancel-Lock: sha1:qjRCdDzWyPV+4NTyMeIjy5HIT7A= Xref: news.eternal-september.org comp.lang.vhdl:4170 On 12/17/2015 3:29 PM, disturbedspace1@gmail.com wrote: > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > ENTITY debounce IS > PORT(pb, clock_100Hz : IN STD_LOGIC; > pb_debounced : OUT STD_LOGIC); > END debounce; > ARCHITECTURE a OF debounce IS > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > SIGNAL PREVIOUS : STD_LOGIC; > BEGIN > -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. > -- Debounce clock should be approximately 10ms > process > begin > wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > SHIFT_PB(3) <= NOT PB; > If SHIFT_PB(3 Downto 0)="0000" THEN > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN > PB_DEBOUNCED <= '1'; > PREVIOUS <= '1'; > ELSE > PB_DEBOUNCED <= PREVIOUS; > End if; > end process; > end a; I rewrote the code to separate the state signals from the shift register. Otherwise I'm not sure what you want to see. Are you looking for some specific format for the FSM? There is no special format a state machine has to be coded in unless your professor insists. I didn't test any of this code. Oh, you should not use the STD_LOGIC_UNSIGNED library. It is not a standard and works differently with different vendors. Use the NUMERIC_STD library which *is* an IEEE standard. Also, use "rising_edge()" instead of (clock_100Hz'EVENT) AND (clock_100Hz = '1'). Lastly, using a wait statement may work for synthesizable logic, but is not a great idea. Use a conditional and I expect your circuit could use a reset. This is a *very* standard form and is well supported. I did find your signal "PREVIOUS" is superfluous. It is always assigned the same value as PB_DEBOUNCED. Either you missed something in your algorithm or you added this thinking it would do something useful but never made it do that. If you want the code to be in the form of a case statement based on the state, you just need to make the conditionals specific to a state, but I don't see any value in that. Rick library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.NUMERIC_STD.all; ENTITY debounce IS PORT(pb, clock_100Hz, Rst : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END debounce; ARCHITECTURE a OF debounce IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL PREVIOUS : STD_LOGIC; BEGIN -- Debounce Button: Filters out mechanical switch bounce for ~40ms. -- Debounce clock should be approximately 10ms process (clock_100Hz, Rst) begin if ('1' = Rst) then SHIFT_PB <= (others => '0'); elsif (rising_edge(clock_100Hz)) then SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); SHIFT_PB(3) <= NOT PB; end if; end process; process (clock_100Hz, Rst) begin if ('1' = Rst) then PB_DEBOUNCED <= '0'; PREVIOUS <= '0'; elsif (rising_edge(clock_100Hz)) then if (SHIFT_PB = (others => '0')) then PB_DEBOUNCED <= '0'; PREVIOUS <= '0'; elsif (SHIFT_PB = (others => '1')) then PB_DEBOUNCED <= '1'; PREVIOUS <= '1'; else PB_DEBOUNCED <= PREVIOUS; end if; end process; end a; -- Rick From newsfish@newsfish Thu Aug 1 00:35:35 2024 X-Received: by 10.50.147.67 with SMTP id ti3mr323151igb.13.1450412702111; Thu, 17 Dec 2015 20:25:02 -0800 (PST) X-Received: by 10.50.57.100 with SMTP id h4mr6146igq.6.1450412702096; Thu, 17 Dec 2015 20:25:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no17631644igc.0!news-out.google.com!f6ni26233igq.0!nntp.google.com!mv3no17631633igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Dec 2015 20:25:01 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.234.122.12; posting-account=fU5vggoAAADRS9PxgZdxgAofsoUGMF84 NNTP-Posting-Host: 73.234.122.12 References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <87248515-1856-4c96-97e8-4d89a908fb6f@googlegroups.com> Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) From: disturbedspace1@gmail.com Injection-Date: Fri, 18 Dec 2015 04:25:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4171 On Thursday, December 17, 2015 at 9:04:39 PM UTC-5, rickman wrote: > On 12/17/2015 3:29 PM, disturbedspace1@gmail.com wrote: > > library IEEE; > > use IEEE.STD_LOGIC_1164.all; > > use IEEE.STD_LOGIC_ARITH.all; > > use IEEE.STD_LOGIC_UNSIGNED.all; > > ENTITY debounce IS > > PORT(pb, clock_100Hz : IN STD_LOGIC; > > pb_debounced : OUT STD_LOGIC); > > END debounce; > > ARCHITECTURE a OF debounce IS > > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > > SIGNAL PREVIOUS : STD_LOGIC; > > BEGIN > > -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. > > -- Debounce clock should be approximately 10ms > > process > > begin > > wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); > > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > > SHIFT_PB(3) <= NOT PB; > > If SHIFT_PB(3 Downto 0)="0000" THEN > > PB_DEBOUNCED <= '0'; > > PREVIOUS <= '0'; > > ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN > > PB_DEBOUNCED <= '1'; > > PREVIOUS <= '1'; > > ELSE > > PB_DEBOUNCED <= PREVIOUS; > > End if; > > end process; > > end a; > > I rewrote the code to separate the state signals from the shift > register. Otherwise I'm not sure what you want to see. Are you looking > for some specific format for the FSM? There is no special format a > state machine has to be coded in unless your professor insists. I > didn't test any of this code. Oh, you should not use the > STD_LOGIC_UNSIGNED library. It is not a standard and works differently > with different vendors. Use the NUMERIC_STD library which *is* an IEEE > standard. Also, use "rising_edge()" instead of (clock_100Hz'EVENT) AND > (clock_100Hz = '1'). Lastly, using a wait statement may work for > synthesizable logic, but is not a great idea. Use a conditional and I > expect your circuit could use a reset. This is a *very* standard form > and is well supported. > > I did find your signal "PREVIOUS" is superfluous. It is always assigned > the same value as PB_DEBOUNCED. Either you missed something in your > algorithm or you added this thinking it would do something useful but > never made it do that. > > If you want the code to be in the form of a case statement based on the > state, you just need to make the conditionals specific to a state, but I > don't see any value in that. > > Rick > > > > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.NUMERIC_STD.all; > ENTITY debounce IS > PORT(pb, clock_100Hz, Rst : IN STD_LOGIC; > pb_debounced : OUT STD_LOGIC); > END debounce; > ARCHITECTURE a OF debounce IS > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > SIGNAL PREVIOUS : STD_LOGIC; > BEGIN > -- Debounce Button: Filters out mechanical switch bounce for ~40ms. > -- Debounce clock should be approximately 10ms > process (clock_100Hz, Rst) > begin > if ('1' = Rst) then > SHIFT_PB <= (others => '0'); > elsif (rising_edge(clock_100Hz)) then > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > SHIFT_PB(3) <= NOT PB; > end if; > end process; > > process (clock_100Hz, Rst) > begin > if ('1' = Rst) then > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > elsif (rising_edge(clock_100Hz)) then > if (SHIFT_PB = (others => '0')) then > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > elsif (SHIFT_PB = (others => '1')) then > PB_DEBOUNCED <= '1'; > PREVIOUS <= '1'; > else > PB_DEBOUNCED <= PREVIOUS; > end if; > end process; > end a; > > -- > > Rick Thanks Rick for the response.. However I dont think thats what is the solution my professor is looking for. Copying the whole question as I got it. "A very common approach to making sense of the strangeness of the real world is not to rely on sensors to trigger events, as we did in question one, but to use an internal clock in the the design. The DEBOUNCE.vhd module from lab7 does that: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; ENTITY debounce IS PORT(pb, clock_100Hz : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END debounce; ARCHITECTURE a OF debounce IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL PREVIOUS : STD_LOGIC; BEGIN -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. -- Debounce clock should be approximately 10ms process begin wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); SHIFT_PB(3) <= NOT PB; If SHIFT_PB(3 Downto 0)="0000" THEN PB_DEBOUNCED <= '0'; PREVIOUS <= '0'; ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN PB_DEBOUNCED <= '1'; PREVIOUS <= '1'; ELSE PB_DEBOUNCED <= PREVIOUS; End if; end process; end a; Express the architecture of this module as a Finite State Machine. There seem to be at least sixteen states, corresponding to the sixteen possible values of SHIFT_PB(3 downto 0)." From newsfish@newsfish Thu Aug 1 00:35:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Fri, 18 Dec 2015 00:57:33 -0500 Organization: A noiseless patient Spider Lines: 154 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> <87248515-1856-4c96-97e8-4d89a908fb6f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Dec 2015 05:55:03 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="22812"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Uy3iiA7xN1Sn7WCpPZh0q" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <87248515-1856-4c96-97e8-4d89a908fb6f@googlegroups.com> Cancel-Lock: sha1:gEGgGGqJ8rNueHujxvO4aOzVZd4= Xref: news.eternal-september.org comp.lang.vhdl:4172 On 12/17/2015 11:25 PM, disturbedspace1@gmail.com wrote: > On Thursday, December 17, 2015 at 9:04:39 PM UTC-5, rickman wrote: >> On 12/17/2015 3:29 PM, disturbedspace1@gmail.com wrote: >>> library IEEE; >>> use IEEE.STD_LOGIC_1164.all; >>> use IEEE.STD_LOGIC_ARITH.all; >>> use IEEE.STD_LOGIC_UNSIGNED.all; >>> ENTITY debounce IS >>> PORT(pb, clock_100Hz : IN STD_LOGIC; >>> pb_debounced : OUT STD_LOGIC); >>> END debounce; >>> ARCHITECTURE a OF debounce IS >>> SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); >>> SIGNAL PREVIOUS : STD_LOGIC; >>> BEGIN >>> -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. >>> -- Debounce clock should be approximately 10ms >>> process >>> begin >>> wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); >>> SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); >>> SHIFT_PB(3) <= NOT PB; >>> If SHIFT_PB(3 Downto 0)="0000" THEN >>> PB_DEBOUNCED <= '0'; >>> PREVIOUS <= '0'; >>> ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN >>> PB_DEBOUNCED <= '1'; >>> PREVIOUS <= '1'; >>> ELSE >>> PB_DEBOUNCED <= PREVIOUS; >>> End if; >>> end process; >>> end a; >> >> I rewrote the code to separate the state signals from the shift >> register. Otherwise I'm not sure what you want to see. Are you looking >> for some specific format for the FSM? There is no special format a >> state machine has to be coded in unless your professor insists. I >> didn't test any of this code. Oh, you should not use the >> STD_LOGIC_UNSIGNED library. It is not a standard and works differently >> with different vendors. Use the NUMERIC_STD library which *is* an IEEE >> standard. Also, use "rising_edge()" instead of (clock_100Hz'EVENT) AND >> (clock_100Hz = '1'). Lastly, using a wait statement may work for >> synthesizable logic, but is not a great idea. Use a conditional and I >> expect your circuit could use a reset. This is a *very* standard form >> and is well supported. >> >> I did find your signal "PREVIOUS" is superfluous. It is always assigned >> the same value as PB_DEBOUNCED. Either you missed something in your >> algorithm or you added this thinking it would do something useful but >> never made it do that. >> >> If you want the code to be in the form of a case statement based on the >> state, you just need to make the conditionals specific to a state, but I >> don't see any value in that. >> >> Rick >> >> >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.all; >> use IEEE.STD_LOGIC_ARITH.all; >> use IEEE.NUMERIC_STD.all; >> ENTITY debounce IS >> PORT(pb, clock_100Hz, Rst : IN STD_LOGIC; >> pb_debounced : OUT STD_LOGIC); >> END debounce; >> ARCHITECTURE a OF debounce IS >> SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); >> SIGNAL PREVIOUS : STD_LOGIC; >> BEGIN >> -- Debounce Button: Filters out mechanical switch bounce for ~40ms. >> -- Debounce clock should be approximately 10ms >> process (clock_100Hz, Rst) >> begin >> if ('1' = Rst) then >> SHIFT_PB <= (others => '0'); >> elsif (rising_edge(clock_100Hz)) then >> SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); >> SHIFT_PB(3) <= NOT PB; >> end if; >> end process; >> >> process (clock_100Hz, Rst) >> begin >> if ('1' = Rst) then >> PB_DEBOUNCED <= '0'; >> PREVIOUS <= '0'; >> elsif (rising_edge(clock_100Hz)) then >> if (SHIFT_PB = (others => '0')) then >> PB_DEBOUNCED <= '0'; >> PREVIOUS <= '0'; >> elsif (SHIFT_PB = (others => '1')) then >> PB_DEBOUNCED <= '1'; >> PREVIOUS <= '1'; >> else >> PB_DEBOUNCED <= PREVIOUS; >> end if; >> end process; >> end a; >> >> -- >> >> Rick > > > Thanks Rick for the response.. However I dont think thats what is the solution my professor is looking for. Copying the whole question as I got it. > > "A very common approach to making sense of the strangeness of the real world is not to rely on sensors to trigger events, as we did in question one, but to use an internal clock in the the design. The DEBOUNCE.vhd module from lab7 does that: > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > ENTITY debounce IS > PORT(pb, clock_100Hz : IN STD_LOGIC; > pb_debounced : OUT STD_LOGIC); > END debounce; > ARCHITECTURE a OF debounce IS > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > SIGNAL PREVIOUS : STD_LOGIC; > BEGIN > -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. > -- Debounce clock should be approximately 10ms > process > begin > wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > SHIFT_PB(3) <= NOT PB; > If SHIFT_PB(3 Downto 0)="0000" THEN > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN > PB_DEBOUNCED <= '1'; > PREVIOUS <= '1'; > ELSE > PB_DEBOUNCED <= PREVIOUS; > End if; > end process; > end a; > Express the architecture of this module as a Finite State Machine. There seem to be at least sixteen states, corresponding to the sixteen possible values of SHIFT_PB(3 downto 0)." I guess your professor wants you to do it with a case statement based on the 16 possible states of SHIFT_PB. I suggest you not bother with that since it is a pointless exercise. Rather you should point out all the bad programming mistakes he made in his code. I'm sure you will get extra credit for that. Really! Your professor sucks at VHDL coding!!! Tell him a professional said so. -- Rick From newsfish@newsfish Thu Aug 1 00:35:35 2024 X-Received: by 10.182.33.74 with SMTP id p10mr5115506obi.34.1450476330639; Fri, 18 Dec 2015 14:05:30 -0800 (PST) X-Received: by 10.50.32.10 with SMTP id e10mr113869igi.2.1450476330580; Fri, 18 Dec 2015 14:05:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no13432102igc.0!news-out.google.com!l1ni7450igd.0!nntp.google.com!mv3no17971555igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Dec 2015 14:05:30 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.34.11.119; posting-account=bEKMqAoAAABkm6h82MvoNJf2KpS09xnf NNTP-Posting-Host: 212.34.11.119 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> Subject: basic computer sequential implementation in vhdl From: kliga Injection-Date: Fri, 18 Dec 2015 22:05:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4173 I am working now on implementing a 16 bit RISC CPU in VHDL, the instruction set consists of 8 instructions 16 bits each. i need your help how to start implementation? could you give me examples for source codes like this architecture From newsfish@newsfish Thu Aug 1 00:35:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: basic computer sequential implementation in vhdl Date: Fri, 18 Dec 2015 18:02:26 -0500 Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Dec 2015 22:59:55 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="29543"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19BAPCYbQez7HSEjz/RbbHg" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> Cancel-Lock: sha1:tgqfWiP/ZWLc97XmUlwE39eRNBg= Xref: news.eternal-september.org comp.lang.vhdl:4174 On 12/18/2015 5:05 PM, kliga wrote: > I am working now on implementing a 16 bit RISC CPU in VHDL, the instruction set consists of 8 instructions 16 bits each. > i need your help how to start implementation? could you give me examples for source codes like this architecture There are tons and tons of CPU designs on the Internet. All you have to do is look around a little. If you have some specific questions please ask. But you can do your own searches, no? -- Rick From newsfish@newsfish Thu Aug 1 00:35:36 2024 X-Received: by 10.98.86.89 with SMTP id k86mr15359191pfb.10.1450689531200; Mon, 21 Dec 2015 01:18:51 -0800 (PST) X-Received: by 10.50.43.168 with SMTP id x8mr245975igl.0.1450689531166; Mon, 21 Dec 2015 01:18:51 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no18958521igc.0!news-out.google.com!l1ni9944igd.0!nntp.google.com!mv3no13995471igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Dec 2015 01:18:50 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> Subject: Re: creating program From: Lars Asplund Injection-Date: Mon, 21 Dec 2015 09:18:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4175 >=20 > Lars, >=20 > Sorry it's been a while... >=20 > First off, when I say "system level" I mean "FPGA level". With that in mi= nd... >=20 > We don't wait for the whole system to be anywhere near complete before we= test. See Jim Lewis' paper "Accelerating Verification Through = Pre-Use of System-Level Testbench Components". We use this approach to get = units integrated into a partially implemented system & test early, with no = wasted time developing unit level tests that won't need to be used again. >=20 > The dificulty in unit level testing is the quantity of unique interfaces = for all the units, and all the monitors, drivers and often-unique transacti= ons required for them. By developing the units in a sensible order to allow= a testbench with a system-level interface to exercise the functionality pr= ovided by lower level units, we can test early and often with one TB <-> DU= T interface, drivers, monitors, etc. >=20 > This approach also makes it easier to refine the system architecture for = improved performance, utilization, functionality, etc. because our verifica= tion is immune to changes in unit level interfaces that change with the arc= hitecture. >=20 > Andy Hi Andy, Thanks for the link to Jim's paper. I've seen a very similar approach at a = company I was helping getting started with VUnit but I didn't know the orig= in. I think there's much to say about this but here is a short summary - The paper describes the "traditional" approach as a methodology testing t= he same things at all levels and once you have the top-level testbench you = throw away the testbenches at the unit (subblock in the paper) level which = is a waste. This is not an inherent property of multi-level testing but rat= her a result of bad practices. When unit testing I aim for full functional = coverage at the unit level, higher levels of testing is focused on verifyin= g integration issues that can't be tested at the lower levels. Since all te= stbenches add unique value you don't throw them away. - To people sceptical about unit testing I recommend starting with a unit t= esting framework and apply that on their current testbenches. It provides m= any features valuable at all levels of testing. Once you understand how it = works and how it removes various obstacles in testing you will hopefully se= e how unit testing becomes more available and less cumbersome. Once there y= ou can take advantage of the values unit testing provides, values that are = lost if you just do higher level testing or variants thereof like the one i= n the paper. - When adopting unit testing there is a degree of personal preferences and = project specific circumstances that affect how it is applied. However, I ha= ve never met any HW or SW developer that want to go back to where they were= before if they have been properly introduced to a good unit testing framew= ork. I've also seen a number of HW and SW teams making the transition and t= hey have all noticed a productivity and quality boost =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D DETAILS: - In the end we are all looking for improved productivity and there are a n= umber of ways in which we can achieve this. First we should maximize the wo= rk not done (avoid waste) and if it's something that must be done we should= look for ways to automate the work, speed it up, or make it simpler in som= e other way. Whatever methodology we use it should scale with design size a= nd complexity and respond well to change. The need for handling change whet= her it's in requirements, design or implementation is an inevitable part of= larger and more complex designs. We are simply not capable of figuring out= everything in advance but have to adapt as we move along. - A short code/test cycle helps us find our mistakes ASAP to avoid wasting = time heading in the wrong direction. But how short is short enough? Suppose= I'm developing a simple UART, 200 lines of code or so, let's say a day of = work. For that I have a handful of of test cases, maybe a little bit more: = sending and receiving a byte, several bytes, verifying reset conditions, sp= ecial cases like overflow. On average I will have a new test case/feature t= hat can be verified every hour. It's not unlikely that I will introduce a b= ug during an hour of coding and I have to test this eventually anyway so wh= y not do it immediately? - One thing that may prevent me taking this approach is too long simulation= times. The method proposed in the paper would on average contain half the = complete system worth of logic in addition to the unit being tested. That i= s significant in a larger system where the total amount of logic is much la= rger than that of a unit. - As you mention, all the interfaces you need to address can become a burde= n when you have one testbench for each unit. However, you're allowed to tak= e well-motivated short-cuts even if you're into unit testing, and people of= ten do. Given that the CPU interface in Jim's example doesn't affect your a= bility to observe and control the units behind it and it doesn't add signif= icant delays, it may save you time to test the CPU interface (CIF) + the ti= mer as a "unit", CIF+UART as a unit, and CIF+memory interface as a unit. To= verify integration of the full system I need a testbench with a few read/w= rites to make sure that decoding works and I don't have conflicts on the in= ternal bus. Same number of testbenches and unique interfaces to handle as i= n the paper but no superfluous logic and no abandon testbenches. - The reason that unit grouping like the one I explained can be motivated i= s that the "main" units in the paper sits right behind a "transparent" CPU = interface and they are largely independent. A larger and more complex desig= n would have more units, they would be more "embedded" and there would be m= ore dependencies. Figuring out how to control and observe the unit under te= st becomes harder from the system boundary. There may also be significant d= elays in the paths before the targeted unit becomes activated (=3D simulati= on time). If testing is hard and slow you won't do it as often (=3D longer = code/test cycles). Also, the amount of logic per I/O of a modern FPGA is ma= ny times higher than it was in 2003 when this paper was written. The observ= ability and controllability from the system interfaces are constantly getti= ng worse. - In general it's not possible to add units to a system in such an order th= at you can test them individually from the system boundary. This is the cas= e with the CPU interface logic in the examples which is partially tested wi= th manual inspection. An alternative would of course be to make that self-c= hecking and fully tested, that is develop a proper unit test. Another appro= ach would be to postpone testing (=3D longer code/test cycle) and wait unti= l you have more units in place. This is what I do when grouping the CPU int= erface with the timer. This problem will get worst with larger and more com= plex designs - Some other obstacles for the short code/test cycle that VUnit will remove - If you want frequent testing your testbenches must be self-checking. V= Unit provides a check package that improves over plain VHDL asserts (but yo= u can use assert as well) and a test runner to organize the test cases in y= our testbench - With many testbenches and test cases it has to be convenient to run the= m frequently or you won't. VUnit will automatically compile all your files = in dependency order, find and execute all your test cases (or a subset you = specify), and present the result. - VUnit can with a command line option split your test case simulations b= etween many threads/CPU cores which can run in the background while you con= tinue to work interactively with another instance of your simulator and the= next piece of code. If you can hide the simulation time altogether there's= no excuse for not running the tests. - If you run many simulations in parallel licensing may become an issue. = VUnit supports the free and open source GHDL simulator to remove that obsta= cle. Use whatever simulator you prefer for interactive work and let GHDL ha= ndle batch simulations. - Developing transactions may be cumbersome as you noted. VUnit has a pac= kage providing message passing combined with code generation for your trans= actions. - In a previous post I described how unit testing drives an architecture wi= th highly cohesive and loosely coupled units, that is a modular design. Suc= h a design is easier to maintain since changes tend to be more localized. M= ore localized changes means less interfaces changes and less rework of test= benches when making the type of optimizations you mention. One thing we cha= nged from the first generation of VUnit to where we are today is that our t= est cases are no longer procedures defined in a separate package since inte= rface changes means that you have to update the procedure declaration as we= ll. Instead our test cases are defined in the same scope as the unit instan= ce so that they have access to the interfaces directly. I guess you have si= milar problems when the test cases are defined in architectures of a separa= te test control entity. Again, remove obstacles whenever you can. From newsfish@newsfish Thu Aug 1 00:35:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Nicholas Collin Paul de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: keywords versus language complexity Date: Tue, 22 Dec 2015 14:37:06 +0100 Organization: A noiseless patient Spider Lines: 31 Message-ID: References: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Injection-Info: mx02.eternal-september.org; posting-host="1b4315c307f3cc5ba77928d0bb2ed33c"; logging-data="26002"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Kmn75rrdHGWslST4WsHCYZ9ewhbvJcYTmLi8sXvFUTg==" User-Agent: Alpine 2.11 (DEB 23 2013-08-11) In-Reply-To: Cancel-Lock: sha1:I3XYLDCj0MDVlPDSEcH8jhtC6uA= X-X-Sender: gloucester@Lydia.insomnia247.nl Xref: news.eternal-september.org comp.lang.vhdl:4176 HT-Lab submitted: |-----------------------------------------------------------------------------| |"[. . .] | |[. . .] if I | |take [out . . .] the BNF pages then we end up | |with about 290 pages of pure VHDL goodness. [. . .] | |[. . .] | | | |I actually mentioned the article as most of us don't realise the pain parser | |and tool developers have to go through to support all the esoteric feature | |mentioned in an LRM. [. . .] | |[. . .]" | |-----------------------------------------------------------------------------| Hi Hans, Without a BNF there is no parser. |-----------------------------------------------------------------------------| |"We are lucky to have Jim Lewis driving the next VHDL standard [. . .] | |[. . .] | | | |Regards, | |Hans. | | www.ht-lab.com " | |-----------------------------------------------------------------------------| True. Regards, Nicholas Collin Paul de Gloucester From newsfish@newsfish Thu Aug 1 00:35:37 2024 X-Received: by 10.129.130.135 with SMTP id s129mr22043271ywf.20.1450807876951; Tue, 22 Dec 2015 10:11:16 -0800 (PST) X-Received: by 10.50.57.84 with SMTP id g20mr414328igq.3.1450807876920; Tue, 22 Dec 2015 10:11:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!94no473194qgt.1!news-out.google.com!f6ni30620igq.0!nntp.google.com!mv3no14472552igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Dec 2015 10:11:16 -0800 (PST) In-Reply-To: <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <88321b8a-514d-4c41-b1c7-b9ef6b411e37@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Tue, 22 Dec 2015 18:11:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 41 Xref: news.eternal-september.org comp.lang.vhdl:4177 Lars, A fundamental aspect of SW test that is not possible in unit level "test" i= s that, by definition, sofware "test" must use the production compiler to p= roduce production object code, which is then run and tested on production-r= epresentative hardware. In reality, simulation is analysis, not test. In HDL, the production compiler is a synthesis, place & route tool (not a s= imulator!), and the production representative hardware/system is the target= FPGA. None of these are possible at the unit level. SPR does not SPR each = module, and "call" it multiple times. Each instance is separately SPR'd as = part of the system. Each instance is uniquely optimized per its environment= within the system). In order to perform testing for Programmable Logic, all stimulus/response m= ust be provided/captured at observable interfaces for the FPGA. RTL simulat= ion at the FPGA level can be used to verify and caputure the stimulus and r= esponse at the FPGA level, which can then be applied to a real FPGA, using = the real bit file (the "production" object code.) Even after that, we still have to run integration testing using real system= hardware to provide the stimulus/response to the FPGA, to verify that simu= lation models of those external components, were accurate models. Therefore, even if we wanted to avail ourselves of the virtues of unit leve= l testing, all coverage must still be achieved at the FPGA level, since tha= t is the only level at which the PL can be truly tested. Necessary exceptions to this include white-box testing at the RTL or gate l= evel. All that said, I agree with your statement about the virtues of loosely cou= pled modules, which are encouraged by unit level development and testing. T= here are other ways to encourage these virtues, including coding/design sta= ndards and reviews.=20 Just keep in mind that what is loosely coupled in the design is not always = loosely coupled in the FPGA after optimization, placement and routing, part= icularly if physical synthesis in employed. Andy From newsfish@newsfish Thu Aug 1 00:35:37 2024 X-Received: by 10.31.7.132 with SMTP id 126mr32643659vkh.3.1450989634708; Thu, 24 Dec 2015 12:40:34 -0800 (PST) X-Received: by 10.50.30.201 with SMTP id u9mr646989igh.4.1450989634675; Thu, 24 Dec 2015 12:40:34 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!6no661752qgy.0!news-out.google.com!f6ni32698igq.0!nntp.google.com!mv3no15091120igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Dec 2015 12:40:33 -0800 (PST) In-Reply-To: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.53.155.162; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.53.155.162 References: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: basic computer sequential implementation in vhdl From: stchebel@gmail.com Injection-Date: Thu, 24 Dec 2015 20:40:34 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4178 W dniu pi=C4=85tek, 18 grudnia 2015 23:05:34 UTC+1 u=C5=BCytkownik kliga na= pisa=C5=82: > I am working now on implementing a 16 bit RISC CPU in VHDL, the instructi= on set consists of 8 instructions 16 bits each. > i need your help how to start implementation? could you give me examples = for source codes like this architecture case Instruction_Code is when "000" =3D> ......; -- here add your desired code=20 when "001" =3D> ......; . . when "111" =3D> ......; when others =3D> null; end case; From newsfish@newsfish Thu Aug 1 00:35:37 2024 X-Received: by 10.129.110.7 with SMTP id j7mr29797591ywc.26.1450990188159; Thu, 24 Dec 2015 12:49:48 -0800 (PST) X-Received: by 10.50.114.105 with SMTP id jf9mr647477igb.1.1450990188091; Thu, 24 Dec 2015 12:49:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!6no662563qgy.0!news-out.google.com!f6ni32695igq.0!nntp.google.com!mv3no20737348igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Dec 2015 12:49:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.53.155.162; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.53.155.162 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Subject: Wide bus From: stchebel@gmail.com Injection-Date: Thu, 24 Dec 2015 20:49:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4179 Suppose I have an n-input simple OR gate. Result <= inp(0) or inp(1) or ...... or inp(n); Q: how to write the above code for generic n? From newsfish@newsfish Thu Aug 1 00:35:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wide bus Date: Thu, 24 Dec 2015 16:48:32 -0500 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Dec 2015 21:45:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="208907d19447316176ab8c9b8a72ea24"; logging-data="8242"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18dwRFVNFXiP+8eG+DrQu/X" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Cancel-Lock: sha1:bxXkuf7oMxFZZj7q8oqGIfmVohE= Xref: news.eternal-september.org comp.lang.vhdl:4180 On 12/24/2015 3:49 PM, stchebel@gmail.com wrote: > Suppose I have an n-input simple OR gate. > > Result <= inp(0) or inp(1) or ...... or inp(n); > > Q: how to write the above code for generic n? I believe there is an existing operator in VHDL 2008 to take the or of each bit in a vector. If you can't find that use a for loop. -- Rick From newsfish@newsfish Thu Aug 1 00:35:38 2024 X-Received: by 10.182.128.39 with SMTP id nl7mr35346251obb.13.1451002666295; Thu, 24 Dec 2015 16:17:46 -0800 (PST) X-Received: by 10.50.30.201 with SMTP id u9mr656572igh.4.1451002666233; Thu, 24 Dec 2015 16:17:46 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!2.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!mv3no20798624igc.0!news-out.google.com!l1ni1431igd.0!nntp.google.com!mv3no15126095igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Dec 2015 16:17:45 -0800 (PST) In-Reply-To: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wide bus From: KJ Injection-Date: Fri, 25 Dec 2015 00:17:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4181 On Thursday, December 24, 2015 at 3:49:53 PM UTC-5, stch...@gmail.com wrote: > Suppose I have an n-input simple OR gate. > > Result <= inp(0) or inp(1) or ...... or inp(n); > > Q: how to write the above code for generic n? The function you want is called 'or_reduce' commonly found in the 'reduce_pkg' package. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Literals UO"2C" = B"011_CCC"? Date: Fri, 25 Dec 2015 13:45:38 +0200 Organization: A noiseless patient Spider Lines: 3 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Dec 2015 11:43:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="10465"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/bHx+um7EQO+6nOSYiQ6saD5RKnYLlf7M=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:dlGJOfsA8HtrOsA13o6H33nmU1M= Xref: news.eternal-september.org comp.lang.vhdl:4182 LRM says that literally UO"2C" -- Equivalent to B"011_CCC" -- that is a copy and paste Octavian 2 has binary equivalent of 010 rather than 011, isn't it? From newsfish@newsfish Thu Aug 1 00:35:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Fri, 25 Dec 2015 18:43:33 +0200 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Dec 2015 16:41:03 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="2431"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+M5fXP9o9eb03XKqg19e/Zx9lhd4n1AY=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:kv6ksE4N5waDxggackYc+Aiq4C0= Xref: news.eternal-september.org comp.lang.vhdl:4183 I discovered it doing some parsing. I have also noticed that I cannot parse the bit string literals because bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] " Please note that bit_value is enclosed into the quotes. bit_value ::= graphic_character { [ underline ] graphic_character } graphic_character ::= basic_graphic_character | lower_case_letter | other_special_character basic_graphic_character ::= upper_case_letter | digit | special_character | space_character where special characters are " # & ' () * + , - . / : ; < = > ? @ [ ] _ ` -- Please note that the first special character is exactly the quotation mark. Such definition makes the bit_string_literal closing literal a part of the literal itself and parser runs into the end of stream. How do you handle such cases? From newsfish@newsfish Thu Aug 1 00:35:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!nntp.club.cc.cmu.edu!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Wide bus Newsgroups: comp.lang.vhdl References: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 26 Dec 2015 09:22:42 GMT Lines: 20 Message-ID: <567e5c62$0$1525$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 6b340b3b.news.astraweb.com X-Trace: DXC=:@hY[S7h;8WD:=ciL5QPHRL?0kYOcDh@ZKF7Mk<5A6iU0WDN7dFMi;XHI6bY5_;LhYEBe]G`V^KXWJ4[iH6U\5J]2FUFZ3noJIP Xref: news.eternal-september.org comp.lang.vhdl:4184 On Thu, 24 Dec 2015 16:17:45 -0800, KJ wrote: > On Thursday, December 24, 2015 at 3:49:53 PM UTC-5, stch...@gmail.com > wrote: >> Suppose I have an n-input simple OR gate. >> >> Result <= inp(0) or inp(1) or ...... or inp(n); >> >> Q: how to write the above code for generic n? > > The function you want is called 'or_reduce' commonly found in the > 'reduce_pkg' package. > > Kevin Jennings or the ieee.std_logic_misc package. It's supported in all the tools I've tried (even ones from Xilinx). Regards, Allan From newsfish@newsfish Thu Aug 1 00:35:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sat, 26 Dec 2015 12:38:50 -0500 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Dec 2015 17:36:17 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f3df5b8edec0e1f9d6c5ec6e1844be5b"; logging-data="1075"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18mAwFauOEWAnZVfZw65DKV" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:knxdR/BwHRxuUvb/sENRfUOQJPU= Xref: news.eternal-september.org comp.lang.vhdl:4185 On 12/25/2015 11:43 AM, valtih1978 wrote: > I discovered it doing some parsing. I have also noticed that I cannot > parse the bit string literals because > > bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] " > > Please note that bit_value is enclosed into the quotes. > > bit_value ::= graphic_character { [ underline ] graphic_character } > graphic_character ::= basic_graphic_character | lower_case_letter | > other_special_character > basic_graphic_character ::= > upper_case_letter | digit | special_character | space_character > > where special characters are " # & ' () * + , - . / : ; < = > ? @ [ ] _ > ` -- Please note that the first special character is exactly the > quotation mark. Such definition makes the bit_string_literal closing > literal a part of the literal itself and parser runs into the end of > stream. How do you handle such cases? So you are trying to write a parser for VHDL? Obviously you scan the input text until you encounter another quote character. I know some languages allow quotes to be embedded in strings by using two quotes in a row, so the scanning is not so simple. You have to scan for a quote followed by a character that is not a quote. But I don't think VHDL does this. -- Rick From newsfish@newsfish Thu Aug 1 00:35:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sat, 26 Dec 2015 20:28:42 +0200 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Dec 2015 18:26:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="13696"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19PellN4YYk0kqXz150szcQGfgTqrmYKhM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:hIo7S5tTbFU2dDf82qbcDHuccmA= Xref: news.eternal-september.org comp.lang.vhdl:4186 > So you are trying to write a parser for VHDL? Obviously you scan the > input text until you encounter another quote character. Obviously, I am doing quite the opposite thing. I follow the grammar rules instead of scanning for the second mark. I have failed exactly because not following this simplistic approach. Probably I am the only one on the planet who does not do that. >I know some > languages allow quotes to be embedded in strings by using two quotes in > a row, so the scanning is not so simple. You have to scan for a quote > followed by a character that is not a quote. But I don't think VHDL > does this. The duplication of quotation mark is stipulated in the `string_literal` chapter in LRM. It is also interesting how good this stipulation matches with the grammar rules, presented in parallel. Yet, I do not see such a remark in the `bit_string_literal` rule, discussed separately in the LRM. I looked into example parser, https://sourceforge.net/p/zamiacad/code/ci/master/tree/src/org/zamia/vhdl/vhdl2008/VHDL2008.jj. They simply throw the quotation mark out of the special character list and then add it separately as an alternative to graphic_character in the string_literal definition. But they do not supply " char in the bit string definition, which means that they do not support " in the bitstring literals. I am looking to know how it is supposed to be done and what does VHDL community does. From newsfish@newsfish Thu Aug 1 00:35:40 2024 X-Received: by 10.140.157.74 with SMTP id d71mr40622154qhd.13.1451163272976; Sat, 26 Dec 2015 12:54:32 -0800 (PST) X-Received: by 10.50.134.69 with SMTP id pi5mr738376igb.5.1451163272945; Sat, 26 Dec 2015 12:54:32 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!6no986330qgy.0!news-out.google.com!l1ni3302igd.0!nntp.google.com!mv3no15510446igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 26 Dec 2015 12:54:31 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Sat, 26 Dec 2015 20:54:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 26 Xref: news.eternal-september.org comp.lang.vhdl:4187 On Friday, December 25, 2015 at 11:43:41 AM UTC-5, valtih1978 wrote: > I discovered it doing some parsing. I have also noticed that I cannot > parse the bit string literals because > > bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] " > > Please note that bit_value is enclosed into the quotes. > > bit_value ::= graphic_character { [ underline ] graphic_character } > graphic_character ::= basic_graphic_character | lower_case_letter | > other_special_character > basic_graphic_character ::= > upper_case_letter | digit | special_character | space_character > > where special characters are " # & ' () * + , - . / : ; < = > ? @ [ ] _ > ` -- Please note that the first special character is exactly the > quotation mark. Such definition makes the bit_string_literal closing > literal a part of the literal itself and parser runs into the end of > stream. How do you handle such cases? The double quote that is to be included in the literal would have to be preceded by a backslash. Also note the definition of a string literal is: string_literal ::= " { graphic_character } " You would have the same issue here trying to insert a " into a string. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sat, 26 Dec 2015 17:26:23 -0500 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Dec 2015 22:23:49 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f3df5b8edec0e1f9d6c5ec6e1844be5b"; logging-data="5126"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/I1IXZ7CB6zCsCQj8woaR5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:+idOpboTEG9/bZ99v9Io8loDMM4= Xref: news.eternal-september.org comp.lang.vhdl:4188 On 12/26/2015 1:28 PM, valtih1978 wrote: >> So you are trying to write a parser for VHDL? Obviously you scan the >> input text until you encounter another quote character. > > Obviously, I am doing quite the opposite thing. I follow the grammar > rules instead of scanning for the second mark. I have failed exactly > because not following this simplistic approach. Probably I am the only > one on the planet who does not do that. > >> I know some >> languages allow quotes to be embedded in strings by using two quotes in >> a row, so the scanning is not so simple. You have to scan for a quote >> followed by a character that is not a quote. But I don't think VHDL >> does this. > > The duplication of quotation mark is stipulated in the `string_literal` > chapter in LRM. It is also interesting how good this stipulation matches > with the grammar rules, presented in parallel. Yet, I do not see such a > remark in the `bit_string_literal` rule, discussed separately in the LRM. > > I looked into example parser, > https://sourceforge.net/p/zamiacad/code/ci/master/tree/src/org/zamia/vhdl/vhdl2008/VHDL2008.jj. > They simply throw the quotation mark out of the special character list > and then add it separately as an alternative to graphic_character in the > string_literal definition. But they do not supply " char in the bit > string definition, which means that they do not support " in the > bitstring literals. > > I am looking to know how it is supposed to be done and what does VHDL > community does. I'm unclear. If you are following "all" the grammar rules, what exactly is your concern? -- Rick From newsfish@newsfish Thu Aug 1 00:35:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 02:59:18 +0200 Organization: A noiseless patient Spider Lines: 18 Message-ID: <567F37E6.5090602@not.email.me> References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="3696"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18DNobNsi7cC9G0GJfPlgr0kXs7lT1BIG4=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> Cancel-Lock: sha1:aWwP2yMzPRQz4m3Q+EUYM4RGtoQ= Xref: news.eternal-september.org comp.lang.vhdl:4189 > You would have the same issue here trying to insert a " into a string. Where did you read about that? > Also note the definition of a string literal is: > > string_literal ::= " { graphic_character } " > > You would have the same issue here trying to insert a " into a string. Yes, I reported that already to the rickman. I reported that I have discovered that LRM mandates user to duplicate the double quote marks in the VHDL source string literals to produce a single quotation in the running program. The Bible says so textually but LRM grammar productions seem to contradict the text. LRM does not even stipulate this issue in the bit_string_literal declaration at all. So I wonder, how did you know that \" must be used there instead of quotation duplication? Did you confuse user input with mine parser code, written in derivative of C? From newsfish@newsfish Thu Aug 1 00:35:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Physical unit ambiguities Date: Sun, 27 Dec 2015 03:07:53 +0200 Organization: A noiseless patient Spider Lines: 22 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 01:05:18 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="5151"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19leCtCat2SlelpMsW6fFPOL3bRPIcaJiI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:vc6HBarZBgQsV5nQRcRuRibPL50= Xref: news.eternal-september.org comp.lang.vhdl:4190 Another ambiguity comes from literal ::= numeric_literal | enumeration_literal | ... numeric_literal ::= physical_literal | ... physical_literal ::= [ abstract_literal ] name name ::= identifier | operator_symbol | character_literal | selected_name | indexed_name | slice_name | attribute_name enumeration_literal ::= identifier | ... For instance, you have a 'second' in the expression. Is it an enumeration or physical literal? The numerical quantity is optional in phys. literals, as we see. It seems that this is an incarnation of what I heard of "context-sensitivity" of VHDL? Does it mean that the parse tree is ambiguous until after the elaboration? Moreover, 'name' admits such fancy names as function invocation, attribute requests and such, which seems to be a nonsense for physical literal, e.g. 1 miles(3) should be valid according to the LRM grammar. Language designers could easily ban this "feature" by saying that physical units are specified by identifiers (aka simple names) rather than arbitrary names. Why does spec choose the general name production instead? From newsfish@newsfish Thu Aug 1 00:35:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sat, 26 Dec 2015 20:33:53 -0500 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 01:31:19 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3e23f04fa29aea4a01d064c7ba7655fc"; logging-data="8338"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Yp2Dh79NQZENP4l602iMZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <567F37E6.5090602@not.email.me> Cancel-Lock: sha1:T/dgLSgf/5beXCURy6LLxvlYi+A= Xref: news.eternal-september.org comp.lang.vhdl:4191 On 12/26/2015 7:59 PM, valtih1978 wrote: >> You would have the same issue here trying to insert a " into a string. > > Where did you read about that? > > > Also note the definition of a string literal is: > > > > string_literal ::= " { graphic_character } " > > > > You would have the same issue here trying to insert a " into a string. > > Yes, I reported that already to the rickman. I reported that I have > discovered that LRM mandates user to duplicate the double quote marks in > the VHDL source string literals to produce a single quotation in the > running program. The Bible says so textually but LRM grammar productions > seem to contradict the text. LRM does not even stipulate this issue in > the bit_string_literal declaration at all. So I wonder, how did you know > that \" must be used there instead of quotation duplication? Did you > confuse user input with mine parser code, written in derivative of C? Except you showed BNF for "bit_string_literal" while the double quote only had meaning in the more literal "string_literal". Is the "string_literal" defined the same way? If your problem is in the "bit_string_literal" why are you trying to embed quotes in it? -- Rick From newsfish@newsfish Thu Aug 1 00:35:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 09:48:30 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: <567F97CE.2060508@not.email.me> References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="25723"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19pdL+KE35iWfDR24XSsGsZKOmtfMTtz2Y=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:Z+gkF+MYQw3N+9O4qKrev6EYCSA= Xref: news.eternal-september.org comp.lang.vhdl:4192 > Except you showed BNF for "bit_string_literal" while the double quote > only had meaning in the more literal "string_literal". Who says that any why does LRM say otherwise? I have demonstrated the grammar that says that all special characters, including the quotes, are allowed in the bit string literal, in the same way as they are included in the string literal. > Is the > "string_literal" defined the same way? You are responding under KJ's remark saying that the string literal string_literal ::= " { graphic_character } " is defined the same way. So, I do not understand this the question. > If your problem is in the > "bit_string_literal" why are you trying to embed quotes in it? Because I tried to implement the spec rather than my fantasies or to embed the quotes into the string. I think that if spec admits embedded quotes, they must be supported. From newsfish@newsfish Thu Aug 1 00:35:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 11:09:32 -0500 Organization: A noiseless patient Spider Lines: 36 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 16:06:58 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="68639cc5c98aed50d7aac76c23cb1a02"; logging-data="23300"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX186sLPGKeZDtL6CPxN7kkOu" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: <567F97CE.2060508@not.email.me> Cancel-Lock: sha1:S0zFNJfkuzGIuZ/AYq/97yms+HE= Xref: news.eternal-september.org comp.lang.vhdl:4193 On 12/27/2015 2:48 AM, valtih1978 wrote: > >> Except you showed BNF for "bit_string_literal" while the double quote >> only had meaning in the more literal "string_literal". > > Who says that any why does LRM say otherwise? I have demonstrated the > grammar that says that all special characters, including the quotes, are > allowed in the bit string literal, in the same way as they are included > in the string literal. > >> Is the >> "string_literal" defined the same way? > > You are responding under KJ's remark saying that the string literal > > string_literal ::= " { graphic_character } " > > is defined the same way. So, I do not understand this the question. > >> If your problem is in the >> "bit_string_literal" why are you trying to embed quotes in it? > > Because I tried to implement the spec rather than my fantasies or to > embed the quotes into the string. I think that if spec admits embedded > quotes, they must be supported. You mean you tried to implement the BNF which seems to not describe the language 100%. To think that a bit literal can contain every letter of the alphabet is a bit silly. They can't because a bit string literal only has meaning when it contains the few characters that are allowed. The VHDL spec is more than just the BNF lists. -- Rick From newsfish@newsfish Thu Aug 1 00:35:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 21:01:09 +0200 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 18:58:33 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="29157"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19qTFLYc35UJiczYW7ESS8hAGi3c2yeS6Y=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:z4p0Kj1HmWLHGwo2teDnqPNO7RM= Xref: news.eternal-september.org comp.lang.vhdl:4194 > You mean you tried to implement the BNF which seems to not describe the > language 100%.The VHDL spec is more than just the BNF lists. Yes, I tried. Yes, BNF is incomplete and water is liquid. But the problem that I address here is that BNF seems to contain a fatal error. Saying that I see it because it does not specify the language 100% is a little bit inappropriate, isn't it? It is like if instruction to go shopping would instruct you to kill youself at one point. You may defend the instruction saying that "it is incomplete" but this would make the situation even more ridiculous. And it does. > To think that a bit literal can contain every letter of > the alphabet is a bit silly. What if BNF admits every character? Have you ever looked at the appropriate lines I have copy pasted before starting to teach me? I do not need to learn the kid stuff. I have a concrete question and need to know where is the error concretely. > They can't because a bit string literal > only has meaning when it contains the few characters that are allowed. Any user-defined literal or identifier falls into this category. Everything that user defines must consist solely of few allowed characters. But, it is again as informative as "the water is wet" above. Simply saying "only permitted characters make sense" does not point us to which of the characters are permitted exactly, isn't it? Can you stop speaking misteriously with insinuations, and start telling exactly which characters are defined legit in LRM. I do not tolerate when people ignore my questions or draw them into 0-information, I hate intellectual pretense and not going to learn trivial, obvious things. From newsfish@newsfish Thu Aug 1 00:35:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 14:16:57 -0500 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 19:14:22 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="1794"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/E0mseH1KMwLFVSoCJJCnp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:BM4zct5OC9iGUCXtm/KfMOA+VNA= Xref: news.eternal-september.org comp.lang.vhdl:4195 On 12/27/2015 2:01 PM, valtih1978 wrote: > >> You mean you tried to implement the BNF which seems to not describe the >> language 100%.The VHDL spec is more than just the BNF lists. > > Yes, I tried. Yes, BNF is incomplete and water is liquid. But the > problem that I address here is that BNF seems to contain a fatal error. > Saying that I see it because it does not specify the language 100% is a > little bit inappropriate, isn't it? It is like if instruction to go > shopping would instruct you to kill youself at one point. You may defend > the instruction saying that "it is incomplete" but this would make the > situation even more ridiculous. And it does. > >> To think that a bit literal can contain every letter of >> the alphabet is a bit silly. > > What if BNF admits every character? Have you ever looked at the > appropriate lines I have copy pasted before starting to teach me? I do > not need to learn the kid stuff. I have a concrete question and need to > know where is the error concretely. > >> They can't because a bit string literal >> only has meaning when it contains the few characters that are allowed. > > Any user-defined literal or identifier falls into this category. > Everything that user defines must consist solely of few allowed > characters. But, it is again as informative as "the water is wet" above. > Simply saying "only permitted characters make sense" does not point us > to which of the characters are permitted exactly, isn't it? > > Can you stop speaking misteriously with insinuations, and start telling > exactly which characters are defined legit in LRM. I do not tolerate > when people ignore my questions or draw them into 0-information, I hate > intellectual pretense and not going to learn trivial, obvious things. I have no idea what you are complaining about. You have the VHDL spec, it clearly says you can embed the quote character in a string by using two in succession. What are you going on about? Either implement the language or give up. I don't know any other alternatives. I've already suggested that you need to ignore the BNF where it is wrong. Or is there a useful question in there somewhere that I missed? If you want, send me a copy of the version of the spec you are implementing and I'll take a look to show you where the various strings are fully explained. I believe I have PDFs of each version other than 2008. -- Rick From newsfish@newsfish Thu Aug 1 00:35:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 14:26:41 -0500 Organization: A noiseless patient Spider Lines: 64 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 19:24:06 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="68639cc5c98aed50d7aac76c23cb1a02"; logging-data="5066"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/+tYBjncw4CRwtkLyV2BDm" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:9C6bovq/3NCLImuNedXxVkqqCe4= Xref: news.eternal-september.org comp.lang.vhdl:4196 On 12/27/2015 2:01 PM, valtih1978 wrote: > >> You mean you tried to implement the BNF which seems to not describe the >> language 100%.The VHDL spec is more than just the BNF lists. > > Yes, I tried. Yes, BNF is incomplete and water is liquid. But the > problem that I address here is that BNF seems to contain a fatal error. > Saying that I see it because it does not specify the language 100% is a > little bit inappropriate, isn't it? It is like if instruction to go > shopping would instruct you to kill youself at one point. You may defend > the instruction saying that "it is incomplete" but this would make the > situation even more ridiculous. And it does. > >> To think that a bit literal can contain every letter of >> the alphabet is a bit silly. > > What if BNF admits every character? Have you ever looked at the > appropriate lines I have copy pasted before starting to teach me? I do > not need to learn the kid stuff. I have a concrete question and need to > know where is the error concretely. > >> They can't because a bit string literal >> only has meaning when it contains the few characters that are allowed. > > Any user-defined literal or identifier falls into this category. > Everything that user defines must consist solely of few allowed > characters. But, it is again as informative as "the water is wet" above. > Simply saying "only permitted characters make sense" does not point us > to which of the characters are permitted exactly, isn't it? > > Can you stop speaking misteriously with insinuations, and start telling > exactly which characters are defined legit in LRM. I do not tolerate > when people ignore my questions or draw them into 0-information, I hate > intellectual pretense and not going to learn trivial, obvious things. Here are the appropriate sections from the 1993 standard... String Literals String literals are composed as a sequence of graphic characters (letters, digits, special characters) enclosed between two quotation marks (double quotes). They are usually used for warnings or reports which are displayed during simulation (Example 3). Bit string literals Bit string literals represent values of string literals that denote sequences of extended digits, range of which depends on the specified base. The base specifier determines the base of the digits: letter B used as a base specifier denotes binary digits (0 or 1), letter O - octal digits (0 to 7) and letter X - hexadecimal (digits 0 to 9 and letters A to F, case insensitive). Underlines can be used to increase readability and have no impact on the value. All values specified as bit string literals are converted into binary representation without underlines. Binary strings remain unchanged (only underlines are removed), each octal digit is converted into three bits and each hexadecimal into four bits (Example 4). What is not clear about that? -- Rick From newsfish@newsfish Thu Aug 1 00:35:44 2024 X-Received: by 10.50.70.42 with SMTP id j10mr44361425igu.9.1451266391698; Sun, 27 Dec 2015 17:33:11 -0800 (PST) X-Received: by 10.50.97.37 with SMTP id dx5mr491938igb.8.1451266391680; Sun, 27 Dec 2015 17:33:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!mv3no21973484igc.0!news-out.google.com!f6ni35649igq.0!nntp.google.com!mv3no15757239igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Dec 2015 17:33:10 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Mon, 28 Dec 2015 01:33:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4197 On Sunday, December 27, 2015 at 2:01:13 PM UTC-5, valtih1978 wrote: > > You mean you tried to implement the BNF which seems to not describe the > > language 100%.The VHDL spec is more than just the BNF lists. >=20 > Yes, I tried. Yes, BNF is incomplete and water is liquid. But the=20 > problem that I address here is that BNF seems to contain a fatal error.= =20 There is more to the language specification than the BNF. In this particul= ar case, the following text is relevant (all from VHDL-2008) Section 15.8 (Bit String Literals): "A bit string literal has a value that= is a string literal" Section 15.7 (String literals): "If a quotation mark value is to be represe= nted in the sequence of character values, then a pair of adjacent quotation= marks shall be written at the corresponding place within the string litera= l. (This means that a string literal that includes two adjacent quotation m= arks is never interpreted as two adjacent string literals.)" There is an example which shows that """" (four consecutive quotation marks= ) is a string literal of length 1. In order for two consecutive quotation = marks to be allowed as a 'special_character', it would have to define the q= uotation mark character to be one of the special characters since you can't= have two of something until you at least have one. They could possibly ha= ve added a footnote to indicate that really the special character is "", bu= t they didn't. But they did explain how you get a " by using "". If you w= ant to fixate that the BNF has a 'fatal error', knock yourself out, but to = do that you have to ignore what was specifically explained in section 15.7 = regarding the quotation mark. If you'd like another example of a discrepancy between BNF and the text, he= re you go... Section 5.2.3.1 (General Integer types) "An implementation may restrict the bounds of the range constraint of integ= er types other than type universal_integer. However, an implementation shall allow the declaration o= f any integer type whose range is wholly contained within the bounds -21474= 83647 and +2147483647 inclusive." Section 9.3.2 Literals "numeric_literal ::=3D abstract_literal | physical_literal Numeric literals include literals of the abstract types universal_integer a= nd universal_real, as well as literals of physical types. Abstract literals= are defined in 15.5; physical literals are defined in 5.2.4.1." So, clearly -1 should be considered a numeric literal. But now look at the= BNF. abstract_literals are numeric_literals. Section 15.5.1: abstract_literal ::=3D decimal_literal Section 15.5.2: decimal_literal ::=3D integer [ . integer ] [ exponent ] integer ::=3D digit { [ underline ] digit } exponent ::=3D E [ + ] integer | E - integer Now, where is the minus sign in the BNF? It's not there. So while the sec= tion that defines integer literals specifically says that -2147483647 is a = literal, the BNF does not support this since there is no way to put in the = minus sign per the BNF. So these two sections of the specification conflic= t. To me, a reasonable interpretation to make is that since there is a con= flict with the specification itself, that there should be no flagging of an= error by a tool if source code adheres to the narrative but not the BNF. = The BNF is no more 'correct' than narrative (unless there is such a disclai= mer somewhere in the specification that says so). So the text -1 should be= interpreted as an integer literal. Not all folks agree and they think tha= t the BNF must trump narrative and think that they are making their tool ad= here 'closer' to the standard by using this interpretation when it is conve= nient...but they are ignoring something specifically called out in the stan= dard. Oh well. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:44 2024 X-Received: by 10.182.236.4 with SMTP id uq4mr47117875obc.3.1451269363668; Sun, 27 Dec 2015 18:22:43 -0800 (PST) X-Received: by 10.50.132.67 with SMTP id os3mr567975igb.7.1451269363648; Sun, 27 Dec 2015 18:22:43 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!mv3no21985990igc.0!news-out.google.com!l1ni4535igd.0!nntp.google.com!mv3no21985984igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Dec 2015 18:22:42 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:352c:4b9:87c4:c93a; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:352c:4b9:87c4:c93a References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <62ee3b9c-9ebd-4f7f-a33b-e73fb0f6ee8d@googlegroups.com> Subject: Re: Physical unit ambiguities From: KJ Injection-Date: Mon, 28 Dec 2015 02:22:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4198 On Saturday, December 26, 2015 at 8:07:55 PM UTC-5, valtih1978 wrote: > Another ambiguity comes from > > literal ::= numeric_literal | enumeration_literal | ... > numeric_literal ::= physical_literal | ... > physical_literal ::= [ abstract_literal ] name > name ::= identifier | operator_symbol | character_literal | > selected_name | indexed_name | slice_name | attribute_name > enumeration_literal ::= identifier | ... > According to VHDL-2000, 2002 and 2008 physical_literal ::= [ abstract_literal ] unit_name physical_literal is not defined as you have posted as physical_literal ::= [ abstract_literal ] name 'unit_name' is not further defined in the specifications, however 'unit name' is defined. Darn those inconsistent humans anyway. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:44 2024 X-Received: by 10.129.154.197 with SMTP id r188mr17734102ywg.40.1451282639027; Sun, 27 Dec 2015 22:03:59 -0800 (PST) X-Received: by 10.50.97.37 with SMTP id dx5mr502051igb.8.1451282638998; Sun, 27 Dec 2015 22:03:58 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!6no1198859qgy.0!news-out.google.com!l1ni4726igd.0!nntp.google.com!mv3no22040833igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Dec 2015 22:03:58 -0800 (PST) In-Reply-To: <62ee3b9c-9ebd-4f7f-a33b-e73fb0f6ee8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.236.158.124; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 125.236.158.124 References: <62ee3b9c-9ebd-4f7f-a33b-e73fb0f6ee8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Physical unit ambiguities From: diogratia@gmail.com Injection-Date: Mon, 28 Dec 2015 06:03:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4199 On Monday, December 28, 2015 at 3:22:46 PM UTC+13, KJ wrote: > On Saturday, December 26, 2015 at 8:07:55 PM UTC-5, valtih1978 wrote: > > Another ambiguity comes from > >=20 > > literal ::=3D numeric_literal | enumeration_literal | ... > > numeric_literal ::=3D physical_literal | ... > > physical_literal ::=3D [ abstract_literal ] name > > name ::=3D identifier | operator_symbol | character_literal |=20 > > selected_name | indexed_name | slice_name | attribute_name > > enumeration_literal ::=3D identifier | ... > >=20 >=20 > According to VHDL-2000, 2002 and 2008 > physical_literal ::=3D [ abstract_literal ] unit_name >=20 > physical_literal is not defined as you have posted as > physical_literal ::=3D [ abstract_literal ] name >=20 > 'unit_name' is not further defined in the specifications, however 'unit n= ame' is defined. Darn those inconsistent humans anyway. The unit_ part of unit_name is shown in italics, which has meaning: IEEE Std 1076-2008 1.3.2 Syntactic description: g) If the name of any syntactic category starts with an italicized part, it= is equivalent to the category name without the italicized part. The italic= ized part is intended to convey some semantic information. For example, typ= e_name and subtype_name are both syntactically equivalent to name alone. -- You can while away some time reading up on syntactic predicates. You could also read 5.2.4 Physical types paragraph 5 for the semantic meani= ng here: Each unit declaration (either the primary unit declaration or a secondary u= nit declaration) defines a unit name. Unit names declared in secondary unit= declarations shall be directly or indirectly defined in terms of integral = multiples of the primary unit of the type declaration in which they appear.= The position numbers of unit names need not lie within the range specified= by the range constraint. -- Para 7: The abstract literal portion (if present) of a physical literal appearing i= n a secondary unit declaration shall be an integer literal. -- And para 9: There is a position number corresponding to each value of a physical type. = The position number of the value corresponding to a unit name is the number= of primary units represented by that unit name. The position number of the= value corresponding to a physical literal with an abstract literal part is= the largest integer that is not greater than the product of the value of t= he abstract literal and the position number of the accompanying unit name. -- Essentially that unit name has to be a declared primary or secondary unit n= ame, despite trying to abstract it to simply a name. You could note that a = unit name is guaranteed to be represented by not just any name, a simple na= me, 1.3.2: h) The term simple_name is used for any occurrence of an identifier that al= ready denotes some declared entity. -- Also see 8.2 Simple names, the first sentence of the first paragraph: A simple name for a named entity is either the identifier associated with t= he entity by its declaration or another identifier associated with the enti= ty by an alias declaration. -- And the following BNF: simple_name ::=3D identifier -- So there's a semantic restriction that limits unit_name to the simple name = (an identifier) of a declared unit. From newsfish@newsfish Thu Aug 1 00:35:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Mon, 28 Dec 2015 13:08:50 -0000 (UTC) Organization: A noiseless patient Spider Lines: 76 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 28 Dec 2015 13:08:50 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="22038"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18XdNnrdsxUARnleMUNHe2XxRjmHQ34z98=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:jfPsYBky/qxOm+OTWgxLunuT9Ys= Xref: news.eternal-september.org comp.lang.vhdl:4200 On Sun, 27 Dec 2015 17:33:10 -0800, KJ wrote: > If you'd like another example of a discrepancy between BNF and the text, > here you go... > Section 5.2.3.1 (General Integer types) > "An implementation may restrict the bounds of the range constraint of > integer types other than type universal_integer. However, an > implementation shall allow the declaration of any integer type whose > range is wholly contained within the bounds -2147483647 and +2147483647 > inclusive." The term "literal" does not appear here, nor is there any statement that every valid value is directly representable as a literal. ( More precisely, any such statement is not part of the quoted material. I haven't found one elsewhere either) > Section 9.3.2 Literals "numeric_literal ::= abstract_literal | > physical_literal Numeric literals include literals of the abstract types > universal_integer and universal_real, as well as literals of physical > types. Abstract literals are defined in 15.5; physical literals are > defined in 5.2.4.1." Nor does this state that the range of literals covers the entire range of values. > So, clearly -1 should be considered a numeric literal. I think that requires an inference that is not stated in the quoted passages above. > But now look at > the BNF. abstract_literals are numeric_literals. > > Section 15.5.1: abstract_literal ::= decimal_literal Section 15.5.2: > decimal_literal ::= integer [ . integer ] [ exponent ] > integer ::= digit { [ underline ] digit } exponent ::= E [ + ] > integer | E - integer > > Now, where is the minus sign in the BNF? It's not there. Which suggests an alternative inference : only the naturals are representable as literals; negative values are expressed as the result of a negation operator on a positive literal. > So while the > section that defines integer literals specifically says that -2147483647 > is a literal, Where exactly? > the BNF does not support this since there is no way to put > in the minus sign per the BNF. So these two sections of the > specification conflict. The conflict exists only if the former section of the specification actually exists, which is not established by the quoted material. > To me, a reasonable interpretation to make is > that since there is a conflict with the specification itself, that there > should be no flagging of an error by a tool if source code adheres to > the narrative but not the BNF. But in the absence of conflict, there is no need to deviate from the BNF. > So the text -1 should be interpreted as an > integer literal. Not all folks agree and they think that the BNF must > trump narrative The BNF unambiguously parses -1 as [unary operator][literal]. If you additionally allow negative literals, how do you resolve the resulting ambiguous parsing? Considering also that operators are overloadable on return type... -- Brian From newsfish@newsfish Thu Aug 1 00:35:45 2024 X-Received: by 10.182.181.100 with SMTP id dv4mr48922935obc.47.1451313253666; Mon, 28 Dec 2015 06:34:13 -0800 (PST) X-Received: by 10.50.108.20 with SMTP id hg20mr830387igb.5.1451313253640; Mon, 28 Dec 2015 06:34:13 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no15889491igc.0!news-out.google.com!f6ni36253igq.0!nntp.google.com!mv3no22220957igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Dec 2015 06:34:13 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:352c:4b9:87c4:c93a; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:352c:4b9:87c4:c93a References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ebe89ed-617f-4cf5-a701-f1581e38b02f@googlegroups.com> Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Mon, 28 Dec 2015 14:34:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4201 On Monday, December 28, 2015 at 8:11:29 AM UTC-5, Brian Drummond wrote: > On Sun, 27 Dec 2015 17:33:10 -0800, KJ wrote: >=20 > > If you'd like another example of a discrepancy between BNF and the text= , > > here you go... > > Section 5.2.3.1 (General Integer types) > > "An implementation may restrict the bounds of the range constraint of > > integer types other than type universal_integer. However, an > > implementation shall allow the declaration of any integer type whose > > range is wholly contained within the bounds -2147483647 and +2147483647 > > inclusive." >=20 > The term "literal" does not appear here, > More precisely, any such statement is not part of the quoted material. I= =20 > haven't found one elsewhere either) >=20 You didn't look too hard. I see you chose to write this before you read th= e next paragraph that I wrote or the section that I referenced in the speci= fication. Maybe you'll read it this time. section 5.2.3.1 (Integer types general) "Integer literals are the literals of an anonymous predefined type that is = called universal_integer in this standard. Other integer types have no lite= rals. However, for each integer type there exists an implicit conversion th= at converts a value of type universal_integer into the corresponding value = (if any) of the integer type (see 9.3.6)." > > Section 9.3.2 Literals "numeric_literal ::=3D abstract_literal | > > physical_literal Numeric literals include literals of the abstract type= s > > universal_integer and universal_real, as well as literals of physical > > types. Abstract literals are defined in 15.5; physical literals are > > defined in 5.2.4.1." >=20 > Nor does this state that the range of literals covers the entire range of= =20 > values. >=20 You've gone off the deep end now. The sections I've cited do establish the= range. > > So, clearly -1 should be considered a numeric literal. =20 >=20 > I think that requires an inference that is not stated in the quoted=20 > passages above. >=20 Then you're part of the small group that accepts: 1. "Integer literals are the literals of an anonymous predefined type that = is called universal_integer" (5.2.3.1) 2. "Numeric literals include literals of the abstract types universal_integ= er" (9.3.2) 3. "integer type whose range is wholly contained within the bounds -2147483= 647 and +2147483647 inclusive." (5.2.3.1) 4. "...may restrict the bounds of the range constraint of integer types oth= er than type universal_integer" 5.2.3.1 But do not think that -1 is a numeric literal. > >=20 > > Now, where is the minus sign in the BNF? It's not there. =20 >=20 > Which suggests an alternative inference : only the naturals are=20 > representable as literals; negative values are expressed as the result of= =20 > a negation operator on a positive literal. Which contradicts the previously cited section 5.2.3.1 "integer type whose = range is wholly contained within the bounds -2147483647 and +2147483647 inc= lusive." > > the BNF does not support this since there is no way to put > > in the minus sign per the BNF. So these two sections of the > > specification conflict.=20 >=20 > The conflict exists only if the former section of the specification=20 > actually exists, which is not established by the quoted material. >=20 It is established, you don't accept it. There is a difference. Or if you'= d prefer, I don't accept the position that you've put forth and you do not = accept mine. >=20 > The BNF unambiguously parses -1 as [unary operator][literal]. If you=20 > additionally allow negative literals, how do you resolve the resulting=20 > ambiguous parsing?=20 >=20 Correcting the problem is not my job, I'm simply pointing out the discrepan= cy. As you already know, the discrepancy has also been pointed out to the = proper authorities who decline official comment as representatives of the V= HDL standard. The narrative of the specification establishes that negative numbers are nu= meric literals. The BNF does not. If there is something in the language s= pecification that says the narrative can be ignored in case of a conflict w= ith the BNF, then you would do well to quote that rather than trundling dow= n the path you're on. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:45 2024 X-Received: by 10.182.142.8 with SMTP id rs8mr25000773obb.33.1451330284791; Mon, 28 Dec 2015 11:18:04 -0800 (PST) X-Received: by 10.50.36.3 with SMTP id m3mr856392igj.0.1451330284729; Mon, 28 Dec 2015 11:18:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!mv3no22341376igc.0!news-out.google.com!l1ni5330igd.0!nntp.google.com!mv3no22341365igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Dec 2015 11:18:04 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=98.176.234.81; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 98.176.234.81 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4096a666-a77b-4a2c-98ec-fdeaa2f15ec3@googlegroups.com> Subject: Re: Literals UO"2C" = B"011_CCC"? From: Jim Lewis Injection-Date: Mon, 28 Dec 2015 19:18:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4202 The LRM is the conjunction of the BNF rules and the text. If a rule is concisely and accurately specified in the BNF, then there is no additional text. OTOH, some of the BNF is more general and the text provides further constraints. Perhaps you can download one of the free simulators and test out the cases you are concerned about. IE, how other simulators handle " in a string. From newsfish@newsfish Thu Aug 1 00:35:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Mon, 28 Dec 2015 22:46:32 +0200 Organization: A noiseless patient Spider Lines: 85 Message-ID: <56819FA8.90204@not.email.me> References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4367"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX193UY8/29vPgYe8oOemwjaKE+JtwYYTH44=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:RtgkkmBNcamJOq5rUZocGJteKUA= Xref: news.eternal-september.org comp.lang.vhdl:4203 On 28.12.2015 3:33, KJ wrote: > There is more to the language specification than the BNF. In this > particular case, the following text is relevant (all from VHDL-2008) > Section 15.7 (String literals): "If a quotation mark value is to > be represented in the sequence of character values, then a pair > of adjacent quotation marks shall be written at the corresponding > place within the string literal. (This means that a string literal > that includes two adjacent quotation marks is never interpreted as > two adjacent string literals.)" > There is an example which shows that """" (four consecutive quotation > marks) is a string literal of length 1. Yes, I know. We have established this already. > Section 15.8 (Bit String Literals): "A bit string literal has a > value that is a string literal" I have overlooked it indeed. But, think a little. What does it mean? IMO, it addresses the output of the conversion. The bit string literal is a function that takes integers in various bases and produces binary strings. It produces string literals. Binary vectors are nothing more than just string literals. There is a bit_string_literal form which allows you to avoid specifying every single bit (which is a pain even for short 8-bit words) in the more compact form, like 16"FFFFFFFF" instead of 32 ones. The bit string literal supports special characters for don't care-like bit strings. The standard just says that characters besides digits and "ABCDF" are copy-pasted into the output string literal. So, 16"F-" is translated into "1111----". The result is string_literal. This way, standard admits double quotes, if you place them instead of don't care '-' sign. Now, what does the fact that value is the same as quadrupled '"' character tell to us? What should the input bit_string_literal look like? Does LRM stipulate this case? Is it ok? And what should poor compiler do? To revise, string_literal ::= " { graphic_character } " bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] " bit_value ::= graphic_character { [ underline ] graphic_character } graphic_character :: == something including quotation mark if user enters "" for every " in the parsed string_literal, what should be the input for bit_string_literal to achieve the same result? > If you'd like another example of a discrepancy between BNF and the text, here you go... > Section 5.2.3.1 (General Integer types) > "An implementation may restrict the bounds of the range constraint of integer types other than type > universal_integer. However, an implementation shall allow the declaration of any integer type whose range is wholly contained within the bounds -2147483647 and +2147483647 inclusive." > > Section 9.3.2 Literals > "numeric_literal ::= abstract_literal | physical_literal > Numeric literals include literals of the abstract types universal_integer and universal_real, as well as literals of physical types. Abstract literals are defined in 15.5; physical literals are defined in 5.2.4.1." > > So, clearly -1 should be considered a numeric literal. But now look at the BNF. abstract_literals are numeric_literals. > > Section 15.5.1: abstract_literal ::= decimal_literal > Section 15.5.2: decimal_literal ::= integer [ . integer ] [ exponent ] > integer ::= digit { [ underline ] digit } > exponent ::= E [ + ] integer | E - integer > > Now, where is the minus sign in the BNF? It's not there. So while the section that defines integer literals specifically says that -2147483647 is a literal, the BNF does not support this since there is no way to put in the minus sign per the BNF. So these two sections of the specification conflict. To me, a reasonable interpretation to make is that since there is a conflict with the specification itself, that there should be no flagging of an error by a tool if source code adheres to the narrative but not the BNF. The BNF is no more 'correct' than narrative (unless there is such a disclaimer somewhere in the specification that says so). So the text -1 should be interpreted as an integer literal. Not all folks agree and they think that the BNF must trump narrative and think that they are making their tool adhere 'closer' to the standard by using this interpretation when it is convenient...but they are ignoring something specifically called out in the standard. Oh well. Uou say that narrative admits the negative integers whereas there is no way to enter them in BNF. You call it a contradiction but I do not see any problem here. You simply allocate internal variable of Int type for every literal that you keep in your tool and do not use the negative part of it. You will get negatives by applying the "-" operation to the literal, as Brain pointed out. It is fine. The user writes -100 and it is parsed as operation followed by literal. The code is parsed, elaboreated and smoothly processed further by the back end. It is not efficient but it is not stopper. Where is the conflict, where is the problem? I do not think that you can treat it equally with the issues that I have raised. The double quote and physical unit is simply unparsable. Yestuday, I have discovered one more conflict of this kind. function_call ::= name [(args)] How do you distinguish it from a simple identifier if arguments are not specified? From newsfish@newsfish Thu Aug 1 00:35:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Physical unit ambiguities Date: Mon, 28 Dec 2015 23:03:48 +0200 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <62ee3b9c-9ebd-4f7f-a33b-e73fb0f6ee8d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Dec 2015 21:01:14 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4eaed61cc34cf27306084f6070dcb276"; logging-data="8793"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ytq6p7nhVka+Hfbm9vZxbLusFtza8FNA=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:Tzu6VMw4CSclP41SxB9hAq23p/I= Xref: news.eternal-september.org comp.lang.vhdl:4204 Ok, in such a complex way you seem to simply say that there is no chance that any other than simple name succeeds for the unit literal. This makes sense. Thanks. It seems that parser can reduce the physical_literal to physical_literal ::= [num] simple_name No, wait. I guess they have "abstracted" it to the more general name to enable extended names! In 2008 you can refer units in the other modules. From newsfish@newsfish Thu Aug 1 00:35:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Mon, 28 Dec 2015 16:13:42 -0500 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Dec 2015 21:11:09 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="11211"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/M9qOVKl0wF7GXM+HknzwF" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: <56819FA8.90204@not.email.me> Cancel-Lock: sha1:mOCvFn4rvq/TFeEZOKr6ZihbhuI= Xref: news.eternal-september.org comp.lang.vhdl:4205 On 12/28/2015 3:46 PM, valtih1978 wrote: > > How do you distinguish it from a simple identifier if arguments are not > specified? Context. It is not at all unusual for interpretation to depend on context. -- Rick From newsfish@newsfish Thu Aug 1 00:35:47 2024 X-Received: by 10.66.102.8 with SMTP id fk8mr49933600pab.40.1451358855785; Mon, 28 Dec 2015 19:14:15 -0800 (PST) X-Received: by 10.50.25.196 with SMTP id e4mr219696igg.8.1451358855754; Mon, 28 Dec 2015 19:14:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no22502499igc.0!news-out.google.com!l1ni5694igd.0!nntp.google.com!mv3no22502498igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Dec 2015 19:14:14 -0800 (PST) In-Reply-To: <56819FA8.90204@not.email.me> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Tue, 29 Dec 2015 03:14:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4206 On Monday, December 28, 2015 at 3:46:36 PM UTC-5, valtih1978 wrote: > On 28.12.2015 3:33, KJ wrote: > > Section 15.8 (Bit String Literals): "A bit string literal has a > > value that is a string literal" >=20 > I have overlooked it indeed. >=20 Now, what does the fact that value is the same as quadrupled '"' > character tell to us? What should the input bit_string_literal look like? >=20 Section 15.8, says "For a character in the simplified value that is not int= erpreted as an extended digit, each character in the replacement sequence i= s the same as the character replaced." So if you run across a " or a "" in the input, it should be copied over as-= is into the output unchanged. > Does LRM stipulate this case? Is it ok? And what should poor compiler do? >=20 Since a " would end up not being a legal bit value when you're all done con= verting and an error is going to be flagged anyway, I would think a compile= r could stop and flag the error at that point. > Uou say that narrative admits the negative integers whereas there is no= =20 > way to enter them in BNF. You call it a contradiction but I do not see=20 > any problem here. You simply allocate internal variable of Int type for= =20 > every literal that you keep in your tool and do not use the negative=20 > part of it. You will get negatives by applying the "-" operation to the= =20 > literal, as Brain pointed out. It is fine. No it's not. There are instances where it mattered. One particular tool t= ook a declaration that had a negative number where a numeric literal was ex= pected and complained saying that it was not a numeric_literal. I don't want to hijack this thread to go into that issue any further. My o= nly point in bringing it up here is that since the LRM is produced by human= beings, it is not out of the question that the BNF does not comply with th= e narrative but that does not imply that the narrative is wrong. Unless sp= ecifically disclaimed, the whole document is on equal footing. >=20 > I do not think that you can treat it equally with the issues that I have= =20 > raised. Right, only things that you bring up are important. Gotcha. > The double quote and physical unit is simply unparsable.=20 Well, other tools I assume are able to parse it, although I admit I haven't= bothered to try to insert a " into a bit string to see what happens. I'm = only giving my take on why the "" appears to be the way to include the " an= d that the LRM does specify this (in my opinion, maybe not yours) > Yestuday, I have discovered one more conflict of this kind. >=20 > function_call ::=3D name [(args)] >=20 > How do you distinguish it from a simple identifier if arguments are not= =20 > specified? In your example, 'name' will be the name of the function that has already b= een defined previously in the source code as a function with no arguments. = The vocabulary keeps expanding as source code is processed. It starts wit= h only the keywords, then adds on everything else that gets declared. Not = sure why you see any issue here. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Tue, 29 Dec 2015 11:09:30 +0200 Organization: A noiseless patient Spider Lines: 83 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Dec 2015 09:06:55 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="907"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19PScKewGP7+796MlworTGE+PJ+n03cOKI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:7tKR5rqE7Oalgl9FS29oYBrtBhI= Xref: news.eternal-september.org comp.lang.vhdl:4207 >> Now, what does the fact that value is the same as quadrupled '"' >> character tell to us? What should the input bit_string_literal look like? > Section 15.8, says "For a character in the simplified value that is not > interpreted as an extended digit, each character in the replacement sequence > is the same as the character replaced." > So if you run across a " or a "" in the input, it should be copied over as-is > into the output unchanged. And now my question again: what should user input look like? I can copy over '-' to get "----" in the resulting string literal value. What should user enter to get '"' instead of '-'? Saying 'copy, as-is' means that user should enter single "-mark in the bit vector literal instead of -mark, right? Or what? Meantime you say that they need to be duplicated to circumvent the BNF grammar. > Since a " would end up not being a legal bit value when you're all done > converting and an error is going to be flagged anyway, I would think > a compiler could stop and flag the error at that point. I have heard that several times already and never received the answer "why illegal". Who says 'illegal'? Why '-' is legal but '"' is illegal? Should I constrain legal bit string values to those used in bit or std_logic? My impression always was that user can define its own logic values and use whatever characters are legal in the enumeration. Why is '"' illegal? Is my convincing wrong? Moreover, you say that bit vector has the same values as string_literal. Does it mean that '"' is illegal in the string_literal? >> I do not think that you can treat it equally with the issues that I have >> raised. > > Right, only things that you bring up are important. Gotcha. First, this is a fascism. It is a fascism to say that "we are right because these are we". Secondly, this is your position. You say LRM creates a problem because your tool had a bug. But it is not, as we explained. Third, you say that this is mine position, despite I discuss the LRM rather than a bug in your tool. I have explained why there is no problem with negatives. You should point to a flaw in my logic rather than say that I must buy whatever you say or I am a unconscious bastard. >> The double quote and physical unit is simply unparsable. > Well, other tools I assume are able to parse it, although I admit I > haven't bothered to try to insert a " into a bit string to see what > happens. I have even looked in source code of such a tool. Why am I still here? > >> Yestuday, I have discovered one more conflict of this kind. >> >> function_call ::= name [(args)] >> >> How do you distinguish it from a simple identifier if arguments are not >> specified? > > In your example, 'name' will be the name of the function that has > already been defined previously in the source code as a function with > no arguments. The vocabulary keeps expanding as source code is processed. > It starts with only the keywords, then adds on everything else that gets > declared. Not sure why you see any issue here. Because "vocabulary" is the collection of scopes that you get during elaboration, which seems to be a step supposed to happen after the parse has finished. Meantime, VHDL seems to be context-sensitive language and cannot parse without elaborating immediately. That is to parse a(b), your parser must beware that a is a type or a function to choose a corresponding grammar production, whether it should be a type conversion or array indexing or function call. There should be elaborated model to tell you that. At the same time, LRM presents material as if elaboration is a thrid step following 1) parsing and 2) analysis. All tools that I have used perpetuate this approach when propose you to select the top level for elaboration after parsing completed. The dilemma "to combine elaboration with parsing or elaborate afterwards" leaves me very puzzled. Your hints suggest that I must combine the two. From newsfish@newsfish Thu Aug 1 00:35:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Tue, 29 Dec 2015 11:15:21 +0200 Organization: A noiseless patient Spider Lines: 18 Message-ID: <56824F29.7090403@not.email.me> References: <4096a666-a77b-4a2c-98ec-fdeaa2f15ec3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="2013"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/nI02iZfzAK8lyUuhCuNyJYNwQxVAKHCA=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <4096a666-a77b-4a2c-98ec-fdeaa2f15ec3@googlegroups.com> Cancel-Lock: sha1:iOtXdKIeKLLhazpVIZUnTsuGLsg= Xref: news.eternal-september.org comp.lang.vhdl:4208 On 28.12.2015 21:18, Jim Lewis wrote: > The LRM is the conjunction of the BNF rules and the text. If a rule is > concisely and accurately specified in the BNF, then there is no additional text. > OTOH, some of the BNF is more general and the text provides further constraints. That was my impression. Thanks for explicating it. The problem is that I started this thread because I could not find the additional text on bis vector literals with embedded quote marks. Ok? > Perhaps you can download one of the free simulators and test out the cases you > are concerned about. IE, how other simulators handle " in a string. I have even looked into the source code of the tool. I am not convinced however that one implementation should be used as ultimate specification when LRM is unclear. Why cannot people at compl.lang.vhdl simply provide the missing narrative or point to the existing one? From newsfish@newsfish Thu Aug 1 00:35:48 2024 X-Received: by 10.182.128.39 with SMTP id nl7mr57903681obb.13.1451437026267; Tue, 29 Dec 2015 16:57:06 -0800 (PST) X-Received: by 10.50.25.196 with SMTP id e4mr311444igg.8.1451437026245; Tue, 29 Dec 2015 16:57:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!mv3no22948687igc.0!news-out.google.com!f6ni37643igq.0!nntp.google.com!mv3no16330347igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Dec 2015 16:57:05 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Wed, 30 Dec 2015 00:57:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 134 X-Received-Bytes: 7834 X-Received-Body-CRC: 4221498830 Xref: news.eternal-september.org comp.lang.vhdl:4209 On Tuesday, December 29, 2015 at 4:09:35 AM UTC-5, valtih1978 wrote: > >> Now, what does the fact that value is the same as quadrupled '"' > >> character tell to us? What should the input bit_string_literal look li= ke? >=20 > > Section 15.8, says "For a character in the simplified value that is not > > interpreted as an extended digit, each character in the replacement=20 > sequence > > is the same as the character replaced." >=20 > > So if you run across a " or a "" in the input, it should be copied over= as-is > > into the output unchanged. >=20 > And now my question again: what should user input look like? And my answer again (last time though) is from section 15.8 "For a characte= r in the simplified value that is not interpreted as an extended digit, eac= h character in the replacement sequence is the same as the character replac= ed." So, if the character cannot be interpreted as an extended digit, then= 'what comes in is what goes out...unchanged'. Can't be any clearer than t= hat. > I can copy=20 > over '-' to get "----" in the resulting string literal value. Not according to my interpretation of the VHDL specification. Again, quoti= ng section 15.8: (capitalized text is mine for emphasis, not for shouting) "If the base specifier is O, UO, or SO, the digits 0 through 7 in the bit v= alue are interpreted as extended digits, AND ALL OTHER GRAPHIC CHARACTERS A= RE NOT INTERPRETED AS EXTENDED DIGITS. If the base specifier is X, UX or SX= , all digits together with the letters A through F in the bit value are int= erpreted as extended digits. If the base specifier is D, all of the graphic= characters in the bit value (not counting underline characters) shall be d= igits" Now, you could look at that and say that the 'and all other graphic charact= ers...' phrase only applies to octal format since that is conspicuously the= only format that includes that phrase. However, like the octal format, th= e hex format clearly details which characters are extended digits so if you= take some other character such as - or " it is clearly not an extended dig= it even without the phrase 'and all other graphic characters...' No characters other than 0 thru 9 and A thru F are listed in the table that= follows that defines the bit replacements for extended digits. Specifical= ly, the character '-' is not listed so if you think that something is conve= rting a single '-' into '----' than this conversion is something other than= what the language specification is calling out in regards to a bit string = literal. > What should user enter to get '"' instead of '-'? Saying 'copy, as-is' me= ans that user should enter single "-mark in the bit vector literal instead= =20 > of -mark, right? Or what?=20 Input Output What it represents in the bit vector literal - - The single dash character -, ASCII 45 or 2D hex "" "" The single quotation mark ", ASCII 34 or 22 hex Again, all of this is my interpretation of the LRM, everyone can have one. = There is no ultimate authority that will issue a judgment on an interpreta= tion of the standard declaring person #1 to be correct, person #2 to be inc= orrect. There is no Supreme Court of the VHDL standard. There used to be,= but no longer. I've asked. So take whatever interpretation you think is = best for your purposes and go run with it, that's what everyone else is doi= ng. >=20 > Moreover, you say that bit vector has the same values as string_literal.= =20 I quoted the VHDL specification. >=20 > >> I do not think that you can treat it equally with the issues that I ha= ve > >> raised. > > > > Right, only things that you bring up are important. Gotcha. >=20 > First, this is a fascism. It is a fascism to say that "we are right=20 > because these are we". fascism ::=3D an authoritarian and nationalistic right-wing system of gover= nment and social organization. I think not...and your use of that word in this forum clearly demonstrates = your lack of any level of professionalism. Secondly your nonsensical quote= "we are right because these are we" is not something attributable to me, o= nly to you. I've given you enough on this thread, so this will be my last. If you can'= t read the specification and interpret it yourself too bad. With the belli= gerent attitude that you demonstrate towards people who are attempting to h= elp you at YOUR OWN request, I would suspect that you will have a hard time= finding someone who will. People can have disagreements in this forum or = elsewhere without going off like they are deranged, perhaps you should give= it a try. > Secondly, this is your position. You say LRM=20 > creates a problem because your tool had a bug. I never said it was MY tool...and, for the record, it is not. But I see th= at you now agree that the tool has a bug...which seems to contradict your e= arlier position, but I don't care. > But it is not, as we explained.=20 That's your position > Third, you say that this is mine position, despite I discuss=20 > the LRM rather than a bug in your tool. I quoted and referenced the LRM, you, not so much. Again, it's not my tool= . > I have explained why there is no=20 > problem with negatives. You should point to a flaw in my logic rather=20 > than say that I must buy whatever you say or I am a unconscious bastard. >=20 I did point out the flaw in your logic and I'll repeat one last time. If t= here is a specific case where the LRM only allows a literal to be placed (a= nd there are such places), AND the literal is a negative number such as -1,= THEN according to the BNF defining the literal, the tool should flag an er= ror BUT according to the narrative which also defines a literal, the negati= ve number should be accepted. >=20 > I have even looked in source code of such a tool. Why am I still here? >=20 I don't know. Why would you post a question that only you know the answer?= Maybe you should go elsewhere and see if anything is any better over ther= e. Done with this thread. Be well. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Tue, 29 Dec 2015 21:48:02 -0500 Organization: A noiseless patient Spider Lines: 68 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Dec 2015 02:45:33 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="24269"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18OMUCQ7KrNufNCwqItd+so" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:LPWs+siUR62+2makoTNg/Cuy5Cs= Xref: news.eternal-september.org comp.lang.vhdl:4210 On 12/29/2015 7:57 PM, KJ wrote: > On Tuesday, December 29, 2015 at 4:09:35 AM UTC-5, valtih1978 wrote: >>>> Now, what does the fact that value is the same as quadrupled >>>> '"' character tell to us? What should the input >>>> bit_string_literal look like? >> >>> Section 15.8, says "For a character in the simplified value that >>> is not interpreted as an extended digit, each character in the >>> replacement >> sequence >>> is the same as the character replaced." >> >>> So if you run across a " or a "" in the input, it should be >>> copied over as-is into the output unchanged. >> >> And now my question again: what should user input look like? > > And my answer again (last time though) is from section 15.8 "For a > character in the simplified value that is not interpreted as an > extended digit, each character in the replacement sequence is the > same as the character replaced." So, if the character cannot be > interpreted as an extended digit, then 'what comes in is what goes > out...unchanged'. Can't be any clearer than that. So the spec is saying that any character that is not treated as a digit is to be inserted into the bit string "as-is". So any character that does not "belong" to the bit string as in, not a valid value, will still be inserted into the bit string and you will find out the error only when some other part of the tool craps, not in the parser, right? >> I can copy over '-' to get "----" in the resulting string literal >> value. > Not according to my interpretation of the VHDL specification. Again, > quoting section 15.8: (capitalized text is mine for emphasis, not for > shouting) > > "If the base specifier is O, UO, or SO, the digits 0 through 7 in the > bit value are interpreted as extended digits, AND ALL OTHER GRAPHIC > CHARACTERS ARE NOT INTERPRETED AS EXTENDED DIGITS. If the base > specifier is X, UX or SX, all digits together with the letters A > through F in the bit value are interpreted as extended digits. If the > base specifier is D, all of the graphic characters in the bit value > (not counting underline characters) shall be digits" > > Now, you could look at that and say that the 'and all other graphic > characters...' phrase only applies to octal format since that is > conspicuously the only format that includes that phrase. However, > like the octal format, the hex format clearly details which > characters are extended digits so if you take some other character > such as - or " it is clearly not an extended digit even without the > phrase 'and all other graphic characters...' > > No characters other than 0 thru 9 and A thru F are listed in the > table that follows that defines the bit replacements for extended > digits. Specifically, the character '-' is not listed so if you > think that something is converting a single '-' into '----' than this > conversion is something other than what the language specification is > calling out in regards to a bit string literal. When converting a hex value I believe each non-hex character is assigned to each of the four bits for that character. For an octal format aren't non-octal characters assigned to three bit positions? Not sure how decimal is handled... -- Rick From newsfish@newsfish Thu Aug 1 00:35:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Wed, 30 Dec 2015 13:40:05 +0200 Organization: A noiseless patient Spider Lines: 163 Message-ID: <5683C295.7020200@not.email.me> References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="4eaed61cc34cf27306084f6070dcb276"; logging-data="11558"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+fFVwJ9gWvafUIK7jvyfeu6VrE5NVVxbM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:9FfMOQ+iN7aPlrQufelYKMaYFeY= Xref: news.eternal-september.org comp.lang.vhdl:4211 You say that VHDL spec says me what to do with bit vector literals and then say that there is not ultimate authority. > copy as-is means - - The single dash character -, ASCII 45 or 2D hex "" "" The single quotation mark ", ASCII 34 or 22 hex The fact you ignore again is that taking user intput "as-is" this way will result in string literal value with duplicated quotation marks embedded in it. Also, it is inconsistent with the issue of legality. You say that doing it is illegal in the other parts of discussion, which is not least puzzling. >> I can copy >> over '-' to get "----" in the resulting string literal value. >Not according to my interpretation of the VHDL specification. Again, quoting section 15.8: (capitalized text is mine for emphasis, not for shouting) >"If the base specifier is O, UO, or SO, the digits 0 through 7 in the bit value are interpreted as extended digits, AND ALL OTHER GRAPHIC CHARACTERS ARE NOT INTERPRETED AS EXTENDED DIGITS. If the base specifier is X, UX or SX, all digits together with the letters A through F in the bit value are interpreted as extended digits. If the base specifier is D, all of the graphic characters in the bit value (not counting underline characters) shall be digits" >Now, you could look at that and say that the 'and all other graphic characters...' phrase only applies to octal format since that is conspicuously the only format that includes that phrase. However, like the octal format, the hex format clearly details which characters are extended digits so if you take some other character such as - or " it is clearly not an extended digit even without the phrase 'and all other graphic characters...' > No characters other than 0 thru 9 and A thru F are listed in the table that follows that defines the bit replacements for extended digits. Specifically, the character '-' is not listed so if you think that something is converting a single '-' into '----' than this conversion is something other than what the language specification is calling out in regards to a bit string literal. It is especially funny after > if the character cannot be interpreted as an extended digit, then 'what comes in is what goes out...unchanged'. You seem not even notice that you have two contradictory statements, '-' must be expanded into "----" and it must not, supported by the specification. And you say that "It can't be any clearer than that". I must be clearly stupid not to understand this contradiction, right? I cannot build up a solid consistent picture of the pieces you shuffle all the way. Correcting myself, I obviously asked for validity of X"F-" => "1111----" when written 16"F-". You seems to realized that when drawn attention to impossibility to expand '-' into "----" according to VHDL spec. Just try to interpret those examples from the same VHDL spec 12UX"F-" -- Equivalent to B"0000_1111_----" UO"2C" -- Equivalent to B"011_CCC" I started the topic with the latter one. C should not expand to CCC since C isn't an octal digit, right? > I never said it was MY tool...and, for the record, it is not. But I see that you now agree that the tool has a bug...which seems to contradict your earlier position, but I don't care. You are calling me lier referring to something. Very nice. Prove. Where did I contradict myself? Do you don't care so much to not bother to provide the evidence? > fascism ::= an authoritarian and nationalistic right-wing system of government and social organization. I think not... As with other definitions, you pick up one, inappropriate one, and demonstrate that opponent is an idiot. That seems very professional. How old are you? > and your use of that word in this forum clearly demonstrates your lack of any level of professionalism. Secondly your nonsensical quote "we are right because these are we" is not something attributable to me, only to you. Sure. The fact that you started to apply that name calling proves that it is me who is a piece of crap. It was me who diverted from discussing the substance into ad-hominem. These are mine words "only things that you bring up are important. Gotcha." Clearly, I called opponents fascists. Ad-hominem, based on ad-hominem makes you true professional. Fascists are everybody who supress others, no matter others are right because fascists define "right" exactly their point of view and domination. We are right because this are we, I am right because this is what I am telling you is a primitive nazi mind set. You probably was never tried to understand political views, what are people struggling for, if you reject this this as total bullshit. People do not struggle for dictatorship or system of government. They struggle for "their order". Here are "us", who must opress "them". That is fascism and it means that "us = right", "them = wrong". You accused me in having this stance. > With the belligerent attitude that you demonstrate towards people who are attempting to help you at YOUR OWN request I don't buy crap. Professionals never cover demagogy with "you are a bad person because you reject the help that I kindly provide. You must happily appreciate whatever I say or otherwise you are amoral person". These are not professionals but fascists. Professionals address the matter or pass by. I raised an issue for interested people rather than those who just pick arbitrary pieces of spec and force me to eat it without letting me to build a solid picture. > BUT according to the narrative which also defines a literal, the negative number should be accepted. I can repeat my "contradictory earlier statement": the narrative says that your account should support both positive and negative top-ups whereas cache-in machine accepts only positive amounts. Using the machine won't cause any failure whatsoever. You approach the machine, put money in -- done. Never fails. Same with VHDL parser: you feed valid number literals, BNF splits them into sign operation and (positive) integer -- never fails. VHDL parsing never fails. Now, some madcap has "fixed" the BNF and got some error. Why spec is to guilt? Even Jim points out that narrative takes preference only to narrow the BNF down: > some of the BNF is more general and the text provides further constraints. Your tool (nobody else cares about it -- it is your tool) instead did the opposite. It took valid BNF and generalized it. I am talking about situation where BNF fails and there seems no narrative to figure out the stance on embedded quotation mark. That is a real problem. You cannot parse VHDL. There is a big difference between you can parser VHDL (there is not conflict) and you have not idea how to do this. The former case resolves naturally. The latter has no resolution (I have got none yet). Tell me what's more important. >> I have even looked in source code of such a tool. > Why am I still here? > I don't know. Why would you post a question that only you know the answer? Somebody pointing out inconsistencies in your logic is not accepted in this forum, for many reasons. Saying that "not eating my shit" = "posting unanswerable question" is one of such reasons. You force me to eat shit or get away. You is a true professionalism. Regards to that. I only care about VHDL, not your tool or other tools. I want to know how is it supposed to be, if it is my omission not being able to see specified resolution or it is a real gap in the spec. Surely, comp.lang.vhdl is not the place to figure this out. From newsfish@newsfish Thu Aug 1 00:35:49 2024 X-Received: by 10.66.160.3 with SMTP id xg3mr56263950pab.35.1451487159662; Wed, 30 Dec 2015 06:52:39 -0800 (PST) X-Received: by 10.50.28.20 with SMTP id x20mr1012381igg.3.1451487159628; Wed, 30 Dec 2015 06:52:39 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no23201828igc.0!news-out.google.com!l1ni7130igd.0!nntp.google.com!mv3no23201821igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Dec 2015 06:52:39 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d342566-3228-4d18-b63c-ffa9bd23c930@googlegroups.com> Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Wed, 30 Dec 2015 14:52:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4212 On Tuesday, December 29, 2015 at 7:57:09 PM UTC-5, KJ wrote: > > > So if you run across a " or a "" in the input, it should be copied=20 > > > over as-is into the output unchanged. Actually, after re-reading, I see that I missed the following in section 15= .8 where it says "the expanded bit value is the string obtained by replacin= g each character of the simplified bit value by a sequence of three (respec= tively four) characters." So any character like a - will be replicated thr= ee (for octal) or four times (for hex). Other than the digits 0-9 and char= acters A-F, the underline character is the only special case character sinc= e "The string literal is formed from the bit value by first obtaining a sim= plified bit value, consisting of the bit value with underline characters re= moved,..." which is to allow you to write "1111_1111" and more clearly see = that it is eight bits. Input Output Interpretation - --- or ---- Three or four dashes depending on whether octal or he= x "" """""" or """""""" Three or four " depending on whether octal or = hex Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:49 2024 X-Received: by 10.66.62.162 with SMTP id z2mr14196691par.5.1451488388570; Wed, 30 Dec 2015 07:13:08 -0800 (PST) X-Received: by 10.50.160.4 with SMTP id xg4mr1014087igb.2.1451488388516; Wed, 30 Dec 2015 07:13:08 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no16477135igc.0!news-out.google.com!l1ni7132igd.0!nntp.google.com!mv3no16477127igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Dec 2015 07:13:07 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4386e156-aeaa-4356-8b6e-c95c7857f017@googlegroups.com> Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Wed, 30 Dec 2015 15:13:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4213 On Tuesday, December 29, 2015 at 9:48:13 PM UTC-5, rickman wrote: > So the spec is saying that any character that is not treated as a digit= =20 > is to be inserted into the bit string "as-is". So any character that=20 > does not "belong" to the bit string as in, not a valid value, will still= =20 > be inserted into the bit string and you will find out the error only=20 > when some other part of the tool craps, not in the parser, right? Yes, almost. I had missed the sentence that says those other characters wi= ll be replicated three or four times for octal and hex, but that just means= that typing an 'M' as input will become 'MMM' or 'MMMM'. Secondly, the ch= aracters other than 0-9 and A-F are not invalid as far as being considered = a bit string literal but you're correct that something downstream will hope= fully complain when you try to interpret that bit string literal as a numbe= r as an example. > When converting a hex value I believe each non-hex character is assigned= =20 > to each of the four bits for that character. For an octal format aren't= =20 > non-octal characters assigned to three bit positions? Not sure how=20 > decimal is handled... >=20 Yes, you're correct. Again, I had missed the replication of the characters= as previously mentioned. But the replicated characters can be any charact= er other than the underscore. For decimal, there is no mention of any replication of characters as there = is with octal and hex so I interpret that meaning that D"35-" is an illegal= bit vector literal (SX"3W" on the other hand is a legal literal). For dec= imal, it says "If the base specifier is D, the simplified bit value is inte= rpreted as a decimal integer. The expanded bit value is a string of 0 and 1= digits that is the binary representation of the decimal integer. The numbe= r of characters in the expanded bit value is given by the expression , wher= e n is the value of the decimal integer." Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Wed, 30 Dec 2015 20:44:42 +0200 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> <3d342566-3228-4d18-b63c-ffa9bd23c930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Dec 2015 18:42:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="8011"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19tm2md63OAMCvcS2BgynlXRcfk2XBSflE=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <3d342566-3228-4d18-b63c-ffa9bd23c930@googlegroups.com> Cancel-Lock: sha1:E7wgN6f20NbhUCrEr2YE8ZIGUzo= Xref: news.eternal-september.org comp.lang.vhdl:4214 > Other than the digits 0-9 and characters A-F, the underline character > is the only special case character since "The string literal is > formed from the bit value by first obtaining a simplified bit value, > consisting of the bit value with underline characters removed,..." and what is this > ---- = Three or four dashes depending on whether octal or hex You telling me how dash cannot become a part of output string literal and immediately complement your words with understanding how it does. Even 4 dashes instead of 1. Is string literal formed from them or not? Which kind of logic do you use? In VHDL, user can not only use the dash, which can you see only selectively, but can exploit any /*graphic_*/characters for his bit literals. All are accepted in string_literal, including all special characters, including quotation mark. That is the story about. Telling which characters are legitimate is fine but you better think a little before dictating them for me to record. Try to check your rules for consistency first. Building a solid picture helps a lot. From newsfish@newsfish Thu Aug 1 00:35:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Wed, 30 Dec 2015 19:58:59 -0000 (UTC) Organization: A noiseless patient Spider Lines: 164 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <5ebe89ed-617f-4cf5-a701-f1581e38b02f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 30 Dec 2015 19:58:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="28953"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+iFqM0sG9z6Q4+Bfnzg0mh7JHBuBNT7MA=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:ceA9Xn06fz2XNT9wWLg/Y/JZx1Y= Xref: news.eternal-september.org comp.lang.vhdl:4215 On Mon, 28 Dec 2015 06:34:13 -0800, KJ wrote: > On Monday, December 28, 2015 at 8:11:29 AM UTC-5, Brian Drummond wrote: >> On Sun, 27 Dec 2015 17:33:10 -0800, KJ wrote: >> >> > If you'd like another example of a discrepancy between BNF and the >> > text, >> > here you go... >> > Section 5.2.3.1 (General Integer types) >> > "An implementation may restrict the bounds of the range constraint of >> > integer types other than type universal_integer. However, an >> > implementation shall allow the declaration of any integer type whose >> > range is wholly contained within the bounds -2147483647 and >> > +2147483647 inclusive." >> The term "literal" does not appear here, > >> More precisely, any such statement is not part of the quoted material. >> I haven't found one elsewhere either) >> > You didn't look too hard. I see you chose to write this before you read > the next paragraph that I wrote or the section that I referenced in the > specification. Maybe you'll read it this time. > > section 5.2.3.1 (Integer types general) > "Integer literals are the literals of an anonymous predefined type that > is called universal_integer in this standard. Other integer types have > no literals. However, for each integer type there exists an implicit > conversion that converts a value of type universal_integer into the > corresponding value (if any) of the integer type (see 9.3.6)." Right. However, to repeat, this neither states nor implies that the integer literals are required to cover the full set of values. And as we shall see, an integer literal is explicitly not an integer value, but a textual representation of an integer value. This distinction appears to be the source of the so-called "discrepancy". To proceed... >> > Section 9.3.2 Literals "numeric_literal ::= abstract_literal | >> > physical_literal Numeric literals include literals of the abstract >> > types universal_integer and universal_real, as well as literals of >> > physical types. Abstract literals are defined in 15.5; physical >> > literals are defined in 5.2.4.1." >> >> Nor does this state that the range of literals covers the entire range >> of values. >> > You've gone off the deep end now. The sections I've cited do establish > the range. Certainly I have gone off the deep end and I can name the exact time and circumstance, but that's entirely irrelevant to *this* discussion. The sections you have cited certainly establish the range of integer *values* but not the range of integer *literals*. >> > So, clearly -1 should be considered a numeric literal. >> >> I think that requires an inference that is not stated in the quoted >> passages above. > Then you're part of the small group that accepts: > 1. "Integer literals are the literals of an anonymous predefined type > that is called universal_integer" (5.2.3.1) > 2. "Numeric literals include literals of the abstract types > universal_integer" (9.3.2) > 3. "integer type whose range is wholly contained within the bounds > -2147483647 and +2147483647 inclusive." (5.2.3.1) > 4. "...may restrict the bounds of the range constraint of integer types > other than type universal_integer" 5.2.3.1 None of which sections either identify *values* with *literals* nor require the literals to cover the full span of values. > But do not think that -1 is a numeric literal. Indeed so. In a bit more detail, you have established via 9.3.2 that an integer literal is an abstract literal. Which latter is ... 15.5.1 abstract_literal ::= decimal_literal | based_literal 15.5.2 decimal_literal ::= integer [ . integer ] [ exponent ] integer ::= digit { [ underline ] digit } (we can discount based literals) Now here is the first problem : `-` is not a digit, thus forming no part of the "integer" component of an abstract literal - despite the very *cough* real existence of negative integer *values*. To which you object the BNF must be incomplete or faulty, surely the text will clarify ... and it does. 15.3 Lexical elements, separators, and delimiters The text of each design unit, apart from text treated specially due to the effect of tool directives (see 15.11), is a sequence of separate lexical elements. Each lexical element is either a delimiter, an identifier (which may be a reserved word), an abstract literal, a character literal, a string literal, a bit string literal, a comment, ... Note here the word "either" - meaning exclusivity. And (still 15.3) A delimiter is either one of the following special characters (in the basic character set): & ' ( ) * + , - . / : ; < = > ` | [ ] ? @ Now, it is established that '-' is a delimiter. It CANNOT (thanks to "either") also form part of an abstract literal. It is also established that an "abstract literal" is a "lexical element" i.e. a textual representation of a value, which is certainly not the same thing as the value itself. >> > Now, where is the minus sign in the BNF? It's not there. >> >> Which suggests an alternative inference : only the naturals are >> representable as literals; negative values are expressed as the result >> of a negation operator on a positive literal. So we are now left with ONLY this alternative inference. > Which contradicts the previously cited section 5.2.3.1 "integer type > whose range is wholly contained within the bounds -2147483647 and > +2147483647 inclusive." Because literals /= values, and values /= literals, this is no contradiction. >> > the BNF does not support this since there is no way to put in the >> > minus sign per the BNF. So these two sections of the specification >> > conflict. >> >> The conflict exists only if the former section of the specification >> actually exists, which is not established by the quoted material. >> > It is established, you don't accept it. Oooohhh, noooo, it isn't!!! (in honour of pantomime season... if you're in a benighted land without pantomime, you'll just have to imagine that line delivered by an entire audience of screaming children) > If there is something in the > language specification that says the narrative can be ignored in case of > a conflict with the BNF, ... Because the narrative classes `-` as a delimiter, and thus explicitly not a component of an abstract literal, the narrative and the BNF appear fully in agreement in calling -1 the result of an operator with an abstract literal argument. No conflict, no need to ignore either. > ... then you would do well to quote that rather > than trundling down the path you're on. I hope this has been satisfactorily clarified. -- Brian > > Kevin Jennings From newsfish@newsfish Thu Aug 1 00:35:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "tuclogicguy" Newsgroups: comp.lang.vhdl Subject: Re: Wide bus Date: Fri, 1 Jan 2016 13:50:20 -0700 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Injection-Date: Fri, 1 Jan 2016 20:47:53 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0e31ff6ed6443f43d4ddd5802d1008e1"; logging-data="20560"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1802FUNuYpUWsGLhOtOsNDqC/yXCtVZ/AE=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6157 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:SLXEM+tzOGtSoBIi2AwUCq/SbcU= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:4216 wrote in message news:1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com... > Suppose I have an n-input simple OR gate. > > Result <= inp(0) or inp(1) or ...... or inp(n); > > Q: how to write the above code for generic n? > VHDL-2008 defines OR, AND and XOR reduction operators, analogous to those in Verilog. So, with VHDL-2008 you can just code Result <= or inp; From newsfish@newsfish Thu Aug 1 00:35:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "tuclogicguy" Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Fri, 1 Jan 2016 14:25:37 -0700 Organization: A noiseless patient Spider Lines: 75 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Injection-Date: Fri, 1 Jan 2016 21:22:58 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0e31ff6ed6443f43d4ddd5802d1008e1"; logging-data="28591"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ZG9QIycPOS/Ah+WYjvfnIm4GN2PPWq/E=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6157 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:87pKTm4W5FNqQBxj3BiBSid1aLk= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:4217 wrote in message news:1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com... > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > ENTITY debounce IS > PORT(pb, clock_100Hz : IN STD_LOGIC; > pb_debounced : OUT STD_LOGIC); > END debounce; > ARCHITECTURE a OF debounce IS > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > SIGNAL PREVIOUS : STD_LOGIC; > BEGIN > -- Debounce Button: Filters out mechanical switch bounce for around > 40Ms. > -- Debounce clock should be approximately 10ms > process > begin > wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > SHIFT_PB(3) <= NOT PB; > If SHIFT_PB(3 Downto 0)="0000" THEN > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN > PB_DEBOUNCED <= '1'; > PREVIOUS <= '1'; > ELSE > PB_DEBOUNCED <= PREVIOUS; > End if; > end process; > end a; Well, here is how another professional logic designer would code this circuit: library IEEE; use IEEE.STD_LOGIC_1164.all; ENTITY debounce IS PORT(pb, clock_100Hz : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END ENTITY; ARCHITECTURE a OF debounce IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. -- Debounce clock should be approximately 10ms process begin wait until rising_edge(clock_100Hz); SHIFT_PB <= NOT PB & SHIFT_PB(3 Downto 1); If SHIFT_PB="0000" THEN PB_DEBOUNCED <= '0'; ELSIF SHIFT_PB = "1111" THEN PB_DEBOUNCED <= '1'; End if; end process; END ARCHITECTURE; This circuit doesn't do any arithmetic so you don't need STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED or numeric_std packages. The PREVIOUS signal is superfluous. There is no problem with using a single WAIT statement in a clocked process. I have many multi-million-gate ASICs in the field where much of the logic is coded that way. (Different designers have different preferences/habits.) This circuit doesn't really need a reset. After 4 clock cycles SHIFT_PB will be in whatever state PB is in. PB_DEBOUNCED will be undefined for a few clock cycles until PB settles down; but, so what? Charles Bailey From newsfish@newsfish Thu Aug 1 00:35:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Sat, 2 Jan 2016 00:22:21 -0500 Organization: A noiseless patient Spider Lines: 97 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 2 Jan 2016 05:19:42 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="cfe4bba9dd09999ac03b55be5e1b1734"; logging-data="10671"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18JcVzgbOEafPa+Ut97vkgW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:eXHeTDdDmcvKTnU3hTeYUwTI1n4= Xref: news.eternal-september.org comp.lang.vhdl:4218 On 1/1/2016 4:25 PM, tuclogicguy wrote: > wrote in message > news:1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com... >> library IEEE; >> use IEEE.STD_LOGIC_1164.all; >> use IEEE.STD_LOGIC_ARITH.all; >> use IEEE.STD_LOGIC_UNSIGNED.all; >> ENTITY debounce IS >> PORT(pb, clock_100Hz : IN STD_LOGIC; >> pb_debounced : OUT STD_LOGIC); >> END debounce; >> ARCHITECTURE a OF debounce IS >> SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); >> SIGNAL PREVIOUS : STD_LOGIC; >> BEGIN >> -- Debounce Button: Filters out mechanical switch bounce for around >> 40Ms. >> -- Debounce clock should be approximately 10ms >> process >> begin >> wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); >> SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); >> SHIFT_PB(3) <= NOT PB; >> If SHIFT_PB(3 Downto 0)="0000" THEN >> PB_DEBOUNCED <= '0'; >> PREVIOUS <= '0'; >> ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN >> PB_DEBOUNCED <= '1'; >> PREVIOUS <= '1'; >> ELSE >> PB_DEBOUNCED <= PREVIOUS; >> End if; >> end process; >> end a; > > Well, here is how another professional logic designer would code this > circuit: > library IEEE; > use IEEE.STD_LOGIC_1164.all; > ENTITY debounce IS > PORT(pb, clock_100Hz : IN STD_LOGIC; > pb_debounced : OUT STD_LOGIC); > END ENTITY; > ARCHITECTURE a OF debounce IS > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > BEGIN > -- Debounce Button: Filters out mechanical switch bounce for around > 40Ms. > -- Debounce clock should be approximately 10ms > process > begin > wait until rising_edge(clock_100Hz); > SHIFT_PB <= NOT PB & SHIFT_PB(3 Downto 1); > If SHIFT_PB="0000" THEN > PB_DEBOUNCED <= '0'; > ELSIF SHIFT_PB = "1111" THEN > PB_DEBOUNCED <= '1'; > End if; > end process; > END ARCHITECTURE; > > This circuit doesn't do any arithmetic so you don't need > STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED or numeric_std packages. Yes, if this circuit stands alone, that is true. But it is likely part of a larger circuit. > The PREVIOUS signal is superfluous. > There is no problem with using a single WAIT statement in a clocked > process. I have many multi-million-gate ASICs in the field where much > of the logic is coded that way. (Different designers have different > preferences/habits.) I don't think anyone said coding a wait statement would cause "problems", at least not with the synthesis. But it is harder to code with a reset. The wait statement replaces the sensitivity list and the IF statement. To add a reset you have to include the reset in the sensitivity list and also use an IF, so you are back to the conventional method. So what is the point of using such an unconventional style? Few books promote it and support for it in tools in question since I have never seen it in the vendor's recommended code. > This circuit doesn't really need a reset. After 4 clock cycles SHIFT_PB > will be in whatever state PB is in. PB_DEBOUNCED will be undefined for > a few clock cycles until PB settles down; but, so what? So what is it doing while settling? If it powers up as all 1's when the input is actually at 0 (or the inverse) at the start it may well see an edge that is not there and put following logic into an unexpected state. If nothing else, PB_DEBOUNCED needs to be reset to the appropriate state. -- Rick From newsfish@newsfish Thu Aug 1 00:35:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "tuclogicguy" Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Sat, 2 Jan 2016 08:19:21 -0700 Organization: A noiseless patient Spider Lines: 62 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Injection-Date: Sat, 2 Jan 2016 15:16:38 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0e31ff6ed6443f43d4ddd5802d1008e1"; logging-data="17058"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+nRS5pr80fe9Id0jyzZolmydkjYN6smgU=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6157 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:fNHmUbuYxDzE9dZYqgCMmblkyEk= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:4219 "rickman" wrote in message news:n67mle$adf$1@dont-email.me... >> There is no problem with using a single WAIT statement in a clocked >> process. I have many multi-million-gate ASICs in the field where >> much >> of the logic is coded that way. (Different designers have different >> preferences/habits.) > > I don't think anyone said coding a wait statement would cause > "problems", at least not with the synthesis. But it is harder to code > with a reset. The wait statement replaces the sensitivity list and > the IF statement. To add a reset you have to include the reset in the > sensitivity list and also use an IF, so you are back to the > conventional method. That is true only if you are using an asynchronous reset. I discourage young designers from using asynchronous resets and explain that they should be used only when you need to reset a latch when the clock isn't running. Otherwise, use a synchronous reset. A synchronous reset shouldn't be in the sensitivity list. If you later decide that a latch needs to be reset, just add an "if" statement to the clocked process. There is no need to rewrite how the process is structured. wait until rising_edge(clk); if reset='1' then latch <= '0'; else latch <= next_state; end if; > So what is the point of using such an unconventional style? Few books > promote it and support for it in tools in question since I have never > seen it in the vendor's recommended code. I guess conventional vs. unconventional depends on what you're used to seeing. The "wait until rising_edge(clk)" construct is well-documented as a way of coding an edge-triggered latch. > >> This circuit doesn't really need a reset. After 4 clock cycles >> SHIFT_PB >> will be in whatever state PB is in. PB_DEBOUNCED will be undefined >> for >> a few clock cycles until PB settles down; but, so what? > > So what is it doing while settling? If it powers up as all 1's when > the input is actually at 0 (or the inverse) at the start it may well > see an edge that is not there and put following logic into an > unexpected state. If nothing else, PB_DEBOUNCED needs to be reset to > the appropriate state. And what would the "appropriate state" be? Probably whatever state the input is at currently. Normally, a circuit that is just sitting there continuously sampling an input signal doesn't need to be reset, just let it latch the input continuously. In the case of this switch debouncer, the downstream logic is probably being held reset until things settle down during power-on so there is probably no reason for resetting the debouncer itself. Charles Bailey From newsfish@newsfish Thu Aug 1 00:35:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Sat, 2 Jan 2016 10:59:00 -0500 Organization: A noiseless patient Spider Lines: 79 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 2 Jan 2016 15:56:22 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="cfe4bba9dd09999ac03b55be5e1b1734"; logging-data="25520"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19DVK+QhCzexnwHJ7pironW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:0XF08U2PAi3r+d+hPzk6PsasMFs= Xref: news.eternal-september.org comp.lang.vhdl:4220 On 1/2/2016 10:19 AM, tuclogicguy wrote: > "rickman" wrote in message > news:n67mle$adf$1@dont-email.me... >>> There is no problem with using a single WAIT statement in a clocked >>> process. I have many multi-million-gate ASICs in the field where >>> much >>> of the logic is coded that way. (Different designers have different >>> preferences/habits.) >> >> I don't think anyone said coding a wait statement would cause >> "problems", at least not with the synthesis. But it is harder to code >> with a reset. The wait statement replaces the sensitivity list and >> the IF statement. To add a reset you have to include the reset in the >> sensitivity list and also use an IF, so you are back to the >> conventional method. > That is true only if you are using an asynchronous reset. I discourage > young designers from using asynchronous resets and explain that they > should be used only when you need to reset a latch when the clock isn't > running. Otherwise, use a synchronous reset. A synchronous reset > shouldn't be in the sensitivity list. If you later decide that a latch > needs to be reset, just add an "if" statement to the clocked process. > There is no need to rewrite how the process is structured. > wait until rising_edge(clk); > if reset='1' then > latch <= '0'; > else > latch <= next_state; > end if; I think that is bad advice. Rather than encourage a blanket reset that wastes resources in inefficient ways, I think users should learn to use the built in async reset in FPGAs properly. In some critical applications an async reset is required since the clock may not be running and a failsafe is needed to shutdown outputs in all cases. I only use a sync reset when it is needed to assure proper startup at the end of the async reset. >> So what is the point of using such an unconventional style? Few books >> promote it and support for it in tools in question since I have never >> seen it in the vendor's recommended code. > I guess conventional vs. unconventional depends on what you're used to > seeing. > The "wait until rising_edge(clk)" construct is well-documented as a way > of coding an edge-triggered latch. Obviously we can argue this all day, but I have not seen a register described using a wait statement in a single book on VHDL. Not once in 20 years. How many books show this method? >>> This circuit doesn't really need a reset. After 4 clock cycles >>> SHIFT_PB >>> will be in whatever state PB is in. PB_DEBOUNCED will be undefined >>> for >>> a few clock cycles until PB settles down; but, so what? >> >> So what is it doing while settling? If it powers up as all 1's when >> the input is actually at 0 (or the inverse) at the start it may well >> see an edge that is not there and put following logic into an >> unexpected state. If nothing else, PB_DEBOUNCED needs to be reset to >> the appropriate state. > And what would the "appropriate state" be? Probably whatever state the > input is at currently. Normally, a circuit that is just sitting there > continuously sampling an input signal doesn't need to be reset, just let > it latch the input continuously. > In the case of this switch debouncer, the downstream logic is probably > being held reset until things settle down during power-on so there is > probably no reason for resetting the debouncer itself. "Probably"??? The appropriate state for PB_DEBOUNCED depends on how it is used in the design. If the quiescent state is a 1 then default it to a 1. -- Rick From newsfish@newsfish Thu Aug 1 00:35:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "tuclogicguy" Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Sat, 2 Jan 2016 18:59:46 -0700 Organization: A noiseless patient Spider Lines: 133 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Injection-Date: Sun, 3 Jan 2016 02:08:35 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0e31ff6ed6443f43d4ddd5802d1008e1"; logging-data="28067"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+LKsr/ohZ4VN8KaLJrf5ETNovfNc7CQ5c=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6157 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:edE6g04hDn2dJ0pewJBzTa9jNUU= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:4221 "rickman" wrote in message news:n68rv6$otg$1@dont-email.me... > On 1/2/2016 10:19 AM, tuclogicguy wrote: >> "rickman" wrote in message >> news:n67mle$adf$1@dont-email.me... >>>> There is no problem with using a single WAIT statement in a clocked >>>> process. I have many multi-million-gate ASICs in the field where >>>> much >>>> of the logic is coded that way. (Different designers have >>>> different >>>> preferences/habits.) >>> >>> I don't think anyone said coding a wait statement would cause >>> "problems", at least not with the synthesis. But it is harder to >>> code >>> with a reset. The wait statement replaces the sensitivity list and >>> the IF statement. To add a reset you have to include the reset in >>> the >>> sensitivity list and also use an IF, so you are back to the >>> conventional method. >> That is true only if you are using an asynchronous reset. I >> discourage >> young designers from using asynchronous resets and explain that they >> should be used only when you need to reset a latch when the clock >> isn't >> running. Otherwise, use a synchronous reset. A synchronous reset >> shouldn't be in the sensitivity list. If you later decide that a >> latch >> needs to be reset, just add an "if" statement to the clocked process. >> There is no need to rewrite how the process is structured. >> wait until rising_edge(clk); >> if reset='1' then >> latch <= '0'; >> else >> latch <= next_state; >> end if; > > I think that is bad advice. Rather than encourage a blanket reset > that wastes resources in inefficient ways, I think users should learn > to use the built in async reset in FPGAs properly. In some critical > applications an async reset is required since the clock may not be > running and a failsafe is needed to shutdown outputs in all cases. > > I only use a sync reset when it is needed to assure proper startup at > the end of the async reset. The last FPGA I worked on was a Xilinx Virtex-4. In the Virtex-4 user's guide there is a fairly lengthy section that discusses synchronous vs. asynchronous resets. They strongly recommend the use of synchronous resets wherever possible and go on the explain how synchronous resets use fewer FPGA resources. I work mainly with IBM ASICs (now owned by Global Foundaries). I know for a fact, because I deal with it everyday, that asynchronous resets cause extra complications in timing analysis that don't exist with synchronous resets. Also, the use of asynchronous resets causes the netlist processing tools to insert additional test logic cells that aren't required with synchronous resets. >>> So what is the point of using such an unconventional style? Few >>> books >>> promote it and support for it in tools in question since I have >>> never >>> seen it in the vendor's recommended code. >> I guess conventional vs. unconventional depends on what you're used >> to >> seeing. >> The "wait until rising_edge(clk)" construct is well-documented as a >> way >> of coding an edge-triggered latch. > > Obviously we can argue this all day, but I have not seen a register > described using a wait statement in a single book on VHDL. Not once > in 20 years. How many books show this method? Lots. Here are a few: In "The Designer's Guide to VHDL", by Peter J. Ashenden, page 608 (in my edition), Figure A-1 "Four equivalent models of an edge-triggered D-flipflop", the wait until rising _edge(clk); construct is the 2nd one listed. Also, back on page 112 of the same book, where the author presents a model for an edge-triggered flip-flop with asynchronous clear, he includes this comment: "If the flipflop did not have the asynchronous clear input, the model could have used a simple wait statement such as wait until clk='1'; to trigger on a rising edge." In "Application-Specific Integrated Circuits", by Michael John Sebastian Smith, in Chapter 10 VHDL, page 380, the first example given is of a counter. The author uses a wait until (Clock = '0'); construct. Then the author goes into the details of the VHDL language and on page 422, where he describes the VHDL wait statement he says: "The most common use of the wait statement is to describe synchronous logic, as in the following model of a D flip-flop: entity DFF is port (CLK, D : BIT; Q : out BIT); end; architecture Behave of DFF is process begin wait until Clk = '1'; Q <= D; end process; end; " Then in section 12.6 VHDL and Logic Synthesis, sub-section 12.6.6 Sequential Logic in VHDL, page 597, it says: "Sensitivity to an edge implies sequential logic in VHDL. A synthesis tool can locate edges in VHDL by finding a process statement that has either: * no sensitivity list with a "wait until" statement * a sensitivity list and test for " 'EVENT " plus a specific level " In the user's guide for IBM BooleDozer, a logic synthesis tool I used for many years and still use for some purposes, it describes different ways that latches (flip-flops) can be inferred by the tool and the "wait until clk='1';" construct is one of ways listed. In "HDL Chip Design", by Douglas J. Smith, on page 172, under the heading "VHDL flip-flop inference", the author gives 4 examples: Wait until (Clock'event and Clock = '1'); if (Clock'event and Clock = '0') then wait until rising_edge(Clock); if falling_edge(Clock) then Charles Bailey From newsfish@newsfish Thu Aug 1 00:35:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Sun, 3 Jan 2016 03:20:40 -0500 Organization: A noiseless patient Spider Lines: 149 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 3 Jan 2016 08:18:01 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9a7e85257bc6d0d7dd5dafae4959c4b0"; logging-data="8735"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/cFUI777mhYWwh2XazndI+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:zh3fle7YR7MZ9nhI4UU22FSXmj4= Xref: news.eternal-september.org comp.lang.vhdl:4222 On 1/2/2016 8:59 PM, tuclogicguy wrote: > "rickman" wrote in message > news:n68rv6$otg$1@dont-email.me... >> On 1/2/2016 10:19 AM, tuclogicguy wrote: >>> "rickman" wrote in message >>> news:n67mle$adf$1@dont-email.me... >>>>> There is no problem with using a single WAIT statement in a clocked >>>>> process. I have many multi-million-gate ASICs in the field where >>>>> much >>>>> of the logic is coded that way. (Different designers have >>>>> different >>>>> preferences/habits.) >>>> >>>> I don't think anyone said coding a wait statement would cause >>>> "problems", at least not with the synthesis. But it is harder to >>>> code >>>> with a reset. The wait statement replaces the sensitivity list and >>>> the IF statement. To add a reset you have to include the reset in >>>> the >>>> sensitivity list and also use an IF, so you are back to the >>>> conventional method. >>> That is true only if you are using an asynchronous reset. I >>> discourage >>> young designers from using asynchronous resets and explain that they >>> should be used only when you need to reset a latch when the clock >>> isn't >>> running. Otherwise, use a synchronous reset. A synchronous reset >>> shouldn't be in the sensitivity list. If you later decide that a >>> latch >>> needs to be reset, just add an "if" statement to the clocked process. >>> There is no need to rewrite how the process is structured. >>> wait until rising_edge(clk); >>> if reset='1' then >>> latch <= '0'; >>> else >>> latch <= next_state; >>> end if; >> >> I think that is bad advice. Rather than encourage a blanket reset >> that wastes resources in inefficient ways, I think users should learn >> to use the built in async reset in FPGAs properly. In some critical >> applications an async reset is required since the clock may not be >> running and a failsafe is needed to shutdown outputs in all cases. >> >> I only use a sync reset when it is needed to assure proper startup at >> the end of the async reset. > The last FPGA I worked on was a Xilinx Virtex-4. In the Virtex-4 user's > guide there is a fairly lengthy section that discusses synchronous vs. > asynchronous resets. They strongly recommend the use of synchronous > resets wherever possible and go on the explain how synchronous resets > use fewer FPGA resources. The chip wide global reset has a dedicated route in every Xilinx chip I have ever worked with, not that this is all of them. A common reset across the design is typically implemented using this global reset. If you don't use an async reset, this resource is wasted. So clearly the synchronous reset would use more resources. > I work mainly with IBM ASICs (now owned by Global Foundaries). I know > for a fact, because I deal with it everyday, that asynchronous resets > cause extra complications in timing analysis that don't exist with > synchronous resets. Also, the use of asynchronous resets causes the > netlist processing tools to insert additional test logic cells that > aren't required with synchronous resets. My comments were aimed at FPGA usage. >>>> So what is the point of using such an unconventional style? Few >>>> books >>>> promote it and support for it in tools in question since I have >>>> never >>>> seen it in the vendor's recommended code. >>> I guess conventional vs. unconventional depends on what you're used >>> to >>> seeing. >>> The "wait until rising_edge(clk)" construct is well-documented as a >>> way >>> of coding an edge-triggered latch. >> >> Obviously we can argue this all day, but I have not seen a register >> described using a wait statement in a single book on VHDL. Not once >> in 20 years. How many books show this method? > > Lots. Here are a few: > In "The Designer's Guide to VHDL", by Peter J. Ashenden, page 608 (in my > edition), Figure A-1 "Four equivalent models of an edge-triggered > D-flipflop", the > wait until rising _edge(clk); > construct is the 2nd one listed. I think I have that one, I'll check when I get home. Even if it is mentioned on one page, what does he show in all the actual examples of registered logic through the book? > Also, back on page 112 of the same book, where the author presents a > model for an edge-triggered flip-flop with asynchronous clear, he > includes this comment: > "If the flipflop did not have the asynchronous clear input, the model > could have used a simple wait statement such as > wait until clk='1'; > to trigger on a rising edge." > > In "Application-Specific Integrated Circuits", by Michael John Sebastian > Smith, in Chapter 10 VHDL, page 380, the first example given is of a > counter. The author uses a > wait until (Clock = '0'); > construct. > > Then the author goes into the details of the VHDL language and on page > 422, where he describes the VHDL wait statement he says: > "The most common use of the wait statement is to describe synchronous > logic, as in the following model of a D flip-flop: > entity DFF is port (CLK, D : BIT; Q : out BIT); end; > architecture Behave of DFF is > process begin wait until Clk = '1'; Q <= D; end process; > end; > " > > Then in section 12.6 VHDL and Logic Synthesis, sub-section 12.6.6 > Sequential Logic in VHDL, page 597, it says: > "Sensitivity to an edge implies sequential logic in VHDL. A synthesis > tool can locate edges in VHDL by finding a process statement that has > either: > * no sensitivity list with a "wait until" statement > * a sensitivity list and test for " 'EVENT " plus a specific level > " > > In the user's guide for IBM BooleDozer, a logic synthesis tool I used > for many years and still use for some purposes, it describes different > ways that latches (flip-flops) can be inferred by the tool and the "wait > until clk='1';" construct is one of ways listed. > > > In "HDL Chip Design", by Douglas J. Smith, on page 172, under the > heading "VHDL flip-flop inference", the author gives 4 examples: > Wait until (Clock'event and Clock = '1'); > if (Clock'event and Clock = '0') then > wait until rising_edge(Clock); > if falling_edge(Clock) then Ok, so it is included in books for completeness. Do you see any books where it is used consistently through the book in most examples? -- Rick From newsfish@newsfish Thu Aug 1 00:35:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Newsgroups: comp.lang.vhdl References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 03 Jan 2016 14:09:00 GMT Lines: 72 Message-ID: <56892b7b$0$11115$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 4b339f94.news.astraweb.com X-Trace: DXC=d=:P`ga?9k96k]7j^a\l<5L?0kYOcDh@:W\:Hm@YlDb: On 1/2/2016 8:59 PM, tuclogicguy wrote: >> "rickman" wrote in message >> news:n68rv6$otg$1@dont-email.me... >>> On 1/2/2016 10:19 AM, tuclogicguy wrote: >>>> "rickman" wrote in message >>>> news:n67mle$adf$1@dont-email.me... >>>>>> There is no problem with using a single WAIT statement in a clocked >>>>>> process. I have many multi-million-gate ASICs in the field where >>>>>> much of the logic is coded that way. (Different designers have >>>>>> different preferences/habits.) >>>>> >>>>> I don't think anyone said coding a wait statement would cause >>>>> "problems", at least not with the synthesis. But it is harder to >>>>> code with a reset. The wait statement replaces the sensitivity list >>>>> and the IF statement. To add a reset you have to include the reset >>>>> in the sensitivity list and also use an IF, so you are back to the >>>>> conventional method. >>>> That is true only if you are using an asynchronous reset. I >>>> discourage young designers from using asynchronous resets and explain >>>> that they should be used only when you need to reset a latch when the >>>> clock isn't running. Otherwise, use a synchronous reset. A >>>> synchronous reset shouldn't be in the sensitivity list. If you later >>>> decide that a latch needs to be reset, just add an "if" statement to >>>> the clocked process. >>>> There is no need to rewrite how the process is structured. >>>> wait until rising_edge(clk); >>>> if reset='1' then >>>> latch <= '0'; >>>> else >>>> latch <= next_state; >>>> end if; >>> >>> I think that is bad advice. Rather than encourage a blanket reset >>> that wastes resources in inefficient ways, I think users should learn >>> to use the built in async reset in FPGAs properly. In some critical >>> applications an async reset is required since the clock may not be >>> running and a failsafe is needed to shutdown outputs in all cases. >>> >>> I only use a sync reset when it is needed to assure proper startup at >>> the end of the async reset. >> The last FPGA I worked on was a Xilinx Virtex-4. In the Virtex-4 >> user's guide there is a fairly lengthy section that discusses >> synchronous vs. asynchronous resets. They strongly recommend the use >> of synchronous resets wherever possible and go on the explain how >> synchronous resets use fewer FPGA resources. > > The chip wide global reset has a dedicated route in every Xilinx chip I > have ever worked with, not that this is all of them. A common reset > across the design is typically implemented using this global reset. If > you don't use an async reset, this resource is wasted. So clearly the > synchronous reset would use more resources. Lurkers might be interested in reading Xilinx WP272. "... applying a global reset to your FPGA designs is not a very good idea and should be avoided" This came in with (I think) Virtex 4. In design guides for earlier families (e.g. up to Virtex 2 Pro) use of the global reset was recommended. http://www.xilinx.com/support/documentation/white_papers/wp272.pdf There is also an XCELL article called "How do I reset my FPGA?" that is worth reading. Regards, Allan From newsfish@newsfish Thu Aug 1 00:35:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Sun, 3 Jan 2016 12:27:09 -0500 Organization: A noiseless patient Spider Lines: 102 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> <56892b7b$0$11115$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 3 Jan 2016 17:24:29 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9ffa99eda9a1c51ff7a262ff9deed1fa"; logging-data="19342"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19kFuuXHjvg2I97s2B90tQX" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: <56892b7b$0$11115$c3e8da3@news.astraweb.com> Cancel-Lock: sha1:D2vz0GT3bZXYqsybBRouQ8Otmtw= Xref: news.eternal-september.org comp.lang.vhdl:4224 On 1/3/2016 9:09 AM, Allan Herriman wrote: > On Sun, 03 Jan 2016 03:20:40 -0500, rickman wrote: > >> On 1/2/2016 8:59 PM, tuclogicguy wrote: >>> "rickman" wrote in message >>> news:n68rv6$otg$1@dont-email.me... >>>> On 1/2/2016 10:19 AM, tuclogicguy wrote: >>>>> "rickman" wrote in message >>>>> news:n67mle$adf$1@dont-email.me... >>>>>>> There is no problem with using a single WAIT statement in a clocked >>>>>>> process. I have many multi-million-gate ASICs in the field where >>>>>>> much of the logic is coded that way. (Different designers have >>>>>>> different preferences/habits.) >>>>>> >>>>>> I don't think anyone said coding a wait statement would cause >>>>>> "problems", at least not with the synthesis. But it is harder to >>>>>> code with a reset. The wait statement replaces the sensitivity list >>>>>> and the IF statement. To add a reset you have to include the reset >>>>>> in the sensitivity list and also use an IF, so you are back to the >>>>>> conventional method. >>>>> That is true only if you are using an asynchronous reset. I >>>>> discourage young designers from using asynchronous resets and explain >>>>> that they should be used only when you need to reset a latch when the >>>>> clock isn't running. Otherwise, use a synchronous reset. A >>>>> synchronous reset shouldn't be in the sensitivity list. If you later >>>>> decide that a latch needs to be reset, just add an "if" statement to >>>>> the clocked process. >>>>> There is no need to rewrite how the process is structured. >>>>> wait until rising_edge(clk); >>>>> if reset='1' then >>>>> latch <= '0'; >>>>> else >>>>> latch <= next_state; >>>>> end if; >>>> >>>> I think that is bad advice. Rather than encourage a blanket reset >>>> that wastes resources in inefficient ways, I think users should learn >>>> to use the built in async reset in FPGAs properly. In some critical >>>> applications an async reset is required since the clock may not be >>>> running and a failsafe is needed to shutdown outputs in all cases. >>>> >>>> I only use a sync reset when it is needed to assure proper startup at >>>> the end of the async reset. >>> The last FPGA I worked on was a Xilinx Virtex-4. In the Virtex-4 >>> user's guide there is a fairly lengthy section that discusses >>> synchronous vs. asynchronous resets. They strongly recommend the use >>> of synchronous resets wherever possible and go on the explain how >>> synchronous resets use fewer FPGA resources. >> >> The chip wide global reset has a dedicated route in every Xilinx chip I >> have ever worked with, not that this is all of them. A common reset >> across the design is typically implemented using this global reset. If >> you don't use an async reset, this resource is wasted. So clearly the >> synchronous reset would use more resources. > > > Lurkers might be interested in reading Xilinx WP272. > > "... applying a global reset to your FPGA designs is not a very good > idea and should be avoided" > > This came in with (I think) Virtex 4. In design guides for earlier > families (e.g. up to Virtex 2 Pro) use of the global reset was > recommended. > > > http://www.xilinx.com/support/documentation/white_papers/wp272.pdf > > There is also an XCELL article called "How do I reset my FPGA?" that is > worth reading. Apples and Oranges. Xilinx is saying adding yet another global async reset is a bad idea. App note 272 says, When a Xilinx FPGA is configured or reconfigured, every cell is initialized (Figure 6). This is the ultimate in master reset because it covers far more than simple flip-flops. Configuration has the same effect as a global reset, but it also initializes all RAM cells. So clearly they are advocating the use of the built in Global Set/Reset (GSR) which is activated at the end of configuration and can also be activated by an external signal is desired. This is what I recommend along with appropriate logic to make sure the async timing of the end of GSR results in FSMs, counters, etc. starting up properly. The Xilins app note shows this under the heading, "Strategy for the 0.01% of Cases". The Xilinx paper goes on to explain the waste of resources when a global reset is constructed from the fabric which includes both an async or sync reset. The app note falls short though by not giving example code for using the global reset to initialize logic, but instead indicating this is somehow "automatic". "There is no requirement to insert a reset for simulation because nothing will be undefined." This is not true unless you code it in or the simulator defaults to initial values ('0', '1') like your chip, which I"m pretty sure none do. I suppose a post layout simulation might do that, but not a pre-systhesis simulation. -- Rick From newsfish@newsfish Thu Aug 1 00:35:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: What is the point of delimiters? Date: Sun, 3 Jan 2016 23:35:08 +0200 Organization: A noiseless patient Spider Lines: 1 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 3 Jan 2016 21:32:34 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="13206"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+nmV+rBZNqdaWCBRQimxylAkQ5//JehhI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:v+H6VaqdPTRQOMn1l6f+CVP9N0s= Xref: news.eternal-september.org comp.lang.vhdl:4225 Why, for instance, dot . is a delimiter but hat ^ is not? From newsfish@newsfish Thu Aug 1 00:35:53 2024 X-Received: by 10.66.160.3 with SMTP id xg3mr76290329pab.35.1451905038862; Mon, 04 Jan 2016 02:57:18 -0800 (PST) X-Received: by 10.50.57.100 with SMTP id h4mr1261368igq.6.1451905038830; Mon, 04 Jan 2016 02:57:18 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no25565325igc.0!news-out.google.com!l1ni3273igd.0!nntp.google.com!mv3no25565316igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Jan 2016 02:57:18 -0800 (PST) In-Reply-To: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6212ad24-cd01-4718-8f0f-7e0971a592eb@googlegroups.com> Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) From: Thomas Stanka Injection-Date: Mon, 04 Jan 2016 10:57:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4226 Am Donnerstag, 17. Dezember 2015 21:29:27 UTC+1 schrieb disturb...@gmail.co= m: > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); Declare this signal as a state and draw a complete bubble diagram for the c= ode below. Eg (SHIFT_PB=3D"0000") with PB=3D1 go to (SHIFT_PB=3D1000) else = stay in that state.=20 Show your professor that buble diagram and tell him, the code itself is alr= eady a FSM, just not the best FSM for debouncing, but this is neither your = fault, nor does he explicite ask you to write a better state machine for de= bouncing, as it is not clear, if there is a reason for having the output hi= gh for an additional clock cycle when the output and he writes "seems to b= e at least sicteen=20 states".=20 Else I agree with Rickman. If you want a ++ mark draw a similar diagram with combination of PBDEBOUNCE= D, PREVIOUS and SHIFT_PB to show your prof that there are theoretically sta= tes that lead to different behavior but are not reachable e.g. (PB_SHIFT=3D= 1100 & PBDEBOUNCED=3D0 & PREVIOUS=3D1) would lead to an different output as= the minimal FSM, but there is no explicite path to this state or similar s= tates. A minimal FSM will deal with 16 states and on the bubble diagram lev= el it is irrelevant if output is delayed by one clock cycle or not. regards Thomas From newsfish@newsfish Thu Aug 1 00:35:54 2024 X-Received: by 10.66.141.102 with SMTP id rn6mr79986288pab.26.1451925077500; Mon, 04 Jan 2016 08:31:17 -0800 (PST) X-Received: by 10.50.61.132 with SMTP id p4mr1041128igr.10.1451925077417; Mon, 04 Jan 2016 08:31:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!weretis.net!feeder6.news.weretis.net!news.glorb.com!mv3no25689259igc.0!news-out.google.com!f6ni43372igq.0!nntp.google.com!mv3no25689252igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Jan 2016 08:31:17 -0800 (PST) In-Reply-To: <9151fs$8o1$1@kermit.esat.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.232.129.34; posting-account=0ESrfgoAAAAERS5Ih2LvEFl1I5btxL51 NNTP-Posting-Host: 103.232.129.34 References: <9151fs$8o1$1@kermit.esat.net> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: 8B/10B encoder From: ravalitngp@gmail.com Injection-Date: Mon, 04 Jan 2016 16:31:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4227 hi sir..... iam trying to understand the lookup table for 8b/10b encoder..but its not getting to how the values are come for rd- and rd+. i have a doubt on lookup tables on 8b/10b encoder..please give me clear explanation of 8b/10b encoder and how its come 6b and 4b in table... is there any concept of getting 6b and 4b in encoder(rd- and rd+). From newsfish@newsfish Thu Aug 1 00:35:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: 8B/10B encoder Date: Mon, 4 Jan 2016 12:41:43 -0500 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <9151fs$8o1$1@kermit.esat.net> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 4 Jan 2016 17:39:02 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="13627"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/44HRm1sS51R9jRHrBNxgb" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:nBuakBV1FdAdyUEFQrDOhn6YO8w= Xref: news.eternal-september.org comp.lang.vhdl:4228 On 1/4/2016 11:31 AM, ravalitngp@gmail.com wrote: > hi sir..... > iam trying to understand the lookup table for 8b/10b encoder..but its not getting to how the values are come for rd- and rd+. > i have a doubt on lookup tables on 8b/10b encoder..please give me clear explanation of 8b/10b encoder and how its come 6b and 4b in table... > is there any concept of getting 6b and 4b in encoder(rd- and rd+). Wikipedia seems to explain this pretty well. https://en.wikipedia.org/wiki/8b/10b_encoding#How_it_works_for_the_IBM_code It appears that the 8b/10b code is actually done by concatenating a pair of codes, 5b/6b and 3b/4b. Read the wiki page and come back with any questions you have on it. I have a question for you. Are rd+ and rd- differential signals or two separate signals from your hardware? Do you know what the waveforms look like on these signals? -- Rick From newsfish@newsfish Thu Aug 1 00:35:54 2024 X-Received: by 10.182.128.72 with SMTP id nm8mr81366040obb.36.1451936125256; Mon, 04 Jan 2016 11:35:25 -0800 (PST) X-Received: by 10.50.225.101 with SMTP id rj5mr3086igc.3.1451936125210; Mon, 04 Jan 2016 11:35:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no25764421igc.0!news-out.google.com!f6ni43484igq.0!nntp.google.com!mv3no18092276igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Jan 2016 11:35:24 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) From: Andy Injection-Date: Mon, 04 Jan 2016 19:35:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4229 IEEE STD 1076.6-2004 (IEEE STANDARD FOR VHDL REGISTER TRANSFER LEVEL SYNTHESIS), Section 6.1.2 Clock Edge Specification, requires both a level and an event part for the clock specification. Thus either clock'event or not clock'stable is required. Many synthesis tools may support non-standard clock edge specifitions with no event part, but such descriptions are not portable and certainly should not be recommended. Note that the IEEE standard rising_edge() and falling_edge() functions include both level and edge conditions, as well as strength stripping and verification of the previous value before the event and the value after (at) the event. Wait statements, with appropriate expressions, are allowed by the standard. However, they tend to be less handy when asynchronous resets are used/required. Also, an asynchronously reset register can be inferred from a concurrent assignment (again, in the standard): q <= '0' when reset = '1' else d when rising_edge(clock); It is not nearly as clean if you want a synchronously reset register... Almost all of our projects require initialized outputs even without a clock. Andy From newsfish@newsfish Thu Aug 1 00:35:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Mon, 4 Jan 2016 15:01:27 -0500 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 4 Jan 2016 19:58:46 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9ffa99eda9a1c51ff7a262ff9deed1fa"; logging-data="16506"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/GGDBqp8e7yFKkoyyxHMOx" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:4PwU+UlUIRl24KXgafaXSHTmp7E= Xref: news.eternal-september.org comp.lang.vhdl:4230 On 1/4/2016 2:35 PM, Andy wrote: > > IEEE STD 1076.6-2004 (IEEE STANDARD FOR VHDL REGISTER TRANSFER LEVEL > SYNTHESIS), Section 6.1.2 Clock Edge Specification, requires both a > level and an event part for the clock specification. Thus either > clock'event or not clock'stable is required. In a process the clock will be in the sensitivity list. So technically, doesn't that imply an event any time the process runs? -- Rick From newsfish@newsfish Thu Aug 1 00:35:55 2024 X-Received: by 10.50.57.114 with SMTP id h18mr980289igq.12.1451949413524; Mon, 04 Jan 2016 15:16:53 -0800 (PST) X-Received: by 10.50.36.3 with SMTP id m3mr25083igj.0.1451949413509; Mon, 04 Jan 2016 15:16:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no25849964igc.0!news-out.google.com!f6ni43623igq.0!nntp.google.com!mv3no25849959igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Jan 2016 15:16:52 -0800 (PST) In-Reply-To: <88321b8a-514d-4c41-b1c7-b9ef6b411e37@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> <88321b8a-514d-4c41-b1c7-b9ef6b411e37@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f4c4790-0b8c-4510-879d-242387221552@googlegroups.com> Subject: Re: creating program From: Lars Asplund Injection-Date: Mon, 04 Jan 2016 23:16:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4231 Hi Andy, I've probably been a bit careless with the word "system" as well. What I'm = trying to say is that unit testing and higher level testing with integratio= n focus is an effective way of developing your code *before* hitting the sy= nthesis button, i.e. the scope described in Jim's paper. *After* you hit that button, assuming HW is available, you will need additi= onal testing and I agree that you won't see the true nature of your PL unti= l it has been integrated into the complete system, tested over full operati= ng conditions and so on but that doesn't take away the value of getting to = this point efficiently. To me there's also a difference between the full functional testing done at= higher levels and that done at the unit level. The PL units that were hard= to test from the PL boundary will be even harder to test at the higher lev= els when additional HW and SW is involved. Due to the sheer amount of PL, S= W and HW units in a larger system it would also be unmanageable to expose t= hem all at every level of testing, it's just too much details. For example,= if you let system testing focus on verifying system functions you will han= dle this and also make sure that the decomposition of system functionality = into unit functionality was done correctly. Unit functionality will be test= ed indirectly of course but if the unit details aren't exposed to system te= sting there may be corner cases only visible to and verified by the unit te= sts. Both types of testing add unique values. Your point that there are other activities than test to get valuable feedba= ck on your design is important and often forgotten. Especially reviews whic= h have been shown to be an important ingredient in quality work. The goal t= o simplify, automate and shorten the feedback loop applies to these activit= ies as well and unit testing plays a role in doing so. Here are some ways t= o improve on code reviews * You can let a lint tool check some of your coding guidelines rather than = having that manually reviewed. * If you review code and unit tests at the same time the reviewers won't wa= ste their time trying to figure out if the code works at all. The reviewer = can also learn a lot by looking at what was tested and how it was tested. F= or example, if he/she expects some functionality but there are no test case= s for that it means that the functionality is missing or it's not properly = verified. * If you set up a formal code review meeting you have to find a time that f= its everyone so the feedback cycle can be long. Since most of the work is d= one by the reviewers before the meeting you can shorten that time with a to= ol that allows everyone to review and comment code inline and submit when d= one. * Live reviewing through pair programming will make the feedback loop much = shorter. To what extent pair programming is cost efficient is often debated= but my personal view is that it should be used when *you* feel that you're= about to take on a tricky piece of code and could use another pair of eyes= . In the end someone else should review your code, one way or the other.=20 * Self-reviews also provide fast feedback and should always be done. The ac= t of writing unit tests helps you with that. It helps you take a step back = and think critically about your code. I would say that I find/avoid at leas= t as many flaws writing the unit tests as I do running them. So self-review= s are in a way more powerful than unit testing but here is an interesting q= uestion. Would you be as rigorous about self-reviewing if you didn't have a= precise method "forcing" you into it? Even when all your test cases pass y= ou should have another look. It works, but can I make it work more efficien= t, can I make the code more readable, is code coverage sufficient and so on= . When you have a set of fast and working unit tests the fear of changing s= omething that works is much reduced. Reviews are powerful but a problem is that we tend to be lazy. "There's no = need to review this small change or run the slow top-level simulations beca= use it's not going to affect anything other than what I was trying to fix. = I'm just going to build a new FPGA and release it.". Running a selected set= of fast regression unit tests in a background thread is an effortless way = of stopping you when you're wrong. The benefits of loose coupling and high cohesion I was thinking about are t= hose associated with the source code. Better readability, maintainability, = and also significantly lower bug rates. The fact that the tools may destroy= that modularity when optimizing is actually good because it means, to some= extent, that I can meet my constraints while still enjoying the benefits o= f modular code. The alternative would be to write optimized code, destroy t= he code modularity and lose the benefits. /Lars From newsfish@newsfish Thu Aug 1 00:35:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Tue, 5 Jan 2016 14:20:03 +0200 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Jan 2016 12:17:24 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4eaed61cc34cf27306084f6070dcb276"; logging-data="31308"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/zjwOJKqodX/NhiJTniLxG2Qqoexj/jp0=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:Sk79YWJ9khDsrlGDMGzYSG8iJIY= Xref: news.eternal-september.org comp.lang.vhdl:4232 > I don't think you understand VHDL. VHDL has sequential code, that is > what a process it. I prefer to think that VHDL processes do not affect each other while executing. The process is affected by others only when goes sleeping. http://www.sigasi.com/content/vhdls-crown-jewel > Huh??? I use single stepping with VHDL at times. Normally it isn't > that useful because there is so much parallelism, things tend to jump > around as one process stops and another starts... same as software on a > processor with interrupts or multitasking. You do not have interrupts in VHDL. There is no preemption. VHDL is a graceful, "cooperative" multitasking. From newsfish@newsfish Thu Aug 1 00:35:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Tue, 5 Jan 2016 14:29:00 +0200 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Jan 2016 12:26:21 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4eaed61cc34cf27306084f6070dcb276"; logging-data="1408"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18wiJb1+7xd6MBXV3LL3LgDHB0wkbej5IY=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Cancel-Lock: sha1:YDsoR2+4nP75VXMypJKyhYbUO4k= Xref: news.eternal-september.org comp.lang.vhdl:4233 > That's also getting more common in software these days. Ever tried debugging > a 1M messages / second Akka application ? Thanks. Now, nobody can say that VHDL program is a program after you pointed this out. Indeed, if VHDL program is indistinguishable from a modern (Akka) application, they cannot be called a program. BTW, how do you call a piece of Akka code? Why Akka code is not a "description"? There was no reason to resort to this killer argument. Because VHDL is executable "description", it clearly cannot be a program. Being executable and "program" are mutually exclusive, even disjoint things, especially if you execute a description. From newsfish@newsfish Thu Aug 1 00:35:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Nicholas Collin Paul de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Tue, 5 Jan 2016 17:27:12 +0100 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Injection-Info: mx02.eternal-september.org; posting-host="1b4315c307f3cc5ba77928d0bb2ed33c"; logging-data="23792"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19DcsE8MaMunN0ctt3/pP3MYLQl1+bkOoXwZaTZNf91WA==" User-Agent: Alpine 2.11 (DEB 23 2013-08-11) In-Reply-To: Cancel-Lock: sha1:K3m/TV0H68RFLaV41FK16Ykci9E= X-X-Sender: gloucester@Lydia.insomnia247.nl Xref: news.eternal-september.org comp.lang.vhdl:4234 On January 5th, 2016, Valtih1978 claimed: |---------------------------------------------| |"[. . .] | | | |[. . .] | |[. . .] Being executable | |and "program" are mutually exclusive, [. . .]| |[. . .]" | |---------------------------------------------| False. Truly, Paul Colin Gloster From newsfish@newsfish Thu Aug 1 00:35:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Tue, 5 Jan 2016 11:46:49 -0500 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Jan 2016 16:44:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9ffa99eda9a1c51ff7a262ff9deed1fa"; logging-data="28520"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+NlLgV1SBFUfQLmfzYhTHt" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:fiEH3qDPilZlJU5F9AjnjMDWu2U= Xref: news.eternal-september.org comp.lang.vhdl:4235 On 1/5/2016 7:20 AM, valtih1978 wrote: > >> I don't think you understand VHDL. VHDL has sequential code, that is >> what a process it. > > I prefer to think that VHDL processes do not affect each other while > executing. The process is affected by others only when goes sleeping. > http://www.sigasi.com/content/vhdls-crown-jewel > > >> Huh??? I use single stepping with VHDL at times. Normally it isn't >> that useful because there is so much parallelism, things tend to jump >> around as one process stops and another starts... same as software on a >> processor with interrupts or multitasking. > > You do not have interrupts in VHDL. There is no preemption. VHDL is a > graceful, "cooperative" multitasking. Uh, interrupts are about a single processor shared between multiple tasks. VHDL allows you to describe multiple hardware "execution units" which all operate in parallel. If you want a single execution unit shared between tasks you can describe that too - complete with interrupts. Your choice. What I was describing is the behavior of of the simulator which essentially *is* a single processor shared between VHDL tasks. No, it doesn't have interrupts, but the task switching is very messy to try to follow while single stepping. -- Rick From newsfish@newsfish Thu Aug 1 00:35:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Nicholas Collin Paul de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Tue, 5 Jan 2016 17:47:07 +0100 Organization: A noiseless patient Spider Lines: 58 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Injection-Info: mx02.eternal-september.org; posting-host="1b4315c307f3cc5ba77928d0bb2ed33c"; logging-data="28657"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/LIRJteV7PTzCI2T0mlVcNO/StPwWkD2s2KUPrLGLQCQ==" User-Agent: Alpine 2.11 (DEB 23 2013-08-11) In-Reply-To: Cancel-Lock: sha1:GFAEWT+R8IsRK8t2Wg4j4qbJ7Ls= X-X-Sender: gloucester@Lydia.insomnia247.nl Xref: news.eternal-september.org comp.lang.vhdl:4236 On January 5th, 2016, Valtih1978 sent: |-------------------------------------------------------------------------| |"[. . .] | | | |> I don't think you understand VHDL. VHDL has sequential code, that is | |> what a process it. | | | |I prefer" | |-------------------------------------------------------------------------| I would prefer to be a millionaire but this does not make it so. |-------------------------------------------------------------------------| |"to think that VHDL processes do not affect each other while | |executing. The process is affected by others only when goes sleeping." | |-------------------------------------------------------------------------| Therefore you admit that processes are affected by other processes. |-------------------------------------------------------------------------| |" http://www.sigasi.com/content/vhdls-crown-jewel " | |-------------------------------------------------------------------------| I quote from this webpage: "[. . .] [. . .] A signal value update may trigger a number of processes. [. . .] [. . .]" |-------------------------------------------------------------------------| |"> Huh??? I use single stepping with VHDL at times. Normally it isn't | |> that useful because there is so much parallelism, things tend to jump | |> around as one process stops and another starts... same as software on a| |> processor with interrupts or multitasking. | | | |You do not have interrupts in VHDL. There is no preemption." | |-------------------------------------------------------------------------| It was a comparison - like saying that stars are like very big fires in the sky. There are not very big fires in the sky - there are stars and stars are like very big fires. |-------------------------------------------------------------------------| |"VHDL is a | |graceful," | |-------------------------------------------------------------------------| VHDL is graceful. |-------------------------------------------------------------------------| |""cooperative" multitasking."" | |-------------------------------------------------------------------------| The SystemC(R) standard is defined in terms of cooperative so-called multitasking which (unlike VHDL) does not have true concurrency. Regards, Paul Colin Gloster From newsfish@newsfish Thu Aug 1 00:35:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Tue, 5 Jan 2016 19:44:58 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Jan 2016 17:42:19 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="10312"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/IWVWyoBrORg1TOAARxkx/1Rih/sWSTdM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:hVulAEyKYGB3D1K39VKLzHSGJD8= Xref: news.eternal-september.org comp.lang.vhdl:4237 > In VHDL you can describe CPU, shared between processes with interrupts Sorry, I was sure that you are talking about simple simulation of VHDL processes. Now, you say that my TV has apples in it. Indeed, I can broadcast the garden and have apples in my TV. It therefore has apples in it. Gotcha! That is a feature of TV set. VHDL process cannot be interrupted. It is dedicated to its program. It cannot execute anything else at all. > Processes can be affected by others only while waiting for events > Therefore you admit that processes are affected by other processes. I admit that they can be interrupted, you say. Indeed, when you have nothing to do and come to the task table to request a new task for you, and they give you that task -- your execution is interrupted! You gotcha me! Indeed, I did not consider that waiting for tasks can be interrupted by the response. This also means that Akka actors are interruptable. I do not understand what people debate in this case https://groups.google.com/forum/#!msg/akka-user/TlIbfaC1eb8/EQ8S2NoI-oIJ. They seem not able to find a way to interrupt the actors. What is the problem? Every actor is interruptable, as you say. Just let it finish the work and read your interrupt/task from the queue! From newsfish@newsfish Thu Aug 1 00:35:58 2024 X-Received: by 10.66.221.39 with SMTP id qb7mr2806688pac.23.1452525403278; Mon, 11 Jan 2016 07:16:43 -0800 (PST) X-Received: by 10.50.25.196 with SMTP id e4mr254014igg.8.1452525403200; Mon, 11 Jan 2016 07:16:43 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h5no3018110igh.0!news-out.google.com!kr2ni2032igb.0!nntp.google.com!h5no3018100igh.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 11 Jan 2016 07:16:42 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.232.129.34; posting-account=0ESrfgoAAAAERS5Ih2LvEFl1I5btxL51 NNTP-Posting-Host: 103.232.129.34 References: <9151fs$8o1$1@kermit.esat.net> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0aa2ca6e-5f19-43bd-ae9b-d4b52f5d0064@googlegroups.com> Subject: Re: 8B/10B encoder From: ravalitngp@gmail.com Injection-Date: Mon, 11 Jan 2016 15:16:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4238 iam doing project on 8b/10b encoder...idnt know how the lookup tables values came??please give me the explanation of the lookup tables.. From newsfish@newsfish Thu Aug 1 00:35:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: 8B/10B encoder Date: Mon, 11 Jan 2016 18:33:35 -0500 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <9151fs$8o1$1@kermit.esat.net> <0aa2ca6e-5f19-43bd-ae9b-d4b52f5d0064@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 11 Jan 2016 23:30:53 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="7014"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18es3nZgUxO+eAenbDMh8rz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: <0aa2ca6e-5f19-43bd-ae9b-d4b52f5d0064@googlegroups.com> Cancel-Lock: sha1:M8+63wqdu4SOutV3UsUQeKMN3qc= Xref: news.eternal-september.org comp.lang.vhdl:4239 On 1/11/2016 10:16 AM, ravalitngp@gmail.com wrote: > iam doing project on 8b/10b encoder...idnt know how the lookup tables values came??please give me the explanation of the lookup tables.. You have unencoded data bits which you use as an address to fetch the data from the encode lookup table for the encoded data. In reverse you have encoded data which you use as an address into a decode table to fetch the decoded data. I'm not sure I understand your question. -- Rick From newsfish@newsfish Thu Aug 1 00:35:58 2024 X-Received: by 10.50.97.98 with SMTP id dz2mr15812912igb.7.1452571712496; Mon, 11 Jan 2016 20:08:32 -0800 (PST) X-Received: by 10.50.30.201 with SMTP id u9mr339380igh.4.1452571712472; Mon, 11 Jan 2016 20:08:32 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h5no3264500igh.0!news-out.google.com!l1ni10941igd.0!nntp.google.com!h5no3264492igh.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 11 Jan 2016 20:08:31 -0800 (PST) In-Reply-To: <5f4c4790-0b8c-4510-879d-242387221552@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> <88321b8a-514d-4c41-b1c7-b9ef6b411e37@googlegroups.com> <5f4c4790-0b8c-4510-879d-242387221552@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <067934d6-ea7f-4648-bc4c-5c8b6ddfdd45@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Tue, 12 Jan 2016 04:08:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4240 On Monday, January 4, 2016 at 5:16:56 PM UTC-6, Lars Asplund wrote: > Hi Andy, >=20 > I've probably been a bit careless with the word "system" as well. What I'= m trying to say is that unit testing and higher level testing with integrat= ion focus is an effective way of developing your code *before* hitting the = synthesis button, i.e. the scope described in Jim's paper. >=20 > *After* you hit that button, assuming HW is available, you will need addi= tional testing and I agree that you won't see the true nature of your PL un= til it has been integrated into the complete system, tested over full opera= ting conditions and so on but that doesn't take away the value of getting t= o this point efficiently. >=20 > To me there's also a difference between the full functional testing done = at higher levels and that done at the unit level. The PL units that were ha= rd to test from the PL boundary will be even harder to test at the higher l= evels when additional HW and SW is involved. Due to the sheer amount of PL,= SW and HW units in a larger system it would also be unmanageable to expose= them all at every level of testing, it's just too much details. For exampl= e, if you let system testing focus on verifying system functions you will h= andle this and also make sure that the decomposition of system functionalit= y into unit functionality was done correctly. Unit functionality will be te= sted indirectly of course but if the unit details aren't exposed to system = testing there may be corner cases only visible to and verified by the unit = tests. Both types of testing add unique values. >=20 > Your point that there are other activities than test to get valuable feed= back on your design is important and often forgotten. Especially reviews wh= ich have been shown to be an important ingredient in quality work. The goal= to simplify, automate and shorten the feedback loop applies to these activ= ities as well and unit testing plays a role in doing so. Here are some ways= to improve on code reviews > * You can let a lint tool check some of your coding guidelines rather tha= n having that manually reviewed. > * If you review code and unit tests at the same time the reviewers won't = waste their time trying to figure out if the code works at all. The reviewe= r can also learn a lot by looking at what was tested and how it was tested.= For example, if he/she expects some functionality but there are no test ca= ses for that it means that the functionality is missing or it's not properl= y verified. > * If you set up a formal code review meeting you have to find a time that= fits everyone so the feedback cycle can be long. Since most of the work is= done by the reviewers before the meeting you can shorten that time with a = tool that allows everyone to review and comment code inline and submit when= done. > * Live reviewing through pair programming will make the feedback loop muc= h shorter. To what extent pair programming is cost efficient is often debat= ed but my personal view is that it should be used when *you* feel that you'= re about to take on a tricky piece of code and could use another pair of ey= es. In the end someone else should review your code, one way or the other.= =20 > * Self-reviews also provide fast feedback and should always be done. The = act of writing unit tests helps you with that. It helps you take a step bac= k and think critically about your code. I would say that I find/avoid at le= ast as many flaws writing the unit tests as I do running them. So self-revi= ews are in a way more powerful than unit testing but here is an interesting= question. Would you be as rigorous about self-reviewing if you didn't have= a precise method "forcing" you into it? Even when all your test cases pass= you should have another look. It works, but can I make it work more effici= ent, can I make the code more readable, is code coverage sufficient and so = on. When you have a set of fast and working unit tests the fear of changing= something that works is much reduced. >=20 > Reviews are powerful but a problem is that we tend to be lazy. "There's n= o need to review this small change or run the slow top-level simulations be= cause it's not going to affect anything other than what I was trying to fix= . I'm just going to build a new FPGA and release it.". Running a selected s= et of fast regression unit tests in a background thread is an effortless wa= y of stopping you when you're wrong. >=20 > The benefits of loose coupling and high cohesion I was thinking about are= those associated with the source code. Better readability, maintainability= , and also significantly lower bug rates. The fact that the tools may destr= oy that modularity when optimizing is actually good because it means, to so= me extent, that I can meet my constraints while still enjoying the benefits= of modular code. The alternative would be to write optimized code, destroy= the code modularity and lose the benefits. >=20 > /Lars Lars, You make excellent points about the importance of good code reviews. One ca= nnot over-emphasize that. I'll admit that reaching the level of coverage with simulations from the ch= ip's edge is not inexpensive. It requires LOTS of simulation time. Luckily = that scales up extremely efficiently with relatively few personnel (just co= mputers and simulator licenses). It also plays well in a constrained-random= verification environment, making the creation of lots of test cases relati= vely easy. Coverage models in the testbench (bins, covergroups, etc.) and i= n the DUT (e.g. statement, FEC, etc.) help tell you when you are done. Intelligent randomization, like that possible in OSVVM, can significantly r= educe redundancy in randomization, and save runs (time and/or licenses). Even without unit level testing per se, it is easy to create wrapper compon= ents (or just architectures) for units that can help ensure that other modu= les are handling the interface correctly. For instance if I have one unit t= hat provides data with a valid strobe asserted when the data is available, = a wrapper can force unknown (or random) data on the output when the strobe = is not asserted. If the recipient tries to use the data when the strobe is = not asserted, then easily discoverable functional errors will result.=20 One can also provide protocol monitors on internal unit interfaces to verif= y coverage of tricky unit interface sequences if needed.=20 These are much easier to develop than full-blown unit testing, especially i= n environments such as ours where functional coverage at the device level, = in both HW and simulation, is needed. That is the only way you can fully te= st your "compiled" code, and therefore the "compiler" (SP&R) too. Andy From newsfish@newsfish Thu Aug 1 00:35:59 2024 X-Received: by 10.13.216.22 with SMTP id a22mr28887087ywe.28.1453236275644; Tue, 19 Jan 2016 12:44:35 -0800 (PST) X-Received: by 10.50.66.230 with SMTP id i6mr886igt.3.1453236275602; Tue, 19 Jan 2016 12:44:35 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!6no5950111qgy.0!news-out.google.com!kr2ni3326igb.0!nntp.google.com!h5no6825632igh.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 19 Jan 2016 12:44:34 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.89.38.60; posting-account=BmNvAQoAAADYUJPsy0vqrxEAse3S6GbJ NNTP-Posting-Host: 85.89.38.60 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6892ebc4-e17c-4382-bf5a-32d55d8a9fb2@googlegroups.com> Subject: set in A vector to the B-th bit value of '1' From: Merlyn <5156214@gmail.com> Injection-Date: Tue, 19 Jan 2016 20:44:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1775 X-Received-Body-CRC: 1359241846 Xref: news.eternal-september.org comp.lang.vhdl:4241 I have three inputs and one output in my enity: entity TEST is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input c : in STD_LOGIC_VECTOR (1 downto 0); --2 bit input out_0 : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output end TEST; I need to do something like this: if c = "10" then if b=("--00") then a_1<= ('---1'); --b(3,4=0 in decimal), a(0)=1 elsif b_1=("--01") then a_1 <= ("--1-"); --b(3,4=1 in decimal), a(1)=1 elsif b_1=("--10") then a_1 <= ("-1--"); --b(3,4=2 in decimal), a(2)=1 elsif b_1=("--11) then a_1 <= ("1---"); end if;--b(3,4=3 in decimal), a(3)=1 end if; out_3 <= a_1; --(--bits don't care 0 or 1) Must I convert STD_LOGIC_VECTOR something else or how can i do that? From newsfish@newsfish Thu Aug 1 00:35:59 2024 X-Received: by 10.182.24.41 with SMTP id r9mr31326037obf.25.1453275323532; Tue, 19 Jan 2016 23:35:23 -0800 (PST) X-Received: by 10.50.160.34 with SMTP id xh2mr50312igb.1.1453275323513; Tue, 19 Jan 2016 23:35:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h5no6987653igh.0!news-out.google.com!kr2ni3742igb.0!nntp.google.com!h5no6987651igh.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 19 Jan 2016 23:35:22 -0800 (PST) In-Reply-To: <6892ebc4-e17c-4382-bf5a-32d55d8a9fb2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <6892ebc4-e17c-4382-bf5a-32d55d8a9fb2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1de12a7a-654c-4731-8eca-2748e3a979a8@googlegroups.com> Subject: Re: set in A vector to the B-th bit value of '1' From: goouse99@gmail.com Injection-Date: Wed, 20 Jan 2016 07:35:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4242 Am Dienstag, 19. Januar 2016 21:44:39 UTC+1 schrieb Merlyn: > I have three inputs and one output in my enity: > entity TEST is > Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input > b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input > c : in STD_LOGIC_VECTOR (1 downto 0); --2 bit input > out_0 : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output > end TEST; > > > I need to do something like this: > if c = "10" then > if b=("--00") then a_1<= ('---1'); --b(3,4=0 in decimal), a(0)=1 > elsif > b_1=("--01") then a_1 <= ("--1-"); --b(3,4=1 in decimal), a(1)=1 > elsif > b_1=("--10") then a_1 <= ("-1--"); --b(3,4=2 in decimal), a(2)=1 > elsif > b_1=("--11) then a_1 <= ("1---"); end if;--b(3,4=3 in decimal), a(3)=1 > end if; > out_3 <= a_1; > --(--bits don't care 0 or 1) > > Must I convert STD_LOGIC_VECTOR something else or how can i do that? Hi, you can make use of some type conversion like this: use numeric_std.all; a(to_integer(unsigned(b(1 downto 0))) <= '1' --if you want to do everything in one line add this: when c="10" else null; Have a nice synthesis Eilert From newsfish@newsfish Thu Aug 1 00:35:59 2024 X-Received: by 10.50.18.100 with SMTP id v4mr5532801igd.1.1453502651373; Fri, 22 Jan 2016 14:44:11 -0800 (PST) X-Received: by 10.50.114.132 with SMTP id jg4mr231145igb.1.1453502651353; Fri, 22 Jan 2016 14:44:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h5no8147739igh.0!news-out.google.com!l1ni4125igd.0!nntp.google.com!o2no5399873iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 Jan 2016 14:44:10 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <001b0749-e98d-4ac0-b98d-cd6bcec2c84d@googlegroups.com> Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) From: Andy Injection-Date: Fri, 22 Jan 2016 22:44:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4243 On Monday, January 4, 2016 at 2:01:27 PM UTC-6, rickman wrote: Rick, In VHDL, every process is run once at time 0, delta 0, regardless of the se= nsitivity list.=20 Thus, even in a clocked process with only the clock in the sensitivity list= , it the clock condition does not include the event part, then such a proce= ss will run as if clock edge had occurred (if the clock is already '1' at T= 0,d0).=20 That may not be how the hardware would behave, and result in simulation mis= matches between gate & RTL, or real HW & RTL. Wait statements are not fooled, nor are if statements if they include the e= vent part. And if asynchronous reset is used (and reset is in the sensitivity list), t= hen the clock if-statement may evaluate true if there was an event on reset= (like a falling edge), while the clock was (already) '1', thus erroneously= behaving as if a clock edge was present. To be safe, and not have different clock-edge-detection conditions for both= synchronously and asynchronously reset registers, just include the edge pa= rt all the time. And rising_edge()/falling_edge() provide that for you in a= much more readable manner. Andy > On 1/4/2016 2:35 PM, Andy wrote: > > > > IEEE STD 1076.6-2004 (IEEE STANDARD FOR VHDL REGISTER TRANSFER LEVEL > > SYNTHESIS), Section 6.1.2 Clock Edge Specification, requires both a > > level and an event part for the clock specification. Thus either > > clock'event or not clock'stable is required. >=20 > In a process the clock will be in the sensitivity list. So technically,= =20 > doesn't that imply an event any time the process runs? >=20 > --=20 >=20 > Rick From newsfish@newsfish Thu Aug 1 00:36:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "tuclogicguy" Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Mon, 25 Jan 2016 22:32:55 -0700 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Injection-Date: Tue, 26 Jan 2016 05:32:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0e31ff6ed6443f43d4ddd5802d1008e1"; logging-data="30419"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/KwqbnpbP9cAZKx+IlfCGvtJqPF5wXv/8=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6157 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:SUlTPseUWJr+1v747/4/kWUbOtQ= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:4244 "glen herrmannsfeldt" wrote in message news:mvs55c$vs$1@speranza.aioe.org... > rickman wrote: >> On 10/16/2015 3:31 PM, Ilya Kalistru wrote: >>> I came across a strange behavior in my project and can't understand >>> it. >>> Maybe you could explain it to me. > > (snip) > >>> R_CHCS_proc : process (Clock) is >>> begin >>> if rising_edge(Clock) then >>> for i in 0 to 0 loop >>> R_CHCS(i * 2) <= '0'; >>> end loop; >>> end if; >>> end process R_CHCS_proc; > >>> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); > > (snip) > >>> On the first clock cycle R_CHCS becomes "X0". > > (snip) > > Also, I didn't know that you could use rising_edge(clock) outside > of process, but then again, I never even thought to try it. > > > -- glen Actually, R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); IS a process; it's just an unnamed process. Any concurrent VHDL statement is a process whether you explicitly call it a process or not. Similarly, Y <= A and B; is also a process and just a shorthand way of writing: some_proc: process(A,B) begin Y <= A and B; end process; Charles Bailey From newsfish@newsfish Thu Aug 1 00:36:00 2024 X-Received: by 10.182.125.132 with SMTP id mq4mr21836217obb.22.1453804927237; Tue, 26 Jan 2016 02:42:07 -0800 (PST) X-Received: by 10.50.114.132 with SMTP id jg4mr509489igb.1.1453804927212; Tue, 26 Jan 2016 02:42:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h5no9544483igh.0!news-out.google.com!kr2ni10479igb.0!nntp.google.com!o2no6282227iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Jan 2016 02:42:06 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e309e0e-5b2e-419f-a79e-92478a6cc013@googlegroups.com> Subject: UVVM (Universal VHDL Verification Methodology) goes Open Source - available on GitHub From: espen.tallaksen@bitvis.no Injection-Date: Tue, 26 Jan 2016 10:42:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4245 UVVM Utility Library has always been open source. UVVM VVC Framework (VVC= =3DVHDL Verification Component) on the other hand has so far only been avai= lable as encrypted Freeware, but is as of today released as open source - = free and with no encryption. This means the complete UVVM is now open sourc= e. UVVM Utility Library (previously Bitvis Utility Library) is a basic VHDL te= stbench infrastructure that allows a much faster testbench development with= a good logging and alert handling mechanism, topped with lots of useful ch= ecking procedures - like checking a signal value, stability and change. It = also has lots of support for string handling and BFMs, and a simple, but ef= ficient set of functions for random value generation.=20 UVVM Utility Library is dead easy to use. The extremely low user threshold = allows users to be up and running in less than an hour. This previous post on LinkedIn will give you some more info on why you shou= ld use this library. UVVM VVC Framework is a VHDL Verification Component system that allows mult= iple interfaces on a DUT to be stimulated/handled simultaneously in a very = structured manner, and controlled by a very simple to understand software l= ike test sequencer.=20 VVC Framework is unique as an open source VHDL approach to building a struc= tured testbench architecture using Verification components and a simple pro= tocol to access these. As an example a simple command like uart_expect(UART= _VVCT, my_data), or axilite_write(AXILITE_VVCT, my_addr, my_data, my_messag= e) will automatically tell the respective VVC (for UART or AXI-Lite) to exe= cute the uart_receive() or axilite_write() BFM respectively. The really gre= at benefit here is that these commands may be issued at the same time from = the test sequencer - thus allowing full control of when an access is to be = performed, and the commands are understandable "even" for a software develo= per ;-) The commands may be queued, skewed, delayed, synchronised, etc - = and a super-set for applying constrained random or other sequences of data = may of of course also be applied. This yields an excellent control over your testbench and VVCs. For debugging you can select logging of a command when it is issued from th= e sequencer, when it is received by the VVC, when it is initiated by the VV= C and/or when it has been executed towards the DUT. This allows full overvi= ew of all actions in your complete testbench. This previous post on LinkedIn will give you some more info on why you shou= ld use this library. Utility Library may be used stand-alone for simple testbenches, whereas VVC= Framework uses the Utility Library for logging, alert handling and checker= s.=20 The UVVM libraries may be downloaded from GitHub (https://github.com/UVVM) = or from Bitvis (http://bitvis.no/products/uvvm-vvc-framework/). From newsfish@newsfish Thu Aug 1 00:36:00 2024 X-Received: by 10.50.43.233 with SMTP id z9mr24367811igl.8.1453842347258; Tue, 26 Jan 2016 13:05:47 -0800 (PST) X-Received: by 10.50.164.194 with SMTP id ys2mr195513igb.3.1453842347202; Tue, 26 Jan 2016 13:05:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!csiph.com!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!h5no9814958igh.0!news-out.google.com!kr2ni10908igb.0!nntp.google.com!h5no9814950igh.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Jan 2016 13:05:46 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.168.172.44; posting-account=Puu0BAoAAABRoL6t2bQ2nxqrugrAOjOb NNTP-Posting-Host: 80.168.172.44 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> Subject: Newbie question From: gmortimer20031 Injection-Date: Tue, 26 Jan 2016 21:05:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 9 Xref: news.eternal-september.org comp.lang.vhdl:4246 I am a systems designer using Vivado for the first time, Zynq for the first= time and programming logic in V (or indeed any) HDL for the first time and= this is also part of a job. So usual story. Fortunately the system is reas= onably self-documenting and the customer knows the score.=20 Does anyone know of good bedtime reading matter (I have the Zynq book, look= ing for a good VHDL cookbook)? MTIA Geoff From newsfish@newsfish Thu Aug 1 00:36:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question Date: Tue, 26 Jan 2016 18:16:44 -0500 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 26 Jan 2016 23:13:53 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="98c9539d2f771747fff4f254680d204c"; logging-data="20893"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+c07gAUgL0LpSwJWsV1iux" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> Cancel-Lock: sha1:lNDS5Pr80mapl4HJbJnvzuWYKSk= Xref: news.eternal-september.org comp.lang.vhdl:4247 On 1/26/2016 4:05 PM, gmortimer20031 wrote: > I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score. > > Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)? Can you give me more of an idea of your experience designing hardware and/or HDL? I remember some years ago a software designer came here to ask for help writing a hello world program in VHDL. He was a sharp guy but did the usual thing of starting out writing like it was C code. It only took a little help and he got his goal done. We were banging pretty hard on him about thinking in terms of hardware rather than what he was used to. In the end he showed us wrong and did a good job. I don't have a go-to book to recommend, at least not until I understand better your level of experience. If you have no experience it may be a harder road than you realize. One other thing, I have heard from some there is a weak link in the connection between the ARM firmware and the FPGA fabric. He said the tool to support that was very hard to use and understand. -- Rick From newsfish@newsfish Thu Aug 1 00:36:01 2024 X-Received: by 10.129.53.68 with SMTP id c65mr24616912ywa.15.1453856283465; Tue, 26 Jan 2016 16:58:03 -0800 (PST) X-Received: by 10.50.20.232 with SMTP id q8mr45340ige.0.1453856283391; Tue, 26 Jan 2016 16:58:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!6no7268497qgy.0!news-out.google.com!kr2ni11055igb.0!nntp.google.com!h5no9894327igh.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Jan 2016 16:58:02 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.168.172.44; posting-account=Puu0BAoAAABRoL6t2bQ2nxqrugrAOjOb NNTP-Posting-Host: 80.168.172.44 References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbie question From: gmortimer20031 Injection-Date: Wed, 27 Jan 2016 00:58:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4248 On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote: > On 1/26/2016 4:05 PM, gmortimer20031 wrote: > > I am a systems designer using Vivado for the first time, Zynq for the f= irst time and programming logic in V (or indeed any) HDL for the first time= and this is also part of a job. So usual story. Fortunately the system is = reasonably self-documenting and the customer knows the score. > > > > Does anyone know of good bedtime reading matter (I have the Zynq book, = looking for a good VHDL cookbook)? >=20 > Can you give me more of an idea of your experience designing hardware=20 > and/or HDL? >=20 > I remember some years ago a software designer came here to ask for help= =20 > writing a hello world program in VHDL. He was a sharp guy but did the=20 > usual thing of starting out writing like it was C code. It only took a= =20 > little help and he got his goal done. We were banging pretty hard on=20 > him about thinking in terms of hardware rather than what he was used to.= =20 > In the end he showed us wrong and did a good job. >=20 > I don't have a go-to book to recommend, at least not until I understand= =20 > better your level of experience. If you have no experience it may be a= =20 > harder road than you realize. >=20 > One other thing, I have heard from some there is a weak link in the=20 > connection between the ARM firmware and the FPGA fabric. He said the=20 > tool to support that was very hard to use and understand. >=20 > --=20 >=20 > Rick Hi Rick, many thanks for the reply I have a hardware background, so I understand the concurrency of operations= and the before/after clocked scenario, as well as issues such as clock dom= ain crossing. I must confess I have taken many leads from the Xilinx-suppli= ed VHDL and the free sites so many US universities make available. I'm begi= nning to understand the pumped architecture of much of the AXI interface. The weak link worries me - the interrupt-driven demo in the Zynq book Tutor= ial appears to create an interrupt storm! Best regards Geoff From newsfish@newsfish Thu Aug 1 00:36:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question Date: Tue, 26 Jan 2016 22:46:42 -0500 Organization: A noiseless patient Spider Lines: 51 Message-ID: References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 27 Jan 2016 03:43:51 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="98c9539d2f771747fff4f254680d204c"; logging-data="30870"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/DCkjX0e+qjvlUOOPP7Y5/" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: Cancel-Lock: sha1:eyZ7GjN8hXp5JsrOZTtNDLETsoQ= Xref: news.eternal-september.org comp.lang.vhdl:4249 On 1/26/2016 7:58 PM, gmortimer20031 wrote: > On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote: >> On 1/26/2016 4:05 PM, gmortimer20031 wrote: >>> I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score. >>> >>> Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)? >> >> Can you give me more of an idea of your experience designing hardware >> and/or HDL? >> >> I remember some years ago a software designer came here to ask for help >> writing a hello world program in VHDL. He was a sharp guy but did the >> usual thing of starting out writing like it was C code. It only took a >> little help and he got his goal done. We were banging pretty hard on >> him about thinking in terms of hardware rather than what he was used to. >> In the end he showed us wrong and did a good job. >> >> I don't have a go-to book to recommend, at least not until I understand >> better your level of experience. If you have no experience it may be a >> harder road than you realize. >> >> One other thing, I have heard from some there is a weak link in the >> connection between the ARM firmware and the FPGA fabric. He said the >> tool to support that was very hard to use and understand. >> >> -- >> >> Rick > > Hi Rick, many thanks for the reply > > I have a hardware background, so I understand the concurrency of operations and the before/after clocked scenario, as well as issues such as clock domain crossing. I must confess I have taken many leads from the Xilinx-supplied VHDL and the free sites so many US universities make available. I'm beginning to understand the pumped architecture of much of the AXI interface. > > The weak link worries me - the interrupt-driven demo in the Zynq book Tutorial appears to create an interrupt storm! I guess the upside is you can have two CPUs to handle all the work. With a fairly large FPGA you can partition the firmware and HDL as you choose. I know it is popular to run Linux on one CPU and real time code on the other while pushing only the really hard real time stuff in the FPGA. So you have a background in hardware, just not in HDL. I am guessing you are committed to VHDL because of others' preferences. I didn't have too much trouble learning to code in VHDL other than the type conversions. That is a lot easier with the signed and unsigned data types in the numeric_std package. I virtually don't use std_logic_vector anymore. -- Rick From newsfish@newsfish Thu Aug 1 00:36:02 2024 X-Received: by 10.66.157.37 with SMTP id wj5mr25695483pab.30.1453870733633; Tue, 26 Jan 2016 20:58:53 -0800 (PST) X-Received: by 10.50.3.73 with SMTP id a9mr694494iga.4.1453870733600; Tue, 26 Jan 2016 20:58:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h5no9951404igh.0!news-out.google.com!l1ni8971igd.0!nntp.google.com!h5no9951403igh.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Jan 2016 20:58:52 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.168.172.44; posting-account=Puu0BAoAAABRoL6t2bQ2nxqrugrAOjOb NNTP-Posting-Host: 80.168.172.44 References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbie question From: gmortimer20031 Injection-Date: Wed, 27 Jan 2016 04:58:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5016 X-Received-Body-CRC: 651113738 Xref: news.eternal-september.org comp.lang.vhdl:4250 On Wednesday, 27 January 2016 03:46:43 UTC, rickman wrote: > On 1/26/2016 7:58 PM, gmortimer20031 wrote: > > On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote: > >> On 1/26/2016 4:05 PM, gmortimer20031 wrote: > >>> I am a systems designer using Vivado for the first time, Zynq for the= first time and programming logic in V (or indeed any) HDL for the first ti= me and this is also part of a job. So usual story. Fortunately the system i= s reasonably self-documenting and the customer knows the score. > >>> > >>> Does anyone know of good bedtime reading matter (I have the Zynq book= , looking for a good VHDL cookbook)? > >> > >> Can you give me more of an idea of your experience designing hardware > >> and/or HDL? > >> > >> I remember some years ago a software designer came here to ask for hel= p > >> writing a hello world program in VHDL. He was a sharp guy but did the > >> usual thing of starting out writing like it was C code. It only took = a > >> little help and he got his goal done. We were banging pretty hard on > >> him about thinking in terms of hardware rather than what he was used t= o. > >> In the end he showed us wrong and did a good job. > >> > >> I don't have a go-to book to recommend, at least not until I understan= d > >> better your level of experience. If you have no experience it may be = a > >> harder road than you realize. > >> > >> One other thing, I have heard from some there is a weak link in the > >> connection between the ARM firmware and the FPGA fabric. He said the > >> tool to support that was very hard to use and understand. > >> > >> -- > >> > >> Rick > > > > Hi Rick, many thanks for the reply > > > > I have a hardware background, so I understand the concurrency of operat= ions and the before/after clocked scenario, as well as issues such as clock= domain crossing. I must confess I have taken many leads from the Xilinx-su= pplied VHDL and the free sites so many US universities make available. I'm = beginning to understand the pumped architecture of much of the AXI interfac= e. > > > > The weak link worries me - the interrupt-driven demo in the Zynq book T= utorial appears to create an interrupt storm! >=20 > I guess the upside is you can have two CPUs to handle all the work.=20 > With a fairly large FPGA you can partition the firmware and HDL as you=20 > choose. I know it is popular to run Linux on one CPU and real time code= =20 > on the other while pushing only the really hard real time stuff in the=20 > FPGA. >=20 > So you have a background in hardware, just not in HDL. I am guessing=20 > you are committed to VHDL because of others' preferences. I didn't have= =20 > too much trouble learning to code in VHDL other than the type=20 > conversions. That is a lot easier with the signed and unsigned data=20 > types in the numeric_std package. I virtually don't use=20 > std_logic_vector anymore. >=20 > --=20 >=20 > Rick The RTOS/metal division is certainly popular but gross overkill for this pr= oject. It is hoped practically everything can be done in the PL - partly as= a learning exercise. I need to capture input date with a precision ADC at = 1 MHz, downsample to 20kHz through a FIR filter and then perform a 1024-poi= nt FFT on the resulting stream. I have it schemed out but had completely un= derestimated the amount of hand coding involved in sticking together the Xi= linx IP! I feel a new career coming on! I have some third-hand zynq experience, with a bunch who used MATLAB/Simuli= nk to generate the code for the PL - no sign of any problem crossing the fa= bric to/from the ARMs. I will dig further, last thing I need at this point = on the learning curve. Best regards Geoff From newsfish@newsfish Thu Aug 1 00:36:02 2024 X-Received: by 10.129.152.137 with SMTP id p131mr25572372ywg.39.1453872169846; Tue, 26 Jan 2016 21:22:49 -0800 (PST) X-Received: by 10.50.41.5 with SMTP id b5mr698631igl.8.1453872169690; Tue, 26 Jan 2016 21:22:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!6no7290399qgy.0!news-out.google.com!l1ni9001igd.0!nntp.google.com!h5no9957511igh.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Jan 2016 21:22:48 -0800 (PST) In-Reply-To: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.168.172.44; posting-account=Puu0BAoAAABRoL6t2bQ2nxqrugrAOjOb NNTP-Posting-Host: 80.168.172.44 References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4553b83c-5d7d-46aa-a31d-b046c1616808@googlegroups.com> Subject: Re: Newbie question From: gmortimer20031 Injection-Date: Wed, 27 Jan 2016 05:22:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4251 On Tuesday, 26 January 2016 21:05:50 UTC, gmortimer20031 wrote: > I am a systems designer using Vivado for the first time, Zynq for the fir= st time and programming logic in V (or indeed any) HDL for the first time a= nd this is also part of a job. So usual story. Fortunately the system is re= asonably self-documenting and the customer knows the score.=20 >=20 > Does anyone know of good bedtime reading matter (I have the Zynq book, lo= oking for a good VHDL cookbook)? >=20 > MTIA > Geoff BTW if you use signed/unsigned can you do things like compare a signal with= a decimal value ('if (adc_count >=3D 17) then') and/or use shift operators= (asl, sra etc.)? From newsfish@newsfish Thu Aug 1 00:36:02 2024 X-Received: by 10.13.213.10 with SMTP id x10mr25925700ywd.46.1453872518952; Tue, 26 Jan 2016 21:28:38 -0800 (PST) X-Received: by 10.50.33.8 with SMTP id n8mr695109igi.9.1453872518907; Tue, 26 Jan 2016 21:28:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!94no7542701qgt.1!news-out.google.com!kr2ni11261igb.0!nntp.google.com!o2no6575585iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Jan 2016 21:28:38 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.168.172.44; posting-account=Puu0BAoAAABRoL6t2bQ2nxqrugrAOjOb NNTP-Posting-Host: 80.168.172.44 References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbie question From: gmortimer20031 Injection-Date: Wed, 27 Jan 2016 05:28:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4252 On Wednesday, 27 January 2016 04:58:56 UTC, gmortimer20031 wrote: > On Wednesday, 27 January 2016 03:46:43 UTC, rickman wrote: > > On 1/26/2016 7:58 PM, gmortimer20031 wrote: > > > On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote: > > >> On 1/26/2016 4:05 PM, gmortimer20031 wrote: > > >>> I am a systems designer using Vivado for the first time, Zynq for t= he first time and programming logic in V (or indeed any) HDL for the first = time and this is also part of a job. So usual story. Fortunately the system= is reasonably self-documenting and the customer knows the score. > > >>> > > >>> Does anyone know of good bedtime reading matter (I have the Zynq bo= ok, looking for a good VHDL cookbook)? > > >> > > >> Can you give me more of an idea of your experience designing hardwar= e > > >> and/or HDL? > > >> > > >> I remember some years ago a software designer came here to ask for h= elp > > >> writing a hello world program in VHDL. He was a sharp guy but did t= he > > >> usual thing of starting out writing like it was C code. It only too= k a > > >> little help and he got his goal done. We were banging pretty hard o= n > > >> him about thinking in terms of hardware rather than what he was used= to. > > >> In the end he showed us wrong and did a good job. > > >> > > >> I don't have a go-to book to recommend, at least not until I underst= and > > >> better your level of experience. If you have no experience it may b= e a > > >> harder road than you realize. > > >> > > >> One other thing, I have heard from some there is a weak link in the > > >> connection between the ARM firmware and the FPGA fabric. He said th= e > > >> tool to support that was very hard to use and understand. > > >> > > >> -- > > >> > > >> Rick > > > > > > Hi Rick, many thanks for the reply > > > > > > I have a hardware background, so I understand the concurrency of oper= ations and the before/after clocked scenario, as well as issues such as clo= ck domain crossing. I must confess I have taken many leads from the Xilinx-= supplied VHDL and the free sites so many US universities make available. I'= m beginning to understand the pumped architecture of much of the AXI interf= ace. > > > > > > The weak link worries me - the interrupt-driven demo in the Zynq book= Tutorial appears to create an interrupt storm! > >=20 > > I guess the upside is you can have two CPUs to handle all the work.=20 > > With a fairly large FPGA you can partition the firmware and HDL as you= =20 > > choose. I know it is popular to run Linux on one CPU and real time cod= e=20 > > on the other while pushing only the really hard real time stuff in the= =20 > > FPGA. > >=20 > > So you have a background in hardware, just not in HDL. I am guessing= =20 > > you are committed to VHDL because of others' preferences. I didn't hav= e=20 > > too much trouble learning to code in VHDL other than the type=20 > > conversions. That is a lot easier with the signed and unsigned data=20 > > types in the numeric_std package. I virtually don't use=20 > > std_logic_vector anymore. > >=20 > > --=20 > >=20 > > Rick >=20 > The RTOS/metal division is certainly popular but gross overkill for this = project. It is hoped practically everything can be done in the PL - partly = as a learning exercise. I need to capture input date with a precision ADC a= t 1 MHz, downsample to 20kHz through a FIR filter and then perform a 1024-p= oint FFT on the resulting stream. I have it schemed out but had completely = underestimated the amount of hand coding involved in sticking together the = Xilinx IP! I feel a new career coming on! >=20 > I have some third-hand zynq experience, with a bunch who used MATLAB/Simu= link to generate the code for the PL - no sign of any problem crossing the = fabric to/from the ARMs. I will dig further, last thing I need at this poin= t on the learning curve. >=20 > Best regards > Geoff BTW if you use signed/unsigned can you do things like compare a signal with= a decimal value ('if (adc_count >=3D 17) then') and/or use shift operators= (sla, sra etc.)? From newsfish@newsfish Thu Aug 1 00:36:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question Date: Wed, 27 Jan 2016 01:36:11 -0500 Organization: A noiseless patient Spider Lines: 80 Message-ID: References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 27 Jan 2016 06:33:19 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="98c9539d2f771747fff4f254680d204c"; logging-data="30190"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19J37UK3vffscIq5GaMTXsS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: Cancel-Lock: sha1:BGy+m/yl/xc3MF7rKaM0hBHxa28= Xref: news.eternal-september.org comp.lang.vhdl:4253 On 1/27/2016 12:28 AM, gmortimer20031 wrote: > On Wednesday, 27 January 2016 04:58:56 UTC, gmortimer20031 wrote: >> On Wednesday, 27 January 2016 03:46:43 UTC, rickman wrote: >>> On 1/26/2016 7:58 PM, gmortimer20031 wrote: >>>> On Tuesday, 26 January 2016 23:16:45 UTC, rickman wrote: >>>>> On 1/26/2016 4:05 PM, gmortimer20031 wrote: >>>>>> I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score. >>>>>> >>>>>> Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)? >>>>> >>>>> Can you give me more of an idea of your experience designing hardware >>>>> and/or HDL? >>>>> >>>>> I remember some years ago a software designer came here to ask for help >>>>> writing a hello world program in VHDL. He was a sharp guy but did the >>>>> usual thing of starting out writing like it was C code. It only took a >>>>> little help and he got his goal done. We were banging pretty hard on >>>>> him about thinking in terms of hardware rather than what he was used to. >>>>> In the end he showed us wrong and did a good job. >>>>> >>>>> I don't have a go-to book to recommend, at least not until I understand >>>>> better your level of experience. If you have no experience it may be a >>>>> harder road than you realize. >>>>> >>>>> One other thing, I have heard from some there is a weak link in the >>>>> connection between the ARM firmware and the FPGA fabric. He said the >>>>> tool to support that was very hard to use and understand. >>>>> >>>>> -- >>>>> >>>>> Rick >>>> >>>> Hi Rick, many thanks for the reply >>>> >>>> I have a hardware background, so I understand the concurrency of operations and the before/after clocked scenario, as well as issues such as clock domain crossing. I must confess I have taken many leads from the Xilinx-supplied VHDL and the free sites so many US universities make available. I'm beginning to understand the pumped architecture of much of the AXI interface. >>>> >>>> The weak link worries me - the interrupt-driven demo in the Zynq book Tutorial appears to create an interrupt storm! >>> >>> I guess the upside is you can have two CPUs to handle all the work. >>> With a fairly large FPGA you can partition the firmware and HDL as you >>> choose. I know it is popular to run Linux on one CPU and real time code >>> on the other while pushing only the really hard real time stuff in the >>> FPGA. >>> >>> So you have a background in hardware, just not in HDL. I am guessing >>> you are committed to VHDL because of others' preferences. I didn't have >>> too much trouble learning to code in VHDL other than the type >>> conversions. That is a lot easier with the signed and unsigned data >>> types in the numeric_std package. I virtually don't use >>> std_logic_vector anymore. >>> >>> -- >>> >>> Rick >> >> The RTOS/metal division is certainly popular but gross overkill for this project. It is hoped practically everything can be done in the PL - partly as a learning exercise. I need to capture input date with a precision ADC at 1 MHz, downsample to 20kHz through a FIR filter and then perform a 1024-point FFT on the resulting stream. I have it schemed out but had completely underestimated the amount of hand coding involved in sticking together the Xilinx IP! I feel a new career coming on! >> >> I have some third-hand zynq experience, with a bunch who used MATLAB/Simulink to generate the code for the PL - no sign of any problem crossing the fabric to/from the ARMs. I will dig further, last thing I need at this point on the learning curve. >> >> Best regards >> Geoff > > BTW if you use signed/unsigned can you do things like compare a signal with a decimal value ('if (adc_count >= 17) then') and/or use shift operators (sla, sra etc.)? A decimal value would be an integer data type and yes, you can compare that directly with a signed/unsigned type using the numeric_std library. Here is a link with a summary of numeric_std capabilities. https://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/ Doulos has a lot of summary info on many things including the VHDL 2008 which has many useful additions to the language. Highly recommended that you use it if your tools support it. In some tools you need to turn on 2008 support first. https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/ -- Rick From newsfish@newsfish Thu Aug 1 00:36:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe001.ams.xsnews.nl!abp001.ams.xsnews.nl!abuse.newsxs.nl!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Newbie question References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: <55728$56a88674$5f6173bc$32359@abuse.newsxs.nl> X-Complaints-To: abuse@newsxs.nl Organization: Newsxs Date: Wed, 27 Jan 2016 09:57:24 +0100 Lines: 24 X-Upload: Secured through NewsXS SSL NNTP-Posting-Date: Wed, 27 Jan 2016 09:57:24 +0100 Xref: news.eternal-september.org comp.lang.vhdl:4254 On 2016-01-26 gmortimer20031 wrote in comp.lang.vhdl: > I am a systems designer using Vivado for the first time, Zynq for the first time and programming logic in V (or indeed any) HDL for the first time and this is also part of a job. So usual story. Fortunately the system is reasonably self-documenting and the customer knows the score. > > Does anyone know of good bedtime reading matter (I have the Zynq book, looking for a good VHDL cookbook)? When I started on the Zynq, this blog was very helpfull: https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-116-Test-Pattern/ba-p/678021 It's now at part 116 (or more). When I started it went to 50 or something. Just start at the beginning (links are at the bottom of the above link). I got my fpga + 2-core bare metal app up and running with this, but I did have previous experience with fpga, vhdl, arm etc. Nice thing about the zynq is that that you can split up your application in 3 parts: sub-usec real time (fpga), 'normal' real time (one core) and long calculations or other tasks (second core), without the need to interrupt long tasks for real time stuff as this can be handled by the other core. At least if your application is suitable for such a division. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) War is never imperative. -- McCoy, "Balance of Terror", stardate 1709.2 From newsfish@newsfish Thu Aug 1 00:36:03 2024 X-Received: by 10.182.29.41 with SMTP id g9mr4206761obh.27.1454007559981; Thu, 28 Jan 2016 10:59:19 -0800 (PST) X-Received: by 10.50.138.138 with SMTP id qq10mr158921igb.10.1454007559953; Thu, 28 Jan 2016 10:59:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h5no10745585igh.0!news-out.google.com!l1ni10623igd.0!nntp.google.com!o2no7120336iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Jan 2016 10:59:19 -0800 (PST) In-Reply-To: <55728$56a88674$5f6173bc$32359@abuse.newsxs.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.168.172.44; posting-account=Puu0BAoAAABRoL6t2bQ2nxqrugrAOjOb NNTP-Posting-Host: 80.168.172.44 References: <5aa55d79-2e16-4fc7-8e68-f138883c4691@googlegroups.com> <55728$56a88674$5f6173bc$32359@abuse.newsxs.nl> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbie question From: gmortimer20031 Injection-Date: Thu, 28 Jan 2016 18:59:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4255 On Wednesday, 27 January 2016 08:59:53 UTC, Stef wrote: > On 2016-01-26 gmortimer20031 wrote in comp.lang.vhdl: > > I am a systems designer using Vivado for the first time, Zynq for the f= irst time and programming logic in V (or indeed any) HDL for the first time= and this is also part of a job. So usual story. Fortunately the system is = reasonably self-documenting and the customer knows the score.=20 > > > > Does anyone know of good bedtime reading matter (I have the Zynq book, = looking for a good VHDL cookbook)? >=20 > When I started on the Zynq, this blog was very helpfull: > https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chro= nicles-Part-116-Test-Pattern/ba-p/678021 >=20 > It's now at part 116 (or more). When I started it went to 50 or something= . > Just start at the beginning (links are at the bottom of the above link). > I got my fpga + 2-core bare metal app up and running with this, but I did > have previous experience with fpga, vhdl, arm etc. >=20 > Nice thing about the zynq is that that you can split up your application > in 3 parts: sub-usec real time (fpga), 'normal' real time (one core) and > long calculations or other tasks (second core), without the need to > interrupt long tasks for real time stuff as this can be handled by the > other core. At least if your application is suitable for such a division. >=20 > --=20 > Stef (remove caps, dashes and .invalid from e-mail address to reply by= mail) >=20 > War is never imperative. > -- McCoy, "Balance of Terror", stardate 1709.2 Hi Stef I'm writing the software for this thing too, but I think one core will suff= ice - just needs to communicate over CAN, at a relatively slow rate, the re= sults of the calculations.=20 Very nice to be able to dig into the hardware and see how it works. Best wishes Geoff From newsfish@newsfish Thu Aug 1 00:36:03 2024 X-Received: by 10.50.112.104 with SMTP id ip8mr11598715igb.5.1454320851011; Mon, 01 Feb 2016 02:00:51 -0800 (PST) X-Received: by 10.50.131.168 with SMTP id on8mr158691igb.5.1454320850995; Mon, 01 Feb 2016 02:00:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ks5no148528igb.0!news-out.google.com!kr2ni3363igb.0!nntp.google.com!ks5no148519igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 1 Feb 2016 02:00:50 -0800 (PST) In-Reply-To: <067934d6-ea7f-4648-bc4c-5c8b6ddfdd45@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> <88321b8a-514d-4c41-b1c7-b9ef6b411e37@googlegroups.com> <5f4c4790-0b8c-4510-879d-242387221552@googlegroups.com> <067934d6-ea7f-4648-bc4c-5c8b6ddfdd45@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Lars Asplund Injection-Date: Mon, 01 Feb 2016 10:00:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4256 Andy, Sorry for a late reply. You're right that you can increase simulation throughput by adding computer= cores and licenses. VUnit has the ability to distribute testing on *all* y= our CPU cores with a single command line option and it also supports GHDL s= o that there is no license cost associated with running many simulations in= the background. You can use GHDL for batch jobs and use a paid license whe= n working more interactively, for example when debugging. However, the latency of a test doesn't scale with more computers. A slow te= st will still be slow and affect the short code/test cycle I'm looking for.= A system-level testbench approach also tend to verify more things in the s= ame test which means that they can't be parallelized in the same way as uni= t tests where each test case can run on its own CPU core.=20 Unit testing is a complement to other testing methodologies so it doesn't e= xclude/replace constrained random testing (or system-level testing). OSVVM = is even redistributed with VUnit but we're about to stop doing that now tha= t OSVVM is released as an official GitHub repo. However, using randomizatio= n as a way to find internal corner cases that you know about can be problem= atic. How long will it take to activate that corner case? When activated, w= ill the effects be propagated to an observable output? There is a good quot= e from Neil Johnson on this. He's working with ASIC verification and is ver= y active in promoting unit testing and Agile principles in general for ASIC= development. He once said something like this about constrained random and= UVM "Constrained random verification is great for finding bugs you didn't know = about but terrible at finding potential bugs you do know" It seems to me that the wrapper to insert X is also a special case solution= to the general problem of testing at the wrong level. The things you want = to test are hard at the system level so you force values on an internal nod= e and use the special properties of X to find the effects. However, making = sure that such an X isn't consumed by a receiver is only one of the interfa= ce properties you want to verify on that hard to reach receiver unit and mo= st of the potential bugs won't result in an easy to spot X value. Embedding checks to monitor things like the protocol of an interface is som= ething that can be done with unit testing as well. Let the unit test provid= e the stimuli but put the checks within the code if you want them to be reu= sed in other test contexts. VUnit checks have translate_on/off pragmas inte= rnally so that they are ignored by synthesis. You can find this in the VUni= t examples https://github.com/VUnit/vunit/tree/master/examples/vhdl We seem to have different opinions on these matters but I think one of the = core Agile values applies. Individuals and interactions over processes and = tools. For obvious reasons I believe that VUnit is something all teams shou= ld try out but in the end it's up to the team to figure out what works for = them. VUnit can be used to automate your type of testing, run constrained r= andom testing, distribute tests on different cores and so on. It's not unit= testing but it might be something that works perfectly for you. We're just= about to update the VUnit web site (vunit.github.io) and in the new versio= n we've actually changed the one line description of VUnit from "a unit tes= ting framework for VHDL" to "a test framework for HDL". This better reflect= s its broad application and the fact that we also have emerging support for= SystemVerilog. Lars From newsfish@newsfish Thu Aug 1 00:36:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Szakacs Newsgroups: comp.lang.vhdl Subject: Re: UVVM (Universal VHDL Verification Methodology) goes Open Source - available on GitHub Date: Mon, 1 Feb 2016 21:52:24 -0500 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <8e309e0e-5b2e-419f-a79e-92478a6cc013@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 2 Feb 2016 02:49:55 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9bd0ba8c53fd0f12dc2ce700b744f948"; logging-data="30735"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/r/S5ycBcsyfF0+1jYbHN7" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: <8e309e0e-5b2e-419f-a79e-92478a6cc013@googlegroups.com> Cancel-Lock: sha1:Pa7XQGsMdlDuqdSCDR2c/1g6GC4= Xref: news.eternal-september.org comp.lang.vhdl:4257 On 1/26/2016 5:42 AM, espen.tallaksen@bitvis.no wrote: > UVVM Utility Library has always been open source. > One more layer of nested acronym: VHSIC = Very High Speed Integrated Circuit (old DARPA project) VHDL = VHSIC Hardware Description Language UVVM = Universal VHDL Verification Methodology -- Gabor From newsfish@newsfish Thu Aug 1 00:36:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe001.ams.xsnews.nl!abp001.ams.xsnews.nl!abuse.newsxs.nl!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: UVVM (Universal VHDL Verification Methodology) goes Open Source - available on GitHub References: <8e309e0e-5b2e-419f-a79e-92478a6cc013@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: <2ad1f$56b08763$5f6173bc$8871@abuse.newsxs.nl> X-Complaints-To: abuse@newsxs.nl Organization: Newsxs Date: Tue, 02 Feb 2016 11:39:31 +0100 Lines: 20 X-Upload: Secured through NewsXS SSL NNTP-Posting-Date: Tue, 02 Feb 2016 11:39:31 +0100 Xref: news.eternal-september.org comp.lang.vhdl:4258 On 2016-02-02 Gabor Szakacs wrote in comp.lang.vhdl: > On 1/26/2016 5:42 AM, espen.tallaksen@bitvis.no wrote: >> UVVM Utility Library has always been open source. >> > > One more layer of nested acronym: > > VHSIC = Very High Speed Integrated Circuit (old DARPA project) > VHDL = VHSIC Hardware Description Language > UVVM = Universal VHDL Verification Methodology Or, after pre-processing: UVVM = Universal Very High Speed Integrated Circuit Hardware Description Language Verification Methodology -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Crazee Edeee, his prices are INSANE!!! From newsfish@newsfish Thu Aug 1 00:36:04 2024 X-Received: by 10.182.52.232 with SMTP id w8mr1694674obo.40.1454510104971; Wed, 03 Feb 2016 06:35:04 -0800 (PST) X-Received: by 10.50.117.3 with SMTP id ka3mr652059igb.0.1454510104909; Wed, 03 Feb 2016 06:35:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hb3no52500igb.0!news-out.google.com!l1ni1727igd.0!nntp.google.com!hb3no52493igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Feb 2016 06:35:04 -0800 (PST) In-Reply-To: <35890525.E5B07997@chipx.co.il>#1/1> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.109.114.131; posting-account=THasBgoAAABQK7v_l4Sk7kUGUC_OUMew NNTP-Posting-Host: 134.109.114.131 References: <35890525.E5B07997@chipx.co.il>#1/1> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) From: purnachandrarao.b@gmail.com Injection-Date: Wed, 03 Feb 2016 14:35:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1336 X-Received-Body-CRC: 4181065091 Xref: news.eternal-september.org comp.lang.vhdl:4259 Hai everyone, i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command. From newsfish@newsfish Thu Aug 1 00:36:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) Date: Wed, 3 Feb 2016 10:51:45 -0500 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <35890525.E5B07997@chipx.co.il> <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 3 Feb 2016 15:48:58 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="7d86bc3aaa111443c2ea1c88ff8e1e33"; logging-data="20966"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18NtF8cdNDa+/o3PNbVCtyG" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> Cancel-Lock: sha1:KV4UlpgG66SXwnKeJXfQt3L3a2M= Xref: news.eternal-september.org comp.lang.vhdl:4260 On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote: > Hai everyone, > > i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command. You can try the assert command. When the assertion is not true it can print a report that typically includes a time stamp by the simulator. No need to actually code up the time I believe. -- Rick From newsfish@newsfish Thu Aug 1 00:36:05 2024 X-Received: by 10.182.56.233 with SMTP id d9mr3956433obq.2.1454538925423; Wed, 03 Feb 2016 14:35:25 -0800 (PST) X-Received: by 10.50.43.165 with SMTP id x5mr46316igl.9.1454538925404; Wed, 03 Feb 2016 14:35:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!o2no1943083iga.0!news-out.google.com!l1ni2072igd.0!nntp.google.com!hb3no254778igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Feb 2016 14:35:24 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.109.114.131; posting-account=THasBgoAAABQK7v_l4Sk7kUGUC_OUMew NNTP-Posting-Host: 134.109.114.131 References: <35890525.E5B07997@chipx.co.il> <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) From: purnachandrarao.b@gmail.com Injection-Date: Wed, 03 Feb 2016 22:35:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2165 X-Received-Body-CRC: 633753474 Xref: news.eternal-september.org comp.lang.vhdl:4261 On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote: > On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote: > > Hai everyone, > > > > i am working on the FPGA and my task is to show the time-stamps when= ever the signal changes as the "$monitor" verilog command shows. but i am u= sing VHDL, please help me which command in VHDL works same as "$monitor" co= mmand. >=20 > You can try the assert command. When the assertion is not true it can=20 > print a report that typically includes a time stamp by the simulator.=20 > No need to actually code up the time I believe. >=20 > --=20 >=20 > Rick thanks for the answer but the assert will use for the result which we are n= ot expecting. But i like to print the signals with time whenever the signal= changes in the given parameters. please check the $monitor verilog command= for better understanding. I want the exactly the same output in VHDL too.= ..... Purna From newsfish@newsfish Thu Aug 1 00:36:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed3-b.proxad.net!nnrp1-2.free.fr!not-for-mail Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) Newsgroups: comp.lang.vhdl References: <35890525.E5B07997@chipx.co.il> <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> From: Nicolas Matringe Date: Thu, 4 Feb 2016 00:22:03 +0100 User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 28 Message-ID: <56b28b9c$0$27846$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 04 Feb 2016 00:22:04 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1454541724 news-4.free.fr 27846 88.185.146.198:1902 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:4262 Le 03/02/2016 23:35, purnachandrarao.b@gmail.com a écrit : > On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote: >> On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote: >>> Hai everyone, >>> >>> i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command. >> >> You can try the assert command. When the assertion is not true it can >> print a report that typically includes a time stamp by the simulator. >> No need to actually code up the time I believe. >> >> -- >> >> Rick > > thanks for the answer but the assert will use for the result which we are not expecting. But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too...... Use a process: monitor : process(monitored_signal) begin report "monitored_signal has changed" severity note; end process monitor; I think messages are time-stamped by he simulator. In case they're not, adding a time stamp to the message is left as an exercise. Nicolas From newsfish@newsfish Thu Aug 1 00:36:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) Date: Wed, 3 Feb 2016 21:07:15 -0500 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <35890525.E5B07997@chipx.co.il> <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 4 Feb 2016 02:04:32 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="10826"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Ap8//mQkCAJoQ8ZEfvCC6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> Cancel-Lock: sha1:FQAWtpRmXQcjmmK37e0O4NxMBZo= Xref: news.eternal-september.org comp.lang.vhdl:4263 On 2/3/2016 5:35 PM, purnachandrarao.b@gmail.com wrote: > On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote: >> On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote: >>> Hai everyone, >>> >>> i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command. >> >> You can try the assert command. When the assertion is not true it can >> print a report that typically includes a time stamp by the simulator. >> No need to actually code up the time I believe. >> >> -- >> >> Rick > > thanks for the answer but the assert will use for the result which we are not expecting. I don't know what you mean by "the assert will use for the result which we are not expecting". If you mean the assert statement is for errors, that is not true. It does not care what you put in the assert statement. You can use "assert not signal_name'event report "signal changed" severity NOTE" to give a report each time the signal changes. "signal changed" is anything you wish to report, but I think the time is reported always. > But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too...... Rather than ask me to learn Verilog, how about you let me show you how to use VHDL? Then you can do what you want with VHDL. Asking people to spoon feed you is not a good way to get help. -- Rick From newsfish@newsfish Thu Aug 1 00:36:06 2024 X-Received: by 10.13.217.150 with SMTP id b144mr5927027ywe.26.1454579368152; Thu, 04 Feb 2016 01:49:28 -0800 (PST) X-Received: by 10.50.136.193 with SMTP id qc1mr103486igb.6.1454579368120; Thu, 04 Feb 2016 01:49:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!94no388117qgt.1!news-out.google.com!kr2ni6237igb.0!nntp.google.com!hb3no427979igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 4 Feb 2016 01:49:27 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.109.114.131; posting-account=THasBgoAAABQK7v_l4Sk7kUGUC_OUMew NNTP-Posting-Host: 134.109.114.131 References: <35890525.E5B07997@chipx.co.il> <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <17a90be5-3887-42f7-a8c4-c11bd3ce5ee0@googlegroups.com> Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) From: purnachandrarao.b@gmail.com Injection-Date: Thu, 04 Feb 2016 09:49:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4264 On Thursday, 4 February 2016 03:07:27 UTC+1, rickman wrote: > On 2/3/2016 5:35 PM, purnachandrarao.b@gmail.com wrote: > > On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote: > >> On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote: > >>> Hai everyone, > >>> > >>> i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command. > >> > >> You can try the assert command. When the assertion is not true it can > >> print a report that typically includes a time stamp by the simulator. > >> No need to actually code up the time I believe. > >> > >> -- > >> > >> Rick > > > > thanks for the answer but the assert will use for the result which we are not expecting. > > I don't know what you mean by "the assert will use for the result which > we are not expecting". If you mean the assert statement is for errors, > that is not true. It does not care what you put in the assert statement. > You can use "assert not signal_name'event report "signal changed" > severity NOTE" to give a report each time the signal changes. "signal > changed" is anything you wish to report, but I think the time is > reported always. > > > > But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too...... > > Rather than ask me to learn Verilog, how about you let me show you how > to use VHDL? Then you can do what you want with VHDL. Asking people to > spoon feed you is not a good way to get help. > > -- > > Rick sorry Rick, i don't mean that way.... i tried using the assert but i am getting the other results what i am not expecting. so i asked you in that way... i will try again, thanks for the response Purna From newsfish@newsfish Thu Aug 1 00:36:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) Date: Thu, 4 Feb 2016 09:36:41 -0500 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <35890525.E5B07997@chipx.co.il> <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> <17a90be5-3887-42f7-a8c4-c11bd3ce5ee0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 4 Feb 2016 14:33:56 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="21575"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18GTUf0rF/BcJbtZl1f7Y+t" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: <17a90be5-3887-42f7-a8c4-c11bd3ce5ee0@googlegroups.com> Cancel-Lock: sha1:AO7MRdctrHc4UPQMYLFhlg6MgdY= Xref: news.eternal-september.org comp.lang.vhdl:4265 On 2/4/2016 4:49 AM, purnachandrarao.b@gmail.com wrote: > On Thursday, 4 February 2016 03:07:27 UTC+1, rickman wrote: >> On 2/3/2016 5:35 PM, purnachandrarao.b@gmail.com wrote: >>> On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote: >>>> On 2/3/2016 9:35 AM, purnachandrarao.b@gmail.com wrote: >>>>> Hai everyone, >>>>> >>>>> i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command. >>>> >>>> You can try the assert command. When the assertion is not true it can >>>> print a report that typically includes a time stamp by the simulator. >>>> No need to actually code up the time I believe. >>>> >>>> -- >>>> >>>> Rick >>> >>> thanks for the answer but the assert will use for the result which we are not expecting. >> >> I don't know what you mean by "the assert will use for the result which >> we are not expecting". If you mean the assert statement is for errors, >> that is not true. It does not care what you put in the assert statement. >> You can use "assert not signal_name'event report "signal changed" >> severity NOTE" to give a report each time the signal changes. "signal >> changed" is anything you wish to report, but I think the time is >> reported always. >> >> >>> But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too...... >> >> Rather than ask me to learn Verilog, how about you let me show you how >> to use VHDL? Then you can do what you want with VHDL. Asking people to >> spoon feed you is not a good way to get help. >> >> -- >> >> Rick > > sorry Rick, i don't mean that way.... i tried using the assert but i am getting the other results what i am not expecting. so i asked you in that way... i will try again, thanks for the response Nicolas gives you a another answer and actually gives code. He skips the assert part of the statement and only uses the report although it has to be used in a process since report alone is only a sequential statement. Assert is either sequential or concurrent so can be used in a process or an architecture. With the example I provided you should get a report every time the signal changes. What are you seeing? -- Rick From newsfish@newsfish Thu Aug 1 00:36:07 2024 X-Received: by 10.182.43.233 with SMTP id z9mr11484755obl.38.1454663727995; Fri, 05 Feb 2016 01:15:27 -0800 (PST) X-Received: by 10.50.27.71 with SMTP id r7mr112226igg.5.1454663727976; Fri, 05 Feb 2016 01:15:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hb3no862263igb.0!news-out.google.com!l1ni3520igd.0!nntp.google.com!hb3no862254igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Feb 2016 01:15:27 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.109.114.131; posting-account=THasBgoAAABQK7v_l4Sk7kUGUC_OUMew NNTP-Posting-Host: 134.109.114.131 References: <35890525.E5B07997@chipx.co.il> <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> <17a90be5-3887-42f7-a8c4-c11bd3ce5ee0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7324436a-66b0-48cc-9157-5a1a47cb8ec0@googlegroups.com> Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) From: purnachandrarao.b@gmail.com Injection-Date: Fri, 05 Feb 2016 09:15:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4266 > Nicolas gives you a another answer and actually gives code. He skips > the assert part of the statement and only uses the report although it > has to be used in a process since report alone is only a sequential > statement. Assert is either sequential or concurrent so can be used in > a process or an architecture. > > With the example I provided you should get a report every time the > signal changes. What are you seeing? > > -- > > Rick Rick, Thank you very much for the suggestions. Finally i achieved what i want to implement. From newsfish@newsfish Thu Aug 1 00:36:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Monitoring with exact timing (Comparison Verilog/VHDL) Date: Fri, 5 Feb 2016 09:23:10 -0500 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <35890525.E5B07997@chipx.co.il> <1acfb01a-d203-4d11-98b1-4f4da3688a64@googlegroups.com> <51c8cde4-3f76-4ff9-af98-7201b9216976@googlegroups.com> <17a90be5-3887-42f7-a8c4-c11bd3ce5ee0@googlegroups.com> <7324436a-66b0-48cc-9157-5a1a47cb8ec0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 5 Feb 2016 14:20:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="17514"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX193VjddBA8vgDD6+LEc7t+/" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 In-Reply-To: <7324436a-66b0-48cc-9157-5a1a47cb8ec0@googlegroups.com> Cancel-Lock: sha1:ljybS7oqhVIKH/93RBOmzxbvrug= Xref: news.eternal-september.org comp.lang.vhdl:4267 On 2/5/2016 4:15 AM, purnachandrarao.b@gmail.com wrote: >> Nicolas gives you a another answer and actually gives code. He skips >> the assert part of the statement and only uses the report although it >> has to be used in a process since report alone is only a sequential >> statement. Assert is either sequential or concurrent so can be used in >> a process or an architecture. >> >> With the example I provided you should get a report every time the >> signal changes. What are you seeing? >> >> -- >> >> Rick > > Rick, Thank you very much for the suggestions. Finally i achieved what i want to implement. Glad it worked out. -- Rick From newsfish@newsfish Thu Aug 1 00:36:07 2024 X-Received: by 10.13.238.130 with SMTP id x124mr21403099ywe.53.1455613086461; Tue, 16 Feb 2016 00:58:06 -0800 (PST) X-Received: by 10.50.41.65 with SMTP id d1mr233193igl.9.1455613086385; Tue, 16 Feb 2016 00:58:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!w104no1339350qge.1!news-out.google.com!l1ni15234igd.0!nntp.google.com!ok5no2370134igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Feb 2016 00:58:06 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=155.69.200.110; posting-account=wJqy3goAAACDIgUikqonF0uez8Ah-JzC NNTP-Posting-Host: 155.69.200.110 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Formal models of VHDL From: Zhe Hou Injection-Date: Tue, 16 Feb 2016 08:58:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 10 Xref: news.eternal-september.org comp.lang.vhdl:4268 Hi, Does anybody know of recent developments on VHDL formal models (preferably = in proof assistants like Coq or Isabelle)? I could only find references bac= k in 1996 or earlier. I'm more interested in synthesis semantics (for synth= esising actual hardware) than event/simulation semantics (which is used by = simulation software). Many thanks. Zhe From newsfish@newsfish Thu Aug 1 00:36:08 2024 X-Received: by 10.182.236.4 with SMTP id uq4mr24477154obc.3.1456082843067; Sun, 21 Feb 2016 11:27:23 -0800 (PST) X-Received: by 10.50.171.228 with SMTP id ax4mr62648igc.5.1456082843009; Sun, 21 Feb 2016 11:27:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!ok5no4212184igc.0!news-out.google.com!kr2ni2989igb.0!nntp.google.com!ok5no4212180igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 21 Feb 2016 11:27:22 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Where is a code example on how to use a floating multiplier on FPGA for VHDL-2008? From: Weng Tianxiang Injection-Date: Sun, 21 Feb 2016 19:27:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4269 Hi, I need a full code example on how to use a floating multiplier on FPGA for VHDL-2008. What is the document name from XILINX? Jim's slides on floating multiplier are good, but not full and outdated. It was published on 2007. http://www.synthworks.com/papers/vhdl_fixedfloat_lewis_bishop_date_2007.pdf Thank you. Weng From newsfish@newsfish Thu Aug 1 00:36:08 2024 X-Received: by 10.182.120.106 with SMTP id lb10mr38955541obb.24.1456336857429; Wed, 24 Feb 2016 10:00:57 -0800 (PST) X-Received: by 10.50.43.234 with SMTP id z10mr320942igl.4.1456336857340; Wed, 24 Feb 2016 10:00:57 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y89no3889364qge.0!news-out.google.com!h70ni238qge.0!nntp.google.com!y89no3889361qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Feb 2016 10:00:56 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=130.83.112.211; posting-account=qWeBcQoAAADZuEtxI91a9TcDO_gS6kTx NNTP-Posting-Host: 130.83.112.211 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Basic question From: Elena Cososchi Injection-Date: Wed, 24 Feb 2016 18:00:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4270 Hi all, I am newly working with Cosmos OpenSSD, a real SSD Board that deploys the flash Storage Controller and the Error Correction Code on FPGA. The Software is C++, yet the firmware is VERILOG. It is my first time working with Verilog and for now I only want a small trick in order to test a hypothesis. My question is: Let's say I have assign nxt_parity[i] = cur_parity[i-1]; I want nxt_parity vector to have only 1s, independent of cur_parity. Can I do this trick in the assign? parameter PARITY_ONE = 1; assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE)); Thank you very much for any hint you may provide! best, Elena From newsfish@newsfish Thu Aug 1 00:36:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Basic question Date: Wed, 24 Feb 2016 18:39:39 -0000 (UTC) Organization: Sonic.net, Inc. Lines: 32 Message-ID: References: Injection-Date: Wed, 24 Feb 2016 18:39:39 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="12047"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+2ia/JO59MCZLD6SzLlcPB" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:9E02erhXPJp80SkMVgnIHK5Wq60= Xref: news.eternal-september.org comp.lang.vhdl:4271 In article , Elena Cososchi wrote: >Hi all, > >I am newly working with Cosmos OpenSSD, a real SSD Board that deploys >the flash Storage Controller and the Error Correction Code on FPGA. The >Software is C++, yet the firmware is VERILOG. It is my first time >working with Verilog and for now I only want a small trick in order to >test a hypothesis. > >My question is: > >Let's say I have >assign nxt_parity[i] = cur_parity[i-1]; > >I want nxt_parity vector to have only 1s, independent of cur_parity. Can >I do this trick in the assign? >parameter PARITY_ONE = 1; >assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE)); > >Thank you very much for any hint you may provide! Elena, comp.lang.verilog would be a better place to ask! In any event, yes this will work fine. Regards, Mark From newsfish@newsfish Thu Aug 1 00:36:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Basic question Date: Wed, 24 Feb 2016 14:55:33 -0500 Organization: Alacron, Inc. Lines: 56 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Feb 2016 19:54:00 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="548"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19A9uD3omZUP8VKg1BVK+ap36zF9MfCS98=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.24) Gecko/20100228 Thunderbird/2.0.0.24 Mnenhy/0.7.6.666 In-Reply-To: Cancel-Lock: sha1:TGzbdmGBGtKGaNr8Fb5rEh2n+B4= Xref: news.eternal-september.org comp.lang.vhdl:4272 Elena Cososchi wrote: > Hi all, > > I am newly working with Cosmos OpenSSD, a real SSD Board that deploys > the flash Storage Controller and the Error Correction Code on FPGA. The > Software is C++, yet the firmware is VERILOG. It is my first time > working with Verilog and for now I only want a small trick in order to > test a hypothesis. > > My question is: > > Let's say I have > assign nxt_parity[i] = cur_parity[i-1]; > > I want nxt_parity vector to have only 1s, independent of cur_parity. Can > I do this trick in the assign? > parameter PARITY_ONE = 1; > assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE)); > > Thank you very much for any hint you may provide! > > best, > Elena Perhaps you really wanted a mux like: assign nxt_parity[i] = PARITY_ONE ? 1 : cur_parity[i-1]; This is equivalent to what you wrote If nxt_parity[i] is a single bit. If nxt_parity is an array like: wire [7:0] nxt_parity [0:7]; Then the two are not equivalent. As you wrote it, if either cur_parity[i-1] is non-zero or PARITY_ONE is non-zero, then nxt_parity[i] will take the value 1, regardless of the number of bits it has. If you want to OR *each* bit of a vector with PARITY_ONE, you could replicate PARITY_ONE to the width of the vector like: parameter WIDTH = 8; parameter DEPTH = 1024; parameter PARITY_ONE = 1; wire [WIDTH-1:0] nxt_parity [0:DEPTH-1]; wire force_parity = PARITY_ONE; assign nxt_parity[i] = cur_parity[i-1] | {WIDTH{force_parity}}; equivalent to: assign nxt_parity[i] = PARITY_ONE ? {WIDTH{1'b1}} : cur_parity[i-1]; -- Gabor From newsfish@newsfish Thu Aug 1 00:36:09 2024 X-Received: by 10.140.140.18 with SMTP id 18mr16540888qhm.26.1456452090975; Thu, 25 Feb 2016 18:01:30 -0800 (PST) X-Received: by 10.50.110.41 with SMTP id hx9mr5771igb.2.1456452090904; Thu, 25 Feb 2016 18:01:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w104no3535961qge.1!news-out.google.com!pn7ni2462igb.0!nntp.google.com!ok5no4858722igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Feb 2016 18:01:30 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=68.13.240.80; posting-account=mW6eKQoAAAAiUk3wsV69Rb-VZxPKvDUh NNTP-Posting-Host: 68.13.240.80 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5b790943-b6b3-4646-a4ee-9a6294e153a1@googlegroups.com> Subject: Array Permutations in VHDL From: Star Wars Gypsy Injection-Date: Fri, 26 Feb 2016 02:01:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4273 Hello, Long time reader, first time poster.... I'm working with a Basys 2 board. My background is in desktop/software pro= gramming. I'm thinking of using these boards in a stem camp. Right now I'= m working on simple tasks. Are there any built in functions that will acce= pt an array and then output all permutations of said array? Is this even p= ossible in VHDL without creating hundreds of lines of code? The younger at= tendees of stem tend to have short attention spans. Could someone kindly point me towards a resource of all the built in functi= ons of VHDL? =20 Thanks in advance, Gypsy From newsfish@newsfish Thu Aug 1 00:36:10 2024 X-Received: by 10.182.20.195 with SMTP id p3mr220175obe.47.1456476266525; Fri, 26 Feb 2016 00:44:26 -0800 (PST) X-Received: by 10.50.43.234 with SMTP id z10mr22805igl.4.1456476266462; Fri, 26 Feb 2016 00:44:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ok5no4883171igc.0!news-out.google.com!k1ni1417igd.0!nntp.google.com!hb3no9158338igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 26 Feb 2016 00:44:26 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=138.128.222.98; posting-account=XUZW3woAAAAvqjhEa35ql7jqrM4YjoTn NNTP-Posting-Host: 138.128.222.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <049813b5-8f60-4214-b39b-afed5b97c38e@googlegroups.com> Subject: const multiplication using shift and add solve From: Yang Luo Injection-Date: Fri, 26 Feb 2016 08:44:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4274 eg1: c=a*29;-->c=a*32-a*4+a-->c=a<<5-a<<2+a; eg2: c=a*72;-->c=a*8*(8+1)-->c=(a<<3)<<3+a<<3; some papers researched this topic, but I didn't find any tools/codes to do this. Is there anybody used this way to optimazation const multiplication? From newsfish@newsfish Thu Aug 1 00:36:10 2024 X-Received: by 10.107.135.209 with SMTP id r78mr6609941ioi.19.1456492710968; Fri, 26 Feb 2016 05:18:30 -0800 (PST) X-Received: by 10.50.98.70 with SMTP id eg6mr37660igb.4.1456492710906; Fri, 26 Feb 2016 05:18:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hb3no9226668igb.0!news-out.google.com!k1ni1572igd.0!nntp.google.com!ok5no4920572igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 26 Feb 2016 05:18:30 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.143.8.131; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.143.8.131 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Basic question From: Daniel Kho Injection-Date: Fri, 26 Feb 2016 13:18:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4275 VHDL only please. :) If you really need a mux: nxt_parity(i) <= '1' when PARITY_ONE else cur_parity(i-1); If you want to force nxt_parity to all '1's, which means all bits are tied to HIGH regardless of any other signals: nxt_parity <= (others => '1'); -daniel From newsfish@newsfish Thu Aug 1 00:36:10 2024 X-Received: by 10.107.135.209 with SMTP id r78mr6639540ioi.19.1456493282793; Fri, 26 Feb 2016 05:28:02 -0800 (PST) X-Received: by 10.50.61.200 with SMTP id s8mr37912igr.3.1456493282768; Fri, 26 Feb 2016 05:28:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hb3no9228396igb.0!news-out.google.com!pn7ni2953igb.0!nntp.google.com!hb3no9228394igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 26 Feb 2016 05:28:02 -0800 (PST) In-Reply-To: <049813b5-8f60-4214-b39b-afed5b97c38e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.143.8.131; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.143.8.131 References: <049813b5-8f60-4214-b39b-afed5b97c38e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <613b27aa-7d76-41e2-92bc-af04c6e316bb@googlegroups.com> Subject: Re: const multiplication using shift and add solve From: Daniel Kho Injection-Date: Fri, 26 Feb 2016 13:28:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4276 On Friday, 26 February 2016 16:44:30 UTC+8, Yang Luo wrote: > eg1: > c=a*29;-->c=a*32-a*4+a-->c=a<<5-a<<2+a; > eg2: > c=a*72;-->c=a*8*(8+1)-->c=(a<<3)<<3+a<<3; > some papers researched this topic, but I didn't find any tools/codes to do this. > Is there anybody used this way to optimazation const multiplication? Is that a sequence of steps? Maybe you want to make a statemachine or case statement to do the sequencing. But assuming you have a and c declared as either integer, or u_signed, you could have: c <= a * 29; ... c <= (a * 32) - (a * 4) + a; -- added parentheses for clarity ... c <= (a sll (5 - a)) sll (2 + a); I may have missed something, but you get the idea. Similarly, you can do for eg2. Just rewrite the syntax in VHDL, and get familiarised a bit with hardware design. - daniel From newsfish@newsfish Thu Aug 1 00:36:11 2024 X-Received: by 10.182.47.132 with SMTP id d4mr1109706obn.40.1456493470634; Fri, 26 Feb 2016 05:31:10 -0800 (PST) X-Received: by 10.50.138.165 with SMTP id qr5mr38476igb.10.1456493470609; Fri, 26 Feb 2016 05:31:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!ok5no4922219igc.0!news-out.google.com!pn7ni2958igb.0!nntp.google.com!ok5no4922216igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 26 Feb 2016 05:31:10 -0800 (PST) In-Reply-To: <049813b5-8f60-4214-b39b-afed5b97c38e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.78.98.142; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 87.78.98.142 References: <049813b5-8f60-4214-b39b-afed5b97c38e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <864e291d-c45e-47b7-8782-1ef499eff414@googlegroups.com> Subject: Re: const multiplication using shift and add solve From: Nikolaos Kavvadias Injection-Date: Fri, 26 Feb 2016 13:31:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 38 Xref: news.eternal-september.org comp.lang.vhdl:4277 Hi! > Is there anybody used this way to optimazation const multiplication? sure, please check the kmul tool: http://github.com/nkkav/kmul You can build it in any unix-like platform. For guidance please consult the README.md that comes with it. For instance, the tool says that a * 29 would be implemented as: signed int kmul_s32_p_29 (signed int x) { signed int t0; signed int t1; signed int t2; signed int t3; signed int t4; signed int y; t0 = x; t1 = t0 << 3; t2 = t1 - x; t3 = t2 << 2; t4 = t3 + x; y = t4; return (y); } To get this result, I ran it with ./kmul.exe -mul 29 -signed -ansic Hope this helps. Best regards, Nikolaos Kavvadias From newsfish@newsfish Thu Aug 1 00:36:11 2024 X-Received: by 10.140.201.75 with SMTP id w72mr1656868qha.1.1456502377826; Fri, 26 Feb 2016 07:59:37 -0800 (PST) X-Received: by 10.50.2.36 with SMTP id 4mr65981igr.2.1456502377757; Fri, 26 Feb 2016 07:59:37 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y89no4287944qge.0!news-out.google.com!k1ni1744igd.0!nntp.google.com!hb3no9266603igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 26 Feb 2016 07:59:37 -0800 (PST) In-Reply-To: <864e291d-c45e-47b7-8782-1ef499eff414@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=138.128.222.98; posting-account=XUZW3woAAAAvqjhEa35ql7jqrM4YjoTn NNTP-Posting-Host: 138.128.222.98 References: <049813b5-8f60-4214-b39b-afed5b97c38e@googlegroups.com> <864e291d-c45e-47b7-8782-1ef499eff414@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: const multiplication using shift and add solve From: Yang Luo Injection-Date: Fri, 26 Feb 2016 15:59:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4278 thanks a lot. From newsfish@newsfish Thu Aug 1 00:36:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Array Permutations in VHDL Date: Fri, 26 Feb 2016 17:10:34 -0000 (UTC) Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <5b790943-b6b3-4646-a4ee-9a6294e153a1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Fri, 26 Feb 2016 17:10:34 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="16955"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+1YF/fvYB6rwSLPTTTNXb6" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:TpSietJQtcUFCI+yRnmkCYwwIpw= Xref: news.eternal-september.org comp.lang.vhdl:4279 Star Wars Gypsy wrote: > Hello, > > Long time reader, first time poster.... > > I'm working with a Basys 2 board. My background is in desktop/software programming. I'm thinking of using these boards in a stem camp. Right now I'm working on simple tasks. Are there any built in functions that will accept an array and then output all permutations of said array? Is this even possible in VHDL without creating hundreds of lines of code? The younger attendees of stem tend to have short attention spans. > > Could someone kindly point me towards a resource of all the built in functions of VHDL? You're thinking about VHDL all wrong, because VHDL is a hardware description language. Not only doesn't the function you ask for exist as a standard part of the language, the concept barely maps onto hardware. You haven't described how the data would get in, or how the data would get out. In software, those are just parameters. In hardware you need to construct the physical busses that move that data. Is the data in an "array" coming in sequentially, one data element per cycle, or broadside? If sequentially, does the packet have a fixed length, or just a maximum one? Are you using any standard streaming interface (AXI, Avalon-ST, etc), or making one up ad-hoc? Hardware doesn't do software, hardware does hardware. That statement is only true insofar as it is, but the closest analogue to what you're talking about would be something like a hardware accelerator for permutations, where you'd write the array in over PCI Express, and the FPGA would DMA back all permutations to a memory block previously agreed upon in the driver, which you'd also have to write. All so that you can manipulate boring data. So, don't do that. Certainly not for a camp. Light LEDs. Play sounds on speakers. Start with the basics: A) While I push the button, the LED is on. B) When I push the button, the LED comes on. It stays on for a full second after I release it. C) When I push the button, the LED toggles state. (Be sure to debounce the button). D) When I push the button the LED spends a second ramping up in brightness. It stays at full brightness while I hold the button, then ramps back down in a second when I let go. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:12 2024 X-Received: by 10.140.252.131 with SMTP id x125mr1312191qhc.12.1457004316746; Thu, 03 Mar 2016 03:25:16 -0800 (PST) X-Received: by 10.50.25.196 with SMTP id e4mr146984igg.8.1457004316676; Thu, 03 Mar 2016 03:25:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y89no5294527qge.0!news-out.google.com!k1ni7373igd.0!nntp.google.com!ok5no5833429igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Mar 2016 03:25:16 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=138.128.222.98; posting-account=XUZW3woAAAAvqjhEa35ql7jqrM4YjoTn NNTP-Posting-Host: 138.128.222.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4a39b7a1-b759-4b92-b494-801bcf6aeac8@googlegroups.com> Subject: mxn bit mulplication maps how many gates? From: Yang Luo Injection-Date: Thu, 03 Mar 2016 11:25:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4280 in asic, given a 8x8b unsigned multiplication, how can i estimate the gates using design compiler? Is there an experient value about mxn bit mul to gates number? From newsfish@newsfish Thu Aug 1 00:36:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: mxn bit mulplication maps how many gates? Date: Thu, 3 Mar 2016 11:44:41 -0500 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <4a39b7a1-b759-4b92-b494-801bcf6aeac8@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 3 Mar 2016 16:41:44 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="12713"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+vIVN5gtUM/iTpmcWvaTnu" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 In-Reply-To: <4a39b7a1-b759-4b92-b494-801bcf6aeac8@googlegroups.com> Cancel-Lock: sha1:DjtggSou8t93jG5ZUiGHlj3oOWo= Xref: news.eternal-september.org comp.lang.vhdl:4281 On 3/3/2016 6:25 AM, Yang Luo wrote: > in asic, given a 8x8b unsigned multiplication, how can i estimate the gates using design compiler? > Is there an experient value about mxn bit mul to gates number? If both inputs are variables, the number of gates is well defined. You know what half and full adders are, right? Try synthesizing a few examples in your favorite tool and measure the gates. It should be very easy to come up with a general formula. -- Rick From newsfish@newsfish Thu Aug 1 00:36:13 2024 X-Received: by 10.66.146.10 with SMTP id sy10mr4094119pab.24.1457055189219; Thu, 03 Mar 2016 17:33:09 -0800 (PST) X-Received: by 10.50.85.107 with SMTP id g11mr78112igz.7.1457055189136; Thu, 03 Mar 2016 17:33:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hb3no11151795igb.0!news-out.google.com!pn7ni8967igb.0!nntp.google.com!ok5no5937780igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Mar 2016 17:33:08 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=138.128.222.98; posting-account=XUZW3woAAAAvqjhEa35ql7jqrM4YjoTn NNTP-Posting-Host: 138.128.222.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54307f27-6ca3-4e89-a27b-7336ae6ab954@googlegroups.com> Subject: recommend some eda tool groups From: Yang Luo Injection-Date: Fri, 04 Mar 2016 01:33:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4282 I'm using Design Complier for synthesis, it belongs to synopsys company. I = know solvnet is forum for DC, But it need an account which bought DC. How c= an I find some groups about DC in google group? I searched some key words (= DC, design compiler, synopsys, EDA tools) in google group, but didn't get r= esult. Can you recommend some google groups or forums about EDA tools? From newsfish@newsfish Thu Aug 1 00:36:13 2024 X-Received: by 10.182.233.170 with SMTP id tx10mr5082866obc.18.1457079995360; Fri, 04 Mar 2016 00:26:35 -0800 (PST) X-Received: by 10.50.142.39 with SMTP id rt7mr95969igb.8.1457079995263; Fri, 04 Mar 2016 00:26:35 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hb3no11223927igb.0!news-out.google.com!pn7ni9240igb.0!nntp.google.com!hb3no11223911igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Mar 2016 00:26:34 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <10c7bf3e-f4cb-4839-9521-6192ecc02b4e@googlegroups.com> Subject: Advanced VHDL Verification - Made simple - For anyone From: espen.tallaksen@bitvis.no Injection-Date: Fri, 04 Mar 2016 08:26:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4283 VHDL testbenches very often need better structuring. We should strive for overview, modifiability, extendibility, maintainability and re-use. We are now posting 3 very easy to understand articles on LinkedIn on how you can achieve this, and of course also increase efficiency and quality significantly. (Using Free, Open source code only) Please check out: https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyone-espen-tallaksen?trk=prof-post From newsfish@newsfish Thu Aug 1 00:36:13 2024 X-Received: by 10.140.101.242 with SMTP id u105mr7241197qge.12.1457121678916; Fri, 04 Mar 2016 12:01:18 -0800 (PST) X-Received: by 10.50.88.3 with SMTP id bc3mr25915igb.6.1457121678863; Fri, 04 Mar 2016 12:01:18 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w104no4900958qge.1!news-out.google.com!k1ni8699igd.0!nntp.google.com!ok5no6079700igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Mar 2016 12:01:18 -0800 (PST) In-Reply-To: <32662D91.4487@mira.e-technik.uni-dortmund.de>#1/1> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2600:8802:4000:407:7414:b698:aa42:5cfe; posting-account=GJHQQgoAAABbfH7hEh5xjdaHyJJr_rGN NNTP-Posting-Host: 2600:8802:4000:407:7414:b698:aa42:5cfe References: <3263AF0E.27B965D4@redline.ru> <32662D91.4487@mira.e-technik.uni-dortmund.de>#1/1> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Looking for VHDL model of 386 or 486 processor From: dylanbrophy@gmail.com Injection-Date: Fri, 04 Mar 2016 20:01:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4284 On Thursday, October 17, 1996 at 12:00:00 AM UTC-7, Edwin Naroska wrote: > Hi, > > Vasily A.Syngaevsky wrote: > > > > Hi everybody ! > > Does anybody know where to find free or purchase > > VHDL model of 386 or 486 microprocessor ? > > Thanks in advance, > > Vasily > > The following links point to some servers containing "non commercial" > VHDL models. Note, there may be some limitations and restrictions > concerning the use of this software. > > MSU: > http://www.erc.msstate.edu/mpl/rassp/modeling/html/modeling.html > Free Modeling Foundation (FMF): > http://vhdl.org/vi/fmf/ > The Hamburg VHDL archive: > http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html > RASSP www site: > http://rassp.scra.org/information/public-vhdl/models/models.html > University of Strasbourg: > http://erm1.u-strasbg.fr/db/ or ftp://erm1.u-strasbg.fr/pub/vhdl/ > Doulos High Level Design Web site; Monthly-updated Original Models > (developed by Doulos): > http://www.doulos.co.uk/informationresource/index.htm > A pipelined version of the DLX RISC processor (with some restrictions), > by Neil Shipp: > http://www.pads.uwaterloo.ca/~nlshipp/dlx > EDIF LPM - Library of Parameterized Modules: > http://www.edif.org/ > > Here are some links to commercial model sites. > > Viewlogic's on-line CAE/CAD model library information center: > http://www.viewlogic.com/ModelSite/ > Virtual Chips, Inc.: > http://www.vchips.com/ > 3Soft's Web Page: > http://www.3soft.com > > For other commercial model vendors see FAQ part 3 products & services at > http://www.vhdl.org/vi/comp.lang.vhdl/ > > Bye,... > Edwin > -- > ----------------------------------------------------------- > Edwin Naroska > Computer Engineering Institute > (Lehrstuhl fuer Datenverarbeitungssysteme) > University of Dortmund > 44221 Dortmund > Germany > > email: edwin@ds.e-technik.uni-dortmund.de > phone: ++49 231 7552406 > fax: ++49 231 7553251 > ----------------------------------------------------------- Heads up- most of your links dont work From newsfish@newsfish Thu Aug 1 00:36:14 2024 X-Received: by 10.66.142.135 with SMTP id rw7mr7390135pab.20.1457122170816; Fri, 04 Mar 2016 12:09:30 -0800 (PST) X-Received: by 10.50.98.70 with SMTP id eg6mr27287igb.4.1457122170727; Fri, 04 Mar 2016 12:09:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hb3no11405473igb.0!news-out.google.com!k1ni8732igd.0!nntp.google.com!hb3no11405465igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Mar 2016 12:09:30 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <3263AF0E.27B965D4@redline.ru> <32662D91.4487@mira.e-technik.uni-dortmund.de>#1/1> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <04d839b5-b41a-4ccc-b9d3-a756da3f070d@googlegroups.com> Subject: Re: Looking for VHDL model of 386 or 486 processor From: KJ Injection-Date: Fri, 04 Mar 2016 20:09:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4285 On Friday, March 4, 2016 at 3:01:23 PM UTC-5, dylan...@gmail.com wrote: > > Heads up- most of your links dont work Wow, that's a shocker. Links that were posted 20 years ago don't work. Whooda thunk? From newsfish@newsfish Thu Aug 1 00:36:14 2024 X-Received: by 10.140.28.71 with SMTP id 65mr7312818qgy.1.1457122734101; Fri, 04 Mar 2016 12:18:54 -0800 (PST) X-Received: by 10.50.43.194 with SMTP id y2mr27164igl.9.1457122734016; Fri, 04 Mar 2016 12:18:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!y89no5558947qge.0!news-out.google.com!k1ni8732igd.0!nntp.google.com!hb3no11407874igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Mar 2016 12:18:53 -0800 (PST) In-Reply-To: <54307f27-6ca3-4e89-a27b-7336ae6ab954@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <54307f27-6ca3-4e89-a27b-7336ae6ab954@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: recommend some eda tool groups From: michael6866 Injection-Date: Fri, 04 Mar 2016 20:18:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 8 Xref: news.eternal-september.org comp.lang.vhdl:4286 On Thursday, March 3, 2016 at 8:33:12 PM UTC-5, Yang Luo wrote: > I'm using Design Complier for synthesis, it belongs to synopsys company. = I know solvnet is forum for DC, But it need an account which bought DC. How= can I find some groups about DC in google group? I searched some key words= (DC, design compiler, synopsys, EDA tools) in google group, but didn't get= result. > Can you recommend some google groups or forums about EDA tools? Are you saying you didn't buy DC but you were able to use it anyhow? From newsfish@newsfish Thu Aug 1 00:36:14 2024 X-Received: by 10.66.122.101 with SMTP id lr5mr8635350pab.3.1457151133571; Fri, 04 Mar 2016 20:12:13 -0800 (PST) X-Received: by 10.50.66.236 with SMTP id i12mr57212igt.7.1457151133494; Fri, 04 Mar 2016 20:12:13 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ok5no6120019igc.0!news-out.google.com!k1ni9052igd.0!nntp.google.com!hb3no11486918igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Mar 2016 20:12:12 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=138.128.222.98; posting-account=XUZW3woAAAAvqjhEa35ql7jqrM4YjoTn NNTP-Posting-Host: 138.128.222.98 References: <54307f27-6ca3-4e89-a27b-7336ae6ab954@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: recommend some eda tool groups From: Yang Luo Injection-Date: Sat, 05 Mar 2016 04:12:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4287 I didn't buy it, my company buy it. but I don't have an account. From newsfish@newsfish Thu Aug 1 00:36:15 2024 X-Received: by 10.140.234.10 with SMTP id f10mr10321438qhc.5.1457231984256; Sat, 05 Mar 2016 18:39:44 -0800 (PST) X-Received: by 10.50.78.131 with SMTP id b3mr112497igx.5.1457231984182; Sat, 05 Mar 2016 18:39:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!w104no5100353qge.1!news-out.google.com!pn7ni1325igb.0!nntp.google.com!ok5no6243168igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Mar 2016 18:39:43 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=182.54.220.115; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 182.54.220.115 References: <54307f27-6ca3-4e89-a27b-7336ae6ab954@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: recommend some eda tool groups From: Daniel Kho Injection-Date: Sun, 06 Mar 2016 02:39:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 7 X-Received-Bytes: 1725 X-Received-Body-CRC: 3203285346 Xref: news.eternal-september.org comp.lang.vhdl:4288 On Saturday, 5 March 2016 12:12:17 UTC+8, Yang Luo wrote: > I didn't buy it, my company buy it. but I don't have an account. You can create a SolvNet account from Synopsys' website and specify your employer's details during the registration process. Oh yes, but first you need to ask for some Site ID from whoever is managing the Synopsys licenses, because the website needs it. This is as far as I remember. -dan From newsfish@newsfish Thu Aug 1 00:36:15 2024 X-Received: by 10.31.152.208 with SMTP id a199mr16635192vke.4.1457358053956; Mon, 07 Mar 2016 05:40:53 -0800 (PST) X-Received: by 10.50.25.196 with SMTP id e4mr190424igg.8.1457358053911; Mon, 07 Mar 2016 05:40:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w104no5388695qge.1!news-out.google.com!k1ni11499igd.0!nntp.google.com!ok5no6506618igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Mar 2016 05:40:53 -0800 (PST) In-Reply-To: <10c7bf3e-f4cb-4839-9521-6192ecc02b4e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <10c7bf3e-f4cb-4839-9521-6192ecc02b4e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9b8b4101-7507-441d-ab07-77ea3b8959c7@googlegroups.com> Subject: Re: Advanced VHDL Verification - Made simple - For anyone From: Thomas Stanka Injection-Date: Mon, 07 Mar 2016 13:40:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4289 Am Freitag, 4. M=E4rz 2016 09:26:39 UTC+1 schrieb espen.t...@bitvis.no: > VHDL testbenches very often need better structuring. We should strive for= overview, modifiability, extendibility, maintainability and re-use.=20 >=20 > We are now posting 3 very easy to understand articles on LinkedIn on how = you can achieve this, and of course also increase efficiency and quality si= gnificantly. (Using Free, Open source code only) >=20 > Please check out: https://www.linkedin.com/pulse/advanced-vhdl-verificati= on-made-simple-anyone-espen-tallaksen?trk=3Dprof-post How about posting here? Or do you just like to fish for linked-in clicks? From newsfish@newsfish Thu Aug 1 00:36:15 2024 X-Received: by 10.140.28.71 with SMTP id 65mr20148841qgy.1.1457422995295; Mon, 07 Mar 2016 23:43:15 -0800 (PST) X-Received: by 10.50.138.165 with SMTP id qr5mr287466igb.10.1457422995256; Mon, 07 Mar 2016 23:43:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w104no5535133qge.1!news-out.google.com!k1ni12283igd.0!nntp.google.com!hb3no12432193igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Mar 2016 23:43:14 -0800 (PST) In-Reply-To: <9b8b4101-7507-441d-ab07-77ea3b8959c7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: <10c7bf3e-f4cb-4839-9521-6192ecc02b4e@googlegroups.com> <9b8b4101-7507-441d-ab07-77ea3b8959c7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <28ba0990-794f-40ea-bc41-67e641a7fed3@googlegroups.com> Subject: Re: Advanced VHDL Verification - Made simple - For anyone From: espen.tallaksen@bitvis.no Injection-Date: Tue, 08 Mar 2016 07:43:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4290 It was my initial intention to post the whole thing here (in addition to Li= nkedIn and our own web site). This free and open source VHDL verification f= ramework has received great feedback from VHDL developers, and I assumed it= would also be of interest to developers in this forum. I tried to find a w= ay of including figures here - as figures make things very much easier to u= nderstand, but it doesn't seem to be possible(?) The alternative was then t= o post it on bitvis.no. I thought I chose the lesser evil. From newsfish@newsfish Thu Aug 1 00:36:16 2024 X-Received: by 10.182.75.196 with SMTP id e4mr24873491obw.36.1457517719246; Wed, 09 Mar 2016 02:01:59 -0800 (PST) X-Received: by 10.50.110.41 with SMTP id hx9mr444960igb.2.1457517719214; Wed, 09 Mar 2016 02:01:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!nt3no89050igb.0!news-out.google.com!pn7ni4673igb.0!nntp.google.com!nt3no89039igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Mar 2016 02:01:58 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Simplify handling of SW accessible registers in FPGA From: espen.tallaksen@bitvis.no Injection-Date: Wed, 09 Mar 2016 10:01:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4291 Save lots of work - Auto-generate register related code and documentation, and - Keep SW, FPGA and Documentation synchronized Register Wizard is now free :-) Register Wizard is now released as a freeware to generate 'C' code, VHDL code and documentation from a single register definition file. This allows a major efficiency boost for developing systems with software accessible registers, - and equally important - a simple way of keeping your Software, FPGA and Documentation synchronized. The register definition file is written as normal text in the JSON file format. From this file you can automatically generate the following: - 'C' header file for all registers and their addresses - VHDL package for all registers and their addresses - Full VHDL simple processor interface for register access (May easily be wrapped to Avalon or AXI4-lite) - Self-checking VHDL testbench for the processor interface (Using UVVM Utility Library) - Documentation in the form of a register map and register description in the Office Open XML format for simple inclusion in MS Word. This also means that specification changes are handled in a very structured manner - just by extending or modifying the register definition file and re-generating all the above. The tool and usage is of course properly documented - including a tutorial and example, - and may be downloaded from our web-site: http://bitvis.no/products/register_wizard/ Enjoy :-) And please send us feedback on potential improvements for your applications. From newsfish@newsfish Thu Aug 1 00:36:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Wed, 9 Mar 2016 12:09:52 -0500 Organization: A noiseless patient Spider Lines: 36 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 9 Mar 2016 17:06:51 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="10852"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18u1Hr4IL59K0L6TckfmPXp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 In-Reply-To: Cancel-Lock: sha1:bBwswM/0Sb+qz/A9RLRLpiXGMdw= Xref: news.eternal-september.org comp.lang.vhdl:4292 On 3/9/2016 5:01 AM, espen.tallaksen@bitvis.no wrote: > Save lots of work > - Auto-generate register related code and documentation, and > - Keep SW, FPGA and Documentation synchronized > Register Wizard is now free :-) > > Register Wizard is now released as a freeware to generate 'C' code, VHDL code and documentation from a single register definition file. > This allows a major efficiency boost for developing systems with software accessible registers, - and equally important - a simple way of keeping your Software, FPGA and Documentation synchronized. > > The register definition file is written as normal text in the JSON file format. From this file you can automatically generate the following: > > - 'C' header file for all registers and their addresses > - VHDL package for all registers and their addresses > - Full VHDL simple processor interface for register access > (May easily be wrapped to Avalon or AXI4-lite) > - Self-checking VHDL testbench for the processor interface > (Using UVVM Utility Library) > - Documentation in the form of a register map and register description > in the Office Open XML format for simple inclusion in MS Word. > > This also means that specification changes are handled in a very structured manner - just by extending or modifying the register definition file and re-generating all the above. > > The tool and usage is of course properly documented - including a tutorial and example, - and may be downloaded from our web-site: http://bitvis.no/products/register_wizard/ > > Enjoy :-) > And please send us feedback on potential improvements for your applications. I'm a bit unclear on this. What is the assumption on how the registers are created in the VHDL code. Is this a block RAM or discrete registers in the fabric? I can see providing a C header file for a memory mapped register bank, but how can you define the registers in the VHDL if you don't know how they need to be implemented? -- Rick From newsfish@newsfish Thu Aug 1 00:36:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Wed, 9 Mar 2016 17:36:17 -0000 (UTC) Organization: A noiseless patient Spider Lines: 67 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Wed, 9 Mar 2016 17:36:17 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="17763"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199r+lFucLJe8CrVfv4dbpH" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:hnOTgpveN8QDaJQF+XBC0GZDw6Y= Xref: news.eternal-september.org comp.lang.vhdl:4293 rickman wrote: > On 3/9/2016 5:01 AM, espen.tallaksen@bitvis.no wrote: >> Save lots of work >> - Auto-generate register related code and documentation, and >> - Keep SW, FPGA and Documentation synchronized >> Register Wizard is now free :-) >> >> Register Wizard is now released as a freeware to generate 'C' code, VHDL code and documentation from a single register definition file. >> This allows a major efficiency boost for developing systems with software accessible registers, - and equally important - a simple way of keeping your Software, FPGA and Documentation synchronized. >> >> The register definition file is written as normal text in the JSON file format. From this file you can automatically generate the following: >> >> - 'C' header file for all registers and their addresses >> - VHDL package for all registers and their addresses >> - Full VHDL simple processor interface for register access >> (May easily be wrapped to Avalon or AXI4-lite) >> - Self-checking VHDL testbench for the processor interface >> (Using UVVM Utility Library) >> - Documentation in the form of a register map and register description >> in the Office Open XML format for simple inclusion in MS Word. >> >> This also means that specification changes are handled in a very structured manner - just by extending or modifying the register definition file and re-generating all the above. >> >> The tool and usage is of course properly documented - including a tutorial and example, - and may be downloaded from our web-site: http://bitvis.no/products/register_wizard/ >> >> Enjoy :-) >> And please send us feedback on potential improvements for your applications. > > I'm a bit unclear on this. What is the assumption on how the registers > are created in the VHDL code. Is this a block RAM or discrete registers > in the fabric? I can see providing a C header file for a memory mapped > register bank, but how can you define the registers in the VHDL if you > don't know how they need to be implemented? > Haven't actually looked at what the bitvis thing is up to, but I've implemented a similar system here (though I'm less than thrilled with the way it all came together). In mine, each register gets its own record type associated with it, made up of unsigned/signed/std_logic/std_logic_vector based on the register definition file, and there are conversion functions for translating records to/from the data bus std_logic_vector, all of which goes into a package that I import into the module that actually does the work. So that gives you automation of defining registers. I never got around to the next logical step, auto-generating the code that defines the "register file" as a record of all the subrecords, and handles the bus transactions against that record in some kind of DoBusTransaction(regfile) call. It would be straightforward to do if cumbersome. It's still up to the designer to actually make those registers do things, but lots of things follow some very basic patterns. Read-only status registers are always updated before DoBusTransaction. Write-only registers get their values used and then blanked after DoBusTransaction. And so on. There's still plenty on the designer's plate, but a ton of the crappy boilerplate can be automated, while generating C headers and pretty documentation along the way. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Wed, 9 Mar 2016 13:00:20 -0500 Organization: A noiseless patient Spider Lines: 78 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 9 Mar 2016 17:57:20 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="23072"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19kmU6xNNHuRLRi1Gkr29Ah" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 In-Reply-To: Cancel-Lock: sha1:jBWQheuuYsMDtA8rH9aSCU7wL6U= Xref: news.eternal-september.org comp.lang.vhdl:4294 On 3/9/2016 12:36 PM, Rob Gaddi wrote: > rickman wrote: > >> On 3/9/2016 5:01 AM, espen.tallaksen@bitvis.no wrote: >>> Save lots of work >>> - Auto-generate register related code and documentation, and >>> - Keep SW, FPGA and Documentation synchronized >>> Register Wizard is now free :-) >>> >>> Register Wizard is now released as a freeware to generate 'C' code, VHDL code and documentation from a single register definition file. >>> This allows a major efficiency boost for developing systems with software accessible registers, - and equally important - a simple way of keeping your Software, FPGA and Documentation synchronized. >>> >>> The register definition file is written as normal text in the JSON file format. From this file you can automatically generate the following: >>> >>> - 'C' header file for all registers and their addresses >>> - VHDL package for all registers and their addresses >>> - Full VHDL simple processor interface for register access >>> (May easily be wrapped to Avalon or AXI4-lite) >>> - Self-checking VHDL testbench for the processor interface >>> (Using UVVM Utility Library) >>> - Documentation in the form of a register map and register description >>> in the Office Open XML format for simple inclusion in MS Word. >>> >>> This also means that specification changes are handled in a very structured manner - just by extending or modifying the register definition file and re-generating all the above. >>> >>> The tool and usage is of course properly documented - including a tutorial and example, - and may be downloaded from our web-site: http://bitvis.no/products/register_wizard/ >>> >>> Enjoy :-) >>> And please send us feedback on potential improvements for your applications. >> >> I'm a bit unclear on this. What is the assumption on how the registers >> are created in the VHDL code. Is this a block RAM or discrete registers >> in the fabric? I can see providing a C header file for a memory mapped >> register bank, but how can you define the registers in the VHDL if you >> don't know how they need to be implemented? >> > > Haven't actually looked at what the bitvis thing is up to, but I've > implemented a similar system here (though I'm less than thrilled with > the way it all came together). > > In mine, each register gets its own record type associated with it, > made up of unsigned/signed/std_logic/std_logic_vector based on the > register definition file, and there are conversion functions for > translating records to/from the data bus std_logic_vector, all of which > goes into a package that I import into the module that actually does the > work. I'm not clear on what you are describing here. Sounds like you are substituting an HDL definition of a register with a configuration file definition of a register. > So that gives you automation of defining registers. I never > got around to the next logical step, auto-generating the code that > defines the "register file" as a record of all the subrecords, > and handles the bus transactions against that record in some kind of > DoBusTransaction(regfile) call. It would be straightforward to do > if cumbersome. Are you talking about the CPU's view of the register file? I'm not clear on what you mean my "defining registers". They have to be defined in HDL both for the CPU and for the hardware as well as for the CPU code. > It's still up to the designer to actually make those registers do > things, but lots of things follow some very basic patterns. Read-only > status registers are always updated before DoBusTransaction. Write-only > registers get their values used and then blanked after > DoBusTransaction. And so on. There's still plenty on the designer's > plate, but a ton of the crappy boilerplate can be automated, while > generating C headers and pretty documentation along the way. Which boiler plate is being automated, the register signal declarations? -- Rick From newsfish@newsfish Thu Aug 1 00:36:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Wed, 9 Mar 2016 18:43:55 -0000 (UTC) Organization: A noiseless patient Spider Lines: 138 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Wed, 9 Mar 2016 18:43:55 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="1946"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Atvg0tqFQQW0NGN2tf87o" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:tq8IQVUdPJN+SMl7d5lfSWYGmXM= Xref: news.eternal-september.org comp.lang.vhdl:4295 rickman wrote: > On 3/9/2016 12:36 PM, Rob Gaddi wrote: >> rickman wrote: >>> >>> I'm a bit unclear on this. What is the assumption on how the registers >>> are created in the VHDL code. Is this a block RAM or discrete registers >>> in the fabric? I can see providing a C header file for a memory mapped >>> register bank, but how can you define the registers in the VHDL if you >>> don't know how they need to be implemented? >>> >> >> Haven't actually looked at what the bitvis thing is up to, but I've >> implemented a similar system here (though I'm less than thrilled with >> the way it all came together). >> >> In mine, each register gets its own record type associated with it, >> made up of unsigned/signed/std_logic/std_logic_vector based on the >> register definition file, and there are conversion functions for >> translating records to/from the data bus std_logic_vector, all of which >> goes into a package that I import into the module that actually does the >> work. > > I'm not clear on what you are describing here. Sounds like you are > substituting an HDL definition of a register with a configuration file > definition of a register. > Exactly. I (hand)write an XML file defining all the registers in a peripheral, then I cook it down and get a VHDL package with definitions such as: constant BUSSTATE_ADDR : t_addr := 16#026#; type t_BUSSTATE is record IACKIN : std_logic; IRQ : std_logic_vector(6 downto 0); DTACK : std_logic; BERR : std_logic; RETRY : std_logic; end record t_BUSSTATE; pure function BUSSTATE_TO_WORD(dat : t_BUSSTATE) return t_word is variable ret : t_word; begin ret := (others => '0'); ret(0) := dat.IACKIN; ret(7 downto 1) := std_logic_vector(dat.IRQ); ret(8) := dat.DTACK; ret(9) := dat.BERR; ret(10) := dat.RETRY; return ret; end function BUSSTATE_TO_WORD; pure function WORD_TO_BUSSTATE(dat : t_word) return t_BUSSTATE is variable ret : t_BUSSTATE; begin ret.IACKIN := dat(0); ret.IRQ := std_logic_vector(dat(7 downto 1)); ret.DTACK := dat(8); ret.BERR := dat(9); ret.RETRY := dat(10); return ret; end function WORD_TO_BUSSTATE; procedure UPDATE_BUSSTATE(reg : inout t_BUSSTATE; nd : in t_word; be : in t_be) is variable tmp : t_word; begin tmp := BUSSTATE_TO_WORD(reg); for i in be'range loop if (be(i) = '1') then tmp(i*8 + 7 downto i*8) := nd(i*8+7 downto i*8); end if; end loop; reg := WORD_TO_BUSSTATE(tmp); end procedure UPDATE_BUSSTATE; The generated VHDL file I sliced those out of is, as an example, 2500 lines long. Those translation functions are responsible for making sure that everyone agrees which bit of the word represents BERR. It also cogenerates a C header file with a struct that puts uint32_t BUSSTATE (and all the other registers in the peripheral) at the correct location, and contains /****************************************************************************** * BUSSTATE Field Descriptions *****************************************************************************/ /* CTLREG_BUSSTATE_RETRY - The current state of the (active-low) RETRY * line. */ #define CTLREG_BUSSTATE_RETRY_LSB (10) #define CTLREG_BUSSTATE_RETRY (0x00000400u) /* CTLREG_BUSSTATE_BERR - The current state of the (active-low) BERR line. */ #define CTLREG_BUSSTATE_BERR_LSB (9) #define CTLREG_BUSSTATE_BERR (0x00000200u) /* CTLREG_BUSSTATE_DTACK - The current state of the (active-low) DTACK * line. */ #define CTLREG_BUSSTATE_DTACK_LSB (8) #define CTLREG_BUSSTATE_DTACK (0x00000100u) /* CTLREG_BUSSTATE_IRQ - The current state of the (active-low) IRQ lines 7 * through 1. */ #define CTLREG_BUSSTATE_IRQ_LSB (1) #define CTLREG_BUSSTATE_IRQ_MASK (0x000000FEu) #define CTLREG_BUSSTATE_IRQ(x) ((x) << CTLREG_BUSSTATE_IRQ_LSB) /* CTLREG_BUSSTATE_IACKIN - The current state of the (active-low) IACKIN * line. */ #define CTLREG_BUSSTATE_IACKIN_LSB (0) #define CTLREG_BUSSTATE_IACKIN (0x00000001u) It also writes out HTML documentation where the bitfields of a BUSSTATE are shown as a 4 row table (1,3 are bit numbers, 2,4 are fields) followed by a bulleted list with the descriptive text. And the most important part is that every time I type "make", I am guaranteed that the VHDL, C, and HTML are all in sync. I still need to go around synchronizing all of the logic, but since cutting over to this system I have NEVER got the wrong bit in the wrong place. Because that's a stupid mistake in copying data redundantly, which is exactly the sort of thing computers are better at than we are. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Wed, 9 Mar 2016 14:30:09 -0500 Organization: A noiseless patient Spider Lines: 145 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 9 Mar 2016 19:27:08 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="13270"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19gLE3Hxvut9Em3shsODXKh" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 In-Reply-To: Cancel-Lock: sha1:2lU0l3WRrDPyS/hAG0/nRs3zNb0= Xref: news.eternal-september.org comp.lang.vhdl:4296 On 3/9/2016 1:43 PM, Rob Gaddi wrote: > rickman wrote: > >> On 3/9/2016 12:36 PM, Rob Gaddi wrote: >>> rickman wrote: >>>> >>>> I'm a bit unclear on this. What is the assumption on how the registers >>>> are created in the VHDL code. Is this a block RAM or discrete registers >>>> in the fabric? I can see providing a C header file for a memory mapped >>>> register bank, but how can you define the registers in the VHDL if you >>>> don't know how they need to be implemented? >>>> >>> >>> Haven't actually looked at what the bitvis thing is up to, but I've >>> implemented a similar system here (though I'm less than thrilled with >>> the way it all came together). >>> >>> In mine, each register gets its own record type associated with it, >>> made up of unsigned/signed/std_logic/std_logic_vector based on the >>> register definition file, and there are conversion functions for >>> translating records to/from the data bus std_logic_vector, all of which >>> goes into a package that I import into the module that actually does the >>> work. >> >> I'm not clear on what you are describing here. Sounds like you are >> substituting an HDL definition of a register with a configuration file >> definition of a register. >> > > Exactly. I (hand)write an XML file defining all the registers in a > peripheral, then I cook it down and get a VHDL package with definitions > such as: > > constant BUSSTATE_ADDR : t_addr := 16#026#; > > type t_BUSSTATE is record > IACKIN : std_logic; > IRQ : std_logic_vector(6 downto 0); > DTACK : std_logic; > BERR : std_logic; > RETRY : std_logic; > end record t_BUSSTATE; > > pure function BUSSTATE_TO_WORD(dat : t_BUSSTATE) return t_word is > variable ret : t_word; > begin > ret := (others => '0'); > ret(0) := dat.IACKIN; > ret(7 downto 1) := std_logic_vector(dat.IRQ); > ret(8) := dat.DTACK; > ret(9) := dat.BERR; > ret(10) := dat.RETRY; > return ret; > end function BUSSTATE_TO_WORD; > > pure function WORD_TO_BUSSTATE(dat : t_word) return t_BUSSTATE is > variable ret : t_BUSSTATE; > begin > ret.IACKIN := dat(0); > ret.IRQ := std_logic_vector(dat(7 downto 1)); > ret.DTACK := dat(8); > ret.BERR := dat(9); > ret.RETRY := dat(10); > return ret; > end function WORD_TO_BUSSTATE; > > procedure UPDATE_BUSSTATE(reg : inout t_BUSSTATE; nd : in t_word; be : in t_be) is > variable tmp : t_word; > begin > tmp := BUSSTATE_TO_WORD(reg); > for i in be'range loop > if (be(i) = '1') then > tmp(i*8 + 7 downto i*8) := nd(i*8+7 downto i*8); > end if; > end loop; > reg := WORD_TO_BUSSTATE(tmp); > end procedure UPDATE_BUSSTATE; > > The generated VHDL file I sliced those out of is, as an example, 2500 > lines long. Those translation functions are responsible for making sure > that everyone agrees which bit of the word represents BERR. > > It also cogenerates a C header file with a struct that puts uint32_t > BUSSTATE (and all the other registers in the peripheral) at the correct > location, and contains > > /****************************************************************************** > * BUSSTATE Field Descriptions > *****************************************************************************/ > > /* CTLREG_BUSSTATE_RETRY - The current state of the (active-low) RETRY > * line. > */ > > #define CTLREG_BUSSTATE_RETRY_LSB (10) > #define CTLREG_BUSSTATE_RETRY (0x00000400u) > > /* CTLREG_BUSSTATE_BERR - The current state of the (active-low) BERR line. > */ > > #define CTLREG_BUSSTATE_BERR_LSB (9) > #define CTLREG_BUSSTATE_BERR (0x00000200u) > > /* CTLREG_BUSSTATE_DTACK - The current state of the (active-low) DTACK > * line. > */ > > #define CTLREG_BUSSTATE_DTACK_LSB (8) > #define CTLREG_BUSSTATE_DTACK (0x00000100u) > > /* CTLREG_BUSSTATE_IRQ - The current state of the (active-low) IRQ lines 7 > * through 1. > */ > > #define CTLREG_BUSSTATE_IRQ_LSB (1) > #define CTLREG_BUSSTATE_IRQ_MASK (0x000000FEu) > #define CTLREG_BUSSTATE_IRQ(x) ((x) << CTLREG_BUSSTATE_IRQ_LSB) > > /* CTLREG_BUSSTATE_IACKIN - The current state of the (active-low) IACKIN > * line. > */ > > #define CTLREG_BUSSTATE_IACKIN_LSB (0) > #define CTLREG_BUSSTATE_IACKIN (0x00000001u) > > It also writes out HTML documentation where the bitfields of a BUSSTATE > are shown as a 4 row table (1,3 are bit numbers, 2,4 are fields) > followed by a bulleted list with the descriptive text. > > And the most important part is that every time I type "make", I am > guaranteed that the VHDL, C, and HTML are all in sync. I still need to > go around synchronizing all of the logic, but since cutting over to this > system I have NEVER got the wrong bit in the wrong place. Because > that's a stupid mistake in copying data redundantly, which is exactly > the sort of thing computers are better at than we are. Good idea. One change I think I would make would be to hand write the C file and derive the rest of the code from that. If any additional info is needed for the VHDL that isn't needed in the C header file it can easily be incorporated in C comments and parsed out by the conversion program. I just prefer not to have yet enough source file. -- Rick From newsfish@newsfish Thu Aug 1 00:36:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Wed, 9 Mar 2016 19:40:25 -0000 (UTC) Organization: A noiseless patient Spider Lines: 173 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Wed, 9 Mar 2016 19:40:25 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="16522"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/PKvbDmsXJsYNKJZFIShqB" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:oHV+w2ynSBEG9ymu8OVXJy/KMSw= Xref: news.eternal-september.org comp.lang.vhdl:4297 rickman wrote: > On 3/9/2016 1:43 PM, Rob Gaddi wrote: >> rickman wrote: >> >>> On 3/9/2016 12:36 PM, Rob Gaddi wrote: >>>> rickman wrote: >>>>> >>>>> I'm a bit unclear on this. What is the assumption on how the registers >>>>> are created in the VHDL code. Is this a block RAM or discrete registers >>>>> in the fabric? I can see providing a C header file for a memory mapped >>>>> register bank, but how can you define the registers in the VHDL if you >>>>> don't know how they need to be implemented? >>>>> >>>> >>>> Haven't actually looked at what the bitvis thing is up to, but I've >>>> implemented a similar system here (though I'm less than thrilled with >>>> the way it all came together). >>>> >>>> In mine, each register gets its own record type associated with it, >>>> made up of unsigned/signed/std_logic/std_logic_vector based on the >>>> register definition file, and there are conversion functions for >>>> translating records to/from the data bus std_logic_vector, all of which >>>> goes into a package that I import into the module that actually does the >>>> work. >>> >>> I'm not clear on what you are describing here. Sounds like you are >>> substituting an HDL definition of a register with a configuration file >>> definition of a register. >>> >> >> Exactly. I (hand)write an XML file defining all the registers in a >> peripheral, then I cook it down and get a VHDL package with definitions >> such as: >> >> constant BUSSTATE_ADDR : t_addr := 16#026#; >> >> type t_BUSSTATE is record >> IACKIN : std_logic; >> IRQ : std_logic_vector(6 downto 0); >> DTACK : std_logic; >> BERR : std_logic; >> RETRY : std_logic; >> end record t_BUSSTATE; >> >> pure function BUSSTATE_TO_WORD(dat : t_BUSSTATE) return t_word is >> variable ret : t_word; >> begin >> ret := (others => '0'); >> ret(0) := dat.IACKIN; >> ret(7 downto 1) := std_logic_vector(dat.IRQ); >> ret(8) := dat.DTACK; >> ret(9) := dat.BERR; >> ret(10) := dat.RETRY; >> return ret; >> end function BUSSTATE_TO_WORD; >> >> pure function WORD_TO_BUSSTATE(dat : t_word) return t_BUSSTATE is >> variable ret : t_BUSSTATE; >> begin >> ret.IACKIN := dat(0); >> ret.IRQ := std_logic_vector(dat(7 downto 1)); >> ret.DTACK := dat(8); >> ret.BERR := dat(9); >> ret.RETRY := dat(10); >> return ret; >> end function WORD_TO_BUSSTATE; >> >> procedure UPDATE_BUSSTATE(reg : inout t_BUSSTATE; nd : in t_word; be : in t_be) is >> variable tmp : t_word; >> begin >> tmp := BUSSTATE_TO_WORD(reg); >> for i in be'range loop >> if (be(i) = '1') then >> tmp(i*8 + 7 downto i*8) := nd(i*8+7 downto i*8); >> end if; >> end loop; >> reg := WORD_TO_BUSSTATE(tmp); >> end procedure UPDATE_BUSSTATE; >> >> The generated VHDL file I sliced those out of is, as an example, 2500 >> lines long. Those translation functions are responsible for making sure >> that everyone agrees which bit of the word represents BERR. >> >> It also cogenerates a C header file with a struct that puts uint32_t >> BUSSTATE (and all the other registers in the peripheral) at the correct >> location, and contains >> >> /****************************************************************************** >> * BUSSTATE Field Descriptions >> *****************************************************************************/ >> >> /* CTLREG_BUSSTATE_RETRY - The current state of the (active-low) RETRY >> * line. >> */ >> >> #define CTLREG_BUSSTATE_RETRY_LSB (10) >> #define CTLREG_BUSSTATE_RETRY (0x00000400u) >> >> /* CTLREG_BUSSTATE_BERR - The current state of the (active-low) BERR line. >> */ >> >> #define CTLREG_BUSSTATE_BERR_LSB (9) >> #define CTLREG_BUSSTATE_BERR (0x00000200u) >> >> /* CTLREG_BUSSTATE_DTACK - The current state of the (active-low) DTACK >> * line. >> */ >> >> #define CTLREG_BUSSTATE_DTACK_LSB (8) >> #define CTLREG_BUSSTATE_DTACK (0x00000100u) >> >> /* CTLREG_BUSSTATE_IRQ - The current state of the (active-low) IRQ lines 7 >> * through 1. >> */ >> >> #define CTLREG_BUSSTATE_IRQ_LSB (1) >> #define CTLREG_BUSSTATE_IRQ_MASK (0x000000FEu) >> #define CTLREG_BUSSTATE_IRQ(x) ((x) << CTLREG_BUSSTATE_IRQ_LSB) >> >> /* CTLREG_BUSSTATE_IACKIN - The current state of the (active-low) IACKIN >> * line. >> */ >> >> #define CTLREG_BUSSTATE_IACKIN_LSB (0) >> #define CTLREG_BUSSTATE_IACKIN (0x00000001u) >> >> It also writes out HTML documentation where the bitfields of a BUSSTATE >> are shown as a 4 row table (1,3 are bit numbers, 2,4 are fields) >> followed by a bulleted list with the descriptive text. >> >> And the most important part is that every time I type "make", I am >> guaranteed that the VHDL, C, and HTML are all in sync. I still need to >> go around synchronizing all of the logic, but since cutting over to this >> system I have NEVER got the wrong bit in the wrong place. Because >> that's a stupid mistake in copying data redundantly, which is exactly >> the sort of thing computers are better at than we are. > > Good idea. One change I think I would make would be to hand write the C > file and derive the rest of the code from that. If any additional info > is needed for the VHDL that isn't needed in the C header file it can > easily be incorporated in C comments and parsed out by the conversion > program. I just prefer not to have yet enough source file. > Thought about making C, VHDL, or HTML the source format rather than XML. Either of the first two can be really ugly to parse, and HTML was even uglier to write than my XML format. Certainly any of those formats have to chock-full of redudant information to be useful. CTLREG_BUSSTATE_IRQ_LSB, CTLREG_BUSSTATE_IRQ_MASK, CTLREG_BUSSTATE_IRQ(x) as an example, to say nothing of the enumerated fields. The idea was to optimize for parseability and just generate from there, since good XML editors are a dime a dozen. That way the processing code can also be responsible for things like automatically doling out addresses, etc. The reality became that, no, good XML editors are in fact NOT a dime a dozen and I wound up having to always write the XML by hand in a text editor. Between projects I inevitably forget what my tag names and attributes were and have to go relearn them from whatever the last project was, which is a nuisance. And XML turns out to be less elegant than one might want; in offering 5 ways to do anything you wind up spending far too much time trying to figure out the "best" way. So it works well enough that I keep using it and can't justify time spent improving it, but requires enough smacking of the TV set that I haven't really made any kind of open-source project from it. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!newspeer1.nac.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Simplify handling of SW accessible registers in FPGA Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 09 Mar 2016 21:32:27 GMT Lines: 19 Message-ID: <56e0966b$0$11091$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: ba994c93.news.astraweb.com X-Trace: DXC=GYBGW38C3Xa:LXj0CA`3KmL?0kYOcDh@jSBc;\8ijUdkYRP3^H]h_dfjKO6J;E[oXng@CcYi\2I4a Xref: news.eternal-september.org comp.lang.vhdl:4298 On Wed, 09 Mar 2016 18:43:55 +0000, Rob Gaddi wrote: [snip] > It also cogenerates a C header file with a struct that puts uint32_t > BUSSTATE (and all the other registers in the peripheral) at the correct > location, and contains Here we use a C typedef to create a "reg32_t" type, which is just like uint32_t but with an added volatile qualifier. Then we just define all registers as "reg32_t" and banish a whole class of hard to find bugs. Of course, (in keeping with the C spirit) one can make the bugs come back by calling functions which expect arguments to be pointers to uint32_t. Regards, Allan From newsfish@newsfish Thu Aug 1 00:36:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Wed, 9 Mar 2016 21:48:34 -0000 (UTC) Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <56e0966b$0$11091$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Wed, 9 Mar 2016 21:48:34 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="15103"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+n1ZyT9LqNeuYJYW5D24fj" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:RBspM43aW94KmCPGPp2A20HZamE= Xref: news.eternal-september.org comp.lang.vhdl:4299 Allan Herriman wrote: > On Wed, 09 Mar 2016 18:43:55 +0000, Rob Gaddi wrote: > > [snip] > >> It also cogenerates a C header file with a struct that puts uint32_t >> BUSSTATE (and all the other registers in the peripheral) at the correct >> location, and contains > > Here we use a C typedef to create a "reg32_t" type, which is just like > uint32_t but with an added volatile qualifier. > > Then we just define all registers as "reg32_t" and banish a whole class > of hard to find bugs. > > Of course, (in keeping with the C spirit) one can make the bugs come back > by calling functions which expect arguments to be pointers to uint32_t. > > Regards, > Allan I have my struct CTLREGS full of uint32_ts, and then wind up with a volatile struct CTLREGS *. That way I can make local copies of the structure that aren't flagged as volatile, work with them, and copy them back en masse; a capability that I've so far used zero times. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Wed, 9 Mar 2016 17:59:49 -0500 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 9 Mar 2016 22:56:48 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="30793"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+y8/edFv+f+vbVZYKgV6tT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 In-Reply-To: Cancel-Lock: sha1:RTxiFgfrGqWzK03lLJSpS42HoqA= Xref: news.eternal-september.org comp.lang.vhdl:4300 On 3/9/2016 2:40 PM, Rob Gaddi wrote: > rickman wrote: >> >> Good idea. One change I think I would make would be to hand write the C >> file and derive the rest of the code from that. If any additional info >> is needed for the VHDL that isn't needed in the C header file it can >> easily be incorporated in C comments and parsed out by the conversion >> program. I just prefer not to have yet enough source file. >> > > Thought about making C, VHDL, or HTML the source format rather than XML. > Either of the first two can be really ugly to parse, and HTML was even > uglier to write than my XML format. But it wouldn't have to be a full C parser, just any limited subset you care to specify. In essence the idea is to write a "special" format file that can be read by a C compiler for those purposes. But whatever, each way has it's drawbacks and advantages. > Certainly any of those formats have > to chock-full of redudant information to be useful. > CTLREG_BUSSTATE_IRQ_LSB, CTLREG_BUSSTATE_IRQ_MASK, > CTLREG_BUSSTATE_IRQ(x) as an example, to say nothing of the enumerated > fields. > > The idea was to optimize for parseability and just generate from there, > since good XML editors are a dime a dozen. That way the processing code > can also be responsible for things like automatically doling out > addresses, etc. > > The reality became that, no, good XML editors are in fact NOT a dime a > dozen and I wound up having to always write the XML by hand in a text > editor. Between projects I inevitably forget what my tag names and > attributes were and have to go relearn them from whatever the last > project was, which is a nuisance. And XML turns out to be less elegant > than one might want; in offering 5 ways to do anything you wind up > spending far too much time trying to figure out the "best" way. > > So it works well enough that I keep using it and can't justify time > spent improving it, but requires enough smacking of the TV set that I > haven't really made any kind of open-source project from it. Lol, I like that image, smacking the TV. Yeah, there are lots of ideas that sound good until you implement them. -- Rick From newsfish@newsfish Thu Aug 1 00:36:19 2024 X-Received: by 10.50.6.7 with SMTP id w7mr772270igw.12.1457576781433; Wed, 09 Mar 2016 18:26:21 -0800 (PST) X-Received: by 10.50.111.100 with SMTP id ih4mr19937igb.3.1457576781399; Wed, 09 Mar 2016 18:26:21 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!sv18no75286igc.0!news-out.google.com!k1ni13987igd.0!nntp.google.com!nt3no313054igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Mar 2016 18:26:20 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13585ac7-7c78-4ac4-b73e-e6603b7227cf@googlegroups.com> Subject: Re: Simplify handling of SW accessible registers in FPGA From: michael6866 Injection-Date: Thu, 10 Mar 2016 02:26:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 5099 X-Received-Body-CRC: 3655472610 Xref: news.eternal-september.org comp.lang.vhdl:4301 On Wednesday, March 9, 2016 at 12:39:25 PM UTC-5, Rob Gaddi wrote: > rickman wrote: > > > On 3/9/2016 5:01 AM, espen.tallaksen@bitvis.no wrote: > >> Save lots of work > >> - Auto-generate register related code and documentation, and > >> - Keep SW, FPGA and Documentation synchronized > >> Register Wizard is now free :-) > >> > >> Register Wizard is now released as a freeware to generate 'C' code, VHDL code and documentation from a single register definition file. > >> This allows a major efficiency boost for developing systems with software accessible registers, - and equally important - a simple way of keeping your Software, FPGA and Documentation synchronized. > >> > >> The register definition file is written as normal text in the JSON file format. From this file you can automatically generate the following: > >> > >> - 'C' header file for all registers and their addresses > >> - VHDL package for all registers and their addresses > >> - Full VHDL simple processor interface for register access > >> (May easily be wrapped to Avalon or AXI4-lite) > >> - Self-checking VHDL testbench for the processor interface > >> (Using UVVM Utility Library) > >> - Documentation in the form of a register map and register description > >> in the Office Open XML format for simple inclusion in MS Word. > >> > >> This also means that specification changes are handled in a very structured manner - just by extending or modifying the register definition file and re-generating all the above. > >> > >> The tool and usage is of course properly documented - including a tutorial and example, - and may be downloaded from our web-site: http://bitvis.no/products/register_wizard/ > >> > >> Enjoy :-) > >> And please send us feedback on potential improvements for your applications. > > > > I'm a bit unclear on this. What is the assumption on how the registers > > are created in the VHDL code. Is this a block RAM or discrete registers > > in the fabric? I can see providing a C header file for a memory mapped > > register bank, but how can you define the registers in the VHDL if you > > don't know how they need to be implemented? > > > > Haven't actually looked at what the bitvis thing is up to, but I've > implemented a similar system here (though I'm less than thrilled with > the way it all came together). > > In mine, each register gets its own record type associated with it, > made up of unsigned/signed/std_logic/std_logic_vector based on the > register definition file, and there are conversion functions for > translating records to/from the data bus std_logic_vector, all of which > goes into a package that I import into the module that actually does the > work. > > So that gives you automation of defining registers. I never > got around to the next logical step, auto-generating the code that > defines the "register file" as a record of all the subrecords, > and handles the bus transactions against that record in some kind of > DoBusTransaction(regfile) call. It would be straightforward to do > if cumbersome. > > It's still up to the designer to actually make those registers do > things, but lots of things follow some very basic patterns. Read-only > status registers are always updated before DoBusTransaction. Write-only > registers get their values used and then blanked after > DoBusTransaction. And so on. There's still plenty on the designer's > plate, but a ton of the crappy boilerplate can be automated, while > generating C headers and pretty documentation along the way. > > -- > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > Email address domain is currently out of order. See above to fix. There is also a standard IEEE 1685-2009 which uses "IP-XACT" format for defining peripheral registers. Major EDA vendors have tools supporting the format and its extensions for code generation. From newsfish@newsfish Thu Aug 1 00:36:19 2024 X-Received: by 10.129.116.214 with SMTP id p205mr2279360ywc.55.1457612556950; Thu, 10 Mar 2016 04:22:36 -0800 (PST) X-Received: by 10.50.138.165 with SMTP id qr5mr51699igb.10.1457612556899; Thu, 10 Mar 2016 04:22:36 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y89no6577503qge.0!news-out.google.com!k1ni14391igd.0!nntp.google.com!nt3no416180igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Mar 2016 04:22:36 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <985abcee-346e-417c-9941-48b356b282be@googlegroups.com> Subject: Re: Simplify handling of SW accessible registers in FPGA From: espen.tallaksen@bitvis.no Injection-Date: Thu, 10 Mar 2016 12:22:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4302 > I'm a bit unclear on this. What is the assumption on how the registers= =20 > are created in the VHDL code. Is this a block RAM or discrete registers= =20 > in the fabric? I can see providing a C header file for a memory mapped= =20 > register bank, but how can you define the registers in the VHDL if you=20 > don't know how they need to be implemented? The registers are discrete. Registers that are not manipulated by the core = functionality (e.g. IER in the provided example) are generated as a part of= the autogenerated processor/register interface (PIF) sub-module. Registers= that are manipulated by the core functionality (e.g. IRR) are located in t= he core sub-module. For these registers you pass control from PIF to core a= nd register contents from core to PIF. Everything inside PIF - including th= e bus interface is auto-generated. We did it this way to allow full flexibi= lity and reduced probability of "assumption-bugs". Hence any register type = is possible.=20 -Espen From newsfish@newsfish Thu Aug 1 00:36:19 2024 X-Received: by 10.140.233.69 with SMTP id e66mr2213896qhc.6.1457613083887; Thu, 10 Mar 2016 04:31:23 -0800 (PST) X-Received: by 10.50.25.196 with SMTP id e4mr51951igg.8.1457613083836; Thu, 10 Mar 2016 04:31:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w104no5923512qge.1!news-out.google.com!pn7ni5760igb.0!nntp.google.com!sv18no125888igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Mar 2016 04:31:23 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Simplify handling of SW accessible registers in FPGA From: espen.tallaksen@bitvis.no Injection-Date: Thu, 10 Mar 2016 12:31:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4303 I see from the discussion above that we should also show the result-files f= rom Register Wizard in the provided download. The result-files are describe= d in the current documentation, but the actual files are not shown. I think= everything will be clearer, and hopefully your questions will be answered = when we include the result files from the documented example. Most probably= we will provide this as a separate zip-file ASAP. From newsfish@newsfish Thu Aug 1 00:36:20 2024 X-Received: by 10.140.221.134 with SMTP id r128mr2331382qhb.0.1457613328565; Thu, 10 Mar 2016 04:35:28 -0800 (PST) X-Received: by 10.50.43.234 with SMTP id z10mr53105igl.4.1457613328526; Thu, 10 Mar 2016 04:35:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y89no6579600qge.0!news-out.google.com!pn7ni5764igb.0!nntp.google.com!nt3no419274igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Mar 2016 04:35:27 -0800 (PST) In-Reply-To: <13585ac7-7c78-4ac4-b73e-e6603b7227cf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: <13585ac7-7c78-4ac4-b73e-e6603b7227cf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <50f913e7-0c82-4d0d-881c-a08e720bb0dc@googlegroups.com> Subject: Re: Simplify handling of SW accessible registers in FPGA From: espen.tallaksen@bitvis.no Injection-Date: Thu, 10 Mar 2016 12:35:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4304 > There is also a standard IEEE 1685-2009 which uses "IP-XACT" format for defining peripheral registers. Major EDA vendors have tools supporting the format and its extensions for code generation. IP-XACT is probably very good for data exchange between different tools, but it is not very good as a human-readable format. We made our own format to significantly increase readability for designers. We evaluated XML, but concluded JSON was better. From newsfish@newsfish Thu Aug 1 00:36:20 2024 X-Received: by 10.66.163.97 with SMTP id yh1mr2953647pab.11.1457622828935; Thu, 10 Mar 2016 07:13:48 -0800 (PST) X-Received: by 10.50.79.133 with SMTP id j5mr77205igx.1.1457622828878; Thu, 10 Mar 2016 07:13:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!sv18no146803igc.0!news-out.google.com!pn7ni5889igb.0!nntp.google.com!nt3no453219igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Mar 2016 07:13:48 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e0a0c1a-eb7b-4e36-93e8-3fc52a02da03@googlegroups.com> Subject: Re: Simplify handling of SW accessible registers in FPGA From: espen.tallaksen@bitvis.no Injection-Date: Thu, 10 Mar 2016 15:13:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4305 > I see from the discussion above that we should also show the result-files= from Register Wizard in the provided download. The result-files are descri= bed in the current documentation, but the actual files are not shown. I thi= nk everything will be clearer, and hopefully your questions will be answere= d when we include the result files from the documented example. Most probab= ly we will provide this as a separate zip-file ASAP. A zip-file showing the generated outputs is now provided for download under= http://bitvis.no/products/register_wizard/ From newsfish@newsfish Thu Aug 1 00:36:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Thu, 10 Mar 2016 12:34:23 -0500 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <0e0a0c1a-eb7b-4e36-93e8-3fc52a02da03@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 10 Mar 2016 17:31:20 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="21611"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+3aN8eNR6O/LBEgxeY0sI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 In-Reply-To: <0e0a0c1a-eb7b-4e36-93e8-3fc52a02da03@googlegroups.com> Cancel-Lock: sha1:0FWpFspo1TKwhPCBlSiNUChvcyA= Xref: news.eternal-september.org comp.lang.vhdl:4306 On 3/10/2016 10:13 AM, espen.tallaksen@bitvis.no wrote: >> I see from the discussion above that we should also show the result-files from Register Wizard in the provided download. The result-files are described in the current documentation, but the actual files are not shown. I think everything will be clearer, and hopefully your questions will be answered when we include the result files from the documented example. Most probably we will provide this as a separate zip-file ASAP. > > A zip-file showing the generated outputs is now provided for download under http://bitvis.no/products/register_wizard/ Some feedback. Your flyer is way too terse and I'm not inclined to download a full user manual to learn the first things about a tool. You might want to have a quick overview manual to give potential customers an idea of the facilities of the tool without having to learn the whole thing or wade through a full manual. The files download is a good start. In addition to the outputs, I found the input which doesn't look too hard to learn. But your example includes no bit fields in the registers. Isn't that essential? I would also include at least one example of logic that is added by the user to be incorporated in one of the output files, the core file I assume. Perhaps something simple like a bit that is cleared when read. Some sort of overview description would be useful explaining each of the output files and how they are intended to be used including some of the specifics of each file. Something I can read in 15-30 minutes rather than hours. I see your user manual has a tutorial and I was able to scan it quickly and found it includes the use of "Write-to-Trigger" which would be interesting to see. Maybe the download could use the files from the tutorial? Just my 10 minute look at your materials. :) -- Rick From newsfish@newsfish Thu Aug 1 00:36:21 2024 X-Received: by 10.140.30.99 with SMTP id c90mr3507122qgc.2.1457631743012; Thu, 10 Mar 2016 09:42:23 -0800 (PST) X-Received: by 10.50.109.230 with SMTP id hv6mr113699igb.2.1457631742954; Thu, 10 Mar 2016 09:42:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!y89no6627282qge.0!news-out.google.com!k1ni14641igd.0!nntp.google.com!nt3no491147igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Mar 2016 09:42:22 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2d0f3797-abcb-4f2a-92bf-4326f5d7b267@googlegroups.com> Subject: Re: Simplify handling of SW accessible registers in FPGA From: KJ Injection-Date: Thu, 10 Mar 2016 17:42:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 61 Xref: news.eternal-september.org comp.lang.vhdl:4307 On Wednesday, March 9, 2016 at 12:39:25 PM UTC-5, Rob Gaddi wrote: >=20 > In mine, each register gets its own record type associated with it, > made up of unsigned/signed/std_logic/std_logic_vector based on the > register definition file, and there are conversion functions for > translating records to/from the data bus std_logic_vector, all of which > goes into a package that I import into the module that actually does the > work. >=20 I do the same but I put the actual bit definitions into the record like thi= s... type t_INPUT_DMA_CONTROL_PORT is record Start: std_ulogic_vector(31 downto 31); Reserved: std_ulogic_vector(30 downto 26); Max_Count: std_ulogic_vector(25 downto 0); end record; That way the 'to/from' std_ulogic_vector functions can be written without h= aving to refer to bit locations, like this... function To_Std_ULogic_Vector(L : t_INPUT_DMA_CONTROL_PORT) return std_= ulogic_vector is variable RetVal: std_ulogic_vector(31 downto 0); begin RetVal :=3D (others =3D> '0'); RetVal(L.Start'range) :=3D L.Start; RetVal(L.Reserved'range) :=3D L.Reserved; RetVal(L.Max_Count'range) :=3D L.Max_Count; return(RetVal); end To_Std_ULogic_Vector; function From_Std_ULogic_Vector(L : std_ulogic_vector) return t_INPUT_D= MA_CONTROL_PORT is variable RetVal: t_INPUT_DMA_CONTROL_PORT; variable Lx: std_ulogic_vector(L'length - 1 downto 0); begin Lx :=3D L; RetVal.Start :=3D Lx(RetVal.Start'range); RetVal.Reserved :=3D Lx(RetVal.Reserved'range); RetVal.Max_Count :=3D Lx(RetVal.Max_Count'range); return(RetVal); end From_Std_ULogic_Vector; Given the record definition, it is a quick macro run to generate these to/f= rom functions which is completed quickly. If only bit definitions change, = then only the record needs to be modified and everything recompiled. If yo= u add/subtract fields then the record and two functions need to be updated = and everything recompiled. All in all, not much maintenance. It's not trying to do as much as I think the OP is doing, but it does handl= e most of the work and most of the stuff that is error prone anyway. > So that gives you automation of defining registers. I never > got around to the next logical step, auto-generating the code that > defines the "register file" as a record of all the subrecords, > and handles the bus transactions against that record in some kind of > DoBusTransaction(regfile) call. It would be straightforward to do > if cumbersome. >=20 I have, but actually I just use a spreadsheet for a lot of the work. Archi= ve the spreadsheet along the source. From newsfish@newsfish Thu Aug 1 00:36:21 2024 X-Received: by 10.13.226.212 with SMTP id l203mr4931088ywe.42.1457655436750; Thu, 10 Mar 2016 16:17:16 -0800 (PST) X-Received: by 10.50.87.40 with SMTP id u8mr1524igz.0.1457655436676; Thu, 10 Mar 2016 16:17:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w104no6031794qge.1!news-out.google.com!k1ni14909igd.0!nntp.google.com!nt3no580153igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Mar 2016 16:17:16 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=138.128.222.98; posting-account=XUZW3woAAAAvqjhEa35ql7jqrM4YjoTn NNTP-Posting-Host: 138.128.222.98 References: <4a39b7a1-b759-4b92-b494-801bcf6aeac8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4d20b10e-9b1a-4125-a822-c5c5b50c3188@googlegroups.com> Subject: Re: mxn bit mulplication maps how many gates? From: Yang Luo Injection-Date: Fri, 11 Mar 2016 00:17:16 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4308 so, different technology=EF=BC=88like 22nm,40nm=EF=BC=89have different resu= lt gates when using dc synthesis? is there a relationship between technolog= y and gates? i use dc to synthesis a two variable input 8*8 mul, it get an = erea about xx um^2, how can i change the scripts to get gate number ? From newsfish@newsfish Thu Aug 1 00:36:21 2024 X-Received: by 10.66.244.171 with SMTP id xh11mr5315544pac.32.1457663419445; Thu, 10 Mar 2016 18:30:19 -0800 (PST) X-Received: by 10.50.178.167 with SMTP id cz7mr1511igc.5.1457663419403; Thu, 10 Mar 2016 18:30:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!sv18no236938igc.0!news-out.google.com!pn7ni6366igb.0!nntp.google.com!sv18no236930igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Mar 2016 18:30:18 -0800 (PST) In-Reply-To: <50f913e7-0c82-4d0d-881c-a08e720bb0dc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <13585ac7-7c78-4ac4-b73e-e6603b7227cf@googlegroups.com> <50f913e7-0c82-4d0d-881c-a08e720bb0dc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <182f3265-e6f1-4985-b77d-b129bf1d8339@googlegroups.com> Subject: Re: Simplify handling of SW accessible registers in FPGA From: michael6866 Injection-Date: Fri, 11 Mar 2016 02:30:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4309 On Thursday, March 10, 2016 at 7:35:31 AM UTC-5, espen.t...@bitvis.no wrote: > > There is also a standard IEEE 1685-2009 which uses "IP-XACT" format for defining peripheral registers. Major EDA vendors have tools supporting the format and its extensions for code generation. > > IP-XACT is probably very good for data exchange between different tools, but it is not very good as a human-readable format. We made our own format to significantly increase readability for designers. We evaluated XML, but concluded JSON was better. Yes, that's why there is the RDL languages such as http://www.accellera.org/activities/working-groups/systemrdl From newsfish@newsfish Thu Aug 1 00:36:22 2024 X-Received: by 10.129.72.195 with SMTP id v186mr6164908ywa.37.1457689009368; Fri, 11 Mar 2016 01:36:49 -0800 (PST) X-Received: by 10.50.25.196 with SMTP id e4mr19436igg.8.1457689009329; Fri, 11 Mar 2016 01:36:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y89no6743608qge.0!news-out.google.com!k1ni15263igd.0!nntp.google.com!av4no30289igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Mar 2016 01:36:48 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: <0e0a0c1a-eb7b-4e36-93e8-3fc52a02da03@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Simplify handling of SW accessible registers in FPGA From: espen.tallaksen@bitvis.no Injection-Date: Fri, 11 Mar 2016 09:36:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4310 torsdag 10. mars 2016 18.34.29 UTC+1 skrev rickman f=F8lgende: > On 3/10/2016 10:13 AM, espen wrote: > >> I see from the discussion above that we should also show the result-fi= les from Register Wizard in the provided download. The result-files are des= cribed in the current documentation, but the actual files are not shown. I = think everything will be clearer, and hopefully your questions will be answ= ered when we include the result files from the documented example. Most pro= bably we will provide this as a separate zip-file ASAP. > > > > A zip-file showing the generated outputs is now provided for download u= nder http://bitvis.no/products/register_wizard/ >=20 > Some feedback. Your flyer is way too terse and I'm not inclined to=20 > download a full user manual to learn the first things about a tool. You= =20 > might want to have a quick overview manual to give potential customers=20 > an idea of the facilities of the tool without having to learn the whole= =20 > thing or wade through a full manual. >=20 > The files download is a good start. In addition to the outputs, I found= =20 > the input which doesn't look too hard to learn. But your example=20 > includes no bit fields in the registers. Isn't that essential? I would= =20 > also include at least one example of logic that is added by the user to= =20 > be incorporated in one of the output files, the core file I assume.=20 > Perhaps something simple like a bit that is cleared when read. Some=20 > sort of overview description would be useful explaining each of the=20 > output files and how they are intended to be used including some of the= =20 > specifics of each file. Something I can read in 15-30 minutes rather=20 > than hours. >=20 > I see your user manual has a tutorial and I was able to scan it quickly= =20 > and found it includes the use of "Write-to-Trigger" which would be=20 > interesting to see. Maybe the download could use the files from the=20 > tutorial? >=20 > Just my 10 minute look at your materials. :) >=20 > --=20 >=20 > Rick Thanks for good suggestions on improving the documentation with simpler get= -started-documentation. I will add it in our issue tracking system. -Espen From newsfish@newsfish Thu Aug 1 00:36:22 2024 X-Received: by 10.107.165.213 with SMTP id o204mr6361297ioe.10.1457689713484; Fri, 11 Mar 2016 01:48:33 -0800 (PST) X-Received: by 10.50.61.200 with SMTP id s8mr19747igr.3.1457689713466; Fri, 11 Mar 2016 01:48:33 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!nt3no675378igb.0!news-out.google.com!k1ni15282igd.0!nntp.google.com!nt3no675367igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Mar 2016 01:48:33 -0800 (PST) In-Reply-To: <182f3265-e6f1-4985-b77d-b129bf1d8339@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: <13585ac7-7c78-4ac4-b73e-e6603b7227cf@googlegroups.com> <50f913e7-0c82-4d0d-881c-a08e720bb0dc@googlegroups.com> <182f3265-e6f1-4985-b77d-b129bf1d8339@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0a3fd04e-b7a8-42ea-bdb4-f94bfc7f212e@googlegroups.com> Subject: Re: Simplify handling of SW accessible registers in FPGA From: espen.tallaksen@bitvis.no Injection-Date: Fri, 11 Mar 2016 09:48:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4311 fredag 11. mars 2016 03.30.24 UTC+1 skrev michael6866 f=F8lgende: > On Thursday, March 10, 2016 at 7:35:31 AM UTC-5, espen.t...@bitvis.no wro= te: > > > There is also a standard IEEE 1685-2009 which uses "IP-XACT" format f= or defining peripheral registers. Major EDA vendors have tools supporting t= he format and its extensions for code generation. > >=20 > > IP-XACT is probably very good for data exchange between different tools= , but it is not very good as a human-readable format. We made our own forma= t to significantly increase readability for designers. We evaluated XML, bu= t concluded JSON was better. >=20 > Yes, that's why there is the RDL languages such as http://www.accellera.o= rg/activities/working-groups/systemrdl Thanks. Seems to be dead though, with no support... From newsfish@newsfish Thu Aug 1 00:36:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Tue, 15 Mar 2016 08:44:00 +0100 Organization: 502 You are not allowed to talk Lines: 19 Sender: newsmailcomp6@gustad.com Message-ID: <878u1k2njz.fsf@filestore.home.gustad.com> References: Mime-Version: 1.0 Content-Type: text/plain Injection-Info: mx02.eternal-september.org; posting-host="6f120dbd3bb53ffbfc53ee24c4fe7513"; logging-data="17169"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19jpIyU6JAHOh0m0/dMMXxz" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.4 (gnu/linux) Cancel-Lock: sha1:19dLijZVo3HvvQmrD1YVIQohLLw= sha1:t3im3ZpypSQxFt0ALDNZjjA+Rwk= X-Home-Page: http://gustad.com Xref: news.eternal-september.org comp.lang.vhdl:4312 rickman writes: >> Thought about making C, VHDL, or HTML the source format rather than XML. >> Either of the first two can be really ugly to parse, and HTML was even >> uglier to write than my XML format. > > But it wouldn't have to be a full C parser, just any limited subset > you care to specify. In essence the idea is to write a "special" Rather than writing a parser one could build a small domain specific language (DSL) on top of an existing HLL or scripting language like Python, CL, Ruby, TCL, or whatever you prefer. Then it's usually quite simple to generate HDL, C header files, ralf, xact, LaTeX, etc. from there. //Petter -- .sig removed by request. From newsfish@newsfish Thu Aug 1 00:36:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Simplify handling of SW accessible registers in FPGA Date: Tue, 15 Mar 2016 03:55:57 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <878u1k2njz.fsf@filestore.home.gustad.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 15 Mar 2016 07:53:01 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="85e5dc7c61fcb84058bd59a2be086c24"; logging-data="19016"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/NCU3h/YgQyevfJYN6u7nb" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 In-Reply-To: <878u1k2njz.fsf@filestore.home.gustad.com> Cancel-Lock: sha1:Qou+8k3CGygxoy1w7Lden3pzs9U= Xref: news.eternal-september.org comp.lang.vhdl:4313 On 3/15/2016 3:44 AM, Petter Gustad wrote: > rickman writes: > >>> Thought about making C, VHDL, or HTML the source format rather than XML. >>> Either of the first two can be really ugly to parse, and HTML was even >>> uglier to write than my XML format. >> >> But it wouldn't have to be a full C parser, just any limited subset >> you care to specify. In essence the idea is to write a "special" > > Rather than writing a parser one could build a small domain specific > language (DSL) on top of an existing HLL or scripting language like > Python, CL, Ruby, TCL, or whatever you prefer. Then it's usually quite > simple to generate HDL, C header files, ralf, xact, LaTeX, etc. from > there. I'm trying to eliminate yet another file and file type. If all the source can be inserted into a C file that is used as the C header file with other code in comments adequate to specify the HDL code required, then this one file would serve as the complete source for the interface allowing the needed HDL files to be generated. -- Rick From newsfish@newsfish Thu Aug 1 00:36:23 2024 X-Received: by 10.31.157.213 with SMTP id g204mr2250626vke.14.1458125173733; Wed, 16 Mar 2016 03:46:13 -0700 (PDT) X-Received: by 10.50.83.34 with SMTP id n2mr95694igy.2.1458125173690; Wed, 16 Mar 2016 03:46:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!y89no7647035qge.0!news-out.google.com!k1ni69igd.0!nntp.google.com!av4no832785igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Mar 2016 03:46:13 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: <878u1k2njz.fsf@filestore.home.gustad.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Simplify handling of SW accessible registers in FPGA From: espen.tallaksen@bitvis.no Injection-Date: Wed, 16 Mar 2016 10:46:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2141 X-Received-Body-CRC: 3728112596 Xref: news.eternal-september.org comp.lang.vhdl:4314 We evaluated various input formats - including VHLD register definition pac= kage (or similar C header file, and of course a pure proprietary text-file)= , but we concluded on JSON. The main reasons as far as I can remember was a= ) We didn't want one of HDL,C or DOC as the source format, because this cou= ld easily lead to forgetting to update the other b) JSON is a quite human friendly format c) The support/tools available for a JSON I guess these evaluations and conclusions will differ depending on previous= experience for good and for bad, but at least the JSON format used with Re= gister Wizard is quite readable for anyone, and it is easy to make new modu= les based on the template/examples. From newsfish@newsfish Thu Aug 1 00:36:23 2024 X-Received: by 10.140.228.7 with SMTP id y7mr16170574qhb.27.1458405184681; Sat, 19 Mar 2016 09:33:04 -0700 (PDT) X-Received: by 10.50.43.234 with SMTP id z10mr120256igl.4.1458405184592; Sat, 19 Mar 2016 09:33:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w104no7509749qge.1!news-out.google.com!pn7ni14403igb.0!nntp.google.com!av4no1289533igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 19 Mar 2016 09:33:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.92.2.211; posting-account=nfkaZQoAAAAX06Pq9mX7kevPOSJOBRvL NNTP-Posting-Host: 217.92.2.211 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e7a4158-6dbb-4921-9a57-0b2ac8acd442@googlegroups.com> Subject: toki-rt.de From: Thorsten Kiefer Injection-Date: Sat, 19 Mar 2016 16:33:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4315 http://toki-rt.de/#mandelbrotspartan Regards From newsfish@newsfish Thu Aug 1 00:36:24 2024 X-Received: by 10.107.40.134 with SMTP id o128mr23600822ioo.7.1458579990601; Mon, 21 Mar 2016 10:06:30 -0700 (PDT) X-Received: by 10.50.43.194 with SMTP id y2mr239345igl.9.1458579990478; Mon, 21 Mar 2016 10:06:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!av4no1558388igc.0!news-out.google.com!u9ni3900igk.0!nntp.google.com!nt3no3576267igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Mar 2016 10:06:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.15.148.34; posting-account=X-nhmQoAAAAar5erUmd6ze-Lu6KuLmxi NNTP-Posting-Host: 194.15.148.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2df285d4-48d8-4ecf-ab96-6709e073e19d@googlegroups.com> Subject: Re: Simplify handling of SW accessible registers in FPGA From: Colin Marquardt Injection-Date: Mon, 21 Mar 2016 17:06:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4316 Some tools for the IP-XACT format that may be worth a look if you are into code generation: * https://bitbucket.org/verilab/tanto * https://andreaslindh.wordpress.com/2013/09/26/ipxact2systemverilog/ From newsfish@newsfish Thu Aug 1 00:36:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: array of strings Date: Fri, 25 Mar 2016 16:34:47 +0200 Organization: Aioe.org NNTP Server Lines: 48 Message-ID: NNTP-Posting-Host: 1kpT4xQY9AWY66LLx1ShuQ.user.gioia.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 X-Mozilla-News-Host: news://nntp.aioe.org:119 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4317 hello: I'm writing a process to write stimulis to a file in a test-bench, I like that pin names are printed vertically, so I need to access individual characters, can this be done with strings? how to make an array of strings, I got error on line: variable PINS: PIN_NAMES :=("CP","PL","CE","BD",.... declaring using a two dimensions array of character is OK. Thanks in advance WRITE_STIMULIS: process --type PIN_NAMES is ARRAY(1 to 14, 1 to 2) of character; type PIN_NAMES is ARRAY(1 to 14) of string; file stimulis : text; variable ligne : line; --variable PINS: PIN_NAMES :=(('C','P'),('P','L'),('C','E'),('B','D'),('U','D'),('T','C'), -- ('P','3'),('P','2'),('P','1'),('P','0'), -- ('Q','3'),('Q','2'),('Q','1'),('Q','0')); variable PINS: PIN_NAMES :=("CP","PL","CE","BD","UD","TC","P3","P2","P1","P0","Q3","Q2","Q1","Q0"); begin file_open(stimulis,"stimulis.txt",WRITE_MODE); write(ligne," "); writeline (stimulis,ligne); write(ligne," "); writeline (stimulis,ligne); for j in 1 to 2 loop write(ligne," "); for i in 1 to 14 loop write(ligne,PINS(i)(j)); end loop; writeline (stimulis,ligne); end loop; write(ligne," "); writeline (stimulis,ligne); for i in 1 to 9 loop wait for 100 ns; write(ligne,time'image(now)); write(ligne," "); for j in 1 to 6 loop write(ligne,chr(sig(j))); end loop; write(ligne, str(P)); write(ligne, str(Q)); writeline(stimulis,ligne); end loop; end process; From newsfish@newsfish Thu Aug 1 00:36:24 2024 X-Received: by 10.31.11.75 with SMTP id 72mr8521021vkl.2.1458916685208; Fri, 25 Mar 2016 07:38:05 -0700 (PDT) X-Received: by 10.50.164.230 with SMTP id yt6mr694897igb.8.1458916685108; Fri, 25 Mar 2016 07:38:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!y89no9334659qge.0!news-out.google.com!pn7ni16835igb.0!nntp.google.com!nt3no4455624igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Mar 2016 07:38:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=27.0.147.206; posting-account=stlxEQoAAABxq7Q_IQTkRsQV5i1IbQ9C NNTP-Posting-Host: 27.0.147.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6af36747-ccbd-4d5c-9a77-5d7d30dcee69@googlegroups.com> Subject: I want vhdl code for wirless sensor network using fpga Virtex 4... From: suhair kp Injection-Date: Fri, 25 Mar 2016 14:38:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:4318 Heloo , I want vhdl code for W.S.N. , which read 2 of sensore and sent this details through UART port. plss help me ... From newsfish@newsfish Thu Aug 1 00:36:25 2024 X-Received: by 10.107.11.104 with SMTP id v101mr9475694ioi.13.1458927123236; Fri, 25 Mar 2016 10:32:03 -0700 (PDT) X-Received: by 10.50.87.40 with SMTP id u8mr309239igz.0.1458927123203; Fri, 25 Mar 2016 10:32:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!nt3no4501825igb.0!news-out.google.com!u9ni4800igk.0!nntp.google.com!av4no2019207igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Mar 2016 10:32:02 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=178.135.82.53; posting-account=dEZDQwoAAAAU6beqje_RDFdBwFAiedug NNTP-Posting-Host: 178.135.82.53 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: array of strings From: morisaab@gmail.com Injection-Date: Fri, 25 Mar 2016 17:32:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4319 On Friday, March 25, 2016 at 4:34:49 PM UTC+2, Maurice SAAB wrote: > hello: > > I'm writing a process to write stimulis to a file in a test-bench, I > like that pin names are printed vertically, so I need to access > individual characters, can this be done with strings? how to make an > array of strings, I got error on line: variable PINS: PIN_NAMES > :=("CP","PL","CE","BD",.... > declaring using a two dimensions array of character is OK. > > Thanks in advance > > > WRITE_STIMULIS: process > --type PIN_NAMES is ARRAY(1 to 14, 1 to 2) of character; > type PIN_NAMES is ARRAY(1 to 14) of string; > file stimulis : text; > variable ligne : line; > --variable PINS: PIN_NAMES > :=(('C','P'),('P','L'),('C','E'),('B','D'),('U','D'),('T','C'), > -- ('P','3'),('P','2'),('P','1'),('P','0'), > -- ('Q','3'),('Q','2'),('Q','1'),('Q','0')); > variable PINS: PIN_NAMES > :=("CP","PL","CE","BD","UD","TC","P3","P2","P1","P0","Q3","Q2","Q1","Q0"); > > begin > file_open(stimulis,"stimulis.txt",WRITE_MODE); > write(ligne," "); writeline (stimulis,ligne); > write(ligne," "); writeline (stimulis,ligne); > for j in 1 to 2 loop > write(ligne," "); > for i in 1 to 14 loop > write(ligne,PINS(i)(j)); > end loop; > writeline (stimulis,ligne); > end loop; > write(ligne," "); writeline (stimulis,ligne); > for i in 1 to 9 loop > wait for 100 ns; > write(ligne,time'image(now)); > write(ligne," "); > for j in 1 to 6 loop > write(ligne,chr(sig(j))); > end loop; > write(ligne, str(P)); > write(ligne, str(Q)); > writeline(stimulis,ligne); > end loop; > end process; Resolved From newsfish@newsfish Thu Aug 1 00:36:25 2024 X-Received: by 10.13.216.129 with SMTP id a123mr7681143ywe.11.1458931168469; Fri, 25 Mar 2016 11:39:28 -0700 (PDT) X-Received: by 10.50.147.8 with SMTP id tg8mr9igb.8.1458931168418; Fri, 25 Mar 2016 11:39:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!b101no277593qga.1!news-out.google.com!pn7ni16843igb.0!nntp.google.com!nt3no4519364igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Mar 2016 11:39:27 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.135.185.226; posting-account=l4GPBAoAAABNHzOGAcrLApkGbYH6E9R_ NNTP-Posting-Host: 67.135.185.226 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL 2008 simplified conditions From: Jerry Injection-Date: Fri, 25 Mar 2016 18:39:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1784 X-Received-Body-CRC: 3127532934 Xref: news.eternal-september.org comp.lang.vhdl:4320 Hi all: I was attracted to simplified conditions, but they don't cross to mixed std_logic / boolean such as this: >> elsif run_tx and (rd_idx < wr_idx) then Where run_tx is std_logic and rd/wr_idx are natural. This will not work? I was hoping to get away with mixing the convenience of bool / std_logic. That should probably be an extension. I had to put in "run_tx = '1'" to resolve to bool / bool. Vsim does not complain about the pure std_logic expression simplification that involves all std_logic, for instance this is fine: >> if not rd_msg_lst and RD_MSG_i then Where rd_msg_lst and RD_MSG_i are std_logic (obvious edge detection). So, not possible to mix bool / std_logic, right? I hope that's only "as of yet". Thanks in advance for the comments, Jerry From newsfish@newsfish Thu Aug 1 00:36:25 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.freedyn.net!news.redatomik.org!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!cleanfeed4-a.proxad.net!nnrp5-1.free.fr!not-for-mail Subject: Re: I want vhdl code for wirless sensor network using fpga Virtex 4... Newsgroups: comp.lang.vhdl References: <6af36747-ccbd-4d5c-9a77-5d7d30dcee69@googlegroups.com> From: Nicolas Matringe Date: Fri, 25 Mar 2016 22:31:10 +0100 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 MIME-Version: 1.0 In-Reply-To: <6af36747-ccbd-4d5c-9a77-5d7d30dcee69@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 9 Message-ID: <56f5ae1e$0$7119$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Mar 2016 22:31:10 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1458941470 news-4.free.fr 7119 88.185.146.198:55434 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:4321 On 25.03.2016 15:38, suhair kp wrote: > Heloo , > > I want vhdl code for W.S.N. , which read 2 of sensore and sent this details through UART port. plss help me ... Hmmm the wireless part won't be doable in VHDL I'm afraid. Nicolas From newsfish@newsfish Thu Aug 1 00:36:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp5-1.free.fr!not-for-mail Subject: Re: array of strings Newsgroups: comp.lang.vhdl References: From: Nicolas Matringe Date: Fri, 25 Mar 2016 22:32:20 +0100 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 19 Message-ID: <56f5ae64$0$7119$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Mar 2016 22:32:20 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1458941540 news-4.free.fr 7119 88.185.146.198:55434 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:4322 On 25.03.2016 18:32, morisaab@gmail.com wrote: > On Friday, March 25, 2016 at 4:34:49 PM UTC+2, Maurice SAAB wrote: >> hello: >> >> I'm writing a process to write stimulis to a file in a test-bench, I >> like that pin names are printed vertically, so I need to access >> individual characters, can this be done with strings? how to make an >> array of strings, I got error on line: variable PINS: PIN_NAMES >> :=("CP","PL","CE","BD",.... >> declaring using a two dimensions array of character is OK. [...] > Resolved Hello It could have been nice to post the solution in case anyone wants to do it again. Nicolas From newsfish@newsfish Thu Aug 1 00:36:26 2024 X-Received: by 10.13.242.134 with SMTP id b128mr90278ywf.28.1459225827354; Mon, 28 Mar 2016 21:30:27 -0700 (PDT) X-Received: by 10.50.60.6 with SMTP id d6mr5487igr.9.1459225827275; Mon, 28 Mar 2016 21:30:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!b101no758685qga.1!news-out.google.com!u9ni129igk.0!nntp.google.com!nt3no5490036igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Mar 2016 21:30:26 -0700 (PDT) In-Reply-To: <6af36747-ccbd-4d5c-9a77-5d7d30dcee69@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.122.197.26; posting-account=qX4MkQoAAACnW7d1f4ZkNQvrAPXyhPvI NNTP-Posting-Host: 70.122.197.26 References: <6af36747-ccbd-4d5c-9a77-5d7d30dcee69@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: I want vhdl code for wirless sensor network using fpga Virtex 4... From: Amit Injection-Date: Tue, 29 Mar 2016 04:30:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4323 Hi suhair, If I understood your question correctly. You need vhdl code for wireless s= ensor that will give output in some digital format to be captured by FPGA a= nd then FPGA convert those data to UART protocol. If yes for that first thi= ng you need is data sheet of that sensors to understand how it sends data o= ut, so that it can be captured by fpga. -amit From newsfish@newsfish Thu Aug 1 00:36:26 2024 X-Received: by 10.176.0.174 with SMTP id 43mr5618204uaj.0.1459360653155; Wed, 30 Mar 2016 10:57:33 -0700 (PDT) X-Received: by 10.50.88.3 with SMTP id bc3mr439993igb.6.1459360653075; Wed, 30 Mar 2016 10:57:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y89no10143371qge.0!news-out.google.com!u9ni251igk.0!nntp.google.com!sy18no256350igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Mar 2016 10:57:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.227.45.23; posting-account=e0-vQwoAAAAdQ6zc2e5-mNOquvinr06- NNTP-Posting-Host: 128.227.45.23 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: FIFO with different widths for input and output From: rajesh.krissh@gmail.com Injection-Date: Wed, 30 Mar 2016 17:57:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4324 I need to read a inputs which is 128 bits wide, but my output is only 16 bits wide. I need to read all the 128 bits. So, having a FIFO would solve my issue. But now, the thing is that FIFO is generally of a particular width and depth. Having the width same as input will not solve my issue as I will still be reading 128 bits of data. So, I will have to have width of 16 bits. My question here is that how do I write 128 bits of data into this FIFO, as each memory location would have space to store only 16 bits. Please help me with this design issue. Thanks in advance! From newsfish@newsfish Thu Aug 1 00:36:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: FIFO with different widths for input and output Date: Wed, 30 Mar 2016 14:32:36 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Mar 2016 18:29:21 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="6517"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19nYmLD4q4pdf41rTzoiTlw" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 In-Reply-To: Cancel-Lock: sha1:SLceGPYL/+N4wEkgRP2EDug05i8= Xref: news.eternal-september.org comp.lang.vhdl:4325 On 3/30/2016 1:57 PM, rajesh.krissh@gmail.com wrote: > I need to read a inputs which is 128 bits wide, but my output is only 16 bits wide. I need to read all the 128 bits. So, having a FIFO would solve my issue. > > But now, the thing is that FIFO is generally of a particular width and depth. Having the width same as input will not solve my issue as I will still be reading 128 bits of data. > > So, I will have to have width of 16 bits. My question here is that how do I write 128 bits of data into this FIFO, as each memory location would have space to store only 16 bits. > > Please help me with this design issue. Ignoring the FIFO for a moment, you want to read 128 bits of data in 16 bit chunks. That means you need to read the chunks serially. You can convert the 128 bit data to serial 16 bit data either before the FIFO (a 16 bit one) or after the FIFO (a 128 bit FIFO). Your choice depending on the requirements of your design. If you need to stream 128 bit data into the FIFO on successive clock cycles, you need a 128 bit FIFO. If the data comes in with sufficient time between samples that you can serially read the eight 16 bit words into a 16 bit FIFO, then that will potentially save bits in the FIFO. Any of this make sense? In many FPGAs the block RAMs (which are often used for FIFOs) can have different data widths on the two data ports and automatically do the muxing to let data be read out in a different width. So the FIFO and the data mux can all be combined in one element. -- Rick From newsfish@newsfish Thu Aug 1 00:36:27 2024 X-Received: by 10.140.102.161 with SMTP id w30mr7301817qge.10.1459750261260; Sun, 03 Apr 2016 23:11:01 -0700 (PDT) X-Received: by 10.50.160.40 with SMTP id xh8mr144266igb.7.1459750261048; Sun, 03 Apr 2016 23:11:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!10no267053qgg.1!news-out.google.com!ha2ni554igb.0!nntp.google.com!nt3no7490405igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 3 Apr 2016 23:11:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=196.1.113.243; posting-account=PuLpSwkAAAAky7wRSHgqq0we_3O6tUL6 NNTP-Posting-Host: 196.1.113.243 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Creating virtual channel for router using verilog From: ash7724 Injection-Date: Mon, 04 Apr 2016 06:11:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4326 I wanted to design virtual channels for FIFO. I have one main FIFO whose data is to be sent to any one of the three virtual channels. Each virtual channel has a FIFO. Plz help me in designing this, From newsfish@newsfish Thu Aug 1 00:36:27 2024 X-Received: by 10.140.92.208 with SMTP id b74mr15052040qge.21.1459832240335; Mon, 04 Apr 2016 21:57:20 -0700 (PDT) X-Received: by 10.50.47.39 with SMTP id a7mr250615ign.2.1459832240131; Mon, 04 Apr 2016 21:57:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y89no11066456qge.0!news-out.google.com!u9ni525igk.0!nntp.google.com!nt3no7854418igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Apr 2016 21:57:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.245.70.248; posting-account=VeLgBQkAAAB8K2D0c8m6Xys_mUXGDEuK NNTP-Posting-Host: 82.245.70.248 References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9185bd6c-27ea-4a68-aff3-8ea780ffa27e@googlegroups.com> Subject: Re: First steps using VUnit From: tutata81@gmail.com Injection-Date: Tue, 05 Apr 2016 04:57:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4327 Hi Tobias, I'm newbie to the jenkins use, I want to automate my vhdl tests using both modelsim and VUnit. Have you a tutorial, advice or an example that allow me start the first steps. Thanks and Regards Khalid From newsfish@newsfish Thu Aug 1 00:36:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Creating virtual channel for router using verilog Date: Tue, 5 Apr 2016 02:19:46 -0400 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Apr 2016 06:16:28 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="733a187b11a19c9739e0fbc159757161"; logging-data="11577"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18caC33oFEfE48izdg7boVH" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 In-Reply-To: Cancel-Lock: sha1:Bfc6DuvCpyHe0+/1qUbNPIpqK+A= Xref: news.eternal-september.org comp.lang.vhdl:4328 On 4/4/2016 2:11 AM, ash7724 wrote: > I wanted to design virtual channels for FIFO. I have one main FIFO whose data is to be sent to any one of the three virtual channels. Each virtual channel has a FIFO. > Plz help me in designing this, Ok, how do you distinguish the three channels? -- Rick From newsfish@newsfish Thu Aug 1 00:36:28 2024 X-Received: by 10.182.24.41 with SMTP id r9mr15009043obf.25.1459837375081; Mon, 04 Apr 2016 23:22:55 -0700 (PDT) X-Received: by 10.50.164.230 with SMTP id yt6mr254493igb.8.1459837375054; Mon, 04 Apr 2016 23:22:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!gy3no295732igb.0!news-out.google.com!u9ni529igk.0!nntp.google.com!nt3no7871616igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Apr 2016 23:22:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.171.36.203; posting-account=e0-vQwoAAAAdQ6zc2e5-mNOquvinr06- NNTP-Posting-Host: 70.171.36.203 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d795667-00fd-4d43-88aa-2aea2599654c@googlegroups.com> Subject: Re: FIFO with different widths for input and output From: rajesh.krissh@gmail.com Injection-Date: Tue, 05 Apr 2016 06:22:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4329 Thanks Rick, your suggestion worked well. And I was successfully able to im= plement it. I used a FIFO with a width of 128 bits and 16 locations wide. It reads 128 = bits of data in 16 bit chunks. Then writes out 16 bits at once with the hel= p of a counter which helps me slide the window to write out from this FIFO.= After all the 128 bits are sent then the tail of the FIFO increments and s= tarts sending from the next location. On Wednesday, March 30, 2016 at 2:32:37 PM UTC-4, rickman wrote: > On 3/30/2016 1:57 PM, rajesh.krissh@gmail.com wrote: > > I need to read a inputs which is 128 bits wide, but my output is only 1= 6 bits wide. I need to read all the 128 bits. So, having a FIFO would solve= my issue. > > > > But now, the thing is that FIFO is generally of a particular width and = depth. Having the width same as input will not solve my issue as I will sti= ll be reading 128 bits of data. > > > > So, I will have to have width of 16 bits. My question here is that how = do I write 128 bits of data into this FIFO, as each memory location would h= ave space to store only 16 bits. > > > > Please help me with this design issue. >=20 > Ignoring the FIFO for a moment, you want to read 128 bits of data in 16= =20 > bit chunks. That means you need to read the chunks serially. You can=20 > convert the 128 bit data to serial 16 bit data either before the FIFO (a= =20 > 16 bit one) or after the FIFO (a 128 bit FIFO). Your choice depending=20 > on the requirements of your design. If you need to stream 128 bit data= =20 > into the FIFO on successive clock cycles, you need a 128 bit FIFO. If=20 > the data comes in with sufficient time between samples that you can=20 > serially read the eight 16 bit words into a 16 bit FIFO, then that will= =20 > potentially save bits in the FIFO. >=20 > Any of this make sense? >=20 > In many FPGAs the block RAMs (which are often used for FIFOs) can have=20 > different data widths on the two data ports and automatically do the=20 > muxing to let data be read out in a different width. So the FIFO and=20 > the data mux can all be combined in one element. >=20 > --=20 >=20 > Rick From newsfish@newsfish Thu Aug 1 00:36:28 2024 X-Received: by 10.182.252.101 with SMTP id zr5mr5910014obc.38.1459838160079; Mon, 04 Apr 2016 23:36:00 -0700 (PDT) X-Received: by 10.50.147.8 with SMTP id tg8mr254541igb.8.1459838160015; Mon, 04 Apr 2016 23:36:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!nt3no7873711igb.0!news-out.google.com!u9ni526igk.0!nntp.google.com!gy3no296467igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Apr 2016 23:35:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.171.36.203; posting-account=e0-vQwoAAAAdQ6zc2e5-mNOquvinr06- NNTP-Posting-Host: 70.171.36.203 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> Subject: Verilog module in VHDL for Altera devices From: Raj Injection-Date: Tue, 05 Apr 2016 06:36:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4330 I found a verilog core which performs the task I want and I wish to use it within my VHDL module. Is such a functionality possible? If yes, what all additional steps would be required? I found this source http://quartushelp.altera.com/14.1/mergedProjects/hdl/vlog/vlog_file_mixed_lang.htm which tells me that I have to declare components within Verilog in the VHDL module, which creates a portmap. My question here is, do I do this within my top level file itself? or create a new file for this mapping? Thanks, Raj From newsfish@newsfish Thu Aug 1 00:36:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: FIFO with different widths for input and output Date: Tue, 5 Apr 2016 02:38:41 -0400 Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <7d795667-00fd-4d43-88aa-2aea2599654c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Apr 2016 06:35:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="733a187b11a19c9739e0fbc159757161"; logging-data="13830"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19qtmJN7IB52ioaIjVTe51B" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 In-Reply-To: <7d795667-00fd-4d43-88aa-2aea2599654c@googlegroups.com> Cancel-Lock: sha1:2vz8tRzCPiQGozuRVnDvb9dJHAE= Xref: news.eternal-september.org comp.lang.vhdl:4331 On 4/5/2016 2:22 AM, rajesh.krissh@gmail.com wrote: > Thanks Rick, your suggestion worked well. And I was successfully able to implement it. > > I used a FIFO with a width of 128 bits and 16 locations wide. It reads 128 bits of data in 16 bit chunks. Then writes out 16 bits at once with the help of a counter which helps me slide the window to write out from this FIFO. After all the 128 bits are sent then the tail of the FIFO increments and starts sending from the next location. Great, I'm glad it worked for you! Care to share your code so we can see exactly what you did? -- Rick From newsfish@newsfish Thu Aug 1 00:36:29 2024 X-Received: by 10.66.141.74 with SMTP id rm10mr16082921pab.16.1459838516436; Mon, 04 Apr 2016 23:41:56 -0700 (PDT) X-Received: by 10.50.43.194 with SMTP id y2mr254575igl.9.1459838516401; Mon, 04 Apr 2016 23:41:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!nt3no7874639igb.0!news-out.google.com!u9ni529igk.0!nntp.google.com!nt3no7874629igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Apr 2016 23:41:55 -0700 (PDT) In-Reply-To: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.171.36.203; posting-account=e0-vQwoAAAAdQ6zc2e5-mNOquvinr06- NNTP-Posting-Host: 70.171.36.203 References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f6696ac-cb1c-4941-92f9-f79755d0dbb4@googlegroups.com> Subject: Re: Verilog module in VHDL for Altera devices From: rajesh.krissh@gmail.com Injection-Date: Tue, 05 Apr 2016 06:41:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4332 On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: > I found a verilog core which performs the task I want and I wish to use it within my VHDL module. > > Is such a functionality possible? If yes, what all additional steps would be required? > > I found this source http://quartushelp.altera.com/14.1/mergedProjects/hdl/vlog/vlog_file_mixed_lang.htm > > which tells me that I have to declare components within Verilog in the VHDL module, which creates a portmap. > > My question here is, do I do this within my top level file itself? or create a new file for this mapping? > > Thanks, > Raj And also while portmapping if a signal is input in the Verilog core, then I should make it output where I will be doing the port maps. Right? From newsfish@newsfish Thu Aug 1 00:36:30 2024 X-Received: by 10.182.110.197 with SMTP id ic5mr5352595obb.5.1459853147720; Tue, 05 Apr 2016 03:45:47 -0700 (PDT) X-Received: by 10.50.102.97 with SMTP id fn1mr270649igb.1.1459853147625; Tue, 05 Apr 2016 03:45:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!nt3no7936170igb.0!news-out.google.com!ha2ni118igb.0!nntp.google.com!nt3no7936160igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Apr 2016 03:45:47 -0700 (PDT) In-Reply-To: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> Subject: Re: Verilog module in VHDL for Altera devices From: KJ Injection-Date: Tue, 05 Apr 2016 10:45:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4333 On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: > My question here is, do I do this within my top level file itself? or create a new file for this mapping? You simply instantiate the Verilog module as if it was a VHDL entity. Nothing special. Kevin From newsfish@newsfish Thu Aug 1 00:36:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Verilog module in VHDL for Altera devices Newsgroups: comp.lang.vhdl References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 05 Apr 2016 11:43:08 GMT Lines: 20 Message-ID: <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: a05176ef.news.astraweb.com X-Trace: DXC=Qi>]gm@=1[6YUQJRTa54B1L?0kYOcDh@:KF7Mk<5A6i5E3=kG9hhb72HI6bY5_;Lh9EBe]G`V^KX7AlHK^XF1Vb;;Jof<\?B^n: Xref: news.eternal-september.org comp.lang.vhdl:4334 On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: > On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: >> My question here is, do I do this within my top level file itself? or >> create a new file for this mapping? > > You simply instantiate the Verilog module as if it was a VHDL entity. > Nothing special. I wish that were true. The last time I tried Quartus, entity instantiation of Verilog in VHDL didn't work; component instantiation was required. I think Vivado is similarly broken, which is quite sad because entity instantiation of Verilog in VHDL worked worked quite well in ISE ten years ago. Regards, Allan From newsfish@newsfish Thu Aug 1 00:36:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Tue, 5 Apr 2016 11:28:14 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Apr 2016 15:24:55 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="30848"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/QIaMBzXRWdaUO+pd927rh" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 In-Reply-To: <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Cancel-Lock: sha1:Q1fba3cCfyeMwvG+AFTF5MQhCbU= Xref: news.eternal-september.org comp.lang.vhdl:4335 On 4/5/2016 7:43 AM, Allan Herriman wrote: > On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: > >> On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: >>> My question here is, do I do this within my top level file itself? or >>> create a new file for this mapping? >> >> You simply instantiate the Verilog module as if it was a VHDL entity. >> Nothing special. > > I wish that were true. > > The last time I tried Quartus, entity instantiation of Verilog in VHDL > didn't work; component instantiation was required. What is "entity instantiation"??? -- Rick From newsfish@newsfish Thu Aug 1 00:36:30 2024 X-Received: by 10.182.103.138 with SMTP id fw10mr17171834obb.47.1459870838867; Tue, 05 Apr 2016 08:40:38 -0700 (PDT) X-Received: by 10.50.153.109 with SMTP id vf13mr328344igb.10.1459870838840; Tue, 05 Apr 2016 08:40:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!nt3no8012629igb.0!news-out.google.com!ha2ni139igb.0!nntp.google.com!gy3no371132igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Apr 2016 08:40:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.227.108.57; posting-account=e0-vQwoAAAAdQ6zc2e5-mNOquvinr06- NNTP-Posting-Host: 128.227.108.57 References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <16c4f828-450d-4df4-9e94-1f860158d343@googlegroups.com> Subject: Re: Verilog module in VHDL for Altera devices From: rajesh.krissh@gmail.com Injection-Date: Tue, 05 Apr 2016 15:40:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4336 On Tuesday, April 5, 2016 at 11:28:15 AM UTC-4, rickman wrote: > On 4/5/2016 7:43 AM, Allan Herriman wrote: > > On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: > > > >> On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: > >>> My question here is, do I do this within my top level file itself? or > >>> create a new file for this mapping? > >> > >> You simply instantiate the Verilog module as if it was a VHDL entity. > >> Nothing special. > > > > I wish that were true. > > > > The last time I tried Quartus, entity instantiation of Verilog in VHDL > > didn't work; component instantiation was required. > > What is "entity instantiation"??? > > > -- > > Rick library IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; entity FFT_TOP is port ( CK : in std_logic; RT : in std_logic; ED : in std_logic; START : in std_logic; SHIFT : in std_logic_vector(3 downto 0); DR : in std_logic_vector(15 downto 0); DI : in std_logic_vector(15 downto 0); RDY : out std_logic; OVF1 : out std_logic; OVF2 : out std_logic; ADDR : out std_logic_vector(7 downto 0); DOR : out std_logic_vector(15 downto 0); DOI : out std_logic_vector(15 downto 0) ); end FFT_TOP; architecture arch of FFT_TOP is component FFT256 port ( CLK : in std_logic; RST : in std_logic; ED : in std_logic; START : in std_logic; SHIFT : in std_logic_vector(3 downto 0); DR : in std_logic_vector(15 downto 0); DI : in std_logic_vector(15 downto 0); RDY : out std_logic; OVF1 : out std_logic; OVF2 : out std_logic; ADDR : out std_logic_vector(7 downto 0); DOR : out std_logic_vector(15 downto 0); DOI : out std_logic_vector(15 downto 0) ); end component; signal my_CLK, my_RST, my_ED, my_START, my_RDY, my_OVF1, my_OVF2 : std_logic; signal my_DR, my_DI, my_DOR, my_DOI : std_logic_vector(15 downto 0); signal my_SHIFT : std_logic_vector(3 downto 0); signal my_ADDR : std_logic_vector(7 downto 0); begin i : FFT256 port map ( CLK => CK, RST => RT, ED => ED, START => START, SHIFT => SHIFT, DR => DR, DI => DI, RDY => RDY, OVF1 => OVF1, OVF2 => OVF2, ADDR => ADDR, DOR => DOR, DOI => DOI ); end arch; This works! We just need to use the same name for the signals used in verilog. From newsfish@newsfish Thu Aug 1 00:36:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Tue, 5 Apr 2016 13:35:57 -0400 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> <16c4f828-450d-4df4-9e94-1f860158d343@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Apr 2016 17:32:38 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="30212"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19jgZ+EPNKtn7m2PntcHv0+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 In-Reply-To: <16c4f828-450d-4df4-9e94-1f860158d343@googlegroups.com> Cancel-Lock: sha1:7RRtAqvlA96Ssl7xe6T99PGUZDg= Xref: news.eternal-september.org comp.lang.vhdl:4337 On 4/5/2016 11:40 AM, rajesh.krissh@gmail.com wrote: > On Tuesday, April 5, 2016 at 11:28:15 AM UTC-4, rickman wrote: >> On 4/5/2016 7:43 AM, Allan Herriman wrote: >>> On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: >>> >>>> On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: >>>>> My question here is, do I do this within my top level file itself? or >>>>> create a new file for this mapping? >>>> >>>> You simply instantiate the Verilog module as if it was a VHDL entity. >>>> Nothing special. >>> >>> I wish that were true. >>> >>> The last time I tried Quartus, entity instantiation of Verilog in VHDL >>> didn't work; component instantiation was required. >> >> What is "entity instantiation"??? >> >> >> -- >> >> Rick > > library IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > USE IEEE.NUMERIC_STD.ALL; > > entity FFT_TOP is > port ( > CK : in std_logic; > RT : in std_logic; > ED : in std_logic; > START : in std_logic; > SHIFT : in std_logic_vector(3 downto 0); > DR : in std_logic_vector(15 downto 0); > DI : in std_logic_vector(15 downto 0); > RDY : out std_logic; > OVF1 : out std_logic; > OVF2 : out std_logic; > ADDR : out std_logic_vector(7 downto 0); > DOR : out std_logic_vector(15 downto 0); > DOI : out std_logic_vector(15 downto 0) > ); > end FFT_TOP; > > architecture arch of FFT_TOP is > component FFT256 > port ( > CLK : in std_logic; > RST : in std_logic; > ED : in std_logic; > START : in std_logic; > SHIFT : in std_logic_vector(3 downto 0); > DR : in std_logic_vector(15 downto 0); > DI : in std_logic_vector(15 downto 0); > RDY : out std_logic; > OVF1 : out std_logic; > OVF2 : out std_logic; > ADDR : out std_logic_vector(7 downto 0); > DOR : out std_logic_vector(15 downto 0); > DOI : out std_logic_vector(15 downto 0) > ); > end component; > > signal my_CLK, my_RST, my_ED, my_START, my_RDY, my_OVF1, my_OVF2 : std_logic; > signal my_DR, my_DI, my_DOR, my_DOI : std_logic_vector(15 downto 0); > signal my_SHIFT : std_logic_vector(3 downto 0); > signal my_ADDR : std_logic_vector(7 downto 0); > > begin > i : FFT256 port map > ( > CLK => CK, > RST => RT, > ED => ED, > START => START, > SHIFT => SHIFT, > DR => DR, > DI => DI, > RDY => RDY, > OVF1 => OVF1, > OVF2 => OVF2, > ADDR => ADDR, > DOR => DOR, > DOI => DOI > ); > end arch; > > > > This works! We just need to use the same name for the signals used in verilog. This looks like a component instantiation. I don't see how it is different. -- Rick From newsfish@newsfish Thu Aug 1 00:36:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Tue, 5 Apr 2016 18:26:18 -0000 (UTC) Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Apr 2016 18:26:18 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="11907"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18m8HO7l4u3d2NInifzc7bB" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:oBL5MSU6nT60cgyhzS6g5U+2qGs= Xref: news.eternal-september.org comp.lang.vhdl:4338 rickman wrote: > On 4/5/2016 7:43 AM, Allan Herriman wrote: >> On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: >> >>> On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: >>>> My question here is, do I do this within my top level file itself? or >>>> create a new file for this mapping? >>> >>> You simply instantiate the Verilog module as if it was a VHDL entity. >>> Nothing special. >> >> I wish that were true. >> >> The last time I tried Quartus, entity instantiation of Verilog in VHDL >> didn't work; component instantiation was required. > > What is "entity instantiation"??? > > INST_BOB: entity work.bob(Bobhavioral) port map (...); With no component declaration. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Tue, 5 Apr 2016 14:50:27 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Apr 2016 18:47:09 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="17248"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+QTDs/04qS97MHEBFbJ0g3" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 In-Reply-To: Cancel-Lock: sha1:cOpv5IACX2Nc0KuoSC1GrokZf5Q= Xref: news.eternal-september.org comp.lang.vhdl:4339 On 4/5/2016 2:26 PM, Rob Gaddi wrote: > rickman wrote: > >> On 4/5/2016 7:43 AM, Allan Herriman wrote: >>> On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: >>> >>>> On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: >>>>> My question here is, do I do this within my top level file itself? or >>>>> create a new file for this mapping? >>>> >>>> You simply instantiate the Verilog module as if it was a VHDL entity. >>>> Nothing special. >>> >>> I wish that were true. >>> >>> The last time I tried Quartus, entity instantiation of Verilog in VHDL >>> didn't work; component instantiation was required. >> >> What is "entity instantiation"??? >> >> > > INST_BOB: entity work.bob(Bobhavioral) > port map (...); > > With no component declaration. Ok, I did a little reading on this and I think I understand. I'm amazed I never came across this before. So as long as the entity/architecture is compiled and visible the component declaration is not required. Other than a packages, I don't typically put more than one entity in a file. But I see now this is not really a limitation if I understand correctly, entity instantiation can still be used. I will try this with my next project. The duplication of the component declaration is a bit absurd really. -- Rick From newsfish@newsfish Thu Aug 1 00:36:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Tue, 5 Apr 2016 19:28:07 -0000 (UTC) Organization: A noiseless patient Spider Lines: 49 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Apr 2016 19:28:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="28146"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/3OAShZhIHSEM/R+x5DUug" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:eCCk2bA9CwFFzYzF3hxgCpsallc= Xref: news.eternal-september.org comp.lang.vhdl:4340 rickman wrote: > On 4/5/2016 2:26 PM, Rob Gaddi wrote: >> rickman wrote: >> >>> On 4/5/2016 7:43 AM, Allan Herriman wrote: >>>> On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: >>>> >>>>> On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: >>>>>> My question here is, do I do this within my top level file itself? or >>>>>> create a new file for this mapping? >>>>> >>>>> You simply instantiate the Verilog module as if it was a VHDL entity. >>>>> Nothing special. >>>> >>>> I wish that were true. >>>> >>>> The last time I tried Quartus, entity instantiation of Verilog in VHDL >>>> didn't work; component instantiation was required. >>> >>> What is "entity instantiation"??? >>> >>> >> >> INST_BOB: entity work.bob(Bobhavioral) >> port map (...); >> >> With no component declaration. > > Ok, I did a little reading on this and I think I understand. I'm amazed > I never came across this before. So as long as the entity/architecture > is compiled and visible the component declaration is not required. > > Other than a packages, I don't typically put more than one entity in a > file. But I see now this is not really a limitation if I understand > correctly, entity instantiation can still be used. I will try this with > my next project. The duplication of the component declaration is a bit > absurd really. > The one limitation is that direct entity instantiation plays very Verilogily with simulation. With a component declaration, if you recompile the thing you're instantiating you can just restart the simulation and go. With direct entities you have to recompile your way everything back up the way. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Tue, 05 Apr 2016 15:36:22 -0400 Organization: Alacron, Inc. Lines: 52 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Apr 2016 19:33:09 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="29472"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/kzdZPKZgddU0iTpIzeb0qoM2ILtpNCno=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.24) Gecko/20100228 Thunderbird/2.0.0.24 Mnenhy/0.7.6.666 In-Reply-To: Cancel-Lock: sha1:yHEE4b15JSm0X9bz4cNYlsRBLwk= Xref: news.eternal-september.org comp.lang.vhdl:4341 rickman wrote: > On 4/5/2016 2:26 PM, Rob Gaddi wrote: >> rickman wrote: >> >>> On 4/5/2016 7:43 AM, Allan Herriman wrote: >>>> On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: >>>> >>>>> On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: >>>>>> My question here is, do I do this within my top level file itself? or >>>>>> create a new file for this mapping? >>>>> >>>>> You simply instantiate the Verilog module as if it was a VHDL entity. >>>>> Nothing special. >>>> >>>> I wish that were true. >>>> >>>> The last time I tried Quartus, entity instantiation of Verilog in VHDL >>>> didn't work; component instantiation was required. >>> >>> What is "entity instantiation"??? >>> >>> >> >> INST_BOB: entity work.bob(Bobhavioral) >> port map (...); >> >> With no component declaration. > > Ok, I did a little reading on this and I think I understand. I'm amazed > I never came across this before. So as long as the entity/architecture > is compiled and visible the component declaration is not required. > > Other than a packages, I don't typically put more than one entity in a > file. But I see now this is not really a limitation if I understand > correctly, entity instantiation can still be used. I will try this with > my next project. The duplication of the component declaration is a bit > absurd really. > The entity doesn't need to be in a particular file. It just needs to compile into a known library ("work" in Rob's example). In Xilinx ISE, all Verilog modules compile into library "work" and there is no way to change it. On the other hand, Verilog has no concept of libraries, so it makes sense that you'd place them all together to allow connectivity within the Verilog part of a design. The last time I had a project where VHDL needed to instantiate Verilog modules in ISE, I seem to remember I still needed component instantiation. That was probably around ISE version 10.1, though. I haven't had the pleasure (pain?) of working with Vivado yet. -- Gabor From newsfish@newsfish Thu Aug 1 00:36:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Verilog module in VHDL for Altera devices Newsgroups: comp.lang.vhdl References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 06 Apr 2016 10:25:22 GMT Lines: 57 Message-ID: <5704e412$0$1586$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: e00afa49.news.astraweb.com X-Trace: DXC=nGGPE7EGA_PJ[9olalG_WRL?0kYOcDh@Z]WEZ@Q1WnGUE3=kG9hhb7RHI6bY5_;LhYEBe]G`V^KXWA1:H5mgg>@]dYf\g8mi1aP Xref: news.eternal-september.org comp.lang.vhdl:4342 On Tue, 05 Apr 2016 14:50:27 -0400, rickman wrote: > On 4/5/2016 2:26 PM, Rob Gaddi wrote: >> rickman wrote: >> >>> On 4/5/2016 7:43 AM, Allan Herriman wrote: >>>> On Tue, 05 Apr 2016 03:45:47 -0700, KJ wrote: >>>> >>>>> On Tuesday, April 5, 2016 at 2:36:02 AM UTC-4, Raj wrote: >>>>>> My question here is, do I do this within my top level file itself? >>>>>> or create a new file for this mapping? >>>>> >>>>> You simply instantiate the Verilog module as if it was a VHDL >>>>> entity. >>>>> Nothing special. >>>> >>>> I wish that were true. >>>> >>>> The last time I tried Quartus, entity instantiation of Verilog in >>>> VHDL didn't work; component instantiation was required. >>> >>> What is "entity instantiation"??? >>> >>> >>> >> INST_BOB: entity work.bob(Bobhavioral) >> port map (...); >> >> With no component declaration. > > Ok, I did a little reading on this and I think I understand. I'm amazed > I never came across this before. So as long as the entity/architecture > is compiled and visible the component declaration is not required. > > Other than a packages, I don't typically put more than one entity in a > file. But I see now this is not really a limitation if I understand > correctly, entity instantiation can still be used. I will try this with > my next project. The duplication of the component declaration is a bit > absurd really. Direct entity instantiation is one of those things that most designers switch over to using the moment they discover it, and never go back. The compile order dependencies are a small price to pay for the elimination of component declarations. It was introduced to the language in the 1993 revision. Tool support wasn't reliable for quite a few years though. I started using it in 2001 or 2002. (Google says my first c.l.v post about it dates from 2002.) One of the best pieces of advice one can give regarding VHDL (or Verilog for that matter) is to ignore any training material that was written last century. Regards, Allan From newsfish@newsfish Thu Aug 1 00:36:33 2024 X-Received: by 10.13.225.211 with SMTP id k202mr19907293ywe.40.1459939325437; Wed, 06 Apr 2016 03:42:05 -0700 (PDT) X-Received: by 10.50.98.70 with SMTP id eg6mr465341igb.4.1459939325264; Wed, 06 Apr 2016 03:42:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!10no658523qgg.1!news-out.google.com!ha2ni189igb.0!nntp.google.com!nt3no8248131igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 6 Apr 2016 03:42:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Verilog module in VHDL for Altera devices From: KJ Injection-Date: Wed, 06 Apr 2016 10:42:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4343 On Tuesday, April 5, 2016 at 3:31:25 PM UTC-4, Rob Gaddi wrote: >=20 > The one limitation is that direct entity instantiation plays very > Verilogily with simulation. With a component declaration, if you > recompile the thing you're instantiating you can just restart the > simulation and go. With direct entities you have to recompile your way > everything back up the way. >=20 That has not been my experience with direct entity instantiation. If I cha= nge something, I just recompile the file that changed and go. If I change = something on the entity, like add/remove a signal, then I also have to reco= mpile the file(s) that instantiate that entity. But that behavior I don't = think is any different than if a component is declared. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:36:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Wed, 06 Apr 2016 14:44:16 +0100 Organization: TRW Conekt Lines: 31 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain X-Trace: individual.net ZVbzh9ZqoHi+zdbT5tzBoAMIKn+MZhTiqW569991HA5tIOgk8= Cancel-Lock: sha1:UBslWb8EGVonevs3vEsCkUPESKU= sha1:Qf+q9Fzi+DPBIF0QwIjwqzdHB8I= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.0.50 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:4344 KJ writes: > On Tuesday, April 5, 2016 at 3:31:25 PM UTC-4, Rob Gaddi wrote: >> >> The one limitation is that direct entity instantiation plays very >> Verilogily with simulation. With a component declaration, if you >> recompile the thing you're instantiating you can just restart the >> simulation and go. With direct entities you have to recompile your way >> everything back up the way. >> > > That has not been my experience with direct entity instantiation. If I change something, I just recompile the file that changed and > go. If I change something on the entity, like add/remove a signal, then I also have to recompile the file(s) that instantiate that > entity. But that behavior I don't think is any different than if a component is declared. > If you have your entity and architecture in the same file (as many people do), unless you can instruct the compiler to only compile the architecture, you end up with the effect that is described (having to recompile all the way up). vcom -just b something.vhd does the trick with Modelsim. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Thu Aug 1 00:36:33 2024 X-Received: by 10.140.156.139 with SMTP id c133mr20293879qhc.4.1459954901271; Wed, 06 Apr 2016 08:01:41 -0700 (PDT) X-Received: by 10.50.108.115 with SMTP id hj19mr408913igb.3.1459954901125; Wed, 06 Apr 2016 08:01:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!10no692299qgg.1!news-out.google.com!u9ni639igk.0!nntp.google.com!gy3no521049igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 6 Apr 2016 08:01:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Verilog module in VHDL for Altera devices From: KJ Injection-Date: Wed, 06 Apr 2016 15:01:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3256 X-Received-Body-CRC: 2321729332 Xref: news.eternal-september.org comp.lang.vhdl:4345 On Wednesday, April 6, 2016 at 9:44:20 AM UTC-4, Martin Thompson wrote: > KJ writes: > > > On Tuesday, April 5, 2016 at 3:31:25 PM UTC-4, Rob Gaddi wrote: > >> > >> The one limitation is that direct entity instantiation plays very > >> Verilogily with simulation. With a component declaration, if you > >> recompile the thing you're instantiating you can just restart the > >> simulation and go. With direct entities you have to recompile your way > >> everything back up the way. > >> > > > > That has not been my experience with direct entity instantiation. If I change something, I just recompile the file that changed and > > go. If I change something on the entity, like add/remove a signal, then I also have to recompile the file(s) that instantiate that > > entity. But that behavior I don't think is any different than if a component is declared. > > > > If you have your entity and architecture in the same file (as many > people do), unless you can instruct the compiler to only compile the > architecture, you end up with the effect that is described (having to > recompile all the way up). > > vcom -just b something.vhd > > does the trick with Modelsim. > Cheers, > Martin > Interesting, but like I said, that has not been my experience. Except for unusual cases, I have entity/architecture in the same file, I use direct entity instantiation and I use Modelsim. When I only change the architecture the steps are: - Edit/Save - Click in the GUI to compile out of date files (which results in that one file getting compiled) - Restart sim with either 'do run.do' (which reinvokes vsim, logs signals, etc.) or 'restart -f; run -a' - Debug - Repeat until design is working I wonder what we're doing differently that I'm not having to compile back up to the top and others are. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:36:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Wed, 6 Apr 2016 15:52:00 -0000 (UTC) Organization: A noiseless patient Spider Lines: 50 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Wed, 6 Apr 2016 15:52:00 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="12592"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18q5E+c+7f1IDtJKMz10gA8" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:4m2Uo3RtTcz7BbnDbvNMqY2M/78= Xref: news.eternal-september.org comp.lang.vhdl:4346 KJ wrote: > On Wednesday, April 6, 2016 at 9:44:20 AM UTC-4, Martin Thompson wrote: >> KJ writes: >> >> > On Tuesday, April 5, 2016 at 3:31:25 PM UTC-4, Rob Gaddi wrote: >> >> >> >> The one limitation is that direct entity instantiation plays very >> >> Verilogily with simulation. With a component declaration, if you >> >> recompile the thing you're instantiating you can just restart the >> >> simulation and go. With direct entities you have to recompile your way >> >> everything back up the way. >> >> >> > >> > That has not been my experience with direct entity instantiation. If I change something, I just recompile the file that changed and >> > go. If I change something on the entity, like add/remove a signal, then I also have to recompile the file(s) that instantiate that >> > entity. But that behavior I don't think is any different than if a component is declared. >> > >> >> If you have your entity and architecture in the same file (as many >> people do), unless you can instruct the compiler to only compile the >> architecture, you end up with the effect that is described (having to >> recompile all the way up). >> >> vcom -just b something.vhd >> >> does the trick with Modelsim. >> Cheers, >> Martin >> > > Interesting, but like I said, that has not been my experience. Except for unusual cases, I have entity/architecture in the same file, I use direct entity instantiation and I use Modelsim. When I only change the architecture the steps are: > - Edit/Save > - Click in the GUI to compile out of date files (which results in that one file getting compiled) > - Restart sim with either 'do run.do' (which reinvokes vsim, logs signals, etc.) or 'restart -f; run -a' > - Debug > - Repeat until design is working > > I wonder what we're doing differently that I'm not having to compile back up to the top and others are. > > Kevin Jennings Now that's just very strange. Most of my experience has been on Active-HDL, but I recently switched over to Modelsim. I'll have to confirm at some point that what I remember being the case is the case. Since component declarations are terrible. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Thu, 14 Apr 2016 16:21:05 +0100 Organization: TRW Conekt Lines: 22 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain X-Trace: individual.net tK5VkMXHv5SgypuAyiXgzwoI/n8R2DhiDn0Ce/jIsY04cmD3Q= Cancel-Lock: sha1:1H3H4JbnhNzQ8TjwRbIGMSt4N9g= sha1:iI/QQv411y+2gWZnewin6V5mE84= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.0.50 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:4347 KJ writes: > > Interesting, but like I said, that has not been my experience. Except for unusual cases, I have entity/architecture in the same > file, I use direct entity instantiation and I use Modelsim. When I only change the architecture the steps are: > - Edit/Save > - Click in the GUI to compile out of date files (which results in that > one file getting compiled) That may be the difference, the GUI :) I tend to stick at the command line and just recompile the bits I know I'm working on (if it's only a couple of files) or run the Makefile which tends to compile everything. I'll have to check out the GUI option (although it runs counter to my ingrained habits of command-lining allt he time I can!) Thanks, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Thu Aug 1 00:36:34 2024 X-Received: by 10.98.12.66 with SMTP id u63mr11203204pfi.12.1460671581937; Thu, 14 Apr 2016 15:06:21 -0700 (PDT) X-Received: by 10.50.108.115 with SMTP id hj19mr35616igb.3.1460671581775; Thu, 14 Apr 2016 15:06:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!gy3no4083626igb.0!news-out.google.com!u9ni13igk.0!nntp.google.com!g8no1143730igr.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 Apr 2016 15:06:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:340d:5fc9:a82c:f202; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:340d:5fc9:a82c:f202 References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2ca26f1c-98b3-462c-a87e-e97e48ed3d4c@googlegroups.com> Subject: Re: Verilog module in VHDL for Altera devices From: KJ Injection-Date: Thu, 14 Apr 2016 22:06:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4348 On Thursday, April 14, 2016 at 11:21:09 AM UTC-4, Martin Thompson wrote: > KJ writes: >=20 > > > > Interesting, but like I said, that has not been my experience. Except = for unusual cases, I have entity/architecture in the same > > file, I use direct entity instantiation and I use Modelsim. When I onl= y change the architecture the steps are: > > - Edit/Save > > - Click in the GUI to compile out of date files (which results in that > > one file getting compiled) >=20 > That may be the difference, the GUI :) I tend to stick at the command > line and just recompile the bits I know I'm working on (if it's only a > couple of files) or run the Makefile which tends to compile everything. > I'll have to check out the GUI option (although it runs counter to my > ingrained habits of command-lining allt he time I can!) >=20 In that case, I would wager that the reason you're compiling files all the = way to the top is due to the make file. I'm guessing that file is setup wi= th dependency rules that if file X changes then you must also compile the p= arents/grandparents/etc of file X. The GUI is simply compiling the file(s)= that have changed since the last compile, there is no notion of dependenci= es for this operation. Kevin From newsfish@newsfish Thu Aug 1 00:36:35 2024 X-Received: by 10.140.42.43 with SMTP id b40mr2485178qga.9.1461084980918; Tue, 19 Apr 2016 09:56:20 -0700 (PDT) X-Received: by 10.50.150.5 with SMTP id ue5mr93112igb.5.1461084980869; Tue, 19 Apr 2016 09:56:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!7no4747801qgj.0!news-out.google.com!u9ni81igk.0!nntp.google.com!g8no4350163igr.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 19 Apr 2016 09:56:19 -0700 (PDT) In-Reply-To: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=186.109.205.100; posting-account=4RIwdAoAAADsHqtZf9W4Nyhv4q8dIoup NNTP-Posting-Host: 186.109.205.100 References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2b686876-af5a-4ef4-9e46-3b483793eea4@googlegroups.com> Subject: Re: Alliance CAD tool VHDL problem From: asrv1985@gmail.com Injection-Date: Tue, 19 Apr 2016 16:56:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4349 El viernes, 8 de mayo de 2015, 14:46:38 (UTC-3), yaser fathy escribi=F3: > Hello, >=20 > I'm learning an opensource cad tool called alliance , it takes a vhdl=20 > design and turns it into a wafer digital layout , its VHDL compiler is=20 > called SYF , the problem is that a code that compiled successfully on=20 > modelsim won't compile here , my VHDL is not very strong so I hope=20 > someone could give my an explanation : >=20 > the problem is with variable declaration >=20 > process(CS,wordin,reset) > variable addr : std_logic_vector (7 DOWNTO 0); > begin > ... >=20 > error : ILLEGAL DECLARATION > at the variable declaration line >=20 > any help ? Hi, maybe you code is wrong because you have to declare "variable" like "si= gnal" before the "begin" statement in the architecture declaration and uses= in the process, you don't forget that Alliance use VHDL 86 standard. I hop= e I was usefully. Sorry for my spanglish. Best Regards Andr=E9s Rojas From newsfish@newsfish Thu Aug 1 00:36:35 2024 X-Received: by 10.182.185.50 with SMTP id ez18mr6094908obc.2.1461169057883; Wed, 20 Apr 2016 09:17:37 -0700 (PDT) X-Received: by 10.50.150.5 with SMTP id ue5mr286408igb.5.1461169057765; Wed, 20 Apr 2016 09:17:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!g8no4843958igr.0!news-out.google.com!j7ni12igm.0!nntp.google.com!gy3no6638203igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Apr 2016 09:17:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.164.85.79; posting-account=eoHi5AoAAAANqf7F8ob2rBA20IKaU8kM NNTP-Posting-Host: 46.164.85.79 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Adding internal signals in Modelsim From: ar.kazemy@gmail.com Injection-Date: Wed, 20 Apr 2016 16:17:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3400 X-Received-Body-CRC: 3345564281 Xref: news.eternal-september.org comp.lang.vhdl:4350 On Tuesday, January 6, 2004 at 10:45:12 AM UTC+3:30, ALuPin wrote: > Dear Sir or Madam, >=20 > I have a question concerning Modelsim: >=20 > In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"=20 > as U1=20 >=20 > In the attached macro I add waves. These waves are inputs and outputs > of the module "packetfile_ctrl.vhd". > But what if I want to view internal signals? For example the internal > signal > last_block: > If I write the following command in my macro I do not get a wave of > this signal > "add wave sim:/tb_packetfile_ctrl/u1/last_block" > So how can I add an internal signal? > Is there an alternative way without using the macro (this means=20 > adding a wave belatedly when the waveform - editor is already opened) > ? >=20 > Thank you for your help. >=20 > Best regards > Andr=E9s V=E1zquez > G&D >=20 > MACRO: > cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim=20 > vlib modelsim_work > vmap work modelsim_work > vsim -sdftyp /U1=3Dpacketfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL > vcom -93 -reportprogress 300 -work work > {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CT= RL.vho} > vcom -93 -reportprogress 300 -work work > {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE= _CTRL.vhd} > view signals > view wave > vsim work.TB_PACKETFILE_CTRL > add wave sim:/tb_packetfile_ctrl/u1/P_clk_in > add wave sim:/tb_packetfile_ctrl/u1/P_clk_out > add wave sim:/tb_packetfile_ctrl/u1/Reset > add wave sim:/tb_packetfile_ctrl/u1/Write > add wave sim:/tb_packetfile_ctrl/u1/Read > add wave sim:/tb_packetfile_ctrl/u1/last_block ????????????????? To be able to add internal module signals in ModelSim 10.1c (for example wh= en simulating a test bench module which has not any I/O pins/ports, the int= ernal signals are necessary to be observable) as follows: 1- Start simulation from the Simulate menu by clicking option "Start Simula= tion..." (not by double clicking on the module). 2- In the dialog which opens to ask the model/module to simulate, click on = "Optimization Options..." button. in the dialog which opens in the Visibili= ty tab check the "Apply the full visibility to all modules (full debug mode= )". From newsfish@newsfish Thu Aug 1 00:36:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Thu, 21 Apr 2016 11:52:57 +0100 Organization: TRW Conekt Lines: 29 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> <2ca26f1c-98b3-462c-a87e-e97e48ed3d4c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain X-Trace: individual.net oXzWO6bKX1geiDojohfs9A5fbonySpR7cgQ3bW3MJPNBOpnSs= Cancel-Lock: sha1:z2bVEUIgMxg6KMhNt/f2yP3R4Mg= sha1:MomraTEgSqmpc8P9f9F/N1FuuFk= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.0.50 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:4351 KJ writes: > I'm guessing > that file is setup with dependency rules that if file X changes then > you must also compile the parents/grandparents/etc of file X. Agreed. Make has no concept of design units within files or the ability to only compile parts of the file. Make is not ideally suited to VHDL work :) > The GUI is simply compiling the file(s) that have changed since the last compile, there is no notion of dependencies for this > operation. I'd go further - I think the GUI is only compiling *parts* of the file (like I do from the command-line) as if it compiled the whole file, it would recompile the entity which would then trigger an "upward flow" of recompiles (which you are not observing). Does the GUI compile show what commands it is executing anywhere? Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Thu Aug 1 00:36:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Adding internal signals in Modelsim Date: Thu, 21 Apr 2016 11:54:01 -0400 Organization: Alacron, Inc. Lines: 57 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 21 Apr 2016 15:50:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="23973"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/tQfgm+s7b88d4/hD11zNkmtt18vWUpMc=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.24) Gecko/20100228 Thunderbird/2.0.0.24 Mnenhy/0.7.6.666 In-Reply-To: Cancel-Lock: sha1:EO64l4NBIvU7KtiOW6Gjv8SxB1A= Xref: news.eternal-september.org comp.lang.vhdl:4352 ar.kazemy@gmail.com wrote: > On Tuesday, January 6, 2004 at 10:45:12 AM UTC+3:30, ALuPin wrote: >> Dear Sir or Madam, >> >> I have a question concerning Modelsim: >> >> In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd" >> as U1 >> >> In the attached macro I add waves. These waves are inputs and outputs >> of the module "packetfile_ctrl.vhd". >> But what if I want to view internal signals? For example the internal >> signal >> last_block: >> If I write the following command in my macro I do not get a wave of >> this signal >> "add wave sim:/tb_packetfile_ctrl/u1/last_block" >> So how can I add an internal signal? >> Is there an alternative way without using the macro (this means >> adding a wave belatedly when the waveform - editor is already opened) >> ? >> >> Thank you for your help. >> >> Best regards >> Andrs Vzquez >> G&D >> >> MACRO: >> cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim >> vlib modelsim_work >> vmap work modelsim_work >> vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL >> vcom -93 -reportprogress 300 -work work >> {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho} >> vcom -93 -reportprogress 300 -work work >> {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd} >> view signals >> view wave >> vsim work.TB_PACKETFILE_CTRL >> add wave sim:/tb_packetfile_ctrl/u1/P_clk_in >> add wave sim:/tb_packetfile_ctrl/u1/P_clk_out >> add wave sim:/tb_packetfile_ctrl/u1/Reset >> add wave sim:/tb_packetfile_ctrl/u1/Write >> add wave sim:/tb_packetfile_ctrl/u1/Read >> add wave sim:/tb_packetfile_ctrl/u1/last_block ????????????????? > > To be able to add internal module signals in ModelSim 10.1c (for example when simulating a test bench module which has not any I/O pins/ports, the internal signals are necessary to be observable) as follows: > > 1- Start simulation from the Simulate menu by clicking option "Start Simulation..." (not by double clicking on the module). > > 2- In the dialog which opens to ask the model/module to simulate, click on "Optimization Options..." button. in the dialog which opens in the Visibility tab check the "Apply the full visibility to all modules (full debug mode)". I don't think Modelsim 10.1 was around in 2004 when that post was written :) -- Gabor From newsfish@newsfish Thu Aug 1 00:36:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer03.am1!peering.am1!peer01.fr7!news.highwinds-media.com!post01.fr7!fx37.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Verilog module in VHDL for Altera devices References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> <2ca26f1c-98b3-462c-a87e-e97e48ed3d4c@googlegroups.com> Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 160421-0, 21/04/2016), Outbound message X-Antivirus-Status: Clean Lines: 41 Message-ID: NNTP-Posting-Host: 81.107.0.228 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1461255185 81.107.0.228 (Thu, 21 Apr 2016 16:13:05 UTC) NNTP-Posting-Date: Thu, 21 Apr 2016 16:13:05 UTC Organization: virginmedia.com Date: Thu, 21 Apr 2016 17:13:03 +0100 X-Received-Body-CRC: 400666767 X-Received-Bytes: 3120 Xref: news.eternal-september.org comp.lang.vhdl:4353 On 21/04/2016 11:52, Martin Thompson wrote: > KJ writes: > > > >> I'm guessing >> that file is setup with dependency rules that if file X changes then >> you must also compile the parents/grandparents/etc of file X. > > Agreed. Make has no concept of design units within files or the ability > to only compile parts of the file. Make is not ideally suited to VHDL > work :) > >> The GUI is simply compiling the file(s) that have changed since the last compile, there is no notion of dependencies for this >> operation. > > I'd go further - I think the GUI is only compiling *parts* of the file > (like I do from the command-line) as if it compiled the whole file, it > would recompile the entity which would then trigger an "upward flow" of > recompiles (which you are not observing). > > Does the GUI compile show what commands it is executing anywhere? Transcript window? Seriously, I assume you are using Modelsim project files? If so then I would strongly recommend you switch to .do/.tcl files as it will make your life a lot easier. If compilation takes a long time then you can use vmake although I believe you need to switch back to the old library format to use them (I might be wrong). Just add the win32pe directory to your search path and you can use simple batch/bash/.. scripts to compile and run your code. If you want to use some Tcl in your script then you can use vsim -c -do "-do mycompile.tcl;quit -f" type of commands. Hans www.ht-lab.com > Martin > > From newsfish@newsfish Thu Aug 1 00:36:36 2024 X-Received: by 10.50.39.43 with SMTP id m11mr616801igk.12.1461285287231; Thu, 21 Apr 2016 17:34:47 -0700 (PDT) X-Received: by 10.50.182.7 with SMTP id ea7mr21439igc.2.1461285287210; Thu, 21 Apr 2016 17:34:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!sq19no64707igc.0!news-out.google.com!uv8ni91igb.0!nntp.google.com!g8no5277280igr.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 21 Apr 2016 17:34:46 -0700 (PDT) In-Reply-To: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.53.155.185; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.53.155.185 References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Alliance CAD tool VHDL problem From: stchebel@gmail.com Injection-Date: Fri, 22 Apr 2016 00:34:47 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 25 Xref: news.eternal-september.org comp.lang.vhdl:4354 W dniu pi=C4=85tek, 8 maja 2015 19:46:38 UTC+2 u=C5=BCytkownik yaser fathy = napisa=C5=82: > Hello, >=20 > I'm learning an opensource cad tool called alliance , it takes a vhdl=20 > design and turns it into a wafer digital layout , its VHDL compiler is=20 > called SYF , the problem is that a code that compiled successfully on=20 > modelsim won't compile here , my VHDL is not very strong so I hope=20 > someone could give my an explanation : >=20 > the problem is with variable declaration >=20 > process(CS,wordin,reset) > variable addr : std_logic_vector (7 DOWNTO 0); > begin > ... >=20 > error : ILLEGAL DECLARATION > at the variable declaration line >=20 > any help ? Try: shared variable addr : std_logic_vector (7 DOWNTO 0); in architecture declaration. From newsfish@newsfish Thu Aug 1 00:36:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Verilog module in VHDL for Altera devices Newsgroups: comp.lang.vhdl References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> <2ca26f1c-98b3-462c-a87e-e97e48ed3d4c@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 22 Apr 2016 10:37:27 GMT Lines: 43 Message-ID: <5719fee7$0$1518$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: ef676509.news.astraweb.com X-Trace: DXC=fM[hP`WGGM`:LXj0CA`3KmL?0kYOcDh@j0V9>>T5iDBa2243=N_ On 21/04/2016 11:52, Martin Thompson wrote: >> KJ writes: >> >> >> >>> I'm guessing that file is setup with dependency rules that if file X >>> changes then you must also compile the parents/grandparents/etc of >>> file X. >> >> Agreed. Make has no concept of design units within files or the >> ability to only compile parts of the file. Make is not ideally suited >> to VHDL work :) >> >>> The GUI is simply compiling the file(s) that have changed since the >>> last compile, there is no notion of dependencies for this operation. >> >> I'd go further - I think the GUI is only compiling *parts* of the file >> (like I do from the command-line) as if it compiled the whole file, it >> would recompile the entity which would then trigger an "upward flow" of >> recompiles (which you are not observing). >> >> Does the GUI compile show what commands it is executing anywhere? > > Transcript window? > > Seriously, I assume you are using Modelsim project files? If so then I > would strongly recommend you switch to .do/.tcl files as it will make > your life a lot easier. If compilation takes a long time then you can > use vmake although I believe you need to switch back to the old library > format to use them (I might be wrong). Just add the win32pe directory to > your search path and you can use simple batch/bash/.. scripts to compile > and run your code. If you want to use some Tcl in your script then you > can use vsim -c -do "-do mycompile.tcl;quit -f" type of commands. How do you switch back to the old library format? I stopped using makefiles with Modelsim once they put the entire library in a single file. Version 10.1something I think it was. Thanks, Allan From newsfish@newsfish Thu Aug 1 00:36:37 2024 X-Received: by 10.129.132.136 with SMTP id u130mr6912881ywf.11.1461333304337; Fri, 22 Apr 2016 06:55:04 -0700 (PDT) X-Received: by 10.50.57.19 with SMTP id e19mr73388igq.6.1461333304299; Fri, 22 Apr 2016 06:55:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!7no5291169qgj.0!news-out.google.com!uv8ni122igb.0!nntp.google.com!sq19no123577igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 Apr 2016 06:55:03 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Testbench architecture/structure is critical for Overview, Readbility, Maintability, Extendibility and Reuse From: espen.tallaksen@bitvis.no Injection-Date: Fri, 22 Apr 2016 13:55:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 24 Xref: news.eternal-september.org comp.lang.vhdl:4356 FPGA development efficiency and quality is extremely dependent on the struc= ture and quality of your TB architecture. Verification time could easily di= ffer by a factor of 2 or 3 for medium to high complexity modules/FPGAs - or= even for low complexity design with cycle related corner cases. We all know that the design architecture is critical for an FPGA or a compl= ex module, but most designers seem to ignore that knowledge when it comes t= o making a good VHDL testbench. UVVM (Universal VHDL Verification Component Framework Methodology) is free = and Open source and provides a very structured VHDL testbench architecture = for modules and FPGAs of any complexity. The testbench architecture is very= easy to understand, and writing testcases is no problem for an FPGA, HW or= SW designer. We have written a series of 3 brief articles that takes you just a few minu= tes to read and gives you a good understanding of why UVVM is a game change= r with respect to testbench architecture, overview, understanding, maintena= nce, etc. You can download the articles from=20 Bitvis.no: http://bitvis.no/products/uvvm-vvc-framework/ or LinkedIn: https://www.linkedin.com/pulse/advanced-vhdl-verification-made= -simple-anyone-espen-tallaksen?trk=3Dhp-feed-article-title-publish Due to the figures and formatting it cannot be properly posted on comp.lang= .vhdl. From newsfish@newsfish Thu Aug 1 00:36:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe002.ams.xsnews.nl!peer02.fr7!news.highwinds-media.com!post02.fr7!fx46.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Verilog module in VHDL for Altera devices References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> <2ca26f1c-98b3-462c-a87e-e97e48ed3d4c@googlegroups.com> <5719fee7$0$1518$c3e8da3$5496439d@news.astraweb.com> Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <5719fee7$0$1518$c3e8da3$5496439d@news.astraweb.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 160422-0, 22/04/2016), Outbound message X-Antivirus-Status: Clean Lines: 25 Message-ID: NNTP-Posting-Host: 81.107.0.228 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1461333775 81.107.0.228 (Fri, 22 Apr 2016 14:02:55 UTC) NNTP-Posting-Date: Fri, 22 Apr 2016 14:02:55 UTC Organization: virginmedia.com Date: Fri, 22 Apr 2016 15:02:52 +0100 X-Received-Body-CRC: 3155343784 X-Received-Bytes: 2173 Xref: news.eternal-september.org comp.lang.vhdl:4357 On 22/04/2016 11:37, Allan Herriman wrote: > On Thu, 21 Apr 2016 17:13:03 +0100, HT-Lab wrote: > .. > > > How do you switch back to the old library format? I stopped using > makefiles with Modelsim once they put the entire library in a single > file. Version 10.1something I think it was. > > Thanks, > Allan > Hi Allan, You could use "vlib -type directory" which will give you the older (slower) format. I haven't used vmake for a while as I started to use SystemC which for some reason is not supported by vmake, Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:36:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Fri, 22 Apr 2016 16:38:16 -0000 (UTC) Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> <2ca26f1c-98b3-462c-a87e-e97e48ed3d4c@googlegroups.com> <5719fee7$0$1518$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Fri, 22 Apr 2016 16:38:16 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0359355f8ebefe2d2daa8a26e0c5d98b"; logging-data="17826"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/GtZGnWt3OttlCVwyvnn6c" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:yPMmaytrhRobEvfgUOYVsPPcjfo= Xref: news.eternal-september.org comp.lang.vhdl:4358 HT-Lab wrote: > On 22/04/2016 11:37, Allan Herriman wrote: >> On Thu, 21 Apr 2016 17:13:03 +0100, HT-Lab wrote: >> > .. >> >> >> How do you switch back to the old library format? I stopped using >> makefiles with Modelsim once they put the entire library in a single >> file. Version 10.1something I think it was. >> >> Thanks, >> Allan >> > Hi Allan, > > You could use "vlib -type directory" which will give you the older > (slower) format. I haven't used vmake for a while as I started to use > SystemC which for some reason is not supported by vmake, > > Regards, > Hans. > www.ht-lab.com > You can also poke your modelsim.ini to make it the default. [utils] ; Default Library Type (while creating a library with "vlib") ; 0 - legacy library using subdirectories for design units ; 2 - flat library DefaultLibType = 0 -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:36:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Verilog module in VHDL for Altera devices Newsgroups: comp.lang.vhdl References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> <2ca26f1c-98b3-462c-a87e-e97e48ed3d4c@googlegroups.com> <5719fee7$0$1518$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 23 Apr 2016 08:34:49 GMT Lines: 39 Message-ID: <571b33a9$0$1499$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 327f0315.news.astraweb.com X-Trace: DXC=7^68X\3Pb=O\kdljK^UWoEL?0kYOcDh@JAFeRkALIbWCFY`X_Y8OYWBHI6bY5_;LhIEBe]G`V^KXGE2OW^nd7W HT-Lab wrote: > >> On 22/04/2016 11:37, Allan Herriman wrote: >>> On Thu, 21 Apr 2016 17:13:03 +0100, HT-Lab wrote: >>> >> .. >>> >>> >>> How do you switch back to the old library format? I stopped using >>> makefiles with Modelsim once they put the entire library in a single >>> file. Version 10.1something I think it was. >>> >>> Thanks, >>> Allan >>> >> Hi Allan, >> >> You could use "vlib -type directory" which will give you the older >> (slower) format. I haven't used vmake for a while as I started to use >> SystemC which for some reason is not supported by vmake, >> >> Regards, >> Hans. >> www.ht-lab.com >> >> > You can also poke your modelsim.ini to make it the default. > > [utils] > ; Default Library Type (while creating a library with "vlib") > ; 0 - legacy library using subdirectories for design units ; 2 - flat > library DefaultLibType = 0 Thanks Rob and Hans. I look forward to being able to use makefiles again. Allan From newsfish@newsfish Thu Aug 1 00:36:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Verilog module in VHDL for Altera devices Date: Thu, 28 Apr 2016 15:00:15 +0100 Organization: TRW Conekt Lines: 25 Message-ID: References: <5304d66e-e84f-4a65-bb12-5917bc8ace62@googlegroups.com> <3cd255ab-d10d-4f38-bfa7-f381abcf0b9d@googlegroups.com> <5703a4cc$0$1526$c3e8da3$5496439d@news.astraweb.com> <2ca26f1c-98b3-462c-a87e-e97e48ed3d4c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain X-Trace: individual.net 9X6V8CwSm0WkpcLXSXwj5QrJ+DtWCk3hLjqVaRSSRNI9l/UhU= Cancel-Lock: sha1:jtymD4wwm56qwuJhkvmlnW0xLuw= sha1:gzwyIA29B3PaN0DQVwebtiy9vVE= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.0.50 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:4360 HT-Lab writes: > On 21/04/2016 11:52, Martin Thompson wrote: > Transcript window? > > Seriously, I assume you are using Modelsim project files? Nope. > If so then I would > strongly recommend you switch to .do/.tcl files as it will make your life a lot > easier. I do (!) use do files. I have used Makefiles in the past, but compile time is much less of an issue these days. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Thu Aug 1 00:36:39 2024 X-Received: by 10.66.146.34 with SMTP id sz2mr683125pab.40.1462265166036; Tue, 03 May 2016 01:46:06 -0700 (PDT) X-Received: by 10.50.92.1 with SMTP id ci1mr22192igb.1.1462265165997; Tue, 03 May 2016 01:46:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i5no2283600ige.0!news-out.google.com!uv8ni208igb.0!nntp.google.com!i5no2283599ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 May 2016 01:46:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.217.9.127; posting-account=MUwWcgoAAACBTWk812300D64_i4GDl-f NNTP-Posting-Host: 88.217.9.127 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <49360666-e526-4a20-a91a-16e286911e4a@googlegroups.com> Subject: Re: VHDL 2008 simplified conditions From: ralf.hallmen@gmail.com Injection-Date: Tue, 03 May 2016 08:46:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4361 Am Freitag, 25. M=E4rz 2016 19:39:32 UTC+1 schrieb JerryO: > Hi all: >=20 > I was attracted to simplified conditions, but they don't cross to mixed s= td_logic / boolean such as this: >=20 > >> elsif run_tx and (rd_idx < wr_idx) then >=20 >=20 > Where run_tx is std_logic and rd/wr_idx are natural. This will not work?= I was hoping to get away with mixing the convenience of bool / std_logic.= That should probably be an extension. >=20 > I had to put in "run_tx =3D '1'" to resolve to bool / bool. >=20 > Vsim does not complain about the pure std_logic expression simplification= that involves all std_logic, for instance this is fine: >=20 > >> if not rd_msg_lst and RD_MSG_i then >=20 > Where rd_msg_lst and RD_MSG_i are std_logic (obvious edge detection). >=20 >=20 > So, not possible to mix bool / std_logic, right? I hope that's only "as = of yet". >=20 > Thanks in advance for the comments, > Jerry Hi Jerry, the simplification is done by implicitly assuming that you used the new "??= " operator, which does std_ulogic/bit to boolean conversion. This works fin= e for me as long as you have only std_ulogic/bit types in the expression. I= f you mix boolean and std_ulogic/bit things may not be so clear and i don't= know if the operator precedences are good enough to assume the correct pla= ce for the "??"-operator. I'm using modelsim and the following two expressi= ons work, with variables logic as std_ulogic and bool as boolean: if bool and (?? logic) then ... if (?? logic) and bool then ... If i don't use the brackets it fails for me. However if this behaviour is so important to you, you could always overload= the operators, e.g. for "and": function "and" (l : std_ulogic; b : boolean) return boolean is begin return (?? l) and b; end function; function "and" (b: boolean; l : std_ulogic) return boolean is begin return l and b; end function; Cheers, Ralf From newsfish@newsfish Thu Aug 1 00:36:39 2024 X-Received: by 10.182.98.77 with SMTP id eg13mr11016878obb.47.1462483371604; Thu, 05 May 2016 14:22:51 -0700 (PDT) X-Received: by 10.50.249.8 with SMTP id yq8mr112325igc.4.1462483371569; Thu, 05 May 2016 14:22:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!sq19no3018507igc.0!news-out.google.com!uv8ni304igb.0!nntp.google.com!i5no3982473ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 May 2016 14:22:51 -0700 (PDT) In-Reply-To: <49360666-e526-4a20-a91a-16e286911e4a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.239.112.66; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 125.239.112.66 References: <49360666-e526-4a20-a91a-16e286911e4a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1ffc4e05-2993-4142-a9db-6cbb3d61ea5f@googlegroups.com> Subject: Re: VHDL 2008 simplified conditions From: diogratia@gmail.com Injection-Date: Thu, 05 May 2016 21:22:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4362 On Tuesday, May 3, 2016 at 8:46:09 PM UTC+12, ralf.h...@gmail.com wrote: > However if this behaviour is so important to you, you could always overlo= ad the operators, e.g. for "and": >=20 > function "and" (l : std_ulogic; b : boolean) return boolean is > begin > return (?? l) and b; > end function; >=20 > function "and" (b: boolean; l : std_ulogic) return boolean is > begin > return l and b; > end function; This is actually illegal in VHDL (IEEE Std 1076-2008) (error in the second = function aside). 9.2.2 Logic operators para 2: For the binary operators and, or, nand, nor, xor, and xnor, the operands sh= all both be of the same base type, or one operand shall be of a scalar type= and the other operand shall be a one-dimensional array whose element type = is the scalar type. The result type is the same as the base type of the ope= rands if both operands are scalars of the same base type or both operands a= re arrays, or the same as the base type of the array operand if one operand= is a scalar and the other operand is an array. Your scalar types do not have the same base type. 1.3 Structure and terminology of this standard, 1.3.1 General, para 4: In this document, the word shall is used to indicate a mandatory requiremen= t. The word should is used to indicate a recommendation. The word may is us= ed to indicate a permissible action. The word can is used for statements of= possibility and capability. The consequence is that your functions should not be interpreted as overloa= ded operators (no use of infix notation). I don't have access to a wide number of VHDL implementations but have found= two so far that do not catch as errors functions with different base types= when used as overloaded binary operators in expressions. As I recall this = semantic rule was new to -1993. From newsfish@newsfish Thu Aug 1 00:36:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 simplified conditions Date: Thu, 5 May 2016 22:10:15 -0400 Organization: A noiseless patient Spider Lines: 59 Message-ID: References: <49360666-e526-4a20-a91a-16e286911e4a@googlegroups.com> <1ffc4e05-2993-4142-a9db-6cbb3d61ea5f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 6 May 2016 02:06:45 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5a134e71dbb5ed1f5921e8ad23124088"; logging-data="14344"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19susPBwMx1N1FM9jknz9fn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: <1ffc4e05-2993-4142-a9db-6cbb3d61ea5f@googlegroups.com> Cancel-Lock: sha1:JV/wY6xW2zOPV2KVZ8JYYxWXUMQ= Xref: news.eternal-september.org comp.lang.vhdl:4363 On 5/5/2016 5:22 PM, diogratia@gmail.com wrote: > On Tuesday, May 3, 2016 at 8:46:09 PM UTC+12, ralf.h...@gmail.com > wrote: > >> However if this behaviour is so important to you, you could always >> overload the operators, e.g. for "and": >> >> function "and" (l : std_ulogic; b : boolean) return boolean is >> begin return (?? l) and b; end function; >> >> function "and" (b: boolean; l : std_ulogic) return boolean is >> begin return l and b; end function; > > > This is actually illegal in VHDL (IEEE Std 1076-2008) (error in the > second function aside). > > 9.2.2 Logic operators para 2: > > For the binary operators and, or, nand, nor, xor, and xnor, the > operands shall both be of the same base type, or one operand shall be > of a scalar type and the other operand shall be a one-dimensional > array whose element type is the scalar type. The result type is the > same as the base type of the operands if both operands are scalars of > the same base type or both operands are arrays, or the same as the > base type of the array operand if one operand is a scalar and the > other operand is an array. > > Your scalar types do not have the same base type. Does this apply to other than the built-in operators in VHDL? > 1.3 Structure and terminology of this standard, 1.3.1 General, para > 4: > > In this document, the word shall is used to indicate a mandatory > requirement. The word should is used to indicate a recommendation. > The word may is used to indicate a permissible action. The word can > is used for statements of possibility and capability. > > The consequence is that your functions should not be interpreted as > overloaded operators (no use of infix notation). > > I don't have access to a wide number of VHDL implementations but have > found two so far that do not catch as errors functions with different > base types when used as overloaded binary operators in expressions. > As I recall this semantic rule was new to -1993. I think you are misinterpreting the standard. If the standard has a restriction, it would be based on some reason, some problem that would be created if you don't stick to that restriction. What would be the reason this restriction would apply to user defined logic operators? I don't have the standard here to consult, so I can't see the context of 9.2.2. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:40 2024 X-Received: by 10.50.32.101 with SMTP id h5mr4564806igi.3.1462511475464; Thu, 05 May 2016 22:11:15 -0700 (PDT) X-Received: by 10.50.183.6 with SMTP id ei6mr129635igc.7.1462511475395; Thu, 05 May 2016 22:11:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i5no4127951ige.0!news-out.google.com!uv8ni358igb.0!nntp.google.com!i5no4127943ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 May 2016 22:11:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.192.246.162; posting-account=JwtCdAoAAAAcT9OZ0UHxcshdNREqyjqw NNTP-Posting-Host: 203.192.246.162 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <109ab6b9-1e5a-490d-8ff6-8ac59351dafb@googlegroups.com> Subject: Book for Vhdl From: Santhosh B Injection-Date: Fri, 06 May 2016 05:11:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4364 Hi, My name is santhosh, Can you please suggest me a good vhdl book for beginners. Regards, Santhosh. From newsfish@newsfish Thu Aug 1 00:36:40 2024 X-Received: by 10.129.159.18 with SMTP id w18mr12781927ywg.57.1462529042388; Fri, 06 May 2016 03:04:02 -0700 (PDT) X-Received: by 10.50.90.5 with SMTP id bs5mr140444igb.5.1462529042265; Fri, 06 May 2016 03:04:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!88no2077483qga.1!news-out.google.com!uv8ni376igb.0!nntp.google.com!i5no4256123ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 May 2016 03:04:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.217.30.121; posting-account=MUwWcgoAAACBTWk812300D64_i4GDl-f NNTP-Posting-Host: 88.217.30.121 References: <49360666-e526-4a20-a91a-16e286911e4a@googlegroups.com> <1ffc4e05-2993-4142-a9db-6cbb3d61ea5f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <74a763ef-d532-42df-9f2d-7995107c518f@googlegroups.com> Subject: Re: VHDL 2008 simplified conditions From: ralf.hallmen@gmail.com Injection-Date: Fri, 06 May 2016 10:04:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4365 Am Freitag, 6. Mai 2016 04:10:16 UTC+2 schrieb rickman: > On 5/5/2016 5:22 PM, diog...@gmail.com wrote: > > On Tuesday, May 3, 2016 at 8:46:09 PM UTC+12, ralf.h...@gmail.com > > wrote: > > > >> However if this behaviour is so important to you, you could always > >> overload the operators, e.g. for "and": > >> > >> function "and" (l : std_ulogic; b : boolean) return boolean is > >> begin return (?? l) and b; end function; > >> > >> function "and" (b: boolean; l : std_ulogic) return boolean is > >> begin return l and b; end function; > > > > > > This is actually illegal in VHDL (IEEE Std 1076-2008) (error in the > > second function aside). There is no error in the second function, it uses the overloaded first func= tion, which is, as you proved by misreading it, probably not a good case of= code re-use. > > > > 9.2.2 Logic operators para 2: > > > > For the binary operators and, or, nand, nor, xor, and xnor, the > > operands shall both be of the same base type, or one operand shall be > > of a scalar type and the other operand shall be a one-dimensional > > array whose element type is the scalar type. The result type is the > > same as the base type of the operands if both operands are scalars of > > the same base type or both operands are arrays, or the same as the > > base type of the array operand if one operand is a scalar and the > > other operand is an array. > > > > Your scalar types do not have the same base type. >=20 > Does this apply to other than the built-in operators in VHDL? >=20 >=20 > > 1.3 Structure and terminology of this standard, 1.3.1 General, para > > 4: > > > > In this document, the word shall is used to indicate a mandatory > > requirement. The word should is used to indicate a recommendation. > > The word may is used to indicate a permissible action. The word can > > is used for statements of possibility and capability. > > > > The consequence is that your functions should not be interpreted as > > overloaded operators (no use of infix notation). > > > > I don't have access to a wide number of VHDL implementations but have > > found two so far that do not catch as errors functions with different > > base types when used as overloaded binary operators in expressions. > > As I recall this semantic rule was new to -1993. >=20 > I think you are misinterpreting the standard. If the standard has a=20 > restriction, it would be based on some reason, some problem that would=20 > be created if you don't stick to that restriction. What would be the=20 > reason this restriction would apply to user defined logic operators? I= =20 > don't have the standard here to consult, so I can't see the context of=20 > 9.2.2. >=20 I don't have the context either, as i don't have access to the 2008 standar= d, but i agree with Rick here. I would be puzzled to learn that this sectio= n also applies to overloaded operators. The only thing i found close to thi= s section in the 1993 standard states basically the same, but with restrict= ion to types bit and boolean (7.2.1). Back then, from your point of view, t= he extension of ieee.std_logic_1164 to apply logical operators (and, or , .= ..) on std_ulogic must be wrong as well. Ralf From newsfish@newsfish Thu Aug 1 00:36:40 2024 X-Received: by 10.98.78.196 with SMTP id c187mr13078391pfb.4.1462546037132; Fri, 06 May 2016 07:47:17 -0700 (PDT) X-Received: by 10.50.224.179 with SMTP id rd19mr167480igc.10.1462546037054; Fri, 06 May 2016 07:47:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i5no4405483ige.0!news-out.google.com!uv8ni29igb.0!nntp.google.com!sq19no3285940igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 May 2016 07:47:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.139.196.5; posting-account=DAF8KwoAAABg78jJUjHDRWFQCkLCgpM3 NNTP-Posting-Host: 14.139.196.5 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3dd558f2-e4ee-4f65-b126-2c53e7d5d9ba@googlegroups.com> Subject: UART for storing data From: soumik.kanad@gmail.com Injection-Date: Fri, 06 May 2016 14:47:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4366 We were using ATLYS FPGA board and want to implement Uart. Here is the link to the VHDL code - https://drive.google.com/folderview?id=0B_PAq8Rf9NIGQnBUQ0JYcmkyS2c&usp=sharing In this code 8 bits of data is sent serially through the UART port into the FPGA at a time and this data is at the same time emitted out of the FPGA. The data sending part is done by the C code that can be found here - https://drive.google.com/file/d/0B_PAq8Rf9NIGaGliQ3VGWmxoVmM/view?usp=sharing This c code can be used to read the data from a text file, which is serially sent into the FPGA which emits it back and stores it into another text file. What I want to do is to store this data into a variable. Can anyone kindly help? From newsfish@newsfish Thu Aug 1 00:36:41 2024 X-Received: by 10.157.8.83 with SMTP id 77mr13262964oty.40.1462546074524; Fri, 06 May 2016 07:47:54 -0700 (PDT) X-Received: by 10.50.172.73 with SMTP id ba9mr166415igc.6.1462546074453; Fri, 06 May 2016 07:47:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!i5no4405731ige.0!news-out.google.com!uv8ni30igb.0!nntp.google.com!i5no4405723ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 May 2016 07:47:54 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.139.196.5; posting-account=DAF8KwoAAABg78jJUjHDRWFQCkLCgpM3 NNTP-Posting-Host: 14.139.196.5 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: UART for storing data From: soumik.kanad@gmail.com Injection-Date: Fri, 06 May 2016 14:47:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 9 Xref: news.eternal-september.org comp.lang.vhdl:4367 We were using ATLYS FPGA board and want to implement Uart. Here is the link to the VHDL code - https://drive.google.com/folderview?id=0B_PAq8Rf9NIGQnBUQ0JYcmkyS2c&usp=sharing In this code 8 bits of data is sent serially through the UART port into the FPGA at a time and this data is at the same time emitted out of the FPGA. The data sending part is done by the C code that can be found here - https://drive.google.com/file/d/0B_PAq8Rf9NIGaGliQ3VGWmxoVmM/view?usp=sharing This c code can be used to read the data from a text file, which is serially sent into the FPGA which emits it back and stores it into another text file. What I want to do is to store this data into a variable. Can anyone kindly help? From newsfish@newsfish Thu Aug 1 00:36:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: UART for storing data Date: Fri, 6 May 2016 12:45:34 -0400 Organization: A noiseless patient Spider Lines: 42 Message-ID: References: <3dd558f2-e4ee-4f65-b126-2c53e7d5d9ba@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 6 May 2016 16:42:03 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5a134e71dbb5ed1f5921e8ad23124088"; logging-data="10790"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18vDv1a31NlytU4O1l8mch9" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: <3dd558f2-e4ee-4f65-b126-2c53e7d5d9ba@googlegroups.com> Cancel-Lock: sha1:jTb3p7RZiMduRphPW4ho9ihj3aM= Xref: news.eternal-september.org comp.lang.vhdl:4368 On 5/6/2016 10:47 AM, soumik.kanad@gmail.com wrote: > We were using ATLYS FPGA board and want to implement Uart. Here is > the link to the VHDL code - > > https://drive.google.com/folderview?id=0B_PAq8Rf9NIGQnBUQ0JYcmkyS2c&usp=sharing > > In this code 8 bits of data is sent serially through the UART port > into the FPGA at a time and this data is at the same time emitted out > of the FPGA. The data sending part is done by the C code that can be > found here - > > https://drive.google.com/file/d/0B_PAq8Rf9NIGaGliQ3VGWmxoVmM/view?usp=sharing > > This c code can be used to read the data from a text file, which is > serially sent into the FPGA which emits it back and stores it into > another text file. What I want to do is to store this data into a > variable. Can anyone kindly help? I believe you are trying to store the bytes received by the UART into a signal, yes? The first problem is the use of IEEE.STD_LOGIC_UNSIGNED. This is a deprecated library which is *not* an IEEE standard or even a standard at all and is defined differently on different systems. So you can get inconsistent results across different systems. So get rid of it and use numeric_std which *is* an IEEE standard producing identical results on all systems. You will need to declare your arithmetic types as unsigned. Or... if you are working with VHDL 2008, you should have available a package called numeric_std_unsigned which again *is* an IEEE standard and will do what std_logic_unsigned intends to do, but in a standard way. Looking at the code I see an output flag called "rx_enable" which seems to be the data available indicator. It is set by the rx input at the time of the stop bit so will not go high if a framing error is detected. This bit goes high when the UART receiver enters the idle state and is reset on the next clock. So you should be able to use the rx_enable signal to enable a register to capture the data in the rx_data register. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:41 2024 X-Received: by 10.176.1.176 with SMTP id 45mr15483817ual.9.1462605282590; Sat, 07 May 2016 00:14:42 -0700 (PDT) X-Received: by 10.50.92.1 with SMTP id ci1mr11457igb.1.1462605282434; Sat, 07 May 2016 00:14:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!11no2329213qgt.0!news-out.google.com!uv8ni85igb.0!nntp.google.com!sq19no3518520igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 May 2016 00:14:41 -0700 (PDT) In-Reply-To: <74a763ef-d532-42df-9f2d-7995107c518f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.239.112.66; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 125.239.112.66 References: <49360666-e526-4a20-a91a-16e286911e4a@googlegroups.com> <1ffc4e05-2993-4142-a9db-6cbb3d61ea5f@googlegroups.com> <74a763ef-d532-42df-9f2d-7995107c518f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 simplified conditions From: diogratia@gmail.com Injection-Date: Sat, 07 May 2016 07:14:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5474 X-Received-Body-CRC: 827429563 Xref: news.eternal-september.org comp.lang.vhdl:4369 On Friday, May 6, 2016 at 10:04:04 PM UTC+12, Ralf wrote: >=20 > I don't have the context either, as i don't have access to the 2008 stand= ard, but i agree with Rick here. I would be puzzled to learn that this sect= ion also applies to overloaded operators. The only thing i found close to t= his section in the 1993 standard states basically the same, but with restri= ction to types bit and boolean (7.2.1). Back then, from your point of view,= the extension of ieee.std_logic_1164 to apply logical operators (and, or ,= ...) on std_ulogic must be wrong as well. Your conclusions "with restriction to types bit and boolean" and "Back then= , from your point of view, the extension of ieee.std_logic_1164 to apply lo= gical operators (and, or , ...) on std_ulogic must be wrong as well" don't = appear supported by my statements, the standard (-1993 or -2008) nor histor= y. The very first VHDL Issue was on this subject, and the result was as I conv= eyed: VASG-ISAC Analysis & Rationale ------------------------------ This is a problem. The solution is relatively straightforward. The paragraph starting "The following logical operators ..." needs to be rewritten to explicitly state that both operands of a binary logical operat= or must be of the same type. For example: The logical operators _and_, _or_, _nand_, _nor_, _xor_, and _not_ are defined for predefined types BIT and BOOLEAN. They are also defined for an= y one-dimensional array type whose element type is BIT or BOOLEAN. For the binary operators _and_, _or_, _nand_, _nor_, and _xor_ the operands must both be of the same type. Furthermore, in the case of the one-dimensi= onal arrays they must be arrays of the same length, the operation is performed on matching elements of the arrays, and the result is an array with the same index range as the left operand. For the unary operator _not_, the operation is performed on each element of the operand, and the result is an array with the same index range as the operand. -- You could note that the predefined operators found in package standard don'= t require the restriction on both operands having the same base type. They'= re defined that way and not frangible. The ghdl author and I were exchanging email on this overnight, he related t= here was an Issue Report (IR), so I searched through my archive then locate= d a Wayback Machine URL to share (eda.org no longer available).=20 See: http://web.archive.org/web/20110927064548/http://eda.org/isac/IRs-VHDL-87/I= R0001.txt This can also be found in IEEE Std 1076_int-991 (IEEE Standards Interpretat= ions, IEEE Std 1076-1987). Document page 15. I used to correspond with IR-0001's author on the -1993 standard but this p= redates my involvement. A bit more from the -2008 standard: 9.2.2 Logical operators The binary logical operators and, or, nand, nor, xor, and xnor, and the una= ry logical operator not are defined for predefined types BIT and BOOLEAN. T= hey are also defined for any one-dimensional array type whose element type = is BIT or BOOLEAN. For the binary operators and, or, nand, nor, xor, and xnor, the operands sh= all both be of the same base type, or one operand shall be of a scalar type= and the other operand shall be a one-dimensional array whose element type = is the scalar type. The result type is the same as the base type of the ope= rands if both operands are scalars of the same base type or both operands a= re arrays, or the same as the base type of the array operand if one operand= is a scalar and the other operand is an array. -- Notice the paragraph separator as in the original, eliminating any possible= misinterpretation of predefined operators for BIT or BOOLEAN as a restrict= ion on the second paragraph. I may get around to looking through the histor= y of that paragraph separator, it means looking for Language Change Specifi= cations (LCSs) for -2008, and the history isn't completely available. The second function has an error in it, it depends on an illegal operator o= verload. Regards, From newsfish@newsfish Thu Aug 1 00:36:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: newbie question: 2 processes modifying the same std_logic_vector Date: Sat, 7 May 2016 15:51:18 +0200 Organization: A noiseless patient Spider Lines: 39 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 7 May 2016 13:47:48 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="64f4dd5f31606e767a21e68f409189d7"; logging-data="1174"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18RyjVShbhj7uJM3vBNrkfU" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 X-Mozilla-News-Host: snews://news.eternal-september.org:563 Cancel-Lock: sha1:3Xjat6Rt0WusPfkHVxJ2+R1odpc= Xref: news.eternal-september.org comp.lang.vhdl:4370 Hi all, I am sorry for this "newbie" question. I bought a xula2 board last week so am now doing my first steps in VHDL and learning the language and trying to master this (more "parallel" way) of thinking. I have this case: you have an audiosensor that generates blockwaves when audio is received (when the voltage of the audio is above a certain threshold, it generates a "1", if not, it is "0"). The exercise it let the device detection audio in a certain frequency range. In the MCU world, one would implement this using interrrupts: generate an interrupt every rising edge of audiosignal, count the number of edges per time-interval, reset the counter to 0 and work from there on. The problem in a FPGA is that the two threads (counting the edges and timer-interval) work in parallel, so I guess there is a possible conflict between the "increase number of samples by one" and the "reset sample-counter" logic. (in a MCU, you can configure the interrupts as such as this never happens at the same time). So, I am trying to understand how to do this is a FPGA. I am sorry as I guess this is a FPGA 101 question, but can somebody shine some light on this? Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Sat, 7 May 2016 10:59:40 -0400 Organization: A noiseless patient Spider Lines: 69 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 7 May 2016 14:56:16 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5a134e71dbb5ed1f5921e8ad23124088"; logging-data="15261"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+VCKPDZQ+Q12sEJ/kN5SQE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:fnH5XMQFMjUC0kKDPlsxxRueZeM= Xref: news.eternal-september.org comp.lang.vhdl:4371 On 5/7/2016 9:51 AM, kristoff wrote: > Hi all, > > > I am sorry for this "newbie" question. > > I bought a xula2 board last week so am now doing my first steps in VHDL > and learning the language and trying to master this (more "parallel" > way) of thinking. > > > I have this case: > you have an audiosensor that generates blockwaves when audio is received > (when the voltage of the audio is above a certain threshold, it > generates a "1", if not, it is "0"). > > The exercise it let the device detection audio in a certain frequency > range. > > In the MCU world, > one would implement this using interrrupts: generate an interrupt every > rising edge of audiosignal, count the number of edges per time-interval, > reset the counter to 0 and work from there on. > > The problem in a FPGA is that the two threads (counting the edges and > timer-interval) work in parallel, so I guess there is a possible > conflict between the "increase number of samples by one" and the "reset > sample-counter" logic. > (in a MCU, you can configure the interrupts as such as this never > happens at the same time). > > > So, I am trying to understand how to do this is a FPGA. > > > I am sorry as I guess this is a FPGA 101 question, but can somebody > shine some light on this? First, I will say I think you are trying to measure the frequency of a signal by a free running counter measuring the period of the waveform. If that is not correct, the rest of this may not apply. Yes, it can be difficult to think in terms of parallel hardware. But in your case it is easier because your hardware is *not* parallel! I think you are describing a counter that is incremented by the clock and read and reset when the signal pulse edge is received, no? One process will be triggered by the clock. process (clk, reset) is begin if reset = '1' then counter_val <= (others => '0'); elsif rising_edge(clk) then counter_val <= counter_val + 1; end if; end process; This just needs a section added to allow the counter to be reset when the pulse edge is detected. To do that you first have to detect the pulse edge. That can be in this same process or a different one. Then that signal would be used by a conditional to instead of incrementing the count, resetting it to zero. Make sense? How would you do that? -- Rick C From newsfish@newsfish Thu Aug 1 00:36:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Sun, 8 May 2016 12:40:30 +0200 Organization: A noiseless patient Spider Lines: 103 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 8 May 2016 10:36:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="7321dc710e96eba562d43ee4f8aa2851"; logging-data="545"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX187mHukTYcLHjJhN5eB8T2p" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:ECV93Vn6m/0s5TPEjxoIqf5OS2E= Xref: news.eternal-september.org comp.lang.vhdl:4372 Hi Rickman, (inline comments) On 07-05-16 16:59, rickman wrote: >> I have this case: >> you have an audiosensor that generates blockwaves when audio is received >> (when the voltage of the audio is above a certain threshold, it >> generates a "1", if not, it is "0"). >> The exercise it let the device detection audio in a certain frequency >> range. >> In the MCU world, >> one would implement this using interrrupts: generate an interrupt every >> rising edge of audiosignal, count the number of edges per time-interval, >> reset the counter to 0 and work from there on. >> The problem in a FPGA is that the two threads (counting the edges and >> timer-interval) work in parallel, so I guess there is a possible >> conflict between the "increase number of samples by one" and the "reset >> sample-counter" logic. >> (in a MCU, you can configure the interrupts as such as this never >> happens at the same time). > First, I will say I think you are trying to measure the frequency of a > signal by a free running counter measuring the period of the waveform. > If that is not correct, the rest of this may not apply. Well, it's the other way around: count the number of rising-edges during a certain interval; but the principe if of course the same. :-) > Yes, it can be difficult to think in terms of parallel hardware. But in > your case it is easier because your hardware is *not* parallel! I think > you are describing a counter that is incremented by the clock and read > and reset when the signal pulse edge is received, no? Well, the reason I thought like that, is because that is how the design was done on this particular MCU-based project: two "threads", one that counts the number of rising edges and one that that "processes" this per timeslot. (*) And global data as a way for the two processes to communicate with eachother. * I know that counting rising edges of signals can be done in hardware on a MCU. > One process will be triggered by the clock. > > process (clk, reset) is > begin > if reset = '1' then > counter_val <= (others => '0'); > elsif rising_edge(clk) then > counter_val <= counter_val + 1; > end if; > end process; So, in fact, all code that change certain data need to be grouped in one process? Is this the conclussion? > Make sense? How would you do that? Yes. Makes sence. Just wondering. On the SPI interface of the STM32F1, there is a "TXNE" bit (part of the "SR" register) which is set by the SPI hardware when data has been received by the SPI interface. And ... by just reading the received data from the SPI DR register, this actually automatically resets that bit. I wonder how you would describe this in VHDL. Setting that bit is clearly done by one process (the process that drives the SPI interface), ... but reading that data (and the result of clearing that bit) is probaby done by code outside the SPI block. Don't you have the same senario as I had: two processes trying to change one piece of data (in this case, the TXNE bit). Or am I seeing things to complicated here? Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Sun, 8 May 2016 10:56:57 -0400 Organization: A noiseless patient Spider Lines: 181 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 8 May 2016 14:53:26 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5a134e71dbb5ed1f5921e8ad23124088"; logging-data="30674"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+66bO4CDFZ2yLyww/SHKhs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:0M7RfipPs8IS7soNClGxma3Xhpk= Xref: news.eternal-september.org comp.lang.vhdl:4373 On 5/8/2016 6:40 AM, kristoff wrote: > Hi Rickman, > > > (inline comments) > > > On 07-05-16 16:59, rickman wrote: >>> I have this case: >>> you have an audiosensor that generates blockwaves when audio is received >>> (when the voltage of the audio is above a certain threshold, it >>> generates a "1", if not, it is "0"). >>> The exercise it let the device detection audio in a certain frequency >>> range. >>> In the MCU world, >>> one would implement this using interrrupts: generate an interrupt every >>> rising edge of audiosignal, count the number of edges per time-interval, >>> reset the counter to 0 and work from there on. >>> The problem in a FPGA is that the two threads (counting the edges and >>> timer-interval) work in parallel, so I guess there is a possible >>> conflict between the "increase number of samples by one" and the "reset >>> sample-counter" logic. >>> (in a MCU, you can configure the interrupts as such as this never >>> happens at the same time). > > >> First, I will say I think you are trying to measure the frequency of a >> signal by a free running counter measuring the period of the waveform. >> If that is not correct, the rest of this may not apply. > > Well, it's the other way around: count the number of rising-edges during > a certain interval; but the principe if of course the same. > :-) I see. You are describing two counters. One running from the clock to measure the time period and another, running from the input signal to count the number of transitions of the input signal. BTW, just to point this out, it can be hard to get a digital signal that corresponds to the frequency of an audio signal if that is what you are doing. The audio signal can produce extraneous edges from the harmonic and noise content. >> Yes, it can be difficult to think in terms of parallel hardware. But in >> your case it is easier because your hardware is *not* parallel! I think >> you are describing a counter that is incremented by the clock and read >> and reset when the signal pulse edge is received, no? > > Well, the reason I thought like that, is because that is how the design > was done on this particular MCU-based project: two "threads", one that > counts the number of rising edges and one that that "processes" this per > timeslot. (*) > > And global data as a way for the two processes to communicate with > eachother. I don't see the need for global "data" exactly. IN VHDL there are signals and variables. Variables exist only within a process because they have meaning only in sequential code like a C variable and there is no sequential code outside a process (or subprograms - procedure/function). While true global variables exist in VHDL, signals are what you would call global variables and are what you want to use here. They are the heavy lifters in VHDL for the work of a signal you would see on a wire in a hardware design. Because a variable does not exist outside the process it is used in, a signal must be used to turn that value into something that has "physical presence" if you will. > * I know that counting rising edges of signals can be done in hardware > on a MCU. > > > >> One process will be triggered by the clock. >> >> process (clk, reset) is >> begin >> if reset = '1' then >> counter_val <= (others => '0'); >> elsif rising_edge(clk) then >> counter_val <= counter_val + 1; >> end if; >> end process; > > So, in fact, all code that change certain data need to be grouped in one > process? > Is this the conclussion? YES! If you assign a value to a signal from two processes it causes an error because that corresponds to two logic outputs driving a voltage onto the same wire. <> One subtle error in VHDL comes from assigning part of a vector in a process. There is a clause in the VHDL "contract" (read the fine print in *all* contracts) that says if you assign part of a vector in a process, you create drivers for all of it. Assign the rest of the vector in another process and you now have two assignments to one signal which equals <> I'm a bit fuzzy on the details of this. I've never run into this error other than the mentions here. Perhaps someone else can flesh it out for you? >> Make sense? How would you do that? > > Yes. Makes sence. > > > Just wondering. > > On the SPI interface of the STM32F1, there is a "TXNE" bit (part of the > "SR" register) which is set by the SPI hardware when data has been > received by the SPI interface. > > And ... by just reading the received data from the SPI DR register, this > actually automatically resets that bit. TX usually means "transmit". Are you sure that is the right bit? Would it be RX... maybe ready or not empty rather than TX..? > I wonder how you would describe this in VHDL. That is easy, I've done it many times. The flag is set by the data being loaded into the receive data register. The address and control bits are decoded as an enable. This enable is used to clear the flag. What is critical is to deal with the condition of a new data being received just as the old data is being read. So the address decode needs to be registered as a one clock wide pulse to coincide with the actual transfer of the data and not before. But that is only important if you want to be able to receive new data while waiting for the old one to be read and handle the flags without reporting overruns erroneously to the exact clock cycle. > Setting that bit is clearly done by one process (the process that drives > the SPI interface), ... but reading that data (and the result of > clearing that bit) is probaby done by code outside the SPI block. SPI is a multi clock "thing". The last time I designed one I coded the shift register as one process using the external clock and the rest of the logic on a separate clock. But each register was updated in *one process*. It's ok for the address decode and state machine to be in a different block. Just don't update any signals in both places. > Don't you have the same senario as I had: two processes trying to change > one piece of data (in this case, the TXNE bit). No. Bring the address decode into the SPI as a "read" signal. This can then be used to update the TXNE bit. Or the "data available" flag can be brought into the bus interface module to update the flag there. Just don't update the flag in both places. > Or am I seeing things to complicated here? You are thinking like software is all. Hardware is a little different. I think in terms of the hardware and code to "describe" what I am thinking of. That's why it's HDL, Hardware Description Language. Others have shown me you can "think" in terms of the code as long as you follow the rules. I've done this so long my rules are quite simpler than the VHDL rules because there are plenty of things I just don't consider doing. The result is I don't have to "think" about the problems it causes as I'll never see those. But sometimes I forget the details of why I do it that way. A signal crossing a clock boundary is a bit ugly, but is important to be done correctly. You can find a number of web pages on how to do this correctly and a number of "correct" ways. This is a mistake that can cause you a *lot* of debugging grief, so is best to just be done correctly. If you want more info on that and can't find it with a search, I can help. The important term is "metastability". I don't think there is a software equivalent, but it is a bit like some of the concerns with semaphores and interrupts. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp3-1.free.fr!not-for-mail Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Newsgroups: comp.lang.vhdl References: From: Nicolas Matringe Date: Sun, 8 May 2016 19:21:12 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:45.0) Gecko/20100101 Thunderbird/45.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 68 Message-ID: <572f7589$0$4539$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 08 May 2016 19:21:14 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1462728074 news-2.free.fr 4539 88.185.146.198:17592 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:4374 On 08.05.2016 12:40, kristoff wrote: [...] > Well, the reason I thought like that, is because that is how the design > was done on this particular MCU-based project: two "threads", one that > counts the number of rising edges and one that that "processes" this per > timeslot. (*) > > And global data as a way for the two processes to communicate with > eachother. The problem you have here is not "thinking hardware". You have to keep in mind that VHDL is a language that describes actual logic gates, not a programming language. A process describes a single piece of logic, with its inputs, outputs and internal signals. Having several processes modify a single signal is *exactly* connecting the outputs of different pieces together. As a basic rule of electronics, you just Don't Do That (it has exceptions, of course) > So, in fact, all code that change certain data need to be grouped in one > process? > Is this the conclussion? Exactly. > Just wondering. > On the SPI interface of the STM32F1, there is a "TXNE" bit (part of the > "SR" register) which is set by the SPI hardware when data has been > received by the SPI interface. > And ... by just reading the received data from the SPI DR register, this > actually automatically resets that bit. > I wonder how you would describe this in VHDL. Well the CPU bus must have a "read" signal somewhere so when the correct address is presented and the read signal is active, the bit is cleared. > Setting that bit is clearly done by one process (the process that drives > the SPI interface), ... but reading that data (and the result of > clearing that bit) is probaby done by code outside the SPI block. > > Don't you have the same senario as I had: two processes trying to change > one piece of data (in this case, the TXNE bit). > > Or am I seeing things to complicated here? I think you're confused by the term "process" Your TXNE bit can be written as a set/reset flip flop in a single process: process (clk, rst) begin if rst = '1' then txne <= '0'; elsif rising_edge(clk) then if set = '1' then txne <= '1'; elsif reset = '1' then txne <= '0'; end if; end if; end process; I didn't think much about what should happen if both set and reset are active at the same time. Here, set has precedence. Nicolas From newsfish@newsfish Thu Aug 1 00:36:43 2024 X-Received: by 10.107.26.194 with SMTP id a185mr21994748ioa.2.1462766393923; Sun, 08 May 2016 20:59:53 -0700 (PDT) X-Received: by 10.50.183.6 with SMTP id ei6mr95430igc.7.1462766393840; Sun, 08 May 2016 20:59:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i5no5892526ige.0!news-out.google.com!k10ni271igv.0!nntp.google.com!i5no5892519ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 May 2016 20:59:53 -0700 (PDT) In-Reply-To: <109ab6b9-1e5a-490d-8ff6-8ac59351dafb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.192.246.162; posting-account=JwtCdAoAAAAcT9OZ0UHxcshdNREqyjqw NNTP-Posting-Host: 203.192.246.162 References: <109ab6b9-1e5a-490d-8ff6-8ac59351dafb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <951ea014-9598-41ef-9e1b-f663a2323755@googlegroups.com> Subject: Re: Book for Vhdl From: Santhosh B Injection-Date: Mon, 09 May 2016 03:59:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:4375 On Friday, May 6, 2016 at 10:41:17 AM UTC+5:30, Santhosh B wrote: > Hi, > > My name is santhosh, > > Can you please suggest me a good vhdl book for beginners. > > Regards, > Santhosh. what happened. . .No one is giving reply From newsfish@newsfish Thu Aug 1 00:36:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Book for Vhdl Date: Mon, 9 May 2016 00:14:36 -0400 Organization: A noiseless patient Spider Lines: 31 Message-ID: References: <109ab6b9-1e5a-490d-8ff6-8ac59351dafb@googlegroups.com> <951ea014-9598-41ef-9e1b-f663a2323755@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 9 May 2016 04:11:05 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5a134e71dbb5ed1f5921e8ad23124088"; logging-data="21631"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/KRb3KULqPbYi8tBlsBx7A" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: <951ea014-9598-41ef-9e1b-f663a2323755@googlegroups.com> Cancel-Lock: sha1:tz9Nw4V+t7cE2Zs+V83hH/jP038= Xref: news.eternal-september.org comp.lang.vhdl:4376 On 5/8/2016 11:59 PM, Santhosh B wrote: > On Friday, May 6, 2016 at 10:41:17 AM UTC+5:30, Santhosh B wrote: >> Hi, >> >> My name is santhosh, >> >> Can you please suggest me a good vhdl book for beginners. >> >> Regards, >> Santhosh. > > what happened. . .No one is giving reply I have never found the "perfect" book. I have five and none of them cover everything you need. Some are good for a beginner. Some are good as references. One has both Verilog and VHDL which lets you compare the two. None solve all my problems when I need help. Also, I haven't opened any of them in over a year, maybe two or three. I normally use any of the *many*, many online references including the Doulos web site which has a great deal of useful info. Whatever book you end up with, be sure it includes details of VHDL-2008. 2008 is such an improvement over the previous versions that it would be foolish (in my opinion) to code without using it. Perhaps you can tell us where you are in learning VHDL and what you hope to learn from the book? -- Rick C From newsfish@newsfish Thu Aug 1 00:36:44 2024 X-Received: by 10.140.174.194 with SMTP id u185mr22574587qhu.15.1462792902646; Mon, 09 May 2016 04:21:42 -0700 (PDT) X-Received: by 10.50.6.70 with SMTP id y6mr115333igy.8.1462792902463; Mon, 09 May 2016 04:21:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!88no3002946qga.1!news-out.google.com!l67ni332ith.0!nntp.google.com!i5no6088414ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 May 2016 04:21:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.217.28.43; posting-account=MUwWcgoAAACBTWk812300D64_i4GDl-f NNTP-Posting-Host: 88.217.28.43 References: <49360666-e526-4a20-a91a-16e286911e4a@googlegroups.com> <1ffc4e05-2993-4142-a9db-6cbb3d61ea5f@googlegroups.com> <74a763ef-d532-42df-9f2d-7995107c518f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a44528a-4a2b-43ed-a522-f28f42bbf7b5@googlegroups.com> Subject: Re: VHDL 2008 simplified conditions From: Ralf Injection-Date: Mon, 09 May 2016 11:21:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4377 Am Samstag, 7. Mai 2016 09:14:44 UTC+2 schrieb diog...@gmail.com: > On Friday, May 6, 2016 at 10:04:04 PM UTC+12, Ralf wrote: > >=20 > > I don't have the context either, as i don't have access to the 2008 sta= ndard, but i agree with Rick here. I would be puzzled to learn that this se= ction also applies to overloaded operators. The only thing i found close to= this section in the 1993 standard states basically the same, but with rest= riction to types bit and boolean (7.2.1). Back then, from your point of vie= w, the extension of ieee.std_logic_1164 to apply logical operators (and, or= , ...) on std_ulogic must be wrong as well. >=20 > Your conclusions "with restriction to types bit and boolean" and "Back th= en, from your point of view, the extension of ieee.std_logic_1164 to apply = logical operators (and, or , ...) on std_ulogic must be wrong as well" don'= t appear supported by my statements, the standard (-1993 or -2008) nor hist= ory. >=20 > The very first VHDL Issue was on this subject, and the result was as I co= nveyed: >=20 > VASG-ISAC Analysis & Rationale > ------------------------------ > This is a problem. The solution is relatively straightforward. >=20 > The paragraph starting "The following logical operators ..." needs to be > rewritten to explicitly state that both operands of a binary logical oper= ator > must be of the same type. >=20 > For example: >=20 > The logical operators _and_, _or_, _nand_, _nor_, _xor_, and _not_ are > defined for predefined types BIT and BOOLEAN. They are also defined for = any > one-dimensional array type whose element type is BIT or BOOLEAN. For > the binary operators _and_, _or_, _nand_, _nor_, and _xor_ the operands > must both be of the same type. Furthermore, in the case of the one-dimen= sional > arrays they must be arrays of the same length, the operation is performed > on matching elements of the arrays, and the result is an array with the > same index range as the left operand. For the unary operator _not_, the > operation is performed on each element of the operand, and the result is > an array with the same index range as the operand. > -- >=20 > You could note that the predefined operators found in package standard do= n't require the restriction on both operands having the same base type. The= y're defined that way and not frangible. >=20 > The ghdl author and I were exchanging email on this overnight, he related= there was an Issue Report (IR), so I searched through my archive then loca= ted a Wayback Machine URL to share (eda.org no longer available).=20 >=20 > See: >=20 > http://web.archive.org/web/20110927064548/http://eda.org/isac/IRs-VHDL-87= /IR0001.txt Thank you, that link is very interesting. >=20 > This can also be found in IEEE Std 1076_int-991 (IEEE Standards Interpret= ations, IEEE Std 1076-1987). Document page 15. I don't have access to this document. >=20 > I used to correspond with IR-0001's author on the -1993 standard but this= predates my involvement. >=20 > A bit more from the -2008 standard: >=20 > 9.2.2 Logical operators >=20 > The binary logical operators and, or, nand, nor, xor, and xnor, and the u= nary logical operator not are defined for predefined types BIT and BOOLEAN.= They are also defined for any one-dimensional array type whose element typ= e is BIT or BOOLEAN. >=20 > For the binary operators and, or, nand, nor, xor, and xnor, the operands = shall both be of the same base type, or one operand shall be of a scalar ty= pe and the other operand shall be a one-dimensional array whose element typ= e is the scalar type. The result type is the same as the base type of the o= perands if both operands are scalars of the same base type or both operands= are arrays, or the same as the base type of the array operand if one opera= nd is a scalar and the other operand is an array. > -- >=20 > Notice the paragraph separator as in the original, eliminating any possib= le misinterpretation of predefined operators for BIT or BOOLEAN as a restri= ction on the second paragraph. I may get around to looking through the hist= ory of that paragraph separator, it means looking for Language Change Speci= fications (LCSs) for -2008, and the history isn't completely available. This is interesting, since this separation is not present in my version of = the 1993 standard. >=20 > The second function has an error in it, it depends on an illegal operator= overload. No, in that case the error is in the first function. However, i don't want = to argue about this. It doesn't solve anything. >=20 > Regards, The question still remains: Can I divert from the standard when overloading= operators? In case of 1993 it can be expanded on: Can i use other types than BIT and B= OOLEAN? I think we have a different view of the standard, that might be because you= know much more about the details. Still, i don't see where the standard st= ates that i can't overload operators like i did in those two functions. The paragraph separator is only a weak indicator for me. It should be menti= onend in the section, which states how to overload operators. E.g. a paragr= aph that states how an implementation has to treat overloaded operators, if= they don't adhere to the standard. Another example of operator overloading that i use is the extension of 1993= VHDL with the operator: "and" (std_logic_vector; std_logic) return std_logic_vector; This was introduced in some later standard and, if i understand you correct= ly, is forbidden in the 1993 version. I argue that this overloaded function is perfectly fine, but if i'm wrong i= 'm glad that the tools i use are not so stiff on their implementation of th= e standard. Regards, Ralf From newsfish@newsfish Thu Aug 1 00:36:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 09 May 2016 12:02:47 GMT Lines: 40 Message-ID: <57307c67$0$1610$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 143f574a.news.astraweb.com X-Trace: DXC=mOOOA_aKZ\ofj0fd2JZgghL?0kYOcDh@je9Xhm8m]ViiiG8i?S9JJ On 5/8/2016 6:40 AM, kristoff wrote: [snip] > YES! If you assign a value to a signal from two processes it causes an > error because that corresponds to two logic outputs driving a voltage > onto the same wire. > > <> One subtle error in VHDL comes from assigning part of a > vector in a process. There is a clause in the VHDL "contract" (read the > fine print in *all* contracts) that says if you assign part of a vector > in a process, you create drivers for all of it. Assign the rest of the > vector in another process and you now have two assignments to one signal > which equals <> > > I'm a bit fuzzy on the details of this. I've never run into this error > other than the mentions here. Perhaps someone else can flesh it out for > you? I contend that it's not an error in the language. I would say it is hard to understand, counterintuitive for beginners, PITA, etc., but not a mistake for an HDL. The search term to make you less fuzzy on the details is "longest static prefix". Basically if the compiler knows the bounds at compile time, it will do what you want and only create drivers for the part of the vector that you want to change. If it doesn't know the bounds at compile time (e.g. if the bounds depend on the value of a signal) then it will create drivers for all elements of the vector (which is probably not what you want). N.B. the drivers are part of the process. It doesn't matter if the assignment statement in that process is never executed. Regards, Allan From newsfish@newsfish Thu Aug 1 00:36:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Mon, 9 May 2016 09:53:47 -0400 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <57307c67$0$1610$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 9 May 2016 13:50:16 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5a134e71dbb5ed1f5921e8ad23124088"; logging-data="31583"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+y/Ql+w7oggTTaypj0IJ4R" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: <57307c67$0$1610$c3e8da3$5496439d@news.astraweb.com> Cancel-Lock: sha1:4phhV6mNeSB45cJIJ2UWDcm1ef0= Xref: news.eternal-september.org comp.lang.vhdl:4379 On 5/9/2016 8:02 AM, Allan Herriman wrote: > On Sun, 08 May 2016 10:56:57 -0400, rickman wrote: > >> On 5/8/2016 6:40 AM, kristoff wrote: > [snip] >> YES! If you assign a value to a signal from two processes it causes an >> error because that corresponds to two logic outputs driving a voltage >> onto the same wire. >> >> <> One subtle error in VHDL comes from assigning part of a >> vector in a process. There is a clause in the VHDL "contract" (read > the >> fine print in *all* contracts) that says if you assign part of a vector >> in a process, you create drivers for all of it. Assign the rest of the >> vector in another process and you now have two assignments to one > signal >> which equals <> >> >> I'm a bit fuzzy on the details of this. I've never run into this error >> other than the mentions here. Perhaps someone else can flesh it out > for >> you? > > I contend that it's not an error in the language. I would say it is hard > to understand, counterintuitive for beginners, PITA, etc., but not a > mistake for an HDL. > > The search term to make you less fuzzy on the details is "longest static > prefix". > Basically if the compiler knows the bounds at compile time, it will do > what you want and only create drivers for the part of the vector that you > want to change. > If it doesn't know the bounds at compile time (e.g. if the bounds depend > on the value of a signal) then it will create drivers for all elements of > the vector (which is probably not what you want). > > N.B. the drivers are part of the process. It doesn't matter if the > assignment statement in that process is never executed. N.B.??? Don't know what that means. I wasn't trying to say it is an error of the tools or the language. It is an error to assign a signal in two processes which is what happens if the user is not aware that the full vector will be assigned. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Newsgroups: comp.lang.vhdl References: <57307c67$0$1610$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 09 May 2016 15:52:16 GMT Lines: 76 Message-ID: <5730b230$0$1525$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 97e84212.news.astraweb.com X-Trace: DXC=Y=Fn?gelN7=J0Z]=gbPP29L?0kYOcDh@:KF7Mk<5A6i50WDN7dFMi;8HI6bY5_;Lh9EBe]G`V^KX7KVUd]ZPXA^029BXB83bQj> Xref: news.eternal-september.org comp.lang.vhdl:4380 On Mon, 09 May 2016 09:53:47 -0400, rickman wrote: > On 5/9/2016 8:02 AM, Allan Herriman wrote: >> On Sun, 08 May 2016 10:56:57 -0400, rickman wrote: >> >>> On 5/8/2016 6:40 AM, kristoff wrote: >> [snip] >>> YES! If you assign a value to a signal from two processes it causes >>> an error because that corresponds to two logic outputs driving a >>> voltage onto the same wire. >>> >>> <> One subtle error in VHDL comes from assigning part of a >>> vector in a process. There is a clause in the VHDL "contract" (read >> the >>> fine print in *all* contracts) that says if you assign part of a >>> vector in a process, you create drivers for all of it. Assign the >>> rest of the vector in another process and you now have two assignments >>> to one >> signal >>> which equals <> >>> >>> I'm a bit fuzzy on the details of this. I've never run into this >>> error other than the mentions here. Perhaps someone else can flesh it >>> out >> for >>> you? >> >> I contend that it's not an error in the language. I would say it is >> hard to understand, counterintuitive for beginners, PITA, etc., but not >> a mistake for an HDL. >> >> The search term to make you less fuzzy on the details is "longest >> static prefix". >> Basically if the compiler knows the bounds at compile time, it will do >> what you want and only create drivers for the part of the vector that >> you want to change. >> If it doesn't know the bounds at compile time (e.g. if the bounds >> depend on the value of a signal) then it will create drivers for all >> elements of the vector (which is probably not what you want). >> >> N.B. the drivers are part of the process. It doesn't matter if the >> assignment statement in that process is never executed. > > N.B.??? Don't know what that means. N.B. is the common abbreviation of the Latin "nota bene" - note well. I assumed most English speakers would know it. > I wasn't trying to say it is an error of the tools or the language. I misunderstood. > It > is an error to assign a signal in two processes which is what happens if > the user is not aware that the full vector will be assigned. The longest static prefix has drivers. This may or may not be the full vector. Typically you would code it such that only the part you want to have drivers, has drivers. It's only an error if: - you have multiple drivers on (a given slice of) an unresolved signal. - you have multiple drivers on (a given slice of) a resolved signal that doesn't match the synthesis template for a tri-state connection (in synthesis only). To the OP, Rick's advice is the one to follow for a "newbie" - only make assignments to a signal from one process (or concurrent assignment, which counts as process in this context). This will avoid many pitfalls. It takes a while to get your head around concepts such as drivers and the longest static prefix. You'll need to know them eventually if you persist with the language though. Allan From newsfish@newsfish Thu Aug 1 00:36:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Mon, 9 May 2016 12:14:00 -0400 Organization: A noiseless patient Spider Lines: 81 Message-ID: References: <57307c67$0$1610$c3e8da3$5496439d@news.astraweb.com> <5730b230$0$1525$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 9 May 2016 16:10:28 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5a134e71dbb5ed1f5921e8ad23124088"; logging-data="30974"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+suQsxbP9Lp1bTplZA3mvz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: <5730b230$0$1525$c3e8da3$5496439d@news.astraweb.com> Cancel-Lock: sha1:zkmDqXI5T3nq84rMJ6nSLowUVbw= Xref: news.eternal-september.org comp.lang.vhdl:4381 On 5/9/2016 11:52 AM, Allan Herriman wrote: > On Mon, 09 May 2016 09:53:47 -0400, rickman wrote: > >> On 5/9/2016 8:02 AM, Allan Herriman wrote: >>> On Sun, 08 May 2016 10:56:57 -0400, rickman wrote: >>> >>>> On 5/8/2016 6:40 AM, kristoff wrote: >>> [snip] >>>> YES! If you assign a value to a signal from two processes it causes >>>> an error because that corresponds to two logic outputs driving a >>>> voltage onto the same wire. >>>> >>>> <> One subtle error in VHDL comes from assigning part of a >>>> vector in a process. There is a clause in the VHDL "contract" (read >>> the >>>> fine print in *all* contracts) that says if you assign part of a >>>> vector in a process, you create drivers for all of it. Assign the >>>> rest of the vector in another process and you now have two assignments >>>> to one >>> signal >>>> which equals <> >>>> >>>> I'm a bit fuzzy on the details of this. I've never run into this >>>> error other than the mentions here. Perhaps someone else can flesh it >>>> out >>> for >>>> you? >>> >>> I contend that it's not an error in the language. I would say it is >>> hard to understand, counterintuitive for beginners, PITA, etc., but not >>> a mistake for an HDL. >>> >>> The search term to make you less fuzzy on the details is "longest >>> static prefix". >>> Basically if the compiler knows the bounds at compile time, it will do >>> what you want and only create drivers for the part of the vector that >>> you want to change. >>> If it doesn't know the bounds at compile time (e.g. if the bounds >>> depend on the value of a signal) then it will create drivers for all >>> elements of the vector (which is probably not what you want). >>> >>> N.B. the drivers are part of the process. It doesn't matter if the >>> assignment statement in that process is never executed. >> >> N.B.??? Don't know what that means. > > N.B. is the common abbreviation of the Latin "nota bene" - note well. I > assumed most English speakers would know it. > >> I wasn't trying to say it is an error of the tools or the language. > > I misunderstood. > >> It >> is an error to assign a signal in two processes which is what happens if >> the user is not aware that the full vector will be assigned. > > The longest static prefix has drivers. This may or may not be the full > vector. Typically you would code it such that only the part you want to > have drivers, has drivers. This is one of the things I don't like about VHDL, the complexity. Just looking up the term "longest static prefix" gives hard to understand results. It is not a thing that is actually dealt with while coding a typical program, so I just don't do things that trigger the problem and I can ignore it. In other words, I work from mental templates rather than trying to always remember all the details of the language. There's just so much storage up there and I need to focus on the more useful information. That is what Kristoff should do. Learn the "right" way of thinking of HDL programming rather than learning all the nuance of the language. I don't think this necessarily means to think in terms of the hardware produced (although that is what I do). However, it is important to think in terms of concurrent (parallel) processes rather than sequential code. Every concurrent statement is a process that runs in parallel with all the others. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Mon, 9 May 2016 22:29:54 +0200 Organization: A noiseless patient Spider Lines: 194 Message-ID: References: <572f7589$0$4539$426a74cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 9 May 2016 20:26:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3a5f6500c984fcf9758b8dfe65939416"; logging-data="27374"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+OLk21R1jPgNtX2CNWFLmM" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: <572f7589$0$4539$426a74cc@news.free.fr> X-Mozilla-News-Host: news://news.eternal-september.org Cancel-Lock: sha1:aUfdVrmpfOfa2XjBDvjGyHoIRrM= Xref: news.eternal-september.org comp.lang.vhdl:4382 Nicolas, (and Rickman) On 08-05-16 19:21, Nicolas Matringe wrote: >> Well, the reason I thought like that, is because that is how the design >> was done on this particular MCU-based project: two "threads", one that >> counts the number of rising edges and one that that "processes" this per >> timeslot. (*) >> And global data as a way for the two processes to communicate with >> eachother. > The problem you have here is not "thinking hardware". You have to keep > in mind that VHDL is a language that describes actual logic gates, not a > programming language. Well, the reason I am interested in FPGAs is to -from what I read about it- it seams to requite a completely different way of thinking then I am used when writing code. And that is now my main problem. If you look on the net, there is quite some information on FPGAs, on VHDL and building your first "blinky", etc. So actually getting started is not that difficult. The next step, learning to get your brain into the correct "twist" and learn to think hardware, will probably require doing a large number of exercises. But this is a lot more difficult to find. I was actually a bit surprised to see there are no courses on FPGA, VHDL or verilog on any of the major MOOC flatforms (edx, coursera, ...) as I hoped thse would have been the places to find the exercises I need. > A process describes a single piece of logic, with its inputs, outputs > and internal signals. Having several processes modify a single signal is > *exactly* connecting the outputs of different pieces together. As a > basic rule of electronics, you just Don't Do That (it has exceptions, of > course) I know, and that I also told myself beforehand ... but you know, my experience gave me a different feeling. The first exercise I did for myself was PWM, based on the logic of how an arduino does PWM: a counter that goes up in loops, a PWM output pin that goes to "1" on counter=0 and "0" on couter=pwm-value. So the logic I had was this: --- cut here --- cut here --- cut here --- cut here --- (...) signal led_t : std_logic := '0'; signal pwm_r : std_logic_vector(18 downto 0) := "1000000000000000000"; (...) process(clk_in,cnt_r,pwm_r) is begin if falling_edge(clk_in) then if cnt_r = pwm_r then led_t <= '0'; elsif cnt_r = 0 then led_t <= '1'; end if; end if; end process; led <= led_t; --- cut here --- cut here --- cut here --- cut here --- In fact, this seams to work, which was ... great. Actually, my first thought was, ... well, this is not that much unlike coding afterall. Apparently, the language is intelligent enough to see that "led_t" is changed under certain conditions, but there are also moments when it is not changed; ... so by itself it seams to create a "memory-cell" for that output pin. Nice! :-) However, I think this particular example kind-of gave me the wrong impression. :-( >> Just wondering. >> On the SPI interface of the STM32F1, there is a "TXNE" bit (part of the >> "SR" register) which is set by the SPI hardware when data has been >> received by the SPI interface. >> And ... by just reading the received data from the SPI DR register, this >> actually automatically resets that bit. >> I wonder how you would describe this in VHDL. > > Well the CPU bus must have a "read" signal somewhere so when the correct > address is presented and the read signal is active, the bit is cleared. Well, I have been thinking about this. My "problem" is to image how a "read" action (which is for the actual piece of hardware containing the data quite a "passive" thing) can trigger a action (in this case, erase the RXNE bit). But I guess "reading data from a register" this is not really the just "reading data". It's probably a "write" action: copy the data from the register to the internal bus of the processor and -once that is done- clear it. (althou, isn't this a "sequencial" action ???) >> Setting that bit is clearly done by one process (the process that drives >> the SPI interface), ... but reading that data (and the result of >> clearing that bit) is probaby done by code outside the SPI block. >> >> Don't you have the same senario as I had: two processes trying to change >> one piece of data (in this case, the TXNE bit). >> >> Or am I seeing things to complicated here? > > I think you're confused by the term "process" > Your TXNE bit can be written as a set/reset flip flop in a single process: > > process (clk, rst) > begin > if rst = '1' then > txne <= '0'; > elsif rising_edge(clk) then > if set = '1' then > txne <= '1'; > elsif reset = '1' then > txne <= '0'; > end if; > end if; > end process; > I didn't think much about what should happen if both set and reset are > active at the same time. Here, set has precedence. OK, my mind-problem is this: Perhaps it is my "IT" mind, but I tend to look at information as "data". In this case, there is a piece of information (the "clock counter") and two actions ("increase the value by one" and "reset the value to zero"). Around this piece of information, there is a box to execute these actions, which can be implemented in software or in hardware. The main difference, as I see it, is that software and hardware work with two different mechanisms: - software is based on a "single-shot" event. Something or someone sends a command to the black box managing the information (i.e. the command "reset the counter to 0"), that command is executed and that is it. - in contrast, hardware is based on a "state" (e.g. the nRST-line is set low -> the value of the register is set to zero). This state remains valid as long as the nRST is low. (so to make the counter "active" again, the nRST line must to reset to 1). (this is also how you implemented this in your VHDL example, no?) So, if I am not wrong, I want to reset the counter to zero, I first need to set the nRST line to 0, and then set it back to 1 again; ... which is works ... except that this is a is a "sequencial" action. And I just though that the whole idea of VHDL was that everything runs in parallel, not in serie. Or not? > Nicolas Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Mon, 9 May 2016 22:54:50 +0200 Organization: A noiseless patient Spider Lines: 194 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 9 May 2016 20:51:19 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3a5f6500c984fcf9758b8dfe65939416"; logging-data="1197"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/0w7b8lGINxJm2Bog5gQQJ" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:mRERFohmlX5gkKN/RUc9l+r0LFw= Xref: news.eternal-september.org comp.lang.vhdl:4383 Hi Rickman, (and everybody else that replied). On 08-05-16 16:56, rickman wrote: >> Well, it's the other way around: count the number of rising-edges during >> a certain interval; but the principe if of course the same. >> :-) > I see. You are describing two counters. One running from the clock to > measure the time period and another, running from the input signal to > count the number of transitions of the input signal. Correct. > BTW, just to point this out, it can be hard to get a digital signal that > corresponds to the frequency of an audio signal if that is what you are > doing. The audio signal can produce extraneous edges from the harmonic > and noise content. Yes, but this is not a practicle example. I give a arduino / microcontroller / programming course one a month in our local ham-radio club here in Ostend (Belgium) and this was one of the exercises we did on microcontrollers (actually an exercise on using interrupts). Last week, I gave a small demo on FPGAs in that course and we tried to use that exercise as an example to try to find out what it would look like on a FPGA instead of on e FPGA. >>> Yes, it can be difficult to think in terms of parallel hardware. But in >>> your case it is easier because your hardware is *not* parallel! I think >>> you are describing a counter that is incremented by the clock and read >>> and reset when the signal pulse edge is received, no? >> >> Well, the reason I thought like that, is because that is how the design >> was done on this particular MCU-based project: two "threads", one that >> counts the number of rising edges and one that that "processes" this per >> timeslot. (*) >> >> And global data as a way for the two processes to communicate with >> eachother. > > I don't see the need for global "data" exactly. IN VHDL there are > signals and variables. Variables exist only within a process because > they have meaning only in sequential code like a C variable and there is > no sequential code outside a process (or subprograms - > procedure/function). While true global variables exist in VHDL, signals > are what you would call global variables and are what you want to use > here. They are the heavy lifters in VHDL for the work of a signal you > would see on a wire in a hardware design. Because a variable does not > exist outside the process it is used in, a signal must be used to turn > that value into something that has "physical presence" if you will. Well, looking at this from a "conceptual" point of view, I am a bit puzzled here. From how I understand from FPGAs up to now, the main idea is that a lot more is done in parallel then on a MCU based setup (which mainly uses a sequencial approach). Now i used to do some multithreaded programming on unix before and interrupt-drive code on MCUs, and my experience is that the more you make things runs in parallel, the more need there is for interprocess-communication. Or not ? > YES! If you assign a value to a signal from two processes it causes an > error because that corresponds to two logic outputs driving a voltage > onto the same wire. So, if there is really a need for multiple processes driving a pin, you need to "and" or "or" them. > <> One subtle error in VHDL comes from assigning part of a > vector in a process. There is a clause in the VHDL "contract" (read the > fine print in *all* contracts) that says if you assign part of a vector > in a process, you create drivers for all of it. Assign the rest of the > vector in another process and you now have two assignments to one signal > which equals <> > I'm a bit fuzzy on the details of this. I've never run into this error > other than the mentions here. Perhaps someone else can flesh it out for > you? OK. Noted. >> On the SPI interface of the STM32F1, there is a "TXNE" bit (part of the >> "SR" register) which is set by the SPI hardware when data has been >> received by the SPI interface. >> And ... by just reading the received data from the SPI DR register, this >> actually automatically resets that bit. > TX usually means "transmit". Are you sure that is the right bit? Would > it be RX... maybe ready or not empty rather than TX..? Yes, sorry. Typo. :-( >> I wonder how you would describe this in VHDL. > That is easy, I've done it many times. The flag is set by the data > being loaded into the receive data register. The address and control > bits are decoded as an enable. This enable is used to clear the flag. OK. I think I kind-of understand this. (...) >> Setting that bit is clearly done by one process (the process that drives >> the SPI interface), ... but reading that data (and the result of >> clearing that bit) is probaby done by code outside the SPI block. > > SPI is a multi clock "thing". The last time I designed one I coded the > shift register as one process using the external clock and the rest of > the logic on a separate clock. But each register was updated in *one > process*. It's ok for the address decode and state machine to be in a > different block. Just don't update any signals in both places. Interesting idea. So even inside one "thing", there can be multiple closks. >> Or am I seeing things to complicated here? > You are thinking like software is all. This could be very correct. (and -as mentioned in my other message- it's actually the main reason I bought this FPGA kit, to learn to think differently :-) ) > ... Hardware is a little different. > I think in terms of the hardware and code to "describe" what I am > thinking of. That's why it's HDL, Hardware Description Language. Others > have shown me you can "think" in terms of the code as long as you follow > the rules. I've done this so long my rules are quite simpler than the > VHDL rules because there are plenty of things I just don't consider > doing. The result is I don't have to "think" about the problems it > causes as I'll never see those. But sometimes I forget the details of > why I do it that way. I understand. As mentioned in my other message, I probably could do with a lot more exercises to get the hang of this. My problem -I think- at this time is how to translate "sequencial" processes into a "parallel" way of thinking. > A signal crossing a clock boundary is a bit ugly, but is important to be > done correctly. You can find a number of web pages on how to do this > correctly and a number of "correct" ways. This is a mistake that can > cause you a *lot* of debugging grief, so is best to just be done > correctly. If you want more info on that and can't find it with a > search, I can help. The important term is "metastability". I don't > think there is a software equivalent, but it is a bit like some of the > concerns with semaphores and interrupts. OK. Thanks! :-) Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Mon, 9 May 2016 21:59:53 -0400 Organization: A noiseless patient Spider Lines: 282 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 10 May 2016 01:56:22 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="21062"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1979kOTuYja+hmxijRngNGh" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:7WsCp3RgN6fXHJNLlzvYgv0m9PQ= Xref: news.eternal-september.org comp.lang.vhdl:4384 On 5/9/2016 4:54 PM, kristoff wrote: > Hi Rickman, > (and everybody else that replied). > > > > On 08-05-16 16:56, rickman wrote: >>> Well, it's the other way around: count the number of rising-edges during >>> a certain interval; but the principe if of course the same. >>> :-) > >> I see. You are describing two counters. One running from the clock to >> measure the time period and another, running from the input signal to >> count the number of transitions of the input signal. > > Correct. > > > >> BTW, just to point this out, it can be hard to get a digital signal that >> corresponds to the frequency of an audio signal if that is what you are >> doing. The audio signal can produce extraneous edges from the harmonic >> and noise content. > > Yes, but this is not a practicle example. > > I give a arduino / microcontroller / programming course one a month in > our local ham-radio club here in Ostend (Belgium) and this was one of > the exercises we did on microcontrollers (actually an exercise on using > interrupts). > > Last week, I gave a small demo on FPGAs in that course and we tried to > use that exercise as an example to try to find out what it would look > like on a FPGA instead of on e FPGA. > > > >>>> Yes, it can be difficult to think in terms of parallel hardware. >>>> But in >>>> your case it is easier because your hardware is *not* parallel! I >>>> think >>>> you are describing a counter that is incremented by the clock and read >>>> and reset when the signal pulse edge is received, no? >>> >>> Well, the reason I thought like that, is because that is how the design >>> was done on this particular MCU-based project: two "threads", one that >>> counts the number of rising edges and one that that "processes" this per >>> timeslot. (*) >>> >>> And global data as a way for the two processes to communicate with >>> eachother. >> >> I don't see the need for global "data" exactly. IN VHDL there are >> signals and variables. Variables exist only within a process because >> they have meaning only in sequential code like a C variable and there is >> no sequential code outside a process (or subprograms - >> procedure/function). While true global variables exist in VHDL, signals >> are what you would call global variables and are what you want to use >> here. They are the heavy lifters in VHDL for the work of a signal you >> would see on a wire in a hardware design. Because a variable does not >> exist outside the process it is used in, a signal must be used to turn >> that value into something that has "physical presence" if you will. > > > Well, looking at this from a "conceptual" point of view, I am a bit > puzzled here. > > > From how I understand from FPGAs up to now, the main idea is that a lot > more is done in parallel then on a MCU based setup (which mainly uses a > sequencial approach). > > > Now i used to do some multithreaded programming on unix before and > interrupt-drive code on MCUs, and my experience is that the more you > make things runs in parallel, the more need there is for > interprocess-communication. > > > Or not ? Absolutely! Inter-process communication in an HDL is done by a wire, also known as a signal. It can't get much simpler than that. A signal can be a single bit, a vector or even an integer. Parallel processes on a CPU are complicated because they aren't really in parallel and the CPU has to be shared between them. In hardware, processes are truly parallel because they have their own hardware to run on. Here is an example. ralph: process (A, B) is begin C <= A and B; end process; malph: process (C, D) is begin E <= C or D; end process; C is used to communicate between the process ralph and process malph. Here is an interesting point. These two processes are scheduled by the sensitivity list, the names in parentheses. Process ralph will run any time there is a change on signal A or signal B. Process malph runs any time there is a change on signals C or D. When they reach the end of the process they are suspended. A process can also have explicit wait statements, but they aren't typically used in synthesized code. >> YES! If you assign a value to a signal from two processes it causes an >> error because that corresponds to two logic outputs driving a voltage >> onto the same wire. > > So, if there is really a need for multiple processes driving a pin, you > need to "and" or "or" them. If you gate them together, the two process outputs (drivers) aren't actually driving the same signal, so yes. >> <> One subtle error in VHDL comes from assigning part of a >> vector in a process. There is a clause in the VHDL "contract" (read the >> fine print in *all* contracts) that says if you assign part of a vector >> in a process, you create drivers for all of it. Assign the rest of the >> vector in another process and you now have two assignments to one signal >> which equals <> > >> I'm a bit fuzzy on the details of this. I've never run into this error >> other than the mentions here. Perhaps someone else can flesh it out for >> you? > > > OK. Noted. > > > > >>> On the SPI interface of the STM32F1, there is a "TXNE" bit (part of the >>> "SR" register) which is set by the SPI hardware when data has been >>> received by the SPI interface. >>> And ... by just reading the received data from the SPI DR register, this >>> actually automatically resets that bit. > >> TX usually means "transmit". Are you sure that is the right bit? Would >> it be RX... maybe ready or not empty rather than TX..? > > Yes, sorry. Typo. :-( > > > >>> I wonder how you would describe this in VHDL. > >> That is easy, I've done it many times. The flag is set by the data >> being loaded into the receive data register. The address and control >> bits are decoded as an enable. This enable is used to clear the flag. > > OK. I think I kind-of understand this. > > (...) > > >>> Setting that bit is clearly done by one process (the process that drives >>> the SPI interface), ... but reading that data (and the result of >>> clearing that bit) is probaby done by code outside the SPI block. >> >> SPI is a multi clock "thing". The last time I designed one I coded the >> shift register as one process using the external clock and the rest of >> the logic on a separate clock. But each register was updated in *one >> process*. It's ok for the address decode and state machine to be in a >> different block. Just don't update any signals in both places. > > Interesting idea. So even inside one "thing", there can be multiple closks. SPI has a clock for the interface. You can use that clock to run the shift registers input and output (or use the same register for both). SPI doesn't guarantee any clock pulses on SCLK outside of the ones to shift the data, so the controller normally has another clock which runs separately. If it is fairly much faster than the SPI clock, you can sample all the interface signals on the internal clock and run everything on one clock. This can reduce the setup or hold time on the I/O pins though so make sure you have plenty of it. Also, when sampling the input signals which are from a different clock domain, you need to run them through two FFs to deal with metastability. Metastability is a whole topic in itself. >>> Or am I seeing things to complicated here? > >> You are thinking like software is all. > > > This could be very correct. > > (and -as mentioned in my other message- it's actually the main reason I > bought this FPGA kit, to learn to think differently :-) ) > > > > > ... Hardware is a little different. >> I think in terms of the hardware and code to "describe" what I am >> thinking of. That's why it's HDL, Hardware Description Language. Others >> have shown me you can "think" in terms of the code as long as you follow >> the rules. I've done this so long my rules are quite simpler than the >> VHDL rules because there are plenty of things I just don't consider >> doing. The result is I don't have to "think" about the problems it >> causes as I'll never see those. But sometimes I forget the details of >> why I do it that way. > > I understand. > > As mentioned in my other message, I probably could do with a lot more > exercises to get the hang of this. > > > My problem -I think- at this time is how to translate "sequencial" > processes into a "parallel" way of thinking. That's easy for me, I visualize the logic. RTL is register transfer language. It describes a level of coding where the registers are described by sequential processes (ones triggered by a clock) and combinatorial processes. These can be combined as well, with both the register and the logic described together. This is a simple register process. smpl_reg: process (clk,reset) is begin if reset = '1' then counter <= (others => '0'); elsif rising_edge(clk) then counter <= next_counter; end if; end process smpl_reg; Here is the logic as a concurrent statement which can also be written as a process. next_counter <= counter + 1; This is a register with the logic together. smpl_reg: process (clk,reset) is begin if reset = '1' then counter <= (others => '0'); elsif rising_edge(clk) then counter <= counter + 1; end if; end process smpl_reg; All of this is RTL. Behavioral descriptions are a bit less to the point of "this is a register" and are a bit more abstract, but fundamentally the same flow. Sequential is often used for combinatorial logic. comb_logic: process (addr, r_w, stb) is begin reg_a <= '0'; reg_b <= '0'; ... case addr is when "0000" reg_a <= '1'; when "0001" reg_b <= '1'; when "0010" ... end case; end process; This would be a lot more messy and a lot less clear if done in concurrent statements. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Mon, 9 May 2016 22:26:46 -0400 Organization: A noiseless patient Spider Lines: 229 Message-ID: References: <572f7589$0$4539$426a74cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 10 May 2016 02:23:18 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="26187"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/iRV+TRZJKNpRTabdsrq3Y" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:u6UWFu2QS+CazAJ7TssgiSdV/ZU= Xref: news.eternal-september.org comp.lang.vhdl:4385 On 5/9/2016 4:29 PM, kristoff wrote: > Nicolas, (and Rickman) > > On 08-05-16 19:21, Nicolas Matringe wrote: > >>> Well, the reason I thought like that, is because that is how the design >>> was done on this particular MCU-based project: two "threads", one that >>> counts the number of rising edges and one that that "processes" this per >>> timeslot. (*) > >>> And global data as a way for the two processes to communicate with >>> eachother. > >> The problem you have here is not "thinking hardware". You have to keep >> in mind that VHDL is a language that describes actual logic gates, not a >> programming language. > > > Well, the reason I am interested in FPGAs is to -from what I read about > it- it seams to requite a completely different way of thinking then I am > used when writing code. > > And that is now my main problem. > If you look on the net, there is quite some information on FPGAs, on > VHDL and building your first "blinky", etc. So actually getting started > is not that difficult. > > The next step, learning to get your brain into the correct "twist" and > learn to think hardware, will probably require doing a large number of > exercises. But this is a lot more difficult to find. > > I was actually a bit surprised to see there are no courses on FPGA, VHDL > or verilog on any of the major MOOC flatforms (edx, coursera, ...) as I > hoped thse would have been the places to find the exercises I need. Chicken and egg I think. FPGAs are not as widely used as are MCUs and CPUs, so they aren't taught as much, so they aren't as widely used. They have a reputation for being much harder to program and for being much harder to put on a board. But that depends on which one you choose. There are FPGAs like MCUs, available in small packages for small tasks. There are FPGAs like an Intel i7 which have a thousand pins and need a heat sink. I don't use those in my designs. > > A process describes a single piece of logic, with its inputs, outputs > > and internal signals. Having several processes modify a single signal is > > *exactly* connecting the outputs of different pieces together. As a > > basic rule of electronics, you just Don't Do That (it has exceptions, of > > course) > > I know, and that I also told myself beforehand ... but you know, my > experience gave me a different feeling. > > > The first exercise I did for myself was PWM, based on the logic of how > an arduino does PWM: a counter that goes up in loops, a PWM output pin > that goes to "1" on counter=0 and "0" on couter=pwm-value. > > > So the logic I had was this: > --- cut here --- cut here --- cut here --- cut here --- > > (...) > signal led_t : std_logic := '0'; > signal pwm_r : std_logic_vector(18 downto 0) := "1000000000000000000"; > (...) > > process(clk_in,cnt_r,pwm_r) is > begin > if falling_edge(clk_in) then > if cnt_r = pwm_r then > led_t <= '0'; > elsif cnt_r = 0 then > led_t <= '1'; > end if; > end if; > end process; > led <= led_t; > --- cut here --- cut here --- cut here --- cut here --- > > > In fact, this seams to work, which was ... great. Did you get any warnings at compile? The sensitivity list of a process is not a list of inputs. It is the signals that need to trigger the process to run. If the process were combinatorial, it would be everything on the right of an assignment statement, but since this is sequential, it is just the clock and the reset, which you didn't use, so just the clock needs to be here. > Actually, my first thought was, ... well, this is not that much unlike > coding afterall. > > Apparently, the language is intelligent enough to see that "led_t" is > changed under certain conditions, but there are also moments when it is > not changed; ... so by itself it seams to create a "memory-cell" for > that output pin. Nice! :-) Yes, if you wrote code like this in a combinatorial process it would produce a latch rather than a register. Usually these are inadvertent, leaving the ELSE off an IF statement, for example. > However, I think this particular example kind-of gave me the wrong > impression. :-( Not sure why. I think you have the right view of it. >>> Just wondering. >>> On the SPI interface of the STM32F1, there is a "TXNE" bit (part of the >>> "SR" register) which is set by the SPI hardware when data has been >>> received by the SPI interface. >>> And ... by just reading the received data from the SPI DR register, this >>> actually automatically resets that bit. >>> I wonder how you would describe this in VHDL. >> >> Well the CPU bus must have a "read" signal somewhere so when the correct >> address is presented and the read signal is active, the bit is cleared. > > Well, I have been thinking about this. > > > My "problem" is to image how a "read" action (which is for the actual > piece of hardware containing the data quite a "passive" thing) can > trigger a action (in this case, erase the RXNE bit). Reads are *not* passive. Read is done via a bus just like a write. The only difference is one or two of the control lines are in a different state. To store data of a write, a register is enabled by logic driven by the address and control lines. Do the same thing to clear a bit on a read. The hardware works the same way. > But I guess "reading data from a register" this is not really the just > "reading data". It's probably a "write" action: copy the data from the > register to the internal bus of the processor and -once that is done- > clear it. > (althou, isn't this a "sequencial" action ???) Clear what? The data or the RXNE bit? It can be done in parallel, but sequential is a coding method that can be used. Registers can be described in concurrent statements, but conventionally that is not used. >>> Setting that bit is clearly done by one process (the process that drives >>> the SPI interface), ... but reading that data (and the result of >>> clearing that bit) is probaby done by code outside the SPI block. >>> >>> Don't you have the same senario as I had: two processes trying to change >>> one piece of data (in this case, the TXNE bit). >>> >>> Or am I seeing things to complicated here? >> >> I think you're confused by the term "process" >> Your TXNE bit can be written as a set/reset flip flop in a single >> process: >> >> process (clk, rst) >> begin >> if rst = '1' then >> txne <= '0'; >> elsif rising_edge(clk) then >> if set = '1' then >> txne <= '1'; >> elsif reset = '1' then >> txne <= '0'; >> end if; >> end if; >> end process; >> I didn't think much about what should happen if both set and reset are >> active at the same time. Here, set has precedence. > > > OK, my mind-problem is this: > > Perhaps it is my "IT" mind, but I tend to look at information as "data". > > In this case, there is a piece of information (the "clock counter") and > two actions ("increase the value by one" and "reset the value to zero"). > > Around this piece of information, there is a box to execute these > actions, which can be implemented in software or in hardware. > > > > The main difference, as I see it, is that software and hardware work > with two different mechanisms: > > - software is based on a "single-shot" event. Something or someone sends > a command to the black box managing the information (i.e. the command > "reset the counter to 0"), that command is executed and that is it. > > > - in contrast, hardware is based on a "state" (e.g. the nRST-line is set > low -> the value of the register is set to zero). This state remains > valid as long as the nRST is low. (so to make the counter "active" > again, the nRST line must to reset to 1). > (this is also how you implemented this in your VHDL example, no?) > > > > So, if I am not wrong, I want to reset the counter to zero, I first need > to set the nRST line to 0, and then set it back to 1 again; ... which is > works ... except that this is a is a "sequencial" action. > And I just though that the whole idea of VHDL was that everything runs > in parallel, not in serie. No, everything in parallel is not "the whole idea". That is how it can work. But sequential code can be turned into hardware just as well as concurrent code. Everything inside a process is sequential code. Everything at the top level of an architecture (outside a process and including the process itself) is concurrent code and in parallel. When you think of a bit being set to '1' and then back to '0', that can all be specified by one command. nRST <= '0' when cnt_r = pwm_r else '1'. I think you are making this a bit harder than it needs to be. I remember I had trouble thinking of this when I started. You need to *not* compare it to software all the time just because it is different and software is what you know. Focusing on the differences is confusing. Instead just focus on how HDL works. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Date: Tue, 10 May 2016 08:32:55 +0200 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 10 May 2016 06:29:35 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="b593b5c3efc76d5cafb9b5cfe7e2ac05"; logging-data="28140"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX189T+1MHgxamh8AJPT+WdM8" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:w5os6fueTQlHsWk9ZjYkVH9YirQ= Xref: news.eternal-september.org comp.lang.vhdl:4386 Hi rickman, On 10-05-16 03:59, rickman wrote: (...) Not that much time now (I'm on the train to work now). Thanks for all the information. All very interesting. I think, at this point, it boils down to one thing: make more exercises and try it out. Do you (or anymore else) happen to know a good website, online course or book with actual exercises to learn this? Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:47 2024 X-Received: by 10.157.10.15 with SMTP id 15mr26677331otg.9.1462878449617; Tue, 10 May 2016 04:07:29 -0700 (PDT) X-Received: by 10.50.29.113 with SMTP id j17mr220560igh.6.1462878449584; Tue, 10 May 2016 04:07:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!sq19no4811468igc.0!news-out.google.com!uv8ni108igb.0!nntp.google.com!i5no6755020ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 10 May 2016 04:07:29 -0700 (PDT) In-Reply-To: <5a44528a-4a2b-43ed-a522-f28f42bbf7b5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.239.112.66; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 125.239.112.66 References: <49360666-e526-4a20-a91a-16e286911e4a@googlegroups.com> <1ffc4e05-2993-4142-a9db-6cbb3d61ea5f@googlegroups.com> <74a763ef-d532-42df-9f2d-7995107c518f@googlegroups.com> <5a44528a-4a2b-43ed-a522-f28f42bbf7b5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 simplified conditions From: diogratia@gmail.com Injection-Date: Tue, 10 May 2016 11:07:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4387 On Monday, May 9, 2016 at 11:21:44 PM UTC+12, Ralf wrote: > The question still remains: Can I divert from the standard when overloadi= ng operators? Now there's the sixty four dollar question. Before I let you off the hook: > In case of 1993 it can be expanded on: Can i use other types than BIT and= BOOLEAN? The semantic restriction only requires both operands be the same type. How = is that restrictive to predefined types? >=20 > I think we have a different view of the standard, that might be because y= ou know much more about the details. Still, i don't see where the standard = states that i can't overload operators like i did in those two functions. I think we have different views of what a standard is. Illegal is a term de= fined in the standard.=20 The IEEE will tell you a standard is an agreement by interested parties (fo= r Design Automation primarily vendors) on how something is defined or funct= ions to insure interoperability and reliability. And what that tells us is that the purpose to which VHDL is used has change= d (I'll explain this further down). > The paragraph separator is only a weak indicator for me. It should be men= tionend in the section, which states how to overload operators. E.g. a para= graph that states how an implementation has to treat overloaded operators, = if they don't adhere to the standard. Here's the shocker. If you look in the -2008 standard 16.3 package standard= you'll find predefined operators for BOOLEAN (and BOOLEAN_VECTOR) as well = as BIT (and BIT_VECTOR) violating the semantic rule in 9.2.2 paragraph 2. You'll also find 9.2.2 doesn't describe these mixed argument binary logic o= perators - at all. There's also no public document trail (and I have a good= portion of all the LCSs). These and the changes you mentioned one of in the -2008 version of package = std_logic_1164 have no visible documentation trail and are contrary to to 9= .2.2. Add to that that the VHDL standard revision passed a vote, was required to = answer all questions (objections) and is inconsistent. >=20 > Another example of operator overloading that i use is the extension of 19= 93 VHDL with the operator: > "and" (std_logic_vector; std_logic) return std_logic_vector; >=20 > This was introduced in some later standard and, if i understand you corre= ctly, is forbidden in the 1993 version. The -2008 revision of the standard, package std_logic_1164 among others wer= e made part of the VHDL standard. >=20 > I argue that this overloaded function is perfectly fine, but if i'm wrong= i'm glad that the tools i use are not so stiff on their implementation of = the standard. It's not consistent with 9.2.2. I'll state categorically that there has ne= ver been a VHDL implementation started and solely consistent with the -2008= standard and that no VHDL implementation is fully compliant with that vers= ion. Now for the difference in purpose for VHDL which was originally sponsored b= y the DoD as a formal notation for use in formal design descriptions for fo= rmal proofs.=20 That's not the case today. A syntactically and semantically valid functiona= lly verified and implementation proven is not accepted as a formal proof of= correctness. (And no other HDL has been either). The same methodology used= to make the C programming language acceptable to the NSA for code controll= ing type I crypto implementations is used for all HDLs. A language subset = is defined that is considered formally provable. VHDL has most of that (his= torically) built in to the language definition. Things like pure versus imp= ure for functions. You'll find that extends to synthesis with things like restrictions on cons= tructs (no while loops, which depend on abstracts). And what's happened in the intervening years (-2000, -2002, -2008 revisions= ) is sort of like the Europe English joke (http://www.ahajokes.com/eng011.h= tml). There's been a slow and steady transformation of VHDL into an HDL lik= e the others, currently there are attempts to add features found in SystemV= erilog (and having been tried before and failed in the marketplace, see the= failed P1551 (Standard for VHDL Electronic Digital System and Interface De= sign) effort based on VHDL+). And what we have today is an inconsistency in the standard where this seman= tic rule is contradicted by poorly documented changes. So the question is if the standard is meant primarily for language implemen= ters and is inconsistent does it serve it's purpose? Imagine someone were to implement a VHDL tool solely from the standard and = actually used the semantic rule in 9.2.2. They'd have (theoretically) a sta= ndard compliant tool that isn't interoperable with another VHDL tool (I hav= en't seen any proof anyone actually conforms to the rule (With it's shall, = like must in -1993). And for this particular point all implementation vary from the standard. Which is good, there's no more Sense of the VASG, or Interpretations - the = DASC has no method to make variances from the standard, that's what revisio= ns are for. The bad news is no one has really noticed, and there have been = no new VHDL tool starts no derived from earlier standard revision compliant= tools. There is good news. Some of the more useful features found in the -2008 rev= ision are actually being adopted, albeit not so much supported by synthesis= vendors. VHDL may still be one of the most concisely defined 'languages' e= ver and has roots earlier than it's 1983 DoD start. And if you have strong feelings on the standard they could always use a han= d with the P1076 VASG effort, it's open to individual contributors. Cheers. From newsfish@newsfish Thu Aug 1 00:36:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp6-1.free.fr!not-for-mail Subject: Re: newbie question: 2 processes modifying the same std_logic_vector Newsgroups: comp.lang.vhdl References: From: Nicolas Matringe Date: Tue, 10 May 2016 13:50:18 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 13 Message-ID: <5731cafb$0$3329$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 10 May 2016 13:50:19 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1462881019 news-2.free.fr 3329 88.185.146.198:12626 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:4388 On 10.05.2016 08:32, kristoff wrote: > I think, at this point, it boils down to one thing: make more exercises > and try it out. I think you need some digital electronics basic course (combinatorial logic, flip-flops, counters) and then see how they are described in VHDL, to make you feel how it works. The fact that processes are called "sequential" is a bit confusing for SW people. A process doesn't run, it just describes a piece of electronics. Nicolas From newsfish@newsfish Thu Aug 1 00:36:48 2024 X-Received: by 10.66.157.229 with SMTP id wp5mr26309594pab.35.1462888862457; Tue, 10 May 2016 07:01:02 -0700 (PDT) X-Received: by 10.36.64.148 with SMTP id n142mr20641ita.4.1462888862265; Tue, 10 May 2016 07:01:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i5no6856965ige.0!news-out.google.com!l67ni396ith.0!nntp.google.com!i5no6856953ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 10 May 2016 07:01:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.246.134.125; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 213.246.134.125 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <811e9ca7-e07b-40da-97cb-a9ba131a0570@googlegroups.com> Subject: Re: newbie question: 2 processes modifying the same std_logic_vector From: "colin_toogood@yahoo.com" Injection-Date: Tue, 10 May 2016 14:01:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4389 Whenever I start to explain VHDL to a new guy I start with explaining how t= he language is used as a simulator (its original purpose). That only takes = ten minutes and then it is only another five to explain how the code is the= n synthesized. It would take much longer here but if you find an article on= it it would speed up your understanding. Colin From newsfish@newsfish Thu Aug 1 00:36:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Hex String to Unsigned Date: Wed, 18 May 2016 11:32:44 -0400 Organization: A noiseless patient Spider Lines: 15 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 18 May 2016 15:29:04 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="25814"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19UmiAU4ncv6JasSqeO86F0" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:2k5tGDiFiVAZH9x/hFgHpRdTuQA= Xref: news.eternal-september.org comp.lang.vhdl:4390 I seem to be bonking my head against the wall on this one. I have not found any standard libraries that convert a string of hex digits to an unsigned variable. I thought it would be easy to write my own, but I'm having a bit of trouble. So first, am I reinventing the wheel here? If not, the last issue I'm having is converting an integer with value of 0 or 1 to a std_logic or unsigned bit. Any suggestions? I've been beating on this one for an hour and keep finding different problems with my approach. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Hex String to Unsigned Date: Wed, 18 May 2016 16:51:20 -0000 (UTC) Organization: Sonic.net, Inc. Lines: 27 Message-ID: References: Injection-Date: Wed, 18 May 2016 16:51:20 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="12636"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19NlMDBlRaoKeR343tD9CUn" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:MWoDj05Q4cSDs+zCj33mOvO4vSQ= Xref: news.eternal-september.org comp.lang.vhdl:4391 In article , rickman wrote: >I seem to be bonking my head against the wall on this one. I have not >found any standard libraries that convert a string of hex digits to an >unsigned variable. I thought it would be easy to write my own, but I'm >having a bit of trouble. > >So first, am I reinventing the wheel here? If not, the last issue I'm >having is converting an integer with value of 0 or 1 to a std_logic or >unsigned bit. Any suggestions? > >I've been beating on this one for an hour and keep finding different >problems with my approach. Rick, I'm no VHDL power user, but the C function you're looking for is "strtoul". Googling that, along with "vhdl" turns up lots of examples. As I said, I don't know enough VHDL to eval the first few i clicked, but they look reasonable. Regards, Mark From newsfish@newsfish Thu Aug 1 00:36:49 2024 X-Received: by 10.140.231.198 with SMTP id b189mr31001289qhc.10.1463607763409; Wed, 18 May 2016 14:42:43 -0700 (PDT) X-Received: by 10.50.231.139 with SMTP id tg11mr12366igc.9.1463607763364; Wed, 18 May 2016 14:42:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!88no4939468qga.1!news-out.google.com!f14ni133ita.0!nntp.google.com!i5no9662183ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 May 2016 14:42:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.212.188.85; posting-account=siWI1goAAADCu904SmsHiBYIWw1g2Ocr NNTP-Posting-Host: 117.212.188.85 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <725b0505-78a6-4754-914e-57eb3680d8e4@googlegroups.com> Subject: Re: Hex String to Unsigned From: iamalien Injection-Date: Wed, 18 May 2016 21:42:43 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4392 On Wednesday, May 18, 2016 at 9:02:42 PM UTC+5:30, rickman wrote: > I seem to be bonking my head against the wall on this one. I have not > found any standard libraries that convert a string of hex digits to an > unsigned variable. I thought it would be easy to write my own, but I'm > having a bit of trouble. > > So first, am I reinventing the wheel here? If not, the last issue I'm > having is converting an integer with value of 0 or 1 to a std_logic or > unsigned bit. Any suggestions? > > I've been beating on this one for an hour and keep finding different > problems with my approach. > > -- > > Rick C I think someone might have done this earlier, anyway for converting the integer to binary in vhdl you can use this: std_logic_vector(to_unsigned(your_integer,required_number_of_bits)) ex, std_logic_vector(to_unsigned(a,8)) (a is signal with integer value less than 256 ofcourse) And i guess for single bit you could std_logic(to_unsigned(a,1)) (havent used this one, but used the earlier one many times) From newsfish@newsfish Thu Aug 1 00:36:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Hex String to Unsigned Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 18 May 2016 22:47:04 GMT Lines: 30 Message-ID: <573cf0e7$0$1609$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 30400fe7.news.astraweb.com X-Trace: DXC=HiJ?h5fDT22lHmK[=4U:; Xref: news.eternal-september.org comp.lang.vhdl:4393 On Wed, 18 May 2016 11:32:44 -0400, rickman wrote: > I seem to be bonking my head against the wall on this one. I have not > found any standard libraries that convert a string of hex digits to an > unsigned variable. I thought it would be easy to write my own, but I'm > having a bit of trouble. > > So first, am I reinventing the wheel here? If not, the last issue I'm > having is converting an integer with value of 0 or 1 to a std_logic or > unsigned bit. Any suggestions? > > I've been beating on this one for an hour and keep finding different > problems with my approach. Not standard libraries, but non-standard ones, will do it. e.g. (Synopsys's) ieee.std_logic_textio has a function called 'hread' which sounds like it can be made to do what you want. (It reads a line rather than a string (line is a pointer to a string), and it only works with std_(u)logic_vector, so you'll need to cast.) There's a good chance that this is already supported in your simulator. http://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_textio.vhd >From STD.textio: type LINE is access STRING; Regards, Allan From newsfish@newsfish Thu Aug 1 00:36:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Hex String to Unsigned Date: Thu, 19 May 2016 02:02:41 -0400 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: <725b0505-78a6-4754-914e-57eb3680d8e4@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 19 May 2016 05:59:00 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="142eb314d770a2fabfd69b6a1c3cd67f"; logging-data="3772"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19A7U+KEJkxOCqGp3XEwOtU" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 In-Reply-To: <725b0505-78a6-4754-914e-57eb3680d8e4@googlegroups.com> Cancel-Lock: sha1:D90OD19ktVhSqUpubMRRSLXcD4s= Xref: news.eternal-september.org comp.lang.vhdl:4394 On 5/18/2016 5:42 PM, iamalien wrote: > On Wednesday, May 18, 2016 at 9:02:42 PM UTC+5:30, rickman wrote: >> I seem to be bonking my head against the wall on this one. I have not >> found any standard libraries that convert a string of hex digits to an >> unsigned variable. I thought it would be easy to write my own, but I'm >> having a bit of trouble. >> >> So first, am I reinventing the wheel here? If not, the last issue I'm >> having is converting an integer with value of 0 or 1 to a std_logic or >> unsigned bit. Any suggestions? >> >> I've been beating on this one for an hour and keep finding different >> problems with my approach. >> >> -- >> >> Rick C > > I think someone might have done this earlier, anyway for converting the integer to binary in vhdl you can use this: > std_logic_vector(to_unsigned(your_integer,required_number_of_bits)) > ex, std_logic_vector(to_unsigned(a,8)) (a is signal with integer value less than 256 ofcourse) > And i guess for single bit you could std_logic(to_unsigned(a,1)) (havent used this one, but used the earlier one many times) Yeah, for some reason I think I was wrapped around the axle and this isn't hard at all. I can read the hex digits and make an integer, then convert that to the unsigned easily. I guess I started with the idea of converting one bit of result at a time and didn't pull back to see another way of doing it. It doesn't help that I'm working on this just before bed time... lol. Thanks for turning on the light. Here is what I ended up with... function Hex_to_integer (HexChar : character) return natural is variable temp : natural; begin temp := character'pos(HexChar) - character'pos('0'); if temp > 9 then temp := temp + character'pos('0') + 10 - character'pos('A'); end if; if temp > 15 then temp := temp + character'pos('A') + 10 - character'pos('a'); end if; assert ((temp >= 0) and (temp <= 15)) report "Error converting '" & HexChar & "' as Hex number" severity error; return (temp); end Hex_to_integer; function to_unsigned (HexDigits : string; DigCnt : positive) return unsigned is variable temp : natural := 0; variable unsgnd : unsigned (DigCnt-1 downto 0) := (others => '0'); begin for I in HexDigits'LEFT to HexDigits'RIGHT loop temp := temp + Hex_to_integer (HexDigits (I)); end loop; return (to_unsigned(temp, DigCnt)); end to_unsigned; It seems like more hex related functions should be provided. No? -- Rick C From newsfish@newsfish Thu Aug 1 00:36:50 2024 X-Received: by 10.140.31.130 with SMTP id f2mr31856583qgf.2.1463643868947; Thu, 19 May 2016 00:44:28 -0700 (PDT) X-Received: by 10.50.150.5 with SMTP id ue5mr35616igb.5.1463643868888; Thu, 19 May 2016 00:44:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!11no5025407qgt.0!news-out.google.com!k10ni970igv.0!nntp.google.com!sq19no6450452igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 May 2016 00:44:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.198.79.23; posting-account=siWI1goAAADCu904SmsHiBYIWw1g2Ocr NNTP-Posting-Host: 117.198.79.23 References: <725b0505-78a6-4754-914e-57eb3680d8e4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Hex String to Unsigned From: iamalien Injection-Date: Thu, 19 May 2016 07:44:28 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4395 On Thursday, May 19, 2016 at 11:32:38 AM UTC+5:30, rickman wrote: > On 5/18/2016 5:42 PM, iamalien wrote: > > On Wednesday, May 18, 2016 at 9:02:42 PM UTC+5:30, rickman wrote: > >> I seem to be bonking my head against the wall on this one. I have not > >> found any standard libraries that convert a string of hex digits to an > >> unsigned variable. I thought it would be easy to write my own, but I'm > >> having a bit of trouble. > >> > >> So first, am I reinventing the wheel here? If not, the last issue I'm > >> having is converting an integer with value of 0 or 1 to a std_logic or > >> unsigned bit. Any suggestions? > >> > >> I've been beating on this one for an hour and keep finding different > >> problems with my approach. > >> > >> -- > >> > >> Rick C > > > > I think someone might have done this earlier, anyway for converting the integer to binary in vhdl you can use this: > > std_logic_vector(to_unsigned(your_integer,required_number_of_bits)) > > ex, std_logic_vector(to_unsigned(a,8)) (a is signal with integer value less than 256 ofcourse) > > And i guess for single bit you could std_logic(to_unsigned(a,1)) (havent used this one, but used the earlier one many times) > > Yeah, for some reason I think I was wrapped around the axle and this > isn't hard at all. I can read the hex digits and make an integer, then > convert that to the unsigned easily. I guess I started with the idea of > converting one bit of result at a time and didn't pull back to see > another way of doing it. It doesn't help that I'm working on this just > before bed time... lol. > > Thanks for turning on the light. Here is what I ended up with... > > function Hex_to_integer (HexChar : character) return natural is > variable temp : natural; > begin > temp := character'pos(HexChar) - character'pos('0'); > if temp > 9 then > temp := temp + character'pos('0') + 10 - character'pos('A'); > end if; > if temp > 15 then > temp := temp + character'pos('A') + 10 - character'pos('a'); > end if; > assert ((temp >= 0) and (temp <= 15)) > report "Error converting '" & HexChar & "' as Hex number" > severity error; > return (temp); > end Hex_to_integer; > > function to_unsigned (HexDigits : string; DigCnt : positive) > return unsigned is > variable temp : natural := 0; > variable unsgnd : unsigned (DigCnt-1 downto 0) := (others => '0'); > begin > for I in HexDigits'LEFT to HexDigits'RIGHT loop > temp := temp + Hex_to_integer (HexDigits (I)); > end loop; > return (to_unsigned(temp, DigCnt)); > end to_unsigned; > > > It seems like more hex related functions should be provided. No? > > -- > > Rick C Agreed, like many other functions that should have been there by default :D From newsfish@newsfish Thu Aug 1 00:36:50 2024 X-Received: by 10.157.26.80 with SMTP id u16mr2223400otu.0.1464178609647; Wed, 25 May 2016 05:16:49 -0700 (PDT) X-Received: by 10.50.208.3 with SMTP id ma3mr137530igc.10.1464178609606; Wed, 25 May 2016 05:16:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!q6no1204485igz.0!news-out.google.com!f14ni862ita.0!nntp.google.com!q6no1204482igz.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 May 2016 05:16:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ce9ee05-819d-4b64-adb4-ccede0102c6b@googlegroups.com> Subject: AXI4-Lite, Avalon-MM, UART, I2C and SPI: VHDL BFMs and VVCs for free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Wed, 25 May 2016 12:16:49 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4396 UVVM - the new VHDL verification methodology is a very good way to structur= e your VHDL testbenches - and to make easily understandable, maintainable, = extendible and reusable testbench architectures. UVVM is free and open source, and now a whole set of BFMs and Verification = Components are also available - open source and for free. This allows a ver= y fast kick-off for new users of UVVM, and of course a really good start fo= r any VHDL testbench development. They also serve as examples on how users = can make their own BFMs and VVCs. In fact - if you have already made your B= FM procedures for your proprietary protocol - you can make a VVC for that i= nterface in 15 to 60 minutes. Spend 5 minutes to read our post 'Advanced VHDL Verification - Made simple - For anyone' https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyon= e-espen-tallaksen?trk=3Dmp-author-card, and see for your self how UVVM will= allow far better and more structured testbenches to be implemented far fas= ter than before. (Includes picture, so can't be posted here) UVVM is free and open source, and you can use it for anything you like, wit= h no restrictions other than the standard MIT open source license. UVVM is available from github.com and bitvis.no (released in February 201= 6).=20 Note that advanced randomization and coverage is available with UVVM via th= e included OSVVM or adapted UVVM-OSVVM. Available BFMs and VVCs (VHDL Verification Components) are: - AXI4-Lite - Avalon-MM (Single access so far) - SBI: Simple Bus Interface (Single cycle, optional ready - very simple bus= interface) - UART - I2C - SPI (coming in June) - GPIO (coming in June) As UVVM takes off we expect the VHDL community will make more BFMs and VVCs= available. From newsfish@newsfish Thu Aug 1 00:36:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Hex String to Unsigned Date: Wed, 25 May 2016 23:41:17 -0400 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <573cf0e7$0$1609$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 26 May 2016 03:37:40 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="15363"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18MHrn57jMniRN5zB+KH5yd" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 In-Reply-To: <573cf0e7$0$1609$c3e8da3$5496439d@news.astraweb.com> Cancel-Lock: sha1:6wl9alO5IqPN2yRdkV/aYTe39K0= Xref: news.eternal-september.org comp.lang.vhdl:4397 On 5/18/2016 6:47 PM, Allan Herriman wrote: > On Wed, 18 May 2016 11:32:44 -0400, rickman wrote: > >> I seem to be bonking my head against the wall on this one. I have not >> found any standard libraries that convert a string of hex digits to an >> unsigned variable. I thought it would be easy to write my own, but I'm >> having a bit of trouble. >> >> So first, am I reinventing the wheel here? If not, the last issue I'm >> having is converting an integer with value of 0 or 1 to a std_logic or >> unsigned bit. Any suggestions? >> >> I've been beating on this one for an hour and keep finding different >> problems with my approach. > > > Not standard libraries, but non-standard ones, will do it. > e.g. (Synopsys's) ieee.std_logic_textio has a function called 'hread' > which sounds like it can be made to do what you want. (It reads a line > rather than a string (line is a pointer to a string), and it only works > with std_(u)logic_vector, so you'll need to cast.) > > There's a good chance that this is already supported in your simulator. > > http://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_textio.vhd > > From STD.textio: > type LINE is access STRING; I missed your post. Yes, HREAD pretty much is what I wanted. I wrote mine to work with a vector of any length though. HREAD output has to be a multiple of 4 length. assert FALSE report "HREAD Error: Trying to read vector " & "with an odd (non multiple of 4) length"; I think I should make my own library for hex values. I think I was down this road some years ago and had a few routines I used, but I didn't look for them. I should dig them up and consolidate them as a library. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:51 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Hex String to Unsigned Newsgroups: comp.lang.vhdl References: <573cf0e7$0$1609$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 26 May 2016 05:20:10 GMT Lines: 49 Message-ID: <57468789$0$2823$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 01ddb8d2.news.astraweb.com X-Trace: DXC=HSSnB4kIGXL?0kYOcDh@Z_1m1SOGk_>W\>T:^Al174X On 5/18/2016 6:47 PM, Allan Herriman wrote: >> On Wed, 18 May 2016 11:32:44 -0400, rickman wrote: >> >>> I seem to be bonking my head against the wall on this one. I have not >>> found any standard libraries that convert a string of hex digits to an >>> unsigned variable. I thought it would be easy to write my own, but >>> I'm having a bit of trouble. >>> >>> So first, am I reinventing the wheel here? If not, the last issue I'm >>> having is converting an integer with value of 0 or 1 to a std_logic or >>> unsigned bit. Any suggestions? >>> >>> I've been beating on this one for an hour and keep finding different >>> problems with my approach. >> >> >> Not standard libraries, but non-standard ones, will do it. >> e.g. (Synopsys's) ieee.std_logic_textio has a function called 'hread' >> which sounds like it can be made to do what you want. (It reads a line >> rather than a string (line is a pointer to a string), and it only works >> with std_(u)logic_vector, so you'll need to cast.) >> >> There's a good chance that this is already supported in your simulator. >> >> http://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_textio.vhd >> >> From STD.textio: >> type LINE is access STRING; > > I missed your post. Yes, HREAD pretty much is what I wanted. I wrote > mine to work with a vector of any length though. HREAD output has to be > a multiple of 4 length. > > assert FALSE report > "HREAD Error: Trying to read vector " & > "with an odd (non multiple of 4) length"; > > I think I should make my own library for hex values. I think I was down > this road some years ago and had a few routines I used, but I didn't > look for them. I should dig them up and consolidate them as a library. Just about every heavy VHDL user I know has their own text processing library. This points to a problem with the language - it really needed a standardised, open/free, versatile text processing library in the '90s. Regards, Allan From newsfish@newsfish Thu Aug 1 00:36:51 2024 X-Received: by 10.98.26.13 with SMTP id a13mr24695407pfa.12.1464724389452; Tue, 31 May 2016 12:53:09 -0700 (PDT) X-Received: by 10.157.56.116 with SMTP id r49mr2754otd.19.1464724389137; Tue, 31 May 2016 12:53:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q32no1947710qgq.0!news-out.google.com!g40ni234qge.1!nntp.google.com!q32no1947705qgq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 May 2016 12:53:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.82.220; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.82.220 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1458e449-473a-4023-b05d-9e6eebdfebab@googlegroups.com> Subject: Re: Hex String to Unsigned From: Jim Lewis Injection-Date: Tue, 31 May 2016 19:53:09 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1442 X-Received-Body-CRC: 1275137038 Xref: news.eternal-september.org comp.lang.vhdl:4399 Hi Rick Turn on VHDL-2008. It is a testbench after all. Then use ieee.numeric_std= .hread. Like your procedure, none of the VHDL-2008 procedures require the= length to be a multiple of 4 bits. Hread was also added for std_logic_vec= tor/std_ulogic_vector and signed in the same package in which the types are= defined. =20 Cheers,=20 Jim=20 From newsfish@newsfish Thu Aug 1 00:36:51 2024 X-Received: by 10.176.65.106 with SMTP id j97mr1895959uad.11.1464769542044; Wed, 01 Jun 2016 01:25:42 -0700 (PDT) X-Received: by 10.157.24.88 with SMTP id t24mr31274ott.18.1464769541967; Wed, 01 Jun 2016 01:25:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!q32no2138376qgq.0!news-out.google.com!z5ni99qge.0!nntp.google.com!q32no2138372qgq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jun 2016 01:25:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.178.68.134; posting-account=Eai9nQoAAADWhSIVdc0G4Z9jh8TwVNw0 NNTP-Posting-Host: 212.178.68.134 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> Subject: Assign record elements of array From: geve115@gmail.com Injection-Date: Wed, 01 Jun 2016 08:25:41 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4400 Hi VHDL gurus, Below a few snippets from code which behaves not as expected. I am wonderin= g if it is a tool issue or that it is forbidden by the language. type rt_rec_type is record data_i : std_logic_vector(31 downto 0); busy : std_logic; header : std_logic; dest : std_logic_vector(3 downto 0); end record rt_rec_type; type t_channels is array (0 to 7) of rt_rec_type; gen1 : for i in 0 to 7 generate channels(i).data_i <=3D (others =3D> =E2=80=980=E2=80=99); channels(i).header <=3D =E2=80=980=E2=80=99; end generate gen1; p_data : process(clk) is begin if rising_edge(clk) then if resetn =3D =E2=80=980=E2=80=99 then for i in 0 to 7 generate channels(i).busy <=3D =E2=80=980=E2=80=99; channels(i).dest <=3D (others =3D> =E2=80=980=E2=80=99); end for; ..... end process; What we see in Modelsim is that data_i and header are still =E2=80=98U=E2= =80=99 and not initialised as expected. Modelsim steps through the lines of= data_i and header at 0 ps + 0. When we move these signals inside the process and add them to the reset the= y are initialised. Is it forbidden by the language to assign the record ele= ments at different places? Thanks, Devas From newsfish@newsfish Thu Aug 1 00:36:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Assign record elements of array Date: Wed, 1 Jun 2016 23:46:33 -0400 Organization: A noiseless patient Spider Lines: 55 Message-ID: References: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 2 Jun 2016 03:46:39 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="447f9ef61c9649341f72e8e609e4ea79"; logging-data="16794"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/oRXXHAr8AX8jsTZzAr7o6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 In-Reply-To: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> Cancel-Lock: sha1:f9S6RpvMyGVVlGDXooecsI0Yiv4= Xref: news.eternal-september.org comp.lang.vhdl:4401 On 6/1/2016 4:25 AM, geve115@gmail.com wrote: > Hi VHDL gurus, > > Below a few snippets from code which behaves not as expected. I am wondering if it is a tool issue or that it is forbidden by the language. > > type rt_rec_type is record > data_i : std_logic_vector(31 downto 0); > busy : std_logic; > header : std_logic; > dest : std_logic_vector(3 downto 0); > end record rt_rec_type; > > type t_channels is array (0 to 7) of rt_rec_type; > > gen1 : for i in 0 to 7 generate > channels(i).data_i <= (others => ‘0’); > channels(i).header <= ‘0’; > end generate gen1; > > p_data : process(clk) is > begin > if rising_edge(clk) then > if resetn = ‘0’ then > for i in 0 to 7 generate > channels(i).busy <= ‘0’; > channels(i).dest <= (others => ‘0’); > end for; > ..... > end process; > > What we see in Modelsim is that data_i and header are still ‘U’ and not initialised as expected. Modelsim steps through the lines of data_i and header at 0 ps + 0. > When we move these signals inside the process and add them to the reset they are initialised. Is it forbidden by the language to assign the record elements at different places? Hi, I'm not certain but I have seen a similar thing where part of an array is assigned in a process and the other part of the array is assigned in another process or a concurrent statement. There is a rule that says under certain circumstances an assignment to part of the array causes the entire array to be assigned a value, in other words a driver is created for every bit in a vector. You may be seeing something similar for the entire record when you assign part of the record. You don't show the rest of the code, so I can't understand why you would want to assign the values to .data_i and .header in a generate statement. This will create drives for at least this part of the record that will always be fixed to '0', in other words a constant. a generate statement can not be used for initialization of a signal that you wish to change at other times. So what are you really trying to do with the various fields of this record? -- Rick C From newsfish@newsfish Thu Aug 1 00:36:52 2024 X-Received: by 10.159.37.72 with SMTP id 66mr6229376uaz.9.1464850179850; Wed, 01 Jun 2016 23:49:39 -0700 (PDT) X-Received: by 10.157.27.100 with SMTP id l91mr110233otl.7.1464850179770; Wed, 01 Jun 2016 23:49:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p34no1522394qgp.1!news-out.google.com!z5ni210qge.0!nntp.google.com!p34no1522392qgp.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jun 2016 23:49:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.178.68.134; posting-account=Eai9nQoAAADWhSIVdc0G4Z9jh8TwVNw0 NNTP-Posting-Host: 212.178.68.134 References: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Assign record elements of array From: geve115@gmail.com Injection-Date: Thu, 02 Jun 2016 06:49:39 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2635 X-Received-Body-CRC: 4185715910 Xref: news.eternal-september.org comp.lang.vhdl:4402 > Hi, >=20 > I'm not certain but I have seen a similar thing where part of an array=20 > is assigned in a process and the other part of the array is assigned in= =20 > another process or a concurrent statement. There is a rule that says=20 > under certain circumstances an assignment to part of the array causes=20 > the entire array to be assigned a value, in other words a driver is=20 > created for every bit in a vector. You may be seeing something similar= =20 > for the entire record when you assign part of the record. >=20 > You don't show the rest of the code, so I can't understand why you would= =20 > want to assign the values to .data_i and .header in a generate=20 > statement. This will create drives for at least this part of the record= =20 > that will always be fixed to '0', in other words a constant. a generate= =20 > statement can not be used for initialization of a signal that you wish=20 > to change at other times. >=20 > So what are you really trying to do with the various fields of this recor= d? >=20 > --=20 >=20 > Rick C Hi Rick, Thank you for the answer, so it is a language issue and not a tool issue.= =20 I modified the code and naming but it was to show that some record elements= were assigned constants in the generate statement and others in the proces= s statement. At this moment in the project some record elements are not use= d. The used elements are assigned in the process statement. Best regards, Devas From newsfish@newsfish Thu Aug 1 00:36:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!peer03.fr7!news.highwinds-media.com!fx44.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Assign record elements of array References: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 160601-7, 01/06/2016), Outbound message X-Antivirus-Status: Clean Lines: 48 Message-ID: NNTP-Posting-Host: 81.107.0.228 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1464855689 81.107.0.228 (Thu, 02 Jun 2016 08:21:29 UTC) NNTP-Posting-Date: Thu, 02 Jun 2016 08:21:29 UTC Organization: virginmedia.com Date: Thu, 2 Jun 2016 09:21:26 +0100 X-Received-Body-CRC: 3575588856 X-Received-Bytes: 3048 Xref: news.eternal-september.org comp.lang.vhdl:4403 On 02/06/2016 07:49, geve115@gmail.com wrote: >> Hi, >> >> I'm not certain but I have seen a similar thing where part of an array >> is assigned in a process and the other part of the array is assigned in >> another process or a concurrent statement. There is a rule that says >> under certain circumstances an assignment to part of the array causes >> the entire array to be assigned a value, in other words a driver is >> created for every bit in a vector. You may be seeing something similar >> for the entire record when you assign part of the record. >> >> You don't show the rest of the code, so I can't understand why you would >> want to assign the values to .data_i and .header in a generate >> statement. This will create drives for at least this part of the record >> that will always be fixed to '0', in other words a constant. a generate >> statement can not be used for initialization of a signal that you wish >> to change at other times. >> >> So what are you really trying to do with the various fields of this record? >> >> -- >> >> Rick C > Hi Rick, > > Thank you for the answer, so it is a language issue and not a tool issue. > I modified the code and naming but it was to show that some record elements were assigned constants in the generate statement and others in the process statement. At this moment in the project some record elements are not used. The used elements are assigned in the process statement. > > Best regards, > > Devas > Hi Devas, This question comes up at least once every year. Have a look at this question (taken from a presentation in the UK many years ago): http://www.ht-lab.com/index_htm_files/question.jpg the correct (for most unexpected) answer is here: http://www.ht-lab.com/index_htm_files/answer.jpg Luckily VHDL only has a few language quirks.... Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:36:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Assign record elements of array Date: Thu, 02 Jun 2016 15:10:36 +0300 Organization: An impatient and LOUD arachnid Lines: 20 Message-ID: References: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain Injection-Info: mx02.eternal-september.org; posting-host="7007fd4d41918b6b81375668d3a8875f"; logging-data="3593"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Fi2+4K+kujmpjAv0HoyJe" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) Cancel-Lock: sha1:ar2UJZiwuVaEAE4ifzKGSE4uFNc= sha1:GDd/cbvxaYGiR0/NqXZp5pHmH/E= Xref: news.eternal-september.org comp.lang.vhdl:4404 HT-Lab writes: > This question comes up at least once every year. Have a look at this > question (taken from a presentation in the UK many years ago): > > http://www.ht-lab.com/index_htm_files/question.jpg > > the correct (for most unexpected) answer is here: > > http://www.ht-lab.com/index_htm_files/answer.jpg > > Luckily VHDL only has a few language quirks.... Come to think of it, is someone maintaining the comp.lang.vhdl FAQ still? I found a copy at https://tams.informatik.uni-hamburg.de/vhdl/index.php?content=02-faq but I don't know if it's the last version. A lot of Google hits seem to point to vhdl.org or eda.org which point today to accellera.org and they don't seem to have it. From newsfish@newsfish Thu Aug 1 00:36:53 2024 X-Received: by 10.66.82.70 with SMTP id g6mr2284667pay.39.1464871136600; Thu, 02 Jun 2016 05:38:56 -0700 (PDT) X-Received: by 10.157.1.4 with SMTP id 4mr176085otu.14.1464871136337; Thu, 02 Jun 2016 05:38:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!p34no1650643qgp.1!news-out.google.com!g40ni26qge.1!nntp.google.com!p34no1650638qgp.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 2 Jun 2016 05:38:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.178.68.134; posting-account=Eai9nQoAAADWhSIVdc0G4Z9jh8TwVNw0 NNTP-Posting-Host: 212.178.68.134 References: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9fd99af4-192f-42ad-8ded-562a7b40e75d@googlegroups.com> Subject: Re: Assign record elements of array From: Devas Injection-Date: Thu, 02 Jun 2016 12:38:56 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4405 On Thursday, June 2, 2016 at 10:21:33 AM UTC+2, HT-Lab wrote: > >> Hi, > >> > >> I'm not certain but I have seen a similar thing where part of an array > >> is assigned in a process and the other part of the array is assigned i= n > >> another process or a concurrent statement. There is a rule that says > >> under certain circumstances an assignment to part of the array causes > >> the entire array to be assigned a value, in other words a driver is > >> created for every bit in a vector. You may be seeing something simila= r > >> for the entire record when you assign part of the record. > >> > >> You don't show the rest of the code, so I can't understand why you wou= ld > >> want to assign the values to .data_i and .header in a generate > >> statement. This will create drives for at least this part of the reco= rd > >> that will always be fixed to '0', in other words a constant. a genera= te > >> statement can not be used for initialization of a signal that you wish > >> to change at other times. > >> > >> So what are you really trying to do with the various fields of this re= cord? > >> > >> -- > >> > >> Rick C > > Hi Rick, > > > > Thank you for the answer, so it is a language issue and not a tool issu= e. > > I modified the code and naming but it was to show that some record elem= ents were assigned constants in the generate statement and others in the pr= ocess statement. At this moment in the project some record elements are not= used. The used elements are assigned in the process statement. > > > > Best regards, > > > > Devas > > > Hi Devas, >=20 > This question comes up at least once every year. Have a look at this=20 > question (taken from a presentation in the UK many years ago): >=20 > http://www.ht-lab.com/index_htm_files/question.jpg >=20 > the correct (for most unexpected) answer is here: >=20 > http://www.ht-lab.com/index_htm_files/answer.jpg >=20 > Luckily VHDL only has a few language quirks.... >=20 > Hans > www.ht-lab.com Hi Hans, Thank you for pointing me to the right search item "longest static prefix".= It is an interesting topic.=20 Mostly you write code without any issue, but sometimes you want to write it= a little bit less complex/try new ideas and you get in conflict with the L= RM. Devas From newsfish@newsfish Thu Aug 1 00:36:53 2024 X-Received: by 10.129.158.14 with SMTP id v14mr186672ywg.57.1464902709047; Thu, 02 Jun 2016 14:25:09 -0700 (PDT) X-Received: by 10.157.40.228 with SMTP id s91mr7315ota.13.1464902708965; Thu, 02 Jun 2016 14:25:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!2.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!p34no1869655qgp.1!news-out.google.com!z5ni300qge.0!nntp.google.com!p34no1869650qgp.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 2 Jun 2016 14:25:08 -0700 (PDT) In-Reply-To: <9fd99af4-192f-42ad-8ded-562a7b40e75d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.239.112.66; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 125.239.112.66 References: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> <9fd99af4-192f-42ad-8ded-562a7b40e75d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Assign record elements of array From: diogratia@gmail.com Injection-Date: Thu, 02 Jun 2016 21:25:08 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 179 Xref: news.eternal-september.org comp.lang.vhdl:4406 On Friday, June 3, 2016 at 12:38:58 AM UTC+12, Devas wrote: > On Thursday, June 2, 2016 at 10:21:33 AM UTC+2, HT-Lab wrote: > > >> Hi, > > >> > > >> I'm not certain but I have seen a similar thing where part of an arr= ay > > >> is assigned in a process and the other part of the array is assigned= in > > >> another process or a concurrent statement. There is a rule that say= s > > >> under certain circumstances an assignment to part of the array cause= s > > >> the entire array to be assigned a value, in other words a driver is > > >> created for every bit in a vector. You may be seeing something simi= lar > > >> for the entire record when you assign part of the record. > > >> > > >> You don't show the rest of the code, so I can't understand why you w= ould > > >> want to assign the values to .data_i and .header in a generate > > >> statement. This will create drives for at least this part of the re= cord > > >> that will always be fixed to '0', in other words a constant. a gene= rate > > >> statement can not be used for initialization of a signal that you wi= sh > > >> to change at other times. > > >> > > >> So what are you really trying to do with the various fields of this = record? > > >> > > >> -- > > >> > > >> Rick C > > > Hi Rick, > > > > > > Thank you for the answer, so it is a language issue and not a tool is= sue. > > > I modified the code and naming but it was to show that some record el= ements were assigned constants in the generate statement and others in the = process statement. At this moment in the project some record elements are n= ot used. The used elements are assigned in the process statement. > > > > > > Best regards, > > > > > > Devas > > > > > Hi Devas, > >=20 > > This question comes up at least once every year. Have a look at this=20 > > question (taken from a presentation in the UK many years ago): > >=20 > > http://www.ht-lab.com/index_htm_files/question.jpg > >=20 > > the correct (for most unexpected) answer is here: > >=20 > > http://www.ht-lab.com/index_htm_files/answer.jpg > >=20 > > Luckily VHDL only has a few language quirks.... > >=20 > > Hans > > www.ht-lab.com >=20 > Thank you for pointing me to the right search item "longest static prefix= ". It is an interesting topic.=20 This isn't a longest static prefix issue This can be demonstrated by examin= ing how a generate statement (a concurrent statement, not the mistaken use = in the process statement where generate should be loop) is elaborated: >From IEEE Std 1076-2008 11.8 Generate Statements paragraph 10 (11. is Concu= rrent statements): The elaboration of a generate statement is given in 14.5.3. 14.5.3 Generate statements, paragraph 2 (14.5 is Elaboration of a statement= part): For a for generate statement, elaboration consists of the elaboration of th= e=20 discrete range, followed by the generation of one block statement for each= =20 value in the range. The block statements all have the following form: a) The label of the block statement is the same as the label of the for= =20 generate statement. b) The block declarative part has, as its first item, a single constant= =20 declaration that declares a constant with the same simple name as th= at=20 of the applicable generate parameter; the value of the constant is t= he=20 value of the generate parameter for the generation of this particula= r=20 block statement. The type of this declaration is determined by the b= ase=20 type of the discrete range of the generate parameter. The remainder = of=20 the block declarative part consists of a copy of the declarative ite= ms=20 contained within the generate statement. c) The block statement part consists of a copy of the concurrent statem= ents=20 contained within the gener- ate statement. So the generate parameter (i) is declared as a constant in each of the gene= rated block statements with the value of i for the particular generated blo= ck statement. =20 That takes this out of the running for a longest static prefix issue. See 8= . Names, 8.1 General paragraph 7: A static signal name is a static name that denotes a signal. The longest st= atic prefix of a signal name is the name itself, if the name is a static si= gnal name; otherwise, it is the longest prefix of the name that is a static= signal name. Similarly, a static variable name is a static name that denot= es a variable, and the longest static prefix of a variable name is the name= itself, if the name is a static variable name; otherwise, it is the longes= t prefix of the name that is a static variable name. And to understand that channels(i).data_i or channels(i).header are static= names we look to 9. Expressions, 9.4 Static expressions, 9.4.3 Globally st= atic primaries: d) A generate parameter And back to 8.1 the paragraph 5: A name is said to be a static name if and only if one of the following=20 conditions holds: =E2=80=94 The name is a simple name or selected name (including those t= hat are=20 expanded names) that does not denote a function call, an object or va= lue of an access type, or an object of a protected type and (in the case = of a selected name) whose prefix is a static name. =E2=80=94 The name is an indexed name whose prefix is a static name, an= d every=20 expression that appears as part of the name is a static expression. =E2=80=94 The name is a slice name whose prefix is a static name and wh= ose discrete range is a static discrete range. =E2=80=94 The name is an attribute name whose prefix is a static signal= name and whose suffix is one of the pre- defined attributes 'DELAYED, 'STABLE,= =20 'QUIET, or 'TRANSACTION. =E2=80=94 The name is an external name. So the names used in the generate statements are static names. And as a res= ult the longest static prefix is the entire selected name for channels(i).d= ata_i or channels(i).header. If it isn't a longest static prefix issue it's simply multiple drivers. 14.7.2 Drivers (pargraph 1, the first sentence): Every signal assignment statement in a process statement defines a set of= =20 drivers for certain scalar signals. The processes elaborated from the concurrent assignment statements from the= generate statement have drivers for their selected names specified by thei= r static names (channels(i).data_i or channels(i).header) giving rise to yo= ur problem: On Wed, 1 Jun 2016 01:25:41 -0700 (PDT), Devas wrote: >What we see in Modelsim is that data_i and header are still =E2=80=98U=E2= =80=99 and not initialised as expected. ... A longest static prefix related issue derived from the generate statement w= ould have unknown values on all the record elements and not just the two wi= th drivers in the eight generated block statements two processes. You should be counting on resetn to insure the state of channels. It's wort= h evaluating how channels is used in determining reset sequence (either asy= nchronous reset somewhere or reset duration of multiple clock cycles). From newsfish@newsfish Thu Aug 1 00:36:54 2024 X-Received: by 10.140.91.136 with SMTP id z8mr417580qgd.12.1464905645381; Thu, 02 Jun 2016 15:14:05 -0700 (PDT) X-Received: by 10.157.52.180 with SMTP id g49mr11739otc.8.1464905645329; Thu, 02 Jun 2016 15:14:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p34no1882927qgp.1!news-out.google.com!g40ni58qge.1!nntp.google.com!q32no2902088qgq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 2 Jun 2016 15:14:05 -0700 (PDT) In-Reply-To: <9fd99af4-192f-42ad-8ded-562a7b40e75d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.239.112.66; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 125.239.112.66 References: <2a8ba5fb-2a6a-469a-af73-00693973c43e@googlegroups.com> <9fd99af4-192f-42ad-8ded-562a7b40e75d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <737b27cd-fe39-48bd-ac1a-93a571d24a8f@googlegroups.com> Subject: Re: Assign record elements of array From: diogratia@gmail.com Injection-Date: Thu, 02 Jun 2016 22:14:05 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 11477 X-Received-Body-CRC: 3921377245 Xref: news.eternal-september.org comp.lang.vhdl:4407 On Friday, June 3, 2016 at 12:38:58 AM UTC+12, Devas wrote: > On Thursday, June 2, 2016 at 10:21:33 AM UTC+2, HT-Lab wrote: > > >> Hi, > > >> > > >> I'm not certain but I have seen a similar thing where part of an arr= ay > > >> is assigned in a process and the other part of the array is assigned= in > > >> another process or a concurrent statement. There is a rule that say= s > > >> under certain circumstances an assignment to part of the array cause= s > > >> the entire array to be assigned a value, in other words a driver is > > >> created for every bit in a vector. You may be seeing something simi= lar > > >> for the entire record when you assign part of the record. > > >> > > >> You don't show the rest of the code, so I can't understand why you w= ould > > >> want to assign the values to .data_i and .header in a generate > > >> statement. This will create drives for at least this part of the re= cord > > >> that will always be fixed to '0', in other words a constant. a gene= rate > > >> statement can not be used for initialization of a signal that you wi= sh > > >> to change at other times. > > >> > > >> So what are you really trying to do with the various fields of this = record? > > >> > > >> -- > > >> > > >> Rick C > > > Hi Rick, > > > > > > Thank you for the answer, so it is a language issue and not a tool is= sue. > > > I modified the code and naming but it was to show that some record el= ements were assigned constants in the generate statement and others in the = process statement. At this moment in the project some record elements are n= ot used. The used elements are assigned in the process statement. > > > > > > Best regards, > > > > > > Devas > > > > > Hi Devas, > >=20 > > This question comes up at least once every year. Have a look at this=20 > > question (taken from a presentation in the UK many years ago): > >=20 > > http://www.ht-lab.com/index_htm_files/question.jpg > >=20 > > the correct (for most unexpected) answer is here: > >=20 > > http://www.ht-lab.com/index_htm_files/answer.jpg > >=20 > > Luckily VHDL only has a few language quirks.... > >=20 > > Hans > > www.ht-lab.com >=20 > Hi Hans, >=20 > Thank you for pointing me to the right search item "longest static prefix= ". It is an interesting topic.=20 > Mostly you write code without any issue, but sometimes you want to write = it a little bit less complex/try new ideas and you get in conflict with the= LRM. >=20 > Devas This isn't a longest static prefix issue This can be demonstrated by examin= ing how a generate statement (a concurrent statement, not the mistaken use = in the process statement where generate should be loop) is elaborated: >From IEEE Std 1076-2008 11.8 Generate Statements paragraph 10 (11. is Concu= rrent statements): The elaboration of a generate statement is given in 14.5.3. 14.5.3 Generate statements, paragraph 2 (14.5 is Elaboration of a statement= part): For a for generate statement, elaboration consists of the elaboration of th= e=20 discrete range, followed by the generation of one block statement for each= =20 value in the range. The block statements all have the following form: a) The label of the block statement is the same as the label of the for= =20 generate statement. b) The block declarative part has, as its first item, a single constant= =20 declaration that declares a constant with the same simple name as th= at=20 of the applicable generate parameter; the value of the constant is t= he=20 value of the generate parameter for the generation of this particula= r=20 block statement. The type of this declaration is determined by the b= ase=20 type of the discrete range of the generate parameter. The remainder = of=20 the block declarative part consists of a copy of the declarative ite= ms=20 contained within the generate statement. c) The block statement part consists of a copy of the concurrent statem= ents=20 contained within the gener- ate statement. So the generate parameter (i) is declared as a constant in each of the gene= rated block statements with the value of i for the particular generated blo= ck statement. =20 That takes this out of the running for a longest static prefix issue. See 8= . Names, 8.1 General paragraph 7: A static signal name is a static name that denotes a signal. The longest st= atic prefix of a signal name is the name itself, if the name is a static si= gnal name; otherwise, it is the longest prefix of the name that is a static= signal name. Similarly, a static variable name is a static name that denot= es a variable, and the longest static prefix of a variable name is the name= itself, if the name is a static variable name; otherwise, it is the longes= t prefix of the name that is a static variable name. And to understand that channels(i).data_i or channels(i).header are static= names we look to 9. Expressions, 9.4 Static expressions, 9.4.3 Globally st= atic primaries: d) A generate parameter And back to 8.1 the paragraph 5: A name is said to be a static name if and only if one of the following=20 conditions holds: =E2=80=94 The name is a simple name or selected name (including those t= hat are=20 expanded names) that does not denote a function call, an object or va= lue of an access type, or an object of a protected type and (in the case = of a selected name) whose prefix is a static name. =E2=80=94 The name is an indexed name whose prefix is a static name, an= d every=20 expression that appears as part of the name is a static expression. =E2=80=94 The name is a slice name whose prefix is a static name and wh= ose discrete range is a static discrete range. =E2=80=94 The name is an attribute name whose prefix is a static signal= name and whose suffix is one of the pre- defined attributes 'DELAYED, 'STABLE,= =20 'QUIET, or 'TRANSACTION. =E2=80=94 The name is an external name. So the names used in the generate statements are static names. And as a res= ult the longest static prefix is the entire selected name for channels(i).d= ata_i or channels(i).header. If it isn't a longest static prefix issue it's simply multiple drivers. 14.7 Execution of a model, 14.7.2 Drivers pargraph 1: Every signal assignment statement in a process statement defines a set o drivers for certain scalar signals. There is a single driver for a given sc= alar=20 signal S in a process statement, provided that there is at least one signal= =20 assignment statement in that process statement and that the longest static= =20 prefix of the target signal of that signal assignment statement denotes S o= r=20 denotes a composite signal of which S is a subelement. Each such signal=20 assignment statement is said to be associated with that driver. Execution o= f a=20 signal assignment statement affects only the associated driver(s). The processes elaborated from the concurrent assignment statements from the= generate statement have drivers for their selected names specified by thei= r static names (channels(i).data_i or channels(i).header) giving rise to yo= ur problem: On Wed, 1 Jun 2016 01:25:41 -0700 (PDT), Devas wrote: >What we see in Modelsim is that data_i and header are still =E2=80=98U=E2= =80=99 and not initialised as expected. ... A longest static prefix related issue derived from the generate statement w= ould have unknown values on all the record elements and not just the two wi= th drivers in the eight generated block statements two processes. You should be counting on resetn to insure the state of channels. It's wort= h evaluating how channels is used in determining reset sequence (either asy= nchronous reset somewhere or reset duration of multiple clock cycles). You could also supply an initial value to the entire array of records as sh= own in the declaration of signal channels: library ieee; -- added context clause use ieee.std_logic_1164.all; entity davos is -- added entity declaration port ( signal clk: std_logic; signal resetn: std_logic ); end entity; architecture foo of davos is -- added architecture type rt_rec_type is record data_i: std_logic_vector(31 downto 0); busy: std_logic; header: std_logic; dest: std_logic_vector(3 downto 0); end record rt_rec_type; type t_channels is array (0 to 7) of rt_rec_type; =20 signal channels: t_channels :=3D ( others =3D> ( -- Added signal dec= laration data_i =3D> (others =3D> '0'), busy =3D> '0', header =3D> '0', dest =3D> (others =3D> '0') ) ); begin =20 -- gen1: -- for i in 0 to 7 generate -- channels(i).data_i <=3D (others =3D> '0'); -- channels(i).header <=3D '0'; -- end generate gen1; p_data: process(clk) is begin if rising_edge(clk) then if resetn =3D '0' then for i in 0 to 7 loop -- loop is exected instead of generate channels(i).busy <=3D '0'; channels(i).dest <=3D (others =3D> '0'); end loop; -- loop is expected instead of for=20 -- .... end if; -- added end end if; -- added end=20 end process; end architecture; -- Also substituted apostrophe for back tick in character literal '0' insta= nces Note this implies you simply chuck out the generate statement. The above c= ode analyzes successfully. Complexity comes from VHDL being a formal notation whose semantics covers b= oth design models and simulation. From newsfish@newsfish Thu Aug 1 00:36:54 2024 X-Received: by 10.140.176.75 with SMTP id w72mr21224097qhw.30.1465400490875; Wed, 08 Jun 2016 08:41:30 -0700 (PDT) X-Received: by 10.36.36.211 with SMTP id f202mr336905ita.8.1465400490835; Wed, 08 Jun 2016 08:41:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p34no4284962qgp.1!news-out.google.com!107ni276qgx.1!nntp.google.com!q32no5304669qgq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 8 Jun 2016 08:41:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.64.129.195; posting-account=H7cinwoAAADYsIQpk3VLrSzu-G7o6bIW NNTP-Posting-Host: 2.64.129.195 References: <109ab6b9-1e5a-490d-8ff6-8ac59351dafb@googlegroups.com> <951ea014-9598-41ef-9e1b-f663a2323755@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <59aa6f2b-babc-4f68-a398-ae8a6af73a67@googlegroups.com> Subject: Re: Book for Vhdl From: lars.synective@gmail.com Injection-Date: Wed, 08 Jun 2016 15:41:30 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1741 X-Received-Body-CRC: 3567999186 Xref: news.eternal-september.org comp.lang.vhdl:4408 I like The Designer's Guide to VHDL (https://www.amazon.com/gp/aw/d/0120887= 851?pc_redir=3DT1) which covers the language very well. I've also started t= o read Effective Coding with VHDL (https://mitpress.mit.edu/books/effective= -coding-vhdl) which has a focus on reusing, where applicable, SW best pract= ices on VHDL. So far I've read a few of those chapters and they are good. N= othing new really but I haven't seen this kind of information in a book on = VHDL before. Much of this is missed by many VHDL developers so the book wor= th reading. From newsfish@newsfish Thu Aug 1 00:36:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Cecil Bayona Newsgroups: comp.lang.vhdl Subject: Re: Book for Vhdl Date: Wed, 8 Jun 2016 12:17:24 -0500 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <109ab6b9-1e5a-490d-8ff6-8ac59351dafb@googlegroups.com> <951ea014-9598-41ef-9e1b-f663a2323755@googlegroups.com> <59aa6f2b-babc-4f68-a398-ae8a6af73a67@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 8 Jun 2016 17:17:26 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4c6149fda0f382b24075b7a1eefa3518"; logging-data="25527"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX184Y8MRgr3t+2oW++j1F0yi" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <59aa6f2b-babc-4f68-a398-ae8a6af73a67@googlegroups.com> Cancel-Lock: sha1:KbaXTq15/UxUF5G8D6x0jVuFl7M= Xref: news.eternal-september.org comp.lang.vhdl:4409 On 6/8/2016 10:41 AM, lars.synective@gmail.com wrote: > I like The Designer's Guide to VHDL (https://www.amazon.com/gp/aw/d/0120887851?pc_redir=T1) which covers the language very well. I purchased that book and it arrived yesterday, it did look like a good book. I bought it for $18 , brand new, I just looked now and the prices have doubled. I've also started to read Effective Coding with VHDL (https://mitpress.mit.edu/books/effective-coding-vhdl) which has a focus on reusing, where applicable, SW best practices on VHDL. So far I've read a few of those chapters and they are good. Nothing new really but I haven't seen this kind of information in a book on VHDL before. Much of this is missed by many VHDL developers so the book worth reading. > A little more expensive, $40 for a used copy but looking inside, it seems to be a decent book. Not available as a Kindle book, if it was I buy it right now. -- Cecil - k5nwa From newsfish@newsfish Thu Aug 1 00:36:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: "rising_edge(clk)" and delay Date: Fri, 10 Jun 2016 08:53:52 +0200 Organization: A noiseless patient Spider Lines: 131 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 10 Jun 2016 06:53:53 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="2eb04a1472f6cba667248c85d54ced2f"; logging-data="5204"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+RHnMpxLcMuZPY8LzOWHSI" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 Cancel-Lock: sha1:cn1l+lJIrBU9LbrUkyg+MPVOfmo= Xref: news.eternal-september.org comp.lang.vhdl:4410 Hi, I know this is very much a beginners question but I did try to find the answer online and at a couple of books but have not yet found an clear answer. I'll ask the question based on a practicle example: in a process, I need to to things at two different rates: certain things at the full clock rate and a slower clock. I have a basic clock 12 Mhz clock, so I build a clock-divider. But, as I know I will need that slower clock in multiple places, my idea would be to have a seperate process for creating the 1 Khz clock and feed that into the processes that need that. My code is below. I have two questions from a generic "how to design a syncrounous system" one. 1/ Is this the right way to do this? Does it make sence to create one clock-divider as a seperate process and feed then then into other process? (so not to have to synthesiser to create one per every process that needs one). Or can I just code the clock-divider into every process that needs that. (Perhaps the synthesier will optimise the design anyway and do all the work for me). 2/ From a timing point of view, the div12000-clock output of the clock divider sits after some logic and is then feed into the other processes. I guess this will create some delay. But in the processes that actually use that clock (processes "a" and "b" in my example) , the vhdl code to check on that signal sits behind a "rising_edge(clk_in)", which is -if I am correct- a very short timespan. Will this not result in timing-issues? Can I be sure that the "slowclock = 1" will arrive in process "a" and "b" fast enough. Or will the synthesiser do special things to make sure it will. (perhaps delay clk_in in the processes "a" and "b" a little bit). Or, in a more generic sence, When doing an initial design of a syncrounous system, do you need to take timing-issues like this in account? Or can I just assume there is zero-delay in all processes and let timing-issues be dealt with by the synthesizer? (I did read some comments that it will at least check certain elements concerning timing of the design). I did a very interesting post in a forum that clock-signals in a FPGA are special and that clock-signals pass over special "lanes" (or whatever the correct term is) so they arrive at all places in the chip at the same moment. It would however be interesting to find some information on how to deal with clock-signals (especially if you create them yourself in a clock-divider) in a syncronous design. --- cut here --- cut here --- cut here --- clockdiv12000: process (clk_in) is begin if (rising_edge(clk_in) then if (counter = 11999) then counter <= 0; slowclock <= '1'; else counter <= counter + 1; slowclock <= '0'; end if; end if; -- end rising_edge end process clockdiv8000; a: process (clk_in, slowclock, in1, in2) is begin if (rising_edge(clk_in) then (do some stuff at 8 Mhz clock) if (slowclock = '1') then (do some stuff at 1 Khz clock) end if; end if; end process a; b: process (clk_in, slowclock, in3, in4) is begin if (rising_edge(clk_in) then (do some stuff at 8 Mhz clock) if (slowclock = '1') then (do some stuff at 1 Khz clock) end if; end if; end process b; --- cut here --- cut here --- cut here --- Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:55 2024 X-Received: by 10.157.51.23 with SMTP id f23mr811679otc.39.1465556296231; Fri, 10 Jun 2016 03:58:16 -0700 (PDT) X-Received: by 10.36.79.141 with SMTP id c135mr641159itb.10.1465556296158; Fri, 10 Jun 2016 03:58:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v48no80661qgd.0!news-out.google.com!107ni149qgx.1!nntp.google.com!v48no80656qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Jun 2016 03:58:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Subject: Re: "rising_edge(clk)" and delay From: KJ Injection-Date: Fri, 10 Jun 2016 10:58:16 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5258 X-Received-Body-CRC: 1610841760 Xref: news.eternal-september.org comp.lang.vhdl:4411 On Friday, June 10, 2016 at 2:53:55 AM UTC-4, kristoff wrote: > I have two questions from a generic "how to design a syncrounous system"= =20 > one. >=20 > 1/ Is this the right way to do this? >=20 If your target is an ASIC, then the answer might be yes. Otherwise, the an= swer is no. The way to do it is to create clock enable signals and then us= e them to enable the processes like this process(My_high_speed_clock) begin if rising_edge(My_high_speed_clock) if (Clock_Enable_1KHz =3D '1') then ...put your stuff that would be clocked by 1kHz here end if; end if; end process; > Does it make sence to create one clock-divider as a seperate process and= =20 > feed then then into other process? (so not to have to synthesiser to=20 > create one per every process that needs one). >=20 The synthesizer wouldn't do what you describe, it would create only one ins= tance. > Or can I just code the clock-divider into every process that needs that.= =20 > (Perhaps the synthesier will optimise the design anyway and do all the=20 > work for me). >=20 >From a code maintenance standpoint, it would be better to create the divide= r once and use it everywhere. Again, the divider would be generating a clo= ck enable signal to use, not an actual clock signal. >=20 > 2/ From a timing point of view, the div12000-clock output of the clock=20 > divider sits after some logic and is then feed into the other processes. > I guess this will create some delay. >=20 Again, if targeting an ASIC, the answer might be yes. Otherwise, the answe= r is no. You will be creating timing problems that you can't actually fix,= only get lucky at best to get it to sometimes work. > But in the processes that actually use that clock (processes "a" and "b"= =20 > in my example) , the vhdl code to check on that signal sits behind a=20 > "rising_edge(clk_in)", which is -if I am correct- a very short timespan. >=20 > Will this not result in timing-issues? Yes > Can I be sure that the "slowclock =3D 1" will arrive in process "a" and= =20 > "b" fast enough. >=20 > Or will the synthesiser do special things to make sure it will. (perhaps= =20 > delay clk_in in the processes "a" and "b" a little bit). >=20 Synthesis implements what you describe even when you describe something tha= t has an inherent design flaw. >=20 >=20 > Or, in a more generic sence, >=20 > When doing an initial design of a syncrounous system, do you need to=20 > take timing-issues like this in account? >=20 Consider clocking and timing upfront on every design. > Or can I just assume there is zero-delay in all processes and let=20 > timing-issues be dealt with by the synthesizer? >=20 Only if you want to spend time trying to debug why your design works for a = couple of minutes and then stops for some reason. > I did a very interesting post in a forum that clock-signals in a FPGA=20 > are special and that clock-signals pass over special "lanes" (or=20 > whatever the correct term is) so they arrive at all places in the chip=20 > at the same moment. >=20 Not exactly the same time, but they arrive quickly enough that they guarant= ee that no matter which flip flops get connected, the clock will get there = first. >=20 > It would however be interesting to find some information on how to deal= =20 > with clock-signals (especially if you create them yourself in a=20 > clock-divider) in a syncronous design. >=20 Synchronous designs use a single clock, not multiple. If something needs t= o happen periodically at a lower rate, you generate a clock enable signal u= sing a counter. For example, if you have a 50 MHz clock but would like to = generate a 1 MHz 'clock', what you would do is create a counter that counts= from 0 to 49 and then resets back to 0. The clock enable signal would be = active whenever the counter is a particular value (say 0 or 49 for example)= . That generates a one clock cycle wide pulse that then gets used as I out= lined earlier. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:36:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Fri, 10 Jun 2016 08:52:00 -0400 Organization: A noiseless patient Spider Lines: 157 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 10 Jun 2016 12:51:58 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="10294"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zo0HVjH1wZFMIiFHfSVn5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:vGGf31vM5Ej7uzyvi89xIyCSHe0= Xref: news.eternal-september.org comp.lang.vhdl:4412 On 6/10/2016 2:53 AM, kristoff wrote: > Hi, > > > I know this is very much a beginners question but I did try to find the > answer online and at a couple of books but have not yet found an clear > answer. > > > I'll ask the question based on a practicle example: in a process, I need > to to things at two different rates: certain things at the full clock > rate and a slower clock. > > > I have a basic clock 12 Mhz clock, so I build a clock-divider. > > > But, as I know I will need that slower clock in multiple places, my idea > would be to have a seperate process for creating the 1 Khz clock and > feed that into the processes that need that. > > > My code is below. > > > I have two questions from a generic "how to design a syncrounous system" > one. > > 1/ Is this the right way to do this? > > Does it make sence to create one clock-divider as a seperate process and > feed then then into other process? (so not to have to synthesiser to > create one per every process that needs one). > > Or can I just code the clock-divider into every process that needs that. > (Perhaps the synthesier will optimise the design anyway and do all the > work for me). > > > 2/ From a timing point of view, the div12000-clock output of the clock > divider sits after some logic and is then feed into the other processes. > I guess this will create some delay. > > But in the processes that actually use that clock (processes "a" and "b" > in my example) , the vhdl code to check on that signal sits behind a > "rising_edge(clk_in)", which is -if I am correct- a very short timespan. > > Will this not result in timing-issues? > Can I be sure that the "slowclock = 1" will arrive in process "a" and > "b" fast enough. > > Or will the synthesiser do special things to make sure it will. (perhaps > delay clk_in in the processes "a" and "b" a little bit). > > > > Or, in a more generic sence, > > When doing an initial design of a syncrounous system, do you need to > take timing-issues like this in account? > > Or can I just assume there is zero-delay in all processes and let > timing-issues be dealt with by the synthesizer? > > (I did read some comments that it will at least check certain elements > concerning timing of the design). > > > > I did a very interesting post in a forum that clock-signals in a FPGA > are special and that clock-signals pass over special "lanes" (or > whatever the correct term is) so they arrive at all places in the chip > at the same moment. > > > It would however be interesting to find some information on how to deal > with clock-signals (especially if you create them yourself in a > clock-divider) in a syncronous design. > > > > > --- cut here --- cut here --- cut here --- > > clockdiv12000: process (clk_in) is > begin > if (rising_edge(clk_in) then > if (counter = 11999) then > counter <= 0; > slowclock <= '1'; > else > counter <= counter + 1; > slowclock <= '0'; > end if; > end if; -- end rising_edge > end process clockdiv8000; > > > a: process (clk_in, slowclock, in1, in2) is > begin > > if (rising_edge(clk_in) then > > (do some stuff at 8 Mhz clock) > > if (slowclock = '1') then > (do some stuff at 1 Khz clock) > end if; > end if; > > end process a; > > > b: process (clk_in, slowclock, in3, in4) is > begin > > if (rising_edge(clk_in) then > > (do some stuff at 8 Mhz clock) > > if (slowclock = '1') then > (do some stuff at 1 Khz clock) > end if; > end if; > > end process b; What is important in your example is not the details of the code, but more the details of the signal flow. If every process in a given clock domain only depends on the signals in that domain, then you don't have any clock boundary crossing problems. But in your text you ask about this so it is clear that signals cross clock domain boundaries. When that is true you have timing issues that can be very hard to solve. Rather than thinking in terms of the code, think in terms of the hardware. Each gate, FF and even routing path has different delays from others and these delays vary with process, voltage and temperature (PVT). They can vary in different amounts since the die temperature is not uniform. The slow clock is going to follow the fast clock by an unknown (but relatively small) amount of time. This time will be very dependent on PVT. This is very hard to deal with unless you do things like generate the slow clock from the falling edge of the fast clock to allow a half clock cycle offset. While improving the available delay on fast to slow clock domain paths this reduces the available delay time on slow to fast paths. These timing delays are very hard to verify in static timing analysis. However, it can be made to work. Soooo.... What is left? The other alternative is to just use one clock for the entire design and to run the other "clock domains" from that same clock, but using a gated enable at the rate of your slow clock. Kevin has already explained this pretty well. I'm not sure what I could add other than this *greatly* simplifies timing analysis since every timing path is a full clock cycle with nothing special to specify. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:56 2024 X-Received: by 10.66.156.137 with SMTP id we9mr1463351pab.28.1465568459180; Fri, 10 Jun 2016 07:20:59 -0700 (PDT) X-Received: by 10.36.36.133 with SMTP id f127mr64838ita.2.1465568458915; Fri, 10 Jun 2016 07:20:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v48no149253qgd.0!news-out.google.com!z5ni28qge.0!nntp.google.com!v48no149237qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Jun 2016 07:20:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.110.38.73; posting-account=IIjqowoAAACUWgZ0ENVmmZXNqAilg0OM NNTP-Posting-Host: 217.110.38.73 References: <109ab6b9-1e5a-490d-8ff6-8ac59351dafb@googlegroups.com> <951ea014-9598-41ef-9e1b-f663a2323755@googlegroups.com> <59aa6f2b-babc-4f68-a398-ae8a6af73a67@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Book for Vhdl From: andy.mcclelland@tesco.net Injection-Date: Fri, 10 Jun 2016 14:20:58 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4413 On Wednesday, June 8, 2016 at 6:17:28 PM UTC+1, Cecil Bayona wrote: > On 6/8/2016 10:41 AM, lars...@gmail.com wrote: > > > I've also started to read Effective Coding with VHDL > > (https://mitpress.mit.edu/books/effective-coding-vhdl) which has a focus > > on reusing, > > where applicable, SW best practices on VHDL. > > > > So far I've read a few of those chapters and they are good. Nothing new > > really but I haven't seen this kind of information in a book on VHDL before. > > Much of this is missed by many VHDL developers so the book worth reading. > > A little more expensive, $40 for a used copy but looking inside, it > seems to be a decent book. Not available as a Kindle book, if it was I > buy it right now. It is available as an eBook (though not Kindle) for $38. This page has information on the available formats and readers: https://mitpress.mit.edu/our-ebooks -- Andy McC From newsfish@newsfish Thu Aug 1 00:36:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 14:06:53 +0200 Organization: A noiseless patient Spider Lines: 114 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 12:06:54 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="a6764f7e10dfd70a01af8cfa3d17e26b"; logging-data="358"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/VlP0C/cv7e/H4hS/gGtbM" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 In-Reply-To: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Cancel-Lock: sha1:apDwVWU5au57iedjjg4P98Mm2TY= Xref: news.eternal-september.org comp.lang.vhdl:4414 Hi Kevin, I must say that learning FPGAs just for books seams to be not very easy. There seams to be all kind of "need to knows" that are usually not covered in the books, so thank you, but to you and to Rick, for your replies. On 10-06-16 12:58, KJ wrote: > On Friday, June 10, 2016 at 2:53:55 AM UTC-4, kristoff wrote: >> I have two questions from a generic "how to design a syncrounous system" >> one. >> >> 1/ Is this the right way to do this? > If your target is an ASIC, then the answer might be yes. Otherwise, the answer is no. The way to do it is to create clock enable signals and then use them to enable the processes like this > process(My_high_speed_clock) > begin > if rising_edge(My_high_speed_clock) > if (Clock_Enable_1KHz = '1') then > ...put your stuff that would be clocked by 1kHz here > end if; > end if; > end process; OK. In the mean time, I did some more reading on the topic of clocks, gated clocks and Clock-enable signals. Now, looking at your code, I do not see to much different between your code (and what I found in other places on the web) and what I have. Only two things: - My signal is called "slow clock", your is called "Clock_Enable") but as I do not see that in the list VHDL reserved works, I guess that is irrelevant. - In my process, I have both VHDL code running at the full clock speed, and other code in the "clock_enabled" clause. So am I correct to assume that for VHDL to be synthesized to a clock-enabled design, I can only have VHDL code in the "Clock_Enabled_1Khz" part and no other things running at the full clock-speed? >> Or can I just code the clock-divider into every process that needs that. >> (Perhaps the synthesier will optimise the design anyway and do all the >> work for me). > From a code maintenance standpoint, it would be better to create the divider once and use it everywhere. > Again, the divider would be generating a clock enable signal to use, not an actual clock signal. OK. Got that. >> 2/ From a timing point of view, the div12000-clock output of the clock >> divider sits after some logic and is then feed into the other processes. >> I guess this will create some delay. > Again, if targeting an ASIC, the answer might be yes. Otherwise, the answer is no. You will be creating timing problems that you can't actually fix, only get lucky at best to get it to sometimes work. Well, I was kind of sceptical about this myself too, I remember reading about zero-delay in the RTL design stage of the design, so I think that confused me. >> Or, in a more generic sence, >> When doing an initial design of a syncrounous system, do you need to >> take timing-issues like this in account? > Consider clocking and timing upfront on every design. Looks logical. I think I might first need a good book on how to design syncronous systems and switch over to how to implement this is a CPLS or FPGA afterwards. >> I did a very interesting post in a forum that clock-signals in a FPGA >> are special and that clock-signals pass over special "lanes" (or >> whatever the correct term is) so they arrive at all places in the chip >> at the same moment. > Not exactly the same time, but they arrive quickly enough that they guarantee that no matter which flip flops get connected, the clock will get there first. But then do we not have the same issue here with the clock-enabled signals? > Synchronous designs use a single clock, not multiple. If something > needs to happen periodically at a lower rate, you generate a clock > enable signal using a counter. OK. That's also what I had in my mind, so that's good :-) > Kevin Jennings From newsfish@newsfish Thu Aug 1 00:36:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 14:25:17 +0200 Organization: A noiseless patient Spider Lines: 73 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 12:25:17 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="a6764f7e10dfd70a01af8cfa3d17e26b"; logging-data="3539"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX193ovZnT16cxzyZvx2Gmi4o" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 In-Reply-To: Cancel-Lock: sha1:GAyPSef/ZQwfHQcf5saNI3mQwAM= Xref: news.eternal-september.org comp.lang.vhdl:4415 Hi Rick, As noted in my answer to Kevin. Thanks for your reply. On 10-06-16 14:52, rickman wrote: > What is important in your example is not the details of the code, but > more the details of the signal flow. If every process in a given clock > domain only depends on the signals in that domain, then you don't have > any clock boundary crossing problems. But in your text you ask about > this so it is clear that signals cross clock domain boundaries. My question was in the first place intented to get an idea of how to do syncronous design. > When that is true you have timing issues that can be very hard to solve. > Rather than thinking in terms of the code, think in terms of the > hardware. My intention was to think about grouping / reusing code (hardware). > Each gate, FF and even routing path has different delays from > others and these delays vary with process, voltage and temperature > (PVT). They can vary in different amounts since the die temperature is > not uniform. The slow clock is going to follow the fast clock by an > unknown (but relatively small) amount of time. This time will be very > dependent on PVT. OK, let me see if I understand this correctly. - Concider "t=0" when the counter in the clock-divider process reaches the value to trigger the "clock_enable = 1" signale - Concider "t=1" is the next timeslot, when clock_enable is set back to 0. So can I then assume that the processes driven by the clock-enable signal (processes "a" and "b" in my example) are NOT fired at "t=0", but at "t=1"; this due to the fact that the clock_enable signal arrives at "a" and "b" with a certain delay, when the "rising_edge(clk)" has already passed. > ... This is very hard to deal with unless you do things > like generate the slow clock from the falling edge of the fast clock to > allow a half clock cycle offset. This is also something I had I had thought about :-) > What is left? The other alternative is to just use one clock for the > entire design and to run the other "clock domains" from that same clock, > but using a gated enable at the rate of your slow clock. Kevin has > already explained this pretty well. I'm not sure what I could add other > than this *greatly* simplifies timing analysis since every timing path > is a full clock cycle with nothing special to specify. OK. I think I got that. Thanks! Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 10:00:30 -0400 Organization: A noiseless patient Spider Lines: 97 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 14:00:32 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="23294"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+s2Ww7JXR7qmWkPCTey5mZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:t6iFX8HX+HmhprYM0c45HMtg1bE= Xref: news.eternal-september.org comp.lang.vhdl:4416 On 6/11/2016 8:25 AM, kristoff wrote: > Hi Rick, > > > As noted in my answer to Kevin. Thanks for your reply. > > > On 10-06-16 14:52, rickman wrote: > >> What is important in your example is not the details of the code, but >> more the details of the signal flow. If every process in a given clock >> domain only depends on the signals in that domain, then you don't have >> any clock boundary crossing problems. But in your text you ask about >> this so it is clear that signals cross clock domain boundaries. > > My question was in the first place intented to get an idea of how to do > syncronous design. My bad, see below. I think you are doing pretty well. >> When that is true you have timing issues that can be very hard to solve. >> Rather than thinking in terms of the code, think in terms of the >> hardware. > > My intention was to think about grouping / reusing code (hardware). > > >> Each gate, FF and even routing path has different delays from >> others and these delays vary with process, voltage and temperature >> (PVT). They can vary in different amounts since the die temperature is >> not uniform. The slow clock is going to follow the fast clock by an >> unknown (but relatively small) amount of time. This time will be very >> dependent on PVT. > > > > OK, let me see if I understand this correctly. > > - Concider "t=0" when the counter in the clock-divider process reaches > the value to trigger the "clock_enable = 1" signale > - Concider "t=1" is the next timeslot, when clock_enable is set back to 0. > > > > So can I then assume that the processes driven by the clock-enable > signal (processes "a" and "b" in my example) are NOT fired at "t=0", but > at "t=1"; this due to the fact that the clock_enable signal arrives at > "a" and "b" with a certain delay, when the "rising_edge(clk)" has > already passed. > > > > >> ... This is very hard to deal with unless you do things >> like generate the slow clock from the falling edge of the fast clock to >> allow a half clock cycle offset. > > This is also something I had I had thought about :-) > > > >> What is left? The other alternative is to just use one clock for the >> entire design and to run the other "clock domains" from that same clock, >> but using a gated enable at the rate of your slow clock. Kevin has >> already explained this pretty well. I'm not sure what I could add other >> than this *greatly* simplifies timing analysis since every timing path >> is a full clock cycle with nothing special to specify. > OK. I think I got that. > > Thanks! Sorry, Kristoff, I didn't see your code correctly (or maybe just didn't pay attention). Your code *is* using clock enables. So the entire chip is running from one clock, clk_in. When I use clock enables I name all signals as xyz_en or something similar rather than calling them "xyz_clock". In this new context the delays are all going to be relative to clk_in and can be fully analyzed by static timing analysis. Looking at your code more carefully, I see you are including slowclock, in1, in2, in3, in4 in your sensitivity lists. None of these signals should be firing the process since nothing will happen unless it is also the rising edge of clk_in (which it won't). Once you remove these signals from your sensitivity lists look at how the code functions again and see if you still have questions. This should make it clear that the slowclock signal is just another data signal and not a clock in the real sense of the word. So you analyze its timing the same as the other non-clock signals. Do you know how to set constraints for static timing analysis? -- Rick C From newsfish@newsfish Thu Aug 1 00:36:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Cecil Bayona Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 10:25:37 -0500 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 15:25:40 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4c6149fda0f382b24075b7a1eefa3518"; logging-data="10160"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+D3ugE/PjFjT3d31pPS5jS" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:SrEiFNPH66j96wdwsmq4ZtQ/8KY= Xref: news.eternal-september.org comp.lang.vhdl:4417 On 6/11/2016 7:06 AM, kristoff wrote: > Hi Kevin, > > > I must say that learning FPGAs just for books seams to be not very easy. > There seams to be all kind of "need to knows" that are usually not > covered in the books, so thank you, but to you and to Rick, for your > replies. > > As a newbie I also agree, most books, and I have several books, they are either are too vague design books, or most jump right into the code but leave out a lot of information, they give a lot of details but leave out the overall picture. I assume one will just have to work with full working examples and read through and them do small hardware projects using the knowledge and code from prior working projects, and see how things turn out. At some point I expect that things will start making sense and one can start making small hardware projects without copy and paste, but that point is nowhere here for now. -- Cecil - k5nwa From newsfish@newsfish Thu Aug 1 00:36:57 2024 X-Received: by 10.107.181.193 with SMTP id e184mr5961647iof.17.1465661634116; Sat, 11 Jun 2016 09:13:54 -0700 (PDT) X-Received: by 10.36.23.206 with SMTP id 197mr128324ith.2.1465661634060; Sat, 11 Jun 2016 09:13:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p34no5509061qgp.1!news-out.google.com!107ni256qgx.1!nntp.google.com!p34no5509059qgp.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Jun 2016 09:13:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:109b:cfea:96db:fbc0; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:109b:cfea:96db:fbc0 References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> Subject: Re: "rising_edge(clk)" and delay From: KJ Injection-Date: Sat, 11 Jun 2016 16:13:54 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4301 X-Received-Body-CRC: 1422487463 Xref: news.eternal-september.org comp.lang.vhdl:4418 On Saturday, June 11, 2016 at 8:06:56 AM UTC-4, kristoff wrote: > > process(My_high_speed_clock) > > begin > > if rising_edge(My_high_speed_clock) > > if (Clock_Enable_1KHz =3D '1') then > > ...put your stuff that would be clocked by 1kHz here > > end if; > > end if; > > end process; >=20 > - In my process, I have both VHDL code running at the full clock speed,= =20 > and other code in the "clock_enabled" clause. >=20 > So am I correct to assume that for VHDL to be synthesized to a=20 > clock-enabled design, I can only have VHDL code in the=20 > "Clock_Enabled_1Khz" part and no other things running at the full=20 > clock-speed? Not quite sure what you mean. You certainly can have signals being assigne= d outside of the "if (Clock_Enable_1KHz =3D '1') then" block, if you want b= ut if you're trying to create signals that can only change when a hypotheti= cal 1kHz clock signal comes along, then yes, everything goes inside the "if= (Clock_Enable_1KHz =3D '1') then". Fundamentally, you're describing logic that gets clocked by the clock signa= l that is listed in "if rising_edge(...) then", but making it operate in su= ch a way that it appears to only be clocked by a 1 KHz clock instead. The = actual design is not being clocked with the 1KHz clock, but it is operating= as if it was...that's not the same thing, but it is usually all that is ac= tually required. >=20 > >> I did a very interesting post in a forum that clock-signals in a FPGA > >> are special and that clock-signals pass over special "lanes" (or > >> whatever the correct term is) so they arrive at all places in the chip > >> at the same moment. >=20 > > Not exactly the same time, but they arrive quickly enough that they gua= rantee that no matter which flip flops get connected, the clock will get th= ere first. >=20 > But then do we not have the same issue here with the clock-enabled signal= s? No, and here is the difference: - The clock enable is just another signal input into the cloud of logic tha= t gets fed into the D input of a flip flop that gets clocked by a high spee= d clock. That high speed clock, can be guaranteed by the FPGA/CPLD manufac= turer to arrive at the clock input of every flip flop on the die without vi= olating setup or hold time violations due to skew on that clock signal itse= lf. In order to get this guarantee you simply need to follow the FPGA/CPLD= rules and use one of the specified clock input pins of the device or use o= ne of the internal PLLs. - When you use an internally generated signal to clock a flip flop (such as= generating a 1KHz signal and using the rising edge of that signal) now the= re are no guarantees that the 1KHz clock will actually arrive when it shoul= d. The data input to the flip flop might actually beat the clock. In that= situation, there is nothing you can do to fix the design in a way that you= can guarantee will work under all temperature and supply voltage condition= s. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:36:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 19:17:46 +0200 Organization: A noiseless patient Spider Lines: 98 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 17:17:46 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="a6764f7e10dfd70a01af8cfa3d17e26b"; logging-data="2829"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Q0wb0hgEk0jzYfiSDmGcJ" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 In-Reply-To: <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> Cancel-Lock: sha1:R1fm0Wn7W9f97DFUKEPkUg8HkDU= Xref: news.eternal-september.org comp.lang.vhdl:4419 Kevin, On 11-06-16 18:13, KJ wrote: >>> process(My_high_speed_clock) >>> begin >>> if rising_edge(My_high_speed_clock) >>> if (Clock_Enable_1KHz = '1') then >>> ...put your stuff that would be clocked by 1kHz here >>> end if; >>> end if; >>> end process; >> >> - In my process, I have both VHDL code running at the full clock speed, >> and other code in the "clock_enabled" clause. >> >> So am I correct to assume that for VHDL to be synthesized to a >> clock-enabled design, I can only have VHDL code in the >> "Clock_Enabled_1Khz" part and no other things running at the full >> clock-speed? > Not quite sure what you mean. You certainly can have signals being assigned > outside of the "if (Clock_Enable_1KHz = '1') then" block, if you want > but if you're trying to create signals that can only change when a > hypothetical 1kHz clock signal comes along, then yes, everything > goes inside the "if (Clock_Enable_1KHz = '1') then". OK. That's clear. > Fundamentally, you're describing logic that gets clocked by the clock > signal that is listed in "if rising_edge(...) then", but making it > operate in such a way that it appears to only be clocked by a 1 > KHz clock instead. The actual design is not being clocked with > the 1KHz clock, but it is operating as if it was...that's not the > same thing, but it is usually all that is actually required. OK then. I still have some issues trying to understand how it really all fits together. From how I understand it, -and feel free to correct me if I am wrong- how the VHDL synthesizer translates into an actual hardware design is by looking into the VHDL code and searching for certain "patterns" (called "templates" ???) in the code that it known about and recognises. So, if it sees "if rising_edge(My_high_speed_clock)" followed by a "if (Clock_Enable_1KHz = '1')", it recognises this as a clock-enabled circui and translates this into (say) a "D flip-flop with enable" hardware component. So I had the (apparently wrong) idea that -for some reason- the synthesier template required that the VHDL process cannot not have other stuff outside the "if (Clock_Enable = '1')" clause. Anycase, it's cleared up now. Thanks! >>>> I did a very interesting post in a forum that clock-signals in a FPGA >>>> are special and that clock-signals pass over special "lanes" (or >>>> whatever the correct term is) so they arrive at all places in the chip >>>> at the same moment. >>> Not exactly the same time, but they arrive quickly enough that they guarantee that no matter which flip flops get connected, the clock will get there first. >> But then do we not have the same issue here with the clock-enabled signals? > No, and here is the difference: > - The clock enable is just another signal input into the cloud of logic that gets fed into the D input of a flip flop that gets clocked by a high speed clock. That high speed clock, can be guaranteed by the FPGA/CPLD manufacturer to arrive at the clock input of every flip flop on the die without violating setup or hold time violations due to skew on that clock signal itself. In order to get this guarantee you simply need to follow the FPGA/CPLD rules and use one of the specified clock input pins of the device or use one of the internal PLLs. > - When you use an internally generated signal to clock a flip flop (such as generating a 1KHz signal and using the rising edge of that signal) now there are no guarantees that the 1KHz clock will actually arrive when it should. The data input to the flip flop might actually beat the clock. In that situation, there is nothing you can do to fix the design in a way that you can guarantee will work under all temperature and supply voltage conditions. Rick's message got me thinking. I guess the best way to do this is- - in the clock-divider process, set the clock_enable signal not on the rising edge, but on the *falling* edge of the clock - in the processes that use that clock_enable, use the *rising* edge. That way, even if there is a delay in the propagation of the clock_enable signal from the clock-divider to the other processes (as it is not a "clock" signal), as long as it less then half of a clock-cycle; this should work. Correct ? > Kevin Jennings Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:58 2024 X-Received: by 10.140.178.6 with SMTP id y6mr5930457qhy.14.1465667275856; Sat, 11 Jun 2016 10:47:55 -0700 (PDT) X-Received: by 10.36.87.195 with SMTP id u186mr133088ita.3.1465667275813; Sat, 11 Jun 2016 10:47:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!p34no5553440qgp.1!news-out.google.com!107ni262qgx.1!nntp.google.com!v48no623411qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Jun 2016 10:47:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2754e8d2-41f7-487a-a2a7-8c05ab19e0c8@googlegroups.com> Subject: Re: "rising_edge(clk)" and delay From: Lars Asplund Injection-Date: Sat, 11 Jun 2016 17:47:55 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 29 Xref: news.eternal-september.org comp.lang.vhdl:4420 > > So am I correct to assume that for VHDL to be synthesized to a=20 > > clock-enabled design, I can only have VHDL code in the=20 > > "Clock_Enabled_1Khz" part and no other things running at the full=20 > > clock-speed? You can mix to two in the same process. Extending the previous template it = can look like this process(My_high_speed_clock) begin if rising_edge(My_high_speed_clock) ...put your stuff that would be clocked by 12 MHz here if (Clock_Enable_1KHz =3D '1') then ...put your stuff that would be clocked by 1kHz here end if; end if; end process; Whether or not you mix them or put them in separate processes is more a mat= ter of grouping things that belongs together such that the code becomes mod= ular (better code readability/maintenance and less error-prone). There are = different ways that things can belong together and grouping things by funct= ionality is the best thing you can do. This is also known as functional coh= esion. Grouping thing because they run at 1 KHz but has nothing else in com= mon is known as logical cohesion and is among the worst things you can do. = With good/bad I'm referring to the benefits of modularity. It might be that= a poor type of cohesion results in other benefits such as better resource = utilization. /Lars From newsfish@newsfish Thu Aug 1 00:36:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: learning sequencial logic (was: "rising_edge(clk)" and delay) Date: Sat, 11 Jun 2016 20:35:05 +0200 Organization: A noiseless patient Spider Lines: 90 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 18:35:05 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3b69aff36207c0e356162b06477ed76e"; logging-data="19211"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+dqz9SMtPavcS+m1E/2RpR" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 In-Reply-To: Cancel-Lock: sha1:Q/vh8jylPESxU44GC1jSJd+fHOE= Xref: news.eternal-september.org comp.lang.vhdl:4421 Hi Cecil, On 11-06-16 17:25, Cecil Bayona wrote: >> I must say that learning FPGAs just for books seams to be not very easy. >> There seams to be all kind of "need to knows" that are usually not >> covered in the books, so thank you, but to you and to Rick, for your >> replies. > As a newbie I also agree, most books, and I have several books, they are > either are too vague design books, or most jump right into the code but > leave out a lot of information, they give a lot of details but leave out > the overall picture. For me, the problem is that I really never learned much about digital logic, I studied electronics some 25 years ago when we already had microcontrollers (my thesis was with a 8051). We did learn about basic digital logic (and, or, not, ...), we never really learned how to solve a problem with it. If you had an issue that involved some kind of "logic" more complex then a couple of 74xx ICs and combinational logic, you simply used a microcontroller and solved it that way. We never really learned about thinks like sequential logic, timing, clocks, etc, ... or how to solve a technical issue with digital logic components; and ... this is what I need now. Certain concepts used in "programming" (e.g. the idea of a statemachine) are also usefull in sequencial logic, but that's about it. The rest is -for me- all quite new. > I assume one will just have to work with full working examples and read > through and them do small hardware projects using the knowledge and > code from prior working projects, and see how things turn out. > At some point I expect that things will start making sense and one can > start making small hardware projects without copy and paste, but that > point is nowhere here for now. I started looking around for websites that offer simple exercises to learn this. Perhaps we can share some ideas on exercises we come up ourselfs. At this time, I have two things I want to rey out: - first, an I/O extender with SPI. The SPI-protocol is not that complex and looks to me like a nice example of "clocked" sequencial logic. I think it might be doable, to create a VHDL design/circuit that allow you to set or clear output pins on a FPGA/CPLD, based on commands issued via SPI (from a microcontroller). - a lot more difficult (perhaps as a "final exercise") is this: https://www.youtube.com/watch?v=35zLnS3fXeA This is a very simple broadboard based 8-bit processor (which seams to be the "SAP" architecture used in quite a number of text-book on microprocessor architecture) completely implemented in 74xx ICs. I currently how no idea how easy or difficult this will be, but perhaps duplicating this in VHDL would be the ultimate "final test" exercise :-) Do you -or somebody else- have ideas for exercises that might be interesting to learn how to solve actual real problems with logic? By the way, I notice you ham callsign in your messages. It's nice to see a fellow ham interested in FPGAs and VHDL. :-) Kristoff (ON1ARF) From newsfish@newsfish Thu Aug 1 00:36:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 14:37:04 -0400 Organization: A noiseless patient Spider Lines: 141 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 18:37:05 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="20174"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18W1gR71kYdvE3ibODLVrkZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:b1NuqombUCVkn4Bq2SXUnOIW/tE= Xref: news.eternal-september.org comp.lang.vhdl:4422 On 6/11/2016 1:17 PM, kristoff wrote: > Kevin, > > > > On 11-06-16 18:13, KJ wrote: > >>>> process(My_high_speed_clock) >>>> begin >>>> if rising_edge(My_high_speed_clock) >>>> if (Clock_Enable_1KHz = '1') then >>>> ...put your stuff that would be clocked by 1kHz here >>>> end if; >>>> end if; >>>> end process; >>> >>> - In my process, I have both VHDL code running at the full clock speed, >>> and other code in the "clock_enabled" clause. >>> >>> So am I correct to assume that for VHDL to be synthesized to a >>> clock-enabled design, I can only have VHDL code in the >>> "Clock_Enabled_1Khz" part and no other things running at the full >>> clock-speed? > >> Not quite sure what you mean. You certainly can have signals being >> assigned >> outside of the "if (Clock_Enable_1KHz = '1') then" block, if you want >> but if you're trying to create signals that can only change when a >> hypothetical 1kHz clock signal comes along, then yes, everything >> goes inside the "if (Clock_Enable_1KHz = '1') then". > > OK. That's clear. > > >> Fundamentally, you're describing logic that gets clocked by the clock >> signal that is listed in "if rising_edge(...) then", but making it >> operate in such a way that it appears to only be clocked by a 1 >> KHz clock instead. The actual design is not being clocked with >> the 1KHz clock, but it is operating as if it was...that's not the >> same thing, but it is usually all that is actually required. > > OK then. > > > I still have some issues trying to understand how it really all fits > together. > > From how I understand it, -and feel free to correct me if I am wrong- > how the VHDL synthesizer translates into an actual hardware design is by > looking into the VHDL code and searching for certain "patterns" (called > "templates" ???) in the code that it known about and recognises. > > So, if it sees "if rising_edge(My_high_speed_clock)" followed by a "if > (Clock_Enable_1KHz = '1')", it recognises this as a clock-enabled circui > and translates this into (say) a "D flip-flop with enable" hardware > component. I don't know exactly how the VHDL tools parse and interpret the code to produce logic. What I do know is that templates are not always used since there are many ways to skin a given cat. For example you can write: q <= d when rising_edge(clk); to infer a register. I don't think this is "template matching" in the sense of pattern matching. BTW, the above will work, but is not recommended for mostly clarity reasons. Not many are familiar with it and will be scratching their heads when they see it, at least for a bit. > So I had the (apparently wrong) idea that -for some reason- the > synthesier template required that the VHDL process cannot not have other > stuff outside the "if (Clock_Enable = '1')" clause. > > Anycase, it's cleared up now. Thanks! > > > > >>>>> I did a very interesting post in a forum that clock-signals in a FPGA >>>>> are special and that clock-signals pass over special "lanes" (or >>>>> whatever the correct term is) so they arrive at all places in the chip >>>>> at the same moment. >>>> Not exactly the same time, but they arrive quickly enough that they >>>> guarantee that no matter which flip flops get connected, the clock >>>> will get there first. > >>> But then do we not have the same issue here with the clock-enabled >>> signals? >> No, and here is the difference: >> - The clock enable is just another signal input into the cloud of >> logic that gets fed into the D input of a flip flop that gets clocked >> by a high speed clock. That high speed clock, can be guaranteed by >> the FPGA/CPLD manufacturer to arrive at the clock input of every flip >> flop on the die without violating setup or hold time violations due to >> skew on that clock signal itself. In order to get this guarantee you >> simply need to follow the FPGA/CPLD rules and use one of the specified >> clock input pins of the device or use one of the internal PLLs. >> - When you use an internally generated signal to clock a flip flop >> (such as generating a 1KHz signal and using the rising edge of that >> signal) now there are no guarantees that the 1KHz clock will actually >> arrive when it should. The data input to the flip flop might actually >> beat the clock. In that situation, there is nothing you can do to fix >> the design in a way that you can guarantee will work under all >> temperature and supply voltage conditions. > > Rick's message got me thinking. > > I guess the best way to do this is- > > - in the clock-divider process, set the clock_enable signal not on the > rising edge, but on the *falling* edge of the clock > > - in the processes that use that clock_enable, use the *rising* edge. > > That way, even if there is a delay in the propagation of the > clock_enable signal from the clock-divider to the other processes (as it > is not a "clock" signal), as long as it less then half of a clock-cycle; > this should work. > > > Correct ? When I was talking about using the negative edge of the clock I was thinking you were using the slow clock as an actual clock to the FFs where you want to avoid race condition problems. When using a clock enable both the design of the chip (clock skew vs. setup and hold times) and the tools assure the timing will work provided the max path delay is less than the clock cycle time minus the setup and hold time of the FFs. Do you understand that using the negative edge of the clock to generate the enable will reduce your slack time in the enable path? Even for the slow clock enable, it only has one clock cycle to be distributed and needs all the time you can give it. Generating it from the same clock edge as you are using elsewhere gives you the longest possible path delay time without having to worry about hold time. I'm sorry if I confused you. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 21:05:38 +0200 Organization: A noiseless patient Spider Lines: 77 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 19:05:38 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3b69aff36207c0e356162b06477ed76e"; logging-data="26676"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+XsAkwx+dRXGuE6z4xVxI2" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 In-Reply-To: Cancel-Lock: sha1:n5eEevbfPuPvhG82Iy2YRJTE6eQ= Xref: news.eternal-september.org comp.lang.vhdl:4423 Hi Rick, On 11-06-16 16:00, rickman wrote: >> My question was in the first place intented to get an idea of how to do >> syncronous design. > My bad, see below. I think you are doing pretty well. No problem. :-) Last week, I talked to somebody who works in a company that does ASIC design and he said that -althou VHDL is a high-level language- you need to keep in mind that this all gets turned into hardware. "always try to understand how the hardware that actually does the job actually works". So, as already mentioned, I really appriciate what you do and the time you take to explain the background of all this! > Sorry, Kristoff, I didn't see your code correctly (or maybe just didn't > pay attention). Your code *is* using clock enables. So the entire chip > is running from one clock, clk_in. > When I use clock enables I name all signals as xyz_en or something > similar rather than calling them "xyz_clock". OK. Granted. I must still learn the naming-conventions of FPGA :-) > In this new context the delays are all going to be relative to clk_in > and can be fully analyzed by static timing analysis. Sofar I have concentrated on understand VHDL and the underlaying concepts. I always try to do basic research myself and try to solve it myself before taking up other peoples time. I have not really focused on the simulation part. I will try it out and if it does not work, I will come back to the forum. > Looking at your code more carefully, I see you are including slowclock, > in1, in2, in3, in4 in your sensitivity lists. None of these signals > should be firing the process since nothing will happen unless it is also > the rising edge of clk_in (which it won't). Once you remove these > signals from your sensitivity lists look at how the code functions again > and see if you still have questions. Yes. You are correct. Thanks for noting that. > ... This should make it clear that the > slowclock signal is just another data signal and not a clock in the real > sense of the word. So you analyze its timing the same as the other > non-clock signals. OK. thx! I understand and use the "clock_enable" naming-convension in the future. :-) Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:36:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: learning sequencial logic Date: Sat, 11 Jun 2016 15:24:40 -0400 Organization: A noiseless patient Spider Lines: 168 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 19:24:41 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="31589"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+iIl8Z5jLBu6iDgltr9P3m" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:r7/SmOi+fWHILjf+7CLYw0oAvMk= Xref: news.eternal-september.org comp.lang.vhdl:4424 On 6/11/2016 2:35 PM, kristoff wrote: > Hi Cecil, > > > On 11-06-16 17:25, Cecil Bayona wrote: > >>> I must say that learning FPGAs just for books seams to be not very easy. >>> There seams to be all kind of "need to knows" that are usually not >>> covered in the books, so thank you, but to you and to Rick, for your >>> replies. > >> As a newbie I also agree, most books, and I have several books, they are >> either are too vague design books, or most jump right into the code but >> leave out a lot of information, they give a lot of details but leave out >> the overall picture. > > > For me, the problem is that I really never learned much about digital > logic, I studied electronics some 25 years ago when we already had > microcontrollers (my thesis was with a 8051). > > We did learn about basic digital logic (and, or, not, ...), we never > really learned how to solve a problem with it. > > If you had an issue that involved some kind of "logic" more complex then > a couple of 74xx ICs and combinational logic, you simply used a > microcontroller and solved it that way. > > We never really learned about thinks like sequential logic, timing, > clocks, etc, ... or how to solve a technical issue with digital logic > components; and ... this is what I need now. > > Certain concepts used in "programming" (e.g. the idea of a statemachine) > are also usefull in sequencial logic, but that's about it. The rest is > -for me- all quite new. There is one important concept that you will need when you are simulating VHDL circuits, that is the delta delay. The delta delay is used to deal with the problem of simulating concurrent logic. When a signal changes, any process (which includes each concurrent logic statement as they are also processes) that depends on that signal runs simultaneously. However, in a simulator "simultaneously" is emulated by evaluating each process one at a time. If the outputs from one process are used by another the results will depend on which process is run first! proc_A: process (clk) begin if rising_edge(clk) then A <= B + C; end if; end process proc_A; proc_D: process (clk) begin if rising_edge(clk) then D <= A + C; end if; end process proc_D; When clk changes both assignments are evaluated. If proc_A runs first, it becomes A' <= B + C', where the ' indicates the new version of each signal. proc_D will be evaluated next as D' <= A' + C' or <= B + C' + C'; So far, so good. But what if proc_D runs first? It will assign D' <= A + C' or <= B + C + C'; clearly a different result. The way to get around this is to use delta delays for all signal assignments. A delta delay can be thought of as smaller than the time resolution of the simulation. So it won't show up as a time delay anywhere, but it affects the ordering of all processes in the system. In the above example when clk rises at time t=0 it triggers both processes to run. However, the assignments will be queued for time t=0+d where d represents a delta delay. So once all the processes have run at time t=0, the signals will be updated to their new values at t=0+d which will give the result shown in the second case above. BTW, Verilog doesn't use delta delays, so I don't know how they get consistent and accurate results from their simulations. I don't know if you have any confusion about this, but I am laid up after a hip surgery and have nothing better to do... lol >> I assume one will just have to work with full working examples and read >> through and them do small hardware projects using the knowledge and >> code from prior working projects, and see how things turn out. >> At some point I expect that things will start making sense and one can >> start making small hardware projects without copy and paste, but that >> point is nowhere here for now. > > I started looking around for websites that offer simple exercises to > learn this. > > Perhaps we can share some ideas on exercises we come up ourselfs. > > > At this time, I have two things I want to rey out: > - first, an I/O extender with SPI. > > The SPI-protocol is not that complex and looks to me like a nice example > of "clocked" sequencial logic. SPI is very simple indeed, but in general well thought out. The labels clearly indicate the direction of signal flow and the clocking avoids race conditions if used properly. The down side is that it is a bit more flexible than needed so it can be a bit tricky to set up. > I think it might be doable, to create a VHDL design/circuit that allow > you to set or clear output pins on a FPGA/CPLD, based on commands > issued via SPI (from a microcontroller). When you say "commands", usually the I/O bits are set/cleared directly from the data shifted through the SPI port. There is normally the shift register that receives the serial data (and provides for shifting data out) which is transferred to the output register when the select line is deasserted. > - a lot more difficult (perhaps as a "final exercise") is this: > https://www.youtube.com/watch?v=35zLnS3fXeA > > This is a very simple broadboard based 8-bit processor (which seams to > be the "SAP" architecture used in quite a number of text-book on > microprocessor architecture) completely implemented in 74xx ICs. That might be an ok project, but when it is done, what do you have? Just an exercise. You might want to design some pieces that will be useful to you in the future. > I currently how no idea how easy or difficult this will be, but perhaps > duplicating this in VHDL would be the ultimate "final test" exercise :-) > > > > > Do you -or somebody else- have ideas for exercises that might be > interesting to learn how to solve actual real problems with logic? A reasonably simple example would be a basic, fixed size UART, say 8 bits, no parity, one stop bit. Design the transmitter and receiver separately and test by connecting them together and shipping characters across. Equally important is the test bench used to test your design. You need to learn how to construct simple and yet powerful test benches to stimulate your designs and verify the output. It is not uncommon for the test bench to be as complex as the design you are testing, but hopefully can be done more simply. In this case you can use the UART transmitter to test the UART receiver and vice versa. The test bench only needs to stimulate the parallel input/output and the control strobes. It also does not need to be synthesizable and so can be written more like a standard sequential program. Once you have that working correctly, you can add programmable controls for the word size, parity and stop bits. That gets a bit more complex and your test bench will be more complex as well. Both of these exercises will result in useful code. Often you can use a simple, fixed size UART in your designs. Other times you will need a programmable UART so it can be configured by software or changed for different modes of operation. Just a thought. -- Rick C From newsfish@newsfish Thu Aug 1 00:36:59 2024 X-Received: by 10.129.98.133 with SMTP id w127mr4614790ywb.0.1465676016418; Sat, 11 Jun 2016 13:13:36 -0700 (PDT) X-Received: by 10.36.79.141 with SMTP id c135mr140155itb.10.1465676016352; Sat, 11 Jun 2016 13:13:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!v48no695135qgd.0!news-out.google.com!v8ni146qgv.0!nntp.google.com!v48no695132qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Jun 2016 13:13:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:109b:cfea:96db:fbc0; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:109b:cfea:96db:fbc0 References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: learning sequencial logic From: KJ Injection-Date: Sat, 11 Jun 2016 20:13:36 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 86 X-Received-Bytes: 4866 X-Received-Body-CRC: 1669745811 Xref: news.eternal-september.org comp.lang.vhdl:4425 On Saturday, June 11, 2016 at 3:24:43 PM UTC-4, rickman wrote: >=20 > There is one important concept that you will need when you are=20 > simulating VHDL circuits, that is the delta delay. The delta delay is=20 > used to deal with the problem of simulating concurrent logic. >=20 > When a signal changes, any process (which includes each concurrent logic= =20 > statement as they are also processes) that depends on that signal runs=20 > simultaneously. However, in a simulator "simultaneously" is emulated by= =20 > evaluating each process one at a time. If the outputs from one process= =20 > are used by another the results will depend on which process is run first= ! >=20 The part about "the results will depend on which process is run first!" is = not correct. At least not with VHDL. > proc_A: process (clk) begin > if rising_edge(clk) then > A <=3D B + C; > end if; > end process proc_A; >=20 > proc_D: process (clk) begin > if rising_edge(clk) then > D <=3D A + C; > end if; > end process proc_D; >=20 > When clk changes both assignments are evaluated. If proc_A runs first,= =20 > it becomes A' <=3D B + C', where the ' indicates the new version of each= =20 > signal. proc_D will be evaluated next as D' <=3D A' + C' or <=3D B + C' = +=20 > C'; So far, so good. >=20 > But what if proc_D runs first? It will assign D' <=3D A + C' or <=3D B += C=20 > + C'; clearly a different result. >=20 This is wrong. Both processes are sensitive only to changes in the signal = clk. Because of the 'if rising_edge(clk)', the statements that assign to '= A' and 'D' will only get executed on the rising edge of clk. Neither signa= l will get updated until all processes that were run on that particular cyc= le have been executed and suspend. Using any compliant VHDL simulator, there will be no differences in the val= ues of 'A' and 'D' based upon which process gets executed first.=20 > The way to get around this is to use delta delays for all signal=20 > assignments. A delta delay can be thought of as smaller than the time=20 > resolution of the simulation. So it won't show up as a time delay=20 > anywhere, but it affects the ordering of all processes in the system. >=20 This is what the simulator does, not the user. Is that what you're trying = to describe?? > In the above example when clk rises at time t=3D0 it triggers both=20 > processes to run. However, the assignments will be queued for time=20 > t=3D0+d where d represents a delta delay. So once all the processes have= =20 > run at time t=3D0, the signals will be updated to their new values at=20 > t=3D0+d which will give the result shown in the second case above. >=20 This is correct...but directly contradicts what you had said earlier about = the values depending on the order of execution of the processes which is no= t correct for VHDL. I'm guessing that you were talking about some hypothet= ical language model that looks like VHDL (since that's what your two exampl= e processes look like), but in fact really is not (since it updates the sig= nals at the end of each process, which is not what the VHDL LRM specifies). >=20 > I don't know if you have any confusion about this, but I am laid up=20 > after a hip surgery and have nothing better to do... lol >=20 Maybe you took too many pills before you posted (kidding, hope you get well= soon). Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:00 2024 X-Received: by 10.200.51.98 with SMTP id u31mr6315902qta.29.1465677052210; Sat, 11 Jun 2016 13:30:52 -0700 (PDT) X-Received: by 10.36.20.206 with SMTP id 197mr140844itg.3.1465677052161; Sat, 11 Jun 2016 13:30:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!au2pb.net!feeder.erje.net!2.us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!p34no5632739qgp.1!news-out.google.com!107ni281qgx.1!nntp.google.com!p34no5632728qgp.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Jun 2016 13:30:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:8949:593b:7bb8:56d1; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:8949:593b:7bb8:56d1 References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3df7c334-9134-4f87-a1a1-0e41081d858c@googlegroups.com> Subject: Re: "rising_edge(clk)" and delay From: KJ Injection-Date: Sat, 11 Jun 2016 20:30:52 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 63 Xref: news.eternal-september.org comp.lang.vhdl:4426 On Saturday, June 11, 2016 at 1:17:48 PM UTC-4, kristoff wrote: >=20 > I still have some issues trying to understand how it really all fits=20 > together. >=20 > From how I understand it, -and feel free to correct me if I am wrong-=20 > how the VHDL synthesizer translates into an actual hardware design is by= =20 > looking into the VHDL code and searching for certain "patterns" (called= =20 > "templates" ???) in the code that it known about and recognises. >=20 > So, if it sees "if rising_edge(My_high_speed_clock)" followed by a "if=20 > (Clock_Enable_1KHz =3D '1')", it recognises this as a clock-enabled circu= i=20 > and translates this into (say) a "D flip-flop with enable" hardware=20 > component. >=20 Almost. Synthesis tools do look for something to match a template. When i= t sees a process with "if rising_edge(...) then" it knows that a flip flop = is needed. It doesn't really care about the part that makes it look like a= clock enabled flip flop. The clock enable portion can also be implemented= as part of the logic that leads into the 'D' input of the flip flop. Ther= e are also templates that infer memory blocks and other things as well. Yo= u're probably close enough though with your understanding. >=20 > Rick's message got me thinking. >=20 > I guess the best way to do this is- >=20 > - in the clock-divider process, set the clock_enable signal not on the= =20 > rising edge, but on the *falling* edge of the clock >=20 > - in the processes that use that clock_enable, use the *rising* edge. >=20 > That way, even if there is a delay in the propagation of the=20 > clock_enable signal from the clock-divider to the other processes (as it= =20 > is not a "clock" signal), as long as it less then half of a clock-cycle;= =20 > this should work. >=20 This is not a good approach since now the clock enable signal will have les= s than 1/2 of a clock cycle to get to where it needs to go rather than havi= ng a full clock cycle. There is nothing at all special about the clock ena= ble signal as compared to any other signal that flows into the logic. When= you use global clocks you are guaranteed that every flip flop output (cloc= k enable being an example) will not arrive at any destination flip flop inp= ut (i.e. where clock enable is being used) before the rising edge of the cl= ock. That means that you are guaranteed one full clock cycle to get from f= lip flop output to the next flip flop input with whatever logic you describ= e. Whether you describe logic for a clock enabled flip flop or not, it doe= sn't matter. Short answer is that if you ever feel the need to use both edges of the clo= ck...most likely you're not going about your design in the correct manner. = Synchronous logic design not only uses only one clock, but only one edge o= f that one clock. Having said that, there are cases when both edges are us= ed and that is the correct thing to do...but what you've described so far i= s not an example. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: learning sequencial logic Date: Sat, 11 Jun 2016 16:32:56 -0400 Organization: A noiseless patient Spider Lines: 73 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 20:32:56 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="13408"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/QaatXCAU6eIIA4gBhsrro" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:E6I3YwYdiI+TxmETWwjZJ6uxJjI= Xref: news.eternal-september.org comp.lang.vhdl:4427 On 6/11/2016 4:13 PM, KJ wrote: > On Saturday, June 11, 2016 at 3:24:43 PM UTC-4, rickman wrote: >> >> There is one important concept that you will need when you are >> simulating VHDL circuits, that is the delta delay. The delta delay is >> used to deal with the problem of simulating concurrent logic. >> >> When a signal changes, any process (which includes each concurrent logic >> statement as they are also processes) that depends on that signal runs >> simultaneously. However, in a simulator "simultaneously" is emulated by >> evaluating each process one at a time. If the outputs from one process >> are used by another the results will depend on which process is run first! >> > > The part about "the results will depend on which process is run first!" is not correct. At least not with VHDL. > >> proc_A: process (clk) begin >> if rising_edge(clk) then >> A <= B + C; >> end if; >> end process proc_A; >> >> proc_D: process (clk) begin >> if rising_edge(clk) then >> D <= A + C; >> end if; >> end process proc_D; >> >> When clk changes both assignments are evaluated. If proc_A runs first, >> it becomes A' <= B + C', where the ' indicates the new version of each >> signal. proc_D will be evaluated next as D' <= A' + C' or <= B + C' + >> C'; So far, so good. >> >> But what if proc_D runs first? It will assign D' <= A + C' or <= B + C >> + C'; clearly a different result. >> > > This is wrong. Both processes are sensitive only to changes in the signal clk. Because of the 'if rising_edge(clk)', the statements that assign to 'A' and 'D' will only get executed on the rising edge of clk. Neither signal will get updated until all processes that were run on that particular cycle have been executed and suspend. > > Using any compliant VHDL simulator, there will be no differences in the values of 'A' and 'D' based upon which process gets executed first. > >> The way to get around this is to use delta delays for all signal >> assignments. A delta delay can be thought of as smaller than the time >> resolution of the simulation. So it won't show up as a time delay >> anywhere, but it affects the ordering of all processes in the system. >> > > This is what the simulator does, not the user. Is that what you're trying to describe?? > >> In the above example when clk rises at time t=0 it triggers both >> processes to run. However, the assignments will be queued for time >> t=0+d where d represents a delta delay. So once all the processes have >> run at time t=0, the signals will be updated to their new values at >> t=0+d which will give the result shown in the second case above. >> > > This is correct...but directly contradicts what you had said earlier about the values depending on the order of execution of the processes which is not correct for VHDL. I'm guessing that you were talking about some hypothetical language model that looks like VHDL (since that's what your two example processes look like), but in fact really is not (since it updates the signals at the end of each process, which is not what the VHDL LRM specifies). > >> >> I don't know if you have any confusion about this, but I am laid up >> after a hip surgery and have nothing better to do... lol >> > > Maybe you took too many pills before you posted (kidding, hope you get well soon). As I said in the opening paragraph, I was trying to explain the concept of delta delay. Now go back and read it again. I doubt Kristoff has learned about the delta delay yet and might not understand how processes interact if you don't have unit delays. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: learning sequencial logic Date: Sat, 11 Jun 2016 16:45:08 -0400 Organization: A noiseless patient Spider Lines: 182 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 20:45:09 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="16713"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18YM8uPPV3OnLDywUcL6nmu" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:gVYmRGcsIyWNk+Hnf99ERuIhOkI= Xref: news.eternal-september.org comp.lang.vhdl:4428 To clear up any confusion created if you already have some knowledge of delta delays in VHDL, read my comments below. On 6/11/2016 3:24 PM, rickman wrote: > On 6/11/2016 2:35 PM, kristoff wrote: >> Hi Cecil, >> >> >> On 11-06-16 17:25, Cecil Bayona wrote: >> >>>> I must say that learning FPGAs just for books seams to be not very >>>> easy. >>>> There seams to be all kind of "need to knows" that are usually not >>>> covered in the books, so thank you, but to you and to Rick, for your >>>> replies. >> >>> As a newbie I also agree, most books, and I have several books, they are >>> either are too vague design books, or most jump right into the code but >>> leave out a lot of information, they give a lot of details but leave out >>> the overall picture. >> >> >> For me, the problem is that I really never learned much about digital >> logic, I studied electronics some 25 years ago when we already had >> microcontrollers (my thesis was with a 8051). >> >> We did learn about basic digital logic (and, or, not, ...), we never >> really learned how to solve a problem with it. >> >> If you had an issue that involved some kind of "logic" more complex then >> a couple of 74xx ICs and combinational logic, you simply used a >> microcontroller and solved it that way. >> >> We never really learned about thinks like sequential logic, timing, >> clocks, etc, ... or how to solve a technical issue with digital logic >> components; and ... this is what I need now. >> >> Certain concepts used in "programming" (e.g. the idea of a statemachine) >> are also usefull in sequencial logic, but that's about it. The rest is >> -for me- all quite new. > > There is one important concept that you will need when you are > simulating VHDL circuits, that is the delta delay. The delta delay is > used to deal with the problem of simulating concurrent logic. If delta delays were *not* used... > When a signal changes, any process (which includes each concurrent logic > statement as they are also processes) that depends on that signal runs > simultaneously. However, in a simulator "simultaneously" is emulated by > evaluating each process one at a time. If the outputs from one process > are used by another the results will depend on which process is run first! > > proc_A: process (clk) begin > if rising_edge(clk) then > A <= B + C; > end if; > end process proc_A; > > proc_D: process (clk) begin > if rising_edge(clk) then > D <= A + C; > end if; > end process proc_D; Assume C has changed to C' prior to the rising clock edge. > When clk changes both assignments are evaluated. If proc_A runs first, > it becomes A' <= B + C', where the ' indicates the new version of each > signal. proc_D will be evaluated next as D' <= A' + C' or <= B + C' + > C'; So far, so good. > > But what if proc_D runs first? It will assign D' <= A + C' or <= B + C > + C'; clearly a different result. But VHDL does always make use of delta delays when making signal assignments... so... > The way to get around this is to use delta delays for all signal > assignments. A delta delay can be thought of as smaller than the time > resolution of the simulation. So it won't show up as a time delay > anywhere, but it affects the ordering of all processes in the system. > > In the above example when clk rises at time t=0 it triggers both > processes to run. However, the assignments will be queued for time > t=0+d where d represents a delta delay. So once all the processes have > run at time t=0, the signals will be updated to their new values at > t=0+d which will give the result shown in the second case above. > > BTW, Verilog doesn't use delta delays, so I don't know how they get > consistent and accurate results from their simulations. > > I don't know if you have any confusion about this, but I am laid up > after a hip surgery and have nothing better to do... lol > > >>> I assume one will just have to work with full working examples and read >>> through and them do small hardware projects using the knowledge and >>> code from prior working projects, and see how things turn out. >>> At some point I expect that things will start making sense and one can >>> start making small hardware projects without copy and paste, but that >>> point is nowhere here for now. >> >> I started looking around for websites that offer simple exercises to >> learn this. >> >> Perhaps we can share some ideas on exercises we come up ourselfs. >> >> >> At this time, I have two things I want to rey out: >> - first, an I/O extender with SPI. >> >> The SPI-protocol is not that complex and looks to me like a nice example >> of "clocked" sequencial logic. > > SPI is very simple indeed, but in general well thought out. The labels > clearly indicate the direction of signal flow and the clocking avoids > race conditions if used properly. The down side is that it is a bit > more flexible than needed so it can be a bit tricky to set up. > > >> I think it might be doable, to create a VHDL design/circuit that allow >> you to set or clear output pins on a FPGA/CPLD, based on commands >> issued via SPI (from a microcontroller). > > When you say "commands", usually the I/O bits are set/cleared directly > from the data shifted through the SPI port. There is normally the shift > register that receives the serial data (and provides for shifting data > out) which is transferred to the output register when the select line is > deasserted. > > >> - a lot more difficult (perhaps as a "final exercise") is this: >> https://www.youtube.com/watch?v=35zLnS3fXeA >> >> This is a very simple broadboard based 8-bit processor (which seams to >> be the "SAP" architecture used in quite a number of text-book on >> microprocessor architecture) completely implemented in 74xx ICs. > > That might be an ok project, but when it is done, what do you have? Just > an exercise. You might want to design some pieces that will be useful > to you in the future. > > >> I currently how no idea how easy or difficult this will be, but perhaps >> duplicating this in VHDL would be the ultimate "final test" exercise :-) >> >> >> >> >> Do you -or somebody else- have ideas for exercises that might be >> interesting to learn how to solve actual real problems with logic? > > A reasonably simple example would be a basic, fixed size UART, say 8 > bits, no parity, one stop bit. Design the transmitter and receiver > separately and test by connecting them together and shipping characters > across. Equally important is the test bench used to test your design. > You need to learn how to construct simple and yet powerful test benches > to stimulate your designs and verify the output. It is not uncommon for > the test bench to be as complex as the design you are testing, but > hopefully can be done more simply. In this case you can use the UART > transmitter to test the UART receiver and vice versa. The test bench > only needs to stimulate the parallel input/output and the control > strobes. It also does not need to be synthesizable and so can be > written more like a standard sequential program. > > Once you have that working correctly, you can add programmable controls > for the word size, parity and stop bits. That gets a bit more complex > and your test bench will be more complex as well. > > Both of these exercises will result in useful code. Often you can use a > simple, fixed size UART in your designs. Other times you will need a > programmable UART so it can be configured by software or changed for > different modes of operation. > > Just a thought. > -- Rick C From newsfish@newsfish Thu Aug 1 00:37:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 23:51:48 +0200 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> <3df7c334-9134-4f87-a1a1-0e41081d858c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 21:51:48 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3b69aff36207c0e356162b06477ed76e"; logging-data="30497"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX188wsTlyF5dbC3JfTAjg6/p" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 In-Reply-To: <3df7c334-9134-4f87-a1a1-0e41081d858c@googlegroups.com> Cancel-Lock: sha1:pWBEkhRTLWtEy9JKPRgc/9N+CEI= Xref: news.eternal-september.org comp.lang.vhdl:4429 Kevin, On 11-06-16 22:30, KJ wrote: (...) > Short answer is that if you ever feel the need to use both edges of > the clock...most likely you're not going about your design in the > correct manner. Synchronous logic design not only uses only one > clock, but only one edge of that one clock. Having said that, there > are cases when both edges are used and that is the correct thing to > do...but what you've described so far is not an example. Very valuable advice. Thanks! :-) > Kevin Jennings Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:37:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sat, 11 Jun 2016 19:19:49 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> <3df7c334-9134-4f87-a1a1-0e41081d858c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 11 Jun 2016 23:19:50 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="17972"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19clzl8GDlN5/NUDm6N5mjT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:4JXplcLVamX8syw5sx7z2REDg9A= Xref: news.eternal-september.org comp.lang.vhdl:4430 On 6/11/2016 5:51 PM, kristoff wrote: > Kevin, > > > > On 11-06-16 22:30, KJ wrote: > (...) >> Short answer is that if you ever feel the need to use both edges of >> the clock...most likely you're not going about your design in the >> correct manner. Synchronous logic design not only uses only one >> clock, but only one edge of that one clock. Having said that, there >> are cases when both edges are used and that is the correct thing to >> do...but what you've described so far is not an example. > > Very valuable advice. Your SPI interface is one of the places where both edges of the clock *will* be used. When exchanging data externally you can't control the clock skew enough to use the same clock edge for shifting data out and shifting data in. So data is clocked out on one edge and in on the other to assure adequate setup and hold times. There are also some interfaces that specify the transmission of data on both edges of the interface clock. Typically a 2x clock is used, but you can also use a 1x clock with two sets of FFs clocked on opposite clock edges. SDRAM memory interfaces typically do this and extra FFs are included in the IO blocks of many FPGAs for this purpose. Internally this would never be used in an FPGA. I had a discussion once with someone laying out a CPU design who was using the negative clock edge in a pipeline to increase his setup and hold times. I tried to explain to him that this does not improve the setup and hold, but in fact reduces the slack time because within 1 clock cycle two setups and two hold times have to be met. Maybe I wasn't understanding what he was doing, but we never came to an agreement. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sun, 12 Jun 2016 13:01:15 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 12 Jun 2016 17:01:14 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="17981"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Gf2MYTwTjEIrSO1matakX" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:CzjfbWUjQOj7BNCvUQ/m95H2BMg= Xref: news.eternal-september.org comp.lang.vhdl:4431 On 6/11/2016 3:05 PM, kristoff wrote: > Hi Rick, > > On 11-06-16 16:00, rickman wrote: > >>> My question was in the first place intented to get an idea of how to do >>> syncronous design. > >> My bad, see below. I think you are doing pretty well. > > No problem. :-) > > > Last week, I talked to somebody who works in a company that does ASIC > design and he said that -althou VHDL is a high-level language- you need > to keep in mind that this all gets turned into hardware. > > "always try to understand how the hardware that actually does the job > actually works". I used to promote this. I think it is useful for sure, but I don't know it is essential. I was helping a software guy get up to speed on VHDL and he was able to develop a "Hello, world" program without really knowing how the hardware would work. He then went on to design the system his boss needed for a demo to the customer. I started out thinking you needed a knowledge of gate level logic principles and an idea of the register level logic you wanted to create. He showed me these are far from essential. These are very useful when you wish to optimize a design either for size or speed. But even more important is familiarity with the tools you are using. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:01 2024 X-Received: by 10.129.87.136 with SMTP id l130mr10619118ywb.38.1465784105960; Sun, 12 Jun 2016 19:15:05 -0700 (PDT) X-Received: by 10.36.204.4 with SMTP id x4mr156271itf.1.1465784105897; Sun, 12 Jun 2016 19:15:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v48no1203837qgd.0!news-out.google.com!u18ni125qgd.1!nntp.google.com!p34no6133955qgp.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 12 Jun 2016 19:15:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> <3df7c334-9134-4f87-a1a1-0e41081d858c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <581a9e8c-ecb5-4268-9db9-fb50d98d1211@googlegroups.com> Subject: Re: "rising_edge(clk)" and delay From: KJ Injection-Date: Mon, 13 Jun 2016 02:15:05 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4432 On Saturday, June 11, 2016 at 7:19:52 PM UTC-4, rickman wrote: >=20 > Your SPI interface is one of the places where both edges of the clock=20 > *will* be used. When exchanging data externally you can't control the=20 > clock skew enough to use the same clock edge for shifting data out and=20 > shifting data in. So data is clocked out on one edge and in on the=20 > other to assure adequate setup and hold times. >=20 Yes, and SPI is the type of example I had in mind where you might mistakenl= y think going in that you need to use the SPI Clock as an actual clock sign= al to clock some register(s), but you don't. SPI clock edges can be determ= ined by sampling with the free running system clock unless the two clocks a= re close in frequency, which many times they are not. By using the system = clock to clock registers rather than SPI clock you avoid clock domain trans= fers further down the road. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: "rising_edge(clk)" and delay Date: Sun, 12 Jun 2016 22:46:04 -0400 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> <5753652d-d041-4a7c-a56a-0b8032f0bf8a@googlegroups.com> <3df7c334-9134-4f87-a1a1-0e41081d858c@googlegroups.com> <581a9e8c-ecb5-4268-9db9-fb50d98d1211@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 13 Jun 2016 02:46:03 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="29942"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/3wfhyfA5lMK3fNzVXPuSh" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <581a9e8c-ecb5-4268-9db9-fb50d98d1211@googlegroups.com> Cancel-Lock: sha1:joeGPTfn+YdMJ9gFinW6zHZKdOk= Xref: news.eternal-september.org comp.lang.vhdl:4433 On 6/12/2016 10:15 PM, KJ wrote: > On Saturday, June 11, 2016 at 7:19:52 PM UTC-4, rickman wrote: >> >> Your SPI interface is one of the places where both edges of the clock >> *will* be used. When exchanging data externally you can't control the >> clock skew enough to use the same clock edge for shifting data out and >> shifting data in. So data is clocked out on one edge and in on the >> other to assure adequate setup and hold times. >> > Yes, and SPI is the type of example I had in mind where you might mistakenly think going in that you need to use the SPI Clock as an actual clock signal to clock some register(s), but you don't. SPI clock edges can be determined by sampling with the free running system clock unless the two clocks are close in frequency, which many times they are not. By using the system clock to clock registers rather than SPI clock you avoid clock domain transfers further down the road. I've never done it that way. SPI can be pretty fast and you need a clock significantly faster to make it work that way. I implement the shift register as clocked by the SPI clock and then cross the clock domain with a handshake. Then your internal clock only needs to be fast enough to receive the data words. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Gray Code Date: Mon, 13 Jun 2016 01:36:24 -0400 Organization: A noiseless patient Spider Lines: 52 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 13 Jun 2016 05:36:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="23624"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18RMANQheCFvvUWiRSVGBhF" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:wYcMtv6c+aK9d20x1Qlgn3TKstI= Xref: news.eternal-september.org comp.lang.vhdl:4434 I was reading up on Gray codes and figured out a fairly simple algorithm for counting up or down with Gray codes directly rather than using a binary counter which is converted to Gray code. It has not been extensively tested. I don't think it will work for vectors declared with a "to" range rather than a "downto" range. I should have used 'left and 'right instead of 'high and 'low, but I don't know how to construct a loop that goes in either direction. I'll need to dig around to see how that might be done. I got the idea from a verbal description of a Gray code that defined the bit to change as the least significant bit that gives even parity with all the higher bits. They didn't say it just like that, but once I thought about it I realized that was what they should have said. Counting down is the same rule, but odd parity. I didn't synthesize it to see how complex the logic is, but I don't think it should be too bad. Here is the code. Any suggestions are welcome. Function CalcGray (cntr : unsigned; UpDwn : std_logic) return unsigned is variable CntrHigh : natural := cntr'high; variable CntrLow : natural := cntr'low; variable Result : unsigned (cntr'range) := cntr; variable ParityWord : unsigned (CntrHigh downto CntrLow) := (others => '0'); begin ParityWord(CntrHigh) := Result(CntrHigh); for i in CntrHigh-1 downto CntrLow loop ParityWord(i) := ParityWord(i+1) xor Result(i); end loop; for i in CntrLow to CntrHigh loop if ((UpDwn = not ParityWord(i)) or (i = CntrHigh)) then Result(i) := not Result(i); exit; end if; end loop; return Result; end CalcGray; Function NextGray (cntr : unsigned) return unsigned is begin return CalcGray(cntr, '1'); end NextGray; Function PrevGray (cntr : unsigned) return unsigned is begin return CalcGray(cntr, '0'); end PrevGray; -- Rick C From newsfish@newsfish Thu Aug 1 00:37:02 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Mon, 13 Jun 2016 03:31:06 -0400 Organization: A noiseless patient Spider Lines: 76 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 13 Jun 2016 07:31:05 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="9210"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18w8nfIdTy4jWGFeOnSgyxW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:nqSI838SsXs+BjqlFPrU+qIMCtM= Xref: news.eternal-september.org comp.lang.vhdl:4435 On 6/13/2016 1:36 AM, rickman wrote: > I was reading up on Gray codes and figured out a fairly simple algorithm > for counting up or down with Gray codes directly rather than using a > binary counter which is converted to Gray code. It has not been > extensively tested. I don't think it will work for vectors declared > with a "to" range rather than a "downto" range. I should have used > 'left and 'right instead of 'high and 'low, but I don't know how to > construct a loop that goes in either direction. I'll need to dig around > to see how that might be done. > > I got the idea from a verbal description of a Gray code that defined the > bit to change as the least significant bit that gives even parity with > all the higher bits. They didn't say it just like that, but once I > thought about it I realized that was what they should have said. > Counting down is the same rule, but odd parity. I didn't synthesize it > to see how complex the logic is, but I don't think it should be too bad. > > Here is the code. Any suggestions are welcome. > > Function CalcGray (cntr : unsigned; UpDwn : std_logic) > return unsigned is > variable CntrHigh : natural := cntr'high; > variable CntrLow : natural := cntr'low; > variable Result : unsigned (cntr'range) := cntr; > variable ParityWord : unsigned (CntrHigh downto CntrLow) > := (others => '0'); > begin > ParityWord(CntrHigh) := Result(CntrHigh); > for i in CntrHigh-1 downto CntrLow loop > ParityWord(i) := ParityWord(i+1) xor Result(i); > end loop; > for i in CntrLow to CntrHigh loop > if ((UpDwn = not ParityWord(i)) or (i = CntrHigh)) then > Result(i) := not Result(i); > exit; > end if; > end loop; > return Result; > end CalcGray; > > Function NextGray (cntr : unsigned) return unsigned is > begin > return CalcGray(cntr, '1'); > end NextGray; > > Function PrevGray (cntr : unsigned) return unsigned is > begin > return CalcGray(cntr, '0'); > end PrevGray; Here is an improved version of the main routine that works for ascending or descending ranges of the input signal. Function CalcGray (Cntr : unsigned; UpDwn : std_logic) return unsigned is variable CntrLeft : natural := Cntr'LEFT; variable Result : unsigned (cntr'RANGE) := cntr; variable ParityWord : unsigned (Cntr'RANGE); variable PrevParity : std_logic := '0'; begin for i in ParityWord'RANGE loop ParityWord(i) := PrevParity xor Result(i); PrevParity := ParityWord(i); end loop; for i in Result'REVERSE_RANGE loop if ((i = CntrLeft) or (UpDwn /= ParityWord(i))) then Result(i) := not Result(i); -- found the bit to toggle exit; end if; end loop; return Result; end CalcGray; -- Rick C From newsfish@newsfish Thu Aug 1 00:37:03 2024 X-Received: by 10.66.119.39 with SMTP id kr7mr11757342pab.18.1465820310310; Mon, 13 Jun 2016 05:18:30 -0700 (PDT) X-Received: by 10.36.36.211 with SMTP id f202mr228751ita.8.1465820310199; Mon, 13 Jun 2016 05:18:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!feeder.erje.net!2.us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!v48no1359195qgd.0!news-out.google.com!u18ni157qgd.1!nntp.google.com!p34no6289255qgp.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 13 Jun 2016 05:18:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <83e98ea6-1be6-4717-af4a-3eff47f2aee7@googlegroups.com> Subject: Re: Gray Code From: KJ Injection-Date: Mon, 13 Jun 2016 12:18:30 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 9 Xref: news.eternal-september.org comp.lang.vhdl:4436 On Monday, June 13, 2016 at 1:36:25 AM UTC-4, rickman wrote: > > Here is the code. Any suggestions are welcome. Here is a relevant link that might be similar to what you're describing. https://groups.google.com/forum/#!topic/comp.lang.vhdl/Zqq03Hj_N7k I don't remember if I benchmarked it relative to converting/unconverting but I'll take a look. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Mon, 13 Jun 2016 10:06:03 -0400 Organization: A noiseless patient Spider Lines: 38 Message-ID: References: <83e98ea6-1be6-4717-af4a-3eff47f2aee7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 13 Jun 2016 14:06:04 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="28633"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/0zvyQvUg4wqvFGvUNcIFU" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <83e98ea6-1be6-4717-af4a-3eff47f2aee7@googlegroups.com> Cancel-Lock: sha1:NL85DC1xn8tc7umSYvdEJEx6NN4= Xref: news.eternal-september.org comp.lang.vhdl:4437 On 6/13/2016 8:18 AM, KJ wrote: > On Monday, June 13, 2016 at 1:36:25 AM UTC-4, rickman wrote: >> >> Here is the code. Any suggestions are welcome. > > Here is a relevant link that might be similar to what you're describing. > https://groups.google.com/forum/#!topic/comp.lang.vhdl/Zqq03Hj_N7k > > I don't remember if I benchmarked it relative to converting/unconverting but I'll take a look. Interesting. Toward the end of that thread I see mention of two ripple chains, "one chain going up, the other down". This sounds like a similar method as my approach. The parity is calculated from the top down for each bit while a lower bit being flipped disables all upper bits from being considered. Rather than enter equations, my approach is to use loops to describe these chains. It seems to result in a much simpler description. I have used Altera devices enough to know they contain a chain of gates which may be a bit faster than using the 4 LUTs for the disable chain. This would be similar to the carry chain in adders. I don't know if this chain of gates sill appears in the more recent parts. I have a file which I think is from Altera with an extra LSB in the counter used to control the counting in the otherwise LSB of the counter. Then the rule is to increment the least significant bit where the bits below are of the form "100...". The extended counter is initialized to "0..01". This would seem to only require one chain direction plus the extra bit in the register. The code is pretty clean other than the "fixup" needed to make the msb work properly. This is likely an optimal solution. Choose your poison. :) -- Rick C From newsfish@newsfish Thu Aug 1 00:37:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Mon, 13 Jun 2016 20:22:49 -0400 Organization: A noiseless patient Spider Lines: 121 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 14 Jun 2016 00:22:47 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="15452"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ZoLrZvd1wnrPrKcSMw5J8" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:GHIr3QEY6p43TMPRE/5N1t3cyU8= Xref: news.eternal-september.org comp.lang.vhdl:4438 On 6/13/2016 3:31 AM, rickman wrote: > On 6/13/2016 1:36 AM, rickman wrote: >> I was reading up on Gray codes and figured out a fairly simple algorithm >> for counting up or down with Gray codes directly rather than using a >> binary counter which is converted to Gray code. It has not been >> extensively tested. I don't think it will work for vectors declared >> with a "to" range rather than a "downto" range. I should have used >> 'left and 'right instead of 'high and 'low, but I don't know how to >> construct a loop that goes in either direction. I'll need to dig around >> to see how that might be done. >> >> I got the idea from a verbal description of a Gray code that defined the >> bit to change as the least significant bit that gives even parity with >> all the higher bits. They didn't say it just like that, but once I >> thought about it I realized that was what they should have said. >> Counting down is the same rule, but odd parity. I didn't synthesize it >> to see how complex the logic is, but I don't think it should be too bad. >> >> Here is the code. Any suggestions are welcome. >> >> Function CalcGray (cntr : unsigned; UpDwn : std_logic) >> return unsigned is >> variable CntrHigh : natural := cntr'high; >> variable CntrLow : natural := cntr'low; >> variable Result : unsigned (cntr'range) := cntr; >> variable ParityWord : unsigned (CntrHigh downto CntrLow) >> := (others => '0'); >> begin >> ParityWord(CntrHigh) := Result(CntrHigh); >> for i in CntrHigh-1 downto CntrLow loop >> ParityWord(i) := ParityWord(i+1) xor Result(i); >> end loop; >> for i in CntrLow to CntrHigh loop >> if ((UpDwn = not ParityWord(i)) or (i = CntrHigh)) then >> Result(i) := not Result(i); >> exit; >> end if; >> end loop; >> return Result; >> end CalcGray; >> >> Function NextGray (cntr : unsigned) return unsigned is >> begin >> return CalcGray(cntr, '1'); >> end NextGray; >> >> Function PrevGray (cntr : unsigned) return unsigned is >> begin >> return CalcGray(cntr, '0'); >> end PrevGray; > > Here is an improved version of the main routine that works for ascending > or descending ranges of the input signal. > > Function CalcGray (Cntr : unsigned; UpDwn : std_logic) > return unsigned is > variable CntrLeft : natural := Cntr'LEFT; > variable Result : unsigned (cntr'RANGE) := cntr; > variable ParityWord : unsigned (Cntr'RANGE); > variable PrevParity : std_logic := '0'; > begin > for i in ParityWord'RANGE loop > ParityWord(i) := PrevParity xor Result(i); > PrevParity := ParityWord(i); > end loop; > for i in Result'REVERSE_RANGE loop > if ((i = CntrLeft) or (UpDwn /= ParityWord(i))) then > Result(i) := not Result(i); -- found the bit to toggle > exit; > end if; > end loop; > return Result; > end CalcGray; Yet another version based on the Altera example code I found somewhere. They added an lsb to the gray counter register and only need one ripple chain linking upward in the calculation. When I synthesized it I didn't see much difference in speed, both reaching a bit over 200 MHz in a not so fast XP3C-5 with a 16 bit register. I wonder if speed could be improved by using a carry chain? It would likely take some very special code to infer that. Sometimes a small piece of code is not estimated well in an otherwise empty part. The tool can pick a poor pin placement that requires a long route which dominates the path timings. I didn't check that. The component count was different. The previous CalcGray code used 63 LUT4 elements and 16 FFs. That's nearly 4 LUT4s per FF. I expect this ratio goes up with register length. The "fast" version used 45 LUT4s and 22 FFs. I would guess some of the registers are being duplicated to optimize performance, but I'm not sure. The simulation seems to give the right results so I don't think there is an error. I did not test this version with bit reversed parameters. Here is the "fast" code. Function CalcGray (Cntr : unsigned; UpDwn : std_logic) return unsigned is variable CntrLeft : natural := Cntr'LEFT; variable Result : unsigned (cntr'RANGE) := cntr; variable one_found : std_logic; variable ones_below : std_logic; begin for i in Result'REVERSE_RANGE loop if (i = Result'right) then ones_below := '0'; one_found := UpDwn xor Result(0); Result(0) := not Result(0); elsif (i /= CntrLeft) then Result(i) := Result(i) xor (one_found and not ones_below); ones_below := ones_below or one_found; one_found := Result(i); else one_found := Result(i) or one_found; Result(i) := Result(i) xor (one_found and not ones_below); end if; end loop; return Result; end CalcGray; -- Rick C From newsfish@newsfish Thu Aug 1 00:37:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Mon, 13 Jun 2016 21:39:03 -0400 Organization: A noiseless patient Spider Lines: 129 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 14 Jun 2016 01:39:08 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="26418"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18PiPXr+jhk3SJTu1W2SZH/" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:t2u3R2siDhaI0Lq1D6GLug50B8g= Xref: news.eternal-september.org comp.lang.vhdl:4439 On 6/13/2016 8:22 PM, rickman wrote: > On 6/13/2016 3:31 AM, rickman wrote: >> On 6/13/2016 1:36 AM, rickman wrote: >>> I was reading up on Gray codes and figured out a fairly simple algorithm >>> for counting up or down with Gray codes directly rather than using a >>> binary counter which is converted to Gray code. It has not been >>> extensively tested. I don't think it will work for vectors declared >>> with a "to" range rather than a "downto" range. I should have used >>> 'left and 'right instead of 'high and 'low, but I don't know how to >>> construct a loop that goes in either direction. I'll need to dig around >>> to see how that might be done. >>> >>> I got the idea from a verbal description of a Gray code that defined the >>> bit to change as the least significant bit that gives even parity with >>> all the higher bits. They didn't say it just like that, but once I >>> thought about it I realized that was what they should have said. >>> Counting down is the same rule, but odd parity. I didn't synthesize it >>> to see how complex the logic is, but I don't think it should be too bad. >>> >>> Here is the code. Any suggestions are welcome. >>> >>> Function CalcGray (cntr : unsigned; UpDwn : std_logic) >>> return unsigned is >>> variable CntrHigh : natural := cntr'high; >>> variable CntrLow : natural := cntr'low; >>> variable Result : unsigned (cntr'range) := cntr; >>> variable ParityWord : unsigned (CntrHigh downto CntrLow) >>> := (others => '0'); >>> begin >>> ParityWord(CntrHigh) := Result(CntrHigh); >>> for i in CntrHigh-1 downto CntrLow loop >>> ParityWord(i) := ParityWord(i+1) xor Result(i); >>> end loop; >>> for i in CntrLow to CntrHigh loop >>> if ((UpDwn = not ParityWord(i)) or (i = CntrHigh)) then >>> Result(i) := not Result(i); >>> exit; >>> end if; >>> end loop; >>> return Result; >>> end CalcGray; >>> >>> Function NextGray (cntr : unsigned) return unsigned is >>> begin >>> return CalcGray(cntr, '1'); >>> end NextGray; >>> >>> Function PrevGray (cntr : unsigned) return unsigned is >>> begin >>> return CalcGray(cntr, '0'); >>> end PrevGray; >> >> Here is an improved version of the main routine that works for ascending >> or descending ranges of the input signal. >> >> Function CalcGray (Cntr : unsigned; UpDwn : std_logic) >> return unsigned is >> variable CntrLeft : natural := Cntr'LEFT; >> variable Result : unsigned (cntr'RANGE) := cntr; >> variable ParityWord : unsigned (Cntr'RANGE); >> variable PrevParity : std_logic := '0'; >> begin >> for i in ParityWord'RANGE loop >> ParityWord(i) := PrevParity xor Result(i); >> PrevParity := ParityWord(i); >> end loop; >> for i in Result'REVERSE_RANGE loop >> if ((i = CntrLeft) or (UpDwn /= ParityWord(i))) then >> Result(i) := not Result(i); -- found the bit to toggle >> exit; >> end if; >> end loop; >> return Result; >> end CalcGray; > > Yet another version based on the Altera example code I found somewhere. > They added an lsb to the gray counter register and only need one ripple > chain linking upward in the calculation. When I synthesized it I didn't > see much difference in speed, both reaching a bit over 200 MHz in a not > so fast XP3C-5 with a 16 bit register. I wonder if speed could be > improved by using a carry chain? It would likely take some very special > code to infer that. Sometimes a small piece of code is not estimated > well in an otherwise empty part. The tool can pick a poor pin placement > that requires a long route which dominates the path timings. I didn't > check that. > > The component count was different. The previous CalcGray code used 63 > LUT4 elements and 16 FFs. That's nearly 4 LUT4s per FF. I expect this > ratio goes up with register length. The "fast" version used 45 LUT4s > and 22 FFs. I would guess some of the registers are being duplicated to > optimize performance, but I'm not sure. The simulation seems to give > the right results so I don't think there is an error. I did not test > this version with bit reversed parameters. Here is the "fast" code. > > Function CalcGray (Cntr : unsigned; UpDwn : std_logic) > return unsigned is > variable CntrLeft : natural := Cntr'LEFT; > variable Result : unsigned (cntr'RANGE) := cntr; > variable one_found : std_logic; > variable ones_below : std_logic; > begin > > for i in Result'REVERSE_RANGE loop > if (i = Result'right) then > ones_below := '0'; > one_found := UpDwn xor Result(0); > Result(0) := not Result(0); > elsif (i /= CntrLeft) then > Result(i) := Result(i) xor (one_found and not ones_below); > ones_below := ones_below or one_found; > one_found := Result(i); > else > one_found := Result(i) or one_found; > Result(i) := Result(i) xor (one_found and not ones_below); > end if; > end loop; > return Result; > end CalcGray; If anyone cares about the reversed range parameters (to instead of downto) change the two assignments using Result(0) to use Result(i). one_found := UpDwn xor Result(i); Result(i) := not Result(i); -- Rick C From newsfish@newsfish Thu Aug 1 00:37:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Active HDL Generic Controls Date: Tue, 14 Jun 2016 19:27:43 -0400 Organization: A noiseless patient Spider Lines: 12 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 14 Jun 2016 23:27:43 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="2160"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/mT+0+Xt+9YRoFKvUUa48h" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:Kor2rJuIv7JVAD8Q6Ufs/ylpGcU= Xref: news.eternal-september.org comp.lang.vhdl:4440 I am working with Active HDL and I'm pretty sure in the past I was able to set generics at the top level from within the simulator. I see in the Design, Settings dialog box they have a Simulation, Generic/Parameters choice which looks like it should display design generics, but I can't see them. The help file talks about editing these items, but I see no editing controls either. Anyone know what I'm doing wrong? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:04 2024 X-Received: by 10.140.148.4 with SMTP id 4mr20630562qhu.8.1466005293067; Wed, 15 Jun 2016 08:41:33 -0700 (PDT) X-Received: by 10.36.64.133 with SMTP id n127mr665559ita.4.1466005293011; Wed, 15 Jun 2016 08:41:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!31no719102qgh.1!news-out.google.com!u18ni192qgd.1!nntp.google.com!v48no2366205qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Jun 2016 08:41:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Subject: GALs and VHDL From: silverdr Injection-Date: Wed, 15 Jun 2016 15:41:33 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3027 X-Received-Body-CRC: 3484254356 Xref: news.eternal-september.org comp.lang.vhdl:4441 Hello group (and please have understanding for a newbie in the subject). I'd like to make use of GAL chips for a relatively simple logic I need to b= uild. Nine inputs to five outputs, purely combinatorial, non-clocked. I wro= te VHDL design and testbench and successfully tested it on edaplayground.co= m. Now, I'd like to synthesise it and then comes some questions: - what software (preferably but not necessarily free as in speech and open-= source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atm= el and one or two more vendors (don't remember exactly now). - are the synthesised files compatible across different vendors' chips? - If there is a GAL (16V8 for example) which has eight inputs and eight Out= put Logic MacroCells, can some of those OLMCs/pins be configured and used a= s inputs too? Judging by the specs/datasheet "yes" but would like to confir= m that. So far I downloaded and installed the ispLEVER from Lattice, which is still= available and supports "obsolete" devices like GALs. The problem is that w= hen I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I = get output like: ******* Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -tar= get ispGAL -pro ' Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights rese= rved. Version : 2.0.00.17.20.15 Done sucessfully with exit code 1. Error output EDIF file c:/documents and settings/silverdr/my documents/sour= ces/vhdl/r512/r512vhdl.edi Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 Done: failed with exit code: 0002. ******* and am stuck at it. I know there is a CUPL software available from Atmel, and it should be able= to synthesise designs for GALs but I would prefer to stick to VHDL, which = I assume is going to stay with me for some time to come. Therefore rewritin= g the design into CUPL is probably the last resort. I'd be grateful for some clues/hints/pointers. --=20 silverdr From newsfish@newsfish Thu Aug 1 00:37:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: GALs and VHDL Date: Wed, 15 Jun 2016 17:02:04 -0400 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 15 Jun 2016 21:02:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="25302"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/lY/DDVI9SxMelhD12x0lz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Cancel-Lock: sha1:Z52ihNeiwp1SnpGYncPzAT949DI= Xref: news.eternal-september.org comp.lang.vhdl:4442 On 6/15/2016 11:41 AM, silverdr wrote: > Hello group (and please have understanding for a newbie in the subject). > > I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions: > > - what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now). > > - are the synthesised files compatible across different vendors' chips? > > - If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that. > > > So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like: > > ******* > Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro ' > > > Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. > Version : 2.0.00.17.20.15 > > Done sucessfully with exit code 1. > Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi > Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 > > Done: failed with exit code: 0002. > ******* > > and am stuck at it. > > I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort. > > I'd be grateful for some clues/hints/pointers. There should be a window with more information including the detail of what error was found. I don't run the classic version of the Lattice tools, but nose around the interface a bit and see if you can find the report. In Diamond there is a "Design Summary" window where you can get reports under "Process Reports" by clicking the tool name. Look for something smilar. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: GALs and VHDL Date: Thu, 16 Jun 2016 09:26:25 -0400 Organization: Alacron, Inc. Lines: 68 Message-ID: References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 16 Jun 2016 13:28:25 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="31762"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18HXjuPJJUXVsNs+nEHERMH75F2d8eIDB8=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.24) Gecko/20100228 Thunderbird/2.0.0.24 Mnenhy/0.7.6.666 In-Reply-To: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Cancel-Lock: sha1:6MGvWkc4KIcpKKML6mb/ihIF6MI= Xref: news.eternal-september.org comp.lang.vhdl:4443 silverdr wrote: > Hello group (and please have understanding for a newbie in the subject). > > I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions: > > - what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now). > It's been at about 20 years since I used these, so most of the software I remember is long gone. Cypress used to have a free VHDL for PALs. > - are the synthesised files compatible across different vendors' chips? > In the very old days there were PALs, one-time fuse-programmable devices that came from multiple sources and used a standard JEDEC file format to program. These were interchangeable from a code standpoint, although your PAL programmer needed to know about the vendor. Later Lattice came out with GALs and others copied them with devices called PALCEs. Again the JEDEC files were similar. Most vendors had software that would allow you to take a standard PAL JEDEC and convert it to the GAL / PALCE format. Of course this reduces the flexibility of the chip, since the original PALs had a fixed number of inputs and outputs, as well as a fixed number of output registers. > - If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that. > Any I/O pin on the GAL can be used as an input. This is different from the old PALs where only the non-registered output pins had feedback from the pin. > > So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like: > > ******* > Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro ' > > > Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. > Version : 2.0.00.17.20.15 > > Done sucessfully with exit code 1. > Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi > Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 > > Done: failed with exit code: 0002. > ******* > > and am stuck at it. > > I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort. > > I'd be grateful for some clues/hints/pointers. > I don't remember using CUPL, although I have used similar languages like Abel, MachXL, and PALASM. Xilinx ISE allows you to target a CPLD like their XC9500-series, which have a PAL-like architecture. Then you can synthesize your VHDL, "fit" the device and view the resulting equations in Abel syntax. These equations are reduced to sum-of-products, so you can easily see how many product terms are used. I suppose if you are lucky, you can then throw those equations into the Atmel software and target your GAL. Seems like a lot more work than you want, though. -- Gabor From newsfish@newsfish Thu Aug 1 00:37:05 2024 X-Received: by 10.129.76.87 with SMTP id z84mr3519841ywa.39.1466084240116; Thu, 16 Jun 2016 06:37:20 -0700 (PDT) X-Received: by 10.36.81.79 with SMTP id s76mr829146ita.9.1466084240063; Thu, 16 Jun 2016 06:37:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v48no2807492qgd.0!news-out.google.com!v8ni444qgv.0!nntp.google.com!v48no2807489qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 06:37:19 -0700 (PDT) In-Reply-To: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3153e102-7387-438f-ae5a-5ad0e238d9a2@googlegroups.com> Subject: Re: GALs and VHDL From: Thomas Stanka Injection-Date: Thu, 16 Jun 2016 13:37:20 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4444 Am Mittwoch, 15. Juni 2016 17:41:35 UTC+2 schrieb silverdr: > I'd like to make use of GAL chips for a relatively simple logic I need to= build. Nine inputs to five outputs, purely combinatorial, non-clocked. I w= rote VHDL design and testbench and successfully tested it on edaplayground.= com. Now, I'd like to synthesise it and then comes some questions: >=20 > - what software (preferably but not necessarily free as in speech and ope= n-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, A= tmel and one or two more vendors (don't remember exactly now). >=20 > - are the synthesised files compatible across different vendors' chips? In usual meaning No. Synthesis means usually you translate a v(hdl) description into a library d= ependend structural netlist containing only library primitives of the targe= t library. The tool usually translate it first in a generic (target indepen= dent) netlist and converts than to a library dependen netlist but for the u= ser the intermediate result is not accessible.=20 Especially the "free" (in terms of no cost) versions that are available fro= m major FPGA vendors allow only the usage of dedicated libraries, while a f= ull blown synthesizer license would usually allow to include self written l= ibraries (and therefore the possibility eg to write out a netlist converted= in NAND2, if you design a library containing only nand2 and Flipflop). =20 > Error output EDIF file c:/documents and settings/silverdr/my documents/so= urces/vhdl/r512/r512vhdl.edi > Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 This might be related to an error in your vhdl description. Impossible for = me to guess why this error is generated. From newsfish@newsfish Thu Aug 1 00:37:06 2024 X-Received: by 10.129.49.142 with SMTP id x136mr3480873ywx.45.1466086653234; Thu, 16 Jun 2016 07:17:33 -0700 (PDT) X-Received: by 10.36.64.133 with SMTP id n127mr845453ita.4.1466086653136; Thu, 16 Jun 2016 07:17:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!31no1175008qgh.1!news-out.google.com!u18ni811qgd.1!nntp.google.com!31no1175002qgh.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 07:17:32 -0700 (PDT) In-Reply-To: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <342594a4-eb77-40c3-ab27-220bc3509ee4@googlegroups.com> Subject: Re: GALs and VHDL From: KJ Injection-Date: Thu, 16 Jun 2016 14:17:33 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:4445 On Wednesday, June 15, 2016 at 11:41:35 AM UTC-4, silverdr wrote: > > - are the synthesised files compatible across different vendors' chips? > For PAL/GAL devices, the synthesis output file is a JEDEC file that is used to program the device. For those devices, the JEDEC files were not vendor specific. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:06 2024 X-Received: by 10.200.42.162 with SMTP id b31mr3615056qta.23.1466086816515; Thu, 16 Jun 2016 07:20:16 -0700 (PDT) X-Received: by 10.36.253.132 with SMTP id m126mr186855ith.10.1466086816479; Thu, 16 Jun 2016 07:20:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!31no1175917qgh.1!news-out.google.com!u18ni811qgd.1!nntp.google.com!31no1175916qgh.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 07:20:15 -0700 (PDT) In-Reply-To: <3153e102-7387-438f-ae5a-5ad0e238d9a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <3153e102-7387-438f-ae5a-5ad0e238d9a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: GALs and VHDL From: KJ Injection-Date: Thu, 16 Jun 2016 14:20:16 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4446 On Thursday, June 16, 2016 at 9:37:21 AM UTC-4, Thomas Stanka wrote: > Am Mittwoch, 15. Juni 2016 17:41:35 UTC+2 schrieb silverdr: > > > > - are the synthesised files compatible across different vendors' chips? > > In usual meaning No. > > Synthesis means usually you translate a v(hdl) description into a library > dependend structural netlist containing only library primitives of the > target library. The tool usually translate it first in a generic (target > independent) netlist and converts than to a library dependen netlist but > for the user the intermediate result is not accessible. > What you described isn't really the case with PAL/GAL devices that the OP was referencing. The output of synthesis for these devices is a JEDEC file which typically could be used to program the device regardless of the vendor. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:06 2024 X-Received: by 10.66.253.2 with SMTP id zw2mr3796304pac.43.1466091153704; Thu, 16 Jun 2016 08:32:33 -0700 (PDT) X-Received: by 10.36.87.195 with SMTP id u186mr213657ita.3.1466091153631; Thu, 16 Jun 2016 08:32:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!v48no2849483qgd.0!news-out.google.com!u18ni818qgd.1!nntp.google.com!v48no2849479qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 08:32:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> Subject: Re: GALs and VHDL From: silverdr Injection-Date: Thu, 16 Jun 2016 15:32:33 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 26 Xref: news.eternal-september.org comp.lang.vhdl:4447 On Wednesday, 15 June 2016 23:02:10 UTC+2, rickman wrote: > > So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like: > > > > ******* > > Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro ' > > > > > > Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. > > Version : 2.0.00.17.20.15 > > > > Done sucessfully with exit code 1. > > Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi > > Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 > > > > Done: failed with exit code: 0002. > > ******* > > > > There should be a window with more information including the detail of > what error was found. I don't run the classic version of the Lattice > tools, but nose around the interface a bit and see if you can find the > report. In Diamond there is a "Design Summary" window where you can get > reports under "Process Reports" by clicking the tool name. Look for > something smilar. > Actually the above is the copy-paste from the only output (except dialog-box, which says even less) I can find. From newsfish@newsfish Thu Aug 1 00:37:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: =?UTF-8?Q?Will_Work_for_H=c3=a4agen-Dazs?= Date: Thu, 16 Jun 2016 11:39:15 -0400 Organization: A noiseless patient Spider Lines: 8 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 16 Jun 2016 15:39:16 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="29142"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19wc86Ajjia06XPOlo8hsRL" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:y0wJ4N5nAZB+4WTP2xsZ7VwzRbo= Xref: news.eternal-september.org comp.lang.vhdl:4448 I am recovering from hip surgery and have passed the point of significant pain, but am still house bound. I'm seriously bored and would be happy to work on a project if anyone has something they can hand off. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: GALs and VHDL Date: Thu, 16 Jun 2016 11:44:41 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 16 Jun 2016 15:44:47 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="30523"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX187eCDqwaTWWgznEFFt4awO" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> Cancel-Lock: sha1:k/XkPDB1tmbUHGGPyxIyxTFzGac= Xref: news.eternal-september.org comp.lang.vhdl:4449 On 6/16/2016 11:32 AM, silverdr wrote: > On Wednesday, 15 June 2016 23:02:10 UTC+2, rickman wrote: >>> So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like: >>> >>> ******* >>> Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro ' >>> >>> >>> Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. >>> Version : 2.0.00.17.20.15 >>> >>> Done sucessfully with exit code 1. >>> Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi >>> Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 >>> >>> Done: failed with exit code: 0002. >>> ******* >>> >> >> There should be a window with more information including the detail of >> what error was found. I don't run the classic version of the Lattice >> tools, but nose around the interface a bit and see if you can find the >> report. In Diamond there is a "Design Summary" window where you can get >> reports under "Process Reports" by clicking the tool name. Look for >> something smilar. >> > > Actually the above is the copy-paste from the only output (except dialog-box, which says even less) I can find. There will be a synthesis report somewhere. You just need to find it. The exit error code tells you not so much. Your output above says it is running Synplicity. Look for the design directories and sort the files by date. The report will be one of the most recent. Have you checked for licensing issues? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:07 2024 X-Received: by 10.129.40.199 with SMTP id o190mr3864909ywo.1.1466091899761; Thu, 16 Jun 2016 08:44:59 -0700 (PDT) X-Received: by 10.36.230.69 with SMTP id e66mr267598ith.0.1466091899715; Thu, 16 Jun 2016 08:44:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!v48no2854868qgd.0!news-out.google.com!u18ni818qgd.1!nntp.google.com!v48no2854865qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 08:44:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <713cc64b-8860-4af9-bf9d-801376aec20a@googlegroups.com> Subject: Re: GALs and VHDL From: silverdr Injection-Date: Thu, 16 Jun 2016 15:44:59 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 64 Xref: news.eternal-september.org comp.lang.vhdl:4450 On Thursday, 16 June 2016 15:28:27 UTC+2, Gabor Sz wrote: > > - what software (preferably but not necessarily free as in speech and o= pen-source) should I use for that? I have 16V8 and 20V8 chips from Lattice,= Atmel and one or two more vendors (don't remember exactly now). > >=20 >=20 > It's been at about 20 years since I used these, so most of the software > I remember is long gone. Cypress used to have a free VHDL for PALs. I tried also "Galaxy WARP 6.3 SP1" from Cypress. Here things go a lot bette= r. It compiles and outputs a JEDEC file but this is for PAL with a most sim= ilar name/symbol. Not for GAL and I have no idea whether this file can be s= afely used. I am sure it doesn't take into account any GAL specific stuff. > > - are the synthesised files compatible across different vendors' chips? >=20 > In the very old days there were PALs, one-time fuse-programmable devices > that came from multiple sources and used a standard JEDEC file format to > program. These were interchangeable from a code standpoint, although > your PAL programmer needed to know about the vendor. >=20 > Later Lattice came out with GALs and others copied them with devices > called PALCEs. Again the JEDEC files were similar. Most vendors had > software that would allow you to take a standard PAL JEDEC and convert > it to the GAL / PALCE format. Of course this reduces the flexibility > of the chip, since the original PALs had a fixed number of inputs and > outputs, as well as a fixed number of output registers. I see - that's a trail I might have a look into if nothing else works. Well= , I don't know if this one is going to work at all either. So far I don't h= ave any tools for converting the PAL JEDEC (which I seem to have from the C= ypress Galaxy WARP software) into GAL/PALCE format. > > - If there is a GAL (16V8 for example) which has eight inputs and eight= Output Logic MacroCells, can some of those OLMCs/pins be configured and us= ed as inputs too? Judging by the specs/datasheet "yes" but would like to co= nfirm that. > >=20 >=20 > Any I/O pin on the GAL can be used as an input. This is different from > the old PALs where only the non-registered output pins had feedback from > the pin. Thanks. That's more or less what I thought, yet - just to make sure - does = that mean that on a GAL16V8 I could theoretically use fifteen inputs and ha= ve one output only? Or are there any other limitations, which would prevent= that kind of use? > > I know there is a CUPL software available from Atmel, and it should be = able to synthesise designs for GALs but I would prefer to stick to VHDL, wh= ich I assume is going to stay with me for some time to come. Therefore rewr= iting the design into CUPL is probably the last resort. > >=20 > I don't remember using CUPL, although I have used similar languages like > Abel, MachXL, and PALASM. Xilinx ISE allows you to target a CPLD like > their XC9500-series, which have a PAL-like architecture. Then you can > synthesize your VHDL, "fit" the device and view the resulting equations > in Abel syntax. These equations are reduced to sum-of-products, so you > can easily see how many product terms are used. I suppose if you are > lucky, you can then throw those equations into the Atmel software and > target your GAL. Seems like a lot more work than you want, though. Huh.. yes. I was kind of expecting that I can get the output for my specifi= c chip, fiddling with VHDL only ;-) From newsfish@newsfish Thu Aug 1 00:37:07 2024 X-Received: by 10.66.119.39 with SMTP id kr7mr4071741pab.18.1466092880685; Thu, 16 Jun 2016 09:01:20 -0700 (PDT) X-Received: by 10.36.64.133 with SMTP id n127mr881638ita.4.1466092880610; Thu, 16 Jun 2016 09:01:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!31no1216398qgh.1!news-out.google.com!u18ni819qgd.1!nntp.google.com!31no1216391qgh.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 09:01:20 -0700 (PDT) In-Reply-To: <3153e102-7387-438f-ae5a-5ad0e238d9a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <3153e102-7387-438f-ae5a-5ad0e238d9a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4073f851-6698-4d0a-9b21-81be027a80bb@googlegroups.com> Subject: Re: GALs and VHDL From: silverdr Injection-Date: Thu, 16 Jun 2016 16:01:20 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 87 Xref: news.eternal-september.org comp.lang.vhdl:4451 On Thursday, 16 June 2016 15:37:21 UTC+2, Thomas Stanka wrote: > > - are the synthesised files compatible across different vendors' chips? >=20 > In usual meaning No. >=20 > Synthesis means usually you translate a v(hdl) description into a library= dependend structural netlist containing only library primitives of the tar= get library. The tool usually translate it first in a generic (target indep= endent) netlist and converts than to a library dependen netlist but for the= user the intermediate result is not accessible.=20 >=20 > Especially the "free" (in terms of no cost) versions that are available f= rom major FPGA vendors allow only the usage of dedicated libraries, while a= full blown synthesizer license would usually allow to include self written= libraries (and therefore the possibility eg to write out a netlist convert= ed in NAND2, if you design a library containing only nand2 and Flipflop). I am aware that if we talk about CPLDs/FPGAs, then those are not compatible= , output files are not compatible and I'd possibly be lucky if VHDL source = files were compatible without any adaptations ;-) But I am not talking about CPLDs/FPGAs but "standardised" SPLDs, namely GAL= s. They seem to be compatible across different vendors. Might not be progra= mmed the same way though. Which is what I ask about.=20 Because when I eventually get my designs synthesised somehow by /some/ soft= ware from /a/ vendor, I'd like to use the chips I have from different manuf= acturers. Obviously it wouldn't be much of an issue if the making the softw= are work and output something usable wasn't such a PITA as I experienced so= far. > This might be related to an error in your vhdl description. Impossible fo= r me to guess why this error is generated. We're in the same boat. I can post the vhdl if that helps - it's almost a k= ind of "Hello, world!" though and both edaplayground and Cypress Galaxy don= 't complain -- Design for RL512 library IEEE; use IEEE.std_logic_1164.all; entity RL512 is port( kl : in std_logic; ksw1 : in std_logic; ksw0 : in std_logic; cm : in std_logic; csw1 : in std_logic; csw0 : in std_logic; bc : in std_logic; bsw0 : in std_logic; a12m : in std_logic; oe : out std_logic; a15 : out std_logic; a14 : out std_logic; a13 : out std_logic; a12 : out std_logic); --attribute pin_numbers of RL512:entity is -- "kl:2 ksw1:3 ksw0:4 cm:5 csw1:6 csw0:7 bc:8 bsw0:9 a12m:18 " -- & "oe:19 a15:15 a14:14 a13:13 a12:12"; end RL512; architecture rl512_behavioral of RL512 is begin oe <=3D kl and cm and bc; a15 <=3D not kl when ((kl =3D '0') or (cm =3D '0') or (bc =3D '0')) els= e 'Z'; a14 <=3D ksw1 when kl =3D '0' else '1' when cm =3D '0' else '0' when bc =3D '0' else 'Z'; a13 <=3D ksw0 when kl =3D '0' else csw1 when cm =3D '0' else bsw0 when bc =3D '0' else 'Z'; a12 <=3D a12m when kl =3D'0' else csw0 when cm =3D '0' else a12m when bc =3D '0' else 'Z'; end rl512_behavioral; From newsfish@newsfish Thu Aug 1 00:37:08 2024 X-Received: by 10.129.120.8 with SMTP id t8mr4096512ywc.58.1466093205289; Thu, 16 Jun 2016 09:06:45 -0700 (PDT) X-Received: by 10.36.230.69 with SMTP id e66mr275024ith.0.1466093205249; Thu, 16 Jun 2016 09:06:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!v48no2865505qgd.0!news-out.google.com!u18ni819qgd.1!nntp.google.com!31no1218582qgh.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 09:06:44 -0700 (PDT) In-Reply-To: <342594a4-eb77-40c3-ab27-220bc3509ee4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <342594a4-eb77-40c3-ab27-220bc3509ee4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: GALs and VHDL From: silverdr Injection-Date: Thu, 16 Jun 2016 16:06:45 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 13 Xref: news.eternal-september.org comp.lang.vhdl:4452 On Thursday, 16 June 2016 16:17:34 UTC+2, KJ wrote: > On Wednesday, June 15, 2016 at 11:41:35 AM UTC-4, silverdr wrote: > >=20 > > - are the synthesised files compatible across different vendors' chips? > >=20 > For PAL/GAL devices, the synthesis output file is a JEDEC file that is us= ed to program the device. For those devices, the JEDEC files were not vend= or specific. Thanks! That's the only good news so far :-) So theoretically I should be a= ble to use the PAL output from Cypress Galaxy WARP (which is the only one t= hat produced something so far), somehow (yeah..) convert it into another fo= rm of JEDEC file in a GAL format and then use to program all the GALs of on= e main type I have (like all 16V8 in my case here), right? From newsfish@newsfish Thu Aug 1 00:37:08 2024 X-Received: by 10.200.45.143 with SMTP id p15mr4113719qta.21.1466093814180; Thu, 16 Jun 2016 09:16:54 -0700 (PDT) X-Received: by 10.36.20.206 with SMTP id 197mr883208itg.3.1466093814123; Thu, 16 Jun 2016 09:16:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v48no2869454qgd.0!news-out.google.com!u18ni822qgd.1!nntp.google.com!31no1222526qgh.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 09:16:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: GALs and VHDL From: silverdr Injection-Date: Thu, 16 Jun 2016 16:16:54 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4453 On Thursday, 16 June 2016 17:44:49 UTC+2, rickman wrote: >=20 > There will be a synthesis report somewhere. You just need to find it.=20 > The exit error code tells you not so much. Your output above says it is= =20 > running Synplicity. Look for the design directories and sort the files= =20 > by date. The report will be one of the most recent. The most recent is the automake.log, which contains what I quoted. It's fol= lowed by .TCL and .PRJ and .JID files, which don't seem to contain anything= useful in the context. Unless it throws that report somewhere into a darke= st corner of the harddrive, I don't see anything else. > Have you checked for licensing issues? Maybe I don't know how but I haven't noticed anything about licensing. I ca= n view the EULA (from 2012 - not so old) and nothing complains about licens= ing. From newsfish@newsfish Thu Aug 1 00:37:08 2024 X-Received: by 10.66.67.11 with SMTP id j11mr4216708pat.48.1466095637918; Thu, 16 Jun 2016 09:47:17 -0700 (PDT) X-Received: by 10.36.84.85 with SMTP id t82mr890590ita.7.1466095637847; Thu, 16 Jun 2016 09:47:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!v48no2879419qgd.0!news-out.google.com!u18ni823qgd.1!nntp.google.com!v48no2879415qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 09:47:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <342594a4-eb77-40c3-ab27-220bc3509ee4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <316d932b-1c31-4b27-b26a-91f10f33d3b6@googlegroups.com> Subject: Re: GALs and VHDL From: KJ Injection-Date: Thu, 16 Jun 2016 16:47:17 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 30 Xref: news.eternal-september.org comp.lang.vhdl:4454 On Thursday, June 16, 2016 at 12:06:46 PM UTC-4, silverdr wrote: > > For PAL/GAL devices, the synthesis output file is a JEDEC file that is= =20 > > used to program the device. For those devices, the JEDEC files were no= t=20 > > vendor specific. >=20 > Thanks! That's the only good news so far :-) So theoretically I should be= =20 > able to use the PAL output from Cypress Galaxy WARP (which is the only on= e=20 > that produced something so far), somehow (yeah..) convert it into another= =20 > form of JEDEC file in a GAL format and then use to program all the GALs o= f=20 > one main type I have (like all 16V8 in my case here), right? I don't know that you can take the JEDEC file of one device and use it on a= different one (i.e. 16R8 JEDEC file using on a 16V8). What I said was tha= t you can take a JEDEC file and use it with any manufacturer's same device = (i.e. Cypress 16V8 using on a Lattice 16V8). Having said that though, it might be that you can take a 16R8 and use it to= program a 16V8. When the GAL devices were first coming out in the 80s the= re were lots of manufacturers of SPLDs and competition. I wouldn't conside= r it to much of a stretch to think that Lattice V8 did accept a JEDEC file = that originally was intended for an MMI 16R8 since it would allow them to g= rab market share even more easily. I just remember if that was the case or= not. The parts are very similar after all. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: GALs and VHDL Date: Thu, 16 Jun 2016 13:06:01 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 16 Jun 2016 17:06:02 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="16842"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX186a3J2lwE+/ctz89p0cdPY" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:fBvmP9cjqArv43i83HJXAyLH7Co= Xref: news.eternal-september.org comp.lang.vhdl:4455 On 6/16/2016 12:16 PM, silverdr wrote: > On Thursday, 16 June 2016 17:44:49 UTC+2, rickman wrote: > >> >> There will be a synthesis report somewhere. You just need to find it. >> The exit error code tells you not so much. Your output above says it is >> running Synplicity. Look for the design directories and sort the files >> by date. The report will be one of the most recent. > > The most recent is the automake.log, which contains what I quoted. It's followed by .TCL and .PRJ and .JID files, which don't seem to contain anything useful in the context. Unless it throws that report somewhere into a darkest corner of the harddrive, I don't see anything else. > >> Have you checked for licensing issues? > > Maybe I don't know how but I haven't noticed anything about licensing. I can view the EULA (from 2012 - not so old) and nothing complains about licensing. I don't know for sure, but Synplicity should need a license to run. I seem to recall when my license expires I get an exit error of 2. Check the Lattice web site to see what they say about licensing this tool. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:09 2024 X-Received: by 10.157.2.39 with SMTP id 36mr1720078otb.15.1466113044977; Thu, 16 Jun 2016 14:37:24 -0700 (PDT) X-Received: by 10.36.103.134 with SMTP id u128mr300894itc.5.1466113044923; Thu, 16 Jun 2016 14:37:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v48no2973745qgd.0!news-out.google.com!u18ni837qgd.1!nntp.google.com!v48no2973744qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 14:37:24 -0700 (PDT) In-Reply-To: <316d932b-1c31-4b27-b26a-91f10f33d3b6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <342594a4-eb77-40c3-ab27-220bc3509ee4@googlegroups.com> <316d932b-1c31-4b27-b26a-91f10f33d3b6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: GALs and VHDL From: silverdr Injection-Date: Thu, 16 Jun 2016 21:37:24 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4456 On Thursday, 16 June 2016 18:47:20 UTC+2, KJ wrote: > > Thanks! That's the only good news so far :-) So theoretically I should = be=20 > > able to use the PAL output from Cypress Galaxy WARP (which is the only = one=20 > > that produced something so far), somehow (yeah..) convert it into anoth= er=20 > > form of JEDEC file in a GAL format and then use to program all the GALs= of=20 > > one main type I have (like all 16V8 in my case here), right? >=20 > I don't know that you can take the JEDEC file of one device and use it on= a different one (i.e. 16R8 JEDEC file using on a 16V8). What I said was t= hat you can take a JEDEC file and use it with any manufacturer's same devic= e (i.e. Cypress 16V8 using on a Lattice 16V8). That's what I mean. I have chips from different manufacturers but all are o= f the same type designation 16V8 and 20V8. But the only, theoretically poss= ible path now is through Cypress tools, which generate some PAL type of JED= EC file. If I can convert it (somehow) to GAL16V8 type JEDEC file then this= JEDEC file should work with all GAL16V8s I have, correct? > Having said that though, it might be that you can take a 16R8 and use it = to program a 16V8. When the GAL devices were first coming out in the 80s t= here were lots of manufacturers of SPLDs and competition. I wouldn't consi= der it to much of a stretch to think that Lattice V8 did accept a JEDEC fil= e that originally was intended for an MMI 16R8 since it would allow them to= grab market share even more easily. I just remember if that was the case = or not. The parts are very similar after all. Hm, interesting. Pardon my ignorance but what are the chances of damaging/"= bricking" the chip when feeding the programmer with a wrong JEDEC file? From newsfish@newsfish Thu Aug 1 00:37:09 2024 X-Received: by 10.157.46.148 with SMTP id w20mr1792715ota.49.1466113502394; Thu, 16 Jun 2016 14:45:02 -0700 (PDT) X-Received: by 10.36.57.131 with SMTP id l125mr300656ita.7.1466113502339; Thu, 16 Jun 2016 14:45:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v48no2978155qgd.0!news-out.google.com!u18ni839qgd.1!nntp.google.com!v48no2978151qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 14:45:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0edaea93-6a16-4d8a-83c6-898283629d11@googlegroups.com> Subject: Re: GALs and VHDL From: silverdr Injection-Date: Thu, 16 Jun 2016 21:45:02 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2139 X-Received-Body-CRC: 330415694 Xref: news.eternal-september.org comp.lang.vhdl:4457 On Thursday, 16 June 2016 19:06:04 UTC+2, rickman wrote: > >> Have you checked for licensing issues? > > > > Maybe I don't know how but I haven't noticed anything about licensing. = I can view the EULA (from 2012 - not so old) and nothing complains about li= censing. >=20 > I don't know for sure, but Synplicity should need a license to run. I=20 > seem to recall when my license expires I get an exit error of 2. Check= =20 > the Lattice web site to see what they say about licensing this tool. I just tried something else - instead of trying to compile VHDL, for testin= g purposes I entered a simple schematic of two gates and went that route. S= eems that I can get through the process up to a JEDEC file. So it hopefully= means that Synplify is properly licensed. Unless I miss something here. From newsfish@newsfish Thu Aug 1 00:37:10 2024 X-Received: by 10.107.134.98 with SMTP id i95mr5983222iod.26.1466113684878; Thu, 16 Jun 2016 14:48:04 -0700 (PDT) X-Received: by 10.36.23.206 with SMTP id 197mr958172ith.2.1466113684675; Thu, 16 Jun 2016 14:48:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!31no1332745qgh.1!news-out.google.com!v8ni461qgv.0!nntp.google.com!v48no2979604qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 14:48:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: GALs and VHDL From: silverdr Injection-Date: Thu, 16 Jun 2016 21:48:04 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4458 On Thursday, 16 June 2016 19:06:04 UTC+2, rickman wrote: > I don't know for sure, but Synplicity should need a license to run. I > seem to recall when my license expires I get an exit error of 2. Check > the Lattice web site to see what they say about licensing this tool. I'll have a look anyway. From newsfish@newsfish Thu Aug 1 00:37:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: GALs and VHDL Date: Thu, 16 Jun 2016 18:06:05 -0400 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> <0edaea93-6a16-4d8a-83c6-898283629d11@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 16 Jun 2016 22:06:05 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="23034"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+WEO+GIJ2KcLcFDb5Febcl" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <0edaea93-6a16-4d8a-83c6-898283629d11@googlegroups.com> Cancel-Lock: sha1:FcgwGMxOIp5HsWmixaEBm37jBDk= Xref: news.eternal-september.org comp.lang.vhdl:4459 On 6/16/2016 5:45 PM, silverdr wrote: > On Thursday, 16 June 2016 19:06:04 UTC+2, rickman wrote: > >>>> Have you checked for licensing issues? >>> >>> Maybe I don't know how but I haven't noticed anything about licensing. I can view the EULA (from 2012 - not so old) and nothing complains about licensing. >> >> I don't know for sure, but Synplicity should need a license to run. I >> seem to recall when my license expires I get an exit error of 2. Check >> the Lattice web site to see what they say about licensing this tool. > > I just tried something else - instead of trying to compile VHDL, for testing purposes I entered a simple schematic of two gates and went that route. Seems that I can get through the process up to a JEDEC file. So it hopefully means that Synplify is properly licensed. Unless I miss something here. How does schematic work? Do they produce an EDIF file from that which Synplicity processes? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:10 2024 X-Received: by 10.36.196.67 with SMTP id v64mr6182322itf.11.1466117691843; Thu, 16 Jun 2016 15:54:51 -0700 (PDT) X-Received: by 10.36.36.211 with SMTP id f202mr964167ita.8.1466117691620; Thu, 16 Jun 2016 15:54:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!v48no2996986qgd.0!news-out.google.com!u18ni26qgd.1!nntp.google.com!v48no2996981qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Jun 2016 15:54:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.43.3.237; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.43.3.237 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2c963d09-8c95-4717-a819-4062f7b3aebd@googlegroups.com> Subject: =?UTF-8?Q?Re=3A_Will_Work_for_H=C3=A4agen=2DDazs?= From: Jim Lewis Injection-Date: Thu, 16 Jun 2016 22:54:51 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:4460 So do you quote an hourly rate in terms of pints of H=C3=A4agen-Dazs :) From newsfish@newsfish Thu Aug 1 00:37:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: =?UTF-8?Q?Re:_Will_Work_for_H=c3=a4agen-Dazs?= Date: Thu, 16 Jun 2016 19:05:45 -0400 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <2c963d09-8c95-4717-a819-4062f7b3aebd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 16 Jun 2016 23:05:46 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="1542"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/f4oKSGYCXd5KfTrMly8A6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <2c963d09-8c95-4717-a819-4062f7b3aebd@googlegroups.com> Cancel-Lock: sha1:s2ZOxcwhbmIeQPC21dDG/NUpof0= Xref: news.eternal-september.org comp.lang.vhdl:4461 On 6/16/2016 6:54 PM, Jim Lewis wrote: > So do you quote an hourly rate in terms of pints of Häagen-Dazs > :) If I did, it would have to be fractional. That stuff can kill! -- Rick C From newsfish@newsfish Thu Aug 1 00:37:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: =?UTF-8?Q?Re:_Will_Work_for_H=c3=a4agen-Dazs?= Date: Mon, 20 Jun 2016 11:24:29 -0400 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 20 Jun 2016 15:24:29 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3c3e53f4f1b58b629f69a9ba65192bdb"; logging-data="20751"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/uJL5xElyrBI0TMTH+CYZq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:pF92OBww1mVFB7CfAtcbq6y6/Ac= Xref: news.eternal-september.org comp.lang.vhdl:4462 On 6/16/2016 11:39 AM, rickman wrote: > I am recovering from hip surgery and have passed the point of > significant pain, but am still house bound. I'm seriously bored and > would be happy to work on a project if anyone has something they can > hand off. This doesn't seem to be generating much business. Maybe I should lower my price. I'll work for Ben & Jerry's! 1 pint per day. You should not pass up this limited time offer. My hip is getting much better and I'll be running around soon. :) -- Rick C From newsfish@newsfish Thu Aug 1 00:37:11 2024 X-Received: by 10.25.80.7 with SMTP id e7mr2099160lfb.7.1466442562128; Mon, 20 Jun 2016 10:09:22 -0700 (PDT) X-Received: by 10.36.124.143 with SMTP id a137mr293479itd.9.1466442562015; Mon, 20 Jun 2016 10:09:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!w10no4386989lbo.0!news-out.google.com!di11ni9858lbb.1!nntp.google.com!oe3no6186509lbb.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 20 Jun 2016 10:09:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: GALs and VHDL From: silverdr Injection-Date: Mon, 20 Jun 2016 17:09:22 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4463 On Thursday, 16 June 2016 23:48:07 UTC+2, silverdr wrote: > On Thursday, 16 June 2016 19:06:04 UTC+2, rickman wrote: > > > I don't know for sure, but Synplicity should need a license to run. I > > seem to recall when my license expires I get an exit error of 2. Check > > the Lattice web site to see what they say about licensing this tool. > > I'll have a look anyway. Tried and re-licenced the software - the licence.dat contains all the packages, including Syn stuff. So this shouldn't (at least theoretically) be the cause. From newsfish@newsfish Thu Aug 1 00:37:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: GALs and VHDL Date: Mon, 20 Jun 2016 13:14:27 -0400 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 20 Jun 2016 17:14:26 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="12718"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wknywYr5BBOj5apUv2cwX" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:5l8L1RzELipxrKLwodfFaWKR8VI= Xref: news.eternal-september.org comp.lang.vhdl:4464 On 6/20/2016 1:09 PM, silverdr wrote: > On Thursday, 16 June 2016 23:48:07 UTC+2, silverdr wrote: >> On Thursday, 16 June 2016 19:06:04 UTC+2, rickman wrote: >> >>> I don't know for sure, but Synplicity should need a license to run. I >>> seem to recall when my license expires I get an exit error of 2. Check >>> the Lattice web site to see what they say about licensing this tool. >> >> I'll have a look anyway. > > Tried and re-licenced the software - the licence.dat contains all the packages, including Syn stuff. So this shouldn't (at least theoretically) be the cause. If the tool has a button for firing up the simulator without doing a compile (the Diamond and iCE40 tools do) see if you can bring up the GUI. If you can, the license is good. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:12 2024 X-Received: by 10.46.1.134 with SMTP id f6mr3726255lji.6.1466442988085; Mon, 20 Jun 2016 10:16:28 -0700 (PDT) X-Received: by 10.36.64.133 with SMTP id n127mr289094ita.4.1466442987971; Mon, 20 Jun 2016 10:16:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin3!goblin1!goblin.stu.neva.ru!oe3no6196292lbb.1!news-out.google.com!di11ni9897lbb.1!nntp.google.com!w10no4396747lbo.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 20 Jun 2016 10:16:27 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> <0edaea93-6a16-4d8a-83c6-898283629d11@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4eaf387b-fbb0-4cfc-97d9-1d8429d02fb6@googlegroups.com> Subject: Re: GALs and VHDL From: silverdr Injection-Date: Mon, 20 Jun 2016 17:16:28 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4465 On Friday, 17 June 2016 00:06:07 UTC+2, rickman wrote: > On 6/16/2016 5:45 PM, silverdr wrote: > > On Thursday, 16 June 2016 19:06:04 UTC+2, rickman wrote: > > > >>>> Have you checked for licensing issues? > >>> > >>> Maybe I don't know how but I haven't noticed anything about licensing= . I can view the EULA (from 2012 - not so old) and nothing complains about = licensing. > >> > >> I don't know for sure, but Synplicity should need a license to run. I > >> seem to recall when my license expires I get an exit error of 2. Chec= k > >> the Lattice web site to see what they say about licensing this tool. > > > > I just tried something else - instead of trying to compile VHDL, for te= sting purposes I entered a simple schematic of two gates and went that rout= e. Seems that I can get through the process up to a JEDEC file. So it hopef= ully means that Synplify is properly licensed. Unless I miss something here= . >=20 > How does schematic work? To be frank - I've got no idea. But the flow presented by the software seem= different. > Do they produce an EDIF file from that which=20 > Synplicity processes? I can't find any .EDI file in the project directory so either they don't or= they delete it after use. Probably the former. Yet my VHDL project didn't = create any either - due to the error.. From newsfish@newsfish Thu Aug 1 00:37:12 2024 X-Received: by 10.28.29.150 with SMTP id d144mr2013578wmd.0.1466443643168; Mon, 20 Jun 2016 10:27:23 -0700 (PDT) X-Received: by 10.36.36.133 with SMTP id f127mr299241ita.2.1466443643050; Mon, 20 Jun 2016 10:27:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin3!goblin1!goblin.stu.neva.ru!w10no4409309lbo.0!news-out.google.com!di11ni9970lbb.1!nntp.google.com!w10no4409302lbo.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 20 Jun 2016 10:27:22 -0700 (PDT) In-Reply-To: <4eaf387b-fbb0-4cfc-97d9-1d8429d02fb6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> <0edaea93-6a16-4d8a-83c6-898283629d11@googlegroups.com> <4eaf387b-fbb0-4cfc-97d9-1d8429d02fb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <71b6bd03-34ec-4584-ae7c-c63434068a3b@googlegroups.com> Subject: Re: GALs and VHDL From: silverdr Injection-Date: Mon, 20 Jun 2016 17:27:23 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4466 On Monday, 20 June 2016 19:16:29 UTC+2, silverdr wrote: > > How does schematic work? > > To be frank - I've got no idea. But the flow presented by the software seem different. My "Pure VHDL" project https://dl.dropboxusercontent.com/u/58002657/r512_purevhdl.png Schematic based project. https://dl.dropboxusercontent.com/u/58002657/r512_schematicvhdl.png From newsfish@newsfish Thu Aug 1 00:37:13 2024 X-Received: by 10.28.203.135 with SMTP id b129mr711748wmg.5.1466443910550; Mon, 20 Jun 2016 10:31:50 -0700 (PDT) X-Received: by 10.36.113.199 with SMTP id n190mr298963itc.0.1466443910368; Mon, 20 Jun 2016 10:31:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!w10no4414540lbo.0!news-out.google.com!f5ni20078lbb.0!nntp.google.com!oe3no6214065lbb.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 20 Jun 2016 10:31:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.238.169.98; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 104.238.169.98 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: GALs and VHDL From: silverdr Injection-Date: Mon, 20 Jun 2016 17:31:50 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4467 On Monday, 20 June 2016 19:14:27 UTC+2, rickman wrote: > > Tried and re-licenced the software - the licence.dat contains all the packages, including Syn stuff. So this shouldn't (at least theoretically) be the cause. > > If the tool has a button for firing up the simulator without doing a > compile (the Diamond and iCE40 tools do) see if you can bring up the > GUI. If you can, the license is good. The closest I can think of are the menu entries named "Waveform editor" and "Waveform viewer". Both pop up normally. From newsfish@newsfish Thu Aug 1 00:37:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: GALs and VHDL Date: Mon, 20 Jun 2016 14:21:40 -0400 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <1b509cd9-2b64-4da4-be5c-c97de4336c30@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 20 Jun 2016 18:21:39 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="28881"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ado6fO0wLlMewOsxW18OL" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Cancel-Lock: sha1:LgbQ2jw2mA59KDrq1y/LengQ9sI= Xref: news.eternal-september.org comp.lang.vhdl:4468 On 6/20/2016 1:31 PM, silverdr wrote: > On Monday, 20 June 2016 19:14:27 UTC+2, rickman wrote: > >>> Tried and re-licenced the software - the licence.dat contains all the packages, including Syn stuff. So this shouldn't (at least theoretically) be the cause. >> >> If the tool has a button for firing up the simulator without doing a >> compile (the Diamond and iCE40 tools do) see if you can bring up the >> GUI. If you can, the license is good. > > The closest I can think of are the menu entries named "Waveform editor" and "Waveform viewer". Both pop up normally. Sorry, I should have said "synthesis", not simulator. They are separate with separate licenses. All the tools I use let you fire up the synthesis software separate from the Lattice GUI. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:13 2024 X-Received: by 10.157.1.79 with SMTP id 73mr6494929otu.47.1466813232604; Fri, 24 Jun 2016 17:07:12 -0700 (PDT) X-Received: by 10.36.227.7 with SMTP id d7mr729181ith.3.1466729177371; Thu, 23 Jun 2016 17:46:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!jk6no628334igb.0!news-out.google.com!d62ni13504ith.0!nntp.google.com!r1no635762ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 23 Jun 2016 17:46:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=1.136.96.209; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 1.136.96.209 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <504f4176-b698-4202-830d-833d292d8bf6@googlegroups.com> Subject: =?UTF-8?Q?Will_Work_for_H=C3=A4agen=2DDazs?= From: Leonardo Injection-Date: Sat, 25 Jun 2016 00:07:12 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4469 Hi! Hope you have a speedy recovery. Well, I am always searching for a friend to help investigate future/current MIPI standards and their implementation in FPGA. Namely: MPHY, CPHY and UniPRO. Interested? Thanks, Leo From newsfish@newsfish Thu Aug 1 00:37:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: =?UTF-8?Q?Re:_Will_Work_for_H=c3=a4agen-Dazs?= Date: Sat, 25 Jun 2016 00:36:00 -0400 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <504f4176-b698-4202-830d-833d292d8bf6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 25 Jun 2016 04:36:00 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="23171"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199S8A/NV6xr27LITce4248" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <504f4176-b698-4202-830d-833d292d8bf6@googlegroups.com> Cancel-Lock: sha1:XsDonZt4HGu85Uqp62FDPeF7f4M= Xref: news.eternal-september.org comp.lang.vhdl:4470 On 6/23/2016 8:46 PM, Leonardo wrote: > Hi! > > Hope you have a speedy recovery. Well, I am always searching for a friend to help investigate future/current MIPI standards and their implementation in FPGA. Namely: MPHY, CPHY and UniPRO. Interested? > > Thanks, > Leo Interesting. Why do you need someone else to do this? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:14 2024 X-Received: by 10.176.4.81 with SMTP id 75mr6906112uav.0.1466830295591; Fri, 24 Jun 2016 21:51:35 -0700 (PDT) X-Received: by 10.36.103.134 with SMTP id u128mr43554itc.5.1466830295546; Fri, 24 Jun 2016 21:51:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!jk6no1362956igb.0!news-out.google.com!d62ni14001ith.0!nntp.google.com!r1no1374282ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Jun 2016 21:51:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.221.110.113; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 203.221.110.113 References: <504f4176-b698-4202-830d-833d292d8bf6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <44806a13-6090-4a72-bf2c-bb5aa5c1f91f@googlegroups.com> Subject: =?UTF-8?Q?Re=3A_Will_Work_for_H=C3=A4agen=2DDazs?= From: Leonardo Injection-Date: Sat, 25 Jun 2016 04:51:35 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4471 El s=C3=A1bado, 25 de junio de 2016, 14:36:03 (UTC+10), rickman escribi=C3= =B3: > On 6/23/2016 8:46 PM, Leonardo wrote: > > Hi! > > > > Hope you have a speedy recovery. Well, I am always searching for a frie= nd to help investigate future/current MIPI standards and their implementati= on in FPGA. Namely: MPHY, CPHY and UniPRO. Interested? > > > > Thanks, > > Leo >=20 > Interesting. Why do you need someone else to do this? >=20 > --=20 >=20 > Rick C I don't need someone else to do this. In fact there is no need for me to do= this. It would be good for anyone that is reasearching this on their own to share= info about possible ways to implement future MIPI solutions. As of now I o= nly have an interest in it, and don't have any way of getting the required = documents to begin thinking about an actual implementation of this emerging= technologies. The question would be: In the myriad of FPGAs that are available for the general public to get, is= it feasible to implement an MPHY or a CPHY ? (I already know how to have a= design with a DPHY). What would the challenges be? From newsfish@newsfish Thu Aug 1 00:37:14 2024 X-Received: by 10.36.73.170 with SMTP id e42mr15646884itd.4.1467101570905; Tue, 28 Jun 2016 01:12:50 -0700 (PDT) X-Received: by 10.36.230.69 with SMTP id e66mr333906ith.0.1467101570846; Tue, 28 Jun 2016 01:12:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!jk6no4879175igb.0!news-out.google.com!o189ni6652ith.0!nntp.google.com!r1no4901743ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Jun 2016 01:12:50 -0700 (PDT) In-Reply-To: <5ce9ee05-819d-4b64-adb4-ccede0102c6b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.29.160.247; posting-account=ln0b3QoAAAByFwaOSiLdXPz4b8TZko_k NNTP-Posting-Host: 194.29.160.247 References: <5ce9ee05-819d-4b64-adb4-ccede0102c6b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: AXI4-Lite, Avalon-MM, UART, I2C and SPI: VHDL BFMs and VVCs for free - and open source From: Adrian Byszuk Injection-Date: Tue, 28 Jun 2016 08:12:50 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4472 Hello Espen, UVVM looks really nice to me. I've started playing with AXI4Lite BFM and I really like it. One addition I would like to see is configurable assertion time for BREADY and RREADY signals, in similar way it's possible for *VALID signals (e.g. config.num_w_pipe_stages). Other than that, do you plan to support Wishbone protocol? It's fairly widespread, especially in open projects. Thanks, Adrian From newsfish@newsfish Thu Aug 1 00:37:14 2024 X-Received: by 10.107.19.144 with SMTP id 16mr7066892iot.0.1467188033272; Wed, 29 Jun 2016 01:13:53 -0700 (PDT) X-Received: by 10.36.110.134 with SMTP id w128mr1009itc.3.1467188033194; Wed, 29 Jun 2016 01:13:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r1no6115933ige.0!news-out.google.com!o189ni9828ith.0!nntp.google.com!r1no6115926ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Jun 2016 01:13:52 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 References: <5ce9ee05-819d-4b64-adb4-ccede0102c6b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: AXI4-Lite, Avalon-MM, UART, I2C and SPI: VHDL BFMs and VVCs for free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Wed, 29 Jun 2016 08:13:53 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4473 Hi Adrian, Good to hear you like it :-) Have you tried the VVC variants yet? Using a VVC is as easy as using a BFM (just add the given VVC target name a= s the first parameter). The VVC allows a very structured, simple and automa= tic simultaneous control of multiple interfaces, so you don't have to contr= ol different verification processes or entities "manually". At the moment we have no resources to make these changes, as vacation is co= ming up and we need to prioritise other features on our UVVM roadmap. We do hope that the Open Source VHDL community will embrace UVVM and make n= ew and improved VVCs/BFMs available, so maybe this is a great opportunity t= o get started. (Maybe we should ask for that in a dedicated post...) Otherwise I guess we could make the AXI4Lite improvements some time in Q3 o= r Q4, and maybe also a Wishbone classic VVC/BFM, but we need to evaluate ou= r priorities based on our roadmap and user requests. -Espen From newsfish@newsfish Thu Aug 1 00:37:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: VHDL's Evil Obsession with Static Expressions Date: Thu, 7 Jul 2016 15:39:32 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 7 Jul 2016 19:39:33 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="22448"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IguYA69IMZozypJd+HlFe" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:7yluli337TcFWk3i6A7LxlNbexE= Xref: news.eternal-september.org comp.lang.vhdl:4474 The following line of code where PhA, PhB, PhA_Old and PhB_Old are all std_logic CASE std_logic_vector'(PhA & PhB & PhA_Old & PhB_Old) IS produces the following warning. subtype of case expression is not locally static I've played with this and keep getting an error of one type or another so I consider a warning to at least be a partial victory. ;) I am not getting what is wrong with this. The old "not locally static" or "not globally static" expression thing seems to kick my butt a lot. What do they mean "subtype"??? Is that because the vector is constrained while the type SLV is unconstrained? Why is this not locally static? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: VHDL's Evil Obsession with Static Expressions Date: Thu, 7 Jul 2016 20:32:31 -0000 (UTC) Organization: A noiseless patient Spider Lines: 36 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Thu, 7 Jul 2016 20:32:31 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="809df500543e3a7eaa0b56650623de8b"; logging-data="2461"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19YUNMgp7RWRe06LvXWxzo6" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:8vWvV21zIa7WduaX+Wqi2yj4XxQ= Xref: news.eternal-september.org comp.lang.vhdl:4475 rickman wrote: > The following line of code where PhA, PhB, PhA_Old and PhB_Old are all > std_logic > > CASE std_logic_vector'(PhA & PhB & PhA_Old & PhB_Old) IS > > produces the following warning. > > subtype of case expression is not locally static > > I've played with this and keep getting an error of one type or another > so I consider a warning to at least be a partial victory. ;) > > I am not getting what is wrong with this. The old "not locally static" > or "not globally static" expression thing seems to kick my butt a lot. > > What do they mean "subtype"??? Is that because the vector is > constrained while the type SLV is unconstrained? Why is this not > locally static? > Can't tell you why it's wrong, but I can probably tell you how to fix it. variable casethejoint : std_logic_vector(3 downto 0); ... casethejoint := PhA & PhB & PhA_Old & PhB_Old; case casethejoint is -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:37:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL's Evil Obsession with Static Expressions Date: Thu, 7 Jul 2016 16:39:17 -0400 Organization: A noiseless patient Spider Lines: 45 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 7 Jul 2016 20:39:17 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="2642"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/GImcDU2ycfnTlDR3z5VKx" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:RIqSzEn4ff+0r+IIXYOCACgToKE= Xref: news.eternal-september.org comp.lang.vhdl:4476 On 7/7/2016 4:32 PM, Rob Gaddi wrote: > rickman wrote: > >> The following line of code where PhA, PhB, PhA_Old and PhB_Old are all >> std_logic >> >> CASE std_logic_vector'(PhA & PhB & PhA_Old & PhB_Old) IS >> >> produces the following warning. >> >> subtype of case expression is not locally static >> >> I've played with this and keep getting an error of one type or another >> so I consider a warning to at least be a partial victory. ;) >> >> I am not getting what is wrong with this. The old "not locally static" >> or "not globally static" expression thing seems to kick my butt a lot. >> >> What do they mean "subtype"??? Is that because the vector is >> constrained while the type SLV is unconstrained? Why is this not >> locally static? >> > > Can't tell you why it's wrong, but I can probably tell you how to fix > it. > > variable casethejoint : std_logic_vector(3 downto 0); > > .... > > casethejoint := PhA & PhB & PhA_Old & PhB_Old; > case casethejoint is Yes, I'm sure that will work, but I hate the verbosity, defining temporary variables that make the code less readable rather than more readable. VHDL-2008 was a big step forward in reducing verbosity and making core more readable. I'm still learning how to use it though. Sometimes I wonder about VHDL and whether I should just bite the bullet and learn Verilog. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:16 2024 X-Received: by 10.157.12.206 with SMTP id o14mr7117991otd.33.1468017752326; Fri, 08 Jul 2016 15:42:32 -0700 (PDT) X-Received: by 10.36.39.83 with SMTP id g80mr408412ita.2.1468017752292; Fri, 08 Jul 2016 15:42:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r1no14287182ige.0!news-out.google.com!d130ni704ith.0!nntp.google.com!r1no14287178ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 Jul 2016 15:42:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.27.165; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.27.165 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL's Evil Obsession with Static Expressions From: diogratia@gmail.com Injection-Date: Fri, 08 Jul 2016 22:42:32 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4477 On Friday, July 8, 2016 at 8:39:19 AM UTC+12, rickman wrote: > > VHDL-2008 was a big step forward in reducing verbosity and making core > more readable. I'm still learning how to use it though. Sometimes I > wonder about VHDL and whether I should just bite the bullet and learn > Verilog. A subtype is a type and a constraint, in this case an index constraint. There are no VHDL language defined warnings and the requirement is that a case expression have a locally static subtype. In your original example std_logic_vector is an unconstrained type (or subtype for -2008). A different solution and an explanation might help to understand VHDL a bit better. This is also legal: library ieee; use ieee.std_logic_1164.all; entity evil is end entity; architecture obsession of evil is signal PhA, PhB, PhA_old, PhB_old: std_logic; -- type necessary_evil is array (3 downto 0) of std_ulogic; -- also legal subtype necessary_evil is std_logic_vector(3 downto 0); begin process (PhA, PhB, PhA_old, PhB_old) begin -- case std_logic_vector'(PhA & PhB & PhA_old & PhB_old) is case necessary_evil'(PhA & PhB & PhA_old & PhB_old) is when others => end case; end process; end architecture; This solution provides a subtype constraint, as does Rob's example using a variable, whose declaration provides a subtype indication (an index constraint). So why is the requirement there (and what is the requirement)? IEEE Std 1076-2008 10.9 Case statement para 1: A case statement selects for execution one of a number of alternative sequences of statements; the chosen alternative is defined by the value of an expression. para 4: The expression shall be of a discrete type or of a one-dimensional array type whose element base type is a character type. This type shall be determined by applying the rules of 12.5 to the expression considered as a complete context, using the rule that the expression shall be of a discrete type or a one-dimensional character array type. (In particular, the type of the case expression must be determinable independent of the type of the case statement choices.) It is an error if the type of the expression in a matching case statement is other than BIT, STD_ULOGIC, or a one-dimensional array type whose element type is BIT or STD_ULOGIC. Each choice in a case statement alternative shall be of the same type as the expression; the list of choices specifies for which values of the expression the alternative is chosen. para 5: For an ordinary case statement, or for a matching case statement in which the expression is of type BIT or an array type whose element type is BIT, if the expression is the name of an object whose subtype is locally static, whether a scalar type or an array type, then each value of the subtype shall be represented once and only once in the set of choices of the case statement, and no other value is allowed; this rule is likewise applied if the expression is a qualified expression or type conversion whose type mark denotes a locally static subtype, or if the expression is a call to a function whose return type mark denotes a locally static subtype, or if the expression is an expression described in this paragraph and enclosed in parentheses. -- So the requirement is the subtype of the expression PhA & PhB & PhA_old & PhB_old is locally static and determinable other than by choice context. This is demonstrated in the legal solution above by having only one choice, others. There is no context that can provide the subtype even should you subscribe to the notion the case statement should be evaluated in multiple passes to determine the subtype. The idea here is that the legality of a choice can be determined at analysis time. In your original the error message we see is ghdl -a necessary_evil.vhdl necessary_evil.vhdl:14:14: type mark is not a locally static subtype ghdl: compilation error Where line 14:14 is your original case expression uncommented. So why can't the subtype be taken from the case expression? The qualified expression Rick C provided stating the type mark is std_logic_vector doesn't provide a subtype constraint. And about here we get the idea that evaluating thel legality of a choice is accomplished by referencing the subtype constraint of the case expression (an unnamed object). That subtype constraint isn't available with a qualified expression using a type mark that is unconstrained. An expression can be of arbitrary complexity and something like F unction Knows Vector Size is practically intractable. A little investigation shows the subtype of a function return value is not declared and all predefined operators ("&") are implemented as pure functions. From newsfish@newsfish Thu Aug 1 00:37:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL's Evil Obsession with Static Expressions Date: Fri, 8 Jul 2016 22:43:10 -0400 Organization: A noiseless patient Spider Lines: 131 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 9 Jul 2016 02:43:10 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="12920"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18BCOVW9YJQlQiICy+fjBbt" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:OmJMTNgbdD39vF11Ma5GtKGTTRE= Xref: news.eternal-september.org comp.lang.vhdl:4478 On 7/8/2016 6:42 PM, diogratia@gmail.com wrote: > On Friday, July 8, 2016 at 8:39:19 AM UTC+12, rickman wrote: > >> >> VHDL-2008 was a big step forward in reducing verbosity and making core >> more readable. I'm still learning how to use it though. Sometimes I >> wonder about VHDL and whether I should just bite the bullet and learn >> Verilog. > > A subtype is a type and a constraint, in this case an index constraint. > > There are no VHDL language defined warnings and the requirement is that a case > expression have a locally static subtype. In your original example > std_logic_vector is an unconstrained type (or subtype for -2008). > > A different solution and an explanation might help to understand VHDL a bit > better. > > This is also legal: > > library ieee; > use ieee.std_logic_1164.all; > > entity evil is > end entity; > > architecture obsession of evil is > signal PhA, PhB, PhA_old, PhB_old: std_logic; > -- type necessary_evil is array (3 downto 0) of std_ulogic; -- also legal > subtype necessary_evil is std_logic_vector(3 downto 0); > begin > process (PhA, PhB, PhA_old, PhB_old) > begin > -- case std_logic_vector'(PhA & PhB & PhA_old & PhB_old) is > case necessary_evil'(PhA & PhB & PhA_old & PhB_old) is > when others => > end case; > end process; > end architecture; > > This solution provides a subtype constraint, as does Rob's example using a > variable, whose declaration provides a subtype indication (an index constraint). > > So why is the requirement there (and what is the requirement)? > > IEEE Std 1076-2008 10.9 Case statement > > para 1: > > A case statement selects for execution one of a number of alternative sequences > of statements; the chosen alternative is defined by the value of an expression. > > para 4: > > The expression shall be of a discrete type or of a one-dimensional array type > whose element base type is a character type. This type shall be determined by > applying the rules of 12.5 to the expression considered as a complete context, > using the rule that the expression shall be of a discrete type or a > one-dimensional character array type. (In particular, the type of the case > expression must be determinable independent of the type of the case statement > choices.) It is an error if the type of the expression in a matching case > statement is other than BIT, STD_ULOGIC, or a one-dimensional array type whose > element type is BIT or STD_ULOGIC. Each choice in a case statement alternative > shall be of the same type as the expression; the list of choices specifies for > which values of the expression the alternative is chosen. > > para 5: > > For an ordinary case statement, or for a matching case statement in which the > expression is of type BIT or an array type whose element type is BIT, if the > expression is the name of an object whose subtype is locally static, whether a > scalar type or an array type, then each value of the subtype shall be > represented once and only once in the set of choices of the case statement, and > no other value is allowed; this rule is likewise applied if the expression is a > qualified expression or type conversion whose type mark denotes a locally > static subtype, or if the expression is a call to a function whose return type > mark denotes a locally static subtype, or if the expression is an expression > described in this paragraph and enclosed in parentheses. > > -- > > So the requirement is the subtype of the expression PhA & PhB & PhA_old & > PhB_old is locally static and determinable other than by choice context. This > is demonstrated in the legal solution above by having only one choice, others. > There is no context that can provide the subtype even should you subscribe to > the notion the case statement should be evaluated in multiple passes to > determine the subtype. > > The idea here is that the legality of a choice can be determined at analysis > time. > > In your original the error message we see is > > ghdl -a necessary_evil.vhdl > necessary_evil.vhdl:14:14: type mark is not a locally static subtype > ghdl: compilation error > > Where line 14:14 is your original case expression uncommented. > > So why can't the subtype be taken from the case expression? The qualified > expression Rick C provided stating the type mark is std_logic_vector doesn't > provide a subtype constraint. > > And about here we get the idea that evaluating thel legality of a choice is > accomplished by referencing the subtype constraint of the case expression (an > unnamed object). That subtype constraint isn't available with a qualified > expression using a type mark that is unconstrained. > > An expression can be of arbitrary complexity and something like href="http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/FunctionKnowsVectorSize">F > unction Knows Vector Size is practically intractable. > > A little investigation shows the subtype of a function return value is not > declared and all predefined operators ("&") are implemented as pure functions. That was a lot to digest... but I believe the crux is that the range of the SLV needs to be defined. Knowing it has four elements is not good enough. That brings me back to, "why"? VHDL seems to have a great many restrictions that are of no purpose. The designers developed a framework and designed a language within this framework which gave it a variety of restrictions that are of little "real world" value. I don't see the value in making VHDL as complex as it is. I have mostly used VHDL trouble free by sticking with templates of work I have done before. That is so constraining while VHDL should promote creativity. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:16 2024 X-Received: by 10.66.77.137 with SMTP id s9mr11078588paw.33.1468105038229; Sat, 09 Jul 2016 15:57:18 -0700 (PDT) X-Received: by 10.36.28.78 with SMTP id c75mr174979itc.0.1468105038188; Sat, 09 Jul 2016 15:57:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r1no14938278ige.0!news-out.google.com!d68ni2018ith.0!nntp.google.com!jk6no14922218igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Jul 2016 15:57:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.27.165; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.27.165 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <62014f5a-91a7-4fe5-85db-717f3a87227a@googlegroups.com> Subject: Re: VHDL's Evil Obsession with Static Expressions From: diogratia@gmail.com Injection-Date: Sat, 09 Jul 2016 22:57:18 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4479 On Saturday, July 9, 2016 at 2:43:12 PM UTC+12, rickman wrote: > > That was a lot to digest... but I believe the crux is that the range of > the SLV needs to be defined. Knowing it has four elements is not good > enough. How does the analyzer know there are four elements? What it's got is an expression in an abstract syntax tree with four objects and three operators. There are two ways to tell it there are four elements. Assign the expression to a declared object or use a qualified expression providing a subtype. Context has a specific meaning in 10.9 paragraph 4 telling us how much work the analyzer must do. It specifically excludes looking at case statement choices which is the only place a simple expression as a choice can express the subtype (which means length here, an index constraint on the unnamed object that is the value produce by evaluating the simple_expression). That the number of elements doesn't match a choice could be discovered at simulation time executing the case expression and evaluating the choice simple expressions. It unfortunately also implies pushing the legality of choices to being validated in simulation as well. With a locally static subtype that doesn't have to occur avoiding simulation complexity and effort. Also imagine how much harder a time you would have if you only got an error message telling you your case statement was invalid but not what was wrong with it or where to look if you couldn't distinguish unknowns about the case expression and choice simple expression. Simply put the analyzer doesn't have to (and can't) evaluate the case expression. During analysis time signals hold no value they haven't been elaborated. The idea behind having a separate syntax production for a case expression would be to simplify it enough you could extract subtype. There is no limit otherwise to the complexity of an expression. > That brings me back to, "why"? VHDL seems to have a great many > restrictions that are of no purpose. The designers developed a > framework and designed a language within this framework which gave it a > variety of restrictions that are of little "real world" value. VHDL provides a formal notation for writing a formal specification for those parts of a design specification describing hardware. That excludes impure expressions or the use of non-portable constructs. > I don't see the value in making VHDL as complex as it is. I have mostly > used VHDL trouble free by sticking with templates of work I have done > before. That is so constraining while VHDL should promote creativity. The words creative and creativity don't appear in the standard. Creation does ('the action or process of bringing something into existence' as opposed to 'a thing that has been made or invented, especially something showing artistic talent'). Both definitions are embraced by copyright eligibility. Those requirements you find annoying are to create hardware descriptions that are unambiguous, can be concise (not open to interpretation), portable and fit to purpose. Something that would translate a description in another language into VHDL would do the same thing you do - use a subset of language (templates). Rob does that by using an intermediary object, a different template than found in some other (programming) language. The advantages can include making a named object visible in a waveform dump display instead of manually (or mentally) evaluating the case expression. And about here you might discern a distinction in what is being expressed here and why. Changes to the language have added complexity for purposes largely unrelated to creative expression. A mixture of removing ambiguity, adding new features and folding in other related standards. The VHDL standard has gone from 218 pages in 1987 to 630 pages in 2008 while the Verilog standard has gone from 653 pages in 1995 to SystemVerilog's 1315 pages in 2012 (superseding Verilog in 2009). Complexity it seems is in the eye of the beholder. It seems more likely your expectation of what VHDL should provide and the purposes for which it was created are not congruent. From newsfish@newsfish Thu Aug 1 00:37:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL's Evil Obsession with Static Expressions Date: Sun, 10 Jul 2016 00:24:49 -0400 Organization: A noiseless patient Spider Lines: 110 Message-ID: References: <62014f5a-91a7-4fe5-85db-717f3a87227a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 10 Jul 2016 04:24:52 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9b54b534bd1cf4536283fb3de0ec6d02"; logging-data="20069"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19aX/N1MutYQDCaD9Uf4BWr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <62014f5a-91a7-4fe5-85db-717f3a87227a@googlegroups.com> Cancel-Lock: sha1:fYFa/bjCdBpxK/p8YWB+nNKkn68= Xref: news.eternal-september.org comp.lang.vhdl:4480 On 7/9/2016 6:57 PM, diogratia@gmail.com wrote: > On Saturday, July 9, 2016 at 2:43:12 PM UTC+12, rickman wrote: > >> >> That was a lot to digest... but I believe the crux is that the range of >> the SLV needs to be defined. Knowing it has four elements is not good >> enough. > > How does the analyzer know there are four elements? What it's got is an > expression in an abstract syntax tree with four objects and three operators. The operators are concatenation which create a 4 element vector, no? Without a conversion operation I would think this vector would be an SLV. It is obvious this is a four element vector, the only thing missing is the range of the four elements. It could be 0 to 3, 4 downto 1 or anything else. > There are two ways to tell it there are four elements. Assign the expression to > a declared object or use a qualified expression providing a subtype. > > Context has a specific meaning in 10.9 paragraph 4 telling us how much work the > analyzer must do. It specifically excludes looking at case statement choices which is the only place a simple expression as a choice can express the subtype > (which means length here, an index constraint on the unnamed object that is the > value produce by evaluating the simple_expression). > > That the number of elements doesn't match a choice could be discovered at > simulation time executing the case expression and evaluating the choice simple > expressions. It unfortunately also implies pushing the legality of choices to > being validated in simulation as well. With a locally static subtype that > doesn't have to occur avoiding simulation complexity and effort. But the number of elements is four. That part is clear to any observer. > Also imagine how much harder a time you would have if you only got an error > message telling you your case statement was invalid but not what was wrong with > it or where to look if you couldn't distinguish unknowns about the case > expression and choice simple expression. > > Simply put the analyzer doesn't have to (and can't) evaluate the case > expression. During analysis time signals hold no value they haven't been > elaborated. The idea behind having a separate syntax production for a case > expression would be to simplify it enough you could extract subtype. There is > no limit otherwise to the complexity of an expression. > >> That brings me back to, "why"? VHDL seems to have a great many >> restrictions that are of no purpose. The designers developed a >> framework and designed a language within this framework which gave it a >> variety of restrictions that are of little "real world" value. > > VHDL provides a formal notation for writing a formal specification for those > parts of a design specification describing hardware. That excludes impure > expressions or the use of non-portable constructs. > >> I don't see the value in making VHDL as complex as it is. I have mostly >> used VHDL trouble free by sticking with templates of work I have done >> before. That is so constraining while VHDL should promote creativity. > > The words creative and creativity don't appear in the standard. That is my point. Why is VHDL the way it is? Why couldn't it be easier to use? > Creation does ('the action or process of bringing something into existence' as > opposed to 'a thing that has been made or invented, especially something > showing artistic talent'). Both definitions are embraced by copyright > eligibility. Mazel tov. > Those requirements you find annoying are to create hardware descriptions that > are unambiguous, can be concise (not open to interpretation), portable and fit > to purpose. Concise? That is the issue at hand. It doesn't appear concise. > Something that would translate a description in another language into VHDL > would do the same thing you do - use a subset of language (templates). Rob does > that by using an intermediary object, a different template than found in some > other (programming) language. The advantages can include making a named object > visible in a waveform dump display instead of manually (or mentally) evaluating > the case expression. And about here you might discern a distinction in what is > being expressed here and why. > > Changes to the language have added complexity for purposes largely unrelated to > creative expression. A mixture of removing ambiguity, adding new features and > folding in other related standards. Recent changes have often improved "conciseness". A few more such changes would be useful. > The VHDL standard has gone from 218 pages in 1987 to 630 pages in 2008 while > the Verilog standard has gone from 653 pages in 1995 to SystemVerilog's 1315 > pages in 2012 (superseding Verilog in 2009). > > Complexity it seems is in the eye of the beholder. It seems more likely your > expectation of what VHDL should provide and the purposes for which it was > created are not congruent. Perhaps, very few things in life are congruent. I see opportunity for VHDL to be more useful. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!buffer1.nntp.dca1.giganews.com!buffer2.nntp.dca1.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 11 Jul 2016 23:52:14 -0500 From: Nicholas Randall Forystek Newsgroups: comp.lang.vhdl Subject: ............................................................ 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From newsfish@newsfish Thu Aug 1 00:37:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!buffer2.nntp.dca1.giganews.com!buffer1.nntp.dca1.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 12 Jul 2016 08:17:47 -0500 From: Nicholas Randall Forystek Newsgroups: comp.lang.vhdl Subject: ............................................................ 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From newsfish@newsfish Thu Aug 1 00:37:18 2024 X-Received: by 10.31.96.137 with SMTP id u131mr2355611vkb.10.1468340116079; Tue, 12 Jul 2016 09:15:16 -0700 (PDT) X-Received: by 10.36.196.5 with SMTP id v5mr269876itf.4.1468340116040; Tue, 12 Jul 2016 09:15:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j37no916623qta.0!news-out.google.com!d130ni487ith.0!nntp.google.com!jk6no21304412igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Jul 2016 09:15:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.196.139.197; posting-account=b54qBQoAAADfu9LrlQEqlZu99hjm7ayM NNTP-Posting-Host: 81.196.139.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: RS LATCH VHDL STRUCTURAL MODEL From: Pavel-Ioan Duta Injection-Date: Tue, 12 Jul 2016 16:15:16 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4483 Hello, I'm new to this group and VHDL too. I'm trying to simulate an RS latch using structural model but with no luck. My code is the following: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ENTITY RSLATCH IS PORT(R,S : IN BIT; Q,NQ : BUFFER BIT); END RSLATCH; ARCHITECTURE NETLIST OF RSLATCH IS COMPONENT NOR2 PORT(a,b : IN BIT; c : OUT BIT); END COMPONENT; BEGIN U1 : NOR2 PORT MAP(R,NQ,Q); U2 : NOR2 PORT MAP(Q,S,NQ); END NETLIST; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ I had compiled the code with success, but when im forcing the R or the S signal, my outputs (Q, NQ) aren't changing. Could somebody help me in this matter, please? Thank you in advance! From newsfish@newsfish Thu Aug 1 00:37:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: RS LATCH VHDL STRUCTURAL MODEL Date: Tue, 12 Jul 2016 16:54:03 -0000 (UTC) Organization: A noiseless patient Spider Lines: 76 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Tue, 12 Jul 2016 16:54:03 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="809df500543e3a7eaa0b56650623de8b"; logging-data="21230"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18g9Qcbz8zBc3iJMl2Dw9zo" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:ESzSxvw01EqHZ0E3jo2f6XHhGZY= Xref: news.eternal-september.org comp.lang.vhdl:4484 Pavel-Ioan Duta wrote: > Hello, > > I'm new to this group and VHDL too. I'm trying to simulate an RS latch using structural model but with no luck. My code is the following: > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > ENTITY RSLATCH IS > > PORT(R,S : IN BIT; Q,NQ : BUFFER BIT); > > END RSLATCH; > > ARCHITECTURE NETLIST OF RSLATCH IS > > COMPONENT NOR2 > > PORT(a,b : IN BIT; c : OUT BIT); > > END COMPONENT; > > BEGIN > > U1 : NOR2 > > PORT MAP(R,NQ,Q); > > U2 : NOR2 > > PORT MAP(Q,S,NQ); > > END NETLIST; > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > I had compiled the code with success, but when im forcing the R or the S signal, my outputs (Q, NQ) aren't changing. Could somebody help me in this matter, please? Thank you in advance! Is the NOR2 something that you have a definition for somewhere? Also, no one would write that code that way any time in the last 20 years. BIT is deeply out of fashion, and structural definitions of basic logic blocks are a grossly overcomplicated approach. Even defining an RS latch is a pretty low-level thing (though I've needed it myself), but if you were going to do it you'd do it like: library ieee; use ieee.std_logic_1164.all; entity RSLATCH is port ( R, S : in std_logic; Q, NQ : out std_logic ); end entity RSLATCH; architecture Behavioral of RSLATCH is begin LATCH: process(R, S) variable state : std_logic; begin if (R = '1') then state := '0'; elsif (S = '1') then state := '1'; end if; Q <= state; NQ <= not state; end process LATCH; end architecture Behavioral; -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:37:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: RS LATCH VHDL STRUCTURAL MODEL Date: Tue, 12 Jul 2016 13:28:28 -0400 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 12 Jul 2016 17:28:30 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="29324"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18sioZ4TAJJI/qxAHehFwpm" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:YXTXlX5huy5SuOGDNzxmrKdWDps= Xref: news.eternal-september.org comp.lang.vhdl:4485 On 7/12/2016 12:15 PM, Pavel-Ioan Duta wrote: > Hello, > > I'm new to this group and VHDL too. I'm trying to simulate an RS latch using structural model but with no luck. My code is the following: > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > ENTITY RSLATCH IS > > PORT(R,S : IN BIT; Q,NQ : BUFFER BIT); > > END RSLATCH; > > ARCHITECTURE NETLIST OF RSLATCH IS > > COMPONENT NOR2 > > PORT(a,b : IN BIT; c : OUT BIT); > > END COMPONENT; > > BEGIN > > U1 : NOR2 > > PORT MAP(R,NQ,Q); > > U2 : NOR2 > > PORT MAP(Q,S,NQ); > > END NETLIST; > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > I had compiled the code with success, but when im forcing the R or the S signal, my outputs (Q, NQ) aren't changing. Could somebody help me in this matter, please? Thank you in advance! I don't see anything wrong with your code off the top of my head. The use of "buffer" is unusual, in fact, I didn't know buffer existed until now. But it should work, certainly in simulation.... except that you are connecting it to an output of the NOR2 component. I read that if buffer is used, it must be used at all levels of the hierarchy. If you can enable VHDL-2008 in your tools, you can do the same thing with OUT that you are doing with BUFFER without the complications. What simulator are you using? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:19 2024 X-Received: by 10.107.182.139 with SMTP id g133mr3124584iof.28.1468344833587; Tue, 12 Jul 2016 10:33:53 -0700 (PDT) X-Received: by 10.36.3.85 with SMTP id e82mr327243ite.1.1468344833349; Tue, 12 Jul 2016 10:33:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!jk6no21368225igb.0!news-out.google.com!d68ni5306ith.0!nntp.google.com!jk6no21368222igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Jul 2016 10:33:52 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.196.139.197; posting-account=b54qBQoAAADfu9LrlQEqlZu99hjm7ayM NNTP-Posting-Host: 81.196.139.197 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: RS LATCH VHDL STRUCTURAL MODEL From: Pavel-Ioan Duta Injection-Date: Tue, 12 Jul 2016 17:33:53 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4486 On Tuesday, July 12, 2016 at 7:54:05 PM UTC+3, Rob Gaddi wrote: > Pavel-Ioan Duta wrote: > > > Hello, > > > > I'm new to this group and VHDL too. I'm trying to simulate an RS latch using structural model but with no luck. My code is the following: > > > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > ENTITY RSLATCH IS > > > > PORT(R,S : IN BIT; Q,NQ : BUFFER BIT); > > > > END RSLATCH; > > > > ARCHITECTURE NETLIST OF RSLATCH IS > > > > COMPONENT NOR2 > > > > PORT(a,b : IN BIT; c : OUT BIT); > > > > END COMPONENT; > > > > BEGIN > > > > U1 : NOR2 > > > > PORT MAP(R,NQ,Q); > > > > U2 : NOR2 > > > > PORT MAP(Q,S,NQ); > > > > END NETLIST; > > > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > I had compiled the code with success, but when im forcing the R or the S signal, my outputs (Q, NQ) aren't changing. Could somebody help me in this matter, please? Thank you in advance! > > Is the NOR2 something that you have a definition for somewhere? > > Also, no one would write that code that way any time in the last 20 > years. BIT is deeply out of fashion, and structural definitions of > basic logic blocks are a grossly overcomplicated approach. Even > defining an RS latch is a pretty low-level thing (though I've needed it > myself), but if you were going to do it you'd do it like: > > library ieee; > use ieee.std_logic_1164.all; > > entity RSLATCH is > port ( > R, S : in std_logic; > Q, NQ : out std_logic > ); > end entity RSLATCH; > > architecture Behavioral of RSLATCH is > begin > > LATCH: process(R, S) > variable state : std_logic; > begin > if (R = '1') then > state := '0'; > elsif (S = '1') then > state := '1'; > end if; > Q <= state; > NQ <= not state; > end process LATCH; > > end architecture Behavioral; > > -- > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > > Email address domain is currently out of order. See above to fix. Thank you so much for your help! So it's seems that my VHDL book source is "a little bit" outdated. Could you please provide me an updated VHDL source for a beginner like me? From newsfish@newsfish Thu Aug 1 00:37:19 2024 X-Received: by 10.157.58.55 with SMTP id j52mr2695571otc.4.1468345470845; Tue, 12 Jul 2016 10:44:30 -0700 (PDT) X-Received: by 10.36.39.83 with SMTP id g80mr41865ita.2.1468345470786; Tue, 12 Jul 2016 10:44:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!jk6no21374831igb.0!news-out.google.com!d68ni5313ith.0!nntp.google.com!hy1no32076igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Jul 2016 10:44:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.196.139.197; posting-account=b54qBQoAAADfu9LrlQEqlZu99hjm7ayM NNTP-Posting-Host: 81.196.139.197 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4eaee18f-f871-4f2d-a06c-425a6052bc05@googlegroups.com> Subject: Re: RS LATCH VHDL STRUCTURAL MODEL From: Pavel-Ioan Duta Injection-Date: Tue, 12 Jul 2016 17:44:30 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4487 On Tuesday, July 12, 2016 at 8:28:33 PM UTC+3, rickman wrote: > On 7/12/2016 12:15 PM, Pavel-Ioan Duta wrote: > > Hello, > > > > I'm new to this group and VHDL too. I'm trying to simulate an RS latch using structural model but with no luck. My code is the following: > > > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > ENTITY RSLATCH IS > > > > PORT(R,S : IN BIT; Q,NQ : BUFFER BIT); > > > > END RSLATCH; > > > > ARCHITECTURE NETLIST OF RSLATCH IS > > > > COMPONENT NOR2 > > > > PORT(a,b : IN BIT; c : OUT BIT); > > > > END COMPONENT; > > > > BEGIN > > > > U1 : NOR2 > > > > PORT MAP(R,NQ,Q); > > > > U2 : NOR2 > > > > PORT MAP(Q,S,NQ); > > > > END NETLIST; > > > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > I had compiled the code with success, but when im forcing the R or the S signal, my outputs (Q, NQ) aren't changing. Could somebody help me in this matter, please? Thank you in advance! > > I don't see anything wrong with your code off the top of my head. The > use of "buffer" is unusual, in fact, I didn't know buffer existed until > now. But it should work, certainly in simulation.... except that you > are connecting it to an output of the NOR2 component. I read that if > buffer is used, it must be used at all levels of the hierarchy. > > If you can enable VHDL-2008 in your tools, you can do the same thing > with OUT that you are doing with BUFFER without the complications. What > simulator are you using? > > -- > > Rick C I am using ModelSim. I'we managed to make the code works. I had to define the entity of NOR2 and it's architecture. Here is the final code that works: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ENTITY NOR2 IS PORT(a,b : IN BIT; c : OUT BIT); END ENTITY NOR2; ARCHITECTURE NETLIST_NOR OF NOR2 IS BEGIN c<=a nor b; END ARCHITECTURE NETLIST_NOR; ENTITY RSLATCH IS PORT(R,S : IN BIT; Q,NQ : BUFFER BIT); END ENTITY RSLATCH; ARCHITECTURE NETLIST OF RSLATCH IS COMPONENT NOR2 PORT(a,b : IN BIT; c : OUT BIT); END COMPONENT; BEGIN U1 : NOR2 PORT MAP(R,NQ,Q); U2 : NOR2 PORT MAP(Q,S,NQ); END ARCHITECTURE NETLIST; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ I know there are many ways of doing this latch and i'm a novice on VHDL but even the smallest progress is still a prgress :) From newsfish@newsfish Thu Aug 1 00:37:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: RS LATCH VHDL STRUCTURAL MODEL Date: Tue, 12 Jul 2016 14:05:04 -0400 Organization: A noiseless patient Spider Lines: 124 Message-ID: References: <4eaee18f-f871-4f2d-a06c-425a6052bc05@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 12 Jul 2016 18:05:10 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="5833"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19RaKXknmncD1IU65iKb9ZJ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <4eaee18f-f871-4f2d-a06c-425a6052bc05@googlegroups.com> Cancel-Lock: sha1:JXHuXvONqyg739cBO3zARbba5J4= Xref: news.eternal-september.org comp.lang.vhdl:4488 On 7/12/2016 1:44 PM, Pavel-Ioan Duta wrote: > On Tuesday, July 12, 2016 at 8:28:33 PM UTC+3, rickman wrote: >> On 7/12/2016 12:15 PM, Pavel-Ioan Duta wrote: >>> Hello, >>> >>> I'm new to this group and VHDL too. I'm trying to simulate an RS latch using structural model but with no luck. My code is the following: >>> >>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>> >>> ENTITY RSLATCH IS >>> >>> PORT(R,S : IN BIT; Q,NQ : BUFFER BIT); >>> >>> END RSLATCH; >>> >>> ARCHITECTURE NETLIST OF RSLATCH IS >>> >>> COMPONENT NOR2 >>> >>> PORT(a,b : IN BIT; c : OUT BIT); >>> >>> END COMPONENT; >>> >>> BEGIN >>> >>> U1 : NOR2 >>> >>> PORT MAP(R,NQ,Q); >>> >>> U2 : NOR2 >>> >>> PORT MAP(Q,S,NQ); >>> >>> END NETLIST; >>> >>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>> >>> I had compiled the code with success, but when im forcing the R or the S signal, my outputs (Q, NQ) aren't changing. Could somebody help me in this matter, please? Thank you in advance! >> >> I don't see anything wrong with your code off the top of my head. The >> use of "buffer" is unusual, in fact, I didn't know buffer existed until >> now. But it should work, certainly in simulation.... except that you >> are connecting it to an output of the NOR2 component. I read that if >> buffer is used, it must be used at all levels of the hierarchy. >> >> If you can enable VHDL-2008 in your tools, you can do the same thing >> with OUT that you are doing with BUFFER without the complications. What >> simulator are you using? >> >> -- >> >> Rick C > > I am using ModelSim. I'we managed to make the code works. I had to define the entity of NOR2 and it's architecture. Here is the final code that works: > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > ENTITY NOR2 IS > > PORT(a,b : IN BIT; c : OUT BIT); > > END ENTITY NOR2; > > ARCHITECTURE NETLIST_NOR OF NOR2 IS > BEGIN > > c<=a nor b; > > END ARCHITECTURE NETLIST_NOR; > > ENTITY RSLATCH IS > > PORT(R,S : IN BIT; Q,NQ : BUFFER BIT); > > END ENTITY RSLATCH; > > ARCHITECTURE NETLIST OF RSLATCH IS > > COMPONENT NOR2 > > PORT(a,b : IN BIT; c : OUT BIT); > > END COMPONENT; > > BEGIN > > U1 : NOR2 > > PORT MAP(R,NQ,Q); > > U2 : NOR2 > > PORT MAP(Q,S,NQ); > > END ARCHITECTURE NETLIST; > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > I know there are many ways of doing this latch and i'm a novice on VHDL but even the smallest progress is still a prgress :) This was not so much an exercise in making a latch... as you will find them seldom used. It is more an exercise in using structural VHDL (components). The other way to produce logic is called "inference" which is what Rob wrote for you. The functionality of the logic is described by the code and the tools turn the source into actual gates and registers or whatever functional elements your target chip contains. Both methods are used with the structural part usually being used to connect modules that you have written or provided by the tool (memory for example). In fact, that is what you have done. You use inference to define the functionality of the NOR2 gate, then you connect these gates structurally to create the latch. When I read your original example it didn't occur to me the entity for the NOR2 gate had not been defined elsewhere. They can be defined in another file of similar source code and combined by your tool or in a package which you refer to with a "use" statement, similar to a C language include statement if you are familiar with that. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:20 2024 X-Received: by 10.98.28.133 with SMTP id c127mr4178151pfc.2.1468368122694; Tue, 12 Jul 2016 17:02:02 -0700 (PDT) X-Received: by 10.36.230.194 with SMTP id e185mr206906ith.9.1468368122650; Tue, 12 Jul 2016 17:02:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!jk6no21602223igb.0!news-out.google.com!d130ni895ith.0!nntp.google.com!hy1no258841igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Jul 2016 17:02:02 -0700 (PDT) In-Reply-To: <4eaee18f-f871-4f2d-a06c-425a6052bc05@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:5476:2fdc:c695:be9; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:5476:2fdc:c695:be9 References: <4eaee18f-f871-4f2d-a06c-425a6052bc05@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: RS LATCH VHDL STRUCTURAL MODEL From: KJ Injection-Date: Wed, 13 Jul 2016 00:02:02 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4489 On Tuesday, July 12, 2016 at 1:44:33 PM UTC-4, Pavel-Ioan Duta wrote: >=20 > I know there are many ways of doing this latch and i'm a novice on VHDL b= ut even the smallest progress is still a prgress :) Then here is a little tidbit, don't bother with the component declaration. = Instead you directly instantiate. Where you currently have a component an= d you instantiate like this... > COMPONENT NOR2 PORT(a,b : IN BIT; c : OUT BIT); END COMPONENT;=20 > U1 : NOR2 PORT MAP(R,NQ,Q); > U2 : NOR2 PORT MAP(Q,S,NQ); Instead you can skip the component declaration and instead write it like th= is... > U1 : entity work.NOR2 PORT MAP(R,NQ,Q); > U2 : entity work.NOR2 PORT MAP(Q,S,NQ); As you've probably already noticed, the entity declaration for NOR2 and the= component declaration for NOR2 are nearly identical. Problem occurs when = those two declarations are not identical usually due to some change in one = place that is not reflected in the other. The errors you get from the simu= lator are often not terribly clear when you have this problem. By using direct entity instantiation (i.e. putting 'entity work.' in front = of the NOR2 entity name), you no longer need to have the component declarat= ion. Since now there is only the entity defining the interface, you don't = have to worry about changing the interface in one place and not the other. = Also less code to write. This has nothing to do with modelling an RS flip flop, just a tip on how to= write things better to avoid future problems. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:20 2024 X-Received: by 10.129.121.76 with SMTP id u73mr4104550ywc.2.1468368680507; Tue, 12 Jul 2016 17:11:20 -0700 (PDT) X-Received: by 10.36.20.201 with SMTP id 192mr214228itg.8.1468368680471; Tue, 12 Jul 2016 17:11:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!c52no1310298qte.1!news-out.google.com!d130ni911ith.0!nntp.google.com!hy1no261518igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Jul 2016 17:11:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:5476:2fdc:c695:be9; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:5476:2fdc:c695:be9 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8854ad9a-6948-44a0-912d-5c29e23e3c75@googlegroups.com> Subject: Re: RS LATCH VHDL STRUCTURAL MODEL From: KJ Injection-Date: Wed, 13 Jul 2016 00:11:20 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 23 Xref: news.eternal-september.org comp.lang.vhdl:4490 On Tuesday, July 12, 2016 at 1:28:33 PM UTC-4, rickman wrote: > The=20 > use of "buffer" is unusual, in fact, I didn't know buffer existed until= =20 > now. But it should work, certainly in simulation.... except that you=20 > are connecting it to an output of the NOR2 component. I read that if=20 > buffer is used, it must be used at all levels of the hierarchy. >=20 As far as I know, 'buffer' is generally supported today and has been for so= me time, I've used it for a while. The 'must be used at all levels of the = hierarchy' thing I'm pretty sure were all compiler bugs that eventually wer= e fixed. There used to be a time when one might want to avoid 'buffer' due= to limitations of the tool that you were using, but I think those days are= off in the past. > If you can enable VHDL-2008 in your tools, you can do the same thing=20 > with OUT that you are doing with BUFFER without the complications. Yes, the use of 'out' and 2008 makes 'buffer' now a secondary way of doing = things. So now that you're aware of 'buffer', you can safely forget about = it. The one use case left would be situations where 2008 is not allowed fo= r whatever reason. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:20 2024 X-Received: by 10.36.17.10 with SMTP id 10mr30596273itf.11.1468535778473; Thu, 14 Jul 2016 15:36:18 -0700 (PDT) X-Received: by 10.36.133.10 with SMTP id r10mr1157720itd.1.1468535778451; Thu, 14 Jul 2016 15:36:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!jk6no23080841igb.0!news-out.google.com!d130ni3131ith.0!nntp.google.com!jk6no23080840igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 Jul 2016 15:36:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=179.24.147.251; posting-account=iKewXwoAAABMdzxglOc51qcPJlFEv-hI NNTP-Posting-Host: 179.24.147.251 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46b4cb23-79dd-4d69-856b-431b8d8e04c1@googlegroups.com> Subject: Re: VHDL's Evil Obsession with Static Expressions From: Walter Injection-Date: Thu, 14 Jul 2016 22:36:18 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4491 >Changes to the language have added complexity for purposes largely unrelated to >creative expression. A mixture of removing ambiguity, adding new features and >folding in other related standards. > >The VHDL standard has gone from 218 pages in 1987 to 630 pages in 2008 while >the Verilog standard has gone from 653 pages in 1995 to SystemVerilog's 1315 >pages in 2012 (superseding Verilog in 2009). Since many years I work with FPGA but my first steps with "languages" was in Pascal with an old Apple-II to many years ago. If someone follow the evolutions of Prof. Wirth languages' from Pascal to actual Oberon-07 lot of elegance and simplicity must be appreciated. So, my question, since many years, why HDLs are going into the other sense ? Could be as E.W.Dijkstra say "Simplicity is a great virtue but it requires hard work to achieve it and education to appreciate it. And to make matters worse: complexity sells better." Walter From newsfish@newsfish Thu Aug 1 00:37:21 2024 X-Received: by 10.157.32.78 with SMTP id n72mr14938528ota.40.1468580533008; Fri, 15 Jul 2016 04:02:13 -0700 (PDT) X-Received: by 10.36.53.200 with SMTP id k191mr1531955ita.9.1468580532972; Fri, 15 Jul 2016 04:02:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no399492ith.0!news-out.google.com!d130ni3649ith.0!nntp.google.com!f6no398035ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 Jul 2016 04:02:12 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0cd5ad3e-790f-4acd-9856-af9565597596@googlegroups.com> Subject: How to constrain this array From: David Perry Injection-Date: Fri, 15 Jul 2016 11:02:12 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4492 I have a problem with constraining an array. I have created the array type: type V_array is array (integer range <>) of std_logic_vector(11 downto 0) and created an array: constant V_level_array : V_array := (x"0000",x"0100",x"2000"); so far so good , now the problem: shared variable Vadc_array : V_array; Gives me the error "Variable Vadc_array is not constrained", which is to be expected, but I can't figure out how to constrain it. I want to make it the same size as V_level_array, but I don't want to just put 3 vectors in, I want it to reference the size of V_level_array, but how to do it is eluding me. Any guidance here would be appreciated. From newsfish@newsfish Thu Aug 1 00:37:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: How to constrain this array Date: Fri, 15 Jul 2016 13:45:43 +0200 Lines: 33 Message-ID: References: <0cd5ad3e-790f-4acd-9856-af9565597596@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net UxqwZtM+xlH09DCRkMpECwCwdVZKCcRbW1LXCq8wJ2/VhyIRty Cancel-Lock: sha1:PGKrhZYPLd+HwU2XVpwmbNqbYJ0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.1 In-Reply-To: <0cd5ad3e-790f-4acd-9856-af9565597596@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:4493 Hi, David Perry wrote: > I have a problem with constraining an array. I have created the array > type: > > type V_array is array (integer range <>) of std_logic_vector(11 > downto 0) > > and created an array: > > constant V_level_array : V_array := (x"0000",x"0100",x"2000"); > > so far so good , now the problem: > > shared variable Vadc_array : V_array; > > Gives me the error "Variable Vadc_array is not constrained", which is > to be expected, but I can't figure out how to constrain it. I want to > make it the same size as V_level_array, but I don't want to just put > 3 vectors in, I want it to reference the size of V_level_array, but > how to do it is eluding me. > > Any guidance here would be appreciated. Haven't tested it, but if you change your declaration to shared variable Vadc_array : V_array(V_level_array'range); ... does it work then? HTH, Sean From newsfish@newsfish Thu Aug 1 00:37:22 2024 X-Received: by 10.66.183.229 with SMTP id ep5mr15283567pac.3.1468583523396; Fri, 15 Jul 2016 04:52:03 -0700 (PDT) X-Received: by 10.36.107.7 with SMTP id v7mr1034340itc.10.1468583523189; Fri, 15 Jul 2016 04:52:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no421575ith.0!news-out.google.com!d68ni1451ith.0!nntp.google.com!f6no422899ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 Jul 2016 04:52:02 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: <0cd5ad3e-790f-4acd-9856-af9565597596@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to constrain this array From: David Perry Injection-Date: Fri, 15 Jul 2016 11:52:03 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4494 It syntax checks ok now :) Why are the rules so confusing :( Ta. From newsfish@newsfish Thu Aug 1 00:37:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: How to constrain this array Date: Fri, 15 Jul 2016 15:28:53 +0200 Lines: 76 Message-ID: References: <0cd5ad3e-790f-4acd-9856-af9565597596@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net H2Q7mCaCfCPhwgj4E2ETZAfQKFaz3DVP7Q1IdF3tV+CV0wDfyI Cancel-Lock: sha1:dmXwUCRYbJ3n0gJ4n4CidHA5GHM= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.1 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:4495 David Perry wrote: > It syntax checks ok now :) > Why are the rules so confusing :( It's not really that confusing if you think about it: - type V_array is array (integer range <>) of std_logic_vector(11 downto 0) This defines an unconstrained array with each element being a 12-bit-vector. Unconstrained means that you have not specified how many elements that array has. This is just like the definition of e.g. the std_logic_vector type, which per se is also unconstrained. So basically you now have two unconstrained types, your own V_array and std_logic_vector, it's just the type of the element that's different. For std_logic_vector, each element is of type std_logic; for V_array, each element is of type std_logic_vector(11 downto 0). But if you now want to create an actual object (signal, variable, constant...) of one of these types, you have to specify the size of that object (because in the end these objects may end up as logic or registers or such, and then their size must be known; also the compiler may need to reserve memory for these objects, also needs to know their size for that). You can do that in a number of ways: - you can explicitly specify the range in parentheses, like you do when you write std_logic_vector(11 downto 0) or V_array(0 to 2) - you can implicitly specify it during initialization, which you did here: constant V_level_array : V_array := (x"0000",x"0100",x"2000"); Since you assigned it an initialization value with three elements, the compiler now concludes that V_level_array should also hold 3 elements. You could also in addition have specified it like this to prevent the compiler from guessing: constant V_level_array : V_array(0 to 2) := (x"0000",x"0100",x"2000"); Actually, I personally would do the latter, since I don't know what range the compiler decides it should be. The only info it has is that V_array should hold 3 elements, but that would also be the case for ranges like (2 downto 0), (7 downto 5), (0 downto -2). I can only assume in the LRM there's a default orientation and numbering defined, which I don't know. So now we know that in order to create an object (in your case the shared variable), we need to specify the size it should have. In your case you want it to be the same size as another object, and fortunately in VHDL there are so-called attributes you can use to find that out. - object'range gives you the range (for example "(11 downto 0)") of a signal, constant or variable (or entity port) - object'length gives you the total length, e.g. for a std_logic_vector(11 downto 0) that would be 12 - object'left and object'right give you the left and right boundaries, which would be 11 and 0, respectively for a std_logic_vector(11 downto 0) There's a few others, you can look those up. All of these are very handy, especially if you want to create flexible, re-usable designs. Imagine you have some arithmetic module that you want to use in several different projects. But sometimes you need it to work with an input data width of 8 bit, sometimes 16 and sometimes 32 bits. You could either create 3 different entities, one each for using 8, 16 and 32 bits as input data width. That's three times the work, and if you fix bugs, you have to do that in all three. So, instead you could just use unconstrained input ports, and inside the module have all signal declarations and such be relative to the port widths, which you can determine using the abovementioned attributes. That way you can write one single module that automatically works for all input bit widths. The actual width is determined by the signal that is connected to the instance's input ports. That's one application for what you're trying to do. Probably not what you had in mind there, but maybe you'll head in that direction later. From newsfish@newsfish Thu Aug 1 00:37:22 2024 X-Received: by 10.107.22.194 with SMTP id 185mr26427429iow.25.1468833426086; Mon, 18 Jul 2016 02:17:06 -0700 (PDT) X-Received: by 10.36.91.205 with SMTP id g196mr1954380itb.0.1468833426007; Mon, 18 Jul 2016 02:17:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no1905405ith.0!news-out.google.com!d130ni6698ith.0!nntp.google.com!f6no1908588ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 18 Jul 2016 02:17:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: <0cd5ad3e-790f-4acd-9856-af9565597596@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <83173fd6-14cb-41ef-b49c-10e06aeae4cc@googlegroups.com> Subject: Re: How to constrain this array From: David Perry Injection-Date: Mon, 18 Jul 2016 09:17:06 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4496 Wow, comprehensive, thanks :) > > It syntax checks ok now :) > > Why are the rules so confusing :( >=20 > It's not really that confusing if you think about it: Some of the syntax confuses me. An example, which took me a while to figure= out was this: I have a Fault vector (it's longer than 2 bits but I've shortened it for cl= arity) Faults <=3D EXT_A & EXT_B; That's fine, it's concatenated using &. Then I want to output a similar vector to some outputs: (A, B) <=3D Faults_mod; This took me a while to work out! The documentation I google for seems to only show the most basic things you= might want to do. > But if you now want to create an actual object (signal, variable, > constant...) of one of these types, you have to specify the size of that > object (because in the end these objects may end up as logic or > registers or such, and then their size must be known; also the compiler > may need to reserve memory for these objects, also needs to know their > size for that). You can do that in a number of ways: > - you can explicitly specify the range in parentheses, like you do when > you write std_logic_vector(11 downto 0) or V_array(0 to 2) > - you can implicitly specify it during initialization, which you did here= : >=20 > constant V_level_array : V_array :=3D (x"0000",x"0100",x"2000"); >=20 > Since you assigned it an initialization value with three elements, the > compiler now concludes that V_level_array should also hold 3 elements. > You could also in addition have specified it like this to prevent the > compiler from guessing: >=20 > constant V_level_array : V_array(0 to 2) :=3D (x"0000",x"0100",x"2000"); >=20 > Actually, I personally would do the latter, since I don't know what > range the compiler decides it should be. The only info it has is that > V_array should hold 3 elements, but that would also be the case for > ranges like (2 downto 0), (7 downto 5), (0 downto -2). I can only assume > in the LRM there's a default orientation and numbering defined, which I > don't know. I deliberately wanted the compiler to determine the size, I'm using 'range = later on to for loop the array. My philosophy was to allow the array size t= o change if needed without having to change anything else. A bit overkill f= or the module I've written, but I'm trying to get into good habits :) (FYI, the 3 elements of the array aren't defined as hex, they are converted= from real values and range limited, best practice and all that :) ). > - object'left and object'right give you the left and right boundaries, > which would be 11 and 0, respectively for a std_logic_vector(11 downto 0) >=20 > There's a few others, you can look those up. All of these are very > handy, especially if you want to create flexible, re-usable designs. I keep looking at this: http://www.csee.umbc.edu/portal/help/VHDL/attribute.html Been using 'high and 'low, not so sure what the best to use is now. > Imagine you have some arithmetic module that you want to use in several > different projects. But sometimes you need it to work with an input data > width of 8 bit, sometimes 16 and sometimes 32 bits. Uh-oh, someone mentioned generics to me a while ago, this has a familiar sm= ell to it :) > You could either create 3 different entities, one each for using 8, 16 > and 32 bits as input data width. That's three times the work, and if you > fix bugs, you have to do that in all three. So, instead you could just > use unconstrained input ports, and inside the module have all signal > declarations and such be relative to the port widths, which you can > determine using the abovementioned attributes. That way you can write > one single module that automatically works for all input bit widths. The > actual width is determined by the signal that is connected to the > instance's input ports. I'm sure that will be something I will want to do at some point. I'm moving= away from the schematic world where I did have to build multiple sized par= ts (it wasn't always convenient to just build the biggest and let the compi= ler remove the excess). > That's one application for what you're trying to do. Probably not what > you had in mind there, but maybe you'll head in that direction later. A mate of mine handed me a module name and a list of IO and asked me to pla= y with it, it's all a bit simple and specific. Thanks for the help :) From newsfish@newsfish Thu Aug 1 00:37:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to constrain this array Date: Mon, 18 Jul 2016 09:47:54 -0400 Organization: A noiseless patient Spider Lines: 129 Message-ID: References: <0cd5ad3e-790f-4acd-9856-af9565597596@googlegroups.com> <83173fd6-14cb-41ef-b49c-10e06aeae4cc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 18 Jul 2016 13:47:52 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="16984"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX183tiB/UfKuvkHc5J/T5KP+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <83173fd6-14cb-41ef-b49c-10e06aeae4cc@googlegroups.com> Cancel-Lock: sha1:WVUleTHjf3UyQR9d+DhhPizMViw= Xref: news.eternal-september.org comp.lang.vhdl:4497 On 7/18/2016 5:17 AM, David Perry wrote: > Wow, comprehensive, thanks :) > >>> It syntax checks ok now :) >>> Why are the rules so confusing :( >> >> It's not really that confusing if you think about it: > > Some of the syntax confuses me. An example, which took me a while to figure out was this: > I have a Fault vector (it's longer than 2 bits but I've shortened it for clarity) > Faults <= EXT_A & EXT_B; > That's fine, it's concatenated using &. > Then I want to output a similar vector to some outputs: > (A, B) <= Faults_mod; > This took me a while to work out! > The documentation I google for seems to only show the most basic things you might want to do. Aggregates can be PITA to use, but a bit easier in VHDL-2008. >> But if you now want to create an actual object (signal, variable, >> constant...) of one of these types, you have to specify the size of that >> object (because in the end these objects may end up as logic or >> registers or such, and then their size must be known; also the compiler >> may need to reserve memory for these objects, also needs to know their >> size for that). You can do that in a number of ways: >> - you can explicitly specify the range in parentheses, like you do when >> you write std_logic_vector(11 downto 0) or V_array(0 to 2) >> - you can implicitly specify it during initialization, which you did here: >> >> constant V_level_array : V_array := (x"0000",x"0100",x"2000"); >> >> Since you assigned it an initialization value with three elements, the >> compiler now concludes that V_level_array should also hold 3 elements. >> You could also in addition have specified it like this to prevent the >> compiler from guessing: >> >> constant V_level_array : V_array(0 to 2) := (x"0000",x"0100",x"2000"); >> >> Actually, I personally would do the latter, since I don't know what >> range the compiler decides it should be. The only info it has is that >> V_array should hold 3 elements, but that would also be the case for >> ranges like (2 downto 0), (7 downto 5), (0 downto -2). I can only assume >> in the LRM there's a default orientation and numbering defined, which I >> don't know. > > I deliberately wanted the compiler to determine the size, I'm using 'range later on to for loop the array. My philosophy was to allow the array size to change if needed without having to change anything else. A bit overkill for the module I've written, but I'm trying to get into good habits :) > (FYI, the 3 elements of the array aren't defined as hex, they are converted from real values and range limited, best practice and all that :) ). > >> - object'left and object'right give you the left and right boundaries, >> which would be 11 and 0, respectively for a std_logic_vector(11 downto 0) >> >> There's a few others, you can look those up. All of these are very >> handy, especially if you want to create flexible, re-usable designs. > > I keep looking at this: > http://www.csee.umbc.edu/portal/help/VHDL/attribute.html > Been using 'high and 'low, not so sure what the best to use is now. 'high and 'low are appropriate often. Once in a while 'left and 'right are appropriate, other times 'range is best. The advantage of 'high and 'low is it will work for inputs defined using both "downto" and "to" if you want to create an internal variable of known direction for example. 'range works defining variables that must match the input, also looping in a direction to match the input. 'left and 'right will match the input range for a loop as well. It all depends on what you need and how flexible the code needs to be. Here I used 'range to define the loop mainly because it is simpler to type. "'left to 'right" would also have worked. "'left to 'right" works because that is how the string needs to be interpreted. 'range works because the string should be converted from the msd to the lsd which matches the definition of the range whether using "downto" or 'to". Sorry for the line wrap. -- Convert a string of hex digits to an unsigned vector of indicated length function Hex_to_unsigned (HexDigits : string; DigCnt : positive) return unsigned is variable temp : natural := 0; variable unsgnd : unsigned (DigCnt-1 downto 0) := (others => '0'); begin for I in HexDigits'RANGE loop temp := temp * 16 + Hex_to_integer (HexDigits (I)); end loop; return (to_unsigned(temp, DigCnt)); end Hex_to_unsigned; >> Imagine you have some arithmetic module that you want to use in several >> different projects. But sometimes you need it to work with an input data >> width of 8 bit, sometimes 16 and sometimes 32 bits. > > Uh-oh, someone mentioned generics to me a while ago, this has a familiar smell to it :) Yes, generics are great for entities which meed to be flexible over data widths. For functions the size should be determined using 'range et al or if necessary with an extra parameter like the way to_unsigned does when converting an integer (see above example). >> You could either create 3 different entities, one each for using 8, 16 >> and 32 bits as input data width. That's three times the work, and if you >> fix bugs, you have to do that in all three. So, instead you could just >> use unconstrained input ports, and inside the module have all signal >> declarations and such be relative to the port widths, which you can >> determine using the abovementioned attributes. That way you can write >> one single module that automatically works for all input bit widths. The >> actual width is determined by the signal that is connected to the >> instance's input ports. > > I'm sure that will be something I will want to do at some point. I'm moving away from the schematic world where I did have to build multiple sized parts (it wasn't always convenient to just build the biggest and let the compiler remove the excess). It can be good to have units that are flexible, but sometimes it just isn't important and the extra time should be avoided. Certainly you should know how to do it when needed, so it's good to practice. >> That's one application for what you're trying to do. Probably not what >> you had in mind there, but maybe you'll head in that direction later. > > A mate of mine handed me a module name and a list of IO and asked me to play with it, it's all a bit simple and specific. > > Thanks for the help :) -- Rick C From newsfish@newsfish Thu Aug 1 00:37:23 2024 X-Received: by 10.129.163.6 with SMTP id a6mr33268676ywh.31.1468941409060; Tue, 19 Jul 2016 08:16:49 -0700 (PDT) X-Received: by 10.36.53.200 with SMTP id k191mr2234250ita.9.1468941408972; Tue, 19 Jul 2016 08:16:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!c52no3531524qte.1!news-out.google.com!d130ni7973ith.0!nntp.google.com!f6no2633080ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 19 Jul 2016 08:16:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: <0cd5ad3e-790f-4acd-9856-af9565597596@googlegroups.com> <83173fd6-14cb-41ef-b49c-10e06aeae4cc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3b31e9cd-9a0e-43a4-a0bc-d6de3dbf8e84@googlegroups.com> Subject: Re: How to constrain this array From: David Perry Injection-Date: Tue, 19 Jul 2016 15:16:49 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 4 Xref: news.eternal-september.org comp.lang.vhdl:4498 > Aggregates can be PITA to use, but a bit easier in VHDL-2008. I don't know if my tools support 2008, worth me looking into though. Annoyingly is seems we can aggregate a vector and a bit to a larger vector quite easily, but not the other way around (you can do it on 2 lines and specify the ranges, but that doesn't look as neat). From newsfish@newsfish Thu Aug 1 00:37:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: learning sequencial logic Date: Tue, 19 Jul 2016 23:59:28 +0200 Organization: A noiseless patient Spider Lines: 86 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 19 Jul 2016 21:59:29 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="431e940ef53f9c375d5566ed24bd7bc1"; logging-data="17652"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19z5o73FuvrvzUKuUPkKMii" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:IGGLj8iWUIHUag9ICzE6Hqjl5qE= Xref: news.eternal-september.org comp.lang.vhdl:4499 Hi Rick, A follow-up on a thread of some month ago :-) On 11-06-16 21:24, rickman wrote: > A reasonably simple example would be a basic, fixed size UART, say 8 > bits, no parity, one stop bit. Design the transmitter and receiver > separately and test by connecting them together and shipping characters (...) OK. I did some work on other stuff inbetween, but I finished the UART sender and UART receiver. I dropped it on my github account: https://github.com/on1arf/vhdl-exercises I tested the code not by simulation but with an test setup of a altera fpga and a mapple mini clone (STM32F103-based). (The UART receiver does seams to "slip" characters from time to time, so that is something I need to look at) :-( I do have two questions: 1/ In uart_receive, there are four signals that are triggered on a positive or negative edge, so I created four small edge-detection processes. (nothing special, just compair in signal with the same signal the previous clock-cycle). As I use the same code four times over, for me - as a programmer- it would be logical to create a function or an object for this; but I don't know how to do this in VHDL. The problem here is that there is a data (the value of the input signal the previous clock-cycle) that must be kept between iterations of calling the function , i.e. a "static vars" in C linguo. But -as far as I have found in the documentation about VHDL functions- local signals in a function in VHDL do not maintain state inbetween iterations and I see no way to define "static" local signals. As a result, uart_receive.vhd has four edge-detection functions, with all data stored as "global" data. Note very clean :-( Now I cannot really image that VHDL does not have a way to store "code" that maintain state inbetween iterations. So how do you do this? 2/ I am now working on a FIFO-buffer to make the UART_receiver more robust. Do I need to add the FIFO buffer in the same VHDL-file (the same architecture) as the UART_receiver code; or is there a way to store the fifo-buffer VHDL-code in a seperate file. Then how do I "include" and "call" the FIFO vhdl-code in the uart_receive circuit? > Just a thought. A very interesting exercise, I must say. :-) I am now working on the 4 byte FIFO buffer for the UART. After that, I'll try the SPI stuff. Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:37:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: learning sequencial logic Date: Tue, 19 Jul 2016 20:22:43 -0400 Organization: A noiseless patient Spider Lines: 103 Message-ID: References: <058f7cf0-eba0-4c38-8fd1-26c58916f9b1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 20 Jul 2016 00:22:45 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="11976"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19mfgR9+7BssIoKWNdRuSaI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:lPuqFBUdjZHIXCbmC0ofqvdWGQo= Xref: news.eternal-september.org comp.lang.vhdl:4500 On 7/19/2016 5:59 PM, kristoff wrote: > Hi Rick, > > > A follow-up on a thread of some month ago :-) > > > > On 11-06-16 21:24, rickman wrote: >> A reasonably simple example would be a basic, fixed size UART, say 8 >> bits, no parity, one stop bit. Design the transmitter and receiver >> separately and test by connecting them together and shipping characters > (...) > > > OK. I did some work on other stuff inbetween, but I finished the UART > sender and UART receiver. I dropped it on my github account: > https://github.com/on1arf/vhdl-exercises > > I tested the code not by simulation but with an test setup of a altera > fpga and a mapple mini clone (STM32F103-based). > > > > (The UART receiver does seams to "slip" characters from time to time, so > that is something I need to look at) :-( > > > > I do have two questions: > > 1/ > In uart_receive, there are four signals that are triggered on a positive > or negative edge, so I created four small edge-detection processes. > (nothing special, just compair in signal with the same signal the > previous clock-cycle). > > > As I use the same code four times over, for me - as a programmer- it > would be logical to create a function or an object for this; but I don't > know how to do this in VHDL. > > The problem here is that there is a data (the value of the input signal > the previous clock-cycle) that must be kept between iterations of > calling the function , i.e. a "static vars" in C linguo. > > But -as far as I have found in the documentation about VHDL functions- > local signals in a function in VHDL do not maintain state inbetween > iterations and I see no way to define "static" local signals. > > > As a result, uart_receive.vhd has four edge-detection functions, with > all data stored as "global" data. Note very clean :-( > > > > Now I cannot really image that VHDL does not have a way to store "code" > that maintain state inbetween iterations. > > So how do you do this? Two ways to do it. One is to create an entity which contains the code as well as the signal declarations of any signals you need for internal storage. Then the entity is instantiated four times. Or you can use a procedure call. A procedure is sequential code and you can declare variables which *can* remember state between invocations if coded so they are used before being set. The variable can only be "seen" from outside of the procedure call by assigning its value to a signal in the parameter list. You might be able to use a function rather than a procedure if it only needs to return a single item (which can be an array or record). > 2/ > I am now working on a FIFO-buffer to make the UART_receiver more robust. > > Do I need to add the FIFO buffer in the same VHDL-file (the same > architecture) as the UART_receiver code; or is there a way to store the > fifo-buffer VHDL-code in a seperate file. > > Then how do I "include" and "call" the FIFO vhdl-code in the > uart_receive circuit? Separate entities can be defined in separate files or the same file. Functions, procedures and data types can be defined in libraries. Libraries are included with "use" statements. >> Just a thought. > > A very interesting exercise, I must say. :-) > > > I am now working on the 4 byte FIFO buffer for the UART. After that, > I'll try the SPI stuff. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:24 2024 X-Received: by 10.129.122.72 with SMTP id v69mr38523640ywc.40.1469022083415; Wed, 20 Jul 2016 06:41:23 -0700 (PDT) X-Received: by 10.36.50.75 with SMTP id j72mr2237902ita.5.1469022083355; Wed, 20 Jul 2016 06:41:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j37no3468352qta.0!news-out.google.com!d130ni8871ith.0!nntp.google.com!f6no2949705ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Jul 2016 06:41:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> Subject: Shared Variables From: David Perry Injection-Date: Wed, 20 Jul 2016 13:41:23 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1725 X-Received-Body-CRC: 2864334355 Xref: news.eternal-september.org comp.lang.vhdl:4501 If I have a shared variable which is only ever written by one process, but = could be read by multiple, will this generally work? Simulation gives me th= e correct results but I don't want to fall into any traps :) If I don't do sequential operations on the variable such as: a =3D b; a =3D a + c; --result is b + c then should I be using a signal? Is there any advantage to either method? I've noticed that the simulation can't display variables (Xilinx ISim), onl= y signals. Could this be because a signal has to be fully synthesised, but = a variable can get optimised away to something that doesn't quite resemble = the variable anymore? (I may be completely up the garden path with this). From newsfish@newsfish Thu Aug 1 00:37:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Shared Variables Date: Wed, 20 Jul 2016 11:01:25 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 20 Jul 2016 15:01:25 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="29802"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/btgJK94vnwI2YsZyGSMyk" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> Cancel-Lock: sha1:y1EcSR43v90jQ6SqNsmlhtSgJbA= Xref: news.eternal-september.org comp.lang.vhdl:4502 On 7/20/2016 9:41 AM, David Perry wrote: > If I have a shared variable which is only ever written by one process, but could be read by multiple, will this generally work? Simulation gives me the correct results but I don't want to fall into any traps :) > > If I don't do sequential operations on the variable such as: > a = b; > a = a + c; --result is b + c > then should I be using a signal? Is there any advantage to either method? I know one advantage of using a signal. If you used a signal you would not be asking about it. > I've noticed that the simulation can't display variables (Xilinx ISim), only signals. Could this be because a signal has to be fully synthesised, but a variable can get optimised away to something that doesn't quite resemble the variable anymore? (I may be completely up the garden path with this). Not so much "optimized away". Other than global variables, variables don't exist between invocations of the code unit where they are defined. This is not exactly true as using the value of a variable before assigning it a value creates a latch or register. Maybe I'll try a few simulations to see if I can get a variable to show in the waveform display. You can view the value of a variable in a watch window, right? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:25 2024 X-Received: by 10.98.204.142 with SMTP id j14mr32004562pfk.13.1469028625313; Wed, 20 Jul 2016 08:30:25 -0700 (PDT) X-Received: by 10.36.123.135 with SMTP id q129mr1046722itc.1.1469028625273; Wed, 20 Jul 2016 08:30:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!f6no2976391ith.0!news-out.google.com!d130ni8949ith.0!nntp.google.com!f6no2967040ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Jul 2016 08:30:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <16c31540-5436-4c30-9ec4-acc70b27e060@googlegroups.com> Subject: Re: Shared Variables From: David Perry Injection-Date: Wed, 20 Jul 2016 15:30:25 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 29 Xref: news.eternal-september.org comp.lang.vhdl:4503 > I know one advantage of using a signal. If you used a signal you would= =20 > not be asking about it. I've used both, at the moment I'm not seeing an advantage either way. > > I've noticed that the simulation can't display variables (Xilinx ISim),= only signals. Could this be because a signal has to be fully synthesised, = but a variable can get optimised away to something that doesn't quite resem= ble the variable anymore? (I may be completely up the garden path with this= ). >=20 > Not so much "optimized away". Other than global variables, variables=20 > don't exist between invocations of the code unit where they are defined.= =20 > This is not exactly true as using the value of a variable before=20 > assigning it a value creates a latch or register. I've yet to get my head around invocation. I have managed to steer clear of= latches tho, yay! > Maybe I'll try a few simulations to see if I can get a variable to show= =20 > in the waveform display. The only way I've managed that is by shoving it to a signal. > You can view the value of a variable in a watch window, right? I didn't even know there was a watch window (I'm on ISE 14.6) From newsfish@newsfish Thu Aug 1 00:37:25 2024 X-Received: by 10.107.27.10 with SMTP id b10mr37131263iob.2.1469030145503; Wed, 20 Jul 2016 08:55:45 -0700 (PDT) X-Received: by 10.36.101.10 with SMTP id u10mr735336itb.3.1469030145479; Wed, 20 Jul 2016 08:55:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no2983234ith.0!news-out.google.com!d68ni984ith.0!nntp.google.com!f6no2983233ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Jul 2016 08:55:44 -0700 (PDT) In-Reply-To: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <767989a1-ee97-47a6-9f88-83b9ba577389@googlegroups.com> Subject: Re: Shared Variables From: KJ Injection-Date: Wed, 20 Jul 2016 15:55:45 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4504 On Wednesday, July 20, 2016 at 9:41:25 AM UTC-4, David Perry wrote: > If I have a shared variable which is only ever written by one process, bu= t=20 > could be read by multiple, will this generally work? Simulation gives me= =20 > the correct results but I don't want to fall into any traps :) >=20 > If I don't do sequential operations on the variable such as: > a =3D b; > a =3D a + c; --result is b + c > then should I be using a signal? Is there any advantage to either method? >=20 If you're only using this for simulation, then either method is OK. If you= intend to synthesize this code, then you'll have to check to see if your s= ynthesis tool supports shared variables. In theory, updating variables in = simulation is quicker than signals (i.e. your wall clock time). You can ex= periment with both, but you'll probably be hard pressed to measure a signif= icant difference unless this signal/variable gets updated a lot. >=20 > I've noticed that the simulation can't display variables (Xilinx ISim),= =20 > only signals. Could this be because a signal has to be fully synthesised,= =20 > but a variable can get optimised away to something that doesn't quite=20 > resemble the variable anymore? (I may be completely up the garden path=20 > with this). No, this is just a limitation of the simulation tool. I don't know about I= Sim, but with Modelsim, you can simply drag a variable over to the wave win= dow for display. The drawback is there is no way to get the history so you= will have to set it up at start of sim if you want it. With a signal you = can log the activity to a file. Then if you want to display the signal in = the wave window it will show the entire history from t=3D0. Again, this is= Modelsim behavior, ISim may be different. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:25 2024 X-Received: by 10.13.214.202 with SMTP id y193mr37462792ywd.19.1469030241987; Wed, 20 Jul 2016 08:57:21 -0700 (PDT) X-Received: by 10.36.115.15 with SMTP id y15mr2639874itb.8.1469030241927; Wed, 20 Jul 2016 08:57:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c52no3769579qte.1!news-out.google.com!d68ni984ith.0!nntp.google.com!f6no2983560ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Jul 2016 08:57:21 -0700 (PDT) In-Reply-To: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.43.3.237; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.43.3.237 References: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5406668b-2ac2-43c1-b5c4-4d346cc709ea@googlegroups.com> Subject: Re: Shared Variables From: Jim Lewis Injection-Date: Wed, 20 Jul 2016 15:57:21 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4505 As of VHDL-2002, all shared variables shall be a protected type. =20 Yes some vendors support shared variables with regular types for RAMs. How= ever, outside of modeling RAMs, I would not use shared variables with anyth= ing except a protected type. Going further, OSVVM (see http://www.osvvm.org) offers a memory modeling pa= ckage (MemoryPkg) based on protected types. It uses a sparse data structur= e internally. For larger RAM models, this can be a significant simulation t= ime saver. It would be a big win to get FPGA vendors to support it. =20 Best, Jim jim at synthworks dot com From newsfish@newsfish Thu Aug 1 00:37:26 2024 X-Received: by 10.13.214.202 with SMTP id y193mr38344266ywd.19.1469043515508; Wed, 20 Jul 2016 12:38:35 -0700 (PDT) X-Received: by 10.36.111.147 with SMTP id x141mr2735716itb.6.1469043515470; Wed, 20 Jul 2016 12:38:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!c52no3808643qte.1!news-out.google.com!d68ni1111ith.0!nntp.google.com!f6no3043252ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Jul 2016 12:38:34 -0700 (PDT) In-Reply-To: <767989a1-ee97-47a6-9f88-83b9ba577389@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.99.53.115; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 81.99.53.115 References: <3f32fde9-cfd9-4734-9c14-972708e2985e@googlegroups.com> <767989a1-ee97-47a6-9f88-83b9ba577389@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <32f7e6fa-1489-44ce-8736-7c0ca200ecd5@googlegroups.com> Subject: Re: Shared Variables From: David Perry Injection-Date: Wed, 20 Jul 2016 19:38:35 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 25 X-Received-Bytes: 2903 X-Received-Body-CRC: 2007793516 Xref: news.eternal-september.org comp.lang.vhdl:4506 > If you're only using this for simulation, then either method is OK. If y= ou intend to synthesize this code, then you'll have to check to see if your= synthesis tool supports shared variables. In theory, updating variables i= n simulation is quicker than signals (i.e. your wall clock time). You can = experiment with both, but you'll probably be hard pressed to measure a sign= ificant difference unless this signal/variable gets updated a lot. I'm only at the simulation stage, I might have a go at building it into a s= mall project and see if it compiles. I'm moving from schematic entry to vhd= l, I'm used to the hardware result being the same as the simulation without= the need to worry about synthesis, it generally 'just works' when it's com= piles. I didn't actually realise it didn't synthesise it when it runs the s= imulation. > No, this is just a limitation of the simulation tool. I don't know about= ISim, but with Modelsim, you can simply drag a variable over to the wave w= indow for display. The drawback is there is no way to get the history so y= ou will have to set it up at start of sim if you want it. With a signal yo= u can log the activity to a file. Then if you want to display the signal i= n the wave window it will show the entire history from t=3D0. Again, this = is Modelsim behavior, ISim may be different. ISim is pretty similar, but I get a warning that it doesn't support variabl= es. I see the latest value in the waveform list, but no waveform. If I really need to see it, I just signal<=3Dvariable as a temporary measur= e, so it's not so bad. From newsfish@newsfish Thu Aug 1 00:37:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Forth in VHDL Date: Sun, 24 Jul 2016 22:29:25 -0400 Organization: A noiseless patient Spider Lines: 10 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 02:29:27 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="18350"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18LgJpf9RTp++zs9mw91jBJ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:WzzY7yVHDRLbAfRZiwwodcURcm8= Xref: news.eternal-september.org comp.lang.vhdl:4507 comp.lang.forth:49659 I wonder how hard it would be to write a Forth in VHDL? It would likely be as easy to do in non-synthesizable code as any other language. It might be a bit harder in synthesizable code. For one, the I/O would need to be constructed from scratch based on some hardware interface. The non-synthesizable code could just read from a file... I wonder if you can read from the console in VHDL? I've never tried that before. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Sun, 24 Jul 2016 23:01:17 -0400 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 03:01:19 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="22313"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX181myLXPbYyOJd2pR53QaKO" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:zh2jNf/yETkZDWMNWcrhnkQ41Ms= Xref: news.eternal-september.org comp.lang.vhdl:4508 comp.lang.forth:49660 On 7/24/2016 10:29 PM, rickman wrote: > I wonder how hard it would be to write a Forth in VHDL? It would likely > be as easy to do in non-synthesizable code as any other language. It > might be a bit harder in synthesizable code. For one, the I/O would > need to be constructed from scratch based on some hardware interface. > The non-synthesizable code could just read from a file... I wonder if > you can read from the console in VHDL? I've never tried that before. I did a little digging and it looks like you *can* do console I/O in VHDL using the textio package. So I can't think of anything to stop a vforth from being written... unless the vforth name has already been used. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Sun, 24 Jul 2016 23:05:27 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 03:05:27 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="22313"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19nTmeoZYdGlyJcBrTlVyrK" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:6vQvw/2LNK4egYuThk6YIqWoRvE= Xref: news.eternal-september.org comp.lang.vhdl:4509 comp.lang.forth:49661 On 7/24/2016 11:01 PM, rickman wrote: > On 7/24/2016 10:29 PM, rickman wrote: >> I wonder how hard it would be to write a Forth in VHDL? It would likely >> be as easy to do in non-synthesizable code as any other language. It >> might be a bit harder in synthesizable code. For one, the I/O would >> need to be constructed from scratch based on some hardware interface. >> The non-synthesizable code could just read from a file... I wonder if >> you can read from the console in VHDL? I've never tried that before. > > I did a little digging and it looks like you *can* do console I/O in > VHDL using the textio package. So I can't think of anything to stop a > vforth from being written... unless the vforth name has already been used. Looks like the name vforth has been used before... twice! Once for a VIC forth and once, more recently for a VAX forth? Really? Do people still have VAX computers? Or is this run on a VAX emulator? Maybe that's a retro thing? So it looks like nothing stands in the way of writing a Forth in VHDL other than free time... which I seem to have a lot of. ;) -- Rick C From newsfish@newsfish Thu Aug 1 00:37:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Cecil Bayona Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Sun, 24 Jul 2016 22:25:25 -0500 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 03:25:26 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4c6149fda0f382b24075b7a1eefa3518"; logging-data="24840"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/AwctXuLlmFBvUEAl++1Yu" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:5rGlx7m2yD7T/k6C8hly243xwJs= Xref: news.eternal-september.org comp.lang.vhdl:4510 comp.lang.forth:49663 On 7/24/2016 10:05 PM, rickman wrote: > On 7/24/2016 11:01 PM, rickman wrote: >> On 7/24/2016 10:29 PM, rickman wrote: >>> I wonder how hard it would be to write a Forth in VHDL? It would likely >>> be as easy to do in non-synthesizable code as any other language. It >>> might be a bit harder in synthesizable code. For one, the I/O would >>> need to be constructed from scratch based on some hardware interface. >>> The non-synthesizable code could just read from a file... I wonder if >>> you can read from the console in VHDL? I've never tried that before. >> >> I did a little digging and it looks like you *can* do console I/O in >> VHDL using the textio package. So I can't think of anything to stop a >> vforth from being written... unless the vforth name has already been >> used. > > Looks like the name vforth has been used before... twice! Once for a > VIC forth and once, more recently for a VAX forth? Really? Do people > still have VAX computers? Or is this run on a VAX emulator? Maybe > that's a retro thing? > > So it looks like nothing stands in the way of writing a Forth in VHDL > other than free time... which I seem to have a lot of. ;) > But what would you gain? It would be horribly slow and no benefit that I can see. Better to use VHDL to create a CPU that runs Forth natively, that is why I been working on some of the Forth CPUs that run in FPGAs. Aside from the above mentioned it would be interesting to create hardware that runs Forth natively, not a CPU but a set of hardware that runs the code natively. Are you still recovering? -- Cecil - k5nwa From newsfish@newsfish Thu Aug 1 00:37:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Mon, 25 Jul 2016 00:08:55 -0400 Organization: A noiseless patient Spider Lines: 77 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 04:08:56 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="30250"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18YMvDYbBFv68hSCgnl7QIS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:5y8jdelcve2IkYcXCPr+vBmbxA8= Xref: news.eternal-september.org comp.lang.vhdl:4511 comp.lang.forth:49669 On 7/24/2016 11:25 PM, Cecil Bayona wrote: > On 7/24/2016 10:05 PM, rickman wrote: >> On 7/24/2016 11:01 PM, rickman wrote: >>> On 7/24/2016 10:29 PM, rickman wrote: >>>> I wonder how hard it would be to write a Forth in VHDL? It would >>>> likely >>>> be as easy to do in non-synthesizable code as any other language. It >>>> might be a bit harder in synthesizable code. For one, the I/O would >>>> need to be constructed from scratch based on some hardware interface. >>>> The non-synthesizable code could just read from a file... I wonder if >>>> you can read from the console in VHDL? I've never tried that before. >>> >>> I did a little digging and it looks like you *can* do console I/O in >>> VHDL using the textio package. So I can't think of anything to stop a >>> vforth from being written... unless the vforth name has already been >>> used. >> >> Looks like the name vforth has been used before... twice! Once for a >> VIC forth and once, more recently for a VAX forth? Really? Do people >> still have VAX computers? Or is this run on a VAX emulator? Maybe >> that's a retro thing? >> >> So it looks like nothing stands in the way of writing a Forth in VHDL >> other than free time... which I seem to have a lot of. ;) >> > But what would you gain? It would be horribly slow and no benefit that I > can see. Better to use VHDL to create a CPU that runs Forth natively, > that is why I been working on some of the Forth CPUs that run in FPGAs. > > Aside from the above mentioned it would be interesting to create > hardware that runs Forth natively, not a CPU but a set of hardware that > runs the code natively. > > Are you still recovering? Recovery is going pretty well, thanks for asking. I have regained most of the muscle strength lost from limping very abnormally for some years. I still have swelling in the operated leg but no one is very concerned and it seems to be better the last week or so. They did an ultrasound to rule out DVT so it should just be some more time. The funny part is that my work no longer requires much of me other than pushing paper and staying on top of things. I accept orders for hardware I sell and place the orders with my fabrication house. When they complete testing and ship the boards I send the invoice to the customer and pay the fab house. Lots of profit with very little work. In fact, technically I was working during my surgery (waiting for boards to be fabbed). That's the main reason why I have free time. I was thinking in terms of a Forth interpreter for use as a test bench. Currently I write test benches one of three ways. Either I write ad hoc code that generates arbitrary signals based on the requirements of the object being tested - or I use another copy of the hardware being tested as the tester when it uses a symmetrical interface - or for interfaces with well parameterized functionality, I write a text interpreter which reads commands from a file to control the testing. Using a Forth interpreter would allow me to handle any of the above in Forth directly reading and writing I/Os to the device under test - or connecting inputs and outputs of various modules - or reading commands from a file to manipulate interfaces. You are thinking of speed in terms of something real time. VHDL simulation are nowhere near real time. But it would be nice to program a test bench in something other than VHDL. As to a "directly executing" Forth CPU, what would that be exactly? Hardware is hardware. To design it requires forming an idea of the hardware. The only hardware I have thought of to execute Forth would be the same sort of stack machines I've seen many times and designed myself. Not much new there. What would a "native" Forth machine look like other than a dual stack CPU which is what the Forth virtual machine is? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Cecil Bayona Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Sun, 24 Jul 2016 23:57:58 -0500 Organization: A noiseless patient Spider Lines: 53 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 04:58:00 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4c6149fda0f382b24075b7a1eefa3518"; logging-data="3714"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+MoYJo++7z8gfteX/iE2XI" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:alw0L+VEZguklY3IQH9CVXx6zps= Xref: news.eternal-september.org comp.lang.vhdl:4512 comp.lang.forth:49674 On 7/24/2016 11:08 PM, rickman wrote: > On 7/24/2016 11:25 PM, Cecil Bayona wrote: >> On 7/24/2016 10:05 PM, rickman wrote: >> Are you still recovering? > > Recovery is going pretty well, thanks for asking. I have regained most > of the muscle strength lost from limping very abnormally for some years. > I still have swelling in the operated leg but no one is very concerned > and it seems to be better the last week or so. They did an ultrasound > to rule out DVT so it should just be some more time. > > The funny part is that my work no longer requires much of me other than > pushing paper and staying on top of things. I accept orders for > hardware I sell and place the orders with my fabrication house. When > they complete testing and ship the boards I send the invoice to the > customer and pay the fab house. Lots of profit with very little work. > In fact, technically I was working during my surgery (waiting for boards > to be fabbed). That's the main reason why I have free time. > Good to hear you are doing better, it might take a while of therapy and exercises until you are closer to being your old self physically. Myself tomorrow I will go to the doctor in the morning to figure out what to try next, I'm not responding to very expensive medicine so I might have to take desperate measures to bring my health under control. > > As to a "directly executing" Forth CPU, what would that be exactly? > Hardware is hardware. To design it requires forming an idea of the > hardware. The only hardware I have thought of to execute Forth would be > the same sort of stack machines I've seen many times and designed > myself. Not much new there. What would a "native" Forth machine look > like other than a dual stack CPU which is what the Forth virtual machine > is? > I've seen CPUs made from asynchronous random logic rather your typical synchronous logic like almost all standard CPUs, they tend to be a little faster but a nightmare to debug. You would still have the registers but most of the logic would be random logic versus nice state machines and everything running off a master clock. Not any major advantages other than being a little bit faster but lots of disadvantages, timing is a nightmare, so is debugging it. No enough gains to justify the problems so I stick to nice synchronous logic, one is better off with CPUs like the ep32, five packed instructions to a 32 bit word, TOS an NOS on registers, single clock execution of instructions, a nice machine, another nice one is the J1 capable of multiple instruction execution in one clock. -- Cecil - k5nwa From newsfish@newsfish Thu Aug 1 00:37:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Mon, 25 Jul 2016 01:22:01 -0400 Organization: A noiseless patient Spider Lines: 95 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 05:22:02 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="7012"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18JUQVCBwRD/ArLjw2+mMTK" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:CsqFsX7wgcvb5+dwg8+V2QEH2Oc= Xref: news.eternal-september.org comp.lang.vhdl:4513 comp.lang.forth:49679 On 7/25/2016 12:57 AM, Cecil Bayona wrote: > On 7/24/2016 11:08 PM, rickman wrote: >> On 7/24/2016 11:25 PM, Cecil Bayona wrote: >>> On 7/24/2016 10:05 PM, rickman wrote: > >>> Are you still recovering? >> >> Recovery is going pretty well, thanks for asking. I have regained most >> of the muscle strength lost from limping very abnormally for some years. >> I still have swelling in the operated leg but no one is very concerned >> and it seems to be better the last week or so. They did an ultrasound >> to rule out DVT so it should just be some more time. >> >> The funny part is that my work no longer requires much of me other than >> pushing paper and staying on top of things. I accept orders for >> hardware I sell and place the orders with my fabrication house. When >> they complete testing and ship the boards I send the invoice to the >> customer and pay the fab house. Lots of profit with very little work. >> In fact, technically I was working during my surgery (waiting for boards >> to be fabbed). That's the main reason why I have free time. >> > Good to hear you are doing better, it might take a while of therapy and > exercises until you are closer to being your old self physically. > > Myself tomorrow I will go to the doctor in the morning to figure out > what to try next, I'm not responding to very expensive medicine so I > might have to take desperate measures to bring my health under control. If you mentioned this before I don't recall. Sounds like it might be serious. >> As to a "directly executing" Forth CPU, what would that be exactly? >> Hardware is hardware. To design it requires forming an idea of the >> hardware. The only hardware I have thought of to execute Forth would be >> the same sort of stack machines I've seen many times and designed >> myself. Not much new there. What would a "native" Forth machine look >> like other than a dual stack CPU which is what the Forth virtual machine >> is? >> > I've seen CPUs made from asynchronous random logic rather your typical > synchronous logic like almost all standard CPUs, they tend to be a > little faster but a nightmare to debug. You would still have the > registers but most of the logic would be random logic versus nice state > machines and everything running off a master clock. Not any major > advantages other than being a little bit faster but lots of > disadvantages, timing is a nightmare, so is debugging it. The speed advantage of async logic is essentially a myth in that you have to design for real time needs which means deadlines. An async processor can be faster due to the various factors which affect timing, but you have to allow for all these factors being the worst possible in calculating if you can meet your deadlines. Same as clocked logic, but rather than at the clock cycle, at the system level. I had this discussion once and the only app anyone came up with was networking. It is not uncommon for CPUs to become saturated so that packets fall on the floor when the CPU is slammed. An async processor would be able to utilize any speed advantage it might have to process more packets before dropping any. > No enough gains to justify the problems so I stick to nice synchronous > logic, one is better off with CPUs like the ep32, five packed > instructions to a 32 bit word, TOS an NOS on registers, single clock > execution of instructions, a nice machine, another nice one is the J1 > capable of multiple instruction execution in one clock. You really can't design async logic in FPGAs that I know of. It has to be custom chips. Achronix is developing async logic FPGAs, but I think they are intent on the really big customers only, small users need not apply. I looked at what amounts to VLIW for MISC processors (sounds like an oxymoron, no?) The ide was that there are three processors in any two stack machine. 1) the instruction processor, 2) tThe data (stack) processor, 3) the return (I call it the address) processor. Each one could do something independent on each instruction cycle. The instructions can be encoded (standard MISC instructions) or the instructions can be separate, one for each of the three processors (which is the main idea behind VLIW). Various combinations of instructions give the basic primitives but many other useful combinations as well such as a return on any instruction that doesn't conflict with the hardware usage. I only looked at this for a bit. I believe that is how the J1 gets some parallelism. My stumbling block was in writing a compiler to take advantage of this. But then I don't really intend to program any of my apps in Forth really. I would just code it in the stack machine assembly, not unlike what Chuck Moore does for the F18A. Forth is used to write the macro assembler. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Paul Rubin Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Sun, 24 Jul 2016 22:38:53 -0700 Organization: A noiseless patient Spider Lines: 19 Message-ID: <87fuqy9t02.fsf@jester.gateway.pace.com> References: Mime-Version: 1.0 Content-Type: text/plain Injection-Info: mx02.eternal-september.org; posting-host="52eac348160ce62b68e4635eee7cc854"; logging-data="8358"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18wdF8+8dXOXqPj8aNCay/Q" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) Cancel-Lock: sha1:wGDx93x4Bvm2ybUNML3KijTZW0w= sha1:c0Pe0CS5YmlBJq1AYNKbZGa6fR4= Xref: news.eternal-september.org comp.lang.vhdl:4514 comp.lang.forth:49680 rickman writes: > The speed advantage of async logic is essentially a myth in that you > have to design for real time needs which means deadlines. I thought the idea was instructions could have variable latency depending on the data, and async meant you could start the next instruction as soon as the previous one finished. > You really can't design async logic in FPGAs that I know of. It has > to be custom chips. Hmm, I wonder what the obstacle is. Certainly async was used in old discrete or low-integration machines like the PDP-6 and KA10 from the 1970s. I think it feel out of favor as machines got more complex, due to debugging headaches etc. > I looked at what amounts to VLIW for MISC processors That's sort of what the Novix was, I thought. From newsfish@newsfish Thu Aug 1 00:37:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Mon, 25 Jul 2016 01:53:44 -0400 Organization: A noiseless patient Spider Lines: 53 Message-ID: References: <87fuqy9t02.fsf@jester.gateway.pace.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 05:53:45 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="11241"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18yEPnLa8vNRtGX9hhEJomT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <87fuqy9t02.fsf@jester.gateway.pace.com> Cancel-Lock: sha1:TpRKaJ3CAgzKaUsNiZLuOlsig1I= Xref: news.eternal-september.org comp.lang.vhdl:4515 comp.lang.forth:49681 On 7/25/2016 1:38 AM, Paul Rubin wrote: > rickman writes: >> The speed advantage of async logic is essentially a myth in that you >> have to design for real time needs which means deadlines. > > I thought the idea was instructions could have variable latency > depending on the data, and async meant you could start the next > instruction as soon as the previous one finished. It is not really without a clock, just no single, system clock. Each data path has to be timed by a parallel path of logic to create the clock. In the F18A, there are a number of paths which are separately timed, but roughly they fall into three or four groups with the same delay. This is not unlike clocked processors with multiple clock instructions. The slow paths are broken into more than one clock cycle. I shouldn't say there is "no" speedup. But I've not seen anything that says it is very significant. >> You really can't design async logic in FPGAs that I know of. It has >> to be custom chips. > > Hmm, I wonder what the obstacle is. Certainly async was used in old > discrete or low-integration machines like the PDP-6 and KA10 from the > 1970s. I think it feel out of favor as machines got more complex, due > to debugging headaches etc. Async logic requires very different design. There is truly async logic which has no clocks at all. This is hard to design requiring "coverage" of boundaries between product terms to make sure there is no glitching when inputs change which should result in no output changes. But what is talked about in processors should be called "self timed" logic. Self timed logic requires a lot more timing data than FPGA makers are willing to commit to. It would be a PITA for them to characterize it and then test to it. All for fairly marginal advantages... unless Achronix finds an easier way to make it all happen. >> I looked at what amounts to VLIW for MISC processors > > That's sort of what the Novix was, I thought. I don't think it is literally separate instructions for the various internal processors, but I haven't looked at it in depth. It does provide for data movements in parallel. But then the CPU I designed had very simple data paths. I don't know so much about the Novix, but I think it had a lot of data path features. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Cecil Bayona Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Mon, 25 Jul 2016 14:11:16 -0500 Organization: A noiseless patient Spider Lines: 82 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 19:11:18 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4c6149fda0f382b24075b7a1eefa3518"; logging-data="7136"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/2d61lwmItyZN4xhB3ekxw" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:Db7deMt+N6wD8VT9E2Asi6L6P0s= Xref: news.eternal-september.org comp.lang.vhdl:4516 comp.lang.forth:49734 On 7/25/2016 12:22 AM, rickman wrote: > On 7/25/2016 12:57 AM, Cecil Bayona wrote: >> On 7/24/2016 11:08 PM, rickman wrote: >> Myself tomorrow I will go to the doctor in the morning to figure out >> what to try next, I'm not responding to very expensive medicine so I >> might have to take desperate measures to bring my health under control. > > If you mentioned this before I don't recall. Sounds like it might be > serious. > > It is, I'm diabetic and for the past 6 month or so I have not been responding very well to my medicine, the doctor has tried several different drugs with poor results, My A1C was 11.3 6 month ago. Slowly things have been improving so 3 months ago it went down to 8.3 on A1C test, this morning my result from lab work show that I have a A1C of 7.1 this time around. Unfortunately the medicine that seems to work (Victoza) is not covered by my insurance and I can't afford it so this morning she gave me some samples of 75%/25% HumaLog Insulin which will cost $212 a month, it will be difficult and a strain on my budget but I have little choice. It will take a few weeks before I know how well its working as it will take a week for the older medicine to work out of my system. The desperate measures has to do with eating, the latest research shows that if someone can tolerate it fasting will help a lot in bringing down your blood sugar, and helps you loose weight which also is a big help. I can tolerate fasting well and tried it out a few times and it worked quite well, after 2 days of fasting my blood sugar was way down into the really good range 85-100 in the morning, and 150 2 hours after a meal, that is totally normal for a non-diabetic. So a starting plan would be fast for three days, eat moderately for 2 days, then repeat the cycle again, after a month or two of this, you can't help it and you start loosing weight, if your weight gets down low enough you don't need to fast as much and you won't need the drugs a much. > > >> No enough gains to justify the problems so I stick to nice synchronous >> logic, one is better off with CPUs like the ep32, five packed >> instructions to a 32 bit word, TOS an NOS on registers, single clock >> execution of instructions, a nice machine, another nice one is the J1 >> capable of multiple instruction execution in one clock. > > You really can't design async logic in FPGAs that I know of. It has to > be custom chips. Achronix is developing async logic FPGAs, but I think > they are intent on the really big customers only, small users need not > apply. I have not looked into it but you might be right as the LUTS have flip flops on their outputs and would need to be clocked. > > I looked at what amounts to VLIW for MISC processors (sounds like an > oxymoron, no?) The ide was that there are three processors in any two > stack machine. 1) the instruction processor, 2) tThe data (stack) > processor, 3) the return (I call it the address) processor. Each one > could do something independent on each instruction cycle. The > instructions can be encoded (standard MISC instructions) or the > instructions can be separate, one for each of the three processors > (which is the main idea behind VLIW). Various combinations of > instructions give the basic primitives but many other useful > combinations as well such as a return on any instruction that doesn't > conflict with the hardware usage. > > I only looked at this for a bit. I believe that is how the J1 gets some > parallelism. My stumbling block was in writing a compiler to take > advantage of this. But then I don't really intend to program any of my > apps in Forth really. I would just code it in the stack machine > assembly, not unlike what Chuck Moore does for the F18A. Forth is used > to write the macro assembler. > The J1 uses micro-programming, the instructions are the control bits for the internal CPU units, so it can do multiple transfers and logic/math operations at the same time, just set the right bits. So you could do a math operation, save the result, and return in one instruction. -- Cecil - k5nwa From newsfish@newsfish Thu Aug 1 00:37:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Mon, 25 Jul 2016 17:39:58 -0400 Organization: A noiseless patient Spider Lines: 144 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 21:40:00 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="8242"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Z8zfr3ZPhojRuOI+DQ6fE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:FHwzTrVDOJ2NFSmJvBI0Pt7mx68= Xref: news.eternal-september.org comp.lang.vhdl:4517 comp.lang.forth:49736 On 7/25/2016 3:11 PM, Cecil Bayona wrote: > On 7/25/2016 12:22 AM, rickman wrote: >> On 7/25/2016 12:57 AM, Cecil Bayona wrote: >>> On 7/24/2016 11:08 PM, rickman wrote: > >>> Myself tomorrow I will go to the doctor in the morning to figure out >>> what to try next, I'm not responding to very expensive medicine so I >>> might have to take desperate measures to bring my health under control. >> >> If you mentioned this before I don't recall. Sounds like it might be >> serious. >> >> > > It is, I'm diabetic and for the past 6 month or so I have not been > responding very well to my medicine, the doctor has tried several > different drugs with poor results, My A1C was 11.3 6 month ago. Slowly > things have been improving so 3 months ago it went down to 8.3 on A1C > test, this morning my result from lab work show that I have a A1C of 7.1 > this time around. > > Unfortunately the medicine that seems to work (Victoza) is not covered > by my insurance and I can't afford it so this morning she gave me some > samples of 75%/25% HumaLog Insulin which will cost $212 a month, it > will be difficult and a strain on my budget but I have little choice. It > will take a few weeks before I know how well its working as it will take > a week for the older medicine to work out of my system. > > The desperate measures has to do with eating, the latest research shows > that if someone can tolerate it fasting will help a lot in bringing down > your blood sugar, and helps you loose weight which also is a big help. I > can tolerate fasting well and tried it out a few times and it worked > quite well, after 2 days of fasting my blood sugar was way down into the > really good range 85-100 in the morning, and 150 2 hours after a meal, > that is totally normal for a non-diabetic. So a starting plan would be > fast for three days, eat moderately for 2 days, then repeat the cycle > again, after a month or two of this, you can't help it and you start > loosing weight, if your weight gets down low enough you don't need to > fast as much and you won't need the drugs a much. Diabetes runs in my family, but so far I have avoided it. Maybe because at *only* 35 lbs overweight I am a lighter member. It's been awhile since I was tested so I should do that. My last check was a doctor doing the blood sugar tests with the little strips in a supermarket. I had something small to eat some hours before and still was in the 70 range I seem to recall. He said that was great! >>> No enough gains to justify the problems so I stick to nice synchronous >>> logic, one is better off with CPUs like the ep32, five packed >>> instructions to a 32 bit word, TOS an NOS on registers, single clock >>> execution of instructions, a nice machine, another nice one is the J1 >>> capable of multiple instruction execution in one clock. >> >> You really can't design async logic in FPGAs that I know of. It has to >> be custom chips. Achronix is developing async logic FPGAs, but I think >> they are intent on the really big customers only, small users need not >> apply. > > I have not looked into it but you might be right as the LUTS have flip > flops on their outputs and would need to be clocked. Async clocked logic still has clocks, they just aren't a single clock running the whole chip. Think of traffic with lights. Cars arrive at a light and are stopped until it turns green. Cars arrive at different times (different logic delays) but they all must wait until they are all there before the light can turn green. The whole city is running all lights on the same cycle. So obviously there will be some lights that could run faster. So instead each block is timed independently. Each light is adjusted for the length and speed of the street so it can cycle faster if the street is shorter. But now all the lights are out of sync and more control signals are needed to allow the traffic to flow smoothly. Much harder to organize to let traffic flow smoothly. But there are still lights and traffic stops waiting for them... >> I looked at what amounts to VLIW for MISC processors (sounds like an >> oxymoron, no?) The ide was that there are three processors in any two >> stack machine. 1) the instruction processor, 2) tThe data (stack) >> processor, 3) the return (I call it the address) processor. Each one >> could do something independent on each instruction cycle. The >> instructions can be encoded (standard MISC instructions) or the >> instructions can be separate, one for each of the three processors >> (which is the main idea behind VLIW). Various combinations of >> instructions give the basic primitives but many other useful >> combinations as well such as a return on any instruction that doesn't >> conflict with the hardware usage. >> >> I only looked at this for a bit. I believe that is how the J1 gets some >> parallelism. My stumbling block was in writing a compiler to take >> advantage of this. But then I don't really intend to program any of my >> apps in Forth really. I would just code it in the stack machine >> assembly, not unlike what Chuck Moore does for the F18A. Forth is used >> to write the macro assembler. >> > The J1 uses micro-programming, the instructions are the control bits for > the internal CPU units, so it can do multiple transfers and logic/math > operations at the same time, just set the right bits. So you could do a > math operation, save the result, and return in one instruction. The J1 does not use microprogramming. Microprogramming is using instructions internal to the CPU which then control the operations of the CPU over multiple clock cycles. The J1 instructions run in a single clock cycle. I see no indication in the Verilog code this processor uses any internal instruction memory or that it uses more than one clock cycle per instruction. I think you are misusing the term microprogramming to refer to the fact that the J1 instructions use separate fields to directly control CPU functions. That is simply a matter of horizontal vs. vertical instruction format (less encoded vs. more encoded). The GA144 would be a vertical format with no fields within the instruction, just 5 bit opcodes to control the entire CPU. The J1 instruction format does have some unencoded fields for internal processor control. But that is only for the ALU and data op instructions. Other instructions usurp these fields for literal addresses or data. The fields of the data op instructions include a bit for return and can manipulate the return stack to pop and push data, but that's all. There is one bit that appears to be unused. The only operations that can be done in parallel is to perform a return in an instruction also performing any data op. With the independent T>R control bit an instruction can in parallel do R>PC, T>R and R>T. This would be a single instruction co-routine switch. I've never used coroutines and I expect few others have. When I mentioned separate processors I was referring to the fact that in my CPU design the data stack and ALU operate in parallel with the return stack and it's ALU along with the instruction fetch. I only explored the possibilities briefly, but a 16 bit instruction would have supported a fairly complete instruction set for each unit independently. The 18 bit memory of many FPGAs would support an even richer instruction set. I expect such a VLIW type instruction format to maximize parallelism and also provide for multiple Forth level instructions to be executed in parallel or at least higher level Forth instructions to be a single instruction rather than multiple, not just executing a return in parallel with a data op. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Cecil Bayona Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Mon, 25 Jul 2016 18:01:11 -0500 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="4c6149fda0f382b24075b7a1eefa3518"; logging-data="25850"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/TEw1ye9UmNXPDk4K/v3Ei" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:C4MgfcvcYYs051GDTU4o8pJP3VE= Xref: news.eternal-september.org comp.lang.vhdl:4518 comp.lang.forth:49741 On 7/25/2016 4:39 PM, rickman wrote: > On 7/25/2016 3:11 PM, Cecil Bayona wrote: >> On 7/25/2016 12:22 AM, rickman wrote: > > Diabetes runs in my family, but so far I have avoided it. Maybe because > at *only* 35 lbs overweight I am a lighter member. It's been awhile > since I was tested so I should do that. My last check was a doctor > doing the blood sugar tests with the little strips in a supermarket. I > had something small to eat some hours before and still was in the 70 > range I seem to recall. He said that was great! > > Normal blood is 100 if you have gone without food for 4 hours or more, 70 is too low to the point you need to eat something to bring it up so I'm not sure what kind of test they did. It used to be they would test for Ketones in your urine that was very inaccurate, the modern way is with a blood sample. Weight is a major factor in preventing Diabetes so try to keep your weight down and close to your optimum weight. Once you have diabetes it's hard to loose the weight. -- Cecil - k5nwa From newsfish@newsfish Thu Aug 1 00:37:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Mon, 25 Jul 2016 19:40:34 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 25 Jul 2016 23:40:36 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="32296"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/JPGm/WFx8/aw72ADzPZ4p" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:XJOQ3XrbuZHtTUUKJ1zHXCwRkAM= Xref: news.eternal-september.org comp.lang.vhdl:4519 comp.lang.forth:49743 On 7/25/2016 7:01 PM, Cecil Bayona wrote: > On 7/25/2016 4:39 PM, rickman wrote: >> On 7/25/2016 3:11 PM, Cecil Bayona wrote: >>> On 7/25/2016 12:22 AM, rickman wrote: > >> >> Diabetes runs in my family, but so far I have avoided it. Maybe because >> at *only* 35 lbs overweight I am a lighter member. It's been awhile >> since I was tested so I should do that. My last check was a doctor >> doing the blood sugar tests with the little strips in a supermarket. I >> had something small to eat some hours before and still was in the 70 >> range I seem to recall. He said that was great! >> >> > > Normal blood is 100 if you have gone without food for 4 hours or more, > 70 is too low to the point you need to eat something to bring it up so > I'm not sure what kind of test they did. It used to be they would test > for Ketones in your urine that was very inaccurate, the modern way is > with a blood sample. > > Weight is a major factor in preventing Diabetes so try to keep your > weight down and close to your optimum weight. Once you have diabetes > it's hard to loose the weight. This was perhaps 2 in the afternoon and I had only had some yogurt earlier in the morning. I was fasting to get the blood test done as I had heard that is how they do it, but I slipped and ate some yogurt. The strips are the ones where you prick your finger, put the blood on the strip and slip it into the glucometer. Web pages I found indicate blood sugar levels of 70 to 100 mg/dL are normal when fasting. Below 60 and they start to worry. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Jan Coombs Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Tue, 26 Jul 2016 11:04:41 +0100 Organization: A noiseless patient Spider Lines: 31 Message-ID: <20160726110441.73da10eb@HP-6550b> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="b60b49d38b5fde30cd476fa043121772"; logging-data="14959"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+d5PMy3l4H7pQ4i8tyrsxFGj28xaPWpzY=" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:DBUn6MiGq1EwHy+kPFhSNE41dzM= Xref: news.eternal-september.org comp.lang.vhdl:4520 comp.lang.forth:49764 On Mon, 25 Jul 2016 14:11:16 -0500 Cecil Bayona wrote: > On 7/25/2016 12:22 AM, rickman wrote: > > You really can't design async logic in FPGAs that I know > > of. It has to be custom chips. Achronix is developing > > async logic FPGAs, but I think they are intent on the really > > big customers only, small users need not apply. > > I have not looked into it but you might be right as the LUTS > have flip flops on their outputs and would need to be clocked. Yes, if a logic device uses LUTs, then it needs to latch the LUT output when it is stable, and the longest logic propagation time must fit between two clock edges. In the fine-grained Microsemi/Actel Flash FPGAs there are no LUTs, the programmable element is either logic or a flop. There are only eight synchronous library parts, and the majority of the rest are purely combinatorial. [1] Perhaps these parts could be used to synthesize async logic designs. Jan Coombs -- [1] IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide http://www.microsemi.com/document-portal/doc_view/130886-igloo-proasic3-smartfusion-and-fusion-macro-library-guide-for-software-v9-0 [2] https://en.wikipedia.org/wiki/Asynchronous_circuit From newsfish@newsfish Thu Aug 1 00:37:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Tue, 26 Jul 2016 11:13:00 -0400 Organization: A noiseless patient Spider Lines: 90 Message-ID: References: <20160726110441.73da10eb@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 26 Jul 2016 15:13:04 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="31971"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19H5hZ8i4vFYT24OfLNfkWI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <20160726110441.73da10eb@HP-6550b> Cancel-Lock: sha1:12O2/SuAADKyyMwL44X+zYhkfxE= Xref: news.eternal-september.org comp.lang.vhdl:4521 comp.lang.forth:49768 On 7/26/2016 6:04 AM, Jan Coombs wrote: > On Mon, 25 Jul 2016 14:11:16 -0500 > Cecil Bayona wrote: > >> On 7/25/2016 12:22 AM, rickman wrote: > >>> You really can't design async logic in FPGAs that I know >>> of. It has to be custom chips. Achronix is developing >>> async logic FPGAs, but I think they are intent on the really >>> big customers only, small users need not apply. >> >> I have not looked into it but you might be right as the LUTS >> have flip flops on their outputs and would need to be clocked. > > Yes, if a logic device uses LUTs, then it needs to latch the LUT > output when it is stable, and the longest logic propagation time > must fit between two clock edges. > > In the fine-grained Microsemi/Actel Flash FPGAs there are no > LUTs, the programmable element is either logic or a flop. There > are only eight synchronous library parts, and the majority of > the rest are purely combinatorial. [1] > > Perhaps these parts could be used to synthesize async logic > designs. I think there is some misunderstanding of the basic LUT-FF cell design. The output of the LUT is always available outside the logic cell. The FF can be used to register the output of the LUT or not. It can also be used to register another signal from outside the logic cell. So the presence of the FF in the logic cell has nothing to do with the ease of implementing async clocked logic in an FPGA. The reason FPGAs are not suited for async clocked logic is because this design method requires the specification of both max and min delays on logic paths. The logic specified by the user has a parallel path which is used to clock the output FF. This parallel path must have a minimum delay that is longer than the maximum delay of the logic. FPGAs are not specified in a way to show a design meets this requirement. If you wish to take it on yourself to figure out appropriate specifications for the various logic and routing paths within an FPGA, you can do your own timing analysis. Then you could design async clocked logic in that FPGA. But this would be a very difficult task without knowing details on the variations of timing across a large number of chips from a large number of batches. If the FPGA vendor makes any changes to the process (which do happen from time to time for yield purposes) your measurements are no longer valid or at least the margin provided by your tools is now suspect. I don't think you will find much speed improvement over just clocking the design synchronously. Yes, on the test bench you can see speed improvements. But once you allow for the three basic variations in timing, process, voltage and temperature you will likely see no real advantage and my find the async logic to be worse than sync logic because of the margins required. As someone pointed out, there will be power improvements. I have been told the clock tree in a large chip can dissipate half the power. That is pretty amazing, but when you think about the huge distributed capacitance and the many matched buffers required to keep the clock skew to a minimum across the chip, I shouldn't doubt this. The bottom line is asynchronously clocked CPU chips have been designed before but have never made an impact on the market. I recall one that was an 8051 I believe and I seem to recall an ARM being designed this way. Of course, the GA144 is the most notable and possibly the most successful example so far. None have made an impact on the market. Partly that is because one big advantage of the sync clocked device is that it can tell time! The digital world works off of timing. Nearly all interfaces require timing. Nearly all applications require timing. Adding a processor that free runs means another way has to be found to sync the processes to the outside world. Once you do that many of the speed advantages go away. We are on a road that gives us faster processors every year. The power for a given level of complexity in processors continues to decrease. Design an async clocked processor this year and next year it will be usurped by the next generation of sync clocked processor. It's hard to hit a moving target. I think FPGAs can be used best to design Forth processors using conventional logic techniques focusing on interesting CPU architectures rather than misusing the FPGA. This post got pretty long... not nearly a manifesto though... -- Rick C From newsfish@newsfish Thu Aug 1 00:37:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Tue, 26 Jul 2016 16:00:23 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 36 Message-ID: <2016Jul26.180023@mips.complang.tuwien.ac.at> References: <20160726110441.73da10eb@HP-6550b> Injection-Info: mx02.eternal-september.org; posting-host="d47d3421039fe8026514328ad0ebacae"; logging-data="15233"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+dMjVgABgw7Z7jA9uhGsb2" X-newsreader: xrn 10.00-beta-3 Cancel-Lock: sha1:KSo9cKgIi8hDL8NHW6DRLf6tjwY= Xref: news.eternal-september.org comp.lang.vhdl:4522 comp.lang.forth:49773 rickman writes: >I have been >told the clock tree in a large chip can dissipate half the power. IIRC the clock for the 21064 (1992) consumed 30% of the power, and the final driver of the clock had a gate length of 35cm. That was at 200MHz. Of course that could not scale, so quite some time ago they have divided the chips into smaller clock domains (and later also power domains); e.g., the Williamette (first Pentium 4, 2001, 1400MHz) had a very fast integer ALU core that, however, did not include multiplication or shifting. So integer multiplication and shifting were achieved by shipping the data over to the FPU, and then shipping the result back. The data had to cross several clock domain borders on the way, losing a cycle on every crossing; that's why integer multiplication is slower than FP multiplication on the Pentium 4. >The bottom line is asynchronously clocked CPU chips have been designed >before but have never made an impact on the market. I recall one that >was an 8051 I believe and I seem to recall an ARM being designed this >way. Of course, the GA144 is the most notable and possibly the most >successful example so far. AFAIK the GA144 is not an asynchronous design; it's a clocked design, but the clock is generated internally (one clock per core). At least an earlier chip by Chuck Moore worked that way (IIRC the MuP21), and the idea that this was an async design was already rampant (and contradicted) at the time. - anton -- M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html New standard: http://www.forth200x.org/forth200x.html EuroForth 2016: http://www.euroforth.org/ef16/ From newsfish@newsfish Thu Aug 1 00:37:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Tue, 26 Jul 2016 12:58:05 -0400 Organization: A noiseless patient Spider Lines: 51 Message-ID: References: <20160726110441.73da10eb@HP-6550b> <2016Jul26.180023@mips.complang.tuwien.ac.at> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 26 Jul 2016 16:58:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="22730"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+b4qHoykaO85ITJfeeEqsf" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <2016Jul26.180023@mips.complang.tuwien.ac.at> Cancel-Lock: sha1:W0BHH0ArACJ4hkuXQtk6Arls3aM= Xref: news.eternal-september.org comp.lang.vhdl:4523 comp.lang.forth:49778 On 7/26/2016 12:00 PM, Anton Ertl wrote: > rickman writes: >> I have been >> told the clock tree in a large chip can dissipate half the power. > > IIRC the clock for the 21064 (1992) consumed 30% of the power, and the > final driver of the clock had a gate length of 35cm. That was at > 200MHz. > > Of course that could not scale, so quite some time ago they have > divided the chips into smaller clock domains (and later also power > domains); e.g., the Williamette (first Pentium 4, 2001, 1400MHz) had a > very fast integer ALU core that, however, did not include > multiplication or shifting. So integer multiplication and shifting > were achieved by shipping the data over to the FPU, and then shipping > the result back. The data had to cross several clock domain borders > on the way, losing a cycle on every crossing; that's why integer > multiplication is slower than FP multiplication on the Pentium 4. > >> The bottom line is asynchronously clocked CPU chips have been designed >> before but have never made an impact on the market. I recall one that >> was an 8051 I believe and I seem to recall an ARM being designed this >> way. Of course, the GA144 is the most notable and possibly the most >> successful example so far. > > AFAIK the GA144 is not an asynchronous design; it's a clocked design, > but the clock is generated internally (one clock per core). At least > an earlier chip by Chuck Moore worked that way (IIRC the MuP21), and > the idea that this was an async design was already rampant (and > contradicted) at the time. None of the CPUs described as "asynchronous" are truly that. They are asynchronously clocked. In the GA144 there are delay paths that are activated for each type of instruction with a delay matched to the time taken for that class of instruction. Someone here argued with me that this constituted an astable oscillator but that is just semantics. Of course it will oscillate as the end of any one clock period has to coincide with the beginning of the next. But just like all the other "async" CPUs, the GA144 is async in the same way, asynchronously clocked. True asynchronous logic is different. It has no clocked registers. The logic is self latching like RS FFs and has to be designed very differently even from asynchronously clocked logic. I remember an async logic state machine available many years ago when PLDs were still new. It was true async logic, but never made much of a dent in the market. I saw it used on one design which likely became out of date due to the part becoming obsolete not too long after. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Wed, 27 Jul 2016 09:39:35 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 18 Message-ID: <2016Jul27.113935@mips.complang.tuwien.ac.at> References: <20160726110441.73da10eb@HP-6550b> <2016Jul26.180023@mips.complang.tuwien.ac.at> Injection-Info: mx02.eternal-september.org; posting-host="d47d3421039fe8026514328ad0ebacae"; logging-data="3463"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+koh3256O4j0wMe/O8+XGj" X-newsreader: xrn 10.00-beta-3 Cancel-Lock: sha1:DaiXmO7e/jXIFuyDT1idVMzCID8= Xref: news.eternal-september.org comp.lang.vhdl:4524 comp.lang.forth:49793 rickman writes: >On 7/26/2016 12:00 PM, Anton Ertl wrote: >In the GA144 there are delay paths that are >activated for each type of instruction with a delay matched to the time >taken for that class of instruction. So you no longer have to do three nops before (or was it after?) a full-length "+"? That's new then. The way I understood the description of the MuP21 in the earlier discussion, it had some kind of on-chip oscillator that clocked the whole core, and the addition could take up to four cycles. - anton -- M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html New standard: http://www.forth200x.org/forth200x.html EuroForth 2016: http://www.euroforth.org/ef16/ From newsfish@newsfish Thu Aug 1 00:37:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Wed, 27 Jul 2016 10:01:57 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <20160726110441.73da10eb@HP-6550b> <2016Jul26.180023@mips.complang.tuwien.ac.at> <2016Jul27.113935@mips.complang.tuwien.ac.at> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 27 Jul 2016 14:02:08 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="24572"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18pmf7MtB0tOHNBMycjmKSY" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <2016Jul27.113935@mips.complang.tuwien.ac.at> Cancel-Lock: sha1:QX0m58cTgMj/tndT2Awi9QvHlrU= Xref: news.eternal-september.org comp.lang.vhdl:4525 comp.lang.forth:49799 On 7/27/2016 5:39 AM, Anton Ertl wrote: > rickman writes: >> On 7/26/2016 12:00 PM, Anton Ertl wrote: >> In the GA144 there are delay paths that are >> activated for each type of instruction with a delay matched to the time >> taken for that class of instruction. > > So you no longer have to do three nops before (or was it after?) a > full-length "+"? That's new then. The way I understood the > description of the MuP21 in the earlier discussion, it had some kind > of on-chip oscillator that clocked the whole core, and the addition > could take up to four cycles. All of the ALU instructions are timed with the same timing path. The add requires extra time for the carry to settle, so one nop is required before an addition unless the previous instruction does not modify either of the two operands in which case no nop is needed. Other, non-alu instructions have various timings and have other timing paths. It is definitely *not* one timing path for the "whole core". I don't recall the various classes of instructions that have separate timing from the ALU, but at one point I made a timing based tool in a spread sheet. Type in the instructions and it gave you the timing. I think it even accounted for instruction word boundaries which require additional timing for the next word fetch under some conditions. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Wed, 27 Jul 2016 18:15:20 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 27 Jul 2016 22:15:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="9102"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/eOLvEyNrAkYJ5m+/j56yJ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:CM49oce1eCXHw60qOLkcRREN8TA= Xref: news.eternal-september.org comp.lang.vhdl:4526 comp.lang.forth:49823 On 7/24/2016 11:01 PM, rickman wrote: > On 7/24/2016 10:29 PM, rickman wrote: >> I wonder how hard it would be to write a Forth in VHDL? It would likely >> be as easy to do in non-synthesizable code as any other language. It >> might be a bit harder in synthesizable code. For one, the I/O would >> need to be constructed from scratch based on some hardware interface. >> The non-synthesizable code could just read from a file... I wonder if >> you can read from the console in VHDL? I've never tried that before. > > I did a little digging and it looks like you *can* do console I/O in > VHDL using the textio package. So I can't think of anything to stop a > vforth from being written... unless the vforth name has already been used. I took a look at a C Forth implementation, pForth. I'm not sure I follow everything he is doing, I guess my C is a bit rusty. I see he used a large CASE statement for primitive words. I'm not clear on how the inner interpreter works through the XTs in a word definition for words compiled into other words. I suppose it is just a matter of indexes into the dictionary (or pointers in C) but I don't see the code he is using to manipulate them. He uses a ton of defines which hide the details and it is a bit of work for me to try to figure this out. I'll get it sooner or later. I just need to keep reading. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Jan Coombs Newsgroups: comp.lang.vhdl,comp.lang.forth Subject: Re: Forth in VHDL Date: Wed, 27 Jul 2016 22:46:46 +0100 Organization: A noiseless patient Spider Lines: 42 Message-ID: <20160727224646.7143824d@HP-6550b> References: <20160726110441.73da10eb@HP-6550b> <2016Jul26.180023@mips.complang.tuwien.ac.at> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="b60b49d38b5fde30cd476fa043121772"; logging-data="21454"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18sA0E3/oe3pczz5AfQN4ToO8mat4iCaPA=" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:+RlcZTi/YhP/DV0e4KI7tUkXllk= Xref: news.eternal-september.org comp.lang.vhdl:4527 comp.lang.forth:49824 On Tue, 26 Jul 2016 16:00:23 GMT anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote: > AFAIK the GA144 is not an asynchronous design; it's a clocked > design, but the clock is generated internally (one clock per > core). At least an earlier chip by Chuck Moore worked that > way (IIRC the MuP21), and the idea that this was an async > design was already rampant (and contradicted) at the time. Yes, both Green Arrays and IntellaSys chips [1][2] need 'nop' or another instruction that does not alter T or S to precede an addition. This is in order to allow the carry to stabilise. The earlier manual states that the carry propagates nine bits in each processor cycle. The GA144 is asynchronous at the boundary of each processor module. AFAICTell this is a common 'asynchronous' design method. Otherwise the wikkipedia article [3] "Asynchronous CPU" needs revision. There are perhaps zero recent CPU designs built of purely asynchronous logic? (And, for good patent readers, what are Achronix async FPGA parts made of) The most efficient asynchronous signalling method for random logic seems to be "four state encoding". This uses two wires to carry a single bit and a 'time stamp'. The 'time stamp' is the data cycle to which the data bit belongs, mod 2. The encoding is arranged so that in the transition to each new time phase only one of the two wires changes state, regardless of whether or not the data has changed. This avoids race problems between the two wires. I'd like to know what the cost for this is in transistors, having guessed it is about 10 _times_ more than simple conventional logic. Jan Coombs -- [1] DB001-110412-F18A.pdf "F18A Technology Reference" pg8 [2] "SEAforth 40C18 Data Sheet (Preliminary)" pg44 [3] https://en.wikipedia.org/wiki/Asynchronous_circuit From newsfish@newsfish Thu Aug 1 00:37:33 2024 X-Received: by 10.157.51.3 with SMTP id f3mr35336375otc.45.1469814282471; Fri, 29 Jul 2016 10:44:42 -0700 (PDT) X-Received: by 10.36.20.201 with SMTP id 192mr193148itg.8.1469814282449; Fri, 29 Jul 2016 10:44:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no5769737ith.0!news-out.google.com!d130ni18403ith.0!nntp.google.com!f6no5769730ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 29 Jul 2016 10:44:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2a02:2f0e:1d5:b800:30fc:c977:32b4:1dc7; posting-account=mlC8NgoAAADaY-YH1JzYEHBHe006s3C- NNTP-Posting-Host: 2a02:2f0e:1d5:b800:30fc:c977:32b4:1dc7 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: generalized agregate From: virgilx13@gmail.com Injection-Date: Fri, 29 Jul 2016 17:44:42 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4528 Hi, I`m kind of new on FPGA design world so forgive my mistakes. I didn't even = knew how to search this problem, so maybe the title is also wrong. I have an array / vector and I want to generate a new array by processing t= he first. A simple example of what I need is that every i-th element from t= he new array is the sum of the i-1, i, and i+1 elements from the first one. I know this can be done very easily in a sequential manner by iterating thr= ough the array. I was wandering if there any kind of assigning expression t= hat would generalize this and make this a parallel operation.(like in math:= new[i] :=3D old[i - 1] + old[i] + old[i + 1], where i =E2=88=88 (1, n) ). any ideas? thanks! From newsfish@newsfish Thu Aug 1 00:37:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: generalized agregate Date: Fri, 29 Jul 2016 15:32:39 -0400 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Fri, 29 Jul 2016 19:32:45 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="21131"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+yHOsINsiM7eYNBFACasNO" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:GYTjaRoZygAJ5DWjWSE6z4xTjiU= Xref: news.eternal-september.org comp.lang.vhdl:4529 On 7/29/2016 1:44 PM, virgilx13@gmail.com wrote: > Hi, I`m kind of new on FPGA design world so forgive my mistakes. I > didn't even knew how to search this problem, so maybe the title is > also wrong. > > I have an array / vector and I want to generate a new array by > processing the first. A simple example of what I need is that every > i-th element from the new array is the sum of the i-1, i, and i+1 > elements from the first one. I know this can be done very easily in a > sequential manner by iterating through the array. I was wandering if > there any kind of assigning expression that would generalize this and > make this a parallel operation.(like in math: new[i] := old[i - 1] + > old[i] + old[i + 1], where i ∈ (1, n) ). Yes, that is not hard, but what do you want to do with the end elements? Is your vector large enough to have inputs for i-1 when i is 1 and i+1 when i is n? New(1 to N) <= Old(0 to N-1) + Old(1 to N) + Old(2 to N+1); But you will need to define the operator '+' for the vector data type you are using. Easy enough, no? I'm pressed for time, but in a nutshell, the definition of '+' will contain the iterative loop you would otherwise put directly in your current code. lol -- Rick C From newsfish@newsfish Thu Aug 1 00:37:34 2024 X-Received: by 10.66.170.208 with SMTP id ao16mr70321400pac.9.1470424273058; Fri, 05 Aug 2016 12:11:13 -0700 (PDT) X-Received: by 10.36.123.135 with SMTP id q129mr233360itc.1.1470424273014; Fri, 05 Aug 2016 12:11:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no7652053ith.0!news-out.google.com!d130ni25720ith.0!nntp.google.com!f6no7652047ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Aug 2016 12:11:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> Subject: Re: Gray Code From: Ilya Kalistru Injection-Date: Fri, 05 Aug 2016 19:11:13 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4530 On Monday, June 13, 2016 at 10:31:06 AM UTC+3, rickman wrote: > On 6/13/2016 1:36 AM, rickman wrote: > > I was reading up on Gray codes and figured out a fairly simple algorithm > > for counting up or down with Gray codes directly rather than using a > > binary counter which is converted to Gray code. It has not been > > extensively tested. I don't think it will work for vectors declared > > with a "to" range rather than a "downto" range. I should have used > > 'left and 'right instead of 'high and 'low, but I don't know how to > > construct a loop that goes in either direction. I'll need to dig around > > to see how that might be done. > > > > I got the idea from a verbal description of a Gray code that defined the > > bit to change as the least significant bit that gives even parity with > > all the higher bits. They didn't say it just like that, but once I > > thought about it I realized that was what they should have said. > > Counting down is the same rule, but odd parity. I didn't synthesize it > > to see how complex the logic is, but I don't think it should be too bad. > > > > Here is the code. Any suggestions are welcome. > > > > Function CalcGray (cntr : unsigned; UpDwn : std_logic) > > return unsigned is > > variable CntrHigh : natural := cntr'high; > > variable CntrLow : natural := cntr'low; > > variable Result : unsigned (cntr'range) := cntr; > > variable ParityWord : unsigned (CntrHigh downto CntrLow) > > := (others => '0'); > > begin > > ParityWord(CntrHigh) := Result(CntrHigh); > > for i in CntrHigh-1 downto CntrLow loop > > ParityWord(i) := ParityWord(i+1) xor Result(i); > > end loop; > > for i in CntrLow to CntrHigh loop > > if ((UpDwn = not ParityWord(i)) or (i = CntrHigh)) then > > Result(i) := not Result(i); > > exit; > > end if; > > end loop; > > return Result; > > end CalcGray; > > > > Function NextGray (cntr : unsigned) return unsigned is > > begin > > return CalcGray(cntr, '1'); > > end NextGray; > > > > Function PrevGray (cntr : unsigned) return unsigned is > > begin > > return CalcGray(cntr, '0'); > > end PrevGray; > > Here is an improved version of the main routine that works for ascending > or descending ranges of the input signal. > > Function CalcGray (Cntr : unsigned; UpDwn : std_logic) > return unsigned is > variable CntrLeft : natural := Cntr'LEFT; > variable Result : unsigned (cntr'RANGE) := cntr; > variable ParityWord : unsigned (Cntr'RANGE); > variable PrevParity : std_logic := '0'; > begin > for i in ParityWord'RANGE loop > ParityWord(i) := PrevParity xor Result(i); > PrevParity := ParityWord(i); > end loop; > for i in Result'REVERSE_RANGE loop > if ((i = CntrLeft) or (UpDwn /= ParityWord(i))) then > Result(i) := not Result(i); -- found the bit to toggle > exit; > end if; > end loop; > return Result; > end CalcGray; > > -- > > Rick C I've always used the simplest possible way to do that: B <= Bin2Gray(Gray2Bin(A) + 1); And I've never have had any performance problems with it. Vivado manage to optimize it quite well and employs carry chain for that. And it's look like it's even better than Rick's sophisticated method: http://imgur.com/Hu2MuMr From newsfish@newsfish Thu Aug 1 00:37:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Fri, 5 Aug 2016 16:57:08 -0400 Organization: A noiseless patient Spider Lines: 100 Message-ID: References: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 5 Aug 2016 20:57:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="fa709bca2c29e91a32a18acfb77d2487"; logging-data="1078"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/jQnXXMS3QHUX3K7AWKr5y" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> Cancel-Lock: sha1:iHSpAhETHOMs/C3rfUgjLkhkjjE= Xref: news.eternal-september.org comp.lang.vhdl:4531 On 8/5/2016 3:11 PM, Ilya Kalistru wrote: > On Monday, June 13, 2016 at 10:31:06 AM UTC+3, rickman wrote: >> On 6/13/2016 1:36 AM, rickman wrote: >>> I was reading up on Gray codes and figured out a fairly simple algorithm >>> for counting up or down with Gray codes directly rather than using a >>> binary counter which is converted to Gray code. It has not been >>> extensively tested. I don't think it will work for vectors declared >>> with a "to" range rather than a "downto" range. I should have used >>> 'left and 'right instead of 'high and 'low, but I don't know how to >>> construct a loop that goes in either direction. I'll need to dig around >>> to see how that might be done. >>> >>> I got the idea from a verbal description of a Gray code that defined the >>> bit to change as the least significant bit that gives even parity with >>> all the higher bits. They didn't say it just like that, but once I >>> thought about it I realized that was what they should have said. >>> Counting down is the same rule, but odd parity. I didn't synthesize it >>> to see how complex the logic is, but I don't think it should be too bad. >>> >>> Here is the code. Any suggestions are welcome. >>> >>> Function CalcGray (cntr : unsigned; UpDwn : std_logic) >>> return unsigned is >>> variable CntrHigh : natural := cntr'high; >>> variable CntrLow : natural := cntr'low; >>> variable Result : unsigned (cntr'range) := cntr; >>> variable ParityWord : unsigned (CntrHigh downto CntrLow) >>> := (others => '0'); >>> begin >>> ParityWord(CntrHigh) := Result(CntrHigh); >>> for i in CntrHigh-1 downto CntrLow loop >>> ParityWord(i) := ParityWord(i+1) xor Result(i); >>> end loop; >>> for i in CntrLow to CntrHigh loop >>> if ((UpDwn = not ParityWord(i)) or (i = CntrHigh)) then >>> Result(i) := not Result(i); >>> exit; >>> end if; >>> end loop; >>> return Result; >>> end CalcGray; >>> >>> Function NextGray (cntr : unsigned) return unsigned is >>> begin >>> return CalcGray(cntr, '1'); >>> end NextGray; >>> >>> Function PrevGray (cntr : unsigned) return unsigned is >>> begin >>> return CalcGray(cntr, '0'); >>> end PrevGray; >> >> Here is an improved version of the main routine that works for ascending >> or descending ranges of the input signal. >> >> Function CalcGray (Cntr : unsigned; UpDwn : std_logic) >> return unsigned is >> variable CntrLeft : natural := Cntr'LEFT; >> variable Result : unsigned (cntr'RANGE) := cntr; >> variable ParityWord : unsigned (Cntr'RANGE); >> variable PrevParity : std_logic := '0'; >> begin >> for i in ParityWord'RANGE loop >> ParityWord(i) := PrevParity xor Result(i); >> PrevParity := ParityWord(i); >> end loop; >> for i in Result'REVERSE_RANGE loop >> if ((i = CntrLeft) or (UpDwn /= ParityWord(i))) then >> Result(i) := not Result(i); -- found the bit to toggle >> exit; >> end if; >> end loop; >> return Result; >> end CalcGray; >> >> -- >> >> Rick C > > I've always used the simplest possible way to do that: > > B <= Bin2Gray(Gray2Bin(A) + 1); Uh, don't you have to write the two conversion routines? How did you do those? > And I've never have had any performance problems with it. Vivado manage to optimize it quite well and employs carry chain for that. Performance "problems" depend on the performance requirements. > And it's look like it's even better than Rick's sophisticated method: > http://imgur.com/Hu2MuMr What were the sizes and envelope code you used? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:34 2024 X-Received: by 10.36.110.210 with SMTP id w201mr5178057itc.7.1470449294039; Fri, 05 Aug 2016 19:08:14 -0700 (PDT) X-Received: by 10.36.50.145 with SMTP id j139mr295097ita.9.1470449294019; Fri, 05 Aug 2016 19:08:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no7722848ith.0!news-out.google.com!d68ni18087ith.0!nntp.google.com!f6no7701340ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Aug 2016 19:08:13 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.27.165; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.27.165 References: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <20fc2c8a-a3f7-45f2-8948-b463486166d5@googlegroups.com> Subject: Re: Gray Code From: diogratia@gmail.com Injection-Date: Sat, 06 Aug 2016 02:08:14 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4532 On Saturday, August 6, 2016 at 8:57:10 AM UTC+12, rickman wrote: > On 8/5/2016 3:11 PM, Ilya Kalistru wrote: > > On Monday, June 13, 2016 at 10:31:06 AM UTC+3, rickman wrote: > >> On 6/13/2016 1:36 AM, rickman wrote: > >>> I was reading up on Gray codes and figured out a fairly simple algorithm > >>> for counting up or down with Gray codes directly rather than using a > >>> binary counter which is converted to Gray code. It has not been > >>> extensively tested. I don't think it will work for vectors declared > >>> with a "to" range rather than a "downto" range. I should have used > >>> 'left and 'right instead of 'high and 'low, but I don't know how to > >>> construct a loop that goes in either direction. I'll need to dig around > >>> to see how that might be done. > >>> > >>> I got the idea from a verbal description of a Gray code that defined the > >>> bit to change as the least significant bit that gives even parity with > >>> all the higher bits. They didn't say it just like that, but once I > >>> thought about it I realized that was what they should have said. > >>> Counting down is the same rule, but odd parity. I didn't synthesize it > >>> to see how complex the logic is, but I don't think it should be too bad. > >>> > >>> Here is the code. Any suggestions are welcome. > >>> > >>> Function CalcGray (cntr : unsigned; UpDwn : std_logic) > >>> return unsigned is > >>> variable CntrHigh : natural := cntr'high; > >>> variable CntrLow : natural := cntr'low; > >>> variable Result : unsigned (cntr'range) := cntr; > >>> variable ParityWord : unsigned (CntrHigh downto CntrLow) > >>> := (others => '0'); > >>> begin > >>> ParityWord(CntrHigh) := Result(CntrHigh); > >>> for i in CntrHigh-1 downto CntrLow loop > >>> ParityWord(i) := ParityWord(i+1) xor Result(i); > >>> end loop; > >>> for i in CntrLow to CntrHigh loop > >>> if ((UpDwn = not ParityWord(i)) or (i = CntrHigh)) then > >>> Result(i) := not Result(i); > >>> exit; > >>> end if; > >>> end loop; > >>> return Result; > >>> end CalcGray; > >>> > >>> Function NextGray (cntr : unsigned) return unsigned is > >>> begin > >>> return CalcGray(cntr, '1'); > >>> end NextGray; > >>> > >>> Function PrevGray (cntr : unsigned) return unsigned is > >>> begin > >>> return CalcGray(cntr, '0'); > >>> end PrevGray; > >> > >> Here is an improved version of the main routine that works for ascending > >> or descending ranges of the input signal. > >> > >> Function CalcGray (Cntr : unsigned; UpDwn : std_logic) > >> return unsigned is > >> variable CntrLeft : natural := Cntr'LEFT; > >> variable Result : unsigned (cntr'RANGE) := cntr; > >> variable ParityWord : unsigned (Cntr'RANGE); > >> variable PrevParity : std_logic := '0'; > >> begin > >> for i in ParityWord'RANGE loop > >> ParityWord(i) := PrevParity xor Result(i); > >> PrevParity := ParityWord(i); > >> end loop; > >> for i in Result'REVERSE_RANGE loop > >> if ((i = CntrLeft) or (UpDwn /= ParityWord(i))) then > >> Result(i) := not Result(i); -- found the bit to toggle > >> exit; > >> end if; > >> end loop; > >> return Result; > >> end CalcGray; > >> > >> -- > >> > >> Rick C > > > > I've always used the simplest possible way to do that: > > > > B <= Bin2Gray(Gray2Bin(A) + 1); > > Uh, don't you have to write the two conversion routines? How did you > do those? > > > > And I've never have had any performance problems with it. Vivado manage to optimize it quite well and employs carry chain for that. > > Performance "problems" depend on the performance requirements. > > > > And it's look like it's even better than Rick's sophisticated method: > > http://imgur.com/Hu2MuMr > > What were the sizes and envelope code you used? Both of the shown schematics have 16 bit inputs/outputs. The noticeable difference is you have an up/down control while the smaller only increments. Yours resembles the combinatorial portion of an up/down gray counter. You can throw out around half the logic by only providing increment (or making UpDwn a static value allowing optimization). From newsfish@newsfish Thu Aug 1 00:37:35 2024 X-Received: by 10.129.164.13 with SMTP id b13mr1147529ywh.48.1470481190970; Sat, 06 Aug 2016 03:59:50 -0700 (PDT) X-Received: by 10.36.111.147 with SMTP id x141mr348349itb.6.1470481190924; Sat, 06 Aug 2016 03:59:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!j37no7005333qta.0!news-out.google.com!d130ni26385ith.0!nntp.google.com!f6no7795730ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Aug 2016 03:59:50 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Gray Code From: Ilya Kalistru Injection-Date: Sat, 06 Aug 2016 10:59:50 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 35 Xref: news.eternal-september.org comp.lang.vhdl:4533 > Uh, don't you have to write the two conversion routines? How did you > do those? Gray encoding is ubiquitous and I just have this functions in my "frequently used functions" package. function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is variable Bin_var : STD_LOGIC_VECTOR(Gray'range); begin Bin_var := (others => '0'); Bin_var(Gray'high) := Gray(Gray'high); for i in Gray'high-1 downto 0 loop Bin_var(i):= Bin_var(i+1) xor Gray(i); end loop; return Bin_var; end function Gray2Bin; > What were the sizes and envelope code you used? .. entity Add is Port ( clk : in std_logic; A : in unsigned(15 downto 0); B : out unsigned(15 downto 0); C : in unsigned(15 downto 0); D : out unsigned(15 downto 0) ); end Add; architecture Behavioral of Add is ... begin B <= Bin2Gray(Gray2Bin(A) + 1) when rising_edge(clk); D <= CalcGray(C, '1') when rising_edge(clk); end Behavioral; From newsfish@newsfish Thu Aug 1 00:37:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Sat, 6 Aug 2016 14:57:38 -0400 Organization: A noiseless patient Spider Lines: 56 Message-ID: References: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 6 Aug 2016 18:57:38 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="aa7aced67b1ffdae46494c18a1065d63"; logging-data="27270"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+EXbrVeekEOCrt7Loil1W1" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:pOoYRdU3gpdApuNSitkJ5OjCdrg= Xref: news.eternal-september.org comp.lang.vhdl:4534 On 8/6/2016 6:59 AM, Ilya Kalistru wrote: > >> Uh, don't you have to write the two conversion routines? How did you >> do those? > > Gray encoding is ubiquitous and I just have this functions in my "frequently used functions" package. > > function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is > variable Bin_var : STD_LOGIC_VECTOR(Gray'range); > begin > Bin_var := (others => '0'); > Bin_var(Gray'high) := Gray(Gray'high); > for i in Gray'high-1 downto 0 loop > Bin_var(i):= Bin_var(i+1) xor Gray(i); > end loop; > return Bin_var; > end function Gray2Bin; > >> What were the sizes and envelope code you used? > > ... > entity Add is > Port ( > clk : in std_logic; > A : in unsigned(15 downto 0); > B : out unsigned(15 downto 0); > C : in unsigned(15 downto 0); > D : out unsigned(15 downto 0) > ); > end Add; > > architecture Behavioral of Add is > .... > begin > B <= Bin2Gray(Gray2Bin(A) + 1) when rising_edge(clk); > D <= CalcGray(C, '1') when rising_edge(clk); > end Behavioral; Thanks. What about Bin2Gray? I'd like to try your code in my synthesis. In general, I don't find optimization to work all that well for many functions. It can work ok for smaller code sections, so maybe this is one that happens to do well with many synthesizers, or maybe the description you use turns out to be optimal in spite of the apparent simplicity of the description I used. For example, your code above would use an adder chain along with the explicit chain described in Gray2Bin (don't know about Bin2Gray) while my code has two explicit chains. This could be simpler since the adder carry chain is embedded in the logic elements in most FPGA families. I've wondered just how much complexity the exit in the second loop adds. Coding without the exit might simplify the logic. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Gray Code Newsgroups: comp.lang.vhdl References: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 07 Aug 2016 07:05:09 GMT Lines: 57 Message-ID: <57a6dda4$0$2751$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 2dbd9eb1.news.astraweb.com X-Trace: DXC=AKdBoNlR_JA5\iVS6:P;:IL?0kYOcDh@JZD3?OaX:SkM4B81KWZLGd@ On 8/6/2016 6:59 AM, Ilya Kalistru wrote: >> >>> Uh, don't you have to write the two conversion routines? How did you >>> do those? >> >> Gray encoding is ubiquitous and I just have this functions in my >> "frequently used functions" package. >> >> function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return >> STD_LOGIC_VECTOR is >> variable Bin_var : STD_LOGIC_VECTOR(Gray'range); >> begin >> Bin_var := (others => '0'); Bin_var(Gray'high) := Gray (Gray'high); >> for i in Gray'high-1 downto 0 loop >> Bin_var(i):= Bin_var(i+1) xor Gray(i); >> end loop; >> return Bin_var; >> end function Gray2Bin; >> >>> What were the sizes and envelope code you used? >> >> ... >> entity Add is >> Port ( >> clk : in std_logic; >> A : in unsigned(15 downto 0); B : out unsigned(15 downto 0); >> C : in unsigned(15 downto 0); D : out unsigned(15 downto 0) ); >> end Add; >> >> architecture Behavioral of Add is .... >> begin >> B <= Bin2Gray(Gray2Bin(A) + 1) when rising_edge(clk); >> D <= CalcGray(C, '1') when rising_edge(clk); >> end Behavioral; > > Thanks. What about Bin2Gray? I'd like to try your code in my > synthesis. Here's my one that I've been using (variants of) since last century: function binary_to_gray ( b : unsigned ) return std_logic_vector is variable bcopy : std_logic_vector(b'length-1 downto 0) := std_logic_vector(b); begin return std_logic_vector(bcopy xor ('0' & bcopy(bcopy'high downto 1))); end function binary_to_gray; Note that (unlike gray to binary) this one doesn't need long chains of logic. Allan From newsfish@newsfish Thu Aug 1 00:37:35 2024 X-Received: by 10.36.110.210 with SMTP id w201mr9806551itc.7.1470554309317; Sun, 07 Aug 2016 00:18:29 -0700 (PDT) X-Received: by 10.36.115.15 with SMTP id y15mr430139itb.8.1470554309295; Sun, 07 Aug 2016 00:18:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no7989890ith.0!news-out.google.com!d130ni27249ith.0!nntp.google.com!f6no7989885ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Aug 2016 00:18:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Gray Code From: Ilya Kalistru Injection-Date: Sun, 07 Aug 2016 07:18:29 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4536 On Saturday, August 6, 2016 at 9:57:40 PM UTC+3, rickman wrote: > On 8/6/2016 6:59 AM, Ilya Kalistru wrote: > > > >> Uh, don't you have to write the two conversion routines? How did you > >> do those? > > > > Gray encoding is ubiquitous and I just have this functions in my "frequently used functions" package. > > > > function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is > > variable Bin_var : STD_LOGIC_VECTOR(Gray'range); > > begin > > Bin_var := (others => '0'); > > Bin_var(Gray'high) := Gray(Gray'high); > > for i in Gray'high-1 downto 0 loop > > Bin_var(i):= Bin_var(i+1) xor Gray(i); > > end loop; > > return Bin_var; > > end function Gray2Bin; > > > >> What were the sizes and envelope code you used? > > > > ... > > entity Add is > > Port ( > > clk : in std_logic; > > A : in unsigned(15 downto 0); > > B : out unsigned(15 downto 0); > > C : in unsigned(15 downto 0); > > D : out unsigned(15 downto 0) > > ); > > end Add; > > > > architecture Behavioral of Add is > > .... > > begin > > B <= Bin2Gray(Gray2Bin(A) + 1) when rising_edge(clk); > > D <= CalcGray(C, '1') when rising_edge(clk); > > end Behavioral; > > Thanks. What about Bin2Gray? I'd like to try your code in my synthesis. > > In general, I don't find optimization to work all that well for many > functions. It can work ok for smaller code sections, so maybe this is > one that happens to do well with many synthesizers, or maybe the > description you use turns out to be optimal in spite of the apparent > simplicity of the description I used. For example, your code above > would use an adder chain along with the explicit chain described in > Gray2Bin (don't know about Bin2Gray) while my code has two explicit > chains. This could be simpler since the adder carry chain is embedded > in the logic elements in most FPGA families. > > I've wondered just how much complexity the exit in the second loop adds. > Coding without the exit might simplify the logic. > > -- > > Rick C function Bin2Gray (Bin : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is variable Gray_var : STD_LOGIC_VECTOR(Bin'range); begin Gray_var(Gray_var'high) := Bin(bin'high); for i in 0 to bin'high - 1 loop Gray_var(i) := Bin(i) xor Bin(i + 1); end loop; return Gray_var; end function Bin2Gray; function Bin2Gray (Bin : in unsigned) return unsigned is begin return unsigned(Bin2Gray(std_logic_vector(Bin))); end function Bin2Gray; function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is variable Bin_var : STD_LOGIC_VECTOR(Gray'range); begin Bin_var := (others => '0'); Bin_var(Gray'high) := Gray(Gray'high); for i in Gray'high-1 downto 0 loop Bin_var(i):= Bin_var(i+1) xor Gray(i); end loop; return Bin_var; end function Gray2Bin; function Gray2Bin (Gray : in unsigned) return unsigned is begin return unsigned(Gray2Bin(std_logic_vector(Gray))); end function Gray2Bin; From newsfish@newsfish Thu Aug 1 00:37:36 2024 X-Received: by 10.36.228.8 with SMTP id o8mr6045691ith.11.1470927315088; Thu, 11 Aug 2016 07:55:15 -0700 (PDT) X-Received: by 10.36.115.15 with SMTP id y15mr569662itb.8.1470927315065; Thu, 11 Aug 2016 07:55:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no9135965ith.0!news-out.google.com!d130ni31907ith.0!nntp.google.com!f6no9135960ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Aug 2016 07:55:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: upside down generics or so From: Ilya Kalistru Injection-Date: Thu, 11 Aug 2016 14:55:15 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4537 Sometimes I design complex pipeline which splits on several pipelines at so= me point and then these branch pipelines are joined in one pipeline again. | root pipeline | |\ |\\ ||| branch pipelines |// joint point | =20 At the pipeline joint point data from different branches have to be aligne= d relatively to each other, so sometimes I have to add shift registers to s= horter branch pipelines. Branch pipelines usually consist of several module= s and added delays depends on the latencies of each module. As long as modu= les can be changed and their latency can be changed, I have to adjust delay= s. Is there a way to set latency of the module as some =E2=80=9Cproperty=E2=80= =9D in it, so that a top module could read it and adjust delay lines? Somet= hing like reversed generics =E2=80=93 generics pass parameter to a module b= ut I need to pass it from the module. Any ideas? From newsfish@newsfish Thu Aug 1 00:37:36 2024 X-Received: by 10.200.46.149 with SMTP id h21mr7187400qta.3.1470933018255; Thu, 11 Aug 2016 09:30:18 -0700 (PDT) X-Received: by 10.36.91.205 with SMTP id g196mr611865itb.0.1470933018217; Thu, 11 Aug 2016 09:30:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!j37no7962050qta.0!news-out.google.com!d130ni31949ith.0!nntp.google.com!f6no9179158ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Aug 2016 09:30:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> Subject: Re: upside down generics or so From: KJ Injection-Date: Thu, 11 Aug 2016 16:30:18 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 15 Xref: news.eternal-september.org comp.lang.vhdl:4538 On Thursday, August 11, 2016 at 10:55:20 AM UTC-4, Ilya Kalistru wrote: >=20 > Is there a way to set latency of the module as some =E2=80=9Cproperty=E2= =80=9D in it, so=20 > that a top module could read it and adjust delay lines? Something like=20 > reversed generics =E2=80=93 generics pass parameter to a module but I nee= d to pass=20 > it from the module. >=20 Presumably, the amount of latency of a particular module is either fixed or= is a function of the generic inputs to that module. Since those generics = are available to the top level module as well, then a function can be creat= ed that calculates the latency of all of the modules and then uses those la= tencies to define the amount of latency required at the top. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: upside down generics or so Date: Thu, 11 Aug 2016 12:55:08 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 11 Aug 2016 16:55:09 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="2356"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/6tLRIUt0y+dVrlPUyW2FY" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:6UotKPiIuQdIYdnDYMT7BRWTtuA= Xref: news.eternal-september.org comp.lang.vhdl:4539 On 8/11/2016 10:55 AM, Ilya Kalistru wrote: > Sometimes I design complex pipeline which splits on several pipelines at some point and then these branch pipelines are joined in one pipeline again. > > | root pipeline > | > |\ > |\\ > ||| branch pipelines > |// joint point > | > > At the pipeline joint point data from different branches have to be aligned relatively to each other, so sometimes I have to add shift registers to shorter branch pipelines. Branch pipelines usually consist of several modules and added delays depends on the latencies of each module. As long as modules can be changed and their latency can be changed, I have to adjust delays. > > Is there a way to set latency of the module as some “property” in it, so that a top module could read it and adjust delay lines? Something like reversed generics – generics pass parameter to a module but I need to pass it from the module. > > Any ideas? A module passes signals in and out. You can create a constant integer output signal. Nothing fancy needed. Add up all the delays and subtract from the longest to get the additional pipeline stages needed. These values will only be used in generate statements so it won't create any logic. You may get warnings of signals that are deleted for having no source and/or no destination. Personally I hate that. A design should be synthesized without warnings. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:37 2024 X-Received: by 10.157.29.40 with SMTP id m37mr3809462otm.42.1470948789458; Thu, 11 Aug 2016 13:53:09 -0700 (PDT) X-Received: by 10.36.107.7 with SMTP id v7mr704787itc.10.1470948789438; Thu, 11 Aug 2016 13:53:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no9224142ith.0!news-out.google.com!d68ni24446ith.0!nntp.google.com!f6no9224131ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Aug 2016 13:53:08 -0700 (PDT) In-Reply-To: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8a14e1c4-1097-42e5-8270-7de62fae7e0e@googlegroups.com> Subject: Re: upside down generics or so From: Ilya Kalistru Injection-Date: Thu, 11 Aug 2016 20:53:09 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4540 On Thursday, August 11, 2016 at 7:30:20 PM UTC+3, KJ wrote: > On Thursday, August 11, 2016 at 10:55:20 AM UTC-4, Ilya Kalistru wrote: > >=20 > > Is there a way to set latency of the module as some =E2=80=9Cproperty= =E2=80=9D in it, so=20 > > that a top module could read it and adjust delay lines? Something like= =20 > > reversed generics =E2=80=93 generics pass parameter to a module but I n= eed to pass=20 > > it from the module. > >=20 > Presumably, the amount of latency of a particular module is either fixed = or is a function of the generic inputs to that module. Since those generic= s are available to the top level module as well, then a function can be cre= ated that calculates the latency of all of the modules and then uses those = latencies to define the amount of latency required at the top. >=20 > Kevin Jennings I don't think so. Latency depends on algorithms, how they are implemented a= nd how well the module is optimized. All that could (and will) change durin= g product development. From newsfish@newsfish Thu Aug 1 00:37:37 2024 X-Received: by 10.200.49.116 with SMTP id h49mr8159858qtb.19.1470950214678; Thu, 11 Aug 2016 14:16:54 -0700 (PDT) X-Received: by 10.36.230.68 with SMTP id e65mr701502ith.1.1470950214631; Thu, 11 Aug 2016 14:16:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!c52no8289517qte.1!news-out.google.com!d130ni32182ith.0!nntp.google.com!f6no9250731ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Aug 2016 14:16:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: Ilya Kalistru Injection-Date: Thu, 11 Aug 2016 21:16:54 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3669 X-Received-Body-CRC: 3235719694 Xref: news.eternal-september.org comp.lang.vhdl:4541 On Thursday, August 11, 2016 at 7:55:11 PM UTC+3, rickman wrote: > On 8/11/2016 10:55 AM, Ilya Kalistru wrote: > > Sometimes I design complex pipeline which splits on several pipelines a= t some point and then these branch pipelines are joined in one pipeline aga= in. > > > > | root pipeline > > | > > |\ > > |\\ > > ||| branch pipelines > > |// joint point > > | > > > > At the pipeline joint point data from different branches have to be al= igned relatively to each other, so sometimes I have to add shift registers = to shorter branch pipelines. Branch pipelines usually consist of several mo= dules and added delays depends on the latencies of each module. As long as = modules can be changed and their latency can be changed, I have to adjust d= elays. > > > > Is there a way to set latency of the module as some =E2=80=9Cproperty= =E2=80=9D in it, so that a top module could read it and adjust delay lines?= Something like reversed generics =E2=80=93 generics pass parameter to a mo= dule but I need to pass it from the module. > > > > Any ideas? >=20 > A module passes signals in and out. You can create a constant integer=20 > output signal. Nothing fancy needed. Add up all the delays and=20 > subtract from the longest to get the additional pipeline stages needed. >=20 > These values will only be used in generate statements so it won't create= =20 > any logic. You may get warnings of signals that are deleted for having= =20 > no source and/or no destination. Personally I hate that. A design=20 > should be synthesized without warnings. >=20 > --=20 >=20 > Rick C With constant signal outputs you can neither define signals like signal DelayLine : std_logic_vector(DelayFromTheModule downto 0); nor use generate statements with this parameters. The only way to use them (that I see) is to make excessively long delay lin= es and multiplexers from each stage of it, controlled by that constant sign= al. Then we have to hope that synthesizer will optimize it properly, remove= unnecessary multiplexer and will be able to infer built-in shift registers= there. It's not very elegant solution and it has very limited use because we canno= t use signals everywhere we want (but can use constants and generics). Or I miss something? I've seen that it's possible to define some objects inside entity declarati= on. I hope that there is something exotic like that which will allow to do = what I want... From newsfish@newsfish Thu Aug 1 00:37:37 2024 X-Received: by 10.36.127.72 with SMTP id r69mr2029996itc.13.1471012770536; Fri, 12 Aug 2016 07:39:30 -0700 (PDT) X-Received: by 10.36.108.66 with SMTP id w63mr116103itb.7.1471012770470; Fri, 12 Aug 2016 07:39:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no9394842ith.0!news-out.google.com!d130ni32952ith.0!nntp.google.com!f6no9394831ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Aug 2016 07:39:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.43.3.237; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.43.3.237 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: Jim Lewis Injection-Date: Fri, 12 Aug 2016 14:39:30 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4542 I would put a constant in a package that is associated with a particular en= tity. As you do your detailed design and update the pipeline in a particul= ar block, simply update the corresponding constant in the package - even be= tter would be to use that constant to define the number of pipeline stages = in the block. =20 Then any design that references the package can see the constant. From newsfish@newsfish Thu Aug 1 00:37:38 2024 X-Received: by 10.107.205.4 with SMTP id d4mr11799782iog.3.1471021961395; Fri, 12 Aug 2016 10:12:41 -0700 (PDT) X-Received: by 10.36.3.85 with SMTP id e82mr177382ite.1.1471021961372; Fri, 12 Aug 2016 10:12:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no9454080ith.0!news-out.google.com!d68ni25326ith.0!nntp.google.com!f6no9432289ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Aug 2016 10:12:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> Subject: Re: upside down generics or so From: Ilya Kalistru Injection-Date: Fri, 12 Aug 2016 17:12:41 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4543 On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: > I would put a constant in a package that is associated with a particular = entity. As you do your detailed design and update the pipeline in a partic= ular block, simply update the corresponding constant in the package - even = better would be to use that constant to define the number of pipeline stage= s in the block. =20 >=20 > Then any design that references the package can see the constant. That's exactly what I've done. But when you are modifying the module you ha= ve to remember that somewhere in a different file (package) there is a cons= tant you have to adjust according to you changes. From newsfish@newsfish Thu Aug 1 00:37:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: upside down generics or so Newsgroups: comp.lang.vhdl References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 13 Aug 2016 03:09:56 GMT Lines: 36 Message-ID: <57ae8f84$0$11104$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: b8c1a44a.news.astraweb.com X-Trace: DXC=Al@9Zk`7BGPo4L?0kYOcDh@:W\:Hm@YlDb:j6?2e\NLLm2KWEEb\\?8>=4]FTUCBkMM= Xref: news.eternal-september.org comp.lang.vhdl:4544 On Fri, 12 Aug 2016 10:12:40 -0700, Ilya Kalistru wrote: > On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: >> I would put a constant in a package that is associated with a >> particular entity. As you do your detailed design and update the >> pipeline in a particular block, simply update the corresponding >> constant in the package - even better would be to use that constant to >> define the number of pipeline stages in the block. >> >> Then any design that references the package can see the constant. > > That's exactly what I've done. But when you are modifying the module you > have to remember that somewhere in a different file (package) there is a > constant you have to adjust according to you changes. I contend that you *don't* have to remember to adjust that, as long as you: 1. Write an assert statement inside your module that checks that the package constant has the value that matches your design. I suggest a higher severity level on the assertion, e.g. failure. 2. You remember to simulate your design (so that the assertion can be checked). I wouldn't rely on a synthesiser to check an assertion, but all simulators should work properly. (In any reasonable development process) you'll already be required to simulate your testbench before committing your code change. The only new thing you have to do is add the 1 line of assertion statement in your module. Regards, Allan From newsfish@newsfish Thu Aug 1 00:37:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: upside down generics or so Date: Fri, 12 Aug 2016 23:28:13 -0400 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 13 Aug 2016 03:28:24 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="23139"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ztB91AphdNNQPBo+7xzA0" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <57ae8f84$0$11104$c3e8da3@news.astraweb.com> Cancel-Lock: sha1:E7ulvsQ03Q6wxfat7/7EC9h1ShQ= Xref: news.eternal-september.org comp.lang.vhdl:4545 On 8/12/2016 11:09 PM, Allan Herriman wrote: > On Fri, 12 Aug 2016 10:12:40 -0700, Ilya Kalistru wrote: > >> On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: >>> I would put a constant in a package that is associated with a >>> particular entity. As you do your detailed design and update the >>> pipeline in a particular block, simply update the corresponding >>> constant in the package - even better would be to use that constant to >>> define the number of pipeline stages in the block. >>> >>> Then any design that references the package can see the constant. >> >> That's exactly what I've done. But when you are modifying the module you >> have to remember that somewhere in a different file (package) there is a >> constant you have to adjust according to you changes. > > > I contend that you *don't* have to remember to adjust that, as long as > you: > > 1. Write an assert statement inside your module that checks that the > package constant has the value that matches your design. I suggest a > higher severity level on the assertion, e.g. failure. > > 2. You remember to simulate your design (so that the assertion can be > checked). I wouldn't rely on a synthesiser to check an assertion, but > all simulators should work properly. > > > (In any reasonable development process) you'll already be required to > simulate your testbench before committing your code change. > The only new thing you have to do is add the 1 line of assertion > statement in your module. So when a change is made to the pipeline depth a change will need to be made for adjusting the delay pipeline in two places. One to check the other. I guess that's one way to make this work. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: upside down generics or so Newsgroups: comp.lang.vhdl References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 13 Aug 2016 04:58:45 GMT Lines: 57 Message-ID: <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 4982e839.news.astraweb.com X-Trace: DXC=Vn^J\jPhTJH^MAbH1]K;0BL?0kYOcDh@J_1m1SOGk_>Gh:BbU8OZ3AM On 8/12/2016 11:09 PM, Allan Herriman wrote: >> On Fri, 12 Aug 2016 10:12:40 -0700, Ilya Kalistru wrote: >> >>> On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: >>>> I would put a constant in a package that is associated with a >>>> particular entity. As you do your detailed design and update the >>>> pipeline in a particular block, simply update the corresponding >>>> constant in the package - even better would be to use that constant >>>> to define the number of pipeline stages in the block. >>>> >>>> Then any design that references the package can see the constant. >>> >>> That's exactly what I've done. But when you are modifying the module >>> you have to remember that somewhere in a different file (package) >>> there is a constant you have to adjust according to you changes. >> >> >> I contend that you *don't* have to remember to adjust that, as long as >> you: >> >> 1. Write an assert statement inside your module that checks that the >> package constant has the value that matches your design. I suggest a >> higher severity level on the assertion, e.g. failure. >> >> 2. You remember to simulate your design (so that the assertion can be >> checked). I wouldn't rely on a synthesiser to check an assertion, but >> all simulators should work properly. >> >> >> (In any reasonable development process) you'll already be required to >> simulate your testbench before committing your code change. >> The only new thing you have to do is add the 1 line of assertion >> statement in your module. > > So when a change is made to the pipeline depth a change will need to be > made for adjusting the delay pipeline in two places. A change is need in two places: the pipeline depth inside the module and the constant in the package. The assert statement checks one against the other and won't need to be changed. You're doing something wrong if you need to change the assert statement as well, because then you're not checking the constant in the package directly against the thing it's meant to track. > One to check the > other. I guess that's one way to make this work. Are you implying you have a better way (that works with the current language and tools)? Please tell - I'm always happy to learn new techniques. Allan From newsfish@newsfish Thu Aug 1 00:37:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: upside down generics or so Date: Sat, 13 Aug 2016 01:33:10 -0400 Organization: A noiseless patient Spider Lines: 87 Message-ID: References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 13 Aug 2016 05:33:12 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="5955"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/661JZqTWlDYzNQnN9/pAP" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> Cancel-Lock: sha1:tI8p8qf5fyo04Fl+4eDLg9l6cnI= Xref: news.eternal-september.org comp.lang.vhdl:4547 On 8/13/2016 12:58 AM, Allan Herriman wrote: > On Fri, 12 Aug 2016 23:28:13 -0400, rickman wrote: > >> On 8/12/2016 11:09 PM, Allan Herriman wrote: >>> On Fri, 12 Aug 2016 10:12:40 -0700, Ilya Kalistru wrote: >>> >>>> On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: >>>>> I would put a constant in a package that is associated with a >>>>> particular entity. As you do your detailed design and update the >>>>> pipeline in a particular block, simply update the corresponding >>>>> constant in the package - even better would be to use that constant >>>>> to define the number of pipeline stages in the block. >>>>> >>>>> Then any design that references the package can see the constant. >>>> >>>> That's exactly what I've done. But when you are modifying the module >>>> you have to remember that somewhere in a different file (package) >>>> there is a constant you have to adjust according to you changes. >>> >>> >>> I contend that you *don't* have to remember to adjust that, as long as >>> you: >>> >>> 1. Write an assert statement inside your module that checks that the >>> package constant has the value that matches your design. I suggest a >>> higher severity level on the assertion, e.g. failure. >>> >>> 2. You remember to simulate your design (so that the assertion can be >>> checked). I wouldn't rely on a synthesiser to check an assertion, but >>> all simulators should work properly. >>> >>> >>> (In any reasonable development process) you'll already be required to >>> simulate your testbench before committing your code change. >>> The only new thing you have to do is add the 1 line of assertion >>> statement in your module. >> >> So when a change is made to the pipeline depth a change will need to be >> made for adjusting the delay pipeline in two places. > > > A change is need in two places: the pipeline depth inside the module and > the constant in the package. > > The assert statement checks one against the other and won't need to be > changed. You're doing something wrong if you need to change the assert > statement as well, because then you're not checking the constant in the > package directly against the thing it's meant to track. Not sure what you are saying about "pipeline depth". The module has functionality that uses some number of logic pipeline stages. This has to be noted in the module as a constant to use in the assert statement, otherwise it is not needed in the module. This value also must be noted as a constant in the package to correspond to the module. These two values must be kept in sync and also aligned with the design of the module. Maybe this is not as big issue as I am thinking since it is not likely the modules will change pipeline depths. Rather modules will be added or replaced by other modules. But in addition to keeping the two constants in sync with the module design, the use of the module has to be kept in sync with the corresponding constant being passed into the module as well as the use in defining the delay pipeline. This sounds like a lot of work to me and potentially error prone which is what it is trying to prevent. It also ends up being a bit verbose which is one of the problems with VHDL. The use of various tools has made design of VHDL code a bit easier, but I know I get tired of all the typing I have to do when making changes which end up being manual mostly. >> One to check the >> other. I guess that's one way to make this work. > > Are you implying you have a better way (that works with the current > language and tools)? Please tell - I'm always happy to learn new > techniques. My opinion is to not do it at all. The documentation of the module can provide the logic pipeline depth used and the designer can work it out in the unit using the module. I think that would be easier and less error prone in real usage. I can't tell how many times I have gone to lengths to try to prevent errors only to find I have done more work that is useful. Sometimes simpler is better. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:39 2024 X-Received: by 10.129.145.8 with SMTP id i8mr14397949ywg.17.1471106724981; Sat, 13 Aug 2016 09:45:24 -0700 (PDT) X-Received: by 10.36.227.207 with SMTP id d198mr186002ith.4.1471106724947; Sat, 13 Aug 2016 09:45:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c52no8597559qte.1!news-out.google.com!d68ni26433ith.0!nntp.google.com!f6no9681434ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Aug 2016 09:45:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> Subject: Re: upside down generics or so From: Ilya Kalistru Injection-Date: Sat, 13 Aug 2016 16:45:24 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4548 On Saturday, August 13, 2016 at 8:33:15 AM UTC+3, rickman wrote: > On 8/13/2016 12:58 AM, Allan Herriman wrote: > > On Fri, 12 Aug 2016 23:28:13 -0400, rickman wrote: > > > >> On 8/12/2016 11:09 PM, Allan Herriman wrote: > >>> On Fri, 12 Aug 2016 10:12:40 -0700, Ilya Kalistru wrote: > >>> > >>>> On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: > >>>>> I would put a constant in a package that is associated with a > >>>>> particular entity. As you do your detailed design and update the > >>>>> pipeline in a particular block, simply update the corresponding > >>>>> constant in the package - even better would be to use that constant > >>>>> to define the number of pipeline stages in the block. > >>>>> > >>>>> Then any design that references the package can see the constant. > >>>> > >>>> That's exactly what I've done. But when you are modifying the module > >>>> you have to remember that somewhere in a different file (package) > >>>> there is a constant you have to adjust according to you changes. > >>> > >>> > >>> I contend that you *don't* have to remember to adjust that, as long a= s > >>> you: > >>> > >>> 1. Write an assert statement inside your module that checks that the > >>> package constant has the value that matches your design. I suggest a > >>> higher severity level on the assertion, e.g. failure. > >>> > >>> 2. You remember to simulate your design (so that the assertion can b= e > >>> checked). I wouldn't rely on a synthesiser to check an assertion, bu= t > >>> all simulators should work properly. > >>> > >>> > >>> (In any reasonable development process) you'll already be required to > >>> simulate your testbench before committing your code change. > >>> The only new thing you have to do is add the 1 line of assertion > >>> statement in your module. > >> > >> So when a change is made to the pipeline depth a change will need to b= e > >> made for adjusting the delay pipeline in two places. > > > > > > A change is need in two places: the pipeline depth inside the module an= d > > the constant in the package. > > > > The assert statement checks one against the other and won't need to be > > changed. You're doing something wrong if you need to change the assert > > statement as well, because then you're not checking the constant in the > > package directly against the thing it's meant to track. >=20 > Not sure what you are saying about "pipeline depth". The module has=20 > functionality that uses some number of logic pipeline stages. This has= =20 > to be noted in the module as a constant to use in the assert statement,= =20 > otherwise it is not needed in the module. This value also must be noted= =20 > as a constant in the package to correspond to the module. These two=20 > values must be kept in sync and also aligned with the design of the modul= e. >=20 > Maybe this is not as big issue as I am thinking since it is not likely=20 > the modules will change pipeline depths. Rather modules will be added=20 > or replaced by other modules. But in addition to keeping the two=20 > constants in sync with the module design, the use of the module has to=20 > be kept in sync with the corresponding constant being passed into the=20 > module as well as the use in defining the delay pipeline. >=20 > This sounds like a lot of work to me and potentially error prone which=20 > is what it is trying to prevent. It also ends up being a bit verbose=20 > which is one of the problems with VHDL. The use of various tools has=20 > made design of VHDL code a bit easier, but I know I get tired of all the= =20 > typing I have to do when making changes which end up being manual mostly. >=20 >=20 > >> One to check the > >> other. I guess that's one way to make this work. > > > > Are you implying you have a better way (that works with the current > > language and tools)? Please tell - I'm always happy to learn new > > techniques. >=20 > My opinion is to not do it at all. The documentation of the module can= =20 > provide the logic pipeline depth used and the designer can work it out=20 > in the unit using the module. I think that would be easier and less=20 > error prone in real usage. I can't tell how many times I have gone to=20 > lengths to try to prevent errors only to find I have done more work that= =20 > is useful. Sometimes simpler is better. >=20 > --=20 >=20 > Rick C hm... It's sad that there is no such thing like output generic. It would ma= ke a lot of things much easier. BTW when it comes to simulation, I have a method I use to check correctness= of pipelines length: There is usually something like Data.Valid signal or Data.EndOfPacket signa= l or something like that. When you merge two pipelines you usually really n= eed only one of them from one of the pipelines, but I make an assert to che= ck that both of them are aligned. Sometimes I even add such a signal just for debugging purposes. Unfortunately, it's not always possible. From newsfish@newsfish Thu Aug 1 00:37:39 2024 X-Received: by 10.157.49.114 with SMTP id v47mr7042441otd.47.1471125743150; Sat, 13 Aug 2016 15:02:23 -0700 (PDT) X-Received: by 10.36.111.147 with SMTP id x141mr216049itb.6.1471125743126; Sat, 13 Aug 2016 15:02:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!f6no9743200ith.0!news-out.google.com!d68ni26676ith.0!nntp.google.com!f6no9720813ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Aug 2016 15:02:22 -0700 (PDT) In-Reply-To: <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <56ca9268-9a27-4de2-9d57-90570f14ebbe@googlegroups.com> Subject: Re: upside down generics or so From: Lars Asplund Injection-Date: Sat, 13 Aug 2016 22:02:23 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 23 Xref: news.eternal-september.org comp.lang.vhdl:4549 Often when I design a pipelined module I use the globally available latency= property/constant to specify the signals holding the pipeline registers, f= or example to create the delayline/std_logic_vector between an input and an= output data valid signal. If there is no data valid and the property isn't= used elsewhere in the module's design it should still be used in the testb= ench for the module to check that the expected output is present latency cl= ock cycles after the test input is applied. If you forget to update the pro= perty when changing the pipeline depth you will find out when running your = testbench and not when someone starts using your module *and* your latency = constant.=20 I would not like to maintain the same latency number at multiple places as = that would violate the DRY principle (Don't Repeat Yourself). Note that the= DRY principle applies to documentation as well. If the latency changes you= have to update the documentation as well as all copies of that number made= by users of that module after reading the documents (unless the docs point= s to the constant). When talking about properties I think it's worth mentioning user-defined at= tributes. They are not well-supported by tools and I think the purpose was = to use them as tools directives rather than within the VHDL model itself. S= till, you can define a latency attribute and use that to decorate an entity= with a latency value that can be accessed by other modules. With that appr= oach there is no need to create a package in order to export this property. From newsfish@newsfish Thu Aug 1 00:37:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: upside down generics or so Newsgroups: comp.lang.vhdl References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> <56ca9268-9a27-4de2-9d57-90570f14ebbe@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 14 Aug 2016 06:02:50 GMT Lines: 47 Message-ID: <57b0098a$0$1497$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: b45626b3.news.astraweb.com X-Trace: DXC=OUK1YIUfhN_40PdiKi@9HQL?0kYOcDh@ZAFeRkALIbWSI7g=bIdTQP\HI6bY5_;LhYj@W@0Shli5TYeZJ5OWlM`Q:aWia Often when I design a pipelined module I use the globally available > latency property/constant to specify the signals holding the pipeline > registers, for example to create the delayline/std_logic_vector between > an input and an output data valid signal. If there is no data valid and > the property isn't used elsewhere in the module's design it should still > be used in the testbench for the module to check that the expected > output is present latency clock cycles after the test input is applied. > If you forget to update the property when changing the pipeline depth > you will find out when running your testbench and not when someone > starts using your module *and* your latency constant. > > I would not like to maintain the same latency number at multiple places > as that would violate the DRY principle (Don't Repeat Yourself). Note > that the DRY principle applies to documentation as well. If the latency > changes you have to update the documentation as well as all copies of > that number made by users of that module after reading the documents > (unless the docs points to the constant). > > When talking about properties I think it's worth mentioning user-defined > attributes. They are not well-supported by tools and I think the purpose > was to use them as tools directives rather than within the VHDL model > itself. Still, you can define a latency attribute and use that to > decorate an entity with a latency value that can be accessed by other > modules. With that approach there is no need to create a package in > order to export this property. I don't have a copy of the LRM handy to check this, but I thought (and hopefully I am wrong here) that a user defined attribute associated with an entity could only be used inside that entity or architectures of that entity, and not in an architecture that instantiates that entity (which is where we want it). For example, I *wouldn't* be able to say: my_label : work.my_entity generic map ( ... ) port map ( ... ); report some_type'image(my_label'my_attribute); I'd be very happy to be proven wrong on this. Thanks, Allan From newsfish@newsfish Thu Aug 1 00:37:40 2024 X-Received: by 10.129.122.72 with SMTP id v69mr17677664ywc.40.1471157951347; Sat, 13 Aug 2016 23:59:11 -0700 (PDT) X-Received: by 10.36.230.68 with SMTP id e65mr88437ith.1.1471157951081; Sat, 13 Aug 2016 23:59:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j37no8406394qta.0!news-out.google.com!d130ni34796ith.0!nntp.google.com!f6no9806784ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Aug 2016 23:59:10 -0700 (PDT) In-Reply-To: <57b0098a$0$1497$c3e8da3$5496439d@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=H7cinwoAAADYsIQpk3VLrSzu-G7o6bIW NNTP-Posting-Host: 217.211.21.59 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> <56ca9268-9a27-4de2-9d57-90570f14ebbe@googlegroups.com> <57b0098a$0$1497$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: lars.synective@gmail.com Injection-Date: Sun, 14 Aug 2016 06:59:11 +0000 Content-Type: text/plain; charset=UTF-8 X-Received-Bytes: 1787 X-Received-Body-CRC: 2410231345 Xref: news.eternal-september.org comp.lang.vhdl:4551 You will have to do report some_type'image(work.my_entity'my_attribute); Your report statement would report the attribute for the instance label which would work if it was specified for that label. Not what we want in this case though. /Lars From newsfish@newsfish Thu Aug 1 00:37:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: upside down generics or so Newsgroups: comp.lang.vhdl References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> <56ca9268-9a27-4de2-9d57-90570f14ebbe@googlegroups.com> <57b0098a$0$1497$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 14 Aug 2016 07:29:36 GMT Lines: 22 Message-ID: <57b01ddf$0$11102$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 9689a101.news.astraweb.com X-Trace: DXC=3I8ACP9;ff0hn]AcMfkkb9L?0kYOcDh@:W\:Hm@YlDb:lhbc6D3GE87dDFl>1V@aL7]16S2UbbZi1 Xref: news.eternal-september.org comp.lang.vhdl:4552 On Sat, 13 Aug 2016 23:59:10 -0700, lars.synective wrote: > You will have to do > > report some_type'image(work.my_entity'my_attribute); > > Your report statement would report the attribute for the instance label > which would work if it was specified for that label. Not what we want in > this case though. > > /Lars That doesn't really work for the original problem though, as the attribute value will typically be a function of the generics (in the generic map), and thus it will be different for each instantiation. The label is the only thing that identifies an instantiation of an entity (as opposed to the entity itself). But, as you say, it's not what we want in this case. :( Thanks, Allan From newsfish@newsfish Thu Aug 1 00:37:41 2024 X-Received: by 10.36.121.139 with SMTP id z133mr5436703itc.4.1471162358182; Sun, 14 Aug 2016 01:12:38 -0700 (PDT) X-Received: by 10.36.217.2 with SMTP id p2mr234169itg.5.1471162358163; Sun, 14 Aug 2016 01:12:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no9793731ith.0!news-out.google.com!d68ni27153ith.0!nntp.google.com!f6no9817821ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 14 Aug 2016 01:12:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=H7cinwoAAADYsIQpk3VLrSzu-G7o6bIW NNTP-Posting-Host: 217.211.21.59 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> <56ca9268-9a27-4de2-9d57-90570f14ebbe@googlegroups.com> <57b0098a$0$1497$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: lars.synective@gmail.com Injection-Date: Sun, 14 Aug 2016 08:12:38 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4553 I think this approach would be somewhat limited to entities. The attribute = should really be placed on the architecture since you may have several with= different latencies but I don't think you can denote an architecture with = a selected name like I did in the report statement to denote the entity. A = workaround would be to have several attributes, one for each architecture o= r maybe an attribute of a record type which has an element for each archite= cture. Not great since you cannot use the same attribute for all modules bu= t you have the same problem when using constants. From newsfish@newsfish Thu Aug 1 00:37:41 2024 X-Received: by 10.13.213.73 with SMTP id x70mr17233604ywd.53.1471166608139; Sun, 14 Aug 2016 02:23:28 -0700 (PDT) X-Received: by 10.36.115.203 with SMTP id y194mr234436itb.0.1471166608105; Sun, 14 Aug 2016 02:23:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j37no8422498qta.0!news-out.google.com!d68ni27242ith.0!nntp.google.com!f6no9830357ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 14 Aug 2016 02:23:27 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> <56ca9268-9a27-4de2-9d57-90570f14ebbe@googlegroups.com> <57b0098a$0$1497$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f1669ae-a5ae-43a7-8e19-6eb4c439a717@googlegroups.com> Subject: Re: upside down generics or so From: Lars Asplund Injection-Date: Sun, 14 Aug 2016 09:23:28 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2733 X-Received-Body-CRC: 3929836637 Xref: news.eternal-september.org comp.lang.vhdl:4554 You're right, it wouldn't work when the latency is a function of the generi= cs. I haven't experienced this to be the typical case but if you run into t= hat situation the module would have to provide a latency function in a pack= age. If the latency of a module is a function of its submodules, for example the= sum of the latency for two chained submodules plus some extra pipelining i= ntroduced by the module itself you would still be able to use the attribute= since it can be assigned an expression If we continue to ignore tool support and only discuss what's legal in the = language I guess it would be possible to create a latency constant in the a= rchitecture which is initialized with a latency function based on the gener= ics. That constant can then be referenced using external names. This would = be DRY, there is no extra package, you can separate different instances, an= d you don't have to change the references if the generics and the latency f= unction signature changes. From newsfish@newsfish Thu Aug 1 00:37:41 2024 X-Received: by 10.13.201.3 with SMTP id l3mr8977667ywd.24.1471262157776; Mon, 15 Aug 2016 04:55:57 -0700 (PDT) X-Received: by 10.36.189.198 with SMTP id x189mr30173ite.1.1471262157741; Mon, 15 Aug 2016 04:55:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j37no8614444qta.0!news-out.google.com!d130ni36089ith.0!nntp.google.com!f6no10078174ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Aug 2016 04:55:57 -0700 (PDT) In-Reply-To: <8a14e1c4-1097-42e5-8270-7de62fae7e0e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> <8a14e1c4-1097-42e5-8270-7de62fae7e0e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: KJ Injection-Date: Mon, 15 Aug 2016 11:55:57 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4555 On Thursday, August 11, 2016 at 4:53:11 PM UTC-4, Ilya Kalistru wrote: > On Thursday, August 11, 2016 at 7:30:20 PM UTC+3, KJ wrote: > > On Thursday, August 11, 2016 at 10:55:20 AM UTC-4, Ilya Kalistru wrote: > > >=20 > > > Is there a way to set latency of the module as some =E2=80=9Cproperty= =E2=80=9D in it, so=20 > > > that a top module could read it and adjust delay lines? Something lik= e=20 > > > reversed generics =E2=80=93 generics pass parameter to a module but I= need to pass=20 > > > it from the module. > > >=20 > > Presumably, the amount of latency of a particular module is either fixe= d or is a function of the generic inputs to that module. Since those gener= ics are available to the top level module as well, then a function can be c= reated that calculates the latency of all of the modules and then uses thos= e latencies to define the amount of latency required at the top. > >=20 > > Kevin Jennings >=20 > I don't think so. Latency depends on algorithms, how they are implemented= =20 > and how well the module is optimized. All that could (and will) change=20 > during product development. It depends on the algorithm, period. Once the source code for the module i= s written, the latency number has been locked down. The number of pipeline= stages will be determined once the algorithm is coded. At that point you = know the number and that number can then be put into a package along with o= ther module related things. If you later change the algorithm in some way = that changes the number of pipeline stages, you change the number...to matc= h the change in the algorithm. Not rocket science. The point is to remove any dependency for the user of the module from havin= g to know what the latency is exactly. The user of the module just needs t= o know where to reference that number from which is in the package that com= es along with the module. Suggesting that the module should be developed so that the module creator s= hould somehow be off the hook for defining and publishing in the package th= e latency number is misguided. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:42 2024 X-Received: by 10.66.248.164 with SMTP id yn4mr20359174pac.45.1471262334054; Mon, 15 Aug 2016 04:58:54 -0700 (PDT) X-Received: by 10.36.224.139 with SMTP id c133mr85543ith.2.1471262334017; Mon, 15 Aug 2016 04:58:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no10078570ith.0!news-out.google.com!d68ni28420ith.0!nntp.google.com!f6no10100804ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Aug 2016 04:58:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7ded0dbb-468a-4f4c-a9fc-c930d2782d02@googlegroups.com> Subject: Re: upside down generics or so From: KJ Injection-Date: Mon, 15 Aug 2016 11:58:54 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4556 On Thursday, August 11, 2016 at 12:55:11 PM UTC-4, rickman wrote: > > A module passes signals in and out. You can create a constant integer > output signal. Nothing fancy needed. Add up all the delays and > subtract from the longest to get the additional pipeline stages needed. > > These values will only be used in generate statements so it won't create > any logic. You may get warnings of signals that are deleted for having > no source and/or no destination. Personally I hate that. A design > should be synthesized without warnings. > A signal cannot be used to control generate statements. A signal can also not be used to define the value of a constant. It doesn't matter if that signal is coded to be a constant within the module. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:42 2024 X-Received: by 10.157.7.231 with SMTP id 94mr16984906oto.9.1471263256667; Mon, 15 Aug 2016 05:14:16 -0700 (PDT) X-Received: by 10.36.224.206 with SMTP id c197mr298914ith.3.1471263256641; Mon, 15 Aug 2016 05:14:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no10081348ith.0!news-out.google.com!d68ni28420ith.0!nntp.google.com!f6no10103623ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Aug 2016 05:14:15 -0700 (PDT) In-Reply-To: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: KJ Injection-Date: Mon, 15 Aug 2016 12:14:16 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4557 On Friday, August 12, 2016 at 1:12:48 PM UTC-4, Ilya Kalistru wrote: > On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: > > I would put a constant in a package that is associated with a particula= r entity. As you do your detailed design and update the pipeline in a part= icular block, simply update the corresponding constant in the package - eve= n better would be to use that constant to define the number of pipeline sta= ges in the block. =20 > >=20 > > Then any design that references the package can see the constant. >=20 > That's exactly what I've done. But when you are modifying the module you > have to remember that somewhere in a different file (package) there is a= =20 > constant you have to adjust according to you changes. Typically I have the package, entity and architecture all in the same file.= There are cases where I've put the architecture in a separate file, I don= 't recall a single instance where the package and entity needed to be in se= parate files. But yes you still have to put that latency number change in. What I do to 'remember' to make this package change is to put an assertion = in to check that the actual latency through the module matches the number i= n the package. When the assertion fails, I suddenly 'remember' that the la= tency number needs to be updated...or sometimes that I've made an incorrect= change to the algorithm. The case of a constant (disregarding changes made during development) is ea= sy, just put the number in the package. The more complex case where maybe = the module has different, static ways of being used that are selected by en= tity generics simply means that the package should have a function that get= s passed the values of the entity generics and uses those to compute the la= tency. To the user of the module, that means that yes they need to make su= re that they use the same generics in the call to the function to determine= the latency as they do when they instantiate the entity but once again, ha= ving an assertion in the architecture code that measures the actual latency= and checks it to the expected latency as defined by the package function i= s the way that you can provide reasonable coverage of this type of misuse o= f the module. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:42 2024 X-Received: by 10.129.40.198 with SMTP id o189mr21325820ywo.51.1471263435737; Mon, 15 Aug 2016 05:17:15 -0700 (PDT) X-Received: by 10.36.26.82 with SMTP id 79mr296728iti.6.1471263435694; Mon, 15 Aug 2016 05:17:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!c52no8895276qte.1!news-out.google.com!d130ni36135ith.0!nntp.google.com!f6no10082320ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Aug 2016 05:17:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <16a830c9-8019-4e12-bb83-d4b4bcc766d3@googlegroups.com> Subject: Re: upside down generics or so From: KJ Injection-Date: Mon, 15 Aug 2016 12:17:15 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 11 Xref: news.eternal-september.org comp.lang.vhdl:4558 On Saturday, August 13, 2016 at 1:33:15 AM UTC-4, rickman wrote: > > Not sure what you are saying about "pipeline depth". The module has > functionality that uses some number of logic pipeline stages. This has > to be noted in the module as a constant to use in the assert statement, > otherwise it is not needed in the module. This value also must be noted > as a constant in the package to correspond to the module. These two > values must be kept in sync and also aligned with the design of the module. No, the code in the module would use the constant defined in the package. The pipeline depth number or latency number whatever it is called would be in one place, in the package. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:42 2024 X-Received: by 10.157.34.232 with SMTP id y95mr17020994ota.29.1471263731729; Mon, 15 Aug 2016 05:22:11 -0700 (PDT) X-Received: by 10.36.115.203 with SMTP id y194mr298199itb.0.1471263731697; Mon, 15 Aug 2016 05:22:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no10105798ith.0!news-out.google.com!d130ni36135ith.0!nntp.google.com!f6no10083828ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Aug 2016 05:22:11 -0700 (PDT) In-Reply-To: <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ee91dd9-7e3e-4478-8439-2d96bf361054@googlegroups.com> Subject: Re: upside down generics or so From: KJ Injection-Date: Mon, 15 Aug 2016 12:22:11 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4559 On Saturday, August 13, 2016 at 12:45:26 PM UTC-4, Ilya Kalistru wrote: > On Saturday, August 13, 2016 at 8:33:15 AM UTC+3, rickman wrote: > > On 8/13/2016 12:58 AM, Allan Herriman wrote: > > > On Fri, 12 Aug 2016 23:28:13 -0400, rickman wrote: > > > > > >> On 8/12/2016 11:09 PM, Allan Herriman wrote: > > >>> On Fri, 12 Aug 2016 10:12:40 -0700, Ilya Kalistru wrote: > > >>> > > >>>> On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: > > >>>>> I would put a constant in a package that is associated with a > > >>>>> particular entity. As you do your detailed design and update the > > >>>>> pipeline in a particular block, simply update the corresponding > > >>>>> constant in the package - even better would be to use that consta= nt > > >>>>> to define the number of pipeline stages in the block. > > >>>>> > > >>>>> Then any design that references the package can see the constant. > > >>>> > > >>>> That's exactly what I've done. But when you are modifying the modu= le > > >>>> you have to remember that somewhere in a different file (package) > > >>>> there is a constant you have to adjust according to you changes. > > >>> > > >>> > > >>> I contend that you *don't* have to remember to adjust that, as long= as > > >>> you: > > >>> > > >>> 1. Write an assert statement inside your module that checks that t= he > > >>> package constant has the value that matches your design. I suggest= a > > >>> higher severity level on the assertion, e.g. failure. > > >>> > > >>> 2. You remember to simulate your design (so that the assertion can= be > > >>> checked). I wouldn't rely on a synthesiser to check an assertion, = but > > >>> all simulators should work properly. > > >>> > > >>> > > >>> (In any reasonable development process) you'll already be required = to > > >>> simulate your testbench before committing your code change. > > >>> The only new thing you have to do is add the 1 line of assertion > > >>> statement in your module. > > >> > > >> So when a change is made to the pipeline depth a change will need to= be > > >> made for adjusting the delay pipeline in two places. > > > > > > > > > A change is need in two places: the pipeline depth inside the module = and > > > the constant in the package. > > > > > > The assert statement checks one against the other and won't need to b= e > > > changed. You're doing something wrong if you need to change the asse= rt > > > statement as well, because then you're not checking the constant in t= he > > > package directly against the thing it's meant to track. > >=20 > > Not sure what you are saying about "pipeline depth". The module has=20 > > functionality that uses some number of logic pipeline stages. This has= =20 > > to be noted in the module as a constant to use in the assert statement,= =20 > > otherwise it is not needed in the module. This value also must be note= d=20 > > as a constant in the package to correspond to the module. These two=20 > > values must be kept in sync and also aligned with the design of the mod= ule. > >=20 > > Maybe this is not as big issue as I am thinking since it is not likely= =20 > > the modules will change pipeline depths. Rather modules will be added= =20 > > or replaced by other modules. But in addition to keeping the two=20 > > constants in sync with the module design, the use of the module has to= =20 > > be kept in sync with the corresponding constant being passed into the= =20 > > module as well as the use in defining the delay pipeline. > >=20 > > This sounds like a lot of work to me and potentially error prone which= =20 > > is what it is trying to prevent. It also ends up being a bit verbose= =20 > > which is one of the problems with VHDL. The use of various tools has= =20 > > made design of VHDL code a bit easier, but I know I get tired of all th= e=20 > > typing I have to do when making changes which end up being manual mostl= y. > >=20 > >=20 > > >> One to check the > > >> other. I guess that's one way to make this work. > > > > > > Are you implying you have a better way (that works with the current > > > language and tools)? Please tell - I'm always happy to learn new > > > techniques. > >=20 > > My opinion is to not do it at all. The documentation of the module can= =20 > > provide the logic pipeline depth used and the designer can work it out= =20 > > in the unit using the module. I think that would be easier and less=20 > > error prone in real usage. I can't tell how many times I have gone to= =20 > > lengths to try to prevent errors only to find I have done more work tha= t=20 > > is useful. Sometimes simpler is better. > >=20 > > --=20 > >=20 > > Rick C >=20 > hm... It's sad that there is no such thing like output generic. It would= =20 > make a lot of things much easier. >=20 I don't think you've shown in what way it would be 'easier'. The only thin= g different is where you type in the value of the constant. Maybe it's 'ea= sier' to type it in the architecture, but it's shouldn't really be 'harder'= to type it into the package. Modules typically have packages that are pai= red with the entity/architecture. > BTW when it comes to simulation, I have a method I use to check=20 > correctness of pipelines length: > There is usually something like Data.Valid signal or Data.EndOfPacket=20 > signal or something like that. When you merge two pipelines you usually= =20 > really need only one of them from one of the pipelines, but I make an=20 > assert to check that both of them are aligned. > Sometimes I even add such a signal just for debugging purposes. > Unfortunately, it's not always possible. What were the details of the case where this was not possible? Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:43 2024 X-Received: by 10.129.155.142 with SMTP id s136mr16748589ywg.22.1471268591259; Mon, 15 Aug 2016 06:43:11 -0700 (PDT) X-Received: by 10.36.237.193 with SMTP id r184mr58515ith.2.1471268591178; Mon, 15 Aug 2016 06:43:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j37no8632918qta.0!news-out.google.com!d130ni36162ith.0!nntp.google.com!f6no10102901ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Aug 2016 06:43:10 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.51.157.12; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 206.51.157.12 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: BASYS 3 FPGA Board From: Jordan Christman Injection-Date: Mon, 15 Aug 2016 13:43:11 +0000 Content-Type: text/plain; charset=UTF-8 X-Received-Bytes: 1313 X-Received-Body-CRC: 3091503685 Xref: news.eternal-september.org comp.lang.vhdl:4560 Anyone interested or need additional help using the BASYS 3 board? I have created a course on Udemy, here is a link for more information and a $10 coupon. If you have additional questions feel free to message me. https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=TIGER10 Thanks, Jordan Christman From newsfish@newsfish Thu Aug 1 00:37:43 2024 X-Received: by 10.129.145.8 with SMTP id i8mr22267387ywg.17.1471298931890; Mon, 15 Aug 2016 15:08:51 -0700 (PDT) X-Received: by 10.36.20.201 with SMTP id 192mr381909itg.8.1471298931837; Mon, 15 Aug 2016 15:08:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j37no8715179qta.0!news-out.google.com!d130ni36525ith.0!nntp.google.com!f6no10223343ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Aug 2016 15:08:51 -0700 (PDT) In-Reply-To: <0ee91dd9-7e3e-4478-8439-2d96bf361054@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> <0ee91dd9-7e3e-4478-8439-2d96bf361054@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: Lars Asplund Injection-Date: Mon, 15 Aug 2016 22:08:51 +0000 Content-Type: text/plain; charset=UTF-8 X-Received-Bytes: 2105 X-Received-Body-CRC: 3196767275 Xref: news.eternal-september.org comp.lang.vhdl:4561 Don't get me wrong, I use the package constant like most of you. However, I tested the architecture internal constant accessed by the user using external names just to make sure that it works. Well, it works in simulation (ModelSim). The user would get the latency or some other property with something like this <> Very direct. Ask the object to which the property belongs (the instance). No need to know if the property is a function of the generics or not. But, as can be expected, it doesn't pass synthesis. At least not with Vivado. From newsfish@newsfish Thu Aug 1 00:37:43 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: upside down generics or so Date: Tue, 16 Aug 2016 00:43:20 -0400 Organization: A noiseless patient Spider Lines: 56 Message-ID: References: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> <8a14e1c4-1097-42e5-8270-7de62fae7e0e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 16 Aug 2016 04:43:20 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="acf474af46f1b38ae0d55d4d1131a427"; logging-data="31563"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/9SCytJynfl4+9DUee7UBE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:F5ao4L6/J+eoLW8QJvK71flQ0pU= Xref: news.eternal-september.org comp.lang.vhdl:4562 On 8/15/2016 7:55 AM, KJ wrote: > On Thursday, August 11, 2016 at 4:53:11 PM UTC-4, Ilya Kalistru > wrote: >> On Thursday, August 11, 2016 at 7:30:20 PM UTC+3, KJ wrote: >>> On Thursday, August 11, 2016 at 10:55:20 AM UTC-4, Ilya Kalistru >>> wrote: >>>> >>>> Is there a way to set latency of the module as some “property” >>>> in it, so that a top module could read it and adjust delay >>>> lines? Something like reversed generics – generics pass >>>> parameter to a module but I need to pass it from the module. >>>> >>> Presumably, the amount of latency of a particular module is >>> either fixed or is a function of the generic inputs to that >>> module. Since those generics are available to the top level >>> module as well, then a function can be created that calculates >>> the latency of all of the modules and then uses those latencies >>> to define the amount of latency required at the top. >>> >>> Kevin Jennings >> >> I don't think so. Latency depends on algorithms, how they are >> implemented and how well the module is optimized. All that could >> (and will) change during product development. > > It depends on the algorithm, period. Once the source code for the > module is written, the latency number has been locked down. The > number of pipeline stages will be determined once the algorithm is > coded. At that point you know the number and that number can then be > put into a package along with other module related things. If you > later change the algorithm in some way that changes the number of > pipeline stages, you change the number...to match the change in the > algorithm. Not rocket science. No, and the fact that this will cause errors from forgetting to change corresponding data in other modules is not rocket science either. > The point is to remove any dependency for the user of the module from > having to know what the latency is exactly. The user of the module > just needs to know where to reference that number from which is in > the package that comes along with the module. > > Suggesting that the module should be developed so that the module > creator should somehow be off the hook for defining and publishing in > the package the latency number is misguided. I don't understand why you say this. If you could design the module to return a value telling you the number of pipeline stages so the data did not need to be separately maintained in other module it would be less error prone. But there doesn't seem to be a way for a module to return a generic. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: upside down generics or so Date: Tue, 16 Aug 2016 00:48:39 -0400 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <16a830c9-8019-4e12-bb83-d4b4bcc766d3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 16 Aug 2016 04:48:38 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="acf474af46f1b38ae0d55d4d1131a427"; logging-data="31563"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/WWBE5XucrSjF/wsSaA+kl" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <16a830c9-8019-4e12-bb83-d4b4bcc766d3@googlegroups.com> Cancel-Lock: sha1:2sRaaCYS9gUZ6OfMg/Slx82t2AA= Xref: news.eternal-september.org comp.lang.vhdl:4563 On 8/15/2016 8:17 AM, KJ wrote: > On Saturday, August 13, 2016 at 1:33:15 AM UTC-4, rickman wrote: >> >> Not sure what you are saying about "pipeline depth". The module >> has functionality that uses some number of logic pipeline stages. >> This has to be noted in the module as a constant to use in the >> assert statement, otherwise it is not needed in the module. This >> value also must be noted as a constant in the package to correspond >> to the module. These two values must be kept in sync and also >> aligned with the design of the module. > > No, the code in the module would use the constant defined in the > package. The pipeline depth number or latency number whatever it is > called would be in one place, in the package. Whooosh! I am talking about the assert statement that verifies the constant in the package has been updated to agree with the code in the module. If you don't have error checking and the module is updated without updating the constant in the package, you get messed up code and a debug problem. That is why the assert statement was suggested. I'm simply pointing out that this won't prevent the error, just detect it in most cases. The returned generic from the module is still a better way to go if it were possible. It seems Lars has a method that might work for tools other than Vivaldo and keep all the information in one place. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: upside down generics or so Date: Tue, 16 Aug 2016 13:33:14 +0200 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 16 Aug 2016 11:33:14 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0ef5588c8e3c4fd023e66879f4f6acf3"; logging-data="30220"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18l0gL4GlOB2dcIbRSeb1cH" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> Cancel-Lock: sha1:PjWPdi7uv4X92Ge8FelRkPLB2JM= Xref: news.eternal-september.org comp.lang.vhdl:4564 Am 08/12/2016 um 07:12 PM schrieb Ilya Kalistru: > On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: >> I would put a constant in a package that is associated with a particular entity. As you do your detailed design and update the pipeline in a particular block, simply update the corresponding constant in the package - even better would be to use that constant to define the number of pipeline stages in the block. >> >> Then any design that references the package can see the constant. > > That's exactly what I've done. But when you are modifying the module you have to remember that somewhere in a different file (package) there is a constant you have to adjust according to you changes. > Maybe you can use assertions to check the package defined value against the one used in your entity. When the assertion fails, your synthesize or simulation tool will stop working and reports the problem. From newsfish@newsfish Thu Aug 1 00:37:44 2024 X-Received: by 10.107.144.86 with SMTP id s83mr25316745iod.26.1471354893243; Tue, 16 Aug 2016 06:41:33 -0700 (PDT) X-Received: by 10.36.227.67 with SMTP id d64mr446384ith.3.1471354893203; Tue, 16 Aug 2016 06:41:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no10405160ith.0!news-out.google.com!d130ni37140ith.0!nntp.google.com!f6no10381707ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Aug 2016 06:41:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> <8a14e1c4-1097-42e5-8270-7de62fae7e0e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <92a0345f-f4b8-44fe-b245-feeb16c8f029@googlegroups.com> Subject: Re: upside down generics or so From: KJ Injection-Date: Tue, 16 Aug 2016 13:41:33 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4565 On Tuesday, August 16, 2016 at 12:43:22 AM UTC-4, rickman wrote: > On 8/15/2016 7:55 AM, KJ wrote: > > > > It depends on the algorithm, period. Once the source code for the > > module is written, the latency number has been locked down. The > > number of pipeline stages will be determined once the algorithm is > > coded. At that point you know the number and that number can then be > > put into a package along with other module related things. If you > > later change the algorithm in some way that changes the number of > > pipeline stages, you change the number...to match the change in the > > algorithm. Not rocket science. >=20 > No, and the fact that this will cause errors from forgetting to change=20 > corresponding data in other modules is not rocket science either. >=20 The error gets checked by the assertion in the testbench. So, on the assum= ption that one would run their testbench after entering a design change the= n the error gets immediately caught. Not much different in that regard the= n when I mistype something and the compiler catches the error. Yes you did= have to write the code that does the checking and get that all working whe= reas the typo gets caught by code that has had a lot more eyeballs looking = at it and a lot more users using it, but the point is that once that checki= ng code is debugged and working then when a design error gets created via a= design change, the code does catch it...if you simulate your design. >=20 > > The point is to remove any dependency for the user of the module from > > having to know what the latency is exactly. The user of the module > > just needs to know where to reference that number from which is in > > the package that comes along with the module. > > > > Suggesting that the module should be developed so that the module > > creator should somehow be off the hook for defining and publishing in > > the package the latency number is misguided. >=20 > I don't understand why you say this. If you could design the module to= =20 > return a value telling you the number of pipeline stages so the data did= =20 > not need to be separately maintained in other module it would be less=20 > error prone. But there doesn't seem to be a way for a module to return= =20 > a generic. >=20 I'm not disagreeing that if you could create a constant output that could i= n all cases be used just like a real constant then this would provide a dif= ferent method to accomplish the goal. Some can see it as better, some just= see it as different, that's OK. I think it would be useful. But I would want to be able to use that output= constant just like any other constant. So, based on the latency for a num= ber of modules cascaded together, I could compute the depth of a memory tha= t will be needed to collect up all the pipelined data that comes out after = the output interface says to wait. Or to use that constant in a generate s= tatement. Stuff like that. But as far I've seen in this discussion, that number still looks like it ge= ts typed into the architecture and is therefore potentially wrong. If you = change the design to add another pipeline stage, that number doesn't magica= lly change to the new number so you have an error. Bantering about whether= to change a typed in number in the architecture or the package ***for that= same module*** is splitting hairs. For it truly to be correct by design, that constant output should be calcul= ated from the number of pipeline stages in the design. So if you add/remov= e a pipeline stage, nothing else need be done because the output constant w= ould have a formula to it not just a number (i.e. Pipe_Stages <=3D Pipeline= 'length). Maybe that is what the OP is doing anyway rather than actually h= aving a physically typed in number (i.e. Pipe_Stages <=3D 3). Maybe someone should suggest the idea of entity output constants that can b= e used as we use constants today as an enhancement to the VHDL standard. I= know Jim Lewis is looking for more work (**not**) to pile on to the next r= evision of the standard. But if anyone wants to take up the torch, go to= =20 http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: upside down generics or so Date: Tue, 16 Aug 2016 09:56:06 -0400 Organization: A noiseless patient Spider Lines: 113 Message-ID: References: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> <8a14e1c4-1097-42e5-8270-7de62fae7e0e@googlegroups.com> <92a0345f-f4b8-44fe-b245-feeb16c8f029@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 16 Aug 2016 13:56:10 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="27333"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/f0MBLSaS77xMTSY3rlAJV" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <92a0345f-f4b8-44fe-b245-feeb16c8f029@googlegroups.com> Cancel-Lock: sha1:y8InzjFeSJPP2v3RsMUl/UgHjlc= Xref: news.eternal-september.org comp.lang.vhdl:4566 On 8/16/2016 9:41 AM, KJ wrote: > On Tuesday, August 16, 2016 at 12:43:22 AM UTC-4, rickman wrote: >> On 8/15/2016 7:55 AM, KJ wrote: >>> >>> It depends on the algorithm, period. Once the source code for >>> the module is written, the latency number has been locked down. >>> The number of pipeline stages will be determined once the >>> algorithm is coded. At that point you know the number and that >>> number can then be put into a package along with other module >>> related things. If you later change the algorithm in some way >>> that changes the number of pipeline stages, you change the >>> number...to match the change in the algorithm. Not rocket >>> science. >> >> No, and the fact that this will cause errors from forgetting to >> change corresponding data in other modules is not rocket science >> either. >> > > The error gets checked by the assertion in the testbench. So, on the > assumption that one would run their testbench after entering a design > change then the error gets immediately caught. Not much different in > that regard then when I mistype something and the compiler catches > the error. Yes you did have to write the code that does the checking > and get that all working whereas the typo gets caught by code that > has had a lot more eyeballs looking at it and a lot more users using > it, but the point is that once that checking code is debugged and > working then when a design error gets created via a design change, > the code does catch it...if you simulate your design. Yes, there is the extra code which has to be made to work... but error checking code is also extra testing. One mistake is to write it so it doesn't flag errors at all so it has to be tested to show it catches errors which is a PITA. Eyeballs are not a good way to catch errors like this. Eyes glaze over reading code and miss important details. Bottom line is having one location for a constant is a whole lot better than maintaining values in two places with error checking. >>> The point is to remove any dependency for the user of the module >>> from having to know what the latency is exactly. The user of the >>> module just needs to know where to reference that number from >>> which is in the package that comes along with the module. >>> >>> Suggesting that the module should be developed so that the >>> module creator should somehow be off the hook for defining and >>> publishing in the package the latency number is misguided. >> >> I don't understand why you say this. If you could design the >> module to return a value telling you the number of pipeline stages >> so the data did not need to be separately maintained in other >> module it would be less error prone. But there doesn't seem to be >> a way for a module to return a generic. >> > I'm not disagreeing that if you could create a constant output that > could in all cases be used just like a real constant then this would > provide a different method to accomplish the goal. Some can see it > as better, some just see it as different, that's OK. I've identified specifically why this is preferred, unfortunately not possible to do in the simple way hoped for, but there seems to be a way to do it, perhaps. > I think it would be useful. But I would want to be able to use that > output constant just like any other constant. So, based on the > latency for a number of modules cascaded together, I could compute > the depth of a memory that will be needed to collect up all the > pipelined data that comes out after the output interface says to > wait. Or to use that constant in a generate statement. Stuff like > that. That is exactly the point. > But as far I've seen in this discussion, that number still looks like > it gets typed into the architecture and is therefore potentially > wrong. If you change the design to add another pipeline stage, that > number doesn't magically change to the new number so you have an > error. Bantering about whether to change a typed in number in the > architecture or the package ***for that same module*** is splitting > hairs. We can't eliminate mistakes. We can minimize the chance they will go uncaught and minimize the difficulty in finding them. There is no problem or difficulty with having one constant in the code module it is related to that doesn't also exist in the method where the same constant has to be maintained in two locations. > For it truly to be correct by design, that constant output should be > calculated from the number of pipeline stages in the design. So if > you add/remove a pipeline stage, nothing else need be done because > the output constant would have a formula to it not just a number > (i.e. Pipe_Stages <= Pipeline'length). Maybe that is what the OP is > doing anyway rather than actually having a physically typed in number > (i.e. Pipe_Stages <= 3). > > Maybe someone should suggest the idea of entity output constants that > can be used as we use constants today as an enhancement to the VHDL > standard. I know Jim Lewis is looking for more work (**not**) to > pile on to the next revision of the standard. But if anyone wants to > take up the torch, go to > http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome > > Kevin Jennings > -- Rick C From newsfish@newsfish Thu Aug 1 00:37:45 2024 X-Received: by 10.237.53.75 with SMTP id b11mr25703519qte.4.1471369620126; Tue, 16 Aug 2016 10:47:00 -0700 (PDT) X-Received: by 10.36.107.194 with SMTP id v185mr58193itc.10.1471369620086; Tue, 16 Aug 2016 10:47:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!c52no9133652qte.1!news-out.google.com!d130ni37312ith.0!nntp.google.com!f6no10434489ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Aug 2016 10:46:58 -0700 (PDT) In-Reply-To: <0ee91dd9-7e3e-4478-8439-2d96bf361054@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> <0ee91dd9-7e3e-4478-8439-2d96bf361054@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2ea63787-15c4-48fb-8a81-de6c59595a68@googlegroups.com> Subject: Re: upside down generics or so From: Ilya Kalistru Injection-Date: Tue, 16 Aug 2016 17:47:00 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 179 Xref: news.eternal-september.org comp.lang.vhdl:4567 On Monday, August 15, 2016 at 3:22:13 PM UTC+3, KJ wrote: > On Saturday, August 13, 2016 at 12:45:26 PM UTC-4, Ilya Kalistru wrote: > > On Saturday, August 13, 2016 at 8:33:15 AM UTC+3, rickman wrote: > > > On 8/13/2016 12:58 AM, Allan Herriman wrote: > > > > On Fri, 12 Aug 2016 23:28:13 -0400, rickman wrote: > > > > > > > >> On 8/12/2016 11:09 PM, Allan Herriman wrote: > > > >>> On Fri, 12 Aug 2016 10:12:40 -0700, Ilya Kalistru wrote: > > > >>> > > > >>>> On Friday, August 12, 2016 at 5:39:36 PM UTC+3, Jim Lewis wrote: > > > >>>>> I would put a constant in a package that is associated with a > > > >>>>> particular entity. As you do your detailed design and update t= he > > > >>>>> pipeline in a particular block, simply update the corresponding > > > >>>>> constant in the package - even better would be to use that cons= tant > > > >>>>> to define the number of pipeline stages in the block. > > > >>>>> > > > >>>>> Then any design that references the package can see the constan= t. > > > >>>> > > > >>>> That's exactly what I've done. But when you are modifying the mo= dule > > > >>>> you have to remember that somewhere in a different file (package= ) > > > >>>> there is a constant you have to adjust according to you changes. > > > >>> > > > >>> > > > >>> I contend that you *don't* have to remember to adjust that, as lo= ng as > > > >>> you: > > > >>> > > > >>> 1. Write an assert statement inside your module that checks that= the > > > >>> package constant has the value that matches your design. I sugge= st a > > > >>> higher severity level on the assertion, e.g. failure. > > > >>> > > > >>> 2. You remember to simulate your design (so that the assertion c= an be > > > >>> checked). I wouldn't rely on a synthesiser to check an assertion= , but > > > >>> all simulators should work properly. > > > >>> > > > >>> > > > >>> (In any reasonable development process) you'll already be require= d to > > > >>> simulate your testbench before committing your code change. > > > >>> The only new thing you have to do is add the 1 line of assertion > > > >>> statement in your module. > > > >> > > > >> So when a change is made to the pipeline depth a change will need = to be > > > >> made for adjusting the delay pipeline in two places. > > > > > > > > > > > > A change is need in two places: the pipeline depth inside the modul= e and > > > > the constant in the package. > > > > > > > > The assert statement checks one against the other and won't need to= be > > > > changed. You're doing something wrong if you need to change the as= sert > > > > statement as well, because then you're not checking the constant in= the > > > > package directly against the thing it's meant to track. > > >=20 > > > Not sure what you are saying about "pipeline depth". The module has= =20 > > > functionality that uses some number of logic pipeline stages. This h= as=20 > > > to be noted in the module as a constant to use in the assert statemen= t,=20 > > > otherwise it is not needed in the module. This value also must be no= ted=20 > > > as a constant in the package to correspond to the module. These two= =20 > > > values must be kept in sync and also aligned with the design of the m= odule. > > >=20 > > > Maybe this is not as big issue as I am thinking since it is not likel= y=20 > > > the modules will change pipeline depths. Rather modules will be adde= d=20 > > > or replaced by other modules. But in addition to keeping the two=20 > > > constants in sync with the module design, the use of the module has t= o=20 > > > be kept in sync with the corresponding constant being passed into the= =20 > > > module as well as the use in defining the delay pipeline. > > >=20 > > > This sounds like a lot of work to me and potentially error prone whic= h=20 > > > is what it is trying to prevent. It also ends up being a bit verbose= =20 > > > which is one of the problems with VHDL. The use of various tools has= =20 > > > made design of VHDL code a bit easier, but I know I get tired of all = the=20 > > > typing I have to do when making changes which end up being manual mos= tly. > > >=20 > > >=20 > > > >> One to check the > > > >> other. I guess that's one way to make this work. > > > > > > > > Are you implying you have a better way (that works with the current > > > > language and tools)? Please tell - I'm always happy to learn new > > > > techniques. > > >=20 > > > My opinion is to not do it at all. The documentation of the module c= an=20 > > > provide the logic pipeline depth used and the designer can work it ou= t=20 > > > in the unit using the module. I think that would be easier and less= =20 > > > error prone in real usage. I can't tell how many times I have gone t= o=20 > > > lengths to try to prevent errors only to find I have done more work t= hat=20 > > > is useful. Sometimes simpler is better. > > >=20 > > > --=20 > > >=20 > > > Rick C > >=20 > > hm... It's sad that there is no such thing like output generic. It woul= d=20 > > make a lot of things much easier. > >=20 >=20 > I don't think you've shown in what way it would be 'easier'. The only th= ing different is where you type in the value of the constant. Maybe it's '= easier' to type it in the architecture, but it's shouldn't really be 'harde= r' to type it into the package. Modules typically have packages that are p= aired with the entity/architecture. >=20 > > BTW when it comes to simulation, I have a method I use to check=20 > > correctness of pipelines length: > > There is usually something like Data.Valid signal or Data.EndOfPacket= =20 > > signal or something like that. When you merge two pipelines you usually= =20 > > really need only one of them from one of the pipelines, but I make an= =20 > > assert to check that both of them are aligned. > > Sometimes I even add such a signal just for debugging purposes. > > Unfortunately, it's not always possible. >=20 > What were the details of the case where this was not possible? >=20 > Kevin Jennings > I don't think you've shown in what way it would be 'easier'. I mean that if you have it right in the architecture section it's more like= ly to spot that constant during the process of code editing than if have it in a package. > What were the details of the case where this was not possible? Sorry - maybe "possible" is a wrong word. It's better to say that it can be= not so handy. For example you have a module where data go without any distinct Data.Valid or Data.Last signal and to implement that technique you add artificial signal which goes along with data through all the stages and is meant to be checked during simulation, but be removed by synsesizer as a signal without load. In that case you have to do additional work to add t= hat superfluous signal. Moreover, when I was editing one of such modules once, = I added another stage to data processing but forgot to add another stage to that additional signal. During testing process I didn't see reports on wron= g latencies but saw corrupted data and it took me awhile to find the mistake. From newsfish@newsfish Thu Aug 1 00:37:45 2024 X-Received: by 10.157.4.197 with SMTP id 63mr21916920otm.31.1471370162276; Tue, 16 Aug 2016 10:56:02 -0700 (PDT) X-Received: by 10.36.91.205 with SMTP id g196mr545978itb.0.1471370162255; Tue, 16 Aug 2016 10:56:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no10437779ith.0!news-out.google.com!d130ni37339ith.0!nntp.google.com!f6no10437778ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Aug 2016 10:56:01 -0700 (PDT) In-Reply-To: <0ee91dd9-7e3e-4478-8439-2d96bf361054@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <8c5d386c-7c32-4223-b0dd-1003232d2720@googlegroups.com> <57ae8f84$0$11104$c3e8da3@news.astraweb.com> <57aea904$0$2824$c3e8da3$76491128@news.astraweb.com> <4c7d87f6-2305-410e-ad09-7e31f01c2d38@googlegroups.com> <0ee91dd9-7e3e-4478-8439-2d96bf361054@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: Ilya Kalistru Injection-Date: Tue, 16 Aug 2016 17:56:02 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4568 > I don't think you've shown in what way it would be 'easier'. I mean that if you have it right in the architecture section it's more likely to spot that constant during the process of code editing than if have it in a package. > What were the details of the case where this was not possible? Sorry - maybe "possible" is a wrong word. It's better to say that it can be not so handy. For example you have a module where data go without any distinct Data.Valid or Data.Last signal and to implement that technique you add artificial signal which goes along with data through all the stages and is meant to be checked during simulation, but be removed by synthesizer as a signal without load. In that case you have to do additional work to add that superfluous signal. Moreover, when I was editing one of such modules once, I added another stage to data processing but forgot to add another stage to that additional signal. During testing process I didn't see reports on wrong latencies but saw corrupted data and it took me awhile to find the mistake. From newsfish@newsfish Thu Aug 1 00:37:46 2024 X-Received: by 10.157.26.107 with SMTP id u40mr22956073otu.44.1471370688815; Tue, 16 Aug 2016 11:04:48 -0700 (PDT) X-Received: by 10.36.189.74 with SMTP id x71mr332952ite.4.1471370688793; Tue, 16 Aug 2016 11:04:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no10464946ith.0!news-out.google.com!d130ni37339ith.0!nntp.google.com!f6no10441420ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Aug 2016 11:04:48 -0700 (PDT) In-Reply-To: <92a0345f-f4b8-44fe-b245-feeb16c8f029@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> <8a14e1c4-1097-42e5-8270-7de62fae7e0e@googlegroups.com> <92a0345f-f4b8-44fe-b245-feeb16c8f029@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: upside down generics or so From: Ilya Kalistru Injection-Date: Tue, 16 Aug 2016 18:04:48 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4569 > Maybe that is what the OP is doing anyway rather than actually having a > physically typed in number (i.e. Pipe_Stages <= 3). Upper levels of design calculate their latency based on the length of lower-lewel modules and length of latency adjusting buffers of different sub-pipelines, but modules on the lowest level of hierarchy which really do stuff have their latency as a physically typed number. Unfortunately, I don't know how to calculate it automatically. :( From newsfish@newsfish Thu Aug 1 00:37:46 2024 X-Received: by 10.107.147.136 with SMTP id v130mr27550952iod.28.1471380490148; Tue, 16 Aug 2016 13:48:10 -0700 (PDT) X-Received: by 10.36.115.203 with SMTP id y194mr583400itb.0.1471380488029; Tue, 16 Aug 2016 13:48:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no10504605ith.0!news-out.google.com!d130ni37436ith.0!nntp.google.com!f6no10480322ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Aug 2016 13:48:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <7dba33e1-19df-43a2-a93b-d2a35ed1bfa3@googlegroups.com> <8a14e1c4-1097-42e5-8270-7de62fae7e0e@googlegroups.com> <92a0345f-f4b8-44fe-b245-feeb16c8f029@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7943f46c-b89d-4de2-9c1e-b7c087220a69@googlegroups.com> Subject: Re: upside down generics or so From: Lars Asplund Injection-Date: Tue, 16 Aug 2016 20:48:10 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4570 > Bantering about whether to change a typed in number in the architecture o= r the package ***for that same module*** is splitting hairs. Asking the object that actually creates the latency property (the module in= stance) rather than another object (the package) associated with that first= object enables better information hiding. We saw that in the example of a = latency depending on the generics. This is, to me, a significant difference= . Keeping the property close to its origin is probably less error-prone whe= n we need to remember to keep things in sync but the difference to a packag= e in the same file is probably minor. > But I would want to be able to use that output constant just like any oth= er constant An external name like <> can= be used like any other constant. The only difference I can come to think o= f is that it can only be used after the target of the reference, in this ca= se my_inst, has been elaborated. This is a bit inconvenient. If, for exampl= e, a module's latency depends on the latency for its submodules the latency= constant cannot be placed in the architecture declarative part. It has to = be placed after the submodules have been instantiated such that their laten= cies can be referenced with external names. One way of solving this, which = I used in my example, is to have a block statement at the end of the archit= ecture that contains the constant. I labeled this statement properties as c= an be seen in <> As an advocate for unit testing I don't mind at all if I have to add anothe= r unit test to check the provided latency. In case my module has no data va= lid signals there is no extra work since the latency constant will be used = and verified anyway (to know when to verify the output for a given test inp= ut). If I have data valid signals it's easy to forget verifying the constan= t but such a design would often have a delayline between the input and outp= ut data valid defined as a std_logic_vector of latency length. If that does= n't match the main processing pipeline the tests will fail. There's still a= risk that something like a "quick fix", adding an extra pipelining step on= top of the original design, creates an off-by-one error in the latency con= stant not detected by the tests. From newsfish@newsfish Thu Aug 1 00:37:46 2024 X-Received: by 10.237.44.38 with SMTP id f35mr6800959qtd.18.1471635862424; Fri, 19 Aug 2016 12:44:22 -0700 (PDT) X-Received: by 10.36.127.195 with SMTP id r186mr135472itc.0.1471635862353; Fri, 19 Aug 2016 12:44:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j37no9452305qta.0!news-out.google.com!d130ni40434ith.0!nntp.google.com!f6no11299410ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Aug 2016 12:44:21 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=181.60.36.178; posting-account=o8NCsAoAAACgDevh4ag1CB7Rx22h4iaD NNTP-Posting-Host: 181.60.36.178 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9866067d-f59e-4762-9ce0-4f7eacf5802f@googlegroups.com> Subject: generar Layout a partir de VHDL From: fabmaulopcan@gmail.com Injection-Date: Fri, 19 Aug 2016 19:44:22 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1202 X-Received-Body-CRC: 369077277 Xref: news.eternal-september.org comp.lang.vhdl:4571 Alguien a utilizado alguna vez synopsys?? Como puedo generar un Layout a partir de un c=C3=B3digo VHDL por bloques (u= nidos por medio de la instrucci=C3=B3n Portmap) todo desde synopsys. Gracias From newsfish@newsfish Thu Aug 1 00:37:46 2024 X-Received: by 10.107.147.136 with SMTP id v130mr17088493iod.28.1471871881128; Mon, 22 Aug 2016 06:18:01 -0700 (PDT) X-Received: by 10.36.217.2 with SMTP id p2mr625671itg.5.1471871881103; Mon, 22 Aug 2016 06:18:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no11997281ith.0!news-out.google.com!d130ni43382ith.0!nntp.google.com!f6no11997278ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Aug 2016 06:18:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Splitting 16 bit vector into 2 bytes From: David Perry Injection-Date: Mon, 22 Aug 2016 13:18:01 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4572 I have a 16 bit vector which I want to split into 2 8 bit vectors, I though= t I would be able to do this: (Tx_Byte_4, Tx_Byte_3) <=3D INV_Volts; --this no worky I want to split the 16 bit voltage value into 2 bytes to be transmitted lat= er. Obviously I could avoid the problem by assigning (15:8) to byte 4 and (7:0)= to byte 3 (I was doing this originally), but I am trying to avoid doing th= at, it's not quite as neat :) Is there any decent reference to this stuff? I'm finding that I end up just= trying things and see if it compiles and does what I think it does, which = is a pain and obviously not the best way to find out how to do such things.= Almost all of the documentation I find only deals with the absolute basics= :( From newsfish@newsfish Thu Aug 1 00:37:47 2024 X-Received: by 10.200.48.82 with SMTP id g18mr16405928qte.21.1471877231159; Mon, 22 Aug 2016 07:47:11 -0700 (PDT) X-Received: by 10.36.189.129 with SMTP id x123mr343758ite.1.1471877231023; Mon, 22 Aug 2016 07:47:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!j37no9964345qta.0!news-out.google.com!d130ni43430ith.0!nntp.google.com!f6no12041441ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Aug 2016 07:47:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Splitting 16 bit vector into 2 bytes From: David Perry Injection-Date: Mon, 22 Aug 2016 14:47:11 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:4573 I've ended up using alias's, the code is neater but there's still magic numbers in the alias's :( From newsfish@newsfish Thu Aug 1 00:37:47 2024 X-Received: by 10.66.192.169 with SMTP id hh9mr17256590pac.24.1471888654543; Mon, 22 Aug 2016 10:57:34 -0700 (PDT) X-Received: by 10.36.91.200 with SMTP id g191mr184389itb.5.1471888654502; Mon, 22 Aug 2016 10:57:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no12082977ith.0!news-out.google.com!d68ni35772ith.0!nntp.google.com!f6no12056854ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Aug 2016 10:57:33 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <48efbafa-4859-4cee-8de8-1fb0803d6af8@googlegroups.com> Subject: Re: Splitting 16 bit vector into 2 bytes From: KJ Injection-Date: Mon, 22 Aug 2016 17:57:34 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4574 On Monday, August 22, 2016 at 9:18:05 AM UTC-4, David Perry wrote: > I have a 16 bit vector which I want to split into 2 8 bit vectors, I thought I would be able to do this: > (Tx_Byte_4, Tx_Byte_3) <= INV_Volts; --this no worky > I want to split the 16 bit voltage value into 2 bytes to be transmitted later. If Tx_Byte_4 happens to be defined as (15 downto 8) and Tx_Byte_3 defined as (7 downto 0), then you could write it as: Tx_Byte_4 <= INV_Volts(Tx_Byte_4'range); Tx_Byte_3 <= INV_Volts(Tx_Byte_3'range); Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Splitting 16 bit vector into 2 bytes Date: Mon, 22 Aug 2016 20:57:42 -0400 Organization: A noiseless patient Spider Lines: 55 Message-ID: References: <48efbafa-4859-4cee-8de8-1fb0803d6af8@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 23 Aug 2016 00:57:41 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="26703"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+aCm1j4rLPvOcq7cNz6/XF" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <48efbafa-4859-4cee-8de8-1fb0803d6af8@googlegroups.com> Cancel-Lock: sha1:a7aYuyoKqDIMSgDftsnLdyenOhs= Xref: news.eternal-september.org comp.lang.vhdl:4575 On 8/22/2016 1:57 PM, KJ wrote: > On Monday, August 22, 2016 at 9:18:05 AM UTC-4, David Perry wrote: >> I have a 16 bit vector which I want to split into 2 8 bit vectors, I thought I would be able to do this: >> (Tx_Byte_4, Tx_Byte_3) <= INV_Volts; --this no worky >> I want to split the 16 bit voltage value into 2 bytes to be transmitted later. > > If Tx_Byte_4 happens to be defined as (15 downto 8) and Tx_Byte_3 defined as (7 downto 0), then you could write it as: > > Tx_Byte_4 <= INV_Volts(Tx_Byte_4'range); > Tx_Byte_3 <= INV_Volts(Tx_Byte_3'range); Or you can do some shifting... Tx_Byte_4 <= RESIZE(srl(unsigned(INV_Volts),Tx_Byte_3'LENGTH),Tx_Byte_4'LENGTH); Tx_Byte_3 <= INV_Volts(Tx_Byte_3'range); Pretty groady. Or you can do some math without the numbers... Tx_Byte_4 <= INV_Volts(Tx_Byte_4'HIGH+Tx_Byte_3'LENGTH downto Tx_Byte_3'LENGTH); Tx_Byte_3 <= INV_Volts(Tx_Byte_3'range); Still far from compact. It would be simpler if there was a way to specify a range plus an offset. Then the high byte assignment would be just... Tx_Byte_4 <= INV_Volts(Tx_Byte_4'RANGE+Tx_Byte_3'LENGTH); Not quite as bad. ranges in VHDL always get messy. The simplest approach is something like KJ's suggestion or I would define ranges to use... subtype ByteRngHi is Integer range 15 downto 8; subtype ByteRngLo is Integer range 7 downto 0; Tx_Byte_4 <= INV_Volts(ByteRngHi); Tx_Byte_3 <= INV_Volts(ByteRngLo); I actually defined four such ranges for four bytes in a 32 bit word. Here is my use of a couple. IF (RamLobWr = '1') THEN DataSramLo (RamAddr) <= DatTosReg(ByteRng0); END IF; IF (RamHibWr = '1') THEN DataSramHi (RamAddr) <= DatTosReg(ByteRng1); END IF; -- Rick C From newsfish@newsfish Thu Aug 1 00:37:48 2024 X-Received: by 10.157.4.197 with SMTP id 63mr18843540otm.31.1471916727692; Mon, 22 Aug 2016 18:45:27 -0700 (PDT) X-Received: by 10.36.227.67 with SMTP id d64mr754067ith.3.1471916727633; Mon, 22 Aug 2016 18:45:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no12152437ith.0!news-out.google.com!d130ni43885ith.0!nntp.google.com!f6no12152428ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Aug 2016 18:45:27 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.24.182; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.24.182 References: <48efbafa-4859-4cee-8de8-1fb0803d6af8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Splitting 16 bit vector into 2 bytes From: diogratia@gmail.com Injection-Date: Tue, 23 Aug 2016 01:45:27 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4576 On Tuesday, August 23, 2016 at 12:57:44 PM UTC+12, rickman wrote: > On 8/22/2016 1:57 PM, KJ wrote: > > On Monday, August 22, 2016 at 9:18:05 AM UTC-4, David Perry wrote: > Or you can do some shifting... Or you can hide the magic (numbers) in a package: library ieee; use ieee.std_logic_1164.all; package byte_games is subtype byte1_range is integer range 15 downto 8; subtype byte0_range is integer range 7 downto 0; subtype byte is std_logic_vector(byte0_range); type two_byte is record byte1: byte; byte0: byte; end record; end package; library ieee; use ieee.std_logic_1164.all; use work.byte_games.all; entity foo is end entity; architecture fum of foo is signal tx_Byte_4: std_logic_vector (7 downto 0); signal tx_Byte_3: std_logic_vector (7 downto 0); signal INV_Volts: std_logic_vector (15 downto 0); function to_string (inp: std_logic_vector) return string is variable image_str: string (1 to inp'length); alias input_str: std_logic_vector (1 to inp'length) is inp; begin for i in input_str'range loop image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i))); end loop; return image_str; end function; begin process begin INV_Volts <= x"1234"; wait for 0 ns; -- (Tx_Byte_4, Tx_Byte_3) <= INV_Volts; --this no worky (Tx_Byte_4, Tx_Byte_3) <= two_byte'(INV_Volts(byte1_range), INV_Volts(byte0_range)); wait for 0 ns; report "Tx_Byte_4 = " & to_string(Tx_Byte_4); report "Tx_Byte_3 = " & to_string(Tx_Byte_3); wait; end process; end architecture; ghdl -r foo foo.vhdl:44:9:@0ms:(report note): Tx_Byte_4 = 00010010 foo.vhdl:45:9:@0ms:(report note): Tx_Byte_3 = 00110100 (The to_string function is predefined in -2008). From newsfish@newsfish Thu Aug 1 00:37:48 2024 X-Received: by 10.13.214.202 with SMTP id y193mr3353009ywd.19.1472068015600; Wed, 24 Aug 2016 12:46:55 -0700 (PDT) X-Received: by 10.36.237.193 with SMTP id r184mr65148ith.2.1472068015566; Wed, 24 Aug 2016 12:46:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j37no10438409qta.0!news-out.google.com!d130ni45653ith.0!nntp.google.com!f6no12671119ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Aug 2016 12:46:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <48efbafa-4859-4cee-8de8-1fb0803d6af8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <523eaad6-5c68-4b12-810d-eb0379636d0a@googlegroups.com> Subject: Re: Splitting 16 bit vector into 2 bytes From: Lars Asplund Injection-Date: Wed, 24 Aug 2016 19:46:55 +0000 Content-Type: text/plain; charset=UTF-8 X-Received-Bytes: 1904 X-Received-Body-CRC: 3656255337 Xref: news.eternal-september.org comp.lang.vhdl:4577 If you want to split INV_Volts between Tx_Byte_4 and Tx_Byte_3 you could express just that with a procedure call. For example split(INV_Volts, between => Tx_Byte_4, \and\ => Tx_Byte_3); Readable? I guess that depends who you're asking. The extended \and\ identifier is likely to confuse people and tools. Anyway, such a procedure would be somewhat generic with respect to the vector ranges and there are no magic numbers. Example code/testbench is here: https://github.com/LarsAsplund/splitting_signals/blob/master/test/tb_split.vhd The testbench report is here: https://travis-ci.org/LarsAsplund/splitting_signals From newsfish@newsfish Thu Aug 1 00:37:48 2024 X-Received: by 10.237.40.5 with SMTP id r5mr3642027qtd.20.1472574739083; Tue, 30 Aug 2016 09:32:19 -0700 (PDT) X-Received: by 10.36.137.67 with SMTP id s64mr626561itd.1.1472574739050; Tue, 30 Aug 2016 09:32:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!c52no11953137qte.1!news-out.google.com!b4ni4801iti.0!nntp.google.com!n75no197706ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Aug 2016 09:32:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: A constant signal in a case if hierarchical procedure calls From: Ilya Kalistru Injection-Date: Tue, 30 Aug 2016 16:32:19 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 51 Xref: news.eternal-september.org comp.lang.vhdl:4578 Hello. I=E2=80=99d like to know your opinion on an issue I met. I used a procedure in my code. Let=E2=80=99s say that it is the procedure (It=E2=80=99s not. Just an example): procedure p1( signal clk : in std_logic; signal A : in std_logic; signal C : out std_logic ) is begin loop wait until rising_edge(clk); C <=3D A xor =E2=80=981=E2=80=99; end loop; end procedure p1; Then I decided that I needed extended version of the procedure, so I rewrote it using a new procedure name p2 for extended version, and I just called the new procedure p2 with a constant parameter in the old procedure p1 like that: procedure p2( signal clk : in std_logic; signal A : in std_logic; signal B : in std_logic; signal C : out std_logic ) is begin loop wait until rising_edge(clk); C <=3D A xor B; end loop; end procedure p2; =20 procedure p1( signal clk : in std_logic; signal A : in std_logic; signal C : out std_logic ) is begin p2(clk, A, '1', C); end procedure p1; =20 The problem is that I got an error ERROR: [VRFC 10-275] actual '1' of formal b must be a signal [D:/VHDL_proj/= test1/test1.srcs/sources_1/new/test.vhd:59] Is it impossible to call a subprogram from an another subprogram, assigning an actual constant to a formal signal parameter of the internal subprogram? From newsfish@newsfish Thu Aug 1 00:37:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: A constant signal in a case if hierarchical procedure calls Date: Tue, 30 Aug 2016 15:48:17 -0400 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 30 Aug 2016 19:48:18 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="21929"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mk5nOIVSJdhYnZnsEX3NU" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: Cancel-Lock: sha1:lbTEk7Qdbsn+lGzCxYBEFsCA36Q= Xref: news.eternal-september.org comp.lang.vhdl:4579 On 8/30/2016 12:32 PM, Ilya Kalistru wrote: > Hello. > > I’d like to know your opinion on an issue I met. > I used a procedure in my code. Let’s say that it is the procedure > (It’s not. Just an example): > > procedure p1( > signal clk : in std_logic; > signal A : in std_logic; > signal C : out std_logic > ) is > begin > loop > wait until rising_edge(clk); > C <= A xor ‘1’; > end loop; > end procedure p1; > > Then I decided that I needed extended version of the procedure, > so I rewrote it using a new procedure name p2 for extended version, > and I just called the new procedure p2 with a constant parameter in > the old procedure p1 like that: > > procedure p2( > signal clk : in std_logic; > signal A : in std_logic; > signal B : in std_logic; > signal C : out std_logic > ) is > begin > loop > wait until rising_edge(clk); > C <= A xor B; > end loop; > end procedure p2; > > procedure p1( > signal clk : in std_logic; > signal A : in std_logic; > signal C : out std_logic > ) is > begin > p2(clk, A, '1', C); > end procedure p1; > > The problem is that I got an error > ERROR: [VRFC 10-275] actual '1' of formal b must be a signal [D:/VHDL_proj/test1/test1.srcs/sources_1/new/test.vhd:59] > > Is it impossible to call a subprogram from an another subprogram, > assigning an actual constant to a formal signal parameter of the > internal subprogram? Instead of using a literal (what your '1' really is), what happens if you declare a constant and use that? I think the problem may be that the tool doesn't know the type of the literal but a constant has a declared type. Or you can try indicating the type with type casting such as std_logic('1'). -- Rick C From newsfish@newsfish Thu Aug 1 00:37:49 2024 X-Received: by 10.129.122.72 with SMTP id v69mr5811698ywc.40.1472612570649; Tue, 30 Aug 2016 20:02:50 -0700 (PDT) X-Received: by 10.36.120.140 with SMTP id p134mr790721itc.10.1472612570612; Tue, 30 Aug 2016 20:02:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j37no11767909qta.0!news-out.google.com!n186ni706ith.0!nntp.google.com!n75no95108ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Aug 2016 20:02:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.24.182; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.24.182 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <75daf801-fc69-445e-8884-4bda6a36899a@googlegroups.com> Subject: Re: A constant signal in a case if hierarchical procedure calls From: diogratia@gmail.com Injection-Date: Wed, 31 Aug 2016 03:02:50 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4640 X-Received-Body-CRC: 1606623555 Xref: news.eternal-september.org comp.lang.vhdl:4580 On Wednesday, August 31, 2016 at 4:32:22 AM UTC+12, Ilya Kalistru wrote: > Hello. >=20 > I=E2=80=99d like to know your opinion on an issue I met. > I used a procedure in my code. Let=E2=80=99s say that it is the procedure > ... > Then I decided that I needed extended version of the procedure, > so I rewrote it using a new procedure name p2 for extended version, > and I just called the new procedure p2 with a constant parameter in > the old procedure p1 like that: >=20 > procedure p2( > signal clk : in std_logic; > signal A : in std_logic; > signal B : in std_logic; > signal C : out std_logic > ) is > begin > loop > wait until rising_edge(clk); > C <=3D A xor B; > end loop; > end procedure p2; > =20 > procedure p1( > signal clk : in std_logic; > signal A : in std_logic; > signal C : out std_logic > ) is > begin > p2(clk, A, '1', C); > end procedure p1; > =20 > The problem is that I got an error > ERROR: [VRFC 10-275] actual '1' of formal b must be a signal [D:/VHDL_pro= j/test1/test1.srcs/sources_1/new/test.vhd:59] >=20 > Is it impossible to call a subprogram from an another subprogram, > assigning an actual constant to a formal signal parameter of the > internal subprogram? Yes, it's impossible. IEEE Std 1076-2008 4.2.2.1 Formal parameter lists In a subprogram call, the actual designator (see 6.5.7.1) associated with a= formal parameter of class signal shall be a name denoting a signal. The ac= tual designator associated with a formal of class variable shall be a name = denoting a variable. The actual designator associated with a formal of clas= s constant shall be an expression. The actual designator associated with a = formal of class file shall be a name denoting a file. -- The actual in a subprogram call of a formal of class signal must be a signa= l. Note that a signal name is a primary in an expression and an expression can= consist solely of a primary. (9.1). While an expression can be associated as an actual of a formal in a port ma= p aspect the difference is that a subprogram call's parameter association e= lements are dynamically elaborated (14.6). If you are not using predefined signal attributes your inputs can be class = constant (the default). For use as a concurrent procedure call (11.4) the s= ensitivity list of the final wait statement in the equivalent process "is c= onstructed by taking the union of the sets constructed by applying the rule= of 10.2 to each actual part associated with a formal parameter". In other words sensitivity stems from the actual and not the formal, allowi= ng signals as primaries of expressions to provide events for resumption of = the equivalent process to a concurrent procedure call with parameters of mo= de in or inout ("for which reading is permitted" (10.2) that are class con= stant. The distinction is the inability to use predefined signal attributes of whi= ch 'STABLE, 'QUIET, 'TRANSACTION, and 'DELAYED are already disallowed for f= ormal signal parameters (4.2.2.3). So delete the reserved word signal in the declaration for parameter B in P2= resulting in class constant, or in general any signal you are not using a = signal attribute from. The function rising_edge depends on a signal paramet= er and uses signal attributes. From newsfish@newsfish Thu Aug 1 00:37:49 2024 X-Received: by 10.66.161.130 with SMTP id xs2mr5439969pab.40.1472613512119; Tue, 30 Aug 2016 20:18:32 -0700 (PDT) X-Received: by 10.36.228.11 with SMTP id o11mr505425ith.3.1472613512024; Tue, 30 Aug 2016 20:18:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!n75no337396ith.0!news-out.google.com!n186ni706ith.0!nntp.google.com!n75no96677ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Aug 2016 20:18:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.43.3.237; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.43.3.237 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Splitting 16 bit vector into 2 bytes From: Jim Lewis Injection-Date: Wed, 31 Aug 2016 03:18:32 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4581 > I have a 16 bit vector which I want to split into 2 8 bit vectors, I thought I would be able to do this: > (Tx_Byte_4, Tx_Byte_3) <= INV_Volts; --this no worky > I want to split the 16 bit voltage value into 2 bytes to be transmitted later. If your tool supports VHDL-2008, that will work. Did you turn on the VHDL-2008 switch? See KJ's solution for a good prior to VHDL-2008 solution. From newsfish@newsfish Thu Aug 1 00:37:50 2024 X-Received: by 10.157.54.216 with SMTP id s24mr6134778otd.49.1472621345977; Tue, 30 Aug 2016 22:29:05 -0700 (PDT) X-Received: by 10.36.228.76 with SMTP id o73mr294008ith.4.1472621345915; Tue, 30 Aug 2016 22:29:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!n75no109992ith.0!news-out.google.com!b4ni5301iti.0!nntp.google.com!n75no109986ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Aug 2016 22:29:05 -0700 (PDT) In-Reply-To: <75daf801-fc69-445e-8884-4bda6a36899a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=31.173.80.178; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 31.173.80.178 References: <75daf801-fc69-445e-8884-4bda6a36899a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: A constant signal in a case if hierarchical procedure calls From: Ilya Kalistru Injection-Date: Wed, 31 Aug 2016 05:29:05 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4582 Oh, thank you so much. It works. I thought that if a formal is defined as constant, its value will be fixed at the moment of procedure call and won't change no matter what. It's a surprise for me that value of a constant can be adjusted. ) From newsfish@newsfish Thu Aug 1 00:37:50 2024 X-Received: by 10.36.82.11 with SMTP id d11mr9512478itb.0.1472628294699; Wed, 31 Aug 2016 00:24:54 -0700 (PDT) X-Received: by 10.36.189.73 with SMTP id x70mr542932ite.4.1472628294633; Wed, 31 Aug 2016 00:24:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!n75no130400ith.0!news-out.google.com!b4ni5351iti.0!nntp.google.com!n75no130392ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 31 Aug 2016 00:24:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8b12a5f8-a51a-4fa7-b2c0-7567b73555c5@googlegroups.com> Subject: Re: Splitting 16 bit vector into 2 bytes From: David Perry Injection-Date: Wed, 31 Aug 2016 07:24:54 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:4583 You have all given me something to think about. I didn't realise you can define a sybtype of range, suddenly all my code will look a lot neater! I shall look into vhdl-2008, so far I've stayed with the default '93. From newsfish@newsfish Thu Aug 1 00:37:50 2024 X-Received: by 10.66.167.207 with SMTP id zq15mr8535901pab.7.1472672090581; Wed, 31 Aug 2016 12:34:50 -0700 (PDT) X-Received: by 10.36.120.140 with SMTP id p134mr1153724itc.10.1472672090544; Wed, 31 Aug 2016 12:34:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!e124no143671ith.0!news-out.google.com!b4ni5854iti.0!nntp.google.com!e124no143669ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 31 Aug 2016 12:34:50 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.24.182; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.24.182 References: <75daf801-fc69-445e-8884-4bda6a36899a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <27cf5f9b-804b-4ba6-9910-f9fcd342e6b2@googlegroups.com> Subject: Re: A constant signal in a case if hierarchical procedure calls From: diogratia@gmail.com Injection-Date: Wed, 31 Aug 2016 19:34:50 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4584 On Wednesday, August 31, 2016 at 5:29:07 PM UTC+12, Ilya Kalistru wrote: > Oh, thank you so much. It works. > > I thought that if a formal is defined as constant, its value will be fixed at the moment of procedure call and won't change no matter what. > It's a surprise for me that value of a constant can be adjusted. ) The value is passed as a parameter at elaboration time, which for subprograms is during evaluation when called - subprogram calls are dynamically elaborated. From newsfish@newsfish Thu Aug 1 00:37:51 2024 X-Received: by 10.157.6.11 with SMTP id 11mr9152577otn.7.1472678140086; Wed, 31 Aug 2016 14:15:40 -0700 (PDT) X-Received: by 10.36.103.4 with SMTP id u4mr1184662itc.9.1472678140060; Wed, 31 Aug 2016 14:15:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!e124no167640ith.0!news-out.google.com!n186ni1518ith.0!nntp.google.com!e124no167632ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 31 Aug 2016 14:15:39 -0700 (PDT) In-Reply-To: <27cf5f9b-804b-4ba6-9910-f9fcd342e6b2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <75daf801-fc69-445e-8884-4bda6a36899a@googlegroups.com> <27cf5f9b-804b-4ba6-9910-f9fcd342e6b2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: A constant signal in a case if hierarchical procedure calls From: Ilya Kalistru Injection-Date: Wed, 31 Aug 2016 21:15:40 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4585 On Wednesday, August 31, 2016 at 10:34:57 PM UTC+3, diog...@gmail.com wrote: > On Wednesday, August 31, 2016 at 5:29:07 PM UTC+12, Ilya Kalistru wrote: > > Oh, thank you so much. It works. > > > > I thought that if a formal is defined as constant, its value will be fixed at the moment of procedure call and won't change no matter what. > > It's a surprise for me that value of a constant can be adjusted. ) > > The value is passed as a parameter at elaboration time, which for subprograms is during evaluation when called - subprogram calls are dynamically elaborated. Then I don't understand why the process procedure p2( signal clk : in std_logic; signal A : in std_logic; B : in std_logic; signal C : out std_logic ) is begin loop wait until rising_edge(clk); C <= A xor B; end loop; end procedure p2; responds to changes of the constant B each cycle if the procedure was called only once. Does the process resuming after suspension count as a "call"? I can't find this part in the standard... From newsfish@newsfish Thu Aug 1 00:37:51 2024 X-Received: by 10.159.38.77 with SMTP id 71mr23995810uag.3.1472973264959; Sun, 04 Sep 2016 00:14:24 -0700 (PDT) X-Received: by 10.36.69.142 with SMTP id c14mr113850itd.2.1472973264899; Sun, 04 Sep 2016 00:14:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m9no431221qte.0!news-out.google.com!w143ni3409itb.0!nntp.google.com!e124no1038216ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Sep 2016 00:14:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.24.182; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.24.182 References: <75daf801-fc69-445e-8884-4bda6a36899a@googlegroups.com> <27cf5f9b-804b-4ba6-9910-f9fcd342e6b2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: A constant signal in a case if hierarchical procedure calls From: diogratia@gmail.com Injection-Date: Sun, 04 Sep 2016 07:14:24 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5435 X-Received-Body-CRC: 1480499521 Xref: news.eternal-september.org comp.lang.vhdl:4586 On Thursday, September 1, 2016 at 9:15:41 AM UTC+12, Ilya Kalistru wrote: > On Wednesday, August 31, 2016 at 10:34:57 PM UTC+3, diog...@gmail.com wro= te: > > On Wednesday, August 31, 2016 at 5:29:07 PM UTC+12, Ilya Kalistru wrote= : > > > Oh, thank you so much. It works. > > >=20 > > > I thought that if a formal is defined as constant, its value will be = fixed at the moment of procedure call and won't change no matter what. > > > It's a surprise for me that value of a constant can be adjusted. ) > >=20 > > The value is passed as a parameter at elaboration time, which for subpr= ograms is during evaluation when called - subprogram calls are dynamically = elaborated. >=20 > Then I don't understand why the process >=20 > procedure p2( > signal clk : in std_logic; > signal A : in std_logic; > B : in std_logic; > signal C : out std_logic > ) is > begin > loop > wait until rising_edge(clk); > C <=3D A xor B; > end loop; > end procedure p2; >=20 > responds to changes of the constant B each cycle if the procedure was cal= led > only once. > Does the process resuming after suspension count as a "call"? I can't fin= d > this part in the standard... It's not responding to B, it's responding to the condition rising_edge (clk= ) in the condition clause of the wait statement in p2. =20 IEEE Std 1076-2008 10.2 Wait statements paragraphs 8, 9 and 10: The execution of a wait statement causes the time expression to be evaluate= d to determine the timeout interval. It also causes the execution of the co= rresponding process statement to be suspended, where the corresponding proc= ess statement is the one that either contains the wait statement or is the = parent (see 4.3) of the procedure that contains the wait statement. The sus= pended process will resume, at the latest, immediately after the timeout in= terval has expired. The suspended process also resumes as a result of an event occurring on any= signal in the sensitivity set of the wait statement. If such an event occu= rs, the condition in the condition clause is evaluated. If the value of the= condition is FALSE, the process suspends again. Such repeated suspension d= oes not involve the recalculation of the timeout interval. It is an error if a wait statement appears in a function subprogram or in a= procedure that has a parent that is a function subprogram. Furthermore, it= is an error if a wait statement appears in an explicit process statement t= hat includes a sensitivity list or in a procedure that has a parent that is= such a process statement. Finally, it is an error if a wait statement appe= ars within any subprogram whose body is declared within a protected type bo= dy, or within any subprogram that has a parent whose body is declared withi= n a protected type body. --=20 (There's a default timeout clause described in paragraph 7, every wait stat= ement will timeout at TIME'HIGH). Neither procedure calls p1 nor p2 ever 'completes'. The parent process (whe= ther constructed from p1 if p1 is a concurrent process, or enclosing p1 sus= pends and resumes executing the wait statement in p2. p2 has an endless lo= op with a wait statement. If there were any other sequential statements fol= lowing the p2 sequential procedure call in p1 they'd never be executed. No = other sequential statements in the parent process will be executed. Any event on a signal in P2's wait statement sensitivity set derived from t= he condition clause will cause P2 to resume and evaluate it's condition. When the condition is satisfied p2 will execute the next sequential stateme= nt. It's in an endless loop that will wrap around. Wait statements are sequential statements, only one of them at a time can c= ause a parent process to suspend. To have a different wait statement cause = the parent process to suspend it has to be reached. That can't happen here.= =20 From newsfish@newsfish Thu Aug 1 00:37:51 2024 X-Received: by 10.66.73.101 with SMTP id k5mr11135310pav.9.1472980717142; Sun, 04 Sep 2016 02:18:37 -0700 (PDT) X-Received: by 10.36.103.4 with SMTP id u4mr395572itc.9.1472980717088; Sun, 04 Sep 2016 02:18:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i184no1046872itf.0!news-out.google.com!b4ni9382iti.0!nntp.google.com!e124no1054987ith.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Sep 2016 02:18:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.182; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.182 References: <75daf801-fc69-445e-8884-4bda6a36899a@googlegroups.com> <27cf5f9b-804b-4ba6-9910-f9fcd342e6b2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <256151e9-109e-4d17-a480-973510c00035@googlegroups.com> Subject: Re: A constant signal in a case if hierarchical procedure calls From: Ilya Kalistru Injection-Date: Sun, 04 Sep 2016 09:18:37 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4587 On Sunday, September 4, 2016 at 10:14:27 AM UTC+3, diog...@gmail.com wrote: > On Thursday, September 1, 2016 at 9:15:41 AM UTC+12, Ilya Kalistru wrote: > > On Wednesday, August 31, 2016 at 10:34:57 PM UTC+3, diog...@gmail.com w= rote: > > > On Wednesday, August 31, 2016 at 5:29:07 PM UTC+12, Ilya Kalistru wro= te: > > > > Oh, thank you so much. It works. > > > >=20 > > > > I thought that if a formal is defined as constant, its value will b= e fixed at the moment of procedure call and won't change no matter what. > > > > It's a surprise for me that value of a constant can be adjusted. ) > > >=20 > > > The value is passed as a parameter at elaboration time, which for sub= programs is during evaluation when called - subprogram calls are dynamicall= y elaborated. > >=20 > > Then I don't understand why the process > >=20 > > procedure p2( > > signal clk : in std_logic; > > signal A : in std_logic; > > B : in std_logic; > > signal C : out std_logic > > ) is > > begin > > loop > > wait until rising_edge(clk); > > C <=3D A xor B; > > end loop; > > end procedure p2; > >=20 > > responds to changes of the constant B each cycle if the procedure was c= alled > > only once. > > Does the process resuming after suspension count as a "call"? I can't f= ind > > this part in the standard... >=20 > It's not responding to B, it's responding to the condition rising_edge (c= lk) in the condition clause of the wait statement in p2. =20 >=20 > IEEE Std 1076-2008 10.2 Wait statements paragraphs 8, 9 and 10: >=20 > The execution of a wait statement causes the time expression to be evalua= ted to determine the timeout interval. It also causes the execution of the = corresponding process statement to be suspended, where the corresponding pr= ocess statement is the one that either contains the wait statement or is th= e parent (see 4.3) of the procedure that contains the wait statement. The s= uspended process will resume, at the latest, immediately after the timeout = interval has expired. >=20 > The suspended process also resumes as a result of an event occurring on a= ny signal in the sensitivity set of the wait statement. If such an event oc= curs, the condition in the condition clause is evaluated. If the value of t= he condition is FALSE, the process suspends again. Such repeated suspension= does not involve the recalculation of the timeout interval. >=20 > It is an error if a wait statement appears in a function subprogram or in= a procedure that has a parent that is a function subprogram. Furthermore, = it is an error if a wait statement appears in an explicit process statement= that includes a sensitivity list or in a procedure that has a parent that = is such a process statement. Finally, it is an error if a wait statement ap= pears within any subprogram whose body is declared within a protected type = body, or within any subprogram that has a parent whose body is declared wit= hin a protected type body. >=20 > --=20 >=20 > (There's a default timeout clause described in paragraph 7, every wait st= atement will timeout at TIME'HIGH). >=20 > Neither procedure calls p1 nor p2 ever 'completes'. The parent process (w= hether constructed from p1 if p1 is a concurrent process, or enclosing p1 s= uspends and resumes executing the wait statement in p2. p2 has an endless = loop with a wait statement. If there were any other sequential statements f= ollowing the p2 sequential procedure call in p1 they'd never be executed. N= o other sequential statements in the parent process will be executed. >=20 > Any event on a signal in P2's wait statement sensitivity set derived from= the condition clause will cause P2 to resume and evaluate it's condition. >=20 > When the condition is satisfied p2 will execute the next sequential state= ment. It's in an endless loop that will wrap around. >=20 > Wait statements are sequential statements, only one of them at a time can= cause a parent process to suspend. To have a different wait statement caus= e the parent process to suspend it has to be reached. That can't happen her= e. I understand that. I don't understand other thing. Let's suppose initially actual B=3D0. As long as P2 is a concurrent process= it will be called at 0 ps. STD 2.1.1.1 For a nonforeign subprogram having a parameter of a scalar type or an access type, the parameter is passed by copy. At the start of each call= , if the mode is in or inout, the value of the actual parameter is copied into the associated formal parameter; At that moment value of the actual B=3D0 is copied to the formal B of the p= 2. After wait statement we resume p2 and execute "C <=3D A xor B" with form= al B =3D 0. Let's suppose that at that moment the actual B outside of the p= 2 is changed to '1'. As I understand, after next "wait until rising_edge(cl= k);" statement in p2 when the actual B=3D'1', formal B should still be '0' = because it's the value copied from actual to formal during call of the p2. In fact, the simulator behaves like it copies the actual B to the formal B = each time it resumes p2 after wait statement. From newsfish@newsfish Thu Aug 1 00:37:51 2024 X-Received: by 10.157.21.114 with SMTP id z47mr3161950otz.13.1473091119767; Mon, 05 Sep 2016 08:58:39 -0700 (PDT) X-Received: by 10.36.237.193 with SMTP id r184mr460366ith.2.1473091119736; Mon, 05 Sep 2016 08:58:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i184no1353244itf.0!news-out.google.com!b4ni10626iti.0!nntp.google.com!i184no1353236itf.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Sep 2016 08:58:39 -0700 (PDT) In-Reply-To: <256151e9-109e-4d17-a480-973510c00035@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.152.136.215; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.152.136.215 References: <75daf801-fc69-445e-8884-4bda6a36899a@googlegroups.com> <27cf5f9b-804b-4ba6-9910-f9fcd342e6b2@googlegroups.com> <256151e9-109e-4d17-a480-973510c00035@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <952ab298-407c-447b-8a81-3a7d14447e80@googlegroups.com> Subject: Re: A constant signal in a case if hierarchical procedure calls From: diogratia@gmail.com Injection-Date: Mon, 05 Sep 2016 15:58:39 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4588 On Sunday, September 4, 2016 at 9:18:54 PM UTC+12, Ilya Kalistru wrote: > On Sunday, September 4, 2016 at 10:14:27 AM UTC+3, diog...@gmail.com wrot= e: > > On Thursday, September 1, 2016 at 9:15:41 AM UTC+12, Ilya Kalistru wrot= e: > > > On Wednesday, August 31, 2016 at 10:34:57 PM UTC+3, diog...@gmail.com= wrote: > > > > On Wednesday, August 31, 2016 at 5:29:07 PM UTC+12, Ilya Kalistru w= rote: > > > > > Oh, thank you so much. It works. > > > > >=20 > > > > > I thought that if a formal is defined as constant, its value will= be fixed at the moment of procedure call and won't change no matter what. > > > > > It's a surprise for me that value of a constant can be adjusted. = ) > > > >=20 > > > > The value is passed as a parameter at elaboration time, which for s= ubprograms is during evaluation when called - subprogram calls are dynamica= lly elaborated. > > >=20 > > > Then I don't understand why the process > > >=20 > > > procedure p2( > > > signal clk : in std_logic; > > > signal A : in std_logic; > > > B : in std_logic; > > > signal C : out std_logic > > > ) is > > > begin > > > loop > > > wait until rising_edge(clk); > > > C <=3D A xor B; > > > end loop; > > > end procedure p2; > > >=20 > > > responds to changes of the constant B each cycle if the procedure was= called > > > only once. > > > Does the process resuming after suspension count as a "call"? I can't= find > > > this part in the standard... > >=20 > > It's not responding to B, it's responding to the condition rising_edge = (clk) in the condition clause of the wait statement in p2. =20 > >=20 > > IEEE Std 1076-2008 10.2 Wait statements paragraphs 8, 9 and 10: > >=20 > > The execution of a wait statement causes the time expression to be eval= uated to determine the timeout interval. It also causes the execution of th= e corresponding process statement to be suspended, where the corresponding = process statement is the one that either contains the wait statement or is = the parent (see 4.3) of the procedure that contains the wait statement. The= suspended process will resume, at the latest, immediately after the timeou= t interval has expired. > >=20 > > The suspended process also resumes as a result of an event occurring on= any signal in the sensitivity set of the wait statement. If such an event = occurs, the condition in the condition clause is evaluated. If the value of= the condition is FALSE, the process suspends again. Such repeated suspensi= on does not involve the recalculation of the timeout interval. > >=20 > > It is an error if a wait statement appears in a function subprogram or = in a procedure that has a parent that is a function subprogram. Furthermore= , it is an error if a wait statement appears in an explicit process stateme= nt that includes a sensitivity list or in a procedure that has a parent tha= t is such a process statement. Finally, it is an error if a wait statement = appears within any subprogram whose body is declared within a protected typ= e body, or within any subprogram that has a parent whose body is declared w= ithin a protected type body. > >=20 > > --=20 > >=20 > > (There's a default timeout clause described in paragraph 7, every wait = statement will timeout at TIME'HIGH). > >=20 > > Neither procedure calls p1 nor p2 ever 'completes'. The parent process = (whether constructed from p1 if p1 is a concurrent process, or enclosing p1= suspends and resumes executing the wait statement in p2. p2 has an endles= s loop with a wait statement. If there were any other sequential statements= following the p2 sequential procedure call in p1 they'd never be executed.= No other sequential statements in the parent process will be executed. > >=20 > > Any event on a signal in P2's wait statement sensitivity set derived fr= om the condition clause will cause P2 to resume and evaluate it's conditio= n. > >=20 > > When the condition is satisfied p2 will execute the next sequential sta= tement. It's in an endless loop that will wrap around. > >=20 > > Wait statements are sequential statements, only one of them at a time c= an cause a parent process to suspend. To have a different wait statement ca= use the parent process to suspend it has to be reached. That can't happen h= ere. >=20 > I understand that. I don't understand other thing. > Let's suppose initially actual B=3D0. As long as P2 is a concurrent proce= ss it will be called at 0 ps. >=20 > STD 2.1.1.1 > For a nonforeign subprogram having a parameter of a scalar type or an > access type, the parameter is passed by copy. At the start of each ca= ll, > if the mode is in or inout, the value of the actual parameter is copi= ed > into the associated formal parameter; >=20 > At that moment value of the actual B=3D0 is copied to the formal B of the= p2. After wait statement we resume p2 and execute "C <=3D A xor B" with fo= rmal B =3D 0. Let's suppose that at that moment the actual B outside of the= p2 is changed to '1'. As I understand, after next "wait until rising_edge(= clk);" statement in p2 when the actual B=3D'1', formal B should still be '0= ' because it's the value copied from actual to formal during call of the p2= . >=20 > In fact, the simulator behaves like it copies the actual B to the formal = B each time it resumes p2 after wait statement. IEEE Std 1076-2008 4.2 Subprogram declarations (2.1 -1993) 4.2.2 Formal parameters (2.1.1 -1993) 4.2.2.2 Constant and variable parameters (2.1.1.1 -1993) For parameters of class constant or variable, only the values of the actual= or formal are transferred into or out of the subprogram call. The manner o= f such transfers, and the accompanying access privileges that are granted f= or constant and variable parameters, are described in this subclause. ... __ 4.2.2.3 Signal parameters (2.1.1.2 -1993) For a formal parameter of class signal, references to the signal, the drive= r of the signal, or both, are passed into the subprogram call. For a signal parameter of mode in or inout, the actual signal is associated= with the corresponding formal signal parameter at the start of each call. = Thereafter, during the execution of the subprogram body, a reference to the= formal signal parameter within an expression is equivalent to a reference = to the actual signal. ... __ Unlike constants or variables where the value of the actual is passed, a si= gnal reference (name) points to the effective value of a signal. > > >=20 > > > Then I don't understand why the process > > >=20 > > > procedure p2( > > > signal clk : in std_logic; > > > signal A : in std_logic; > > > B : in std_logic; > > > signal C : out std_logic > > > ) is > > > . . . > > > responds to changes of the constant B each cycle if the procedure was= called > > > only once. I'll again point out p2 is only called once, and as you note if B is class = constant it won't change. You could note that the value of '1' for B in your original question is a s= tatic value and not a reference. Passing it requires passing a value, in th= is case class constant. If you want the value of B to change the actual needs to be a signal and th= e formal B needs to be class signal, with the actual passed as a reference = (name). If on the other hand if B is class constant and you're seeing the value of = C change, it's in response to a change of value of signal A. Because B was= originally defined as a static value of '1' at the beginning of this threa= d, C is effectively the inversion of A after the rising edge of clk. If you think you're getting behavior inconsistent with the standard you cou= ld provide a minimal, complete and verifiable example as well as specify wh= o's VHDL tool implementation you're using and it's version. Providing a minimal, complete and verifiable example with a testbench would= give the opportunity to point to specific simulation times and signal valu= e changes. From newsfish@newsfish Thu Aug 1 00:37:52 2024 X-Received: by 10.200.48.98 with SMTP id g31mr14798263qte.13.1473124053018; Mon, 05 Sep 2016 18:07:33 -0700 (PDT) X-Received: by 10.36.115.203 with SMTP id y194mr474828itb.0.1473124052981; Mon, 05 Sep 2016 18:07:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m9no878584qte.0!news-out.google.com!w143ni5110itb.0!nntp.google.com!i184no1476933itf.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Sep 2016 18:07:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.53.155.226; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.53.155.226 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8250989d-a0cf-41d4-b9e6-2ff97f5d5dd8@googlegroups.com> Subject: Re: Splitting 16 bit vector into 2 bytes From: stchebel@gmail.com Injection-Date: Tue, 06 Sep 2016 01:07:32 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3315 X-Received-Body-CRC: 3332811206 Xref: news.eternal-september.org comp.lang.vhdl:4589 W dniu poniedzia=C5=82ek, 22 sierpnia 2016 15:18:05 UTC+2 u=C5=BCytkownik D= avid Perry napisa=C5=82: > I have a 16 bit vector which I want to split into 2 8 bit vectors, I thou= ght I would be able to do this: > (Tx_Byte_4, Tx_Byte_3) <=3D INV_Volts; --this no worky > I want to split the 16 bit voltage value into 2 bytes to be transmitted l= ater. >=20 > Obviously I could avoid the problem by assigning (15:8) to byte 4 and (7:= 0) to byte 3 (I was doing this originally), but I am trying to avoid doing = that, it's not quite as neat :) >=20 And Congratulations!! VHDL is a hardware description Language, and you sho= uld precisely assign wires to wires. VHDL is a strong typed HW description = language enhirited from ADA. In fact, the declarations of signals and its t= ypes are very sensitive. Well, probably you have some bad behaviors taken f= rom C language.=20 I strongly prefare STRONGLY TYPED HDL languages. And also programming langu= ages. Your problem is 100+% a reason of looking on HDL from a point of view= of a C educated/bemused. The problem you described, occurs very often in a= very similar situations in software developement (C "youngsters").=20 C is an invitation to dissaster. Unfortunately, worldwide marketing made is= a "standard". Pascal as a predecessor of C is a strong typed language. It'= s syntax is in fact quite similar to C, however it's more rigorous. What a = f... for was C designed?! Well, not because programmers needed it, but just= only because it was possible. Moreover, good marketing (C is high level la= nguage fast as assembler). Bul...t !! Final code is as good as the compiler= is.=20 Returning back to the main topic, define precisely your input and output ve= ctors. For example: a: in std_logic_vector(N downto 0); b: out std_logic_vector(I downto 0); c: out std_logic_vector(J downto 0); Further assigment like: b((I downto 0)) <=3D a( SameNumberOfBits); The above is not 100% correct, but I hope you know what I mean. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D If any more questions, just ask. I'll try to explain as much as I can. Stachu From newsfish@newsfish Thu Aug 1 00:37:52 2024 X-Received: by 10.157.63.161 with SMTP id r30mr8627659otc.24.1473152848976; Tue, 06 Sep 2016 02:07:28 -0700 (PDT) X-Received: by 10.36.238.143 with SMTP id b137mr493642iti.7.1473152848862; Tue, 06 Sep 2016 02:07:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p55no884012qtp.1!news-out.google.com!h51ni589qth.0!nntp.google.com!m9no996484qte.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 Sep 2016 02:07:28 -0700 (PDT) In-Reply-To: <1165839399.052587.15440@n67g2000cwd.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=202.131.115.146; posting-account=BFsHFgoAAABKJZeUnukY5purjmPDHQ2A NNTP-Posting-Host: 202.131.115.146 References: <1165839399.052587.15440@n67g2000cwd.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <05b0b710-73e7-41a9-bbe9-967263b31eda@googlegroups.com> Subject: Re: ModelSim SE 6.1f : code coverage database merge problem From: hitesh.zanzmera@sibridgetech.com Injection-Date: Tue, 06 Sep 2016 09:07:28 +0000 Content-Type: text/plain; charset=UTF-8 X-Received-Bytes: 2161 X-Received-Body-CRC: 2951348902 Xref: news.eternal-september.org comp.lang.vhdl:4590 On Monday, December 11, 2006 at 5:46:39 PM UTC+5:30, Nicolas Matringe wrote: > Hello > I am using ModelSim to measure code coverage and have problem when > merging individual simulation results into a single database using the > vcover merge command. I use it as shown in the manual (*): > vcover merge coverage_results ucdb/*.ucdb > where ucdb files are individual results and coverage_results is the > output file. I invariably get the message "File '*.ucdb' is > unreadable". why can't I use a wildcard ? > > Nicolas > > (*) these two lines are copied from the command reference : > vcover merge myresult2 /dut/*.cov > Uses wildcards to merge all files with a .cov extension in a particular > directory. Hi, I have a same problem while merging individual .ucdb into single .ucdb file. I am using below command to merge individual *.ucdb files vcover merge -out final.ucdb write.ucdb read.ucdb Error stating : Segmentation fault. Can anyone have idea!! Looking forward to your quick reply! From newsfish@newsfish Thu Aug 1 00:37:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news.roellig-ltd.de!news.babsi.de!open-news-network.org!news2.open-news-network.org!.POSTED!not-for-mail From: Mike Perkins Newsgroups: comp.lang.vhdl Subject: Re: Splitting 16 bit vector into 2 bytes Date: Tue, 6 Sep 2016 20:57:52 +0100 Organization: news.babsi.de for www.open-news-network.org Lines: 61 Message-ID: References: <8250989d-a0cf-41d4-b9e6-2ff97f5d5dd8@googlegroups.com> NNTP-Posting-Host: host109-150-158-119.range109-150.btcentralplus.com Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Trace: news2.open-news-network.org 1473191872 29001 109.150.158.119 (6 Sep 2016 19:57:52 GMT) X-Complaints-To: abuse@open-news-network.org NNTP-Posting-Date: Tue, 6 Sep 2016 19:57:52 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <8250989d-a0cf-41d4-b9e6-2ff97f5d5dd8@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:4591 On 06/09/2016 02:07, stchebel@gmail.com wrote: > W dniu poniedziałek, 22 sierpnia 2016 15:18:05 UTC+2 użytkownik David > Perry napisał: >> I have a 16 bit vector which I want to split into 2 8 bit vectors, >> I thought I would be able to do this: (Tx_Byte_4, Tx_Byte_3) <= >> INV_Volts; --this no worky I want to split the 16 bit voltage value >> into 2 bytes to be transmitted later. >> >> Obviously I could avoid the problem by assigning (15:8) to byte 4 >> and (7:0) to byte 3 (I was doing this originally), but I am trying >> to avoid doing that, it's not quite as neat :) >> > > And Congratulations!! VHDL is a hardware description Language, and > you should precisely assign wires to wires. VHDL is a strong typed HW > description language enhirited from ADA. In fact, the declarations of > signals and its types are very sensitive. Well, probably you have > some bad behaviors taken from C language. I strongly prefare STRONGLY > TYPED HDL languages. And also programming languages. Your problem is > 100+% a reason of looking on HDL from a point of view of a C > educated/bemused. The problem you described, occurs very often in a > very similar situations in software developement (C "youngsters"). > > C is an invitation to dissaster. Unfortunately, worldwide marketing > made is a "standard". Pascal as a predecessor of C is a strong typed > language. It's syntax is in fact quite similar to C, however it's > more rigorous. What a f... for was C designed?! Well, not because > programmers needed it, but just only because it was possible. You need to have a look at the history of C. While it not as strongly typed as some, it is better than assembler. The whole intention was initially to move away from assembler. > Moreover, good marketing (C is high level language fast as > assembler). Bul...t !! Final code is as good as the compiler is. I think C sold itself. Despite lots of marketing it hasn't changed much. > Returning back to the main topic, define precisely your input and > output vectors. > > For example: > > a: in std_logic_vector(N downto 0); > b: out std_logic_vector(I downto 0); > c: out std_logic_vector(J downto 0); > > Further assigment like: > > b((I downto 0)) <= a( SameNumberOfBits); > > The above is not 100% correct, but I hope you know what I mean. Assuming N GE I -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk From newsfish@newsfish Thu Aug 1 00:37:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news.roellig-ltd.de!news.babsi.de!open-news-network.org!news2.open-news-network.org!.POSTED!not-for-mail From: Mike Perkins Newsgroups: comp.lang.vhdl Subject: Re: ModelSim SE 6.1f : code coverage database merge problem Date: Tue, 6 Sep 2016 21:00:34 +0100 Organization: news.babsi.de for www.open-news-network.org Lines: 39 Message-ID: References: <1165839399.052587.15440@n67g2000cwd.googlegroups.com> <05b0b710-73e7-41a9-bbe9-967263b31eda@googlegroups.com> NNTP-Posting-Host: host109-150-158-119.range109-150.btcentralplus.com Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news2.open-news-network.org 1473192033 29001 109.150.158.119 (6 Sep 2016 20:00:33 GMT) X-Complaints-To: abuse@open-news-network.org NNTP-Posting-Date: Tue, 6 Sep 2016 20:00:33 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <05b0b710-73e7-41a9-bbe9-967263b31eda@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:4592 On 06/09/2016 10:07, hitesh.zanzmera@sibridgetech.com wrote: > On Monday, December 11, 2006 at 5:46:39 PM UTC+5:30, Nicolas Matringe wrote: >> Hello >> I am using ModelSim to measure code coverage and have problem when >> merging individual simulation results into a single database using the >> vcover merge command. I use it as shown in the manual (*): >> vcover merge coverage_results ucdb/*.ucdb >> where ucdb files are individual results and coverage_results is the >> output file. I invariably get the message "File '*.ucdb' is >> unreadable". why can't I use a wildcard ? >> >> Nicolas >> >> (*) these two lines are copied from the command reference : >> vcover merge myresult2 /dut/*.cov >> Uses wildcards to merge all files with a .cov extension in a particular >> directory. > > Hi, > > I have a same problem while merging individual .ucdb into single .ucdb file. > > I am using below command to merge individual *.ucdb files > vcover merge -out final.ucdb write.ucdb read.ucdb > > Error stating : Segmentation fault. > > Can anyone have idea!! > > Looking forward to your quick reply! Quick reply? You are kidding when it took you 10 years to reply? When a post is more than a few weeks old I recommend starting anew. -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk From newsfish@newsfish Thu Aug 1 00:37:53 2024 X-Received: by 10.67.7.4 with SMTP id cy4mr15147382pad.30.1473671037935; Mon, 12 Sep 2016 02:03:57 -0700 (PDT) X-Received: by 10.36.6.18 with SMTP id 18mr225375itv.8.1473671037855; Mon, 12 Sep 2016 02:03:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!x192no602443itb.0!news-out.google.com!w143ni1549itb.0!nntp.google.com!x192no602442itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Sep 2016 02:03:55 -0700 (PDT) In-Reply-To: <8250989d-a0cf-41d4-b9e6-2ff97f5d5dd8@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: <8250989d-a0cf-41d4-b9e6-2ff97f5d5dd8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Splitting 16 bit vector into 2 bytes From: David Perry Injection-Date: Mon, 12 Sep 2016 09:03:57 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 5 Xref: news.eternal-september.org comp.lang.vhdl:4593 On Tuesday, 6 September 2016 02:07:35 UTC+1, stch...@gmail.com wrote: >Your problem is 100+% a reason of looking on HDL from a point of view of a C educated/bemused. The problem you described, occurs very often in a very similar situations in software developement (C "youngsters"). Actually, I'm moving from Schematic entry to VHDL. I will miss schematic entry, newer toolchains seem to be dropping it though :( From newsfish@newsfish Thu Aug 1 00:37:53 2024 X-Received: by 10.157.34.41 with SMTP id o38mr3571665ota.34.1473885330995; Wed, 14 Sep 2016 13:35:30 -0700 (PDT) X-Received: by 10.36.105.3 with SMTP id e3mr516827itc.4.1473885330952; Wed, 14 Sep 2016 13:35:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!u18no300599ita.0!news-out.google.com!w143ni1255itb.0!nntp.google.com!x192no437338itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Sep 2016 13:35:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:e68:5422:2c45:2861:3a9b:3579:5143; posting-account=3o3GBgoAAADFbXPOzspALKh7MxNxnCbn NNTP-Posting-Host: 2001:e68:5422:2c45:2861:3a9b:3579:5143 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <52293205-a307-4c14-a774-9708b8618342@googlegroups.com> Subject: can anyone plz do help with this From: Marwan Naji Injection-Date: Wed, 14 Sep 2016 20:35:30 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4594 VHDL Group Project Work in a group of three members design a dual-function digital timer using VHDL. The digital timer can function as a stopwatch or a count-down timer. In the stopwatch mode, it is capable of recording the time up to hundredths of a second accuracy. In the count-down mode, it is capable of counting down from a maximum of 24 hours. It has three buttons (B1, B2 and B3) that are used to change the mode, set the time, start and stop the stopwatch or the timer functions, and etc. Pushing button B1 changes the mode from Stopwatch to Countdown Timer and back to Stopwatch. The function of the buttons B2 and B3 vary depending on the mode and are explained in the following: Operation in Stopwatch mode: Display indicates stopwatch time in the format of mm:ss.cc (where cc is hundredths of a second). Pressing B2 starts the time counter, pressing B2 again stops it, and then pressing B2 again will resume the time counter and so on. Pressing B3 resets the time. Once the stopwatch is started, it will keep running even when it is in the Countdown Timer mode. Operation in Countdown Timer mode: Display indicates the time in the format of hh:mm. Pushing B2 cycles the state to Set Hours, then to Set Minutes, to start the timer, and to stop the timer. When in the Set Hours or Set Minutes state, each press of B3 advances the hours and minutes by 1. Similarly, once the countdown timer is started, it will keep running even when it is in the Stopwatch mode. In short, the dual function timer can run both operations in parallel. Assume that the system clock is at 50 MHz. You should try to include any of the concepts in designfor-test and low power design techniques to improve the testability of the design, and better manage the power consumption of your design, respectively From newsfish@newsfish Thu Aug 1 00:37:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: can anyone plz do help with this Date: Wed, 14 Sep 2016 17:04:56 -0400 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <52293205-a307-4c14-a774-9708b8618342@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 14 Sep 2016 21:04:54 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="10204"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+8QYUzkhOmbSYPmskijVEK" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 In-Reply-To: <52293205-a307-4c14-a774-9708b8618342@googlegroups.com> Cancel-Lock: sha1:sTVtwB8ItvDtdvRpJMwZOXXidRM= Xref: news.eternal-september.org comp.lang.vhdl:4595 On 9/14/2016 4:35 PM, Marwan Naji wrote: > VHDL Group Project > Work in a group of three members design a dual-function digital timer using VHDL. The digital timer > can function as a stopwatch or a count-down timer. In the stopwatch mode, it is capable of recording > the time up to hundredths of a second accuracy. In the count-down mode, it is capable of counting down > from a maximum of 24 hours. It has three buttons (B1, B2 and B3) that are used to change the mode, > set the time, start and stop the stopwatch or the timer functions, and etc. > Pushing button B1 changes the mode from Stopwatch to Countdown Timer and back to Stopwatch. > The function of the buttons B2 and B3 vary depending on the mode and are explained in the following: > Operation in Stopwatch mode: > Display indicates stopwatch time in the format of mm:ss.cc (where cc is hundredths of a second). > Pressing B2 starts the time counter, pressing B2 again stops it, and then pressing B2 again will resume > the time counter and so on. Pressing B3 resets the time. Once the stopwatch is started, it will keep > running even when it is in the Countdown Timer mode. > Operation in Countdown Timer mode: > Display indicates the time in the format of hh:mm. Pushing B2 cycles the state to Set Hours, then to Set > Minutes, to start the timer, and to stop the timer. When in the Set Hours or Set Minutes state, each press > of B3 advances the hours and minutes by 1. Similarly, once the countdown timer is started, it will keep > running even when it is in the Stopwatch mode. In short, the dual function timer can run both operations > in parallel. > Assume that the system clock is at 50 MHz. You should try to include any of the concepts in designfor-test > and low power design techniques to improve the testability of the design, and better manage > the power consumption of your design, respectively This looks like a pretty complete set of requirements. What do you need help with? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: can anyone plz do help with this Date: Wed, 14 Sep 2016 21:06:59 -0000 (UTC) Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <52293205-a307-4c14-a774-9708b8618342@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Wed, 14 Sep 2016 21:06:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="809df500543e3a7eaa0b56650623de8b"; logging-data="11380"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+lRfydAirEu94JwU0mFosd" User-Agent: XPN/1.2.6 (Street Spirit ; Linux) Cancel-Lock: sha1:zbd+dUd/K3A1E/HUNg0pRSTaSVs= Xref: news.eternal-september.org comp.lang.vhdl:4596 Marwan Naji wrote: > VHDL Group Project > Work in a group of three members design a dual-function digital timer using VHDL. The digital timer > can function as a stopwatch or a count-down timer. In the stopwatch mode, it is capable of recording > the time up to hundredths of a second accuracy. In the count-down mode, it is capable of counting down > from a maximum of 24 hours. It has three buttons (B1, B2 and B3) that are used to change the mode, > set the time, start and stop the stopwatch or the timer functions, and etc. > Pushing button B1 changes the mode from Stopwatch to Countdown Timer and back to Stopwatch. > The function of the buttons B2 and B3 vary depending on the mode and are explained in the following: > Operation in Stopwatch mode: > Display indicates stopwatch time in the format of mm:ss.cc (where cc is hundredths of a second). > Pressing B2 starts the time counter, pressing B2 again stops it, and then pressing B2 again will resume > the time counter and so on. Pressing B3 resets the time. Once the stopwatch is started, it will keep > running even when it is in the Countdown Timer mode. > Operation in Countdown Timer mode: > Display indicates the time in the format of hh:mm. Pushing B2 cycles the state to Set Hours, then to Set > Minutes, to start the timer, and to stop the timer. When in the Set Hours or Set Minutes state, each press > of B3 advances the hours and minutes by 1. Similarly, once the countdown timer is started, it will keep > running even when it is in the Stopwatch mode. In short, the dual function timer can run both operations > in parallel. > Assume that the system clock is at 50 MHz. You should try to include any of the concepts in designfor-test > and low power design techniques to improve the testability of the design, and better manage > the power consumption of your design, respectively I suggest you start by asking the other two members of your team. Should none of you have any ideas on where to do go on this project, you should then, collectively, ask your professor. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:37:54 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: can anyone plz do help with this Date: Thu, 15 Sep 2016 14:26:40 -0400 Organization: Alacron, Inc. Lines: 43 Message-ID: References: <52293205-a307-4c14-a774-9708b8618342@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 15 Sep 2016 18:27:16 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="395ab2ded3179cbf1e99f893b14f59e2"; logging-data="2342"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX198doAFwoqr7+ehlhpxOVT4afx7KkvoKTU=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.24) Gecko/20100228 Thunderbird/2.0.0.24 Mnenhy/0.7.6.666 In-Reply-To: <52293205-a307-4c14-a774-9708b8618342@googlegroups.com> Cancel-Lock: sha1:BihqykD/2/MKDEyjxbjT78yxY7E= Xref: news.eternal-september.org comp.lang.vhdl:4597 Marwan Naji wrote: > VHDL Group Project > Work in a group of three members design a dual-function digital timer using VHDL. The digital timer > can function as a stopwatch or a count-down timer. In the stopwatch mode, it is capable of recording > the time up to hundredths of a second accuracy. In the count-down mode, it is capable of counting down > from a maximum of 24 hours. It has three buttons (B1, B2 and B3) that are used to change the mode, > set the time, start and stop the stopwatch or the timer functions, and etc. > Pushing button B1 changes the mode from Stopwatch to Countdown Timer and back to Stopwatch. > The function of the buttons B2 and B3 vary depending on the mode and are explained in the following: > Operation in Stopwatch mode: > Display indicates stopwatch time in the format of mm:ss.cc (where cc is hundredths of a second). > Pressing B2 starts the time counter, pressing B2 again stops it, and then pressing B2 again will resume > the time counter and so on. Pressing B3 resets the time. Once the stopwatch is started, it will keep > running even when it is in the Countdown Timer mode. > Operation in Countdown Timer mode: > Display indicates the time in the format of hh:mm. Pushing B2 cycles the state to Set Hours, then to Set > Minutes, to start the timer, and to stop the timer. When in the Set Hours or Set Minutes state, each press > of B3 advances the hours and minutes by 1. Similarly, once the countdown timer is started, it will keep > running even when it is in the Stopwatch mode. In short, the dual function timer can run both operations > in parallel. > Assume that the system clock is at 50 MHz. You should try to include any of the concepts in designfor-test > and low power design techniques to improve the testability of the design, and better manage > the power consumption of your design, respectively My suggestion is to break the project into three parts, and assign one team member to design each part. This will help you learn how to work in a design team as well as how to design logic. One possible way to partition the design is: 1) Down counter 2) Stop watch 3) Button debounce and display (top level) Then you need to agree on the interface to use between these design partitions so that each team member can design and test their part against the interface requirements, and if all goes well the parts will match up and work. -- Gabor From newsfish@newsfish Thu Aug 1 00:37:55 2024 X-Received: by 10.66.188.137 with SMTP id ga9mr11511671pac.23.1474080559224; Fri, 16 Sep 2016 19:49:19 -0700 (PDT) X-Received: by 10.36.50.145 with SMTP id j139mr11851ita.9.1474080559124; Fri, 16 Sep 2016 19:49:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!x192no1342265itb.0!news-out.google.com!b4ni3173iti.0!nntp.google.com!x192no1342258itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Sep 2016 19:49:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.72.195.4; posting-account=qlqsaQoAAABvqhVd5Nk34rK_cELYWili NNTP-Posting-Host: 119.72.195.4 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Fixed point ieee_2008 compilation errors in xilinx vivado 2014.3 From: ghadakdr@gmail.com Injection-Date: Sat, 17 Sep 2016 02:49:19 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4598 Hello,=20 I added the fixed_float_types.vhd, fixed_generic_pkg.vhd, fixed_generic_pkg= -body.vhd, fixed_pkg.vhd to my project, I set the library for them to ieee. I wrote the following code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.fixed_float_types.all; use IEEE.fixed_pkg.all; entity test_mul is -- Port ( ); end test_mul; architecture Behavioral of test_mul is signal a,b :sfixed(7 downto -6); signal c:sfixed(8 downto -6); begin c<=3Da +b; end Behavioral; I got the following warnings and errors : Analysis Results sources_1 [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/imports/new/fixed_float_types.vhdl" = into library IEEE ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_= t/project_t.srcs/sources_1/imports/new/fixed_float_types.vhdl":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-body.v= hdl" into library IEEE ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/pro= ject_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-body.vhdl":1] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1020] [HDL 9-806] Syntax error near "if". ["D:/GhadaKdr/Xilinx_Projects/Tutorials= /Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-= body.vhdl":1022] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1031] [HDL 9-806] Syntax error near "if". ["D:/GhadaKdr/Xilinx_Projects/Tutorials= /Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-= body.vhdl":1033] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1042] [HDL 9-806] Syntax error near "if". ["D:/GhadaKdr/Xilinx_Projects/Tutorials= /Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-= body.vhdl":1044] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1053] [HDL 9-806] Syntax error near "if". ["D:/GhadaKdr/Xilinx_Projects/Tutorials= /Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-= body.vhdl":1055] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1794] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1815] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1836] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1857] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1878] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1899] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1920] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1941] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1962] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1983] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":2004] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":2025] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4147] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4155] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4163] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4171] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4179] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4187] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4260] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4268] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4276] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4284] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4292] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4300] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4373] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4381] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4389] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4397] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4405] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4413] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4486] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4494] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4502] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4510] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4518] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4526] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4599] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4607] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4615] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4623] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4631] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4639] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4712] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4720] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4728] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4736] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4744] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4752] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4825] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4833] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4841] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4849] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4857] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4865] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4938] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4946] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4954] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4962] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4970] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4978] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg.vhdl" = into library IEEE ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_= t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg.vhdl":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/imports/new/fixed_pkg.vhdl" into lib= rary IEEE ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_t/projec= t_t.srcs/sources_1/imports/new/fixed_pkg.vhdl":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/new/load_inp.vhd" into library xil_d= efaultlib ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_t/projec= t_t.srcs/sources_1/new/load_inp.vhd":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/new/test_mul.vhd" into library xil_d= efaultlib ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_t/projec= t_t.srcs/sources_1/new/test_mul.vhd":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/new/work_pkg.vhd" into library work = ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_t/project_t.srcs/s= ources_1/new/work_pkg.vhd":1] sim_1 [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/imports/new/fixed_float_types.vhdl" = into library IEEE ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_= t/project_t.srcs/sources_1/imports/new/fixed_float_types.vhdl":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-body.v= hdl" into library IEEE ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/pro= ject_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-body.vhdl":1] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1020] [HDL 9-806] Syntax error near "if". ["D:/GhadaKdr/Xilinx_Projects/Tutorials= /Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-= body.vhdl":1022] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1031] [HDL 9-806] Syntax error near "if". ["D:/GhadaKdr/Xilinx_Projects/Tutorials= /Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-= body.vhdl":1033] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1042] [HDL 9-806] Syntax error near "if". ["D:/GhadaKdr/Xilinx_Projects/Tutorials= /Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-= body.vhdl":1044] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1053] [HDL 9-806] Syntax error near "if". ["D:/GhadaKdr/Xilinx_Projects/Tutorials= /Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-= body.vhdl":1055] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1794] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1815] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1836] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1857] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1878] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1899] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1920] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1941] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1962] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1983] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":2004] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":2025] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4147] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4155] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4163] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4171] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4179] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4187] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4260] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4268] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4276] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4284] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4292] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4300] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4373] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4381] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4389] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4397] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4405] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4413] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4486] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4494] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4502] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4510] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4518] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4526] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4599] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4607] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4615] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4623] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4631] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4639] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4712] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4720] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4728] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4736] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4744] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4752] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4825] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4833] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4841] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4849] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4857] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4865] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4938] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4946] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4954] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4962] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4970] [HDL 9-806] Syntax error near "?". ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4978] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg.vhdl" = into library IEEE ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_= t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg.vhdl":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/imports/new/fixed_pkg.vhdl" into lib= rary IEEE ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_t/projec= t_t.srcs/sources_1/imports/new/fixed_pkg.vhdl":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/new/load_inp.vhd" into library xil_d= efaultlib ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_t/projec= t_t.srcs/sources_1/new/load_inp.vhd":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/new/test_mul.vhd" into library xil_d= efaultlib ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_t/projec= t_t.srcs/sources_1/new/test_mul.vhd":1] [HDL 9-1061] Parsing VHDL file "D:/GhadaKdr/Xilinx_Projects/Tutorials/Embed= ded/project_t/project_t.srcs/sources_1/new/work_pkg.vhd" into library work = ["D:/GhadaKdr/Xilinx_Projects/Tutorials/Embedded/project_t/project_t.srcs/s= ources_1/new/work_pkg.vhd":1] Synthesis [Vivado_Tcl 4-279] hardware handoff file cannot be generated as there is no= block diagram instance in the design [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z045' [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1020] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1031] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1042] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1053] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1794] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1815] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1836] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1857] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1878] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1899] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1920] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1941] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1962] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":1983] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":2004] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":2025] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4147] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4155] [Synth 8-2715] syntax error near ? ["D:/GhadaKdr/Xilinx_Projects/Tutorials/= Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_pkg-b= ody.vhdl":4163] [Synth 8-2757] this construct is only supported in VHDL 1076-2008 ["D:/Ghad= aKdr/Xilinx_Projects/Tutorials/Embedded/project_t/project_t.srcs/sources_1/= imports/new/fixed_generic_pkg.vhdl":73] [Synth 8-2757] this construct is only supported in VHDL 1076-2008 ["D:/Ghad= aKdr/Xilinx_Projects/Tutorials/Embedded/project_t/project_t.srcs/sources_1/= imports/new/fixed_generic_pkg.vhdl":74] [Synth 8-1031] unresolved_signed is not declared ["D:/GhadaKdr/Xilinx_Proje= cts/Tutorials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed= _generic_pkg.vhdl":377] [Synth 8-1031] unresolved_signed is not declared ["D:/GhadaKdr/Xilinx_Proje= cts/Tutorials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed= _generic_pkg.vhdl":379] [Synth 8-970] "and" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tutor= ials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_= pkg.vhdl":687] [Synth 8-970] "nand" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tuto= rials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic= _pkg.vhdl":688] [Synth 8-970] "or" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tutori= als/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_p= kg.vhdl":689] [Synth 8-970] "nor" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tutor= ials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_= pkg.vhdl":690] [Synth 8-970] "xor" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tutor= ials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_= pkg.vhdl":691] [Synth 8-970] "xnor" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tuto= rials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic= _pkg.vhdl":692] [Synth 8-970] "and" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tutor= ials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_= pkg.vhdl":693] [Synth 8-970] "nand" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tuto= rials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic= _pkg.vhdl":694] [Synth 8-970] "or" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tutori= als/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_p= kg.vhdl":695] [Synth 8-970] "nor" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tutor= ials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_= pkg.vhdl":696] [Synth 8-970] "xor" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tutor= ials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic_= pkg.vhdl":697] [Synth 8-970] "xnor" expects 2 arguments ["D:/GhadaKdr/Xilinx_Projects/Tuto= rials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fixed_generic= _pkg.vhdl":698] [Synth 8-1031] unresolved_unsigned is not declared ["D:/GhadaKdr/Xilinx_Pro= jects/Tutorials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fix= ed_generic_pkg.vhdl":802] [Synth 8-1031] unresolved_unsigned is not declared ["D:/GhadaKdr/Xilinx_Pro= jects/Tutorials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fix= ed_generic_pkg.vhdl":810] [Synth 8-1031] unresolved_unsigned is not declared ["D:/GhadaKdr/Xilinx_Pro= jects/Tutorials/Embedded/project_t/project_t.srcs/sources_1/imports/new/fix= ed_generic_pkg.vhdl":818] can someone help From newsfish@newsfish Thu Aug 1 00:37:55 2024 X-Received: by 10.66.85.37 with SMTP id e5mr7655451paz.118.1475026395774; Tue, 27 Sep 2016 18:33:15 -0700 (PDT) X-Received: by 10.36.115.203 with SMTP id y194mr410367itb.0.1475026395725; Tue, 27 Sep 2016 18:33:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no59003itl.0!news-out.google.com!w143ni194itb.0!nntp.google.com!x192no61459itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Sep 2016 18:33:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=137.132.228.35; posting-account=lYq8NwoAAAAPgtz7rx5LxTjTo3IG6-El NNTP-Posting-Host: 137.132.228.35 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1ae03121-3ca4-4884-9de1-93ecdad433e0@googlegroups.com> Subject: Sharing a single general lookup table From: user123random@gmail.com Injection-Date: Wed, 28 Sep 2016 01:33:15 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4599 I am implementing the gamma correction LUT as in https://ptpb.pw/ZwYS if I want to share a single combinatorial lookup table with multiple input, it is not possible, right ? because in this case, the lookup table would just assign to one output reg say all r, g and b channels want to use the same combinatorial lookup table, how would I do it ? Someone suggested the following, could anyone advice ? mux -> lut -> demux But my friend told me the following instead: A 256-sized table can be done in one slice, containing 4-luts--for every output bit. It will consume all 4 luts of the slice. So ... we're talking about 8 slices, or 32-luts, per color. 96 LUTs is reasonable. Now, if you wished to somehow re-use those 96 LUTs to get your logic down to a smaller size, be prepared for the fact that it will cost logic to make any logic change--perhaps as much as the 96 LUTs that you would originally need. From newsfish@newsfish Thu Aug 1 00:37:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Sharing a single general lookup table Date: Wed, 28 Sep 2016 01:59:05 -0400 Organization: A noiseless patient Spider Lines: 53 Message-ID: References: <1ae03121-3ca4-4884-9de1-93ecdad433e0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 Sep 2016 05:58:52 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="14414"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+TxpzXuvnVHiL6qt4Nn1oT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: <1ae03121-3ca4-4884-9de1-93ecdad433e0@googlegroups.com> Cancel-Lock: sha1:v5zaijLNxEZ7f3i/7p52Xy4P/L8= Xref: news.eternal-september.org comp.lang.vhdl:4600 On 9/27/2016 9:33 PM, user123random@gmail.com wrote: > I am implementing the gamma correction LUT as in > https://ptpb.pw/ZwYS > > if I want to share a single combinatorial lookup table with multiple > input, it is not possible, right ? > > because in this case, the lookup table would just assign to one > output reg > > say all r, g and b channels want to use the same combinatorial lookup > table, how would I do it ? > > Someone suggested the following, could anyone advice ? mux -> lut -> > demux There is no need for a demux on the output. Typically the output would go to all three circuits and only one would use it at any given time. Worst case you would add registers at the three inputs to the following circuits and only enable one at a time. > But my friend told me the following instead: A 256-sized table can be > done in one slice, containing 4-luts--for every output bit. It will > consume all 4 luts of the slice. > > So ... we're talking about 8 slices, or 32-luts, per color. > > 96 LUTs is reasonable. Now, if you wished to somehow re-use those 96 > LUTs to get your logic down to a smaller size, be prepared for the > fact that it will cost logic to make any logic change--perhaps as > much as the 96 LUTs that you would originally need. There are also block RAMs on most FPGAs which will hold your entire table in one RAM or you can use three separate RAMs and skip the multiplexers. Often they are dual port so you can look up two values at once in the same RAM. I'm not very familiar with gamma correction, but I thought this was based on luminance. That is, the luminance gives you a gamma value that then must be multiplied by each RGB component to get the output values. If you do this in a lookup table, you would need to either combine the luminance with the individual RGB signals which would give you at least 16 address inputs, not 8. Or you could generate the luminance signal from the RGB values and use a lookup table to get the multiplier which then is multiplied by each of the RGB color signals to get the result. FPGAs often have hardware multipliers as well. Or do I not understand what you are doing? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:56 2024 X-Received: by 10.13.210.129 with SMTP id u123mr9135282ywd.148.1475100544071; Wed, 28 Sep 2016 15:09:04 -0700 (PDT) X-Received: by 10.36.115.203 with SMTP id y194mr914440itb.0.1475100543993; Wed, 28 Sep 2016 15:09:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w41no494187qtw.1!news-out.google.com!w143ni766itb.0!nntp.google.com!l13no208115itl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Sep 2016 15:09:03 -0700 (PDT) In-Reply-To: <1ae03121-3ca4-4884-9de1-93ecdad433e0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.198.82.127; posting-account=siWI1goAAADCu904SmsHiBYIWw1g2Ocr NNTP-Posting-Host: 117.198.82.127 References: <1ae03121-3ca4-4884-9de1-93ecdad433e0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <930422fa-f61f-4242-991f-c5eba8766126@googlegroups.com> Subject: Re: Sharing a single general lookup table From: iamalien Injection-Date: Wed, 28 Sep 2016 22:09:04 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4601 But do remember, if you use block ram then you will need a clock pulse for every read operation since its synchronous. From newsfish@newsfish Thu Aug 1 00:37:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: inter-dependent assignments in process Date: Fri, 30 Sep 2016 01:45:52 +0200 Organization: A noiseless patient Spider Lines: 83 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 29 Sep 2016 23:45:41 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ca667408d11d7535d85675045d4ca919"; logging-data="3378"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+3PPRA+fsvRJEkltgu3v3y" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 X-Mozilla-News-Host: snews://news.eternal-september.org:563 Cancel-Lock: sha1:7C9IGPAFvRvKRttkBlTHYaSiy7k= Xref: news.eternal-september.org comp.lang.vhdl:4602 Hi all, I have a question on a very simple piece of code: I have been looking in the different VHDL documentation I have here, but have not found it. This is part of a process: > if (s_sclk_edgeup = '1') then > -- on rising edge of spi-clock, read data, and determine > -- next bit position > > buffer(bitcounter) <= spi_mosi; > > -- determine new bitposition > if (bitcounter > 0) then > bitcounter <= bitcounter - 1; > else > bitcounter <= 7; > -- last bit -> go process received data > state <= PROCESS_DATA; > end if; > end if; My question is related to the fact there are two signals that are assignments, but these two signals are inter-dependent. Here there are two actions: - store data from the spi_mosi input-pin to the correct position of the buffer - move down the buffer-position pointer The order in which these two actions are executed does matter. If I understand this correctly, as this is part of a process, the general rule is that the assignment is actually done at the END of the process!!! So, I tested this and ... in this case, this works nice. ... But ... why? How does the VHDL compiler know what actions comes first? At first, I thought that this was related to the order in which the two actions are written in the process (commands inside a process do are processed in sequence, no?), but when I move the "move down buffer-position pointer" part to the start of this process, the code still works. (so this part was executed LAST, not first!) What exactly is going on here? Is this just a random behaviour or how quartus is processing this paricular example, or is this senario exactually described in the VHDL specification? (as said, I have been looking in the documentation I have, and not found any information about this). Now, I know there are other ways to code this that are more explicit about the order these two actions are executed: - make the statemachine more complex - use a temporary variable. What would be "best practice" to code this "the proper way"? Cheerio! Kristoff From newsfish@newsfish Thu Aug 1 00:37:56 2024 X-Received: by 10.159.32.99 with SMTP id 90mr1292217uam.24.1475200198871; Thu, 29 Sep 2016 18:49:58 -0700 (PDT) X-Received: by 10.36.29.144 with SMTP id 138mr125835itj.8.1475200198829; Thu, 29 Sep 2016 18:49:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w41no776726qtw.1!news-out.google.com!203ni2017itk.0!nntp.google.com!184no18345ity.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 Sep 2016 18:49:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:1a30:b4c7:ae53:3456:34c6; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:1a30:b4c7:ae53:3456:34c6 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Subject: Re: inter-dependent assignments in process From: KJ Injection-Date: Fri, 30 Sep 2016 01:49:58 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4603 On Thursday, September 29, 2016 at 7:45:54 PM UTC-4, kristoff wrote: >=20 > This is part of a process: >=20 > > if (s_sclk_edgeup =3D '1') then > > -- on rising edge of spi-clock, read data, and determine > > -- next bit position > > > > buffer(bitcounter) <=3D spi_mosi; > > > > -- determine new bitposition > > if (bitcounter > 0) then > > bitcounter <=3D bitcounter - 1; > > else > > bitcounter <=3D 7; > > -- last bit -> go process received data > > state <=3D PROCESS_DATA; > > end if; > > end if; >=20 >=20 >=20 >=20 > If I understand this correctly, as this is part of a process, the=20 > general rule is that the assignment is actually done at the END of the=20 > process!!! >=20 Almost. What happens inside the process is that the signals are 'scheduled= ' to be updated. At the end of the process, it suspends. Once *all* the p= rocesses that are active in the entire simulation have run and suspended, t= he simulator takes the list of all signals that have been scheduled to be u= pdated and actually updates them. Scheduling to be updated and updating ar= e two very different things. This behavior is different than for variables. For a variable assignment, = the variable is updated immediately, there is no scheduling. >=20 >=20 > So, I tested this and ... in this case, this works nice. ... But ... why? >=20 > How does the VHDL compiler know what actions comes first? >=20 The VHDL LRM defines this signal update scheduling. >=20 > At first, I thought that this was related to the order in which the two= =20 > actions are written in the process (commands inside a process do are=20 > processed in sequence, no?),=20 Correct. > but when I move the "move down=20 > buffer-position pointer" part to the start of this process, the code=20 > still works. (so this part was executed LAST, not first!) >=20 'Executed' might be the wrong word to use here. When the signal assignment= statement is 'executed' it is not updating the signal, it is just scheduli= ng it to be updated. If there had been multiple assignments to a particula= r signal, then yes the order would matter since the scheduling that occurs = for the last assignment would essentially override the scheduling that alre= ady occurred for the first assignment. In your process, there is only one = assignment statement that will be executed no matter how one goes through t= he process. > (as said, I have been looking in the documentation I have, and not found= =20 > any information about this). >=20 The LRM can be difficult to read. >=20 >=20 > Now, I know there are other ways to code this that are more explicit=20 > about the order these two actions are executed: > - make the statemachine more complex > - use a temporary variable. >=20 Not sure what you're trying to get at here. The order doesn't matter in yo= ur example. You proved it yourself by noting the behavior was the same eve= n when you shuffled the order. >=20 > What would be "best practice" to code this "the proper way"? >=20 There is nothing objectionable about the process you posted. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Fri, 30 Sep 2016 00:12:49 -0400 Organization: A noiseless patient Spider Lines: 176 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Sep 2016 04:12:38 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="cfa3b34c288179253928b4d47ccee148"; logging-data="30439"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18jh6LgdFJrMRQdWMtHpUOZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Cancel-Lock: sha1:VzP4DNXrvCtsaWMNj2NKh6MxXhE= Xref: news.eternal-september.org comp.lang.vhdl:4604 On 9/29/2016 9:49 PM, KJ wrote: > On Thursday, September 29, 2016 at 7:45:54 PM UTC-4, kristoff wrote: >> >> This is part of a process: >> >>> if (s_sclk_edgeup = '1') then -- on rising edge of spi-clock, >>> read data, and determine -- next bit position >>> >>> buffer(bitcounter) <= spi_mosi; >>> >>> -- determine new bitposition if (bitcounter > 0) then bitcounter >>> <= bitcounter - 1; else bitcounter <= 7; -- last bit -> go >>> process received data state <= PROCESS_DATA; end if; end if; >> >> >> >> >> If I understand this correctly, as this is part of a process, the >> general rule is that the assignment is actually done at the END of >> the process!!! >> > Almost. What happens inside the process is that the signals are > 'scheduled' to be updated. At the end of the process, it suspends. > Once *all* the processes that are active in the entire simulation > have run and suspended, the simulator takes the list of all signals > that have been scheduled to be updated and actually updates them. > Scheduling to be updated and updating are two very different things. Your code segment does not indicate if these items are signals or variables, but from your description of their behavior I expect they are signals. I would just add to what KJ said by saying the terminology for this delay of assignment is delta delay. Delta delays are like an infinitely small increment of time, but no actual time elapses. When a process executes and updates a signal, the update is scheduled for now + 1 delta delay. The same thing happens when a concurrent statement is executed, the assignment is scheduled for 1 delta delay later. So a process runs at time 100 ns and does a signal assignment scheduled for 100 ns + 1 delta delay. This signal is used in a concurrent assignment and that signal update is scheduled for 100 ns + 2 delta delays. All of these events look like they happen at 100 ns but the delta delays preserve the proper order of events to get the right result. In a process multiple assignments can be done to the same signal. The last one to be executed is the one that actually is assigned to the signal 1 delta delay later. You can create problems by running clocks through signal assignments. If process one is clocked by clk1, clk2 is assigned the value of clk1 and clk2 is used to clock process two, this will happen as if the two processes run at different times, but a simulation will show the changes at the same time. Example: clk2 <= clk1; process_one (clk1) begin if (rising_edge(clk1) then A <= input; end if; end process; process_two (clk1) begin if (rising_edge(clk2) then B <= A; end if; end process; Start with A = '0' and input = '1' when clk1 has a positive edge at time 100 ns. After the dust has settled, A will be '0' and B will be '0'. That is because A is assigned a '1' at time 100 ns + 1 delta delay. Clk2 is also scheduled for a rising edge at 100 ns + 1 delta delay, so process_two may be executed after A has been updated. If that happens B will be assigned a '1' rather than a '0' which was the state of A prior to the rising edge of clk1. I hope that makes sense. There are times you need to understand to prevent this sort of error. > This behavior is different than for variables. For a variable > assignment, the variable is updated immediately, there is no > scheduling. Yes, variables in VHDL work like variables in a typical sequential programming language like C. A statement is executed entirely before the next statement is executed. This is the opposite of how signals work. So if variable A is assigned a value and later in the process A is used, it will have the updated value. If A is a signal used anywhere in the process before waiting the old value will be used. Once the process suspends for any reason (exits at end or encounters a wait statement) it won't run again until at least one delta delay. I'm a little unclear on how events scheduled for the same delta delay are ordered for execution. Maybe someone else can explain that. I don't know if they are ordered by the order they were executed (the simulator actually can only run one process at a time, even if the processes are supposed to run on the same delta delay) or in some other sequence. >> So, I tested this and ... in this case, this works nice. ... But >> ... why? >> >> How does the VHDL compiler know what actions comes first? >> > The VHDL LRM defines this signal update scheduling. > >> >> At first, I thought that this was related to the order in which the >> two actions are written in the process (commands inside a process >> do are processed in sequence, no?), > > Correct. > >> but when I move the "move down buffer-position pointer" part to the >> start of this process, the code still works. (so this part was >> executed LAST, not first!) >> > 'Executed' might be the wrong word to use here. When the signal > assignment statement is 'executed' it is not updating the signal, it > is just scheduling it to be updated. If there had been multiple > assignments to a particular signal, then yes the order would matter > since the scheduling that occurs for the last assignment would > essentially override the scheduling that already occurred for the > first assignment. In your process, there is only one assignment > statement that will be executed no matter how one goes through the > process. > >> (as said, I have been looking in the documentation I have, and not >> found any information about this). >> > > The LRM can be difficult to read. +1 VERY! Part of the problem is how it is written, to be precise and unambiguous rather than easy to read. Partly it is because many times to understand one thing, you have to go back and learn about something else which means you have to learn another thing and so on. >> Now, I know there are other ways to code this that are more >> explicit about the order these two actions are executed: - make the >> statemachine more complex - use a temporary variable. >> > > Not sure what you're trying to get at here. The order doesn't matter > in your example. You proved it yourself by noting the behavior was > the same even when you shuffled the order. > >> >> What would be "best practice" to code this "the proper way"? >> > There is nothing objectionable about the process you posted. I prefer to order statements so it is clear and easy to read. The order you have written them makes sense whether they are executed in sequence as variables, or pending a delta delay, so unambiguous even if you don't know whether they are signals or variables. There are many times I rewrite my code a bit to make it easier to read, but mostly I used a style that is not hard to read in the first place. You get used to using signals pretty quickly once you get the concept of the delta delay. BTW, Verilog doesn't have delta delays, so they talk about blocking vs. non-blocking assignments. When I code Verilog I just use simple templates so I don't have to remember what "blocking" means exactly. I'm not so good with names if the meaning isn't clear from the name. I've never memorized what is being blocked and what that implies. I just write the code in a way that I know works. lol -- Rick C From newsfish@newsfish Thu Aug 1 00:37:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Fri, 30 Sep 2016 02:13:52 -0400 Organization: A noiseless patient Spider Lines: 194 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Sep 2016 06:13:41 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="cfa3b34c288179253928b4d47ccee148"; logging-data="13776"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+rRW6D7adb67kXxWprLejc" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: Cancel-Lock: sha1:OAICKhcwNmFpzX41XpIYfITPW6M= Xref: news.eternal-september.org comp.lang.vhdl:4605 On 9/30/2016 12:12 AM, rickman wrote: > On 9/29/2016 9:49 PM, KJ wrote: >> On Thursday, September 29, 2016 at 7:45:54 PM UTC-4, kristoff wrote: >>> >>> This is part of a process: >>> >>>> if (s_sclk_edgeup = '1') then -- on rising edge of spi-clock, >>>> read data, and determine -- next bit position >>>> >>>> buffer(bitcounter) <= spi_mosi; >>>> >>>> -- determine new bitposition if (bitcounter > 0) then bitcounter >>>> <= bitcounter - 1; else bitcounter <= 7; -- last bit -> go >>>> process received data state <= PROCESS_DATA; end if; end if; >>> >>> >>> >>> >>> If I understand this correctly, as this is part of a process, the >>> general rule is that the assignment is actually done at the END of >>> the process!!! >>> >> Almost. What happens inside the process is that the signals are >> 'scheduled' to be updated. At the end of the process, it suspends. >> Once *all* the processes that are active in the entire simulation >> have run and suspended, the simulator takes the list of all signals >> that have been scheduled to be updated and actually updates them. >> Scheduling to be updated and updating are two very different things. > > Your code segment does not indicate if these items are signals or > variables, but from your description of their behavior I expect they are > signals. I would just add to what KJ said by saying the terminology for > this delay of assignment is delta delay. Delta delays are like an > infinitely small increment of time, but no actual time elapses. When a > process executes and updates a signal, the update is scheduled for now + > 1 delta delay. The same thing happens when a concurrent statement is > executed, the assignment is scheduled for 1 delta delay later. > > So a process runs at time 100 ns and does a signal assignment scheduled > for 100 ns + 1 delta delay. This signal is used in a concurrent > assignment and that signal update is scheduled for 100 ns + 2 delta > delays. All of these events look like they happen at 100 ns but the > delta delays preserve the proper order of events to get the right result. > > In a process multiple assignments can be done to the same signal. The > last one to be executed is the one that actually is assigned to the > signal 1 delta delay later. > > You can create problems by running clocks through signal assignments. If > process one is clocked by clk1, clk2 is assigned the value of clk1 and > clk2 is used to clock process two, this will happen as if the two > processes run at different times, but a simulation will show the changes > at the same time. Example: > > clk2 <= clk1; > > process_one (clk1) begin > if (rising_edge(clk1) then > A <= input; > end if; > end process; > > process_two (clk1) begin > if (rising_edge(clk2) then > B <= A; > end if; > end process; > > Start with A = '0' and input = '1' when clk1 has a positive edge at time > 100 ns. After the dust has settled, A will be '0' and B will be '0'. > That is because A is assigned a '1' at time 100 ns + 1 delta delay. Clk2 > is also scheduled for a rising edge at 100 ns + 1 delta delay, so > process_two may be executed after A has been updated. If that happens B > will be assigned a '1' rather than a '0' which was the state of A prior > to the rising edge of clk1. > > I hope that makes sense. There are times you need to understand to > prevent this sort of error. > > >> This behavior is different than for variables. For a variable >> assignment, the variable is updated immediately, there is no >> scheduling. > > Yes, variables in VHDL work like variables in a typical sequential > programming language like C. A statement is executed entirely before > the next statement is executed. This is the opposite of how signals > work. So if variable A is assigned a value and later in the process A > is used, it will have the updated value. If A is a signal used anywhere > in the process before waiting the old value will be used. Once the > process suspends for any reason (exits at end or encounters a wait > statement) it won't run again until at least one delta delay. > > I'm a little unclear on how events scheduled for the same delta delay > are ordered for execution. Maybe someone else can explain that. I > don't know if they are ordered by the order they were executed (the > simulator actually can only run one process at a time, even if the > processes are supposed to run on the same delta delay) or in some other > sequence. > > >>> So, I tested this and ... in this case, this works nice. ... But >>> ... why? >>> >>> How does the VHDL compiler know what actions comes first? >>> >> The VHDL LRM defines this signal update scheduling. >> >>> >>> At first, I thought that this was related to the order in which the >>> two actions are written in the process (commands inside a process >>> do are processed in sequence, no?), >> >> Correct. >> >>> but when I move the "move down buffer-position pointer" part to the >>> start of this process, the code still works. (so this part was >>> executed LAST, not first!) >>> >> 'Executed' might be the wrong word to use here. When the signal >> assignment statement is 'executed' it is not updating the signal, it >> is just scheduling it to be updated. If there had been multiple >> assignments to a particular signal, then yes the order would matter >> since the scheduling that occurs for the last assignment would >> essentially override the scheduling that already occurred for the >> first assignment. In your process, there is only one assignment >> statement that will be executed no matter how one goes through the >> process. >> >>> (as said, I have been looking in the documentation I have, and not >>> found any information about this). >>> >> >> The LRM can be difficult to read. > > +1 VERY! > > Part of the problem is how it is written, to be precise and unambiguous > rather than easy to read. Partly it is because many times to understand > one thing, you have to go back and learn about something else which > means you have to learn another thing and so on. > > >>> Now, I know there are other ways to code this that are more >>> explicit about the order these two actions are executed: - make the >>> statemachine more complex - use a temporary variable. >>> >> >> Not sure what you're trying to get at here. The order doesn't matter >> in your example. You proved it yourself by noting the behavior was >> the same even when you shuffled the order. >> >>> >>> What would be "best practice" to code this "the proper way"? >>> >> There is nothing objectionable about the process you posted. > > I prefer to order statements so it is clear and easy to read. The order > you have written them makes sense whether they are executed in sequence > as variables, or pending a delta delay, so unambiguous even if you don't > know whether they are signals or variables. There are many times I > rewrite my code a bit to make it easier to read, but mostly I used a > style that is not hard to read in the first place. > > You get used to using signals pretty quickly once you get the concept of > the delta delay. > > BTW, Verilog doesn't have delta delays, so they talk about blocking vs. > non-blocking assignments. When I code Verilog I just use simple > templates so I don't have to remember what "blocking" means exactly. I'm > not so good with names if the meaning isn't clear from the name. I've > never memorized what is being blocked and what that implies. I just > write the code in a way that I know works. lol Opps, typo... > process_two (clk1) begin > if (rising_edge(clk2) then > B <= A; > end if; > end process; Should be... > process_two (clk2) begin > if (rising_edge(clk2) then > B <= A; > end if; > end process; -- Rick C From newsfish@newsfish Thu Aug 1 00:37:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Fri, 30 Sep 2016 02:18:04 -0400 Organization: A noiseless patient Spider Lines: 92 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Sep 2016 06:17:53 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="cfa3b34c288179253928b4d47ccee148"; logging-data="14661"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19++ut4HO86oshwXE43x5ok" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: Cancel-Lock: sha1:KaaRQbFUhhva9R4xoqZbpoktBRo= Xref: news.eternal-september.org comp.lang.vhdl:4606 On 9/30/2016 12:12 AM, rickman wrote: > On 9/29/2016 9:49 PM, KJ wrote: >> On Thursday, September 29, 2016 at 7:45:54 PM UTC-4, kristoff wrote: >>> >>> This is part of a process: >>> >>>> if (s_sclk_edgeup = '1') then -- on rising edge of spi-clock, >>>> read data, and determine -- next bit position >>>> >>>> buffer(bitcounter) <= spi_mosi; >>>> >>>> -- determine new bitposition if (bitcounter > 0) then bitcounter >>>> <= bitcounter - 1; else bitcounter <= 7; -- last bit -> go >>>> process received data state <= PROCESS_DATA; end if; end if; >>> >>> >>> >>> >>> If I understand this correctly, as this is part of a process, the >>> general rule is that the assignment is actually done at the END of >>> the process!!! >>> >> Almost. What happens inside the process is that the signals are >> 'scheduled' to be updated. At the end of the process, it suspends. >> Once *all* the processes that are active in the entire simulation >> have run and suspended, the simulator takes the list of all signals >> that have been scheduled to be updated and actually updates them. >> Scheduling to be updated and updating are two very different things. > > Your code segment does not indicate if these items are signals or > variables, but from your description of their behavior I expect they are > signals. I would just add to what KJ said by saying the terminology for > this delay of assignment is delta delay. Delta delays are like an > infinitely small increment of time, but no actual time elapses. When a > process executes and updates a signal, the update is scheduled for now + > 1 delta delay. The same thing happens when a concurrent statement is > executed, the assignment is scheduled for 1 delta delay later. > > So a process runs at time 100 ns and does a signal assignment scheduled > for 100 ns + 1 delta delay. This signal is used in a concurrent > assignment and that signal update is scheduled for 100 ns + 2 delta > delays. All of these events look like they happen at 100 ns but the > delta delays preserve the proper order of events to get the right result. > > In a process multiple assignments can be done to the same signal. The > last one to be executed is the one that actually is assigned to the > signal 1 delta delay later. > > You can create problems by running clocks through signal assignments. If > process one is clocked by clk1, clk2 is assigned the value of clk1 and > clk2 is used to clock process two, this will happen as if the two > processes run at different times, but a simulation will show the changes > at the same time. Example: > > clk2 <= clk1; > > process_one (clk1) begin > if (rising_edge(clk1) then > A <= input; > end if; > end process; > > process_two (clk1) begin > if (rising_edge(clk2) then > B <= A; > end if; > end process; It is just not my night. I also left off a close parentheses on the IF statements. :( The example should be... > clk2 <= clk1; > > process_one (clk1) begin > if (rising_edge(clk1)) then > A <= input; > end if; > end process; > > process_two (clk2) begin > if (rising_edge(clk2)) then > B <= A; > end if; > end process; Each of the data items are signals. -- Rick C From newsfish@newsfish Thu Aug 1 00:37:58 2024 X-Received: by 10.157.47.9 with SMTP id h9mr1936907otb.81.1475237536997; Fri, 30 Sep 2016 05:12:16 -0700 (PDT) X-Received: by 10.36.29.144 with SMTP id 138mr207554itj.8.1475237536953; Fri, 30 Sep 2016 05:12:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!184no153620ity.0!news-out.google.com!203ni2504itk.0!nntp.google.com!184no153616ity.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Sep 2016 05:12:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: inter-dependent assignments in process From: KJ Injection-Date: Fri, 30 Sep 2016 12:12:16 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4607 On Friday, September 30, 2016 at 12:12:52 AM UTC-4, rickman wrote: > On 9/29/2016 9:49 PM, KJ wrote: > I'm a little unclear on how events scheduled for the same delta delay=20 > are ordered for execution. Maybe someone else can explain that. I=20 > don't know if they are ordered by the order they were executed (the=20 > simulator actually can only run one process at a time, even if the=20 > processes are supposed to run on the same delta delay) or in some other= =20 > sequence. >=20 Events scheduled for the same delta delay are not ordered for execution. I= f a signal has more than one event scheduled (for example being driven by m= ore than one process), and it is a resolved signal, then the resolved funct= ion for that signal's data type is called. The inputs to that resolved fun= ction are the various events that have been scheduled for that signal, the = output is a single value. Once all of the signal events have been resolved= , every signal has at most exactly one scheduled event. At that point, all= of the signals are then updated and time is advanced, typically to the nex= t delta cycle. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:37:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed3-b.proxad.net!nnrp3-2.free.fr!not-for-mail Subject: Re: inter-dependent assignments in process Newsgroups: comp.lang.vhdl References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> From: Nicolas Matringe Date: Fri, 30 Sep 2016 23:35:29 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 25 Message-ID: <57eedaa1$0$19742$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 30 Sep 2016 23:35:29 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1475271329 news-3.free.fr 19742 88.185.146.198:24876 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:4608 On 30.09.2016 06:12, rickman wrote: > On 9/29/2016 9:49 PM, KJ wrote: >> On Thursday, September 29, 2016 at 7:45:54 PM UTC-4, kristoff wrote: >>> >>> This is part of a process: >>> >>>> if (s_sclk_edgeup = '1') then -- on rising edge of spi-clock, >>>> read data, and determine -- next bit position >>>> >>>> buffer(bitcounter) <= spi_mosi; >>>> >>>> -- determine new bitposition if (bitcounter > 0) then bitcounter >>>> <= bitcounter - 1; else bitcounter <= 7; -- last bit -> go >>>> process received data state <= PROCESS_DATA; end if; end if; [...] > > Your code segment does not indicate if these items are signals or > variables, but from your description of their behavior I expect they are > signals. Well obviously they are signals because the assignment operator is "<=", variables would have been assigned using ":=". Nicolas From newsfish@newsfish Thu Aug 1 00:37:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Fri, 30 Sep 2016 18:05:25 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Sep 2016 22:05:13 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="dc4c7f6c74879e49eaad02f7e7b2f2f0"; logging-data="12832"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/LmF5Efsm83MCkTgLh89Km" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: Cancel-Lock: sha1:VA4xRA2v3EvmGyTFuXxQHiGg9/M= Xref: news.eternal-september.org comp.lang.vhdl:4609 On 9/30/2016 8:12 AM, KJ wrote: > On Friday, September 30, 2016 at 12:12:52 AM UTC-4, rickman wrote: >> On 9/29/2016 9:49 PM, KJ wrote: I'm a little unclear on how events >> scheduled for the same delta delay are ordered for execution. >> Maybe someone else can explain that. I don't know if they are >> ordered by the order they were executed (the simulator actually can >> only run one process at a time, even if the processes are supposed >> to run on the same delta delay) or in some other sequence. >> > > Events scheduled for the same delta delay are not ordered for > execution. If a signal has more than one event scheduled (for > example being driven by more than one process), and it is a resolved > signal, then the resolved function for that signal's data type is > called. The inputs to that resolved function are the various events > that have been scheduled for that signal, the output is a single > value. Once all of the signal events have been resolved, every > signal has at most exactly one scheduled event. At that point, all > of the signals are then updated and time is advanced, typically to > the next delta cycle. Thanks for that explanation. I think I was mixing up the execution of statements and the assignment of values. So consider the example where clk2 is assigned a value from clk1; the rising edge of clk2 is 1 delta delay after the rising edge of clk1. So the signals in the clk1 triggered process are assigned a value at time delta 1, but then the clk2 process runs *after* the signals are updated, correct? If it is not done this way where all the signals are updated prior to any code being executed, the ordering of events can change the outcome. So do I have this correct now? -- Rick C From newsfish@newsfish Thu Aug 1 00:37:59 2024 X-Received: by 10.157.3.1 with SMTP id 1mr2609485otv.95.1475297603694; Fri, 30 Sep 2016 21:53:23 -0700 (PDT) X-Received: by 10.36.237.193 with SMTP id r184mr485890ith.2.1475297603668; Fri, 30 Sep 2016 21:53:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!184no407277ity.0!news-out.google.com!203ni3234itk.0!nntp.google.com!184no407269ity.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Sep 2016 21:53:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:1a30:80f5:de70:7a49:c5d9; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:1a30:80f5:de70:7a49:c5d9 References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: inter-dependent assignments in process From: KJ Injection-Date: Sat, 01 Oct 2016 04:53:23 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4610 On Friday, September 30, 2016 at 6:05:26 PM UTC-4, rickman wrote: > So consider the example where=20 > clk2 is assigned a value from clk1; the rising edge of clk2 is 1 delta=20 > delay after the rising edge of clk1. So the signals in the clk1=20 > triggered process are assigned a value at time delta 1, but then the=20 > clk2 process runs *after* the signals are updated, correct? =20 Correct. Processes that have clk2 in the sensitivity list (or are waiting = for a clk2'event) will run after all the signals that have been affected by= the clk1'event have been updated. Updating signals is the last thing that= happens prior to time advancing. Kevin From newsfish@newsfish Thu Aug 1 00:37:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Sat, 1 Oct 2016 13:22:22 +0200 Organization: A noiseless patient Spider Lines: 69 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Oct 2016 11:22:11 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="07120b51675752922eb694b944b92404"; logging-data="23734"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/GAtfl5XTXZ+k3vqRJYed0" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Cancel-Lock: sha1:7optivmDm1Q37nk9RNYybDVvzXM= Xref: news.eternal-september.org comp.lang.vhdl:4611 Hi Kevin, (and Rick who also replied) On 30-09-16 03:49, KJ wrote: >> This is part of a process: >>> if (s_sclk_edgeup = '1') then >>> -- on rising edge of spi-clock, read data, and determine >>> -- next bit position >>> >>> buffer(bitcounter) <= spi_mosi; >>> >>> -- determine new bitposition >>> if (bitcounter > 0) then >>> bitcounter <= bitcounter - 1; >>> else >>> bitcounter <= 7; >>> -- last bit -> go process received data >>> state <= PROCESS_DATA; >>> end if; >>> end if; >> If I understand this correctly, as this is part of a process, the >> general rule is that the assignment is actually done at the END of the >> process!!! > Almost. What happens inside the process is that the signals are > 'scheduled' to be updated. At the end of the process, it suspends. > Once *all* the processes that are active in the entire simulation have > run and suspended, the simulator takes the list of all signals that > have been scheduled to be updated and actually updates them. > Scheduling to be updated and updating are two very different things. Thanks for the very clear explanation! It really helped me to understand things. >> How does the VHDL compiler know what actions comes first? > The VHDL LRM defines this signal update scheduling. (...) > The LRM can be difficult to read. (...) Well, a simple summary of this particular process would be nice :-) In another message, you talked about a "resolved function". Does this mean that -in my case- that - "bitcounter <= bitcounter - 1" is a resolved function (as it requires itself). - "buffer(bitcounter) <= spi_mosi" is not a resolved function as the "buffer(...)" depends on another signal (bitcounter in this case)? So can I assume that resolved functions are scheduled to be executed first? Or is there something else in play here? > Kevin Jennings Cheerio! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:37:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: kristoff Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Sat, 1 Oct 2016 14:15:36 +0200 Organization: A noiseless patient Spider Lines: 58 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Oct 2016 12:15:25 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="07120b51675752922eb694b944b92404"; logging-data="1369"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19S87yaBpKMYlLYBwucjFin" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: Cancel-Lock: sha1:aLIGUVpt8HY2wjrt1S6dfw97aBc= Xref: news.eternal-september.org comp.lang.vhdl:4612 Rickman, On 30-09-16 06:12, rickman wrote: >>> What would be "best practice" to code this "the proper way"? >> There is nothing objectionable about the process you posted. > I prefer to order statements so it is clear and easy to read. The order > you have written them makes sense whether they are executed in sequence > as variables, or pending a delta delay, so unambiguous even if you don't > know whether they are signals or variables. There are many times I > rewrite my code a bit to make it easier to read, but mostly I used a > style that is not hard to read in the first place. That was indeed my point. Some of my code ends up on github and I myself also look at other peoples code from public source. I like code to be self-explaining. In fact, there three layer here: - the algorithm you want to implement - the source-code - the actual execution. On a microcontroller, it is pretty simple: if the source-code matches the algorithm, the actual execution of the code will match that too. In VHDL, that's not the case. Now, you can say "ok, that's VHDL is like, learn it!". But I just wonder that if -say- using temporary variables (e.g. in my example, to store the value of the index) is not a better idea. That way, you can write VHDL-code that does *always* result in an execution in the same order as what the VHDL-source looks like. > BTW, Verilog doesn't have delta delays, so they talk about blocking vs. > non-blocking assignments. When I code Verilog I just use simple > templates so I don't have to remember what "blocking" means exactly. I'm > not so good with names if the meaning isn't clear from the name. I've > never memorized what is being blocked and what that implies. I just > write the code in a way that I know works. lol Interesting point. Thanks! Kr. Bonne. From newsfish@newsfish Thu Aug 1 00:37:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Sat, 1 Oct 2016 09:52:34 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Oct 2016 13:52:22 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c307b8822932c9442f7fa2e5b87fe11b"; logging-data="21687"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18R1vdT0zJB+UBr3/nRg4Yp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: Cancel-Lock: sha1:3z2r3Z5hY+HsZGi8LUUV4iXmNLs= Xref: news.eternal-september.org comp.lang.vhdl:4613 On 10/1/2016 12:53 AM, KJ wrote: > On Friday, September 30, 2016 at 6:05:26 PM UTC-4, rickman wrote: >> So consider the example where clk2 is assigned a value from clk1; >> the rising edge of clk2 is 1 delta delay after the rising edge of >> clk1. So the signals in the clk1 triggered process are assigned a >> value at time delta 1, but then the clk2 process runs *after* the >> signals are updated, correct? > > Correct. Processes that have clk2 in the sensitivity list (or are > waiting for a clk2'event) will run after all the signals that have > been affected by the clk1'event have been updated. Updating signals > is the last thing that happens prior to time advancing. I think I know what you mean, but you said that backwards. When a statement is evaluated and an assignment is scheduled, the update for the signal is scheduled for the *next* delta cycle. So the update should be the *first* thing to happen on that t+1 delta cycle. Or maybe when you say "prior to time advancing", maybe you mean actual clock time? I had the impression delta time was invented so it could be treated the same as clock time, every event is scheduled for a time and when that time arrives the event happens. The order of assignments are not important because the values to be assigned to the signals are already determined. Once all the assignment events are completed, the various processes are checked to see what events trigger a sensitivity list and those processes run, possibly scheduling new assignments at future times. The assignments happen a bit like a master-slave FF. At this time the value to be assigned is calculated (the master FF is latched) and at a later time the assignment is made to the signal (the slave FF is latched). -- Rick C From newsfish@newsfish Thu Aug 1 00:38:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Sat, 1 Oct 2016 10:05:40 -0400 Organization: A noiseless patient Spider Lines: 71 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Oct 2016 14:05:27 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c307b8822932c9442f7fa2e5b87fe11b"; logging-data="24171"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18YOiD+SGjKYMKxNhSrr5hJ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: Cancel-Lock: sha1:GWEO5RqmrnPHUlsqttdHxT0/6lc= Xref: news.eternal-september.org comp.lang.vhdl:4614 On 10/1/2016 8:15 AM, kristoff wrote: > Rickman, > > > On 30-09-16 06:12, rickman wrote: > >>>> What would be "best practice" to code this "the proper way"? > >>> There is nothing objectionable about the process you posted. > >> I prefer to order statements so it is clear and easy to read. The order >> you have written them makes sense whether they are executed in sequence >> as variables, or pending a delta delay, so unambiguous even if you don't >> know whether they are signals or variables. There are many times I >> rewrite my code a bit to make it easier to read, but mostly I used a >> style that is not hard to read in the first place. > > That was indeed my point. > > Some of my code ends up on github and I myself also look at other > peoples code from public source. I like code to be self-explaining. > > > > In fact, there three layer here: > - the algorithm you want to implement > - the source-code > - the actual execution. > > > On a microcontroller, it is pretty simple: if the source-code matches > the algorithm, the actual execution of the code will match that too. > In VHDL, that's not the case. > > Now, you can say "ok, that's VHDL is like, learn it!". I don't follow this. Are you saying that because signals work the way they do, this means the source code does not match the algorithm??? > But I just wonder that if -say- using temporary variables (e.g. in my > example, to store the value of the index) is not a better idea. > That way, you can write VHDL-code that does *always* result in an > execution in the same order as what the VHDL-source looks like. I think this is a hold over in thinking from coding sequential code like MCUs. VHDL works like it does because it supports parallelism at a fundamental level. Of course this requires thinking about coding in a different way. Signal assignments happen in a consistent way. You just need to understand how they happen and not think of them like sequential code. In other words, "that's VHDL, learn it!" You are going to have a hard time if you don't. >> BTW, Verilog doesn't have delta delays, so they talk about blocking vs. >> non-blocking assignments. When I code Verilog I just use simple >> templates so I don't have to remember what "blocking" means exactly. I'm >> not so good with names if the meaning isn't clear from the name. I've >> never memorized what is being blocked and what that implies. I just >> write the code in a way that I know works. lol > Interesting point. Thanks! > > > > Kr. Bonne. > -- Rick C From newsfish@newsfish Thu Aug 1 00:38:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: inter-dependent assignments in process Date: Sat, 1 Oct 2016 10:18:11 -0400 Organization: A noiseless patient Spider Lines: 102 Message-ID: References: <87852ad0-ebe9-45cc-916c-7625b91aee7b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Oct 2016 14:17:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c307b8822932c9442f7fa2e5b87fe11b"; logging-data="27458"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19/bzXa9a/FuSpRJ97XGxQj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 In-Reply-To: Cancel-Lock: sha1:KFfTmFEzvlGKo9rxk1tXZhjtiNc= Xref: news.eternal-september.org comp.lang.vhdl:4615 On 10/1/2016 7:22 AM, kristoff wrote: > Hi Kevin, (and Rick who also replied) > > > > > On 30-09-16 03:49, KJ wrote: >>> This is part of a process: >>>> if (s_sclk_edgeup = '1') then >>>> -- on rising edge of spi-clock, read data, and determine >>>> -- next bit position >>>> >>>> buffer(bitcounter) <= spi_mosi; >>>> >>>> -- determine new bitposition >>>> if (bitcounter > 0) then >>>> bitcounter <= bitcounter - 1; >>>> else >>>> bitcounter <= 7; >>>> -- last bit -> go process received data >>>> state <= PROCESS_DATA; >>>> end if; >>>> end if; > >>> If I understand this correctly, as this is part of a process, the >>> general rule is that the assignment is actually done at the END of the >>> process!!! > >> Almost. What happens inside the process is that the signals are >> 'scheduled' to be updated. At the end of the process, it suspends. >> Once *all* the processes that are active in the entire simulation have >> run and suspended, the simulator takes the list of all signals that >> have been scheduled to be updated and actually updates them. >> Scheduling to be updated and updating are two very different things. > > Thanks for the very clear explanation! > It really helped me to understand things. > > >>> How does the VHDL compiler know what actions comes first? >> The VHDL LRM defines this signal update scheduling. > > (...) >> The LRM can be difficult to read. > (...) > > Well, a simple summary of this particular process would be nice :-) > > > In another message, you talked about a "resolved function". > > Does this mean that -in my case- that > - "bitcounter <= bitcounter - 1" is a resolved function (as it requires > itself). > > - "buffer(bitcounter) <= spi_mosi" is not a resolved function as the > "buffer(...)" depends on another signal (bitcounter in this case)? > > > So can I assume that resolved functions are scheduled to be executed first? > > > Or is there something else in play here? Not exactly. A resolved function relates to signals that have a definition of what happens when multiple drivers are on the same signal. An unresolved does not, so multiple drivers create a simulation error. The correct term would be a resolved data type or a resolution function which is the algorithm to define what happens to resolve the conflict. So a resolved data type will have a resolution function. Otherwise resolved data types are exactly the same as any other data types and execute the same. buffer(bitcounter) <= spi_mosi is resolved if buffer is a resolved data type. It only matters if you assign to this signal in two processes... process A (...) begin ... buffer(bitcounter) <= (others -> '0'); ... end process; process B (...) begin ... buffer(bitcounter) <= spi_mosi; ... end process; They do things similar to this in Verilog with an "initial" block and a usage block. In VHDL this creates two drivers for the signal buffer. Since Hi-Z buffers are very seldom used these days (at least inside FPGAs) this is usually an error. I would use unresolved data types to immediately flag this as an error, but some of the newer data types which are useful for math and such are defined in terms of std_logic which is a resolved function. I don't know of any way to make the signed or unsigned data types unresolved since they are based on std_logic and not std_ulogic (the unresolved type). -- Rick C From newsfish@newsfish Thu Aug 1 00:38:00 2024 X-Received: by 10.36.230.196 with SMTP id e187mr265379ith.1.1475821198071; Thu, 06 Oct 2016 23:19:58 -0700 (PDT) X-Received: by 10.36.181.92 with SMTP id j28mr1413287iti.3.1475821197081; Thu, 06 Oct 2016 23:19:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no790393itl.0!news-out.google.com!w143ni2430itb.0!nntp.google.com!o19no795274ito.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Oct 2016 23:19:56 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2404:e800:e62c:27c:ab28:8e46:9228:c3cc; posting-account=lYq8NwoAAAAPgtz7rx5LxTjTo3IG6-El NNTP-Posting-Host: 2404:e800:e62c:27c:ab28:8e46:9228:c3cc User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Help with multiplier code From: Marvin L Injection-Date: Fri, 07 Oct 2016 06:19:58 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4616 Hi, I am having problem with https://ptpb.pw/4Twc , https://ptpb.pw/UpJX and http://i.imgur.com/wGEVxuL.png It just could not multiply 2 and 3. and 3 is never read in. Why ? Besides, there is timing violation, if I am not wrong, should be due to inefficient multiplier operator * I searched online and found wallace tree and daddas multiplier. Any advice ? From newsfish@newsfish Thu Aug 1 00:38:01 2024 X-Received: by 10.129.91.136 with SMTP id p130mr142277ywb.61.1476271643120; Wed, 12 Oct 2016 04:27:23 -0700 (PDT) X-Received: by 10.36.71.141 with SMTP id t135mr61279itb.10.1476271643047; Wed, 12 Oct 2016 04:27:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!g45no139797qte.1!news-out.google.com!203ni672itk.0!nntp.google.com!o19no201512ito.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 Oct 2016 04:27:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.107.2.7; posting-account=hYnf0woAAADHUli9G8YQxNJxnkarW2ni NNTP-Posting-Host: 175.107.2.7 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: ADC_DAC_PGA_SPI_INTERFACE From: khuda Bakhsh Rai Injection-Date: Wed, 12 Oct 2016 11:27:23 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4617 HELLO, i have written a vhdl code of on chip adc,dac,pga on spartan 3e kit. code is working good.but when i applied ac input signal at the input then output of dac is clipped. can anyone help me out to resolve this issue. From newsfish@newsfish Thu Aug 1 00:38:01 2024 X-Received: by 10.200.51.97 with SMTP id u30mr437627qta.16.1476287175351; Wed, 12 Oct 2016 08:46:15 -0700 (PDT) X-Received: by 10.36.121.78 with SMTP id z75mr227764itc.9.1476287175307; Wed, 12 Oct 2016 08:46:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.mixmin.net!enother.net!at.enother.net!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!f6no243380qtd.0!news-out.google.com!203ni871itk.0!nntp.google.com!o19no363547ito.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 Oct 2016 08:46:14 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.224.63.50; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.224.63.50 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: ADC_DAC_PGA_SPI_INTERFACE From: KJ Injection-Date: Wed, 12 Oct 2016 15:46:15 +0000 Content-Type: text/plain; charset=UTF-8 X-Received-Bytes: 1676 X-Received-Body-CRC: 1698158430 Xref: news.eternal-september.org comp.lang.vhdl:4618 On Wednesday, October 12, 2016 at 7:27:25 AM UTC-4, khuda Bakhsh Rai wrote: > HELLO, > i have written a vhdl code of on chip adc,dac,pga on spartan 3e kit. code is working good.but when i applied ac input signal at the input then output of dac is clipped. can anyone help me out to resolve this issue. Either cut down the AC input signal voltage or increase the reference voltage. In short, verify that the input signal stays within the range that it is supposed to. In the future, you might also want to post to a forum that is more relevant to your problem. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:38:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: ADC_DAC_PGA_SPI_INTERFACE Date: Wed, 12 Oct 2016 16:33:39 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 12 Oct 2016 20:33:20 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="41b7be89130f600228983cf8c51dba19"; logging-data="19091"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Z1E7Rvujv0EZudhnJmesh" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 In-Reply-To: Cancel-Lock: sha1:r8AeTMp+CeAK34Lnqelum+qYAY4= Xref: news.eternal-september.org comp.lang.vhdl:4619 On 10/12/2016 11:46 AM, KJ wrote: > On Wednesday, October 12, 2016 at 7:27:25 AM UTC-4, khuda Bakhsh Rai wrote: >> HELLO, >> i have written a vhdl code of on chip adc,dac,pga on spartan 3e kit. code is working good.but when i applied ac input signal at the input then output of dac is clipped. can anyone help me out to resolve this issue. > > Either cut down the AC input signal voltage or increase the reference voltage. In short, verify that the input signal stays within the range that it is supposed to. > > In the future, you might also want to post to a forum that is more relevant to your problem. What's wrong with this group? What group should he post in? -- Rick C From newsfish@newsfish Thu Aug 1 00:38:02 2024 X-Received: by 10.237.37.154 with SMTP id x26mr2235506qtc.17.1476386585873; Thu, 13 Oct 2016 12:23:05 -0700 (PDT) X-Received: by 10.36.237.193 with SMTP id r184mr758179ith.2.1476386585787; Thu, 13 Oct 2016 12:23:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!g45no670226qte.1!news-out.google.com!w143ni2043itb.0!nntp.google.com!l13no1123789itl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 13 Oct 2016 12:23:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.53.155.245; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.53.155.245 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <98d0f942-7037-48f9-9a2a-215a2d51464d@googlegroups.com> Subject: Re: ADC_DAC_PGA_SPI_INTERFACE From: stchebel@gmail.com Injection-Date: Thu, 13 Oct 2016 19:23:05 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 8 X-Original-Bytes: 1644 Xref: news.eternal-september.org comp.lang.vhdl:4620 W dniu =C5=9Broda, 12 pa=C5=BAdziernika 2016 13:27:25 UTC+2 u=C5=BCytkownik= khuda Bakhsh Rai napisa=C5=82: > HELLO, > i have written a vhdl code of on chip adc,dac,pga on spartan 3e kit. code= is working good.but when i applied ac input signal at the input then outpu= t of dac is clipped. can anyone help me out to resolve this issue. Without the details about the AC signal,DAC and your code, nobody could be = able to help you in this matter here. From newsfish@newsfish Thu Aug 1 00:38:02 2024 From: "Michael Kellett" Newsgroups: comp.lang.vhdl Subject: Re: ADC_DAC_PGA_SPI_INTERFACE Date: fri, 14 oct 2016 14:07:07 +0100 Message-ID: Content-Type: text/plain; charset="iso-8859-1" References: X-Newsreader: UseNeXT 5.64 Organization: Welcome to Aviteo Ltd DE Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.abavia.com!fbe001.abavia.com!abp001.abavia.com!news.usenext.de!not-for-mail Lines: 25 Injection-Date: Fri, 14 Oct 2016 15:07:14 +0200 Injection-Info: news.usenext.de; mail-complaints-to="abuse@usenext.de" Xref: news.eternal-september.org comp.lang.vhdl:4621 khuda Bakhsh Rai: > HELLO, > i have written a vhdl code of on chip adc,dac,pga on spartan 3e kit. code is working good.but when i applied ac input signal at the input then output of dac is clipped. can anyone help me out to resolve this issue. You don't explain enough to help except in the most general terms. Your DAC might be clipping because the digital signal is clipped or your power supplies are at fault. Mod your vhdl to make ramp driving the DAC from max to min and see what that looks like - if good then your signal from the ADC must be clipped. Check that max adc signal is OK for the DAC. Add some more test code to capture the maximum and minium digital codes from the ADC (I often use a UART implemneted on the FPGA for this) - then drive the ADC with signals. Next time design your FPGA with test modes built in from the outset. I pretty much never have an ADC without there also being a test mode where I can substitute patterns for its data. MK From newsfish@newsfish Thu Aug 1 00:38:02 2024 X-Received: by 10.36.40.148 with SMTP id h142mr2016178ith.12.1477207077268; Sun, 23 Oct 2016 00:17:57 -0700 (PDT) X-Received: by 10.36.185.91 with SMTP id k27mr190952iti.6.1477207077175; Sun, 23 Oct 2016 00:17:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!66no1963654itl.0!news-out.google.com!w143ni2246itb.0!nntp.google.com!e187no1949908itc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 23 Oct 2016 00:17:56 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2404:e800:e62c:27c:ab28:8e46:9228:c3cc; posting-account=lYq8NwoAAAAPgtz7rx5LxTjTo3IG6-El NNTP-Posting-Host: 2404:e800:e62c:27c:ab28:8e46:9228:c3cc User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6a9df45a-f780-4cab-ba74-0efcfde6647f@googlegroups.com> Subject: entity component binding issue with configurations From: Marvin L Injection-Date: Sun, 23 Oct 2016 07:17:57 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4622 I have binding warnings http://paste2.org/La9jIxbF with http://paste2.org/wnHDY0g3 How do I solve them ? even I modify the configuration as in http://paste2.org/bJZJPdWt , I have this error http://paste2.org/BLW1yg32 From newsfish@newsfish Thu Aug 1 00:38:03 2024 X-Received: by 10.98.149.142 with SMTP id c14mr9559978pfk.38.1477274373288; Sun, 23 Oct 2016 18:59:33 -0700 (PDT) X-Received: by 10.36.36.15 with SMTP id f15mr13052ita.8.1477274373219; Sun, 23 Oct 2016 18:59:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f6no1925711qtd.0!news-out.google.com!w25ni30777qtc.0!nntp.google.com!g45no1925972qte.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 23 Oct 2016 18:59:32 -0700 (PDT) In-Reply-To: <6a9df45a-f780-4cab-ba74-0efcfde6647f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2404:e800:e62c:27c:ab28:8e46:9228:c3cc; posting-account=lYq8NwoAAAAPgtz7rx5LxTjTo3IG6-El NNTP-Posting-Host: 2404:e800:e62c:27c:ab28:8e46:9228:c3cc References: <6a9df45a-f780-4cab-ba74-0efcfde6647f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7ae985f2-0629-47c7-a8b8-c371a64c7deb@googlegroups.com> Subject: Re: entity component binding issue with configurations From: Marvin L Injection-Date: Mon, 24 Oct 2016 01:59:33 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4623 On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote: > I have binding warnings http://paste2.org/La9jIxbF with http://paste2.org= /wnHDY0g3 How do I solve them ? even I modify the configuration as in h= ttp://paste2.org/bJZJPdWt , I have this error http://paste2.org/BLW1yg32 I have solved the binding compilation warning.=20 Now, I could not view the internal signal http://i.imgur.com/w4jwnN1.png ev= en though I am using the formal format *ghw with http://paste2.org/mVMOJZYA= , http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , http://paste2.= org/FDh4c6Av and http://paste2.org/UwgnBnds From newsfish@newsfish Thu Aug 1 00:38:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: entity component binding issue with configurations Date: Mon, 24 Oct 2016 19:42:08 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <6a9df45a-f780-4cab-ba74-0efcfde6647f@googlegroups.com> <7ae985f2-0629-47c7-a8b8-c371a64c7deb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 24 Oct 2016 23:41:44 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="2887446b358e63b6fbfd954a972219c2"; logging-data="11857"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18l/1LfX7tGD7THw0ZgKgQW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 In-Reply-To: <7ae985f2-0629-47c7-a8b8-c371a64c7deb@googlegroups.com> Cancel-Lock: sha1:qFQ2L1oUGKD7hpdI+6Fouh5sdt4= Xref: news.eternal-september.org comp.lang.vhdl:4624 On 10/23/2016 9:59 PM, Marvin L wrote: > On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote: >> I have binding warnings http://paste2.org/La9jIxbF with >> http://paste2.org/wnHDY0g3 How do I solve them ? even I modify >> the configuration as in http://paste2.org/bJZJPdWt , I have this >> error http://paste2.org/BLW1yg32 > > I have solved the binding compilation warning. > > Now, I could not view the internal signal > http://i.imgur.com/w4jwnN1.png even though I am using the formal > format *ghw with http://paste2.org/mVMOJZYA , > http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , > http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds Hi Marvin, I don't know how to help you. I'm not at all familiar with the tools you are using. I know I don't have this problem with Aldec Active-HDL. Can you explain the problem you had initially and how you fixed it? Others may have the same problem in the future. Likewise, when you fix this problem please post what you found. -- Rick C From newsfish@newsfish Thu Aug 1 00:38:03 2024 X-Received: by 10.237.34.47 with SMTP id n44mr11171580qtc.46.1477367416308; Mon, 24 Oct 2016 20:50:16 -0700 (PDT) X-Received: by 10.36.65.7 with SMTP id x7mr3878ita.0.1477367416075; Mon, 24 Oct 2016 20:50:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!y38no186518qta.0!news-out.google.com!f59ni94qtb.1!nntp.google.com!g49no1024qtc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Oct 2016 20:50:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=137.132.228.29; posting-account=lYq8NwoAAAAPgtz7rx5LxTjTo3IG6-El NNTP-Posting-Host: 137.132.228.29 References: <6a9df45a-f780-4cab-ba74-0efcfde6647f@googlegroups.com> <7ae985f2-0629-47c7-a8b8-c371a64c7deb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <35747496-95e1-43d9-81d3-09cf6f4c33f9@googlegroups.com> Subject: Re: entity component binding issue with configurations From: Marvin L Injection-Date: Tue, 25 Oct 2016 03:50:16 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 33 Xref: news.eternal-september.org comp.lang.vhdl:4625 On Tuesday, October 25, 2016 at 7:42:09 AM UTC+8, rickman wrote: > On 10/23/2016 9:59 PM, Marvin L wrote: > > On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote: > >> I have binding warnings http://paste2.org/La9jIxbF with > >> http://paste2.org/wnHDY0g3 How do I solve them ? even I modify > >> the configuration as in http://paste2.org/bJZJPdWt , I have this > >> error http://paste2.org/BLW1yg32 > > > > I have solved the binding compilation warning. > > > > Now, I could not view the internal signal > > http://i.imgur.com/w4jwnN1.png even though I am using the formal > > format *ghw with http://paste2.org/mVMOJZYA , > > http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , > > http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds > > Hi Marvin, > > I don't know how to help you. I'm not at all familiar with the tools > you are using. I know I don't have this problem with Aldec Active-HDL. > > Can you explain the problem you had initially and how you fixed it? > Others may have the same problem in the future. Likewise, when you fix > this problem please post what you found. > > -- > > Rick C I have solved the previous problem because I have forgotten to compile subbytes.vhd and round_constant.vhd together with key_expansion.vhd what does mutiple architecture means as in http://www.edaboard.com/thread360462.html ? How do I fix that ? anything wrong with the compile order as in the makefile at http://paste2.org/Kv7vD8xL ? From newsfish@newsfish Thu Aug 1 00:38:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: entity component binding issue with configurations Date: Tue, 25 Oct 2016 00:38:49 -0400 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <6a9df45a-f780-4cab-ba74-0efcfde6647f@googlegroups.com> <7ae985f2-0629-47c7-a8b8-c371a64c7deb@googlegroups.com> <35747496-95e1-43d9-81d3-09cf6f4c33f9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 25 Oct 2016 04:38:24 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="2887446b358e63b6fbfd954a972219c2"; logging-data="573"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/KxJdUCaOJfph8cQ6+XNWw" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 In-Reply-To: <35747496-95e1-43d9-81d3-09cf6f4c33f9@googlegroups.com> Cancel-Lock: sha1:+la+0lc574urUIB2y/VrIcHOQj4= Xref: news.eternal-september.org comp.lang.vhdl:4626 On 10/24/2016 11:50 PM, Marvin L wrote: > On Tuesday, October 25, 2016 at 7:42:09 AM UTC+8, rickman wrote: >> On 10/23/2016 9:59 PM, Marvin L wrote: >>> On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote: >>>> I have binding warnings http://paste2.org/La9jIxbF with >>>> http://paste2.org/wnHDY0g3 How do I solve them ? even I modify >>>> the configuration as in http://paste2.org/bJZJPdWt , I have this >>>> error http://paste2.org/BLW1yg32 >>> >>> I have solved the binding compilation warning. >>> >>> Now, I could not view the internal signal >>> http://i.imgur.com/w4jwnN1.png even though I am using the formal >>> format *ghw with http://paste2.org/mVMOJZYA , >>> http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , >>> http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds >> >> Hi Marvin, >> >> I don't know how to help you. I'm not at all familiar with the tools >> you are using. I know I don't have this problem with Aldec Active-HDL. >> >> Can you explain the problem you had initially and how you fixed it? >> Others may have the same problem in the future. Likewise, when you fix >> this problem please post what you found. >> >> -- >> >> Rick C > > I have solved the previous problem because I have forgotten to compile subbytes.vhd and round_constant.vhd together with key_expansion.vhd > > what does mutiple architecture means as in http://www.edaboard.com/thread360462.html ? How do I fix that ? > > anything wrong with the compile order as in the makefile at http://paste2.org/Kv7vD8xL ? I can't say if your compile order is good or not without going through all the code. Any module that invokes another module must be compiled *after* the invoked module has been compiled. At least that is how the tools I use do it. They automatically scan the files looking for dependencies and order the files appropriately. I have never run into multiple architectures before, but I suppose it means you have more than one architecture with the same name? -- Rick C From newsfish@newsfish Thu Aug 1 00:38:04 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!newspump.sol.net!newspeer1.nac.net!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: entity component binding issue with configurations Newsgroups: comp.lang.vhdl References: <6a9df45a-f780-4cab-ba74-0efcfde6647f@googlegroups.com> <7ae985f2-0629-47c7-a8b8-c371a64c7deb@googlegroups.com> <35747496-95e1-43d9-81d3-09cf6f4c33f9@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 25 Oct 2016 10:04:17 GMT Lines: 87 Message-ID: <580f2e20$0$1514$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 53b10d49.news.astraweb.com X-Trace: DXC=MK]U]8e49]BWe7Bc]TQV_NL?0kYOcDh@J0V9>>T5iDBAh:BbU8OZ3AMHI6bY5_;LhIEBe]G`V^KXGcD`Fd36>n On 10/24/2016 11:50 PM, Marvin L wrote: >> On Tuesday, October 25, 2016 at 7:42:09 AM UTC+8, rickman wrote: >>> On 10/23/2016 9:59 PM, Marvin L wrote: >>>> On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote: >>>>> I have binding warnings http://paste2.org/La9jIxbF with >>>>> http://paste2.org/wnHDY0g3 How do I solve them ? even I modify >>>>> the configuration as in http://paste2.org/bJZJPdWt , I have this >>>>> error http://paste2.org/BLW1yg32 >>>> >>>> I have solved the binding compilation warning. >>>> >>>> Now, I could not view the internal signal >>>> http://i.imgur.com/w4jwnN1.png even though I am using the formal >>>> format *ghw with http://paste2.org/mVMOJZYA , >>>> http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , >>>> http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds >>> >>> Hi Marvin, >>> >>> I don't know how to help you. I'm not at all familiar with the tools >>> you are using. I know I don't have this problem with Aldec >>> Active-HDL. >>> >>> Can you explain the problem you had initially and how you fixed it? >>> Others may have the same problem in the future. Likewise, when you >>> fix this problem please post what you found. >>> >>> -- >>> >>> Rick C >> >> I have solved the previous problem because I have forgotten to compile >> subbytes.vhd and round_constant.vhd together with key_expansion.vhd >> >> what does mutiple architecture means as in >> http://www.edaboard.com/thread360462.html ? How do I fix that ? >> >> anything wrong with the compile order as in the makefile at >> http://paste2.org/Kv7vD8xL ? > > I can't say if your compile order is good or not without going through > all the code. Any module that invokes another module must be compiled > *after* the invoked module has been compiled. At least that is how the > tools I use do it. They automatically scan the files looking for > dependencies and order the files appropriately. > > I have never run into multiple architectures before, but I suppose it > means you have more than one architecture with the same name? Let's take those things one at a time. > Any module that invokes another module must be compiled > *after* the invoked module has been compiled. That's true if using entity instantiation. It's not true if using component instantiation. Components merely need to be compiled before elaboration. > At least that is how the > tools I use do it. They automatically scan the files looking for > dependencies and order the files appropriately. My experience has been that tools that try to guess the compile order will violate the LRM if confronted by unusual conditions such as configurations or multiple architectures for the one entity. (BTW, I only really have experience with Xilinx and Altera tools. Other tools may be better or worse. I'm not hopeful though.) > I have never run into multiple architectures before, but I suppose it > means you have more than one architecture with the same name? It's allowable to have multiple architectures (with unique names) for a given entity. This is commonly done, e.g. for RAM models - you might have a (quick to simulate) behavioural one, as well as a (slow to simulate) one with accurate timing. You can select between different architectures in multiple ways. - You can specify the architecture name in an entity instantiation. - You can use a configuration. - If not specified, it will default to the most recently compiled architecture. Regards, Allan From newsfish@newsfish Thu Aug 1 00:38:04 2024 X-Received: by 10.107.148.8 with SMTP id w8mr10970884iod.97.1477390396421; Tue, 25 Oct 2016 03:13:16 -0700 (PDT) X-Received: by 10.36.116.208 with SMTP id o199mr44752itc.6.1477390396331; Tue, 25 Oct 2016 03:13:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!g49no108929qtc.1!news-out.google.com!w25ni32770qtc.0!nntp.google.com!y38no294527qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Oct 2016 03:13:15 -0700 (PDT) In-Reply-To: <7ae985f2-0629-47c7-a8b8-c371a64c7deb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.60.125.22; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.60.125.22 References: <6a9df45a-f780-4cab-ba74-0efcfde6647f@googlegroups.com> <7ae985f2-0629-47c7-a8b8-c371a64c7deb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: entity component binding issue with configurations From: diogratia@gmail.com Injection-Date: Tue, 25 Oct 2016 10:13:16 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4628 On Monday, October 24, 2016 at 2:59:38 PM UTC+13, Marvin L wrote: > On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote: > > I have binding warnings http://paste2.org/La9jIxbF with http://paste2.o= rg/wnHDY0g3 How do I solve them ? even I modify the configuration as in= http://paste2.org/bJZJPdWt , I have this error http://paste2.org/BLW1yg32 >=20 > I have solved the binding compilation warning.=20 >=20 > Now, I could not view the internal signal http://i.imgur.com/w4jwnN1.png = even though I am using the formal format *ghw with http://paste2.org/mVMOJZ= YA , http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , http://paste= 2.org/FDh4c6Av and http://paste2.org/UwgnBnds Other than an unneeded use clause for package numeric_std in key_expansion.= vhd the only errors causing 'U's are in round_constant.vhd: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity round_constant is port ( CLK : in std_logic; key_load: in std_logic; rcon: out std_logic_vector(31 downto 0) ); =20 attribute SIGIS : string; attribute SIGIS of CLK : signal is "Clk"; =20 end round_constant; architecture EXAMPLE of round_constant is -- WAS key_expansion is signal rcnt_next, rcnt: integer :=3D 0; -- signal rcon : std_logic_vector(31 downto 0) :=3D (OTHERS =3D> '0'); -- = NAME signal rcon_next : std_logic_vector(31 downto 0) :=3D (OTHERS =3D> '0'); --= CHANGED begin process(clk) begin if rising_edge(clk) then if(key_load =3D '1') then=09 rcon <=3D x"01000000"; rcnt <=3D 0; else rcon <=3D rcon_next; -- ADDED=09 rcnt <=3D rcnt_next; end if; end if; end process; rcnt_next <=3D rcnt + 1; process(rcnt_next) begin =09 case(rcnt_next) is -- when 0 =3D> rcon <=3D x"01_00_00_00"; -- CHANGE rcon to rcon_nex= t -- when 1 =3D> rcon <=3D x"02_00_00_00"; -- when 2 =3D> rcon <=3D x"04_00_00_00"; -- when 3 =3D> rcon <=3D x"08_00_00_00"; -- when 4 =3D> rcon <=3D x"10_00_00_00"; -- when 5 =3D> rcon <=3D x"20_00_00_00"; -- when 6 =3D> rcon <=3D x"40_00_00_00"; -- when 7 =3D> rcon <=3D x"80_00_00_00"; -- when 8 =3D> rcon <=3D x"1b_00_00_00"; -- when 9 =3D> rcon <=3D x"36_00_00_00"; -- when OTHERS =3D> rcon <=3D x"00_00_00_00"; when 0 =3D> rcon_next <=3D x"01_00_00_00"; when 1 =3D> rcon_next <=3D x"02_00_00_00"; when 2 =3D> rcon_next <=3D x"04_00_00_00"; when 3 =3D> rcon_next <=3D x"08_00_00_00"; when 4 =3D> rcon_next <=3D x"10_00_00_00"; when 5 =3D> rcon_next <=3D x"20_00_00_00"; when 6 =3D> rcon_next <=3D x"40_00_00_00"; when 7 =3D> rcon_next <=3D x"80_00_00_00"; when 8 =3D> rcon_next <=3D x"1b_00_00_00"; when 9 =3D> rcon_next <=3D x"36_00_00_00"; when OTHERS =3D> rcon_next <=3D x"00_00_00_00"; end case; end process; end architecture EXAMPLE; Notice you had the entity name wrong in the architecture, I converted the a= rchitecture declarative part signal declaration of rcon to rcon_next, chang= ed the assignments in the case statement in the process, and added an assig= nment to rcon from rcon_next in your register process. From newsfish@newsfish Thu Aug 1 00:38:05 2024 X-Received: by 10.157.58.10 with SMTP id j10mr1611189otc.138.1478798793397; Thu, 10 Nov 2016 09:26:33 -0800 (PST) X-Received: by 10.157.11.120 with SMTP id p53mr808746otd.19.1478798793308; Thu, 10 Nov 2016 09:26:33 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!e187no396265itc.0!news-out.google.com!i74ni1250itb.0!nntp.google.com!q124no395118itd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Nov 2016 09:26:33 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.64.19.63; posting-account=FbSGrAoAAABQ2wJ_w2F-9zz9o6pYCJJr NNTP-Posting-Host: 91.64.19.63 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <63bda249-31e2-49d7-a4c9-a8c60e2266e7@googlegroups.com> Subject: newbio needs some help From: mike.be@gmx.de Injection-Date: Thu, 10 Nov 2016 17:26:33 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4629 this is adopted code of the original code, where I simply replaced all "and" by "or" [code] --------------------------------------------------------- -- Author : http://www.teahlab.com/ -- -- Circuit: or Gate -- -- Note : This VHDL program is a structural description -- of the interactive or Gate on teahlab.com. -- -- If you are new to VHDL, then notice how the -- program is designed: 1] first we declare the -- ENTITY, which is where we define the inputs -- and the outputs of the circuit. 2] Second -- we present the ARCHITECTURE, which is where -- we describe the behavior and function of -- the circuit. --------------------------------------------------------- --import std_logic from the IEEE library library ieee; use ieee.std_logic_1164.all; --ENTITY DECLARATION: name, inputs, outputs entity orGate is port( A, B : in std_logic; F : out std_logic); end orGate; --FUNCTIONAL DESCRIPTION: how the or Gate works architecture func of orGate is begin F <= A or B; end func; ------------------------------------------------------END ------------------------------------------------------END [/code] same in Testbench: [code] ------------------------------------------------------------ -- Author : http://www.teahlab.com/ -- -- Program : OR Gate Testbench -- -- Note : A testbench is a program that defines a set -- of input signals to verity the operation of -- a circuit: in this case, the or Gate. -- -- 1] The testbench takes no inputs or returns -- no outputs. As such the ENTITY declaration -- is empty. -- -- 2] The circuit under verification, here the -- or Gate, is imported into the testbench -- ARCHITECTURE as a component. ------------------------------------------------------------ --import std_logic from the IEEE library library ieee; use ieee.std_logic_1164.all; --ENTITY DECLARATION: no inputs, no outputs entity orGate_tb is end orGate_tb; -- Describe how to test the or Gate architecture tb1 of orGate_tb is --pass orGate entity to the testbench as component component orGate is port( A, B : in std_logic; F : out std_logic); end component; signal inA, inB, outF : std_logic; begin --map the testbench signals to the ports of the orGate mapping: orGate port map(inA, inB, outF); process --variable to track errors variable errCnt : integer := 0; begin --TEST 1 inA <= '0'; inB <= '0'; wait for 15 ns; assert(outF = '0') report "Error 1" severity error; if(outF /= '0') then errCnt := errCnt + 1; end if; --TEST 2 inA <= '0'; inB <= '1'; wait for 15 ns; assert(outF = '0') report "Error 2<---" severity error; if(outF /= '0') then errCnt := errCnt + 1; end if; --TEST 3 inA <= '1'; inB <= '1'; wait for 15 ns; assert(outF = '1') report "Error 3" severity error; if(outF /= '1') then errCnt := errCnt + 1; end if; -------------- SUMMARY ------------- if(errCnt = 0) then assert false report "Good!" severity note; else assert true report "Error!" severity error; end if; end process; end tb1; -------------------------------------------- configuration cfg_tb1 of orGate_tb is for tb1 end for; end cfg_tb1; ---------------------------------------------------------END ---------------------------------------------------------END [/code] in this I added a "1" to the "tb" ghdl shows non error on the "and"-Simulation (also via gtkwave) ghdl shows non error on ghdl -a or.vhdl ghdl shows non error on ghdl -a or_tb.vhdl ghdl shows non error on ghdl -e or_tb but ghdl shows continuously errors on ghdl -r or_tb "...(assertion error): Error 2<---" I manually added the "<---" to the "Error 2"-mark to see if is THIS "Error2" or another compiler-error. So, what is wrong in Test 2 of or_tb ? Mike. From newsfish@newsfish Thu Aug 1 00:38:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: newbio needs some help Date: Thu, 10 Nov 2016 14:03:05 -0500 Organization: Alacron, Inc. Lines: 150 Message-ID: References: <63bda249-31e2-49d7-a4c9-a8c60e2266e7@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 10 Nov 2016 19:03:13 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ec5d6afaf7f51b0712de398f816ed83d"; logging-data="16143"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18HHVaLJKxCHU6wsDUZLLnBHxh4JDA1HyE=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.24) Gecko/20100228 Thunderbird/2.0.0.24 Mnenhy/0.7.6.666 In-Reply-To: <63bda249-31e2-49d7-a4c9-a8c60e2266e7@googlegroups.com> Cancel-Lock: sha1:Y0xt3vGAtabmWX+4wHNpOhfAyDs= Xref: news.eternal-september.org comp.lang.vhdl:4630 mike.be@gmx.de wrote: > this is adopted code of the original code, where I simply replaced all "and" by "or" > [code] > --------------------------------------------------------- > -- Author : http://www.teahlab.com/ > -- > -- Circuit: or Gate > -- > -- Note : This VHDL program is a structural description > -- of the interactive or Gate on teahlab.com. > -- > -- If you are new to VHDL, then notice how the > -- program is designed: 1] first we declare the > -- ENTITY, which is where we define the inputs > -- and the outputs of the circuit. 2] Second > -- we present the ARCHITECTURE, which is where > -- we describe the behavior and function of > -- the circuit. > --------------------------------------------------------- > > --import std_logic from the IEEE library > library ieee; > use ieee.std_logic_1164.all; > > --ENTITY DECLARATION: name, inputs, outputs > entity orGate is > port( A, B : in std_logic; > F : out std_logic); > end orGate; > > --FUNCTIONAL DESCRIPTION: how the or Gate works > architecture func of orGate is > begin > F <= A or B; > end func; > ------------------------------------------------------END > ------------------------------------------------------END > [/code] > > same in Testbench: > [code] > ------------------------------------------------------------ > -- Author : http://www.teahlab.com/ > -- > -- Program : OR Gate Testbench > -- > -- Note : A testbench is a program that defines a set > -- of input signals to verity the operation of > -- a circuit: in this case, the or Gate. > -- > -- 1] The testbench takes no inputs or returns > -- no outputs. As such the ENTITY declaration > -- is empty. > -- > -- 2] The circuit under verification, here the > -- or Gate, is imported into the testbench > -- ARCHITECTURE as a component. > ------------------------------------------------------------ > > --import std_logic from the IEEE library > library ieee; > use ieee.std_logic_1164.all; > > --ENTITY DECLARATION: no inputs, no outputs > entity orGate_tb is > end orGate_tb; > > -- Describe how to test the or Gate > architecture tb1 of orGate_tb is > --pass orGate entity to the testbench as component > component orGate is > port( A, B : in std_logic; > F : out std_logic); > end component; > > signal inA, inB, outF : std_logic; > begin > --map the testbench signals to the ports of the orGate > mapping: orGate port map(inA, inB, outF); > > process > --variable to track errors > variable errCnt : integer := 0; > begin > --TEST 1 > inA <= '0'; > inB <= '0'; > wait for 15 ns; > assert(outF = '0') report "Error 1" severity error; > if(outF /= '0') then > errCnt := errCnt + 1; > end if; > > --TEST 2 > inA <= '0'; > inB <= '1'; > wait for 15 ns; > assert(outF = '0') report "Error 2<---" severity error; > if(outF /= '0') then > errCnt := errCnt + 1; > end if; > > --TEST 3 > inA <= '1'; > inB <= '1'; > wait for 15 ns; > assert(outF = '1') report "Error 3" severity error; > if(outF /= '1') then > errCnt := errCnt + 1; > end if; > > -------------- SUMMARY ------------- > if(errCnt = 0) then > assert false report "Good!" severity note; > else > assert true report "Error!" severity error; > end if; > > end process; > end tb1; > -------------------------------------------- > configuration cfg_tb1 of orGate_tb is > for tb1 > end for; > end cfg_tb1; > ---------------------------------------------------------END > ---------------------------------------------------------END > [/code] > in this I added a "1" to the "tb" > > ghdl shows non error on the "and"-Simulation (also via gtkwave) > ghdl shows non error on ghdl -a or.vhdl > ghdl shows non error on ghdl -a or_tb.vhdl > ghdl shows non error on ghdl -e or_tb > but ghdl shows continuously errors on ghdl -r or_tb > "...(assertion error): Error 2<---" > > I manually added the "<---" to the "Error 2"-mark to see if is THIS "Error2" or another compiler-error. > > So, what is wrong in Test 2 of or_tb ? > > Mike. Ummm... The "error" is that the assertion failed because you neglected to change the expected value of the output of an OR gate ('1') when one input is '1' and the other input '0'. This shows that assertions are working and caught the error in your testbench expected output. -- Gabor From newsfish@newsfish Thu Aug 1 00:38:05 2024 X-Received: by 10.157.7.197 with SMTP id 63mr10334701oto.38.1479288165973; Wed, 16 Nov 2016 01:22:45 -0800 (PST) X-Received: by 10.157.20.197 with SMTP id r5mr2088726otr.9.1479288165949; Wed, 16 Nov 2016 01:22:45 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!o1no112979ito.0!news-out.google.com!c26ni512itd.0!nntp.google.com!o1no112973ito.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Nov 2016 01:22:45 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.213.40.250; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 193.213.40.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Universal VHDL Verification Methodology (Free & Open source), Free webinar Thursday Nov. 17. From: espen.tallaksen@bitvis.no Injection-Date: Wed, 16 Nov 2016 09:22:45 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:4631 How can we do FPGA VHDL Verification faster and with better quality =E2=80= =93 at no extra cost? This is actually possible =E2=80=93 and with an average efficiency improvem= ent of 20 to 50% for medium to high complexity FPGAs. Less for data path or= iented designs and more for control or protocol oriented designs. At no ext= ra cost. All that is required is that you do your testbench development the same way= you do your design. Every single FPGA designer knows that a good top level= design architecture is critical. Most FPGA designers also know that a good= microarchitecture is at least as important for module design. It should th= us be obvious that a good architecture is also equally important for your t= estbench, but for some strange reason most testbenches do not have the same= good architecture as the design being verified. Most designers agree that the following are critical for an efficient devel= opment of a high quality design module: - Overview, Readability, Simplicity - Modifiability, Maintainability, Extendibility - Debuggability - Reusability So why should testbenches be any different, with on average the same time u= sage as the actual design? It should be obvious that these aspects are equally critical for testbench = development, but there has been no standard solution to build a good testbe= nch architecture =E2=80=93 until now =E2=80=93 when UVVM has been introduce= d as a free and open source solution to this challenge. See blog at EDACaf=C3=A9: http://www10.edacafe.com/blogs/aldec/2016/11/14/fpga-vhdl-verification-can-= we-do-this-faster-with-better-quality-at-no-extra-cost/ And please join the webinar tomorrow by registering at either of https://www.aldec.com/en/events/770 for presentation at 3pm CET https://www.aldec.com/en/events/771 for presentation at 11am PST From newsfish@newsfish Thu Aug 1 00:38:06 2024 X-Received: by 10.157.48.97 with SMTP id w30mr2039436otd.138.1479571922575; Sat, 19 Nov 2016 08:12:02 -0800 (PST) X-Received: by 10.157.17.167 with SMTP id v36mr498174otf.12.1479571922508; Sat, 19 Nov 2016 08:12:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!o1no1010137ito.0!news-out.google.com!x12ni3696ita.0!nntp.google.com!w132no1015673ita.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 19 Nov 2016 08:12:02 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=27.97.19.208; posting-account=XH_Z9goAAAAnzRmFx4T73aAVKtVO7Jwl NNTP-Posting-Host: 27.97.19.208 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5189d4eb-3ca2-4b4a-b8a6-fdba20908662@googlegroups.com> Subject: Re: Viterbi Decoder in VHDL From: azarudeentheboss@gmail.com Injection-Date: Sat, 19 Nov 2016 16:12:02 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4632 hi sir, i am also doing a project in viterbi decoder of convolutional codes in VHDL. constraint length k=3.code rate=1/2.i am now having some design problems in decoder side so if u have any coding in VHDL ping me at azarudeentheboss@gmail.com thank you From newsfish@newsfish Thu Aug 1 00:38:06 2024 X-Received: by 10.157.21.97 with SMTP id z30mr4242351otz.5.1479668711183; Sun, 20 Nov 2016 11:05:11 -0800 (PST) X-Received: by 10.157.17.167 with SMTP id v36mr645007otf.12.1479668711147; Sun, 20 Nov 2016 11:05:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!o1no1224761ito.0!news-out.google.com!x12ni4725ita.0!nntp.google.com!w132no1230541ita.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 20 Nov 2016 11:05:10 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:803:200:a6c0:7583:be64:b0cf:b08d; posting-account=fdLNJQoAAADUaOIcxjRoh3S4244ARyt9 NNTP-Posting-Host: 2601:803:200:a6c0:7583:be64:b0cf:b08d User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: String list parser in VHDL... From: omarjamal77@gmail.com Injection-Date: Sun, 20 Nov 2016 19:05:11 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4633 I am designing a VHDL combinational block that takes in a list of 8 ASCII characters as input and replaces the non-numeral characters with a dash '-', then rearranges the list to have the numerals on one side and '-'s on the other. Example input and output: Input: d126r24! Output: ---12246 Source Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity module1 is port (list1: IN string (1 to 8); list2: OUT string (1 to 8)); end entity; architecture behavior of module1 is signal temp: string (1 to 8); begin process (list1) variable a: integer:= 1; variable b: integer:= 8; variable c: string (1 to 8); begin for i in 1 to 8 loop if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1(i) = '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then c(a):= list1(i); a := a + 1; else c(b) := '-'; b := b - 1; end if; end loop; temp <= c; end process; list2 <= temp; end behavior; TEST BENCH: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tb_module1 is end entity; architecture behavior of tb_module1 is component module1 port (list1: IN string (1 to 8); list2: OUT string (1 to 8)); end component; signal list1, list2: string (1 to 8); begin DUT: module1 port map (list1 => list1, list2 => list2); process begin wait for 0 ns; list1 <= "12345678"; wait for 10 ns; list1 <= "001122nn"; wait for 10 ns; end process; end behavior; ISSUE: codes compile fine but upon simulating I get a fatal error in modelsim: "run # ** Fatal: (vsim-3734) Index value 9 is out of range 1 to 8. # Time: 10 ns Iteration: 1 Process: /tb_module1/DUT/line__15 File: C:/Modeltech_pe_edu_10.4a/examples/module1.vhd # Fatal error in ForLoop loop at C:/Modeltech_pe_edu_10.4a/examples/module1.vhd line 23 # # HDL call sequence: # Stopped at C:/Modeltech_pe_edu_10.4a/examples/module1.vhd 23 ForLoop loop" I cannot understand how this index error is happening. Please help! From newsfish@newsfish Thu Aug 1 00:38:06 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: String list parser in VHDL... Date: Mon, 21 Nov 2016 13:41:07 +0200 Organization: An impatient and LOUD arachnid Lines: 12 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain Injection-Info: mx02.eternal-september.org; posting-host="db093a81968eb179e9fb9d4d110d2ccd"; logging-data="10039"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+NOistim+yKcUY+0luuLBm" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) Cancel-Lock: sha1:fBMhXK+iX/Jaf9cxt13KkOPKrsU= sha1:H2p4mFX3P1kuk8AoAbNnilYpiKU= Xref: news.eternal-september.org comp.lang.vhdl:4634 omarjamal77@gmail.com writes: > ISSUE: codes compile fine but upon simulating I get a fatal error in modelsim: > > "run > # ** Fatal: (vsim-3734) Index value 9 is out of range 1 to 8. You need to reset the values of a and b after the loop, otherwise with the second input they start from whatever values they ended up with on the previous execution of the process. In your testcase, a is 8 when processing the second input starts and so goes out of bounds as soon as it's incremented. From newsfish@newsfish Thu Aug 1 00:38:07 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: String list parser in VHDL... Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 21 Nov 2016 11:56:31 GMT Lines: 120 Message-ID: <5832e0ef$0$1533$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 927623c8.news.astraweb.com X-Trace: DXC=gARJG\g4ZGd=3UWcM[dT7dL?0kYOcDh@jdIUPXe>9D4g\>T:^Al174hHI6bY5_;LhiEBe]G`V^KXgAXDib6QC`Fg2CHhlPo`9Ad X-Received-Body-CRC: 631155976 X-Received-Bytes: 4073 Xref: news.eternal-september.org comp.lang.vhdl:4635 On Sun, 20 Nov 2016 11:05:10 -0800, omarjamal77 wrote: > I am designing a VHDL combinational block that takes in a list of 8 > ASCII characters as input and replaces the non-numeral characters with a > dash '-', then rearranges the list to have the numerals on one side and > '-'s on the other. > > Example input and output: > > Input: d126r24! Output: ---12246 > > Source Code: > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity module1 is > port (list1: IN string (1 to 8); > list2: OUT string (1 to 8)); > end entity; > > architecture behavior of module1 is signal temp: string (1 to 8); > > begin > > process (list1) > variable a: integer:= 1; > variable b: integer:= 8; > variable c: string (1 to 8); > begin > > for i in 1 to 8 loop > if ((list1(i) = '0') or (list1(i) = '1') or (list1(i) = '2') or > (list1(i) = '3') or (list1(i) = '4') or (list1(i) = '5') or (list1 (i) = > '6') or (list1(i) = '7') or (list1(i) = '8') or (list1(i) = '9')) then > c(a):= list1(i); > a := a + 1; > else > c(b) := '-'; > b := b - 1; > end if; > end loop; > > temp <= c; > end process; > list2 <= temp; > end behavior; > > > TEST BENCH: > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity tb_module1 is end entity; > > architecture behavior of tb_module1 is component module1 > port (list1: IN string (1 to 8); > list2: OUT string (1 to 8)); > end component; > > signal list1, list2: string (1 to 8); > begin DUT: module1 port map (list1 => list1, list2 => list2); > > process begin wait for 0 ns; > list1 <= "12345678"; > wait for 10 ns; > list1 <= "001122nn"; > wait for 10 ns; > end process; > end behavior; > > > ISSUE: codes compile fine but upon simulating I get a fatal error in > modelsim: > > "run # ** Fatal: (vsim-3734) Index value 9 is out of range 1 to 8. > # Time: 10 ns Iteration: 1 Process: /tb_module1/DUT/line__15 File: > C:/Modeltech_pe_edu_10.4a/examples/module1.vhd # Fatal error in ForLoop > loop at C:/Modeltech_pe_edu_10.4a/examples/module1.vhd line 23 # > # HDL call sequence: > # Stopped at C:/Modeltech_pe_edu_10.4a/examples/module1.vhd 23 ForLoop > loop" > > I cannot understand how this index error is happening. Please help! The loop iterator 'i' is always within the range 1 to 8, but the variables 'a' and 'b' are not. Hint: change their declaration from: variable a: integer:= 1; variable b: integer:= 8; to variable a: integer range 1 to 8 := 1; variable b: integer range 1 to 8 := 8; and you will see that this is true. Variable 'a' will overflow once your code has processed more than 8 digits. The basic problem is that the initialisers for variables 'a' and 'b' are only done once at the start of simulation. They are not reinitialised every time the process is run. (It's just how VHDL works.) You can fix that by adding the following statements just before the for loop. a := 1; b := 8; Regards, Allan From newsfish@newsfish Thu Aug 1 00:38:07 2024 X-Received: by 10.99.61.205 with SMTP id k196mr1581241pga.3.1480016257410; Thu, 24 Nov 2016 11:37:37 -0800 (PST) X-Received: by 10.157.35.87 with SMTP id k23mr123397otd.13.1480016257309; Thu, 24 Nov 2016 11:37:37 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!n6no765170qtd.0!news-out.google.com!j8ni3015qtc.0!nntp.google.com!p16no764275qta.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Nov 2016 11:37:37 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.57.128.129; posting-account=Wd2I_AoAAAB4z7OYhNsW27LPxlNSGsqc NNTP-Posting-Host: 213.57.128.129 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: SRAM controller From: edix12345@gmail.com Injection-Date: Thu, 24 Nov 2016 19:37:37 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4636 Hi everyone, As I want to improve my VHDL skills and understand how to make good designs, I've decided to make a simple SRAM controller and would like to get some feedback about the design. Please give feedback with explanations so I can understand it better. Code: http://pastebin.com/epiBgi1Z From newsfish@newsfish Thu Aug 1 00:38:07 2024 X-Received: by 10.159.34.23 with SMTP id 23mr5831043uad.16.1480236595907; Sun, 27 Nov 2016 00:49:55 -0800 (PST) X-Received: by 10.157.11.120 with SMTP id p53mr394695otd.19.1480236595780; Sun, 27 Nov 2016 00:49:55 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!2.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!p16no1653162qta.1!news-out.google.com!j8ni7986qtc.0!nntp.google.com!p16no1653157qta.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Nov 2016 00:49:55 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.80.20.86; posting-account=u_ByjQoAAADfNLF-KSR-eHh67X5B0K4Q NNTP-Posting-Host: 203.80.20.86 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: [NEED HELP ARGENT!!]8-bit CPU system From: Chong Tee Injection-Date: Sun, 27 Nov 2016 08:49:55 +0000 Content-Type: text/plain; charset=UTF-8 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:4637 Design a functional 8-bit CPU System that combines and connect memory system, ALU, registers and control unit. include VHDL Model/Coding From newsfish@newsfish Thu Aug 1 00:38:08 2024 X-Received: by 10.99.121.132 with SMTP id u126mr7818860pgc.1.1480237368381; Sun, 27 Nov 2016 01:02:48 -0800 (PST) X-Received: by 10.157.48.39 with SMTP id d36mr398917otc.1.1480237368264; Sun, 27 Nov 2016 01:02:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!n6no1657324qtd.0!news-out.google.com!j8ni8000qtc.0!nntp.google.com!n6no1657320qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Nov 2016 01:02:47 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.80.20.86; posting-account=u_ByjQoAAADfNLF-KSR-eHh67X5B0K4Q NNTP-Posting-Host: 203.80.20.86 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: [NEED HELP ARGENT!!]8-bit CPU system From: Chong Tee Injection-Date: Sun, 27 Nov 2016 09:02:48 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4638 HI all. I am still a beginner in VHDL. Hope someone can help me to solve this problem. Thanks in advance. From newsfish@newsfish Thu Aug 1 00:38:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!post01.iad.highwinds-media.com!fx22.iad.POSTED!not-for-mail From: Evgeny Filatov User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [NEED HELP ARGENT!!]8-bit CPU system References: In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 14 Message-ID: X-Complaints-To: abuse@usenet-news.net NNTP-Posting-Date: Sun, 27 Nov 2016 11:43:06 UTC Organization: usenet-news.net Date: Sun, 27 Nov 2016 14:43:05 +0300 X-Received-Bytes: 1163 X-Received-Body-CRC: 164407816 Xref: news.eternal-september.org comp.lang.vhdl:4639 On 27.11.2016 11:49, Chong Tee wrote: > Design a functional 8-bit CPU System that combines and connect memory system, ALU, registers and control unit. > > include VHDL Model/Coding > Or you will kill one hostage an hour? ;-) If you want to get some help, it would be useful to provide some more information, such as: what part exactly of your project you don't understand? Gene From newsfish@newsfish Thu Aug 1 00:38:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Adam Jensen Newsgroups: comp.lang.vhdl Subject: Re: [NEED HELP ARGENT!!]8-bit CPU system Date: Sun, 27 Nov 2016 12:42:46 -0500 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Nov 2016 17:41:32 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="fe96371013b472f50c87a1eb1c303688"; logging-data="21079"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19IWNtAvXR8kxSmmyfqXrnG" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 In-Reply-To: Cancel-Lock: sha1:Sreug5I2dg4zyqVqTUtLQQWvAlk= Xref: news.eternal-september.org comp.lang.vhdl:4640 On 11/27/2016 06:43 AM, Evgeny Filatov wrote: > On 27.11.2016 11:49, Chong Tee wrote: >> Design a functional 8-bit CPU System that combines and connect memory >> system, ALU, registers and control unit. >> >> include VHDL Model/Coding >> > > Or you will kill one hostage an hour? ;-) ROFL From newsfish@newsfish Thu Aug 1 00:38:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: Re: [NEED HELP ARGENT!!]8-bit CPU system Date: Sun, 27 Nov 2016 22:00:40 +0200 Organization: Aioe.org NNTP Server Lines: 7 Message-ID: References: NNTP-Posting-Host: 9TAw1IQmpkeSuqrZD7/Uwg.user.gioia.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:4641 On 27/11/2016 10:49, Chong Tee wrote: > Design a functional 8-bit CPU System that combines and connect memory system, ALU, registers and control unit. > > include VHDL Model/Coding > check opencores.org, plenty of projects there From newsfish@newsfish Thu Aug 1 00:38:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Thu, 22 Dec 2016 14:58:25 -0500 Organization: A noiseless patient Spider Lines: 98 Message-ID: References: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 22 Dec 2016 19:56:54 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0c2ff391ec22dc1f3062535fbccab728"; logging-data="9336"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/kDr2uLOBpdxH9CHxZPEKc" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 In-Reply-To: Cancel-Lock: sha1:ML0AHSd+l35UBl5Wjeenx4S0n3c= Xref: news.eternal-september.org comp.lang.vhdl:4642 On 8/7/2016 3:18 AM, Ilya Kalistru wrote: > On Saturday, August 6, 2016 at 9:57:40 PM UTC+3, rickman wrote: >> On 8/6/2016 6:59 AM, Ilya Kalistru wrote: >>> >>>> Uh, don't you have to write the two conversion routines? How did you >>>> do those? >>> >>> Gray encoding is ubiquitous and I just have this functions in my "frequently used functions" package. >>> >>> function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is >>> variable Bin_var : STD_LOGIC_VECTOR(Gray'range); >>> begin >>> Bin_var := (others => '0'); >>> Bin_var(Gray'high) := Gray(Gray'high); >>> for i in Gray'high-1 downto 0 loop >>> Bin_var(i):= Bin_var(i+1) xor Gray(i); >>> end loop; >>> return Bin_var; >>> end function Gray2Bin; >>> >>>> What were the sizes and envelope code you used? >>> >>> ... >>> entity Add is >>> Port ( >>> clk : in std_logic; >>> A : in unsigned(15 downto 0); >>> B : out unsigned(15 downto 0); >>> C : in unsigned(15 downto 0); >>> D : out unsigned(15 downto 0) >>> ); >>> end Add; >>> >>> architecture Behavioral of Add is >>> .... >>> begin >>> B <= Bin2Gray(Gray2Bin(A) + 1) when rising_edge(clk); >>> D <= CalcGray(C, '1') when rising_edge(clk); >>> end Behavioral; >> >> Thanks. What about Bin2Gray? I'd like to try your code in my synthesis. >> >> In general, I don't find optimization to work all that well for many >> functions. It can work ok for smaller code sections, so maybe this is >> one that happens to do well with many synthesizers, or maybe the >> description you use turns out to be optimal in spite of the apparent >> simplicity of the description I used. For example, your code above >> would use an adder chain along with the explicit chain described in >> Gray2Bin (don't know about Bin2Gray) while my code has two explicit >> chains. This could be simpler since the adder carry chain is embedded >> in the logic elements in most FPGA families. >> >> I've wondered just how much complexity the exit in the second loop adds. >> Coding without the exit might simplify the logic. >> >> -- >> >> Rick C > > function Bin2Gray (Bin : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is > variable Gray_var : STD_LOGIC_VECTOR(Bin'range); > begin > Gray_var(Gray_var'high) := Bin(bin'high); > for i in 0 to bin'high - 1 loop > Gray_var(i) := Bin(i) xor Bin(i + 1); > end loop; > return Gray_var; > end function Bin2Gray; > > function Bin2Gray (Bin : in unsigned) return unsigned is > begin > return unsigned(Bin2Gray(std_logic_vector(Bin))); > end function Bin2Gray; > > > function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is > variable Bin_var : STD_LOGIC_VECTOR(Gray'range); > begin > Bin_var := (others => '0'); > Bin_var(Gray'high) := Gray(Gray'high); > for i in Gray'high-1 downto 0 loop > Bin_var(i):= Bin_var(i+1) xor Gray(i); > end loop; > return Bin_var; > end function Gray2Bin; > > function Gray2Bin (Gray : in unsigned) return unsigned is > begin > return unsigned(Gray2Bin(std_logic_vector(Gray))); > end function Gray2Bin; Nice illustrations of these algorithms. http://ncalculators.com/digital-computation/binary-gray-code-converter.htm -- Rick C From newsfish@newsfish Thu Aug 1 00:38:10 2024 X-Received: by 10.159.35.118 with SMTP id 109mr6966411uae.13.1482518410018; Fri, 23 Dec 2016 10:40:10 -0800 (PST) X-Received: by 10.157.47.183 with SMTP id r52mr1252723otb.0.1482518409937; Fri, 23 Dec 2016 10:40:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d45no151556qta.0!news-out.google.com!c1ni14999itd.0!nntp.google.com!b123no3060347itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 23 Dec 2016 10:40:09 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.176.16.76; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.176.16.76 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e144ca0-b21d-47ed-a31f-4d6f938db996@googlegroups.com> Subject: CPU 8051 translation from VHDL to verilog. From: bknpk@hotmail.com Injection-Date: Fri, 23 Dec 2016 18:40:09 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4643 CPU 8051 translation from VHDL to verilog. I used 8051 from http://www.cs.ucr.edu/~dalton/i8051/i8051syn The VHDL code has been translated to verilog. The cpu is also slightly modified to be able to use XILINX memories. Design General: The design is translated from a VHDL dalton project http://www.cs.ucr.edu/~dalton/i8051/i8051syn. For more info http://bknpk.dynu.com/my_web/cpu_8051_ver/top.html From newsfish@newsfish Thu Aug 1 00:38:10 2024 X-Received: by 10.107.34.80 with SMTP id i77mr3933111ioi.55.1482518470932; Fri, 23 Dec 2016 10:41:10 -0800 (PST) X-Received: by 10.157.42.16 with SMTP id t16mr268826ota.18.1482518470868; Fri, 23 Dec 2016 10:41:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!b123no3060554itb.0!news-out.google.com!c1ni14999itd.0!nntp.google.com!b123no3060552itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 23 Dec 2016 10:41:10 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.176.16.76; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.176.16.76 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2065a8dd-450c-441e-b3db-731c3470afdd@googlegroups.com> Subject: simple UART, tested with GHDL From: bknpk@hotmail.com Injection-Date: Fri, 23 Dec 2016 18:41:10 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4644 For a self study project, I needed some DUT. I found this simple UART, written in VHDL. For this DUT, I created, as an exercise, a complete specman verification environment. It includes three main parts:... For more info: http://bknpk.dynu.com/my_web/MiscellaneousHW/UART/uart_tx_1.html From newsfish@newsfish Thu Aug 1 00:38:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Fri, 23 Dec 2016 14:09:52 -0500 Organization: A noiseless patient Spider Lines: 122 Message-ID: References: <417e73dd-afc8-4578-8caa-f12480f88884@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 23 Dec 2016 19:08:21 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="8c071df23e1eba2f02f08e7f6653dcab"; logging-data="12272"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18//LrkPmArUSL/gcMcS8hQ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 In-Reply-To: Cancel-Lock: sha1:7nFfM/iFcn4hiG6EJo/RGsHdp/U= Xref: news.eternal-september.org comp.lang.vhdl:4645 On 12/22/2016 2:58 PM, rickman wrote: > On 8/7/2016 3:18 AM, Ilya Kalistru wrote: >> On Saturday, August 6, 2016 at 9:57:40 PM UTC+3, rickman wrote: >>> On 8/6/2016 6:59 AM, Ilya Kalistru wrote: >>>> >>>>> Uh, don't you have to write the two conversion routines? How did you >>>>> do those? >>>> >>>> Gray encoding is ubiquitous and I just have this functions in my >>>> "frequently used functions" package. >>>> >>>> function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return >>>> STD_LOGIC_VECTOR is >>>> variable Bin_var : STD_LOGIC_VECTOR(Gray'range); >>>> begin >>>> Bin_var := (others => '0'); >>>> Bin_var(Gray'high) := Gray(Gray'high); >>>> for i in Gray'high-1 downto 0 loop >>>> Bin_var(i):= Bin_var(i+1) xor Gray(i); >>>> end loop; >>>> return Bin_var; >>>> end function Gray2Bin; >>>> >>>>> What were the sizes and envelope code you used? >>>> >>>> ... >>>> entity Add is >>>> Port ( >>>> clk : in std_logic; >>>> A : in unsigned(15 downto 0); >>>> B : out unsigned(15 downto 0); >>>> C : in unsigned(15 downto 0); >>>> D : out unsigned(15 downto 0) >>>> ); >>>> end Add; >>>> >>>> architecture Behavioral of Add is >>>> .... >>>> begin >>>> B <= Bin2Gray(Gray2Bin(A) + 1) when rising_edge(clk); >>>> D <= CalcGray(C, '1') when rising_edge(clk); >>>> end Behavioral; >>> >>> Thanks. What about Bin2Gray? I'd like to try your code in my >>> synthesis. >>> >>> In general, I don't find optimization to work all that well for many >>> functions. It can work ok for smaller code sections, so maybe this is >>> one that happens to do well with many synthesizers, or maybe the >>> description you use turns out to be optimal in spite of the apparent >>> simplicity of the description I used. For example, your code above >>> would use an adder chain along with the explicit chain described in >>> Gray2Bin (don't know about Bin2Gray) while my code has two explicit >>> chains. This could be simpler since the adder carry chain is embedded >>> in the logic elements in most FPGA families. >>> >>> I've wondered just how much complexity the exit in the second loop adds. >>> Coding without the exit might simplify the logic. >>> >>> -- >>> >>> Rick C >> >> function Bin2Gray (Bin : in STD_LOGIC_VECTOR) return >> STD_LOGIC_VECTOR is >> variable Gray_var : STD_LOGIC_VECTOR(Bin'range); >> begin >> Gray_var(Gray_var'high) := Bin(bin'high); >> for i in 0 to bin'high - 1 loop >> Gray_var(i) := Bin(i) xor Bin(i + 1); >> end loop; >> return Gray_var; >> end function Bin2Gray; >> >> function Bin2Gray (Bin : in unsigned) return unsigned is >> begin >> return unsigned(Bin2Gray(std_logic_vector(Bin))); >> end function Bin2Gray; >> >> >> function Gray2Bin (Gray : in STD_LOGIC_VECTOR) return >> STD_LOGIC_VECTOR is >> variable Bin_var : STD_LOGIC_VECTOR(Gray'range); >> begin >> Bin_var := (others => '0'); >> Bin_var(Gray'high) := Gray(Gray'high); >> for i in Gray'high-1 downto 0 loop >> Bin_var(i):= Bin_var(i+1) xor Gray(i); >> end loop; >> return Bin_var; >> end function Gray2Bin; >> >> function Gray2Bin (Gray : in unsigned) return unsigned is >> begin >> return unsigned(Gray2Bin(std_logic_vector(Gray))); >> end function Gray2Bin; > > Nice illustrations of these algorithms. > > http://ncalculators.com/digital-computation/binary-gray-code-converter.htm I came across this thread by accident yesterday when my news reader hiccuped and marked all threads in this group as unread. On reviewing all the info and finding a couple of new web pages with good presentations of the problem I see why only one chain is needed. The extra bit added as the new lsb is in essence the parity bit. It changes on every clock and the single rule of, flip the bit to the left of the rightmost set bit unless that rightmost set bit is the msb in which case the msb is flipped, covers the full operation of the gray code bits. So directly incrementing the gray code is likely to be faster and simpler than converting to binary, incrementing and converting back. This method needs only one chain since the parity is not calculated by a word wide function. I will have to check which is better... and I need to reread this thread fully to make sure this hasn't been done already... after the holidays I think. BTW, why can hiccuped be spelled with only 1 'p'? -- Rick C From newsfish@newsfish Thu Aug 1 00:38:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Gray Code Date: Wed, 11 Jan 2017 05:52:07 -0500 Organization: A noiseless patient Spider Lines: 61 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 11 Jan 2017 10:50:31 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="003b5b518c77bd724d2eb22d69373699"; logging-data="10516"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ux4lYor82YMRY/hOGzqxJ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 In-Reply-To: Cancel-Lock: sha1:hLWHyvlTrKGTMa9Dw/nXaqI8hrc= Xref: news.eternal-september.org comp.lang.vhdl:4646 I spent some time on this and got my head around it finally. I would like to point out that the set of gray codes typically used are reflected binary codes and are just one type of gray codes. They are easy to work with in conversion routines. Converting binary to gray only requires searching for all changes of bit value in adjacent bits. In the binary word a bit pair where the value is different, the rightmost bit in the gray word will be a '1'. So the logic is just an XOR gate for each output bit other than the msb which doesn't change. If you are going to use the gray code to increment or decrement directly, having the parity bit will simplify the logic greatly so this is also calculated easily by inverting the binary lsb. The gray to binary conversion is similar, but requires the calculation of the msb first which is then used to XOR with the next gray bit to obtain that binary bit. This is just the reverse of the process to create the gray word from the binary word. However, this results in a chain calculation from msb to lsb. If a gray word needs to be incremented or decremented the process is also not complex. If you consider how a gray code is generated from binary and how incrementing works for binary, you will see the only change in a gray word is defined by either the lsb changing or the bit defined by the ripple carry will change. When the parity of the gray word is even, the lsb of the binary word is zero and so the lsb in the binary word will change from a zero to a one and the *only* bit to change. So likewise, the lsb in the gray word will change. Otherwise, when the binary lsb is a one (odd parity in the gray word) the ones are followed and the first zero bit will become a one with all the lower bits becoming zeros. Looking at the binary to gray conversion rules you'll see the bit that then changes is the first bit to the left of the series of one bits or in the gray word the bit to the left of the first one bit from the lsb end. This sets up a chain of checking for all zeros from the lsb up in the gray word. This is simple logic and potentially can make use of a ripple carry chain. Decrementing the gray code is exactly the same, but the polarity of the parity bit is inverted. A gray up/down counter only requires the parity be inverted by the direction bit. When these algorithms were synthesized using Lattice Diamond/Synplify Pro for an N bit word N-1 LUTs were used for the two conversions, binary to gray and gray to binary. For incrementing or decrementing it used 22 LUTs for a 16 bit counter, 16 for the final calculation of each bit and six chained LUTs to help calculate the cascade of zeros. Adding a signal to control the up/down mode increases the LUT count by one to 23. A funny thing though. When I modified the logic so instead of passing the signals in and out of the chip to a counter that simply starts at zeero and counts up/down, the logic blew up to using 51 LUTs. No change to the logic, simply routing the output of the FF back to the input to the incrementer. If I set the speed target to just 10 MHz the LUT counts dropped back too the above numbers. The speed did drop off a lot from over 200 MHz to a bit over 100 MHz. I suppose the big increase in LUTs got rid of the chain calculation. I wonder what it takes to get the tools to use a carry chain? -- Rick C From newsfish@newsfish Thu Aug 1 00:38:11 2024 X-Received: by 10.99.36.130 with SMTP id k124mr2828286pgk.25.1484845609722; Thu, 19 Jan 2017 09:06:49 -0800 (PST) X-Received: by 10.157.1.117 with SMTP id 108mr1093710otu.16.1484845609638; Thu, 19 Jan 2017 09:06:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r185no539799ita.0!news-out.google.com!78ni9459itm.0!nntp.google.com!r185no529102ita.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Jan 2017 09:06:49 -0800 (PST) In-Reply-To: <5189d4eb-3ca2-4b4a-b8a6-fdba20908662@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=131.94.186.20; posting-account=hdZLAwoAAADxjEU4F5YYKIEt8OvQFINS NNTP-Posting-Host: 131.94.186.20 References: <5189d4eb-3ca2-4b4a-b8a6-fdba20908662@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <593f15c8-9b68-4337-b7f0-647dcd548ed3@googlegroups.com> Subject: Re: Viterbi Decoder in VHDL From: Enes Erdin Injection-Date: Thu, 19 Jan 2017 17:06:49 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4647 On Saturday, November 19, 2016 at 11:12:05 AM UTC-5, azarudee...@gmail.com wrote: > hi sir, > i am also doing a project in viterbi decoder of convolutional codes in VHDL. > constraint length k=3.code rate=1/2.i am now having some design problems in decoder side so if u have any coding in VHDL ping me at azarudeentheboss@gmail.com thank you I designed a turbo decoder in VHDL in 2008. From newsfish@newsfish Thu Aug 1 00:38:11 2024 X-Received: by 10.107.135.92 with SMTP id j89mr6795355iod.94.1487568294330; Sun, 19 Feb 2017 21:24:54 -0800 (PST) X-Received: by 10.157.56.117 with SMTP id r50mr1326548otd.12.1487568294264; Sun, 19 Feb 2017 21:24:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!e137no1643048itc.0!news-out.google.com!15ni1830itm.0!nntp.google.com!e137no1643042itc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 19 Feb 2017 21:24:54 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.139.223.167; posting-account=VguK8QoAAABNYej9L-tC_JYfbdZFzjds NNTP-Posting-Host: 14.139.223.167 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: instructor solution manual for Wireless Communications (Andrea Goldsmith) From: chandrajeetkumarnanda@gmail.com Injection-Date: Mon, 20 Feb 2017 05:24:54 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4648 i need solution manual of Wireless Communication By Andrea Goldsmith From newsfish@newsfish Thu Aug 1 00:38:12 2024 X-Received: by 10.98.139.154 with SMTP id e26mr1200304pfl.30.1487970876308; Fri, 24 Feb 2017 13:14:36 -0800 (PST) X-Received: by 10.157.68.226 with SMTP id p34mr392766otg.8.1487970876132; Fri, 24 Feb 2017 13:14:36 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!e137no873541itc.0!news-out.google.com!15ni3152itm.0!nntp.google.com!e137no873537itc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Feb 2017 13:14:35 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.43.3.237; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.43.3.237 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <38e31904-27fe-402a-b215-490cc205ee65@googlegroups.com> Subject: Ballot Invitation for VHDL Standard (IEEE 1076) From: Jim Lewis Injection-Date: Fri, 24 Feb 2017 21:14:36 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.vhdl:4649 Hi, Below are the instructions to signup to ballot on 1076-2017 More about the 1076 WG see: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/MeetingMinutes http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/CollectedRequirements Best Regards, Jim Lewis IEEE 1076 (VHDL) Working Group Chair SynthWorks Director of Training OSVVM co-founder and chief architect ***** ENROLLMENT INSTRUCTIONS ***** Go directly to: https://development.standards.ieee.org/my-site/open-ballot-invitations Or, follow this process: 1. Log onto myProject; click the link for myBallot. 2. Click the link for myBallot Control Panel (if applicable); click the link for "Show/Join Open Ballot Invitations": https://development.standards.ieee.org/my-site/open-ballot-invitations 3. Scroll down until you find the open ballot group of interest to you; then scroll over to the right margin and click ?join? under the ?Actions? column. 4. Select a classification category and click ?OK? at the bottom of the screen. You will receive an on-screen confirmation that you successfully joined the group. If you are not an IEEE SA Member, you can either enroll in a single ballot by paying a per-ballot fee or you can join the IEEE SA by choosing an option link below. Joining the IEEE SA entitles you to participate in as many sponsor ballots as you like for the year. OPTION 1 - I am already an IEEE Member and I want to add Standards Association Membership. Go to: https://myieeemembership.ieee.org/renewal/RenewalLogin OPTION 2 - I am not an IEEE Member but would like to enroll in both IEEE and IEEE Standards Association. Go to: https://webapps2.ieee.org/member/Member OPTION 3 - I am not interested in becoming an IEEE Member, however I would like to enroll as a Standards Association Member only. Go to: http://standards.ieee.org/sa-mem/join.html ============================================ OBLIGATIONS AND RESPONSIBILITIES OF BALLOTERS ============================================ Balloting group members are selected to vote on the acceptability of a new or revised standard, or on the reaffirmation of a published standard submitted by the Sponsor; based on interest in and commitment to reviewing and voting on a specific existing or proposed standard. Once the document is ready to be balloted, you will receive notification via email. You will typically have 30 days to review the document and return the ballot with your vote. By agreeing to participate in this ballot you have an *obligation* to respond. Failure to return a completed ballot may disqualify you from participating in future ballots. From newsfish@newsfish Thu Aug 1 00:43:09 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.fcku.it!peer04.fr7!futter-mich.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!post02.iad.highwinds-media.com!fx43.iad.POSTED!not-for-mail From: floffy Newsgroups: comp.lang.vhdl Subject: test Message-ID: X-Newsreader: Forte Agent 1.93/32.576 English (American) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Distribution: mccarragher.org Lines: 2 X-Server: news.mccarragher.org Feed: Full Feed Text Only Peering: Peering Available USENET: FREE access to usenet X-Complaints-To: abuse@frugalusenet.com NNTP-Posting-Date: Mon, 01 May 2017 21:35:29 UTC Organization: frugalusenet - www.frugalusenet.com Date: 1 May 2017 17:35:17 -0500 X-Received-Body-CRC: 1861973413 X-Received-Bytes: 831 Xref: news.eternal-september.org comp.lang.vhdl:9165 test From newsfish@newsfish Thu Aug 1 00:43:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: test Date: Tue, 2 May 2017 10:47:33 -0400 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 2 May 2017 14:44:21 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="79fed166db58261cece25c9a08cf046c"; logging-data="25079"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX188sKtuLjDjZlrbOnjskgxT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 In-Reply-To: Cancel-Lock: sha1:mtOIlQclmWWsxqQNla5eu/fsMug= Xref: news.eternal-september.org comp.lang.vhdl:9166 On 5/1/2017 6:35 PM, floffy wrote: > test Did it pass? -- Rick C From newsfish@newsfish Thu Aug 1 00:43:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: SciTE Editor for VHDL Date: Tue, 9 May 2017 23:25:13 -0400 Organization: A noiseless patient Spider Lines: 9 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 10 May 2017 03:21:56 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="8acfff0272a4368c4da705b43ced92ff"; logging-data="7059"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19aBBF3Nzv0AedRIk7pspo/" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:w1itPq169i8IN2rLYqHHzw9d5sQ= Xref: news.eternal-september.org comp.lang.vhdl:9167 I am giving the SciTE editor a try. I don't see it treating VHDL files as anything other than text. In various places I see that VHDL is allegedly supported, but I can't figure out how this works. Any thoughts? -- Rick C From newsfish@newsfish Thu Aug 1 00:43:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Re: SciTE Editor for VHDL Date: Wed, 10 May 2017 14:23:29 +0200 Lines: 10 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net P5aH3KjMKB5EEpY665zLnQp7EuslDD64IBs+ZvY1TwDijgljM= Cancel-Lock: sha1:F1HWGzQsh98nLs65F5mJwzJxIZ8= User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:9168 Am 10.05.2017 um 05:25 schrieb rickman: > I am giving the SciTE editor a try. I don't see it treating VHDL files > as anything other than text. In various places I see that VHDL is > allegedly supported, but I can't figure out how this works. Remove the 'vhdl' entry from the imports.exclude section in SciTEglobal.properties. Thomas From newsfish@newsfish Thu Aug 1 00:43:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: SciTE Editor for VHDL Date: Wed, 10 May 2017 09:30:37 -0700 Organization: A noiseless patient Spider Lines: 23 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 10 May 2017 16:27:21 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="d02835556df7bd93ef97851c36e7efa4"; logging-data="19924"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18QpNVb8DL+yzqs4LIFdpYw" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 In-Reply-To: Cancel-Lock: sha1:T9T6cVOijlWf4dlbnnpjFzjtf9o= Xref: news.eternal-september.org comp.lang.vhdl:9169 On 05/10/2017 05:23 AM, Thomas Heller wrote: > Am 10.05.2017 um 05:25 schrieb rickman: >> I am giving the SciTE editor a try. I don't see it treating VHDL files >> as anything other than text. In various places I see that VHDL is >> allegedly supported, but I can't figure out how this works. > > Remove the 'vhdl' entry from the imports.exclude section in > SciTEglobal.properties. > > Thomas > I'll also say, I tried SciTE for a while and didn't love it. It wraps the same Scintilla backend that both Notepad++ (Windows only) and Geany (cross platform and my current editor of choice) do, but in a very "I am just a tutorial on how to use this" kind of way. Not to restart the editor wars (M-0 C-k), but if SciTE is holding appeal for you then you should give Geany a look. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:43:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: SciTE Editor for VHDL Date: Wed, 10 May 2017 12:38:35 -0400 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 10 May 2017 16:35:17 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="8acfff0272a4368c4da705b43ced92ff"; logging-data="20952"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+HkMwgRps6xYdy78ndY/Ee" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 In-Reply-To: Cancel-Lock: sha1:NbfdgScIREZLouZQjO4FUJsDjBk= Xref: news.eternal-september.org comp.lang.vhdl:9170 On 5/10/2017 12:30 PM, Rob Gaddi wrote: > On 05/10/2017 05:23 AM, Thomas Heller wrote: >> Am 10.05.2017 um 05:25 schrieb rickman: >>> I am giving the SciTE editor a try. I don't see it treating VHDL files >>> as anything other than text. In various places I see that VHDL is >>> allegedly supported, but I can't figure out how this works. >> >> Remove the 'vhdl' entry from the imports.exclude section in >> SciTEglobal.properties. >> >> Thomas >> > > I'll also say, I tried SciTE for a while and didn't love it. It wraps > the same Scintilla backend that both Notepad++ (Windows only) and Geany > (cross platform and my current editor of choice) do, but in a very "I am > just a tutorial on how to use this" kind of way. > > Not to restart the editor wars (M-0 C-k), but if SciTE is holding appeal > for you then you should give Geany a look. I'm not going anywhere until I figure out how to use this damn thing. Right now I am fighting the fonts. The default font is proportional and so is not suitable for code. I can't figure out how to tell it to use a monospaced font by default. The font selected by the monospaced option in the menu is not as clear to me (I don't have great vision) and I can't figure out how to change that. I really can't find much documentation that actually explains how to use the damn thing!!! -- Rick C From newsfish@newsfish Thu Aug 1 00:43:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Valentin Tihhomirov Newsgroups: comp.lang.vhdl Subject: Entity instantiation in GHDL Date: Sat, 13 May 2017 14:26:53 +0300 Organization: A noiseless patient Spider Lines: 16 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 13 May 2017 11:23:37 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0d471521c312a7fc8c2e1fd1bf5ae622"; logging-data="5839"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/r0B9KOAyTPweZ9+WLM1G4o6mJWWgwxVw=" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:17.0) Gecko/20130215 Thunderbird/17.0.3 Cancel-Lock: sha1:mfaxr6NSpVrdsVWIuCTi00PoIHg= Xref: news.eternal-september.org comp.lang.vhdl:9171 GHDL gives an example of adder instantiation, using components adder_0: adder port map (i0 => i0, i1 => i1, ci => ci, s => s, co => co); which works. I tried to get rid of the component, making direct instantiation of the entity adder_0: entity adder port map (i0 => i0, i1 => i1, ci => ci, s => s, co => co); But, it says > no declaration for "adder" What is wrong? From newsfish@newsfish Thu Aug 1 00:43:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Valentin Tihhomirov Newsgroups: comp.lang.vhdl Subject: Re: Entity instantiation in GHDL Date: Sat, 13 May 2017 15:30:34 +0300 Organization: A noiseless patient Spider Lines: 5 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 13 May 2017 12:27:17 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0d471521c312a7fc8c2e1fd1bf5ae622"; logging-data="18164"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+nYib6XOIj/w9O8+OnoreNEFzF/xlT7Lc=" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:17.0) Gecko/20130215 Thunderbird/17.0.3 In-Reply-To: Cancel-Lock: sha1:RqTDN7n/wMgw1i8AfwtTblskzPY= Xref: news.eternal-september.org comp.lang.vhdl:9172 > What is wrong? It is configuration spec that caused the error actually. Excuse me for the fuss. From newsfish@newsfish Thu Aug 1 00:43:12 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Same syntax for variable and signal update Date: Fri, 9 Jun 2017 12:25:46 -0700 Organization: A noiseless patient Spider Lines: 44 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 9 Jun 2017 19:22:14 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f9ff9e51f04cd96d2920965ec67618df"; logging-data="3635"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18/UwWtdlIoWVRknk2nS4Ch" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 Content-Language: en-US X-Mozilla-News-Host: snews://news.eternal-september.org:563 Cancel-Lock: sha1:0x4R3BLpx3dQJmE8hVg+6ozXzOw= Xref: news.eternal-september.org comp.lang.vhdl:9173 So I'm writing code generating code and running into a thing that's syntactically icky. procedure UPDATE_REGISTER( dat : in std_logic_vector; variable reg: inout fancytype) is begin reg := UPDATE_FANCYDATA(dat, reg); end procedure UPDATE_REGISTER; procedure UPDATE_REGISTER_SIG( dat : in std_logic_vector; signal reg: inout fancytype) is begin reg <= UPDATE_FANCYDATA(dat, reg)); end procedure UPDATE_REGISTER_SIG; As far as I understand it (and please someone correct me if I'm wrong) those procedures need different definitions because I need to use the current update semantics. And I need to use different names for them even because you can't differentiate subprogram overloads by nothing but class. Does anyone have a better way of doing this? Ultimately this is going to be working on single elements at a time of large composites, and so I don't like the simulation performance implications of something like: signal sreg : fancytype; ... process: variable vreg : fancytype; begin wait until rising_edge(clk); vreg := sreg; UPDATE_REGISTER(vreg); sreg <= vreg; end process; Anyone have a more elegant solution? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:43:12 2024 X-Received: by 10.157.83.42 with SMTP id g42mr7011165oth.81.1497658809611; Fri, 16 Jun 2017 17:20:09 -0700 (PDT) X-Received: by 10.157.43.235 with SMTP id u98mr363123ota.9.1497658809573; Fri, 16 Jun 2017 17:20:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!185no1174246itv.0!news-out.google.com!k7ni3199itk.0!nntp.google.com!185no1174242itv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Jun 2017 17:20:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.47.82.47; posting-account=5-Vq2QoAAADoME7UK53LBXuWUWp3jubN NNTP-Posting-Host: 24.47.82.47 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: create 400 clocks delay for a signal From: rejohnson.fpga.design@gmail.com Injection-Date: Sat, 17 Jun 2017 00:20:09 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9174 I would use a dual-port RAM ...say 512 x 1-bit. The DP RAM will have separa= te write and read address ports, as well as a 1-bit data input and 1-bit da= ta output ports. The idea is to use an additional counter to generate a seq= uence of write address. The counter would be designed to roll-over to "0000= 00000" after it reaches "110001111" (399 decimal). Use a comparator to gene= rate a "the count is equal or greater than" signal which would connect to t= he Synchronous Reset input. It takes less logic to look for an equal or gre= ater-than signal, than to look for an exact match. Now use a subtract function subtract 400 from the Write Address and use thi= s as the read address. The contraption will write to an address, then 400 c= lock cycles later it will read the contents of that address. Since writing, comparing, subtracting, and reading all take some clock cycl= es themselves, the compare value may have to be adjusted to account for the= se. This is similar to how "back in the day" shift registers actually shifted t= he data through registers. This is what you were trying to do. It is wastef= ul of registers, especially 400 of them. Now-a-days, the write and read add= resses are finagled instead.=20 best - Robert On Thursday, August 28, 2003 at 5:07:32 PM UTC-4, john wrote: > Help wanted, thank you in advance; >=20 > I have two signals, > signal a: std_logic ; =20 > signal b: std_logic ; >=20 > I try to delay "a " 400 clocks , then send to "b", > I use=20 > a <=3D b after 400 clocks time; > I put the above code into my project, then download to the > FPGA(XC2v3000), the result is wrong, >=20 > then I use the "D" flip flop > signal a: std_logic ; =20 > signal b: std_logic ; > signal temp1:std_logic ; > ..... > signal temp399:std_logic ; >=20 >=20 > delay : process (CLK) > if( CLK'event and CLK =3D '1' ) then > temp1<=3Da; > temp2<=3Dtemp1; > ....... > b<=3Dtemp399; > end process; > then my project runs correctly on the FPGA chip, > I think there is a smart way to write(maybe use loop?) > temp1<=3Da; > temp2<=3Dtemp1; > ....... > b<=3Dtemp399; > currently I use 400 lines in my code, I am novice in FPGA, I have no > idea how to simplify the code. > thanks From newsfish@newsfish Thu Aug 1 00:43:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Fri, 16 Jun 2017 20:59:30 -0400 Organization: A noiseless patient Spider Lines: 61 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Jun 2017 00:56:01 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="825db10b58f98d6e0a01e17f76246470"; logging-data="3386"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18fpPilNZhosGeJhE7O2HQI" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 In-Reply-To: Content-Language: en-US Cancel-Lock: sha1:TRe+UGOxfpwmIxoLNNWvvaeRyzk= Xref: news.eternal-september.org comp.lang.vhdl:9175 On Friday, 6/16/2017 8:20 PM, rejohnson.fpga.design@gmail.com wrote: > I would use a dual-port RAM ...say 512 x 1-bit. The DP RAM will have separate write and read address ports, as well as a 1-bit data input and 1-bit data output ports. The idea is to use an additional counter to generate a sequence of write address. The counter would be designed to roll-over to "000000000" after it reaches "110001111" (399 decimal). Use a comparator to generate a "the count is equal or greater than" signal which would connect to the Synchronous Reset input. It takes less logic to look for an equal or greater-than signal, than to look for an exact match. > > Now use a subtract function subtract 400 from the Write Address and use this as the read address. The contraption will write to an address, then 400 clock cycles later it will read the contents of that address. > > Since writing, comparing, subtracting, and reading all take some clock cycles themselves, the compare value may have to be adjusted to account for these. > > This is similar to how "back in the day" shift registers actually shifted the data through registers. This is what you were trying to do. It is wasteful of registers, especially 400 of them. Now-a-days, the write and read addresses are finagled instead. > > best - Robert > > > On Thursday, August 28, 2003 at 5:07:32 PM UTC-4, john wrote: >> Help wanted, thank you in advance; >> >> I have two signals, >> signal a: std_logic ; >> signal b: std_logic ; >> >> I try to delay "a " 400 clocks , then send to "b", >> I use >> a <= b after 400 clocks time; >> I put the above code into my project, then download to the >> FPGA(XC2v3000), the result is wrong, >> >> then I use the "D" flip flop >> signal a: std_logic ; >> signal b: std_logic ; >> signal temp1:std_logic ; >> ..... >> signal temp399:std_logic ; >> >> >> delay : process (CLK) >> if( CLK'event and CLK = '1' ) then >> temp1<=a; >> temp2<=temp1; >> ....... >> b<=temp399; >> end process; >> then my project runs correctly on the FPGA chip, >> I think there is a smart way to write(maybe use loop?) >> temp1<=a; >> temp2<=temp1; >> ....... >> b<=temp399; >> currently I use 400 lines in my code, I am novice in FPGA, I have no >> idea how to simplify the code. >> thanks > You're responding to a 14-year-old post. However for a fixed delay using block RAM (at least for Xilinx) you don't need separate read and write address. In read-before-write mode, you get the data from a cell just before it is written. Then setting the delay is simply a matter of deciding where you wrap the count. This can be done in single-port mode. -- Gabor From newsfish@newsfish Thu Aug 1 00:43:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Sat, 17 Jun 2017 03:30:57 -0400 Organization: A noiseless patient Spider Lines: 83 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Jun 2017 07:27:17 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="66a9f7fad8b128829f9e03f9d113c850"; logging-data="23429"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18rFS+Xr7UQ4ZmYkDWWfyYV" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:49.0) Gecko/20100101 Firefox/49.0 SeaMonkey/2.46 In-Reply-To: Cancel-Lock: sha1:xsZ9qotkUTdrV2seeLHnsjpXd/g= Xref: news.eternal-september.org comp.lang.vhdl:9176 Gabor wrote on 6/16/2017 8:59 PM: > On Friday, 6/16/2017 8:20 PM, rejohnson.fpga.design@gmail.com wrote: >> I would use a dual-port RAM ...say 512 x 1-bit. The DP RAM will have >> separate write and read address ports, as well as a 1-bit data input and >> 1-bit data output ports. The idea is to use an additional counter to >> generate a sequence of write address. The counter would be designed to >> roll-over to "000000000" after it reaches "110001111" (399 decimal). Use a >> comparator to generate a "the count is equal or greater than" signal which >> would connect to the Synchronous Reset input. It takes less logic to look >> for an equal or greater-than signal, than to look for an exact match. >> >> Now use a subtract function subtract 400 from the Write Address and use >> this as the read address. The contraption will write to an address, then >> 400 clock cycles later it will read the contents of that address. >> >> Since writing, comparing, subtracting, and reading all take some clock >> cycles themselves, the compare value may have to be adjusted to account >> for these. >> >> This is similar to how "back in the day" shift registers actually shifted >> the data through registers. This is what you were trying to do. It is >> wasteful of registers, especially 400 of them. Now-a-days, the write and >> read addresses are finagled instead. >> >> best - Robert >> >> >> On Thursday, August 28, 2003 at 5:07:32 PM UTC-4, john wrote: >>> Help wanted, thank you in advance; >>> >>> I have two signals, >>> signal a: std_logic ; >>> signal b: std_logic ; >>> >>> I try to delay "a " 400 clocks , then send to "b", >>> I use >>> a <= b after 400 clocks time; >>> I put the above code into my project, then download to the >>> FPGA(XC2v3000), the result is wrong, >>> >>> then I use the "D" flip flop >>> signal a: std_logic ; >>> signal b: std_logic ; >>> signal temp1:std_logic ; >>> ..... >>> signal temp399:std_logic ; >>> >>> >>> delay : process (CLK) >>> if( CLK'event and CLK = '1' ) then >>> temp1<=a; >>> temp2<=temp1; >>> ....... >>> b<=temp399; >>> end process; >>> then my project runs correctly on the FPGA chip, >>> I think there is a smart way to write(maybe use loop?) >>> temp1<=a; >>> temp2<=temp1; >>> ....... >>> b<=temp399; >>> currently I use 400 lines in my code, I am novice in FPGA, I have no >>> idea how to simplify the code. >>> thanks >> > > You're responding to a 14-year-old post. However for a fixed delay > using block RAM (at least for Xilinx) you don't need separate read > and write address. In read-before-write mode, you get the data from > a cell just before it is written. Then setting the delay is simply > a matter of deciding where you wrap the count. This can be done in > single-port mode. Additionally, I would point out that the counter can be implemented more efficiently by coding it as a loadable, down counter. You can code it so the carry chain is used to detect the zero condition (next value will be less than zero) and load the max counter value, 399 in this case. The load control and directly load inputs will fit in the same LUTs as the down counter in most FPGA families. Very efficient and very fast. -- Rick C From newsfish@newsfish Thu Aug 1 00:43:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Sat, 17 Jun 2017 10:25:46 -0700 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Jun 2017 17:22:09 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3b1dc75652eb2c20b80bffd856aebcd7"; logging-data="7504"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/PagO8jDnDhfeYRaN95koE7zPituaXkbY=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:ug9VY9yEoTB1eDtjmOFQwS0OlxI= Xref: news.eternal-september.org comp.lang.vhdl:9177 On 2017-06-17 00:30, rickman wrote: > Additionally, I would point out that the counter can be implemented more > efficiently by coding it as a loadable, down counter. You can code it > so the carry chain is used to detect the zero condition (next value will > be less than zero) and load the max counter value, 399 in this case. > The load control and directly load inputs will fit in the same LUTs as > the down counter in most FPGA families. Very efficient and very fast. > Or, based on my ASIC mindset, I would code it like this: signal a : std_logic; signal b : std_logic; signal q : std_logic_vector(0 to 399); begin delay : process (CLK) if( CLK'event and CLK = '1' ) then q <= a & q(0 to 398); end if; end process; b <= q(399); From newsfish@newsfish Thu Aug 1 00:43:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Sat, 17 Jun 2017 14:08:39 -0400 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Jun 2017 18:04:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="66a9f7fad8b128829f9e03f9d113c850"; logging-data="16346"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/gEK9Cgi7Qj+7skqURXv5E" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:49.0) Gecko/20100101 Firefox/49.0 SeaMonkey/2.46 In-Reply-To: Cancel-Lock: sha1:bdyLt6HTJbcvw/F7EZ1/8N30CCc= Xref: news.eternal-september.org comp.lang.vhdl:9178 Charles Bailey wrote on 6/17/2017 1:25 PM: > On 2017-06-17 00:30, rickman wrote: >> Additionally, I would point out that the counter can be implemented more >> efficiently by coding it as a loadable, down counter. You can code it >> so the carry chain is used to detect the zero condition (next value will >> be less than zero) and load the max counter value, 399 in this case. >> The load control and directly load inputs will fit in the same LUTs as >> the down counter in most FPGA families. Very efficient and very fast. >> > Or, based on my ASIC mindset, I would code it like this: > signal a : std_logic; > signal b : std_logic; > signal q : std_logic_vector(0 to 399); > > begin > delay : process (CLK) > if( CLK'event and CLK = '1' ) then > q <= a & q(0 to 398); > end if; > end process; > b <= q(399); This appears to be using 400 registers as an actual shift register, no? I suppose shift registers (which don't need the output multiplexer) could be more efficient than block RAM in an ASIC. I'm curious, why do you still use the notation above for a clock edge rather than rising_edge(CLK)? Normally this is only seen in students being taught by teachers who aren't versed in modern methods. -- Rick C From newsfish@newsfish Thu Aug 1 00:43:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Sat, 17 Jun 2017 15:46:01 -0700 Organization: A noiseless patient Spider Lines: 42 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Jun 2017 22:42:26 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f31daa49d494756362a37df8414146dc"; logging-data="8110"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/lYB5RXlk2IDiJ4cToICAdRBEKGYLBduk=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:pwHbnIE/Xg3+v/xMlH053eNy60g= Xref: news.eternal-september.org comp.lang.vhdl:9179 On 2017-06-17 11:08, rickman wrote: > Charles Bailey wrote on 6/17/2017 1:25 PM: >> On 2017-06-17 00:30, rickman wrote: >>> Additionally, I would point out that the counter can be implemented more >>> efficiently by coding it as a loadable, down counter. You can code it >>> so the carry chain is used to detect the zero condition (next value will >>> be less than zero) and load the max counter value, 399 in this case. >>> The load control and directly load inputs will fit in the same LUTs as >>> the down counter in most FPGA families. Very efficient and very fast. >>> >> Or, based on my ASIC mindset, I would code it like this: >> signal a : std_logic; >> signal b : std_logic; >> signal q : std_logic_vector(0 to 399); >> >> begin >> delay : process (CLK) >> if( CLK'event and CLK = '1' ) then >> q <= a & q(0 to 398); >> end if; >> end process; >> b <= q(399); > > This appears to be using 400 registers as an actual shift register, no? > I suppose shift registers (which don't need the output multiplexer) > could be more efficient than block RAM in an ASIC. > > I'm curious, why do you still use the notation above for a clock edge > rather than rising_edge(CLK)? Normally this is only seen in students > being taught by teachers who aren't versed in modern methods. > No particular reason. It's a very common way of specifying the clock for sequential logic. For all practical purposes, for both simulation and synthesis, it's equivalent to rising_edge(CLK). In some ways, I tend to prefer this coding style: delay : process wait until CLK = '1'; q <= a & q(0 to 398); end process; because it's simpler and more compact. From newsfish@newsfish Thu Aug 1 00:43:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!feeder.usenetexpress.com!feeder1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: create 400 clocks delay for a signal Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 18 Jun 2017 05:07:33 GMT Lines: 50 Message-ID: <59460a95$0$1503$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 30fdea7d.news.astraweb.com X-Trace: DXC=3`nReQ8P\GMo;ii5o?B_6AL?0kYOcDh@Jo4f23ged[eH\>T:^Al174HHI6bY5_;LhIRU[X2G?9@POcln^W;VXlFL=FjL:S On 2017-06-17 11:08, rickman wrote: >> Charles Bailey wrote on 6/17/2017 1:25 PM: >>> On 2017-06-17 00:30, rickman wrote: >>>> Additionally, I would point out that the counter can be implemented >>>> more efficiently by coding it as a loadable, down counter. You can >>>> code it so the carry chain is used to detect the zero condition (next >>>> value will be less than zero) and load the max counter value, 399 in >>>> this case. The load control and directly load inputs will fit in the >>>> same LUTs as the down counter in most FPGA families. Very efficient >>>> and very fast. >>>> >>> Or, based on my ASIC mindset, I would code it like this: >>> signal a : std_logic; >>> signal b : std_logic; >>> signal q : std_logic_vector(0 to 399); >>> >>> begin delay : process (CLK) >>> if( CLK'event and CLK = '1' ) then >>> q <= a & q(0 to 398); >>> end if; >>> end process; >>> b <= q(399); >> >> This appears to be using 400 registers as an actual shift register, no? >> I suppose shift registers (which don't need the output multiplexer) >> could be more efficient than block RAM in an ASIC. >> >> I'm curious, why do you still use the notation above for a clock edge >> rather than rising_edge(CLK)? Normally this is only seen in students >> being taught by teachers who aren't versed in modern methods. >> > No particular reason. It's a very common way of specifying the clock > for sequential logic. For all practical purposes, for both simulation > and synthesis, it's equivalent to rising_edge(CLK). > > In some ways, I tend to prefer this coding style: > delay : process > wait until CLK = '1'; > q <= a & q(0 to 398); > end process; > > because it's simpler and more compact. I used to specify clocked logic like that last century. I got over it. Regards, Allan From newsfish@newsfish Thu Aug 1 00:43:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Sun, 18 Jun 2017 23:59:59 -0400 Organization: A noiseless patient Spider Lines: 62 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 19 Jun 2017 03:56:20 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="bba7b7fba8cea3498bf0a4ea1c483a80"; logging-data="9298"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Upx41NkGvtSj/+0D2eG5u" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:49.0) Gecko/20100101 Firefox/49.0 SeaMonkey/2.46 In-Reply-To: Cancel-Lock: sha1:TKVVR9+Ke0xfpP49TUXNzxUzSx8= Xref: news.eternal-september.org comp.lang.vhdl:9181 Charles Bailey wrote on 6/17/2017 6:46 PM: > On 2017-06-17 11:08, rickman wrote: >> Charles Bailey wrote on 6/17/2017 1:25 PM: >>> On 2017-06-17 00:30, rickman wrote: >>>> Additionally, I would point out that the counter can be implemented more >>>> efficiently by coding it as a loadable, down counter. You can code it >>>> so the carry chain is used to detect the zero condition (next value will >>>> be less than zero) and load the max counter value, 399 in this case. >>>> The load control and directly load inputs will fit in the same LUTs as >>>> the down counter in most FPGA families. Very efficient and very fast. >>>> >>> Or, based on my ASIC mindset, I would code it like this: >>> signal a : std_logic; >>> signal b : std_logic; >>> signal q : std_logic_vector(0 to 399); >>> >>> begin >>> delay : process (CLK) >>> if( CLK'event and CLK = '1' ) then >>> q <= a & q(0 to 398); >>> end if; >>> end process; >>> b <= q(399); >> >> This appears to be using 400 registers as an actual shift register, no? >> I suppose shift registers (which don't need the output multiplexer) >> could be more efficient than block RAM in an ASIC. >> >> I'm curious, why do you still use the notation above for a clock edge >> rather than rising_edge(CLK)? Normally this is only seen in students >> being taught by teachers who aren't versed in modern methods. >> > No particular reason. It's a very common way of specifying the clock for > sequential logic. For all practical purposes, for both simulation and > synthesis, it's equivalent to rising_edge(CLK). > > In some ways, I tend to prefer this coding style: > delay : process > wait until CLK = '1'; > q <= a & q(0 to 398); > end process; > > because it's simpler and more compact. I'm very surprised this works. Is there something about this notation that implies a sensitivity list including CLK? It's been too long since I've studied the rules of VHDL and this is syntax I just don't use. If there is not an implied wait for CLK to change, this won't work. When CLK changes to '1' it will trigger correctly, but as soon as the process exits CLK will still be '1' and will retrigger. So there must be an implied sensitivity list with CLK to wait for a change in CLK, just like the CLK'event in the other syntax. The underlying rules of VHDL are indeed complex. That is why I learned them once, found basic forms that did what I want to do and don't deviate. Then I know my stuff will work without needing to always dig down to the underlying complex rules. -- Rick C From newsfish@newsfish Thu Aug 1 00:43:15 2024 X-Received: by 10.176.81.25 with SMTP id e25mr11626246uaa.7.1497873072738; Mon, 19 Jun 2017 04:51:12 -0700 (PDT) X-Received: by 10.157.51.139 with SMTP id u11mr375240otc.16.1497873072654; Mon, 19 Jun 2017 04:51:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!s24no1045439qte.0!news-out.google.com!k7ni2097itk.0!nntp.google.com!185no1729907itv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 Jun 2017 04:51:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.237.54.238; posting-account=9wwWagoAAAAyocXBEU8dCgb2sVWXuh7w NNTP-Posting-Host: 37.237.54.238 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <98c010d3-aaa5-451f-ae03-c9478e10cf76@googlegroups.com> Subject: calculate crc in vhdl From: adhamalrubiey@gmail.com Injection-Date: Mon, 19 Jun 2017 11:51:12 +0000 Content-Type: text/plain; charset="UTF-8" Xref: news.eternal-september.org comp.lang.vhdl:9182 Dffvv From newsfish@newsfish Thu Aug 1 00:43:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Mon, 19 Jun 2017 17:11:15 -0700 Organization: A noiseless patient Spider Lines: 57 Message-ID: References: <59460a95$0$1503$c3e8da3$5496439d@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 20 Jun 2017 00:07:40 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0ea40028e63233883f4749a429d43383"; logging-data="2349"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+NVphZT/0knnjI4NRBw6avwbYLrORfiMc=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: <59460a95$0$1503$c3e8da3$5496439d@news.astraweb.com> Cancel-Lock: sha1:RFcJ5FDgfyYHIp8fRWNxFydxl4c= Xref: news.eternal-september.org comp.lang.vhdl:9183 On 2017-06-17 22:07, Allan Herriman wrote: > On Sat, 17 Jun 2017 15:46:01 -0700, Charles Bailey wrote: > >> On 2017-06-17 11:08, rickman wrote: >>> Charles Bailey wrote on 6/17/2017 1:25 PM: >>>> On 2017-06-17 00:30, rickman wrote: >>>>> Additionally, I would point out that the counter can be implemented >>>>> more efficiently by coding it as a loadable, down counter. You can >>>>> code it so the carry chain is used to detect the zero condition (next >>>>> value will be less than zero) and load the max counter value, 399 in >>>>> this case. The load control and directly load inputs will fit in the >>>>> same LUTs as the down counter in most FPGA families. Very efficient >>>>> and very fast. >>>>> >>>> Or, based on my ASIC mindset, I would code it like this: >>>> signal a : std_logic; >>>> signal b : std_logic; >>>> signal q : std_logic_vector(0 to 399); >>>> >>>> begin delay : process (CLK) >>>> if( CLK'event and CLK = '1' ) then >>>> q <= a & q(0 to 398); >>>> end if; >>>> end process; >>>> b <= q(399); >>> >>> This appears to be using 400 registers as an actual shift register, no? >>> I suppose shift registers (which don't need the output multiplexer) >>> could be more efficient than block RAM in an ASIC. >>> >>> I'm curious, why do you still use the notation above for a clock edge >>> rather than rising_edge(CLK)? Normally this is only seen in students >>> being taught by teachers who aren't versed in modern methods. >>> >> No particular reason. It's a very common way of specifying the clock >> for sequential logic. For all practical purposes, for both simulation >> and synthesis, it's equivalent to rising_edge(CLK). >> >> In some ways, I tend to prefer this coding style: >> delay : process >> wait until CLK = '1'; >> q <= a & q(0 to 398); >> end process; >> >> because it's simpler and more compact. > > > I used to specify clocked logic like that last century. I got over it. > > Regards, > Allan > I recently completed a large-scale ASIC design of a 4-pass Reed-Solomon decoder. I don't have access to the stats at the moment but it contains 10,000's of latches, SRAMs, register arrays, etc. All of the clocked logic was coded with the "wait until CLK = '1';" style. It simulates and synthesizes just fine. What's to get over? From newsfish@newsfish Thu Aug 1 00:43:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Mon, 19 Jun 2017 17:24:53 -0700 Organization: A noiseless patient Spider Lines: 71 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 20 Jun 2017 00:21:18 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0ea40028e63233883f4749a429d43383"; logging-data="4298"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+EB5GKWMgdy4nlhoSXNVeLbMtDZvqzMk=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:ErFJrb2NvbPgRqP1+h3Sq0vdva0= Xref: news.eternal-september.org comp.lang.vhdl:9184 On 2017-06-18 20:59, rickman wrote: > Charles Bailey wrote on 6/17/2017 6:46 PM: >> On 2017-06-17 11:08, rickman wrote: >>> Charles Bailey wrote on 6/17/2017 1:25 PM: >>>> On 2017-06-17 00:30, rickman wrote: >>>>> Additionally, I would point out that the counter can be implemented >>>>> more >>>>> efficiently by coding it as a loadable, down counter. You can code it >>>>> so the carry chain is used to detect the zero condition (next value >>>>> will >>>>> be less than zero) and load the max counter value, 399 in this case. >>>>> The load control and directly load inputs will fit in the same LUTs as >>>>> the down counter in most FPGA families. Very efficient and very fast. >>>>> >>>> Or, based on my ASIC mindset, I would code it like this: >>>> signal a : std_logic; >>>> signal b : std_logic; >>>> signal q : std_logic_vector(0 to 399); >>>> >>>> begin >>>> delay : process (CLK) >>>> if( CLK'event and CLK = '1' ) then >>>> q <= a & q(0 to 398); >>>> end if; >>>> end process; >>>> b <= q(399); >>> >>> This appears to be using 400 registers as an actual shift register, no? >>> I suppose shift registers (which don't need the output multiplexer) >>> could be more efficient than block RAM in an ASIC. >>> >>> I'm curious, why do you still use the notation above for a clock edge >>> rather than rising_edge(CLK)? Normally this is only seen in students >>> being taught by teachers who aren't versed in modern methods. >>> >> No particular reason. It's a very common way of specifying the clock for >> sequential logic. For all practical purposes, for both simulation and >> synthesis, it's equivalent to rising_edge(CLK). >> >> In some ways, I tend to prefer this coding style: >> delay : process >> wait until CLK = '1'; >> q <= a & q(0 to 398); >> end process; >> >> because it's simpler and more compact. > > I'm very surprised this works. Is there something about this notation > that implies a sensitivity list including CLK? It's been too long since > I've studied the rules of VHDL and this is syntax I just don't use. > > If there is not an implied wait for CLK to change, this won't work. > When CLK changes to '1' it will trigger correctly, but as soon as the > process exits CLK will still be '1' and will retrigger. So there must > be an implied sensitivity list with CLK to wait for a change in CLK, > just like the CLK'event in the other syntax. > > The underlying rules of VHDL are indeed complex. That is why I learned > them once, found basic forms that did what I want to do and don't > deviate. Then I know my stuff will work without needing to always dig > down to the underlying complex rules. > The sensitivity list is implied in the WAIT statement itself. The statement gets executed whenever there is an event on any signal included in the statement. It is essentially equivalent to delay : process (CLK) if( CLK'event and CLK = '1' ) then ... Pretty much every book or manual on VHDL and logic design includes the "wait until CLK = '1';" style as one possible way of coding clocked logic. From newsfish@newsfish Thu Aug 1 00:43:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: create 400 clocks delay for a signal Newsgroups: comp.lang.vhdl References: <59460a95$0$1503$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 20 Jun 2017 09:41:47 GMT Lines: 85 Message-ID: <5948edda$0$11128$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 33ecf8cf.news.astraweb.com X-Trace: DXC=PA`5@Snggkd3i\;U\i>iJhL?0kYOcDh@jW\:Hm@YlDbj17l\Y\;NI@ajO66OajTU8n`SNXaO\01b` Xref: news.eternal-september.org comp.lang.vhdl:9185 On Mon, 19 Jun 2017 17:11:15 -0700, Charles Bailey wrote: > On 2017-06-17 22:07, Allan Herriman wrote: >> On Sat, 17 Jun 2017 15:46:01 -0700, Charles Bailey wrote: >> >>> On 2017-06-17 11:08, rickman wrote: >>>> Charles Bailey wrote on 6/17/2017 1:25 PM: >>>>> On 2017-06-17 00:30, rickman wrote: >>>>>> Additionally, I would point out that the counter can be implemented >>>>>> more efficiently by coding it as a loadable, down counter. You can >>>>>> code it so the carry chain is used to detect the zero condition >>>>>> (next value will be less than zero) and load the max counter value, >>>>>> 399 in this case. The load control and directly load inputs will >>>>>> fit in the same LUTs as the down counter in most FPGA families. >>>>>> Very efficient and very fast. >>>>>> >>>>> Or, based on my ASIC mindset, I would code it like this: >>>>> signal a : std_logic; >>>>> signal b : std_logic; >>>>> signal q : std_logic_vector(0 to 399); >>>>> >>>>> begin delay : process (CLK) >>>>> if( CLK'event and CLK = '1' ) then >>>>> q <= a & q(0 to 398); >>>>> end if; >>>>> end process; >>>>> b <= q(399); >>>> >>>> This appears to be using 400 registers as an actual shift register, >>>> no? >>>> I suppose shift registers (which don't need the output multiplexer) >>>> could be more efficient than block RAM in an ASIC. >>>> >>>> I'm curious, why do you still use the notation above for a clock edge >>>> rather than rising_edge(CLK)? Normally this is only seen in students >>>> being taught by teachers who aren't versed in modern methods. >>>> >>> No particular reason. It's a very common way of specifying the clock >>> for sequential logic. For all practical purposes, for both simulation >>> and synthesis, it's equivalent to rising_edge(CLK). >>> >>> In some ways, I tend to prefer this coding style: >>> delay : process >>> wait until CLK = '1'; >>> q <= a & q(0 to 398); >>> end process; >>> >>> because it's simpler and more compact. >> >> >> I used to specify clocked logic like that last century. I got over it. >> >> Regards, >> Allan >> > I recently completed a large-scale ASIC design of a 4-pass Reed-Solomon > decoder. I don't have access to the stats at the moment but it contains > 10,000's of latches, SRAMs, register arrays, etc. All of the clocked > logic was coded with the "wait until CLK = '1';" style. It simulates > and synthesizes just fine. What's to get over? If no-one else has to read or reuse your code, you can use whatever coding style you want as long as your tools are happy with it. I could argue that it's better to code the way most people code so that it's easier for a wide audience to understand. Consider the problems Rickman had understanding the few lines you posted. The LRM allows for several ways to specify clocked logic. I learned a few different ways in my initial VHDL training, but my experience has been that over the last decade or two most people only learn this way: process (clk) begin if rising_edge(clk) then q <= d; end if; end process; That said, I think it's important to know all the possible ways that clocked logic can be specified. Regards, Allan From newsfish@newsfish Thu Aug 1 00:43:16 2024 X-Received: by 10.13.231.66 with SMTP id q63mr10810282ywe.78.1498028765237; Wed, 21 Jun 2017 00:06:05 -0700 (PDT) X-Received: by 10.157.83.13 with SMTP id g13mr563971oth.10.1498028765166; Wed, 21 Jun 2017 00:06:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y44no5387qth.1!news-out.google.com!k7ni512itk.0!nntp.google.com!185no1806281itv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Jun 2017 00:06:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.159.112.170; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 195.159.112.170 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0bfcd34c-67a0-4b80-aeee-4b8bd2e29b5c@googlegroups.com> Subject: =?UTF-8?Q?VHDL_Verification_components_=E2=80=93_The_obvious_solutio?= =?UTF-8?Q?n_to_efficient_reuse?= From: espen.tallaksen@bitvis.no Injection-Date: Wed, 21 Jun 2017 07:06:05 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9186 How would you assure safe and efficient reuse of an FPGA design module for= some stand-alone functionality? Let's consider this for a simple example like a UART. Now what would you do= ? You could of course just make lots of functions, procedures, processes and = concurrent statements, - and then include all of this into your FPGA top-le= vel whenever you need a UART... But no serious FPGA designer would ever d= o this. =20 Why? Because we all know it is much better to put all of this into a comp= onent (a VHDL entity), as this has the following benefits: - Everything is encapsulated in an entity containing all needed elements - No risk of forgetting parts or functionality - No need to understand the implementation - A simple port interface for integration into the FPGA top level - A simple generic interface for parameterisation of the module - Internal modifications may be done locally - invisible at the FPGA top le= vel - New functionality may be added inside the encapsulation - Reuse is safe and efficient Now - give me one reason why all of this does not apply to verification exa= ctly the same way. Yes - we could still just use lots of processes, sub-programs, etc, but as = for design that would be very inefficient and risky. What we need is of course a VHDL entity - a VHDL Verification Component (VV= C) - encapsulating the complete verification functionality for a given desi= gn interface, where the VVC should be characterized by: - An easy to understand component interface (ports and generics) - A clearly defined internal functionality, where the internal implementati= on is of no interest when integrating the VVC - An easy to understand command interface to control and monitor the behavi= our of the VVC This is exactly how the VVCs of UVVM (Universal VHDL Verification Methodolo= gy, free and Open source) are made.=20 (For a figure of the UART VVC please see http://bitvis.no/products/uvvm-vvc= -framework/vvc_efficient_reuse/) The VVC for a UART has two simple physical port (TX, RX), and is thus very = easy to integrate in a testbench. All the functionality is included inside = and thus well encapsulated and easy to reuse. Once included in the testbenc= h the test sequencer/driver/controller may then execute commands to transmi= t and receive data in many different ways. This command interface is predef= ined in UVVM, which thus provides a common and standardised way of communic= ating with any VVC independent of type - again just like a CPU may communic= ate with any design module inside an FPGA via a predefined bus interface. A major additional benefit of the UVVM VVCs is the ease of integration, the= very structured internal architecture and the extreme reuse friendliness. UVVM is free and open source, and may be downloaded from Github: https://gi= thub.com/UVVM/UVVM_All For a simple and fast introduction to UVVM and VHDL Verification Components= see: http://bitvis.no/media/21190/UVVM_Advanced_Verif_made_simple_1.pdf From newsfish@newsfish Thu Aug 1 00:43:16 2024 X-Received: by 10.157.33.54 with SMTP id i51mr16692401otb.126.1498087043408; Wed, 21 Jun 2017 16:17:23 -0700 (PDT) X-Received: by 10.157.43.235 with SMTP id u98mr1110733ota.9.1498087043319; Wed, 21 Jun 2017 16:17:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!185no526169itv.0!news-out.google.com!k7ni1230itk.0!nntp.google.com!185no526165itv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Jun 2017 16:17:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.38.33.251; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.38.33.251 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4d0e511a-6273-4bbb-86e4-982796add07e@googlegroups.com> Subject: Re: Same syntax for variable and signal update From: Jim Lewis Injection-Date: Wed, 21 Jun 2017 23:17:23 +0000 Content-Type: text/plain; charset="UTF-8" Xref: news.eternal-september.org comp.lang.vhdl:9187 Hi Rob, The function you implied with UPDATE_REGISTER seems to do it quite well. For procedures, perhaps this is an update needed for VHDL-2020. Know of anyone willing to write an LCS. :) Did you post to stack overflow as well? Jim From newsfish@newsfish Thu Aug 1 00:43:17 2024 X-Received: by 10.107.161.82 with SMTP id k79mr7411533ioe.57.1498324415406; Sat, 24 Jun 2017 10:13:35 -0700 (PDT) X-Received: by 10.157.46.80 with SMTP id c16mr331900otd.7.1498324415343; Sat, 24 Jun 2017 10:13:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!185no719539itv.0!news-out.google.com!k7ni1279itk.0!nntp.google.com!185no719536itv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 24 Jun 2017 10:13:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.85.22.108; posting-account=Ba9MNAoAAADMDN4ZiaHdyoXRUliIlEGa NNTP-Posting-Host: 95.85.22.108 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5241920b-db28-4eed-8c04-6b853deb6f25@googlegroups.com> Subject: Re: instructor solution manual for Wireless Communications (Andrea Goldsmith) From: wayeyadata24@gmail.com Injection-Date: Sat, 24 Jun 2017 17:13:35 +0000 Content-Type: text/plain; charset="UTF-8" Xref: news.eternal-september.org comp.lang.vhdl:9188 I want solution of goldsmith book From newsfish@newsfish Thu Aug 1 00:43:17 2024 X-Received: by 10.36.84.212 with SMTP id t203mr7046791ita.36.1498352549908; Sat, 24 Jun 2017 18:02:29 -0700 (PDT) X-Received: by 10.157.12.161 with SMTP id b30mr362774otb.3.1498352549854; Sat, 24 Jun 2017 18:02:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!185no857600itv.0!news-out.google.com!s132ni929itb.0!nntp.google.com!185no857596itv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 24 Jun 2017 18:02:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:1a30:5de5:71c9:48:4711; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:1a30:5de5:71c9:48:4711 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: create 400 clocks delay for a signal From: KJ Injection-Date: Sun, 25 Jun 2017 01:02:29 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9189 Charles Bailey wrote on 6/17/2017 6:46 PM:=20 On Monday, June 19, 2017 at 12:00:01 AM UTC-4, rickman wrote: > > In some ways, I tend to prefer this coding style:=20 > > delay : process=20 > > wait until CLK =3D '1';=20 > > q <=3D a & q(0 to 398);=20 > > end process;=20 > >=20 > > because it's simpler and more compact.=20 > I'm very surprised this works. Is there something about this notation > that implies a sensitivity list including CLK? No, there is no implied sensitivity list. Processes can be written in two = forms: 1. With a sensitivity list, in which case it is illegal to use a wait state= ment within the process. 2. Without a sensitivity list in which case it is legal to use a wait state= ment. When you're writing code for synthesis, it is 'safer' to write in the form = of #1 since it is a bit more difficult (but definitely not impossible) to w= rite code that can't be synthesized. When you're writing testbench code, sometimes it can be easier to write it = in form #2. Using form #2, a wait statement is not required in order to ge= t everything to compile but such code will fail at run time since the proce= ss will keep re-triggering at t=3D0 and you'll get some form of 'iteration = limit exceeded' error. The advantage to form #2 in testbench code is that it is perfectly permissi= ble to sequentially wait on completely separate signal events like the foll= owing: process begin wait until this=3Dthat; wait until rising_edge(moon); wait until CowsComeHome =3D '1' end process; Presumably you would write it this way because the testing environment for = whatever you're testing needs to step through some sequence of steps. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:43:17 2024 X-Received: by 10.99.109.7 with SMTP id i7mr8732113pgc.30.1498353404749; Sat, 24 Jun 2017 18:16:44 -0700 (PDT) X-Received: by 10.157.43.235 with SMTP id u98mr364294ota.9.1498353404695; Sat, 24 Jun 2017 18:16:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f20no861407itb.0!news-out.google.com!s132ni975itb.0!nntp.google.com!185no859971itv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 24 Jun 2017 18:16:44 -0700 (PDT) In-Reply-To: <0bfcd34c-67a0-4b80-aeee-4b8bd2e29b5c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:1a30:5de5:71c9:48:4711; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:1a30:5de5:71c9:48:4711 References: <0bfcd34c-67a0-4b80-aeee-4b8bd2e29b5c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1af6695e-e49d-466e-a1e8-cf70d19a61c0@googlegroups.com> Subject: =?UTF-8?Q?Re=3A_VHDL_Verification_components_=E2=80=93_The_obvious_sol?= =?UTF-8?Q?ution_to_efficient_reuse?= From: KJ Injection-Date: Sun, 25 Jun 2017 01:16:44 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9190 On Wednesday, June 21, 2017 at 3:06:07 AM UTC-4, espen.t...@bitvis.no wrote= : > How would you assure safe and efficient reuse of an FPGA design module= =20 > for some stand-alone functionality? >=20 > Let's consider this for a simple example like a UART. Now what would you = do? >=20 > You could of course just make lots of functions, procedures, processes an= d concurrent statements, - and then include all of this into your FPGA top-= level whenever you need a UART... But no serious FPGA designer would ever= do this. =20 >=20 > Why? Because we all know it is much better to put all of this into a co= mponent (a VHDL entity), as this has the following benefits: >=20 > - Everything is encapsulated in an entity containing all needed elements > - No risk of forgetting parts or functionality > - No need to understand the implementation > - A simple port interface for integration into the FPGA top level > - A simple generic interface for parameterisation of the module > - Internal modifications may be done locally - invisible at the FPGA top = level > - New functionality may be added inside the encapsulation > - Reuse is safe and efficient >=20 > Now - give me one reason why all of this does not apply to verification= =20 > exactly the same way. > Yes - we could still just use lots of processes, sub-programs, etc, but a= s for design that would be very inefficient and risky. >=20 > What we need is of course a VHDL entity - a VHDL Verification Component= =20 > (VVC) - encapsulating the complete verification functionality for a given= =20 > design interface, where the VVC should be characterized by: >=20 > - An easy to understand component interface (ports and generics) > - A clearly defined internal functionality, where the internal=20 > implementation is of no interest when integrating the VVC > - An easy to understand command interface to control and monitor the=20 > behaviour of the VVC >=20 A simpler approach is to simply model the system in which the design operat= es. An FPGA for example is rarely an entire system. Many times the FPGA i= s just one part on a PCBA. Model all of the other parts and you now have a= simulation model of the PCBA. A PCBA is also rarely the entire system. M= any times the PCBA is connected to sensors, actuators, etc. Model those pa= rts and typically you do now have a full system model. All of those parts models are derived from published specifications so when= the entire system does not behave as you think it should and you're trying= to debug whether you have a bug in your design or the model, you refer bac= k to the part specification to validate whether the part model is working o= r not. Part models do not necessarily have to model every nuance of the part, proc= essors are a good example. These models only have to model enough behavior= for the entire system to function somewhat like the real system. One can also 'design in', whatever types of fault models that one wants to = be able to emulate and test. This goes somewhat beyond part's specificatio= ns since no commercial part is probably designed to intentionally fault. This approach is much more straightforward then trying to come up with some= abstract "VHDL Verification Component (VVC) - encapsulating the complete v= erification functionality for a given design interface". Each of the parts= being modeled are individual entities, each PCBA, sensor, actuator, etc. a= re also entities. Nothing abstract and subject to individual interpretati= on since the behavior of those part models is governed by published specifi= cations. Just my two cents. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:43:18 2024 X-Received: by 10.157.61.33 with SMTP id a30mr12014684otc.114.1498473530681; Mon, 26 Jun 2017 03:38:50 -0700 (PDT) X-Received: by 10.157.32.55 with SMTP id n52mr378693ota.10.1498473530636; Mon, 26 Jun 2017 03:38:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f20no1376108itb.0!news-out.google.com!s132ni2402itb.0!nntp.google.com!185no1371580itv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Jun 2017 03:38:50 -0700 (PDT) In-Reply-To: <1af6695e-e49d-466e-a1e8-cf70d19a61c0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.159.112.170; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 195.159.112.170 References: <0bfcd34c-67a0-4b80-aeee-4b8bd2e29b5c@googlegroups.com> <1af6695e-e49d-466e-a1e8-cf70d19a61c0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <025b3416-5b2d-464e-b4b7-81e8eb1ab540@googlegroups.com> Subject: =?UTF-8?Q?Re=3A_VHDL_Verification_components_=E2=80=93_The_obvious_sol?= =?UTF-8?Q?ution_to_efficient_reuse?= From: espen.tallaksen@bitvis.no Injection-Date: Mon, 26 Jun 2017 10:38:50 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9191 s=C3=B8ndag 25. juni 2017 03.16.48 UTC+2 skrev KJ f=C3=B8lgende: > On Wednesday, June 21, 2017 at 3:06:07 AM UTC-4, espen.t...@bitvis.no wro= te: > > How would you assure safe and efficient reuse of an FPGA design module= =20 > > for some stand-alone functionality? > >=20 > > Let's consider this for a simple example like a UART. Now what would yo= u do? > >=20 > > You could of course just make lots of functions, procedures, processes = and concurrent statements, - and then include all of this into your FPGA to= p-level whenever you need a UART... But no serious FPGA designer would ev= er do this. =20 > >=20 > > Why? Because we all know it is much better to put all of this into a = component (a VHDL entity), as this has the following benefits: > >=20 > > - Everything is encapsulated in an entity containing all needed element= s > > - No risk of forgetting parts or functionality > > - No need to understand the implementation > > - A simple port interface for integration into the FPGA top level > > - A simple generic interface for parameterisation of the module > > - Internal modifications may be done locally - invisible at the FPGA to= p level > > - New functionality may be added inside the encapsulation > > - Reuse is safe and efficient > >=20 > > Now - give me one reason why all of this does not apply to verification= =20 > > exactly the same way. > > Yes - we could still just use lots of processes, sub-programs, etc, but= as for design that would be very inefficient and risky. > >=20 > > What we need is of course a VHDL entity - a VHDL Verification Component= =20 > > (VVC) - encapsulating the complete verification functionality for a giv= en=20 > > design interface, where the VVC should be characterized by: > >=20 > > - An easy to understand component interface (ports and generics) > > - A clearly defined internal functionality, where the internal=20 > > implementation is of no interest when integrating the VVC > > - An easy to understand command interface to control and monitor the=20 > > behaviour of the VVC > >=20 >=20 > A simpler approach is to simply model the system in which the design oper= ates. An FPGA for example is rarely an entire system. Many times the FPGA= is just one part on a PCBA. Model all of the other parts and you now have= a simulation model of the PCBA. A PCBA is also rarely the entire system. = Many times the PCBA is connected to sensors, actuators, etc. Model those = parts and typically you do now have a full system model. >=20 > All of those parts models are derived from published specifications so wh= en the entire system does not behave as you think it should and you're tryi= ng to debug whether you have a bug in your design or the model, you refer b= ack to the part specification to validate whether the part model is working= or not. >=20 > Part models do not necessarily have to model every nuance of the part, pr= ocessors are a good example. These models only have to model enough behavi= or for the entire system to function somewhat like the real system. >=20 > One can also 'design in', whatever types of fault models that one wants t= o be able to emulate and test. This goes somewhat beyond part's specificat= ions since no commercial part is probably designed to intentionally fault. >=20 > This approach is much more straightforward then trying to come up with so= me abstract "VHDL Verification Component (VVC) - encapsulating the complete= verification functionality for a given design interface". Each of the par= ts being modeled are individual entities, each PCBA, sensor, actuator, etc.= are also entities. Nothing abstract and subject to individual interpreta= tion since the behavior of those part models is governed by published speci= fications. >=20 > Just my two cents. >=20 > Kevin Jennings I agree that partial (or complete) modelling of your system is also a good = approach, and in my opinion (and experience) combining this with verificati= on components is a very good combined solution. (And sometimes one is bette= r than the other - depending on your actual system to verify.) The great thing about verification components is that for a given interface= you don't need to bother about the details of interface protocols or timin= g, but can access your system via high level SW-like commands (e.g. uart_tr= ansmit(data) or uart_transmit(byte array) or uart_transmit(send N * random = data and also forward to a model), etc...) Similarly you can add functionality to provoke bugs, check bit-timing, etc,= - and everything can be reused 100% from one project to another, and also = from module level to FPGA level.=20 This means interface dedicated functionality is dead simple to use and reus= e, and it also makes it much simpler to control/monitor the FPGA functional= ity that differs from one FPGA to another via commands that anyone can unde= rstand. From newsfish@newsfish Thu Aug 1 00:43:18 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: instructor solution manual for Wireless Communications (Andrea Goldsmith) Date: Mon, 26 Jun 2017 09:44:55 -0700 Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <5241920b-db28-4eed-8c04-6b853deb6f25@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 26 Jun 2017 16:41:11 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="79ed4902580d12fc86dca20925cdf2fb"; logging-data="7092"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ZwWXjA7iQdpT1EP/XF8Ur" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 In-Reply-To: <5241920b-db28-4eed-8c04-6b853deb6f25@googlegroups.com> Content-Language: en-US Cancel-Lock: sha1:o0YNpYRzqifos/KLvk6oPJkZY1s= Xref: news.eternal-september.org comp.lang.vhdl:9192 On 06/24/2017 10:13 AM, wayeyadata24@gmail.com wrote: > I want solution of goldsmith book > I want a fully paid mortgage, a smaller gut, and a pony. Guess we're both going to be disappointed. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:43:18 2024 X-Received: by 10.13.231.66 with SMTP id q63mr9428556ywe.78.1498733094812; Thu, 29 Jun 2017 03:44:54 -0700 (PDT) X-Received: by 10.36.46.202 with SMTP id i193mr331899ita.8.1498733094765; Thu, 29 Jun 2017 03:44:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v31no1391828qtb.0!news-out.google.com!s132ni1532itb.0!nntp.google.com!188no57413itx.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 Jun 2017 03:44:54 -0700 (PDT) In-Reply-To: <025b3416-5b2d-464e-b4b7-81e8eb1ab540@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:1a30:43f:70d8:76a7:cd26; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:1a30:43f:70d8:76a7:cd26 References: <0bfcd34c-67a0-4b80-aeee-4b8bd2e29b5c@googlegroups.com> <1af6695e-e49d-466e-a1e8-cf70d19a61c0@googlegroups.com> <025b3416-5b2d-464e-b4b7-81e8eb1ab540@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1bcab60c-e555-401b-ae54-9d1ed681127c@googlegroups.com> Subject: =?UTF-8?Q?Re=3A_VHDL_Verification_components_=E2=80=93_The_obvious_sol?= =?UTF-8?Q?ution_to_efficient_reuse?= From: KJ Injection-Date: Thu, 29 Jun 2017 10:44:54 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9193 On Monday, June 26, 2017 at 6:38:52 AM UTC-4, espen.t...@bitvis.no wrote: > s=C3=B8ndag 25. juni 2017 03.16.48 UTC+2 skrev KJ f=C3=B8lgende: > > On Wednesday, June 21, 2017 at 3:06:07 AM UTC-4, espen.t...@bitvis.no w= rote: > > > How would you assure safe and efficient reuse of an FPGA design modu= le=20 > > > for some stand-alone functionality? > > >=20 > > > Let's consider this for a simple example like a UART. Now what would = you do? > > >=20 > > > You could of course just make lots of functions, procedures, processe= s and concurrent statements, - and then include all of this into your FPGA = top-level whenever you need a UART... But no serious FPGA designer would = ever do this. =20 > > >=20 > > > Why? Because we all know it is much better to put all of this into = a component (a VHDL entity), as this has the following benefits: > > >=20 > > > - Everything is encapsulated in an entity containing all needed eleme= nts > > > - No risk of forgetting parts or functionality > > > - No need to understand the implementation > > > - A simple port interface for integration into the FPGA top level > > > - A simple generic interface for parameterisation of the module > > > - Internal modifications may be done locally - invisible at the FPGA = top level > > > - New functionality may be added inside the encapsulation > > > - Reuse is safe and efficient > > >=20 > > > Now - give me one reason why all of this does not apply to verificati= on=20 > > > exactly the same way. > > > Yes - we could still just use lots of processes, sub-programs, etc, b= ut as for design that would be very inefficient and risky. > > >=20 > > > What we need is of course a VHDL entity - a VHDL Verification Compone= nt=20 > > > (VVC) - encapsulating the complete verification functionality for a g= iven=20 > > > design interface, where the VVC should be characterized by: > > >=20 > > > - An easy to understand component interface (ports and generics) > > > - A clearly defined internal functionality, where the internal=20 > > > implementation is of no interest when integrating the VVC > > > - An easy to understand command interface to control and monitor the= =20 > > > behaviour of the VVC > > >=20 > >=20 > > A simpler approach is to simply model the system in which the design op= erates. An FPGA for example is rarely an entire system. Many times the FP= GA is just one part on a PCBA. Model all of the other parts and you now ha= ve a simulation model of the PCBA. A PCBA is also rarely the entire system= . Many times the PCBA is connected to sensors, actuators, etc. Model thos= e parts and typically you do now have a full system model. > >=20 > > All of those parts models are derived from published specifications so = when the entire system does not behave as you think it should and you're tr= ying to debug whether you have a bug in your design or the model, you refer= back to the part specification to validate whether the part model is worki= ng or not. > >=20 > > Part models do not necessarily have to model every nuance of the part, = processors are a good example. These models only have to model enough beha= vior for the entire system to function somewhat like the real system. > >=20 > > One can also 'design in', whatever types of fault models that one wants= to be able to emulate and test. This goes somewhat beyond part's specific= ations since no commercial part is probably designed to intentionally fault= . > >=20 > > This approach is much more straightforward then trying to come up with = some abstract "VHDL Verification Component (VVC) - encapsulating the comple= te verification functionality for a given design interface". Each of the p= arts being modeled are individual entities, each PCBA, sensor, actuator, et= c. are also entities. Nothing abstract and subject to individual interpre= tation since the behavior of those part models is governed by published spe= cifications. > >=20 > > Just my two cents. > >=20 > > Kevin Jennings >=20 > I agree that partial (or complete) modelling of your system is also a goo= d approach, and in my opinion (and experience) combining this with verifica= tion components is a very good combined solution. (And sometimes one is bet= ter than the other - depending on your actual system to verify.) >=20 > The great thing about verification components is that for a given interfa= ce you don't need to bother about the details of interface protocols or tim= ing, but can access your system via high level SW-like commands (e.g. uart_= transmit(data) or uart_transmit(byte array) or uart_transmit(send N * rando= m data and also forward to a model), etc...) > Similarly you can add functionality to provoke bugs, check bit-timing, et= c, - and everything can be reused 100% from one project to another, and als= o from module level to FPGA level.=20 > This means interface dedicated functionality is dead simple to use and re= use, and it also makes it much simpler to control/monitor the FPGA function= ality that differs from one FPGA to another via commands that anyone can un= derstand. And the exact same things can be said about using models of real physical p= arts and other components. I disagree with your statement "you don't need to bother about the details = of interface protocols or timing", sure you do. You need to create that fi= rst model of that interface protocol and that needs to be correct. Again, = this comment is the same as with a model of a true physical component. The= advantage of using a model of a real part is that you have a true datashee= t to use to validate that the model itself is correct. With some virtual v= erification component, you don't have that datasheet which can mean that yo= u come up with a verification component that does not match reality. Every= line of code that gets written, whether as part of a design or part of a v= erification model has a chance of being wrong. What is your strategy for v= alidating that your model itself is correct? Kevin Jennings From newsfish@newsfish Thu Aug 1 00:43:18 2024 X-Received: by 10.99.127.1 with SMTP id a1mr1002682pgd.16.1498807628213; Fri, 30 Jun 2017 00:27:08 -0700 (PDT) X-Received: by 10.36.125.65 with SMTP id b62mr242742itc.5.1498807628155; Fri, 30 Jun 2017 00:27:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v202no175258itb.0!news-out.google.com!k7ni4083itk.0!nntp.google.com!188no240606itx.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Jun 2017 00:27:07 -0700 (PDT) In-Reply-To: <1bcab60c-e555-401b-ae54-9d1ed681127c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.159.112.170; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 195.159.112.170 References: <0bfcd34c-67a0-4b80-aeee-4b8bd2e29b5c@googlegroups.com> <1af6695e-e49d-466e-a1e8-cf70d19a61c0@googlegroups.com> <025b3416-5b2d-464e-b4b7-81e8eb1ab540@googlegroups.com> <1bcab60c-e555-401b-ae54-9d1ed681127c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0b9a9b41-d15f-4093-b3fe-766466ec42c7@googlegroups.com> Subject: =?UTF-8?Q?Re=3A_VHDL_Verification_components_=E2=80=93_The_obvious_sol?= =?UTF-8?Q?ution_to_efficient_reuse?= From: espen.tallaksen@bitvis.no Injection-Date: Fri, 30 Jun 2017 07:27:08 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9194 There are of course different scenarios here. One is to access the rest of = your FPGA through an interface/protocol. This is the default for most BFMs = and VVCs and a allow a testbench to be up and running in a very short time.= The other is a protocol checker that also checks your interface/protocol t= horoughly. We have heard of several users who actually have found design bu= gs in their interface design even with non-protocol checker BFM/VVC, so the= y may be partially useful for that as well. And in many cases you don't nee= d a protocol checker, but just an access into/out of the "rest" of your FPG= A. What I meant about the statement "you don't need to bother about the detail= s of interface protocols or timing" is that this is already care of inside = a good BFM or VVC, a bit like when you use IP (your own, FPGA vendor, tool = vendor, 3rd party) for say a complex interface or some complex data process= ing, then you don't really want to waste time understanding the details of = the implementation if you are provided with a simplified user interface. Also in many projects several designers may need to access the same interfa= ce, and it would be a total waste of time if everybody had to go into the d= etails of that interface/protocol if they could rather use a simple transac= tion level procedure that hides the details for them. I fact in most cases where people talk about models they tend to mix interf= ace and internal functionality, or tend to combine multiple interface layer= s inside the same model. For those cases it is obvious that layering is mor= e efficient, more reusable and safer, - and one of those layers is very oft= en a BFM or VVC. I think the best strategy for validating any type of model/BFM/VVC (at the = level of ambition for which it is intended) is to have as many designers as= possible using and checking them, and I must admit that we have already im= proved/fixed our BFMs/VVCs several times do to feedback from UVVM users all= over the world. From newsfish@newsfish Thu Aug 1 00:43:19 2024 X-Received: by 10.31.52.79 with SMTP id b76mr12952105vka.36.1498873506685; Fri, 30 Jun 2017 18:45:06 -0700 (PDT) X-Received: by 10.36.69.103 with SMTP id y100mr447956ita.0.1498873506511; Fri, 30 Jun 2017 18:45:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m54no1695667qtb.1!news-out.google.com!s132ni3123itb.0!nntp.google.com!188no420414itx.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Jun 2017 18:45:05 -0700 (PDT) In-Reply-To: <0b9a9b41-d15f-4093-b3fe-766466ec42c7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:1a30:5de5:71c9:48:4711; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:1a30:5de5:71c9:48:4711 References: <0bfcd34c-67a0-4b80-aeee-4b8bd2e29b5c@googlegroups.com> <1af6695e-e49d-466e-a1e8-cf70d19a61c0@googlegroups.com> <025b3416-5b2d-464e-b4b7-81e8eb1ab540@googlegroups.com> <1bcab60c-e555-401b-ae54-9d1ed681127c@googlegroups.com> <0b9a9b41-d15f-4093-b3fe-766466ec42c7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7a0d0915-a360-4ffb-b329-b611c53d120e@googlegroups.com> Subject: =?UTF-8?Q?Re=3A_VHDL_Verification_components_=E2=80=93_The_obvious_sol?= =?UTF-8?Q?ution_to_efficient_reuse?= From: KJ Injection-Date: Sat, 01 Jul 2017 01:45:06 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9195 On Friday, June 30, 2017 at 3:27:12 AM UTC-4, espen.t...@bitvis.no wrote: > What I meant about the statement "you don't need to bother about the deta= ils of interface protocols or timing" is that this is already care of insid= e a good BFM or VVC, a bit like when you use IP (your own, FPGA vendor, too= l vendor, 3rd party) for say a complex interface or some complex data proce= ssing, then you don't really want to waste time understanding the details o= f the implementation if you are provided with a simplified user interface. You have to understand the complex interface once in order to write the mod= el. It's also likely that you'll need to delve into those details on occas= ion afterwards in order to fix the bugs. That's called support which hopef= ully does decrease over time. But yes, of course, the idea is always that = you're transforming a 'complex' interface into a simpler easier to use one = so you're not stating anything that isn't obvious. > Also in many projects several designers may need to access the same inter= face, and it would be a total waste of time if everybody had to go into the= details of that interface/protocol if they could rather use a simple trans= action level procedure that hides the details for them. That's called design reuse, again nothing new. Whether or not the 'design'= being used is part of an actual physical design or a simulation model is n= ot important. > I fact in most cases where people talk about models they tend to mix inte= rface and internal functionality, or tend to combine multiple interface lay= ers inside the same model. For those cases it is obvious that layering is m= ore efficient, more reusable and safer, - and one of those layers is very o= ften a BFM or VVC. Yet when I look at the UART example you posted (http://bitvis.no/products/u= vvm-vvc-framework/vvc_efficient_reuse/), the figure (maybe the code too) do= es not reflect your statement. The DUT has unconnected interfaces that are= required in order to actually test functionality. Had that figure been dr= awn properly, there would be some form of processor model to the left of th= e DUT UART and one to the right of the UART_VVC. In fact, the functionalit= y of UART_VVC would simply be that of some known good UART model, such as a= n actual commercial part that has a datasheet as I've said all along. The = processor models would be the thing that provides the translation between h= igh level statements like "print("Hello world\n") and the processor interfa= ce. Ideally this would be an abstract interface that would then connect wi= th a converter to translate between the abstract interface and that of the = DUT UART's 'Register IF' or the VVC UART's register interface. The same pr= ocessor model is used, they are only 'running' a different high level progr= am such as "while TRUE loop, ch =3D getc(); putc(ch);". That model simply = echoes back everything that comes in. The VVC model would then check all i= ncoming messages to make sure they match what was sent out. Graphically, t= he connections are: DUT Proc<-->Intf Conv<-->DUT UART<--RX/RX-->VVC UART<-->Intf Conv<--VVC Pro= c Not shown in the figures would be some fault model that actually disrupts R= X/TX in some fashion if that level of testing is required. That's how I would draw it. That method actually does break down the 'laye= rs' as you called them but there is no mystery about which layer to which s= omething belongs. Within the processor model, one can build up device spec= ific layers of code so that one is not having to read/write hard coded addr= esses. Instead you build up device specific code so that you can eventuall= y say "print("Hello world\n" in the source code. But you wouldn't stop the= re. You would also build up test procedures so that maybe at the top level= your code is just "Test(Uart);". But all of this is exactly the same as w= riting traditional software, so again, not breaking new ground just using e= stablished principals. The only thing you don't need to create or emulate = here is a compiler to translate source code into object code for the proces= sor. The VHDL compiler is essentially performing that function. The VVC Proc runs the program that generates the messages, the DUT Proc run= s the program that simply echos back whatever came in. The VVC Proc then h= as a checker to validate that what comes back was what was sent out; that a= ll messages did arrive; that you check operation for all baud rates, etc. While your web page touts of reuse, no actual examples are really shown. F= or instance, when would one ever have a need to reuse the UART VVC? You ca= n't use it to test a disk controller. Once you have it all working with th= e UART design, there is never a need to even re-run the simulation let alon= e reuse the UART VVC unless the DUT UART design is changed. But even there= the most likely scenario is you simply rerun the simulation tests with the= new DUT UART rather than reuse anything into some new code. At best, you'= ve added some new functionality which then requires additional testing soft= ware to be added to the processor model. Not design reuse. On the other hand, my drawing is already reusing a processor model and perh= aps using the same 'abstract processor to UART Register' converter if DUT U= ART and VVC UART happen to have the same interface. Actual design reuse ac= hieved by using models that reflect reality. > I think the best strategy for validating any type of model/BFM/VVC (at th= e level of ambition for which it is intended) is to have as many designers = as possible using and checking them, and I must admit that we have already = improved/fixed our BFMs/VVCs several times do to feedback from UVVM users a= ll over the world. Well, that's the strategy of Microsoft and all the other software providers= . Put it out there and let the user's find the bugs. Not saying it's not = a successful strategy but it's one that has had nearly every user cursing a= t their device or the software. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:43:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: create 400 clocks delay for a signal Date: Sat, 1 Jul 2017 09:11:15 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Jul 2017 13:07:38 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="e9b7d49a5498205cf31417869a56e8a6"; logging-data="2048"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/EBlaAcNWuP51sJdhFBGyY" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 In-Reply-To: Content-Language: en-US Cancel-Lock: sha1:XKPLmlcE8FONQfH6n2WO9co2Tik= Xref: news.eternal-september.org comp.lang.vhdl:9196 On Sunday, 6/18/2017 11:59 PM, rickman wrote: >> In some ways, I tend to prefer this coding style: >> delay : process >> wait until CLK = '1'; >> q <= a & q(0 to 398); >> end process; >> >> because it's simpler and more compact. > > I'm very surprised this works. Is there something about this notation > that implies a sensitivity list including CLK? Probably beating a dead horse, but an important point here is that without a sensitivity list, the process runs continuously. So if you *don't* have a wait (either on an event or a fixed time period) the process will prevent simulation time from advancing. This is a common mistake I see in beginner code. It can also be hard to find why the simulation is stuck if you don't know how to break the simulation and see what code is currently "executing." -- Gabor From newsfish@newsfish Thu Aug 1 00:43:20 2024 X-Received: by 10.99.127.1 with SMTP id a1mr1500807pgd.16.1498936228631; Sat, 01 Jul 2017 12:10:28 -0700 (PDT) X-Received: by 10.36.16.207 with SMTP id 198mr596111ity.1.1498936228538; Sat, 01 Jul 2017 12:10:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!188no539233itx.0!news-out.google.com!k7ni5560itk.0!nntp.google.com!v202no475118itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 1 Jul 2017 12:10:28 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.137.215.241; posting-account=qrVKxAoAAABIjvVnVCEmCXgB_uFUfdCR NNTP-Posting-Host: 129.137.215.241 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8505caac-5a0c-4a30-8cb7-a7f2f719d3bd@googlegroups.com> Subject: User Defined Primitives From: tylerjoshuahilbert@gmail.com Injection-Date: Sat, 01 Jul 2017 19:10:28 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9197 I'm just learning Verilog now and came across User Defined Primitives in my= textbook. They seem really useless to me because they can only have 1 out= put. What is the use of them if you can only have 1 output? Also do peopl= e use them a lot in development instead of modules? From newsfish@newsfish Thu Aug 1 00:43:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: User Defined Primitives Followup-To: comp.lang.verilog Date: Sun, 2 Jul 2017 12:29:10 -0400 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <8505caac-5a0c-4a30-8cb7-a7f2f719d3bd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 2 Jul 2017 16:25:25 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ff13eef9cdd565e01ded94a60c231433"; logging-data="26622"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+KctpD0VFXOyKoe2CGwaGe" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 In-Reply-To: <8505caac-5a0c-4a30-8cb7-a7f2f719d3bd@googlegroups.com> Content-Language: en-US Cancel-Lock: sha1:pWsa6kVHLWQ7R7dXBzOUYdhBcBA= Xref: news.eternal-september.org comp.lang.vhdl:9198 On Saturday, 7/1/2017 3:10 PM, tylerjoshuahilbert@gmail.com wrote: > I'm just learning Verilog now and came across User Defined Primitives in my textbook. They seem really useless to me because they can only have 1 output. What is the use of them if you can only have 1 output? Also do people use them a lot in development instead of modules? > (setting follow-up to c.a.verilog) As this is a Verilog question, it makes sense to post in comp.lang.verilog rather than the VHDL group. My guess is that User Defined Primitives are not used very often, but when they are it's more likely in ASIC design than FPGA design. In my FPGA work I don't use either the pre-defined primitives or user defined primitives, since the tools are very good at inferring logic from a behavioral description. -- Gabor From newsfish@newsfish Thu Aug 1 00:43:20 2024 X-Received: by 10.36.10.139 with SMTP id 133mr11445746itw.3.1499072750286; Mon, 03 Jul 2017 02:05:50 -0700 (PDT) X-Received: by 10.36.23.151 with SMTP id 145mr1074350ith.7.1499072750257; Mon, 03 Jul 2017 02:05:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v202no751108itb.0!news-out.google.com!k7ni7113itk.0!nntp.google.com!v202no751097itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Jul 2017 02:05:49 -0700 (PDT) In-Reply-To: <7a0d0915-a360-4ffb-b329-b611c53d120e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.159.112.170; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 195.159.112.170 References: <0bfcd34c-67a0-4b80-aeee-4b8bd2e29b5c@googlegroups.com> <1af6695e-e49d-466e-a1e8-cf70d19a61c0@googlegroups.com> <025b3416-5b2d-464e-b4b7-81e8eb1ab540@googlegroups.com> <1bcab60c-e555-401b-ae54-9d1ed681127c@googlegroups.com> <0b9a9b41-d15f-4093-b3fe-766466ec42c7@googlegroups.com> <7a0d0915-a360-4ffb-b329-b611c53d120e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: =?UTF-8?Q?Re=3A_VHDL_Verification_components_=E2=80=93_The_obvious_sol?= =?UTF-8?Q?ution_to_efficient_reuse?= From: espen.tallaksen@bitvis.no Injection-Date: Mon, 03 Jul 2017 09:05:50 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9199 There are very many ways of making testbenches, and I do understand that fo= r some approaches VVCs may not fit in. But it seems to me that UVM's UVCs = (UVM Verification Components) has been very successful and a very efficient= approach for making good testbenches in an efficient manner. UVVM and VVCs= are basically providing much of the same concept, but for VHDL and with a = far lower user threshold and allowing the use of low cost tools). So at lea= st for quite a few testbench approaches VVCs is a good thing. As to your comment that VVCs are no longer needed once your interface has b= een checked, - that might apply for protocol checkers, but still it would b= e a huge advantage to have protocol checker for everyone who makes a new in= terface. The VVCs that we have provided with UVVM are not intended as proto= col checkers, but as interface access procedures. E.g. when writing to any= thing inside your FPGA via an Avalon interface, a procedural access like av= alon_write(my_addr, my_data) is the preferred approach in most testbenches,= - i.e. as a BFM. Some added benefits of a VVC are - Queueing of commands - Very simple control of simultaneous access on multiple interfaces - Encapsulated all relevant Avalon MM functionality (including - Avalon acc= ess initiation and completion (for pipelined access)) We could of course provide more figures for how the VVC may fit in, but we = have so far seen that the VVC users have lots of different use cases. Thus = we explain how it works and the users may apply them any way they want. I don't really see any similarity with the Microsoft approach you mention. = UVVM including all the VVCs are free and Open source, so it's a bit more li= ke other Open source... My point was that with many users we ALL benefit fr= om the fact that any module that is used by many designers in average has a= better quality than something used by just one person or a small team. We really hope other designers/companies will soon start making their own V= VCs and make them available for the VHDL community. That would be really gr= eat both from an efficiency and quality point of view. If they make them av= ailable as Open source or commercial IP is really up to each single contrib= utor, but the sum of it all will make VHDL testbench development faster and= better - at least for a large number of users. From newsfish@newsfish Thu Aug 1 00:43:20 2024 X-Received: by 10.129.83.68 with SMTP id h65mr760108ywb.135.1499933532096; Thu, 13 Jul 2017 01:12:12 -0700 (PDT) X-Received: by 10.31.69.77 with SMTP id s74mr7371vka.1.1499933532062; Thu, 13 Jul 2017 01:12:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m54no306860qtb.1!news-out.google.com!p50ni6160qte.0!nntp.google.com!m54no306859qtb.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 13 Jul 2017 01:12:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: create 400 clocks delay for a signal From: Thomas Stanka Injection-Date: Thu, 13 Jul 2017 08:12:12 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:9200 Am Dienstag, 20. Juni 2017 02:25:00 UTC+2 schrieb Charles Bailey: > Pretty much every book or manual on VHDL and logic design includes the=20 > "wait until CLK =3D '1';" style as one possible way of coding clocked log= ic. It is, but I bet you will find more tools not supporting this style than to= ols supporting it when you leave the both major simulator and synthesis too= ls and have to use other tools. Additionally it is not as intuitive to understand for beginner that=20 wait until clk =3D '1' is in some cases equivalent to rising_edge(Clk) and = ofc it will simulate different for clk having more states than only '1' and= '0', as '1'=3D> 'H'=3D>'1' would be rising edge for your style of code.=20 As you are aware of this, it is fine for you, but someone else using your c= ode will not see, if you took care of this or it is just by chance sometim= es working. And it would have been no problem for you to write "wait until = rising_edge(Clk)" to show other using your code what you really intended. regards, Thomas From newsfish@newsfish Thu Aug 1 00:43:21 2024 X-Received: by 10.98.78.88 with SMTP id c85mr6494112pfb.9.1501312121415; Sat, 29 Jul 2017 00:08:41 -0700 (PDT) X-Received: by 10.31.153.84 with SMTP id b81mr53051vke.14.1501312121156; Sat, 29 Jul 2017 00:08:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!t6no546864itb.0!news-out.google.com!g57ni148qtg.1!nntp.google.com!s6no770915qtc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 29 Jul 2017 00:08:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=202.170.60.248; posting-account=f_jXWQkAAABftWYZvg0kV2D3CVWEBUqI NNTP-Posting-Host: 202.170.60.248 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6369e617-22a3-41f7-8c73-b8390cd1072c@googlegroups.com> Subject: Re: VHDL 2008 support in Modelsim? From: sockpemote@gmail.com Injection-Date: Sat, 29 Jul 2017 07:08:41 +0000 Content-Type: text/plain; charset="UTF-8" Xref: news.eternal-september.org comp.lang.vhdl:9201 On Friday, 19 December 2014 05:05:02 UTC+8, Daniel Kho wrote: > On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote: > > On 05/12/2014 12:48, Anssi Saari wrote: > > > > > > Is Modelsim still not implementing VHDL 2008? I have some code with the > > > "new" if ... generate with else branch but Modelsim 10.1e doesn't seem > > > to support that. Or is it just that the Altera's Starter Edition doesn't > > > support that? I don't have a Modelsim PE or SE installed right now... I > > > tried case in generate as well but it didn't work any better. > > > > Modelsim 10.1e was released in June of 2013. Your code compiled OK in > > the latest 10.3d release. > > > > Modelsim SE is an obsolete product and replaced by Questa core. > > > > Regards, > > Hans > > www.ht-lab.com > > > > > > > > > > > > Example code, vcom -2008 says > > > ** Error: generate_prob.vhdl(20): near "else": syntax error > > > (line 20 is the else generate line.) > > > > > > LIBRARY ieee; > > > USE ieee.std_logic_1164.ALL; > > > > > > entity dummy is > > > generic ( > > > some_boolean_generic : boolean := false); > > > port( > > > clk : in std_logic; > > > reset_n : in std_logic; > > > dout : out std_logic > > > ); > > > end dummy; > > > > > > architecture dummy_arch of dummy is > > > > > > begin > > > > > > some_label: if some_boolean_generic = false generate > > > dout <= '0'; > > > else generate > > > dout <= '1'; > > > end generate some_label; > > > > > > end dummy_arch; > > > > > The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty well. It's free (as in beer) - you can get it from Altera's website. > > -dan Does VHDL-2008 need to be activated? From newsfish@newsfish Thu Aug 1 00:43:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.alt.net!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: VHDL 2008 support in Modelsim? Newsgroups: comp.lang.vhdl References: <6369e617-22a3-41f7-8c73-b8390cd1072c@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 30 Jul 2017 06:13:57 GMT Lines: 76 Message-ID: <597d7925$0$1530$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 4d24254a.news.astraweb.com X-Trace: DXC=gYM]ZKd9D4GiG8i?S9JJK Xref: news.eternal-september.org comp.lang.vhdl:9202 On Sat, 29 Jul 2017 00:08:40 -0700, sockpemote wrote: > On Friday, 19 December 2014 05:05:02 UTC+8, Daniel Kho wrote: >> On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote: >> > On 05/12/2014 12:48, Anssi Saari wrote: >> > > >> > > Is Modelsim still not implementing VHDL 2008? I have some code with >> > > the "new" if ... generate with else branch but Modelsim 10.1e >> > > doesn't seem to support that. Or is it just that the Altera's >> > > Starter Edition doesn't support that? I don't have a Modelsim PE or >> > > SE installed right now... I tried case in generate as well but it >> > > didn't work any better. >> > >> > Modelsim 10.1e was released in June of 2013. Your code compiled OK in >> > the latest 10.3d release. >> > >> > Modelsim SE is an obsolete product and replaced by Questa core. >> > >> > Regards, >> > Hans www.ht-lab.com >> > >> > >> > >> > >> > > Example code, vcom -2008 says ** Error: generate_prob.vhdl(20): >> > > near "else": syntax error (line 20 is the else generate line.) >> > > >> > > LIBRARY ieee; >> > > USE ieee.std_logic_1164.ALL; >> > > >> > > entity dummy is >> > > generic ( >> > > some_boolean_generic : boolean := false); >> > > port( >> > > clk : in std_logic; >> > > reset_n : in std_logic; >> > > dout : out std_logic ); >> > > end dummy; >> > > >> > > architecture dummy_arch of dummy is >> > > >> > > begin >> > > >> > > some_label: if some_boolean_generic = false generate >> > > dout <= '0'; >> > > else generate >> > > dout <= '1'; >> > > end generate some_label; >> > > >> > > end dummy_arch; >> > > >> > > >> The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty >> well. It's free (as in beer) - you can get it from Altera's website. >> >> -dan > > Does VHDL-2008 need to be activated? Not activated, but the VHDL compiler, vcom, takes a command line flag to indicate which version of VHDL you want to apply. e.g. vcom -93 or vcom -2008 You can also put a default version in modelsim.ini [vcom] ; VHDL93 variable selects language version as the default. VHDL93 = 2008 Regards, Allan From newsfish@newsfish Thu Aug 1 00:43:21 2024 X-Received: by 10.129.106.197 with SMTP id f188mr829841ywc.127.1501827200722; Thu, 03 Aug 2017 23:13:20 -0700 (PDT) X-Received: by 10.31.179.145 with SMTP id c139mr5749vkf.24.1501827200681; Thu, 03 Aug 2017 23:13:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!w51no397364qtc.0!news-out.google.com!e5ni306qta.0!nntp.google.com!s6no397180qtc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Aug 2017 23:13:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.23.226.36; posting-account=3RYUJQoAAACVZ74LdG_QrCMIEtybDYwT NNTP-Posting-Host: 185.23.226.36 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: LFSR doesn't generate random values during simulation From: hamzar105@gmail.com Injection-Date: Fri, 04 Aug 2017 06:13:20 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Body-CRC: 179094904 X-Received-Bytes: 4192 Lines: 107 Xref: news.eternal-september.org comp.lang.vhdl:9203 I am new to VHDL, but have some idea. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. library ieee; use ieee.std_logic_1164.all; --creating a galois LFSR entity LFSR is port ( clk : in std_logic; rst : in std_logic; en : in std_logic; rdm_out : out std_logic_vector(15 downto 0); rdm_out_a : out std_logic_vector(7 downto 0); rdm_out_b : out std_logic_vector(7 downto 0); lfsr_Done : out std_logic --lfsr done ); end entity LFSR; architecture behavioral of LFSR is signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' ,others => '0'); --initial value as seed signal temp_done : std_logic; begin process (clk, rst) begin if rising_edge (clk) then --module operates only when enabled if (rst = '1') then temp_out <= (0 => '1' ,others => '0'); temp_done <= '0'; elsif (en = '1') then temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0); --temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0); temp_done <= '1'; end if; end if; end process; rdm_out <= temp_out(15 downto 0); rdm_out_a <= temp_out(15 downto 8); rdm_out_b <= temp_out(7 downto 0); lfsr_Done <= temp_done; end architecture behavioral;` The commented out temp_out is actual feedback (taps are 16,15,13, and 4) as I checked with random taps but still no improvement. And the testbench I used is this: library ieee; use ieee.std_logic_1164.all; entity lfsr_tb is end lfsr_tb; architecture test_bench of lfsr_tb is component LFSR port ( clk : in std_logic; rst : in std_logic; en : in std_logic; rdm_out : out std_logic_vector(15 downto 0); rdm_out_a : out std_logic_vector(7 downto 0); rdm_out_b : out std_logic_vector(7 downto 0); lfsr_Done : out std_logic ); end component; signal clk1: std_logic; signal rst1: std_logic; signal en1 : std_logic; signal rdm_out1 : std_logic_vector(15 downto 0); signal rdm_out_a1 : std_logic_vector(7 downto 0); signal rdm_out_b1 : std_logic_vector(7 downto 0); signal lfsr_Done1 : std_logic ; begin mapping: LFSR port map( clk => clk1, rst => rst1, en => en1, rdm_out => rdm_out1, rdm_out_a => rdm_out_a1, rdm_out_b => rdm_out_b1, lfsr_Done => lfsr_Done1 ); clock: process begin clk1 <= '0'; wait for 10 ps; clk1 <= '1'; wait for 10 ps; end process; reset: process begin rst1 <= '1'; wait for 10 ps; rst1 <= '0'; en1 <= '1'; wait for 800 ps; end process; end test_bench; I cannot understand what is wrong in the code. Kindly guide as its related to my project. From newsfish@newsfish Thu Aug 1 00:43:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: LFSR doesn't generate random values during simulation Date: Fri, 4 Aug 2017 11:48:13 -0400 Organization: A noiseless patient Spider Lines: 116 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 4 Aug 2017 15:44:05 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="e7432ae38b79f8a78b1b6608f8b9717c"; logging-data="21307"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+X1Oap7KvBYJWOtcrR/ov8" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:49.0) Gecko/20100101 Firefox/49.0 SeaMonkey/2.46 In-Reply-To: Cancel-Lock: sha1:07Dk5vcQvWsvgaNTaliqUv3zjqU= Xref: news.eternal-september.org comp.lang.vhdl:9204 hamzar105@gmail.com wrote on 8/4/2017 2:13 AM: > I am new to VHDL, but have some idea. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. > > library ieee; > use ieee.std_logic_1164.all; > > --creating a galois LFSR > entity LFSR is > port ( > clk : in std_logic; > rst : in std_logic; > en : in std_logic; > rdm_out : out std_logic_vector(15 downto 0); > rdm_out_a : out std_logic_vector(7 downto 0); > rdm_out_b : out std_logic_vector(7 downto 0); > lfsr_Done : out std_logic --lfsr done > ); > end entity LFSR; > > architecture behavioral of LFSR is > signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' ,others => '0'); --initial value as seed > signal temp_done : std_logic; > > begin > > process (clk, rst) > begin > if rising_edge (clk) then --module operates only when enabled > if (rst = '1') then > temp_out <= (0 => '1' ,others => '0'); > temp_done <= '0'; > > elsif (en = '1') then > temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0); > --temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0); > temp_done <= '1'; > end if; > end if; > end process; > > > rdm_out <= temp_out(15 downto 0); > rdm_out_a <= temp_out(15 downto 8); > rdm_out_b <= temp_out(7 downto 0); > lfsr_Done <= temp_done; > end architecture behavioral;` > > The commented out temp_out is actual feedback (taps are 16,15,13, and 4) as I checked with random taps but still no improvement. > > And the testbench I used is this: > > library ieee; > use ieee.std_logic_1164.all; > > entity lfsr_tb is > end lfsr_tb; > > architecture test_bench of lfsr_tb is > > component LFSR > port ( > clk : in std_logic; > rst : in std_logic; > en : in std_logic; > rdm_out : out std_logic_vector(15 downto 0); > rdm_out_a : out std_logic_vector(7 downto 0); > rdm_out_b : out std_logic_vector(7 downto 0); > lfsr_Done : out std_logic ); > > end component; > > > signal clk1: std_logic; > signal rst1: std_logic; > signal en1 : std_logic; > > signal rdm_out1 : std_logic_vector(15 downto 0); > signal rdm_out_a1 : std_logic_vector(7 downto 0); > signal rdm_out_b1 : std_logic_vector(7 downto 0); > signal lfsr_Done1 : std_logic ; > > begin > > mapping: LFSR port map( > clk => clk1, > rst => rst1, > en => en1, > rdm_out => rdm_out1, > rdm_out_a => rdm_out_a1, > rdm_out_b => rdm_out_b1, > lfsr_Done => lfsr_Done1 ); > > clock: process > begin > clk1 <= '0'; wait for 10 ps; > clk1 <= '1'; wait for 10 ps; > end process; > > reset: process > begin > rst1 <= '1'; wait for 10 ps; > rst1 <= '0'; > en1 <= '1'; wait for 800 ps; > end process; > > end test_bench; > > I cannot understand what is wrong in the code. > Kindly guide as its related to my project. Try taking a look at your reset and enable signals. See if they are doing what you expect. -- Rick C From newsfish@newsfish Thu Aug 1 00:43:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!post01.iad!fx08.iad.POSTED!not-for-mail Subject: Re: LFSR doesn't generate random values during simulation Newsgroups: comp.lang.vhdl References: From: Evgeny Filatov User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 122 Message-ID: X-Complaints-To: abuse@usenet-news.net NNTP-Posting-Date: Fri, 04 Aug 2017 18:17:49 UTC Organization: usenet-news.net Date: Fri, 4 Aug 2017 21:17:43 +0300 X-Received-Bytes: 4435 X-Received-Body-CRC: 1396235764 Xref: news.eternal-september.org comp.lang.vhdl:9205 On 04.08.2017 9:13, hamzar105@gmail.com wrote: > I am new to VHDL, but have some idea. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. > > library ieee; > use ieee.std_logic_1164.all; > > --creating a galois LFSR > entity LFSR is > port ( > clk : in std_logic; > rst : in std_logic; > en : in std_logic; > rdm_out : out std_logic_vector(15 downto 0); > rdm_out_a : out std_logic_vector(7 downto 0); > rdm_out_b : out std_logic_vector(7 downto 0); > lfsr_Done : out std_logic --lfsr done > ); > end entity LFSR; > > architecture behavioral of LFSR is > signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' ,others => '0'); --initial value as seed > signal temp_done : std_logic; > > begin > > process (clk, rst) > begin > if rising_edge (clk) then --module operates only when enabled > if (rst = '1') then > temp_out <= (0 => '1' ,others => '0'); > temp_done <= '0'; > > elsif (en = '1') then > temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0); > --temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0); > temp_done <= '1'; > end if; > end if; > end process; > > > rdm_out <= temp_out(15 downto 0); > rdm_out_a <= temp_out(15 downto 8); > rdm_out_b <= temp_out(7 downto 0); > lfsr_Done <= temp_done; > end architecture behavioral;` > > The commented out temp_out is actual feedback (taps are 16,15,13, and 4) as I checked with random taps but still no improvement. > > And the testbench I used is this: > > library ieee; > use ieee.std_logic_1164.all; > > entity lfsr_tb is > end lfsr_tb; > > architecture test_bench of lfsr_tb is > > component LFSR > port ( > clk : in std_logic; > rst : in std_logic; > en : in std_logic; > rdm_out : out std_logic_vector(15 downto 0); > rdm_out_a : out std_logic_vector(7 downto 0); > rdm_out_b : out std_logic_vector(7 downto 0); > lfsr_Done : out std_logic ); > > end component; > > > signal clk1: std_logic; > signal rst1: std_logic; > signal en1 : std_logic; > > signal rdm_out1 : std_logic_vector(15 downto 0); > signal rdm_out_a1 : std_logic_vector(7 downto 0); > signal rdm_out_b1 : std_logic_vector(7 downto 0); > signal lfsr_Done1 : std_logic ; > > begin > > mapping: LFSR port map( > clk => clk1, > rst => rst1, > en => en1, > rdm_out => rdm_out1, > rdm_out_a => rdm_out_a1, > rdm_out_b => rdm_out_b1, > lfsr_Done => lfsr_Done1 ); > > clock: process > begin > clk1 <= '0'; wait for 10 ps; > clk1 <= '1'; wait for 10 ps; > end process; > > reset: process > begin > rst1 <= '1'; wait for 10 ps; > rst1 <= '0'; > en1 <= '1'; wait for 800 ps; > end process; > > end test_bench; > > I cannot understand what is wrong in the code. > Kindly guide as its related to my project. > Why do you think this particular shift register would generate random values? If you have just connected some random taps and expect it to produce a long sequence, you couldn't be more wrong. These sorts of things should be designed, before you implement anything in VHDL. Gene From newsfish@newsfish Thu Aug 1 00:43:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: LFSR doesn't generate random values during simulation Date: Fri, 4 Aug 2017 18:45:48 -0400 Organization: A noiseless patient Spider Lines: 134 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 4 Aug 2017 22:41:40 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="d718d61f80b73a0c00f957784c3c5033"; logging-data="9373"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+NN4iNJ8BRx/pseiIvQeT9" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:49.0) Gecko/20100101 Firefox/49.0 SeaMonkey/2.46 In-Reply-To: Cancel-Lock: sha1:v0oXNeWEZA6wHsOBxySEQj7sLWc= Xref: news.eternal-september.org comp.lang.vhdl:9206 Evgeny Filatov wrote on 8/4/2017 2:17 PM: > On 04.08.2017 9:13, hamzar105@gmail.com wrote: >> I am new to VHDL, but have some idea. I made this LFSR but don't know why >> it is stuck between the initial seed value and the other XOR value. I am >> working with Altera Quartus 16 Lite and ISim. >> >> library ieee; >> use ieee.std_logic_1164.all; >> >> --creating a galois LFSR >> entity LFSR is >> port ( >> clk : in std_logic; >> rst : in std_logic; >> en : in std_logic; >> rdm_out : out std_logic_vector(15 downto 0); >> rdm_out_a : out std_logic_vector(7 downto 0); >> rdm_out_b : out std_logic_vector(7 downto 0); >> lfsr_Done : out std_logic --lfsr done >> ); >> end entity LFSR; >> >> architecture behavioral of LFSR is >> signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' >> ,others => '0'); --initial value as seed >> signal temp_done : std_logic; >> >> begin >> >> process (clk, rst) >> begin >> if rising_edge (clk) then --module operates only when enabled >> if (rst = '1') then >> temp_out <= (0 => '1' ,others => '0'); >> temp_done <= '0'; >> >> elsif (en = '1') then >> temp_out <= temp_out(15 downto 11) & (temp_out(10) xor >> temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & >> temp_out(3 downto 0); >> --temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor >> temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 >> downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0); >> temp_done <= '1'; >> end if; >> end if; >> end process; >> >> >> rdm_out <= temp_out(15 downto 0); >> rdm_out_a <= temp_out(15 downto 8); >> rdm_out_b <= temp_out(7 downto 0); >> lfsr_Done <= temp_done; >> end architecture behavioral;` >> >> The commented out temp_out is actual feedback (taps are 16,15,13, and 4) >> as I checked with random taps but still no improvement. >> >> And the testbench I used is this: >> >> library ieee; >> use ieee.std_logic_1164.all; >> >> entity lfsr_tb is >> end lfsr_tb; >> >> architecture test_bench of lfsr_tb is >> >> component LFSR >> port ( >> clk : in std_logic; >> rst : in std_logic; >> en : in std_logic; >> rdm_out : out std_logic_vector(15 downto 0); >> rdm_out_a : out std_logic_vector(7 downto 0); >> rdm_out_b : out std_logic_vector(7 downto 0); >> lfsr_Done : out std_logic ); >> >> end component; >> >> >> signal clk1: std_logic; >> signal rst1: std_logic; >> signal en1 : std_logic; >> >> signal rdm_out1 : std_logic_vector(15 downto 0); >> signal rdm_out_a1 : std_logic_vector(7 downto 0); >> signal rdm_out_b1 : std_logic_vector(7 downto 0); >> signal lfsr_Done1 : std_logic ; >> >> begin >> >> mapping: LFSR port map( >> clk => clk1, >> rst => rst1, >> en => en1, >> rdm_out => rdm_out1, >> rdm_out_a => rdm_out_a1, >> rdm_out_b => rdm_out_b1, >> lfsr_Done => lfsr_Done1 ); >> >> clock: process >> begin >> clk1 <= '0'; wait for 10 ps; >> clk1 <= '1'; wait for 10 ps; >> end process; >> >> reset: process >> begin >> rst1 <= '1'; wait for 10 ps; >> rst1 <= '0'; >> en1 <= '1'; wait for 800 ps; >> end process; >> >> end test_bench; >> >> I cannot understand what is wrong in the code. >> Kindly guide as its related to my project. >> > > Why do you think this particular shift register would generate random values? > > If you have just connected some random taps and expect it to produce a long > sequence, you couldn't be more wrong. > > These sorts of things should be designed, before you implement anything in > VHDL. There is also the issue of a shift register needing to be shifted to call it a shift register. -- Rick C From newsfish@newsfish Thu Aug 1 00:43:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: LFSR doesn't generate random values during simulation Date: Fri, 4 Aug 2017 23:00:12 -0000 (UTC) Organization: Sonic.net, Inc. Lines: 141 Message-ID: References: Injection-Date: Fri, 4 Aug 2017 23:00:12 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="16db89d60edc80b3ed581e17fe553744"; logging-data="12654"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/l8wCdwMfezAaOaBa2I7n+" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:SPwdRD2e5bk5BtqczV1fs7qvoq4= Xref: news.eternal-september.org comp.lang.vhdl:9207 In article , rickman wrote: >Evgeny Filatov wrote on 8/4/2017 2:17 PM: >> On 04.08.2017 9:13, hamzar105@gmail.com wrote: >>> I am new to VHDL, but have some idea. I made this LFSR but don't know why >>> it is stuck between the initial seed value and the other XOR value. I am >>> working with Altera Quartus 16 Lite and ISim. >>> >>> library ieee; >>> use ieee.std_logic_1164.all; >>> >>> --creating a galois LFSR >>> entity LFSR is >>> port ( >>> clk : in std_logic; >>> rst : in std_logic; >>> en : in std_logic; >>> rdm_out : out std_logic_vector(15 downto 0); >>> rdm_out_a : out std_logic_vector(7 downto 0); >>> rdm_out_b : out std_logic_vector(7 downto 0); >>> lfsr_Done : out std_logic --lfsr done >>> ); >>> end entity LFSR; >>> >>> architecture behavioral of LFSR is >>> signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' >>> ,others => '0'); --initial value as seed >>> signal temp_done : std_logic; >>> >>> begin >>> >>> process (clk, rst) >>> begin >>> if rising_edge (clk) then --module operates only when enabled >>> if (rst = '1') then >>> temp_out <= (0 => '1' ,others => '0'); >>> temp_done <= '0'; >>> >>> elsif (en = '1') then >>> temp_out <= temp_out(15 downto 11) & (temp_out(10) xor >>> temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & >>> temp_out(3 downto 0); >>> --temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor >>> temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 >>> downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0); >>> temp_done <= '1'; >>> end if; >>> end if; >>> end process; >>> >>> >>> rdm_out <= temp_out(15 downto 0); >>> rdm_out_a <= temp_out(15 downto 8); >>> rdm_out_b <= temp_out(7 downto 0); >>> lfsr_Done <= temp_done; >>> end architecture behavioral;` >>> >>> The commented out temp_out is actual feedback (taps are 16,15,13, and 4) >>> as I checked with random taps but still no improvement. >>> >>> And the testbench I used is this: >>> >>> library ieee; >>> use ieee.std_logic_1164.all; >>> >>> entity lfsr_tb is >>> end lfsr_tb; >>> >>> architecture test_bench of lfsr_tb is >>> >>> component LFSR >>> port ( >>> clk : in std_logic; >>> rst : in std_logic; >>> en : in std_logic; >>> rdm_out : out std_logic_vector(15 downto 0); >>> rdm_out_a : out std_logic_vector(7 downto 0); >>> rdm_out_b : out std_logic_vector(7 downto 0); >>> lfsr_Done : out std_logic ); >>> >>> end component; >>> >>> >>> signal clk1: std_logic; >>> signal rst1: std_logic; >>> signal en1 : std_logic; >>> >>> signal rdm_out1 : std_logic_vector(15 downto 0); >>> signal rdm_out_a1 : std_logic_vector(7 downto 0); >>> signal rdm_out_b1 : std_logic_vector(7 downto 0); >>> signal lfsr_Done1 : std_logic ; >>> >>> begin >>> >>> mapping: LFSR port map( >>> clk => clk1, >>> rst => rst1, >>> en => en1, >>> rdm_out => rdm_out1, >>> rdm_out_a => rdm_out_a1, >>> rdm_out_b => rdm_out_b1, >>> lfsr_Done => lfsr_Done1 ); >>> >>> clock: process >>> begin >>> clk1 <= '0'; wait for 10 ps; >>> clk1 <= '1'; wait for 10 ps; >>> end process; >>> >>> reset: process >>> begin >>> rst1 <= '1'; wait for 10 ps; >>> rst1 <= '0'; >>> en1 <= '1'; wait for 800 ps; >>> end process; >>> >>> end test_bench; >>> >>> I cannot understand what is wrong in the code. >>> Kindly guide as its related to my project. >>> >> >> Why do you think this particular shift register would generate random values? >> >> If you have just connected some random taps and expect it to produce a long >> sequence, you couldn't be more wrong. >> >> These sorts of things should be designed, before you implement anything in >> VHDL. > >There is also the issue of a shift register needing to be shifted to call it >a shift register. Also, it looks like OP is initializing the shift registers to all zeros (My VHDL poor). All-zeros LFSRs are usually degenerate-cases which are "stuck" at all zeros. (Primitive polynomial LFSRs have periods of 2^N - 1. Where "N" is the number of bits. The degenerate last state (usually all zeros) wraps around to itself. Regards, Mark From newsfish@newsfish Thu Aug 1 00:43:23 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: LFSR doesn't generate random values during simulation Date: Fri, 4 Aug 2017 20:31:34 -0400 Organization: A noiseless patient Spider Lines: 152 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 5 Aug 2017 00:27:28 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="d718d61f80b73a0c00f957784c3c5033"; logging-data="31543"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+MkaRpjPN0NijowOW1P1ME" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:49.0) Gecko/20100101 Firefox/49.0 SeaMonkey/2.46 In-Reply-To: Cancel-Lock: sha1:2MhVZ9wfLxNsLH/k8LtxV5+NCV8= Xref: news.eternal-september.org comp.lang.vhdl:9208 Mark Curry wrote on 8/4/2017 7:00 PM: > In article , rickman wrote: >> Evgeny Filatov wrote on 8/4/2017 2:17 PM: >>> On 04.08.2017 9:13, hamzar105@gmail.com wrote: >>>> I am new to VHDL, but have some idea. I made this LFSR but don't know why >>>> it is stuck between the initial seed value and the other XOR value. I am >>>> working with Altera Quartus 16 Lite and ISim. >>>> >>>> library ieee; >>>> use ieee.std_logic_1164.all; >>>> >>>> --creating a galois LFSR >>>> entity LFSR is >>>> port ( >>>> clk : in std_logic; >>>> rst : in std_logic; >>>> en : in std_logic; >>>> rdm_out : out std_logic_vector(15 downto 0); >>>> rdm_out_a : out std_logic_vector(7 downto 0); >>>> rdm_out_b : out std_logic_vector(7 downto 0); >>>> lfsr_Done : out std_logic --lfsr done >>>> ); >>>> end entity LFSR; >>>> >>>> architecture behavioral of LFSR is >>>> signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' >>>> ,others => '0'); --initial value as seed >>>> signal temp_done : std_logic; >>>> >>>> begin >>>> >>>> process (clk, rst) >>>> begin >>>> if rising_edge (clk) then --module operates only when enabled >>>> if (rst = '1') then >>>> temp_out <= (0 => '1' ,others => '0'); >>>> temp_done <= '0'; >>>> >>>> elsif (en = '1') then >>>> temp_out <= temp_out(15 downto 11) & (temp_out(10) xor >>>> temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & >>>> temp_out(3 downto 0); >>>> --temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor >>>> temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 >>>> downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0); >>>> temp_done <= '1'; >>>> end if; >>>> end if; >>>> end process; >>>> >>>> >>>> rdm_out <= temp_out(15 downto 0); >>>> rdm_out_a <= temp_out(15 downto 8); >>>> rdm_out_b <= temp_out(7 downto 0); >>>> lfsr_Done <= temp_done; >>>> end architecture behavioral;` >>>> >>>> The commented out temp_out is actual feedback (taps are 16,15,13, and 4) >>>> as I checked with random taps but still no improvement. >>>> >>>> And the testbench I used is this: >>>> >>>> library ieee; >>>> use ieee.std_logic_1164.all; >>>> >>>> entity lfsr_tb is >>>> end lfsr_tb; >>>> >>>> architecture test_bench of lfsr_tb is >>>> >>>> component LFSR >>>> port ( >>>> clk : in std_logic; >>>> rst : in std_logic; >>>> en : in std_logic; >>>> rdm_out : out std_logic_vector(15 downto 0); >>>> rdm_out_a : out std_logic_vector(7 downto 0); >>>> rdm_out_b : out std_logic_vector(7 downto 0); >>>> lfsr_Done : out std_logic ); >>>> >>>> end component; >>>> >>>> >>>> signal clk1: std_logic; >>>> signal rst1: std_logic; >>>> signal en1 : std_logic; >>>> >>>> signal rdm_out1 : std_logic_vector(15 downto 0); >>>> signal rdm_out_a1 : std_logic_vector(7 downto 0); >>>> signal rdm_out_b1 : std_logic_vector(7 downto 0); >>>> signal lfsr_Done1 : std_logic ; >>>> >>>> begin >>>> >>>> mapping: LFSR port map( >>>> clk => clk1, >>>> rst => rst1, >>>> en => en1, >>>> rdm_out => rdm_out1, >>>> rdm_out_a => rdm_out_a1, >>>> rdm_out_b => rdm_out_b1, >>>> lfsr_Done => lfsr_Done1 ); >>>> >>>> clock: process >>>> begin >>>> clk1 <= '0'; wait for 10 ps; >>>> clk1 <= '1'; wait for 10 ps; >>>> end process; >>>> >>>> reset: process >>>> begin >>>> rst1 <= '1'; wait for 10 ps; >>>> rst1 <= '0'; >>>> en1 <= '1'; wait for 800 ps; >>>> end process; >>>> >>>> end test_bench; >>>> >>>> I cannot understand what is wrong in the code. >>>> Kindly guide as its related to my project. >>>> >>> >>> Why do you think this particular shift register would generate random values? >>> >>> If you have just connected some random taps and expect it to produce a long >>> sequence, you couldn't be more wrong. >>> >>> These sorts of things should be designed, before you implement anything in >>> VHDL. >> >> There is also the issue of a shift register needing to be shifted to call it >> a shift register. > > Also, it looks like OP is initializing the shift registers to all zeros (My VHDL poor). > All-zeros LFSRs are usually degenerate-cases which are "stuck" at all zeros. (Primitive > polynomial LFSRs have periods of 2^N - 1. Where "N" is the number of bits. The degenerate > last state (usually all zeros) wraps around to itself. You are correct that there is typically a degenerate state that does not change. But the OP has avoided this trap. if (rst = '1') then temp_out <= (0 => '1' ,others => '0'); This code sets the LS bit to a one and all others a zero. It's been a while since I dug into LFSRs, but I believe there is a form where the all ones state is degenerate, I can't recall exactly. -- Rick C From newsfish@newsfish Thu Aug 1 00:43:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: LFSR doesn't generate random values during simulation Date: Mon, 7 Aug 2017 16:45:16 -0000 (UTC) Organization: Sonic.net, Inc. Lines: 25 Message-ID: References: Injection-Date: Mon, 7 Aug 2017 16:45:16 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c5db2a6a6d051e67463e530f396bb904"; logging-data="21386"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18LQNyQym87FUGkECc72QWJ" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:Vtxq4nSPqcFFWTHsFB7bZn/2L3c= Xref: news.eternal-september.org comp.lang.vhdl:9209 In article , rickman wrote: > >You are correct that there is typically a degenerate state that does not >change. But the OP has avoided this trap. > >if (rst = '1') then > temp_out <= (0 => '1' ,others => '0'); > >This code sets the LS bit to a one and all others a zero. > >It's been a while since I dug into LFSRs, but I believe there is a form >where the all ones state is degenerate, I can't recall exactly. As I said - my VHDL is poor. I never understood that "others" syntax of VHDL. Changing the LFSR feedback from XOR to XNOR will change the degenerate state to all ones. With creative selection of inversions, one could "pick" the degenerate state. There's also a way to take a primitive polynomial LFSR, and achieve the full 2^N period with a little trick (It makes the LFSR non-linear, but that may be just academic...) --Mark From newsfish@newsfish Thu Aug 1 00:43:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: LFSR doesn't generate random values during simulation Date: Mon, 7 Aug 2017 14:25:43 -0400 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 7 Aug 2017 18:21:32 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="085185a7a036ab473c19c301daacb980"; logging-data="13582"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/YG3ajCWKfskKuc26xMQxG" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:49.0) Gecko/20100101 Firefox/49.0 SeaMonkey/2.46 In-Reply-To: Cancel-Lock: sha1:ksO5oR1v3pefkuBLbpW/X5HnzyY= Xref: news.eternal-september.org comp.lang.vhdl:9210 Mark Curry wrote on 8/7/2017 12:45 PM: > In article , rickman wrote: >> >> You are correct that there is typically a degenerate state that does not >> change. But the OP has avoided this trap. >> >> if (rst = '1') then >> temp_out <= (0 => '1' ,others => '0'); >> >> This code sets the LS bit to a one and all others a zero. >> >> It's been a while since I dug into LFSRs, but I believe there is a form >> where the all ones state is degenerate, I can't recall exactly. > > As I said - my VHDL is poor. I never understood that "others" syntax of VHDL. Yeah, I don't program in VHDL every day anymore so I forget a lot from one job to the next and have to spend a few days relearning. I mostly go back to my last job and look at my coding style from then. Aggregate notation is not so hard really. There is the form where positions are defined by the, well *position* of each field in the aggregate, e.g. ('1', '0', "00001") will become "1000001". Named association specifically indicates the position of the assigned bits, e.g. (6 => '1', 5 downto 1 => "00000", 0 => '1'). The use of others to assign a default value requires it to be the last association in the aggregate, e.g. (6 => '1', 0 => '1', others => '0'). I don't believe named and positional association can be mixed in an array. I've read they can be mixed across the items in a record. > Changing the LFSR feedback from XOR to XNOR will change the > degenerate state to all ones. With creative selection > of inversions, one could "pick" the degenerate state. Thanks. > There's also a way to take a primitive polynomial LFSR, > and achieve the full 2^N period with a little trick (It > makes the LFSR non-linear, but that may be just academic...) Yes, I believe it essentially requires detecting a certain state and negating a bit to create the degenerate state. I've seen this in an FPGA design. -- Rick C From newsfish@newsfish Thu Aug 1 00:43:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: LFSR doesn't generate random values during simulation Date: Mon, 7 Aug 2017 19:00:23 -0000 (UTC) Organization: Sonic.net, Inc. Lines: 37 Message-ID: References: Injection-Date: Mon, 7 Aug 2017 19:00:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c5db2a6a6d051e67463e530f396bb904"; logging-data="19763"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19es1B9wglUftd+BDxuagnM" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:La50jDssRGtn0slrIYI93bI+h2M= Xref: news.eternal-september.org comp.lang.vhdl:9211 In article , rickman wrote: >Mark Curry wrote on 8/7/2017 12:45 PM: >> In article , rickman wrote: >>> >>> You are correct that there is typically a degenerate state that does not >>> change. But the OP has avoided this trap. >>> >>> if (rst = '1') then >>> temp_out <= (0 => '1' ,others => '0'); >>> >>> This code sets the LS bit to a one and all others a zero. >>> >>> It's been a while since I dug into LFSRs, but I believe there is a form >>> where the all ones state is degenerate, I can't recall exactly. >> >> As I said - my VHDL is poor. I never understood that "others" syntax of VHDL. > >Yeah, I don't program in VHDL every day anymore so I forget a lot from one >job to the next and have to spend a few days relearning. I mostly go back >to my last job and look at my coding style from then. > >Aggregate notation is not so hard really. There is the form where positions >are defined by the, well *position* of each field in the aggregate, e.g. >('1', '0', "00001") will become "1000001". Named association specifically >indicates the position of the assigned bits, e.g. (6 => '1', 5 downto 1 => >"00000", 0 => '1'). The use of others to assign a default value requires it >to be the last association in the aggregate, e.g. (6 => '1', 0 => '1', >others => '0'). I don't believe named and positional association can be >mixed in an array. I've read they can be mixed across the items in a record. Thanks Rick - I'd missed that the one argument in the assignment is the index of the assigned to variable. Ok, it makes sense now, I guess. Regards, Mark From newsfish@newsfish Thu Aug 1 00:43:25 2024 X-Received: by 10.107.10.37 with SMTP id u37mr7043982ioi.1.1502364054478; Thu, 10 Aug 2017 04:20:54 -0700 (PDT) X-Received: by 10.31.178.139 with SMTP id b133mr67909vkf.18.1502364054410; Thu, 10 Aug 2017 04:20:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!u14no2265966ita.0!news-out.google.com!n39ni790qtf.1!nntp.google.com!s6no2061013qtc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Aug 2017 04:20:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <844d88b0-573a-4587-b6af-2c87e1ea5372@googlegroups.com> Subject: Re: LFSR doesn't generate random values during simulation From: Thomas Stanka Injection-Date: Thu, 10 Aug 2017 11:20:54 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Body-CRC: 4289817050 X-Received-Bytes: 2240 Lines: 49 Xref: news.eternal-september.org comp.lang.vhdl:9212 Am Freitag, 4. August 2017 08:13:24 UTC+2 schrieb hamz...@gmail.com: > temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0); This is no shift register. Temp_out(15 downto 11) will always be in resetvalue (all zero) Shift would have been eg: temp_out <= temp_out(14 downto 0) & Feeback; or temp_out <= Feedback & temp_out(15 downto 1); > clock: process > begin > clk1 <= '0'; wait for 10 ps; > clk1 <= '1'; wait for 10 ps; > end process; Are you serious with 20ps Clock periode? > reset: process > begin > rst1 <= '1'; wait for 10 ps; > rst1 <= '0'; > en1 <= '1'; wait for 800 ps; > end process; I doubt that this process is working as intended. 0 ps: rst = 1 en = U 10 ps: rst = 0 en = 1 800 ps: rst = 1 en = 1 810 ps: rst = 0 en = 1 1610 ps: rst = 1 en = 1 1620 ps: rst = 0 en = 1 bye Thomas From newsfish@newsfish Thu Aug 1 00:43:30 2024 X-Received: by 10.200.3.109 with SMTP id w45mr5618336qtg.23.1517840352837; Mon, 05 Feb 2018 06:19:12 -0800 (PST) X-Received: by 10.31.54.205 with SMTP id d196mr4975498vka.14.1517840352620; Mon, 05 Feb 2018 06:19:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!t22no302088qtb.0!news-out.google.com!h12ni178qte.0!nntp.google.com!t22no302086qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Feb 2018 06:19:12 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e4792e2-bb27-45db-a6d6-773762460de7@googlegroups.com> Subject: Re: Microsemi Libero on Linux From: Thomas Stanka Injection-Date: Mon, 05 Feb 2018 14:19:12 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1472 X-Received-Body-CRC: 2075766651 Lines: 7 Xref: reader02.eternal-september.org comp.lang.vhdl:9290 Am Dienstag, 30. Januar 2018 00:27:12 UTC+1 schrieb Rob Gaddi: > Has anyone else had serious stability problems trying to get Microsemi > Libero working under Linux? I started with a day of grief from FlexLM, I never tried to control JTAG programmer. The designer itself was working fine, if you accept worse performance than under windows, as it is native windows ported to Linux. bye, Thomas From newsfish@newsfish Thu Aug 1 00:43:30 2024 X-Received: by 10.233.235.194 with SMTP id b185mr4757546qkg.32.1519299529448; Thu, 22 Feb 2018 03:38:49 -0800 (PST) X-Received: by 10.31.182.77 with SMTP id g74mr774391vkf.12.1519299529185; Thu, 22 Feb 2018 03:38:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer03.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!q21no2098861qtn.1!news-out.google.com!m4ni8456qte.0!nntp.google.com!y7no2093981qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Feb 2018 03:38:48 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> Subject: simple unsigned maths problem with if statement From: David Perry Injection-Date: Thu, 22 Feb 2018 11:38:49 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 28 X-Received-Bytes: 1876 X-Received-Body-CRC: 824789500 Xref: reader02.eternal-september.org comp.lang.vhdl:9291 I'm having an issue with a simple if statement: if ClampIn_u + DMD_u < x"FFFF" then --this doesn't work :( ClampIn_u := ClampIn_u + DMD_u; else ClampIn_u := x"FFFF"; end if; What happens is the addition always occurs, I end up overflowing and I get the wrong result. I tried making the right hand side of the if bigger in attempt to make it work: if ClampIn_u + DMD_u < x"0FFFF" then but that fails in the same way. If I rearrange the maths (subtract DMD_u from both sides): if ClampIn_u < x"FFFF" - DMD_u then this works. DMD_u is an unsigned 16 bit signal, ClampIn_u is an unsigned 16 bit variable. I'm struggling to find an explanation, I can see why my original might fail but I would have expected "0FFFF" to work. Any insight would be appreciated :) Dave From newsfish@newsfish Thu Aug 1 00:43:31 2024 X-Received: by 10.55.161.88 with SMTP id k85mr4727700qke.61.1519304050767; Thu, 22 Feb 2018 04:54:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.alt.net!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!y7no2153032qtn.0!news-out.google.com!o9ni7781qte.1!nntp.google.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!post01.iad!fx34.iad.POSTED!not-for-mail Subject: Re: simple unsigned maths problem with if statement Newsgroups: comp.lang.vhdl References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> From: Richard Damon User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> Lines: 39 Message-ID: X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Thu, 22 Feb 2018 07:54:09 -0500 X-Received-Bytes: 2195 X-Received-Body-CRC: 3362115339 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Original-Bytes: 2051 Xref: reader02.eternal-september.org comp.lang.vhdl:9292 On 2/22/18 6:38 AM, David Perry wrote: > I'm having an issue with a simple if statement: > > if ClampIn_u + DMD_u < x"FFFF" then --this doesn't work :( > ClampIn_u := ClampIn_u + DMD_u; > else > ClampIn_u := x"FFFF"; > end if; > > What happens is the addition always occurs, I end up overflowing and I get the wrong result. > > I tried making the right hand side of the if bigger in attempt to make it work: > > if ClampIn_u + DMD_u < x"0FFFF" then > > but that fails in the same way. > > If I rearrange the maths (subtract DMD_u from both sides): > > if ClampIn_u < x"FFFF" - DMD_u then > > this works. > > DMD_u is an unsigned 16 bit signal, ClampIn_u is an unsigned 16 bit variable. > > I'm struggling to find an explanation, I can see why my original might fail but I would have expected "0FFFF" to work. > > Any insight would be appreciated :) > > Dave > A 16 bit unsigned + a 16 bit unsigned will do the arithmetic in 16 bits, and ignore the overflow/carry out. Making the right hand side bigger doesn't affect how the left hand side is computed. If you coerced the signals on the left hand side to be 17 bit signals (by concatenating a higher order 0 bit), then the arithmetic would produce the needed value, and the comparison would work. From newsfish@newsfish Thu Aug 1 00:43:31 2024 X-Received: by 10.55.155.132 with SMTP id d126mr4955275qke.54.1519311205171; Thu, 22 Feb 2018 06:53:25 -0800 (PST) X-Received: by 10.31.178.81 with SMTP id b78mr218471vkf.14.1519311205000; Thu, 22 Feb 2018 06:53:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!q21no2261961qtn.1!news-out.google.com!m4ni8510qte.0!nntp.google.com!y7no2256655qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Feb 2018 06:53:24 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: simple unsigned maths problem with if statement From: David Perry Injection-Date: Thu, 22 Feb 2018 14:53:25 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Body-CRC: 556763989 X-Received-Bytes: 2191 Xref: reader02.eternal-september.org comp.lang.vhdl:9293 I see, my assumptions were incorrect. So something like: MyTemp17b_u := ClampIn_u + DMD_u; --a 17bit unsigned variable if MyTemp17b_u < x"FFFF" then ClampIn_u := ClampIn_u + DMD_u; else ClampIn_u := x"FFFF"; end if; I could perhaps then use that extra bit to my advantage by testing that rather than the whole result? Such as: if MyTemp17b_u(16) = '0' then --check the overflow bit And would I be best re-using the result and just copying the lower 16 bits, I suspect it might create a second addition otherwise, so I end up with: MyTemp17b_u := ClampIn_u + DMD_u; --a 17bit unsigned variable if MyTemp17b_u(16) = '0' then --check the overflow bit ClampIn_u := MyTemp17b_u(15 downto 0); else ClampIn_u := x"FFFF"; end if; I don't actually need to be gate efficient with what I'm playing with, but it's interesting to fiddle with :) Appreciate the time Richard, cheers. Dave From newsfish@newsfish Thu Aug 1 00:43:31 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!post01.iad!fx14.iad.POSTED!not-for-mail Subject: Re: simple unsigned maths problem with if statement Newsgroups: comp.lang.vhdl References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> From: Richard Damon User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 36 Message-ID: X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Fri, 23 Feb 2018 19:43:28 -0500 X-Received-Bytes: 2335 X-Received-Body-CRC: 279329742 X-Original-Bytes: 2191 Xref: reader02.eternal-september.org comp.lang.vhdl:9294 On 2/22/18 9:53 AM, David Perry wrote: > I see, my assumptions were incorrect. > So something like: > > MyTemp17b_u := ClampIn_u + DMD_u; --a 17bit unsigned variable > if MyTemp17b_u < x"FFFF" then > ClampIn_u := ClampIn_u + DMD_u; > else > ClampIn_u := x"FFFF"; > end if; > > I could perhaps then use that extra bit to my advantage by testing that rather than the whole result? Such as: > > if MyTemp17b_u(16) = '0' then --check the overflow bit > > And would I be best re-using the result and just copying the lower 16 bits, I suspect it might create a second addition otherwise, so I end up with: > > MyTemp17b_u := ClampIn_u + DMD_u; --a 17bit unsigned variable > if MyTemp17b_u(16) = '0' then --check the overflow bit > ClampIn_u := MyTemp17b_u(15 downto 0); > else > ClampIn_u := x"FFFF"; > end if; > > I don't actually need to be gate efficient with what I'm playing with, but it's interesting to fiddle with :) > > Appreciate the time Richard, cheers. > Dave > I am not an expert here, but my first expectation would be that the term ClampIn_u + DMD_u would still be done to 16 bit here, and then that 16 bit result extended to 17 (but I would admit I might be wrong). I would extend ClampIn_u and DMD_u to 17 bits first, and then add them (preferably saving the 17 bit result for reuse). From newsfish@newsfish Thu Aug 1 00:43:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp1-2.free.fr!not-for-mail Subject: Re: simple unsigned maths problem with if statement Newsgroups: comp.lang.vhdl References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> From: Nicolas Matringe Date: Sun, 25 Feb 2018 23:59:49 +0100 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr-classic Content-Transfer-Encoding: 7bit Lines: 14 Message-ID: <5a933fe5$0$9282$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Feb 2018 23:59:49 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1519599589 news-2.free.fr 9282 88.185.146.198:20559 X-Complaints-To: abuse@proxad.net Xref: reader02.eternal-september.org comp.lang.vhdl:9295 On 24.02.2018 01:43, Richard Damon wrote: [...] > I am not an expert here, but my first expectation would be that the term > ClampIn_u + DMD_u would still be done to 16 bit here, and then that 16 > bit result extended to 17 (but I would admit I might be wrong). > > I would extend ClampIn_u and DMD_u to 17 bits first, and then add them > (preferably saving the 17 bit result for reuse). That's correct. However you only need to extend one operand to 17 bits to force the result to 17 bits (though extending both works just as well but requires a bit more typing) Nicolas From newsfish@newsfish Thu Aug 1 00:43:32 2024 X-Received: by 10.200.69.19 with SMTP id q19mr7561790qtn.45.1519635465870; Mon, 26 Feb 2018 00:57:45 -0800 (PST) X-Received: by 10.31.178.81 with SMTP id b78mr1048393vkf.14.1519635465648; Mon, 26 Feb 2018 00:57:45 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feed.usenet.farm!feeder4.feed.usenet.farm!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!r16no340067qtn.1!news-out.google.com!o9ni8431qte.1!nntp.google.com!r16no340064qtn.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Feb 2018 00:57:45 -0800 (PST) In-Reply-To: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <50cdca20-3189-4cd3-99d4-2b605cb91d2d@googlegroups.com> Subject: Re: simple unsigned maths problem with if statement From: David Perry Injection-Date: Mon, 26 Feb 2018 08:57:45 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 9 Xref: reader02.eternal-september.org comp.lang.vhdl:9296 OK, how about: MyTemp17b_u := '0' & ClampIn_u; MyTemp17b_u := MyTemp17b_u + DMD_u; I think I need to put the: '0' & in there as I have experienced what I can only describe as "filling from the left", something else I've struggled to understand :( Cheers, Dave From newsfish@newsfish Thu Aug 1 00:43:32 2024 X-Received: by 10.233.232.139 with SMTP id a133mr7411204qkg.25.1519643942908; Mon, 26 Feb 2018 03:19:02 -0800 (PST) X-Received: by 10.31.67.71 with SMTP id q68mr1077828vka.9.1519643942592; Mon, 26 Feb 2018 03:19:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feed.usenet.farm!feeder3.feed.usenet.farm!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!r16no406135qtn.1!news-out.google.com!m4ni9101qte.0!nntp.google.com!t24no2085111qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Feb 2018 03:19:02 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=105.155.60.241; posting-account=WDdpCQoAAABPyxHNTvrAHX_Qy49ir8fM NNTP-Posting-Host: 105.155.60.241 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> Subject: read binary file in VHDL From: elmakhloufi assaad Injection-Date: Mon, 26 Feb 2018 11:19:02 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 1 Xref: reader02.eternal-september.org comp.lang.vhdl:9297 I want to get access and read binary file content pixel of image from ENVI logiciel :size (100*100) pixel coded each pixel in 16 bits in vhdl.any idea or advice ? From newsfish@newsfish Thu Aug 1 00:43:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: simple unsigned maths problem with if statement Date: Mon, 26 Feb 2018 08:34:45 -0800 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> <50cdca20-3189-4cd3-99d4-2b605cb91d2d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 26 Feb 2018 16:34:46 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="1098c0f079547608dd0830b07f2d3f59"; logging-data="26218"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/igbQP5piOUElInk0Y8Okp" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 In-Reply-To: <50cdca20-3189-4cd3-99d4-2b605cb91d2d@googlegroups.com> Content-Language: en-US Cancel-Lock: sha1:VDXpgCqF0L4d6X4+CBVJ2VW9ueA= Xref: reader02.eternal-september.org comp.lang.vhdl:9298 On 02/26/2018 12:57 AM, David Perry wrote: > OK, how about: > MyTemp17b_u := '0' & ClampIn_u; > MyTemp17b_u := MyTemp17b_u + DMD_u; > > I think I need to put the: > '0' & > in there as I have experienced what I can only describe as "filling from the left", something else I've struggled to understand :( > > Cheers, > Dave > Well then write it this way to do precisely the same thing: MyTemp17b_u := RESIZE(ClampIn_u, 17) MyTemp17b_u := MyTemp17b_u + DMD_u; You have an unsigned value in 16 bits; it's between 0-65535. You can put as many zeros on as many additional MSBs as you like, which changes the number of bits you're using to represent it, but the value there is still 0-65535, the same as in decimal 10, 010, and 000010 all represent the number between 9 and 11. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:43:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp3-2.free.fr!not-for-mail Subject: Re: read binary file in VHDL Newsgroups: comp.lang.vhdl References: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> From: Nicolas Matringe Date: Mon, 26 Feb 2018 22:17:44 +0100 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr-classic Content-Transfer-Encoding: 7bit Lines: 11 Message-ID: <5a947978$0$31643$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 26 Feb 2018 22:17:44 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1519679864 news-1.free.fr 31643 88.185.146.198:28755 X-Complaints-To: abuse@proxad.net Xref: reader02.eternal-september.org comp.lang.vhdl:9299 On 26.02.2018 12:19, elmakhloufi assaad wrote: > I want to get access and read binary file content pixel of image from ENVI logiciel :size (100*100) pixel coded each pixel in 16 bits in vhdl.any idea or advice ? > Keep in mind that this can only work in simulation. There are plenty of examples on how to access files with VHDL, Google is definitely your friend here. http://lmgtfy.com/?iie=1&q=read+binary+files+vhdl Nicolas From newsfish@newsfish Thu Aug 1 00:43:33 2024 X-Received: by 10.55.33.197 with SMTP id f66mr9548808qki.59.1519710075939; Mon, 26 Feb 2018 21:41:15 -0800 (PST) X-Received: by 10.31.169.211 with SMTP id s202mr644372vke.4.1519710075739; Mon, 26 Feb 2018 21:41:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!t24no88454qtn.0!news-out.google.com!o9ni48qte.1!nntp.google.com!r16no86405qtn.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Feb 2018 21:41:15 -0800 (PST) In-Reply-To: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.129.100.75; posting-account=n7aJ0QoAAAAM9S9cFo4hml0ohYBnwXyL NNTP-Posting-Host: 213.129.100.75 References: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: read binary file in VHDL From: andrew_b Injection-Date: Tue, 27 Feb 2018 05:41:15 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Body-CRC: 167928224 X-Received-Bytes: 2269 Lines: 46 Xref: reader02.eternal-september.org comp.lang.vhdl:9300 On 26.02.2018 12:19, elmakhloufi assaad wrote: > I want to get access and read binary file content pixel of image from ENVI logiciel :size (100*100) pixel coded each pixel in 16 bits in vhdl.any idea or advice ? Here is my example: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity binary is end binary; architecture rtl of binary is signal s : std_logic_vector (7 downto 0); begin process subtype byte is character; type binfile is file of byte; file f : binfile; variable b : byte; begin s <= (others => '0'); wait for 10 ns; File_Open (f, "util.o", read_mode); while (not EndFile (f)) loop Read (f, b); s <= std_logic_vector (to_unsigned (byte'pos(b), s'length)); wait for 10 ns; end loop; File_Close (f); wait for 10 ns; s <= (others => '0'); wait; -- forever end process; end rtl; From newsfish@newsfish Thu Aug 1 00:43:34 2024 X-Received: by 10.200.40.80 with SMTP id 16mr10347725qtr.42.1519731344638; Tue, 27 Feb 2018 03:35:44 -0800 (PST) X-Received: by 10.31.2.74 with SMTP id 71mr1429774vkc.6.1519731344226; Tue, 27 Feb 2018 03:35:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!r16no234132qtn.1!news-out.google.com!o9ni65qte.1!nntp.google.com!t24no236971qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Feb 2018 03:35:43 -0800 (PST) In-Reply-To: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.249.74.131; posting-account=WDdpCQoAAABPyxHNTvrAHX_Qy49ir8fM NNTP-Posting-Host: 41.249.74.131 References: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: read binary file in VHDL From: elmakhloufi assaad Injection-Date: Tue, 27 Feb 2018 11:35:44 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Body-CRC: 826950116 X-Received-Bytes: 1663 Lines: 6 Xref: reader02.eternal-september.org comp.lang.vhdl:9301 Le lundi 26 f=C3=A9vrier 2018 11:19:07 UTC, elmakhloufi assaad a =C3=A9crit= =C2=A0: > I want to get access and read binary file content pixel of image from E= NVI logiciel :size (100*100) pixel coded each pixel in 16 bits in vhdl.any = idea or advice ? @andrew_b thankyou for this exemple , when i simulate this code with my bi= nary file the message : he coldnt open file?=20 From newsfish@newsfish Thu Aug 1 00:43:34 2024 X-Received: by 10.55.49.193 with SMTP id x184mr10581130qkx.14.1519731788135; Tue, 27 Feb 2018 03:43:08 -0800 (PST) X-Received: by 10.31.48.198 with SMTP id w189mr1429934vkw.1.1519731787354; Tue, 27 Feb 2018 03:43:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!t24no240209qtn.0!news-out.google.com!m4ni73qte.0!nntp.google.com!r16no237255qtn.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Feb 2018 03:43:07 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.249.74.131; posting-account=WDdpCQoAAABPyxHNTvrAHX_Qy49ir8fM NNTP-Posting-Host: 41.249.74.131 References: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: read binary file in VHDL From: elmakhloufi assaad Injection-Date: Tue, 27 Feb 2018 11:43:08 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1932 X-Received-Body-CRC: 2374404955 Lines: 14 Xref: reader02.eternal-september.org comp.lang.vhdl:9302 Le mardi 27 f=C3=A9vrier 2018 11:35:49 UTC, elmakhloufi assaad a =C3=A9crit= =C2=A0: > Le lundi 26 f=C3=A9vrier 2018 11:19:07 UTC, elmakhloufi assaad a =C3=A9cr= it=C2=A0: > > I want to get access and read binary file content pixel of image from= ENVI logiciel :size (100*100) pixel coded each pixel in 16 bits in vhdl.an= y idea or advice ? > @andrew_b thankyou for this exemple , when i simulate this code with my = binary file the message : he coldnt open file? Could not read binary file C:\Users\hp\Desktop\file\vhdl.txt., because it was not written by Xilinx Simulator Simulation stopped when executing process: binary.vhd:14 on line 26 in file "C:/Xilinx92i/ENVI_read/binary.vhd" From newsfish@newsfish Thu Aug 1 00:43:34 2024 X-Received: by 10.237.62.25 with SMTP id l25mr8378824qtf.53.1519742130505; Tue, 27 Feb 2018 06:35:30 -0800 (PST) X-Received: by 10.31.67.71 with SMTP id q68mr1478399vka.9.1519742130235; Tue, 27 Feb 2018 06:35:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!r16no328144qtn.1!news-out.google.com!m4ni108qte.0!nntp.google.com!t24no331363qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Feb 2018 06:35:29 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.171.128.174; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 108.171.128.174 References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> <50cdca20-3189-4cd3-99d4-2b605cb91d2d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: simple unsigned maths problem with if statement From: David Perry Injection-Date: Tue, 27 Feb 2018 14:35:30 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Body-CRC: 3251541759 X-Received-Bytes: 1354 Lines: 0 Xref: reader02.eternal-september.org comp.lang.vhdl:9303 Ah, I forgot about resize! Thanks Rob From newsfish@newsfish Thu Aug 1 00:43:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: read binary file in VHDL Date: Sat, 3 Mar 2018 19:37:13 -0600 Organization: A noiseless patient Spider Lines: 23 Message-ID: References: <5eaa4dec-21ca-4e59-81aa-d5f404b1794d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Sun, 4 Mar 2018 01:37:14 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="009b5ed13f656a1b023b445a7052f76a"; logging-data="29714"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19kj6bHQby1LpHZG1Aaob+wr0ygHNFA+wA=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:vcEpV9C2g5QsyY7+36kv/wJ31Jg= Xref: reader02.eternal-september.org comp.lang.vhdl:9304 On 2018-02-27 05:43, elmakhloufi assaad wrote: > Le mardi 27 février 2018 11:35:49 UTC, elmakhloufi assaad a écrit : >> Le lundi 26 février 2018 11:19:07 UTC, elmakhloufi assaad a écrit : >>> I want to get access and read binary file content pixel of image from ENVI logiciel :size (100*100) pixel coded each pixel in 16 bits in vhdl.any idea or advice ? >> @andrew_b thankyou for this exemple , when i simulate this code with my binary file the message : he coldnt open file? > Could not read binary file > C:\Users\hp\Desktop\file\vhdl.txt., because it was not written by Xilinx > Simulator > Simulation stopped when executing process: binary.vhd:14 > on line 26 in file "C:/Xilinx92i/ENVI_read/binary.vhd" > Try using vhdl-93 file_open syntax. Also, try fully qualifying the file name. Also, make sure the vhdl is compiled with the vhdl-93 option. (Or later. The file_open syntax was changed between vhdl-87 and vhdl-93. Also, vhdl-87 defined only 128 values for the character data type; vhdl-93 defined all 256 possible values for a byte.) VARIABLE open_status : file_open_status; File_Open (open_status, f, "fully_qualified_filename", read_mode); From newsfish@newsfish Thu Aug 1 00:43:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: john Newsgroups: comp.lang.vhdl Subject: Re: VHDL-2008 first steps and simulator for Linux Date: Thu, 8 Mar 2018 17:16:49 -0000 Organization: Aioe.org NNTP Server Lines: 47 Message-ID: References: NNTP-Posting-Host: gxlAB53gbUKRBUWgXK4Mvg.user.gioia.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: MicroPlanet-Gravity/3.0.4 X-Notice: Filtered by postfilter v. 0.8.3 Xref: reader02.eternal-september.org comp.lang.vhdl:9306 In article , gof@somewhere.invalid says... > 3. What simulators do you use or recommend? I prefer Linux ones (it would > be much easier for me), but if there are no reasonable ones, I can use > Windows ones as well. I want them only to test and simulate my code > snippets during learning. My final goal is to be able to make models > suitable for synthesis and upload into CPLD and FPGA devices. > > Thank you! > Hi Adam I recently started learning VHDL myself - I bought a couple of top end books and found them not to be good to learn from. The example you are doing seems a popular one - take a look around the net - I have an adder here I built starting from a similar example. If you are doing this as serious as it sounds I'd recommend you go get the Xilinx webpack release of Vivado.(Free to use but FPGA chip limited) The limitations are mostly irrelevant when learning and can be ignored. Its a mostly full toolchain with tons of documentation. Dont be put off though - just work with your RTL files to start. Then play with the provided IP when you are ready. You get some example projects to load and play with too so you can see how it all works right through the process. I find doing that helps to learn even when I dont really understand much as I step though initially. It runs identical on windows and linux (I have it on Centos-7 at the moment.) I think ir runs on Suse and of course red-hat and probably any other spin offs (scientific would probably work fine too. You dont need a massive system to run it but I do recommend more that 4GB ram (Some stuff will run in that but you can have a problem sometimes) The application isnt all that power hungry. As you can see - I'm a bit of a fan after using it a short while(but I did have probelms with windows at first so I'd say stick with linux) The forum is quite active and helpful too. -- john ========================= http://johntech.co.uk ========================= From newsfish@newsfish Thu Aug 1 00:43:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: VHDL-2008 first steps and simulator for Linux Date: Thu, 8 Mar 2018 09:53:27 -0800 Organization: A noiseless patient Spider Lines: 69 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 8 Mar 2018 17:53:29 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="5599e4475a0cd39123c5374ea0d0c40a"; logging-data="30329"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19zGbsh9gRTTf+mUxXWLafV" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 In-Reply-To: Content-Language: en-US Cancel-Lock: sha1:1i0S9FPVcoJhUZcVZom1AQoM/HY= Xref: reader02.eternal-september.org comp.lang.vhdl:9307 On 03/08/2018 04:54 AM, Adam Wysocki wrote: > [snip] > > #v+ $ fauhdlc ch1-10.vhdl ERROR> ch1-10.vhdl:8: Symbol '5ns' > undefined. ERROR> ch1-10.vhdl:10: Symbol '5ns' undefined. #v- > 5 ns. The space matters. > and after commenting it out says something similar to gvhdl: > > #v+ $ fauhdlc ch1-10.vhdl ERROR> ch1-10.vhdl:7: Type error for > . #v- > > I understand that the statement "if sel then" is invalid for 'sel' > being a bit type, and not a boolean type. > > This leads to my questions: > > 1. What am I doing wrong? Is it illegal to compare bits this way, or > is it legal only since a certain VHDL language version? The book says > that it's legal, but examples from the book fail with similar > messages. > > 2. I don't know the VHDL version simulated by these two simulators, > and if they support VHDL-2008 or not. I read that comments /* ... */ > are illegal in VHDL versions prior to 2008, so I tried them in these > simulators and they complained, so I guess they support an older VHDL > version. > > I don't see any option to switch them to the 2008 version. > That's only supported in VHDL-2008, earlier you have to use if sel = '1' then. For GHDL you can run ghdl --options-help to be told that if you want to use VHDL-2008 you need to compile (analyze) using the --std=08 argument. If you're going to use GHDL, for projects of any kind of size (like 3 files). I strongly recommend setting up a Makefile or using VUnit. > 3. What simulators do you use or recommend? I prefer Linux ones (it > would be much easier for me), but if there are no reasonable ones, I > can use Windows ones as well. I want them only to test and simulate > my code snippets during learning. My final goal is to be able to make > models suitable for synthesis and upload into CPLD and FPGA devices. > > Thank you! > The price is certainly right on GHDL, and Tristan works crazy hard on it. As such it's actually got some of the most rigorous 2008 support out there. I use it at home, and it definitely gets the job done. It also definitely teaches you about rigor and the importance of self-checking testbenches, since the integration with gtkwave for actually graphically poking about is a pain. GHDL you will quickly find you want your designs to be right the first time rather than having to go spelunking. And that's not a bad thing. But it's a pain. You're learning to drive on a high-performance vehicle with a hair-trigger clutch, and you probably want a Toyota instead. Professionally I use ModelSim DE, which is the sort of decision you can make when it's the company footing the bill rather than your own pocket. It makes life easy. For what you're doing, you can probably get away with the free simulators provided by whichever FPGA you decide you want to target first. Xilinx's has a proprietary thing and Altera and Microsemi both provide Modelsim (and I think Lattice as well); they all work on Linux. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:43:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!news.nask.pl!news.nask.org.pl!newsfeed2.atman.pl!newsfeed.atman.pl!.POSTED!not-for-mail From: gof@somewhere.invalid (Adam Wysocki) Newsgroups: comp.lang.vhdl Subject: Re: VHDL-2008 first steps and simulator for Linux Date: Mon, 12 Mar 2018 09:30:35 +0000 (UTC) Organization: ATMAN - ATM S.A. Lines: 111 Message-ID: References: NNTP-Posting-Host: vps.chmurka.net X-Trace: node2.news.atman.pl 1520847035 23180 81.4.124.88 (12 Mar 2018 09:30:35 GMT) X-Complaints-To: usenet@atman.pl NNTP-Posting-Date: Mon, 12 Mar 2018 09:30:35 +0000 (UTC) User-Agent: tin/2.4.1-20161224 ("Daill") (UNIX) (Linux/4.4.50-v7+ (armv7l)) Cancel-Lock: sha1:ggT2HeSW19I2+84nZHD2gY+X0X0= Xref: reader02.eternal-september.org comp.lang.vhdl:9308 Rob Gaddi wrote: >> #v+ $ fauhdlc ch1-10.vhdl ERROR> ch1-10.vhdl:8: Symbol '5ns' >> undefined. ERROR> ch1-10.vhdl:10: Symbol '5ns' undefined. #v- > > 5 ns. The space matters. Thanks. >> I don't see any option to switch them to the 2008 version. > > That's only supported in VHDL-2008, earlier you have to use if sel = '1' > then. For GHDL you can run ghdl --options-help to be told that if you > want to use VHDL-2008 you need to compile (analyze) using the --std=08 > argument. If you're going to use GHDL, for projects of any kind of size > (like 3 files). I strongly recommend setting up a Makefile or using VUnit. Thanks, I tried ghdl... but I got stuck at trying to run my test bench: #v+ entity test_bench is end entity test_bench; architecture test_mux2 of test_bench is signal a, b, sel, z: bit; begin dut: entity work.mux2(mux2_behav) port map (a, b, sel, z); stimulus: process is begin report "test start"; a <= '0'; b <= '1'; sel <= '0'; wait for 20 ns; assert z = '0'; sel <= '1'; wait for 20 ns; assert z = '1'; a <= '1'; b <= '0'; sel <= '0'; wait for 20 ns; assert z = '1'; sel <= '1'; wait for 20 ns; assert z = '0'; report "test end"; wait; end process stimulus; end architecture test_mux2; #v- ghdl -c --std=08 ch1-10.vhdl -r test_bench This command got stuck 100% CPU usage and didn't print anything. After giving more options for verbosity: ghdl -c --std=08 ch1-10.vhdl -r test_bench --assert-level=note \ --stop-time=10ms --trace-signals --disp-time --trace-processes --stats \ --disp-order --disp-sources --disp-sig-types --disp-signals-map \ --disp-signals-table --checks --activity=all it printed some diagnostic info, but still I can't find the 'z' signal there... #v+ .test_bench(test_mux2).a: 000000000281F380 net: -2 +A .test_bench(test_mux2).b: 000000000281F270 net: -2 +A .test_bench(test_mux2).sel: 000000000281F160 net: -2 +A .test_bench(test_mux2).z: 000000000281F050 net: -1 +A .test_bench(test_mux2).dut@mux2(mux2_behav).a: 000000000281F380 net: -2 +A .test_bench(test_mux2).dut@mux2(mux2_behav).b: 000000000281F270 net: -2 +A .test_bench(test_mux2).dut@mux2(mux2_behav).sel: 000000000281F160 net: -2 +A .test_bench(test_mux2).dut@mux2(mux2_behav).z: 000000000281F050 net: -1 +A 0: 000000000281F380 +A net: -2 smode: signal #prt: 0 #drv: 1 1: 000000000281F270 +A net: -2 smode: signal #prt: 0 #drv: 1 2: 000000000281F160 +A net: -2 smode: signal #prt: 0 #drv: 1 3: 000000000281F050 +A net: -1 smode: signal #prt: 0 #drv: 1 1: end run process .test_bench(test_mux2).dut@mux2(mux2_behav).mux2 [00000000027B62A0] #v- I guess it never runs the "stimulus" process, only the "dut" process... I feel I'm still missing the big picture here. > You're learning to drive on a high-performance vehicle with a > hair-trigger clutch, and you probably want a Toyota instead. You mean VHDL? Or using ghdl? > For what you're doing, you can probably get away with the free > simulators provided by whichever FPGA you decide you want to target > first. I was thinking about Lattice's CPLD LC4064 (ispMACH), because it's affordable and has enough I/O pins to not feel too limited... > Xilinx's has a proprietary thing and Altera and Microsemi both provide > Modelsim (and I think Lattice as well); they all work on Linux. Thanks, I'll take a look. -- [ Adam Wysocki :: Warsaw, Poland ] [ Email: a@b a=grp b=chmurka.net ] [ Web: http://www.chmurka.net/ ] From newsfish@newsfish Thu Aug 1 00:43:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: VHDL-2008 first steps and simulator for Linux Date: Mon, 12 Mar 2018 15:02:01 -0500 Organization: A noiseless patient Spider Lines: 23 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 12 Mar 2018 20:02:02 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="c0da5bb26672d69a66f0a68440cbad1d"; logging-data="26689"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CrKEbNV0C3YjO1MTq8ICw5CFvge/8BMc=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 In-Reply-To: Cancel-Lock: sha1:M0ixYNqbQsMNbhGsLL4frVqKsps= Xref: reader02.eternal-september.org comp.lang.vhdl:9309 On 2018-03-08 06:54, Adam Wysocki wrote: > mux2: process is begin > if sel then > z <= b after 5ns; > else > z <= a after 5ns; > end if; > end process mux2; Your mux2 process needs a sensitivity list. mux2: process(a, b, sel) is begin if sel='1' then z <= b after 5 ns; else z <= a after 5 ns; end if; end process mux2; Or, you could just code it in one line like this: z <= (a and not sel) or (b and sel) after 5 ns; Charles Bailey From newsfish@newsfish Thu Aug 1 00:43:36 2024 X-Received: by 10.55.48.68 with SMTP id w65mr1176199qkw.10.1521207560074; Fri, 16 Mar 2018 06:39:20 -0700 (PDT) X-Received: by 10.31.174.9 with SMTP id x9mr157012vke.10.1521207559477; Fri, 16 Mar 2018 06:39:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!j23no53199qtl.0!news-out.google.com!c39ni832qta.0!nntp.google.com!j23no53195qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Mar 2018 06:39:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.221.49.79; posting-account=Lh4KdAoAAABJAvlW3aC8TUlS8p2qtXo_ NNTP-Posting-Host: 117.221.49.79 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <780b55ce-ba9c-482d-90fb-fc4666be02d2@googlegroups.com> Subject: study and analysis on binary offset carrier modulation in satellite navigation systems From: joseph vishal kumar Injection-Date: Fri, 16 Mar 2018 13:39:20 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 0 X-Received-Bytes: 1296 X-Received-Body-CRC: 2375236450 Xref: reader02.eternal-september.org comp.lang.vhdl:9310 how to write code for divide down to data message rate , data message generator, spreading code generator, square wave generator multiply upto code rate and multiply upto subcarrier frequence in vhdl From newsfish@newsfish Thu Aug 1 00:43:37 2024 X-Received: by 10.200.6.140 with SMTP id f12mr18328635qth.16.1521810764313; Fri, 23 Mar 2018 06:12:44 -0700 (PDT) X-Received: by 10.31.149.199 with SMTP id x190mr3480986vkd.11.1521810764098; Fri, 23 Mar 2018 06:12:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!paganini.bofh.team!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!k53no78204qtc.1!news-out.google.com!c39ni762qta.0!nntp.google.com!j23no962289qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 23 Mar 2018 06:12:43 -0700 (PDT) In-Reply-To: <6287bu$e2c@news.or.intel.com>#1/1> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.156.81.9; posting-account=VnMF6AoAAACQ1z7CznEFosPucd9Pdi5M NNTP-Posting-Host: 197.156.81.9 References: <6287bu$e2c@news.or.intel.com>#1/1> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Peter Ashenden's DP32 code From: hajaman3@gmail.com Injection-Date: Fri, 23 Mar 2018 13:12:44 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 16 Xref: reader02.eternal-september.org comp.lang.vhdl:9311 On Friday, October 17, 1997 at 10:00:00 AM UTC+3, Scott L Baker wrote: > >>Hi, > >> > >>I'm looking for a compilable version of the PD32 processor > >>described in Peter Ashenden's VHDL cookbook. I have the > >>Word dooument which I could convert to text and extract > >>the VHDL, but I was hoping that the files are already available > >>in text format somewhere. > >> > >>Any help would be greatly appreciated. > >> > >> Thanks, > >> > >> Scott L. Baker > > Sorry, forgot to include my email address: scott_l_baker@ccm.jf.intel.com From newsfish@newsfish Thu Aug 1 00:43:37 2024 X-Received: by 10.200.7.2 with SMTP id g2mr5630497qth.44.1522008930135; Sun, 25 Mar 2018 13:15:30 -0700 (PDT) X-Received: by 10.31.180.79 with SMTP id d76mr4486186vkf.7.1522008929881; Sun, 25 Mar 2018 13:15:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!j29no143934qtc.0!news-out.google.com!c39ni1083qta.0!nntp.google.com!k53no580649qtc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 25 Mar 2018 13:15:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.146.65.215; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 188.146.65.215 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d5a24f6-5a3b-4d6d-96fe-7fe9bf14a27e@googlegroups.com> Subject: ispLEVER - VHDL pin assignment From: silverdr Injection-Date: Sun, 25 Mar 2018 20:15:30 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2077 X-Received-Body-CRC: 3953355891 Xref: reader02.eternal-september.org comp.lang.vhdl:9312 Hello everyone, I've encountered a problem with pin assignments in VHDL whe= n using ispLEVER. Lattice has an answer to the generic question here: http://www.latticesemi.com/en/Support/AnswerDatabase/1/8/4/1844 with link to a more thorough document in there. Both the answer and the doc= ument explain how to assign pins to given signals. They even give dummy exa= mples there, like: attribute LOC : string; attribute LOC of out0: signal is "PA3"; The problem is that while this seems to work well with signals defined as e= . g. 'std_logic', when I try to use this for signals defined as 'std_logic_= vector' and assign pins to f. e. address bus lines: attribute LOC of A(1): signal is "P3"; things break and I get: "design.vhd":19:20:19:20|Expecting : before class of object(s)" error. Work= around to this is to drop the vector definition and define each and every a= ddress line as a separate signal, but I would very much prefer to keep the = vectors where they are. Does anyone know a way to assign pins to "vectored"= signals? From newsfish@newsfish Thu Aug 1 00:43:37 2024 X-Received: by 10.55.75.139 with SMTP id y133mr6764595qka.16.1522077575216; Mon, 26 Mar 2018 08:19:35 -0700 (PDT) X-Received: by 10.31.193.140 with SMTP id r134mr4876722vkf.6.1522077574916; Mon, 26 Mar 2018 08:19:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!k53no706833qtc.1!news-out.google.com!c39ni1296qta.0!nntp.google.com!j29no270693qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Mar 2018 08:19:34 -0700 (PDT) In-Reply-To: <1d5a24f6-5a3b-4d6d-96fe-7fe9bf14a27e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.146.98.199; posting-account=aItwoAoAAADl77EHHw0OM7wo4ykKlwDL NNTP-Posting-Host: 188.146.98.199 References: <1d5a24f6-5a3b-4d6d-96fe-7fe9bf14a27e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: ispLEVER - VHDL pin assignment From: silverdr Injection-Date: Mon, 26 Mar 2018 15:19:35 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 12 Xref: reader02.eternal-september.org comp.lang.vhdl:9313 OK - got the answer on another channel. Instead of > attribute LOC of A(1): signal is "P3"; one needs to write: attribute LOC of A: signal is "P4 P3 P2"; in other words for a signal defined as (f. e.) A : out std_logic_vector(2 downto 0); instead of giving the index and assigning one pin, to one signal of the "vector" I needed to give the whole "vector" and separate the pins by spaces in the value string. From newsfish@newsfish Thu Aug 1 00:43:38 2024 X-Received: by 10.200.18.10 with SMTP id x10mr26897339qti.40.1522156470787; Tue, 27 Mar 2018 06:14:30 -0700 (PDT) X-Received: by 10.31.173.80 with SMTP id w77mr2630589vke.13.1522156470221; Tue, 27 Mar 2018 06:14:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!k53no102292qtc.1!news-out.google.com!c39ni132qta.0!nntp.google.com!k53no102291qtc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Mar 2018 06:14:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.82.231.32; posting-account=-5l5JgoAAACnxM5Tfv3tNj7CcomtRPC3 NNTP-Posting-Host: 85.82.231.32 References: <1d5a24f6-5a3b-4d6d-96fe-7fe9bf14a27e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <67a89fa6-0a29-458f-be81-a5ca66e77aff@googlegroups.com> Subject: Re: ispLEVER - VHDL pin assignment From: nordstjernealle10@gmail.com Injection-Date: Tue, 27 Mar 2018 13:14:30 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1845 X-Received-Body-CRC: 2020924421 Xref: reader02.eternal-september.org comp.lang.vhdl:9314 On Monday, 26 March 2018 17:19:37 UTC+2, silverdr wrote: > OK - got the answer on another channel. Instead of > > > attribute LOC of A(1): signal is "P3"; > > one needs to write: > > attribute LOC of A: signal is "P4 P3 P2"; > > in other words for a signal defined as (f. e.) > > A : out std_logic_vector(2 downto 0); > > instead of giving the index and assigning one pin, to one signal of the "vector" I needed to give the whole "vector" and separate the pins by spaces in the value string. Thanks for posting the answer, too many don't do that From newsfish@newsfish Thu Aug 1 00:43:38 2024 X-Received: by 10.200.25.102 with SMTP id g35mr26068419qtk.52.1523289846610; Mon, 09 Apr 2018 09:04:06 -0700 (PDT) X-Received: by 10.31.199.67 with SMTP id x64mr4657607vkf.7.1523289846366; Mon, 09 Apr 2018 09:04:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!xmission!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!k3no2416466qtm.1!news-out.google.com!a19ni509qtj.1!nntp.google.com!g18no2425794qtk.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Apr 2018 09:04:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.254.154.105; posting-account=f8z29goAAAD-2xoyj9-peJRogv12RcXf NNTP-Posting-Host: 80.254.154.105 References: <18ea7387-fb8b-4cf0-9ff6-2923c7f3982a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2d6e0e74-49f5-407f-bba7-d4c4a3e919cf@googlegroups.com> Subject: Re: what is the reason of this error?? From: dahenk88@gmail.com Injection-Date: Mon, 09 Apr 2018 16:04:06 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 20 Xref: reader02.eternal-september.org comp.lang.vhdl:9315 On Tuesday, 6 January 2015 14:49:03 UTC+1, Brian Drummond wrote: > Your pin assignment is incorrect. While you have apparently assigned CLK_= c=20 > and RST_c to "global" pins, that is not good enough, because, incredibly,= =20 > "global" pins are not actually global. You need "chip global" pins as=20 > opposed to the "quadrant global" pins you are apparently using now (which= =20 > the name implies can only access 1/4 of the device). Thank you so much Brian. I had little hope that googling this error would actually find me a solutio= n, but this was pretty much the only one I found. I'm working with a Microsemi IGLOO Nano, and even reading the IGLOO nano FP= GA Fabric User Guide didn't really help me, partly beacuse - like you menti= on - the word "global" feels very misused, and the info is spread out and a= ddresses all devices at once, some of which don't even have global quadrant= clocks etc. /Henrik From newsfish@newsfish Thu Aug 1 00:43:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!paganini.bofh.team!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!post01.iad!fx42.iad.POSTED!not-for-mail Subject: Re: VHDL-2008 first steps and simulator for Linux Newsgroups: comp.lang.vhdl References: From: Paul Urbanus User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 35 Message-ID: X-Complaints-To: abuse(at)newshosting.com NNTP-Posting-Date: Tue, 10 Apr 2018 19:27:32 UTC Organization: Newshosting.com - Highest quality at a great price! www.newshosting.com Date: Tue, 10 Apr 2018 14:27:29 -0500 X-Received-Bytes: 2012 X-Received-Body-CRC: 3199065609 X-Original-Bytes: 1950 Xref: reader02.eternal-september.org comp.lang.vhdl:9316 On 3/8/2018 6:54 AM, Adam Wysocki wrote: > Hi, > > I started learning VHDL from the book "The Designer's Guide To VHDL" > (third edition) and I'm trying to make my first steps in it. > > > 3. What simulators do you use or recommend? I prefer Linux ones (it would > be much easier for me), but if there are no reasonable ones, I can use > Windows ones as well. I want them only to test and simulate my code > snippets during learning. My final goal is to be able to make models > suitable for synthesis and upload into CPLD and FPGA devices. > > Thank you! > For quick, small, things like this you can try https://www.edaplayground.com/ This site is always up, but unfortunately the above site is down for maintenance at the time of posting. You have access to open source simulators (ghdl,...) as well as commercial offerings (Aldec). There is a crude waveform viewer. Hierarchical designs are supported. There are also tutorials. I really like it for just playing around and trying things. https://www.youtube.com/user/edaplayground DISCLAIMER: I have no affiliation with EDA Playground. I just like it, find it useful, and thought it might meet your needs. From newsfish@newsfish Thu Aug 1 00:43:38 2024 X-Received: by 2002:ac8:230c:: with SMTP id a12-v6mr17875570qta.41.1524569746442; Tue, 24 Apr 2018 04:35:46 -0700 (PDT) X-Received: by 10.31.173.80 with SMTP id w77mr3642686vke.13.1524569746248; Tue, 24 Apr 2018 04:35:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!81.171.65.77.MISMATCH!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!x25-v6no6765675qto.0!news-out.google.com!p5-v6ni50560qtp.1!nntp.google.com!x25-v6no6765663qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Apr 2018 04:35:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.159.112.170; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 195.159.112.170 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a951f19-e836-4dbd-bbcf-a1e739ef86ae@googlegroups.com> Subject: =?UTF-8?Q?Free_Webinar_Thursday=3A_UVVM_=E2=80=93_The_standardized_ope?= =?UTF-8?Q?n_source_VHDL_testbench_architecture?= From: espen.tallaksen@bitvis.no Injection-Date: Tue, 24 Apr 2018 11:35:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2569 X-Received-Body-CRC: 1486345424 Xref: reader02.eternal-september.org comp.lang.vhdl:9317 The webinars are hosted by Aldec as follows: Thursday 26 April:=20 EU: 3:00 PM =E2=80=93 4:00 PM (CEST) : https://www.aldec.com/en/events/10= 12 US: 11:00 AM =E2=80=93 12:00 PM (PDT): https://www.aldec.com/en/events/10= 11 For an FPGA design we all know that the architecture =E2=80=93 all the way = from the top to the micro architecture =E2=80=93 is critical for both the F= PGA quality and the development time. It should be obvious to any experienc= ed designer that this also applies to the testbench. Most FPGA designs are split into stand-alone modules =E2=80=93 for instance= for each of the FPGA external interfaces. In VHDL these modules are VHDL e= ntities, and they are normally accessed from a CPU via a standardized regis= ter interface, which acts as an abstraction layer. This abstraction allows = a safe and efficient control of the complete FPGA.=20 Such an approach should also be used for the verification environment - to = simplify the testbench architecture and the control of the interfaces. This= way the verification structure will mirror the design structure, allowing = the best possible overview, readability, maintainability and reuse. See full abstract: https://www.aldec.com/en/events/1011 This webinar will show how UVVM is standardising the VHDL testbench archite= cture and also present some of the most important UVVM extensions sponsored= by ESA (the European Space Agency) From newsfish@newsfish Thu Aug 1 00:43:39 2024 X-Received: by 2002:aed:3644:: with SMTP id e62-v6mr451985qtb.23.1525418582116; Fri, 04 May 2018 00:23:02 -0700 (PDT) X-Received: by 2002:a1f:2f8b:: with SMTP id v133-v6mr3901536vkv.10.1525418581841; Fri, 04 May 2018 00:23:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no3519298qto.0!news-out.google.com!c8-v6ni1097qtc.0!nntp.google.com!x25-v6no3519292qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 May 2018 00:23:01 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.159.112.170; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 195.159.112.170 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2a304b7e-ccfc-4f2c-bcdd-ef5b84b1279f@googlegroups.com> Subject: Sharing VHDL Verification IP From: espen.tallaksen@bitvis.no Injection-Date: Fri, 04 May 2018 07:23:02 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 57 Xref: reader02.eternal-september.org comp.lang.vhdl:9318 Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community h= as previously been difficult because there was no standardised way of inter= facing to and controlling these VVCs. A solution on this challenge could ea= sily reduce the project verification time by 20 to 80%, and at the same tim= e improve the FPGA quality. The open source UVVM has over the last two years standardised the command i= nterface, integration, debugging and internal architecture of VHDL Verifica= tion Components and clearly shown that a standardisation was in deed both p= ossible and extremely efficient. Open source VVCs have been released for AX= I4-lite, AXI4-stream, Avalon MM, I2C, SPI, SBI, UART and GPIO, - showing ho= w easy it is to implement testbenches and write test cases using this stand= ardised methodology. Due to this standardisation, FPGA designers world-wide have recently starte= d asking for more cooperation on UVVM compliant VVCs inside the VHDL commun= ity. As this is actually the main intention behind standardising VVCs, we h= ave now decided to facilitate a Verification IP cooperation. For this purpo= se we have opened a new repository on Github for sharing VHDL VIP next to t= he UVVM repository. https://github.com/UVVM/UVVM_3rd_party_VIP This new repository is intended to link to any UVVM compatible Verification= IP; - VVC, BFM or other. We have chosen not to include any VIP directly in= side this repository, as all 3rd party VIP will be the property of and main= tained by the 3rd party company or designer. Any 3rd part VIP will automatically be UVVM compliant given that the design= ers have used the provided templates or scripts from UVVM. This has of cour= se the major benefit that all UVVM compliant VIP can be controlled and acce= ssed exactly the same way and that they will work together. There is howeve= r no way we can guarantee the functionality of the DUT interface/protocol h= andled by 3rd party VVC or BFM designers, so this will be the full responsi= bility of the VIP provider. Any question regarding the VVC should therefore= be addressed to this provider. Bitvis will not qualify any 3rd party VIP, = but we assume the community will very soon give useful feedback. Open source Verification IP is great, and UVVM with its provided BFMs and V= VCs are all open source and free, - but we also welcome commercial VIP and = will link to this in the same way as open source. It is important for VHDL = designers to get the full overview of what is available, and it is up to th= em to decide whether a commercial VIP is ok. All commercial aspects must be= handled directly between the buyer and the seller. Bitvis has no role in t= his. Note that even if UVVM has standardised the VHDL testbench architecture for= efficient verification, you may still pick only the parts you like. Thus y= ou can pick only a single BFM or VVC from UVVM if you like, and use this in= your testbench together with your own and 3rd party verification IP. We now really hope that the VHDL community will use this opportunity to mak= e us all more efficient. Have a look at this on Github and start the proces= s :-) (This article was also published on LinkedIn. Articles there may also inclu= de figures, which sometimes is very useful... =20 https://www.linkedin.com/pulse/sharing-vhdl-verification-ip-espen-tallaksen= /) From newsfish@newsfish Thu Aug 1 00:43:39 2024 X-Received: by 10.55.73.138 with SMTP id w132mr24469425qka.61.1525769419253; Tue, 08 May 2018 01:50:19 -0700 (PDT) X-Received: by 2002:a1f:9b55:: with SMTP id d82-v6mr6367788vke.12.1525769418892; Tue, 08 May 2018 01:50:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!newsreader5.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!x25-v6no352957qto.0!news-out.google.com!p41-v6ni59qtp.1!nntp.google.com!x25-v6no352950qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 May 2018 01:50:18 -0700 (PDT) In-Reply-To: <2d6e0e74-49f5-407f-bba7-d4c4a3e919cf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=182.64.14.53; posting-account=2hATxgoAAACnaudci4oFUjXUSpQPV0Cn NNTP-Posting-Host: 182.64.14.53 References: <18ea7387-fb8b-4cf0-9ff6-2923c7f3982a@googlegroups.com> <2d6e0e74-49f5-407f-bba7-d4c4a3e919cf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: what is the reason of this error?? From: mandan.kumar@logic-fruit.com Injection-Date: Tue, 08 May 2018 08:50:19 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2516 X-Received-Body-CRC: 3483919892 Xref: reader02.eternal-september.org comp.lang.vhdl:9319 On Monday, April 9, 2018 at 9:34:09 PM UTC+5:30, dahe...@gmail.com wrote: > On Tuesday, 6 January 2015 14:49:03 UTC+1, Brian Drummond wrote: >=20 > > Your pin assignment is incorrect. While you have apparently assigned CL= K_c=20 > > and RST_c to "global" pins, that is not good enough, because, incredibl= y,=20 > > "global" pins are not actually global. You need "chip global" pins as= =20 > > opposed to the "quadrant global" pins you are apparently using now (whi= ch=20 > > the name implies can only access 1/4 of the device). >=20 > Thank you so much Brian. > I had little hope that googling this error would actually find me a solut= ion, but this was pretty much the only one I found. > I'm working with a Microsemi IGLOO Nano, and even reading the IGLOO nano = FPGA Fabric User Guide didn't really help me, partly beacuse - like you men= tion - the word "global" feels very misused, and the info is spread out and= addresses all devices at once, some of which don't even have global quadra= nt clocks etc. >=20 > /Henrik Did Anyone found the solution for this? I am still getting this error in my= project. From newsfish@newsfish Thu Aug 1 00:43:40 2024 X-Received: by 2002:ac8:41cb:: with SMTP id o11-v6mr1692008qtm.26.1527089522843; Wed, 23 May 2018 08:32:02 -0700 (PDT) X-Received: by 2002:a1f:951:: with SMTP id 78-v6mr453833vkj.0.1527089522556; Wed, 23 May 2018 08:32:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no392212qto.0!news-out.google.com!p41-v6ni118qtp.1!nntp.google.com!x25-v6no392207qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 08:32:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Subject: This If statement fails to be true From: David Perry Injection-Date: Wed, 23 May 2018 15:32:02 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 26 Xref: reader02.eternal-september.org comp.lang.vhdl:9320 I have a simple if statment: If Ctrl_uf > to_ufixed(0, 15, 0) then Ctrl_uf is: Signal Ctrl_uf : ufixed(15 downto 0) := x"8000"; it is never 0 for the purposes of trying to get this to work. The code after the if statement is never enabled, if I comment out the if/end if then the code gets used. For completeness here's a bit more code: if Ctrl_Up = HI then if Ctrl_uf < to_ufixed(65535, 15, 0) then CtrlCalc_uf := Ctrl_uf + to_ufixed(1, 15, 0); Ctrl_uf <= CtrlCalc_uf(15 downto 0); end if; else if Ctrl_Dn = HI then if Ctrl_uf > to_ufixed(0, 15, 0) then CtrlCalc_uf := Ctrl_uf - to_ufixed(1, 15, 0); Ctrl_uf <= CtrlCalc_uf(15 downto 0); end if; end if; end if; essentially, Ctrl_Up increments the value of Ctrl_uf correctly, but Ctrl_Dn doesn't and the signal is definitely there, if I comment out the problem 'if' statement, it works but without the end-stop protection. Any ideas? From newsfish@newsfish Thu Aug 1 00:43:40 2024 X-Received: by 2002:a37:c80b:: with SMTP id c11-v6mr1743888qkj.34.1527090293561; Wed, 23 May 2018 08:44:53 -0700 (PDT) X-Received: by 2002:a1f:b40b:: with SMTP id d11-v6mr452011vkf.1.1527090293362; Wed, 23 May 2018 08:44:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no397774qto.0!news-out.google.com!k3-v6ni208qtj.0!nntp.google.com!x25-v6no397770qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 08:44:53 -0700 (PDT) In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <178e0d19-1294-4ddc-a68b-af5847737d6f@googlegroups.com> Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Wed, 23 May 2018 15:44:53 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 0 Xref: reader02.eternal-september.org comp.lang.vhdl:9321 I forgot to mention, I did also use 0.0 as the number, it made no difference From newsfish@newsfish Thu Aug 1 00:43:40 2024 X-Received: by 2002:a37:2915:: with SMTP id p21-v6mr1717572qkh.1.1527090631240; Wed, 23 May 2018 08:50:31 -0700 (PDT) X-Received: by 2002:a1f:2315:: with SMTP id j21-v6mr459695vkj.10.1527090631076; Wed, 23 May 2018 08:50:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!newsreader5.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no400169qto.0!news-out.google.com!k3-v6ni208qtj.0!nntp.google.com!x25-v6no400158qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 08:50:30 -0700 (PDT) In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9ed775c6-2ea0-46c4-91d7-59b4831606e2@googlegroups.com> Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Wed, 23 May 2018 15:50:31 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 0 X-Received-Bytes: 1460 X-Received-Body-CRC: 2916431975 Xref: reader02.eternal-september.org comp.lang.vhdl:9322 Oh, and it simulates fine, when I put it on hardware it only increments, decrement only works with the if/end if commented out! From newsfish@newsfish Thu Aug 1 00:43:40 2024 X-Received: by 2002:ac8:714d:: with SMTP id h13-v6mr1842464qtp.37.1527094194499; Wed, 23 May 2018 09:49:54 -0700 (PDT) X-Received: by 2002:a1f:88d2:: with SMTP id k201-v6mr482076vkd.9.1527094194046; Wed, 23 May 2018 09:49:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no422557qto.0!news-out.google.com!k3-v6ni208qtj.0!nntp.google.com!x25-v6no422548qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 09:49:53 -0700 (PDT) In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=74.36.195.182; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 74.36.195.182 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8346c89c-8ab3-47d8-bb89-792d00252bb4@googlegroups.com> Subject: Re: This If statement fails to be true From: Jim Lewis Injection-Date: Wed, 23 May 2018 16:49:54 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 10 Xref: reader02.eternal-september.org comp.lang.vhdl:9323 On Wednesday, May 23, 2018 at 8:32:05 AM UTC-7, David Perry wrote: > I have a simple if statment: > If Ctrl_uf > to_ufixed(0, 15, 0) then You are working harder than you need to. The overloading allows both integer and real valued literals, so your comparison becomes: if Ctrl_uf > 0 then (ExtraCarryOut_sl, Ctrl_uf) <= Ctrl_uf - 1; Have you also tried: if Ctrl_uf /= 0 then From newsfish@newsfish Thu Aug 1 00:43:41 2024 X-Received: by 2002:ac8:70c2:: with SMTP id g2-v6mr1854723qtp.60.1527095472705; Wed, 23 May 2018 10:11:12 -0700 (PDT) X-Received: by 2002:a1f:3614:: with SMTP id d20-v6mr492678vka.5.1527095472477; Wed, 23 May 2018 10:11:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no429696qto.0!news-out.google.com!k3-v6ni208qtj.0!nntp.google.com!x25-v6no429689qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 10:11:12 -0700 (PDT) In-Reply-To: <8346c89c-8ab3-47d8-bb89-792d00252bb4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> <8346c89c-8ab3-47d8-bb89-792d00252bb4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9cd36b2b-5fd3-4d84-a9c2-3c9544ef26aa@googlegroups.com> Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Wed, 23 May 2018 17:11:12 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 6 Xref: reader02.eternal-september.org comp.lang.vhdl:9324 > You are working harder than you need to. The overloading allows both integer and real valued literals, so your comparison becomes: > if Ctrl_uf > 0 then > (ExtraCarryOut_sl, Ctrl_uf) <= Ctrl_uf - 1; I have now tried: if Ctrl_uf > 0 then but this didn't work. I can't figure out how to make your carry bit work either :( From newsfish@newsfish Thu Aug 1 00:43:41 2024 X-Received: by 2002:a0c:f946:: with SMTP id i6-v6mr1988061qvo.4.1527096846436; Wed, 23 May 2018 10:34:06 -0700 (PDT) X-Received: by 2002:a1f:951:: with SMTP id 78-v6mr511962vkj.0.1527096846006; Wed, 23 May 2018 10:34:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!news.redatomik.org!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!85.12.16.69.MISMATCH!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!x25-v6no437647qto.0!news-out.google.com!k3-v6ni208qtj.0!nntp.google.com!x25-v6no437639qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 10:34:05 -0700 (PDT) In-Reply-To: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=189.156.188.82; posting-account=y79GLQoAAABEHAscbqbkft5z75KY9PKd NNTP-Posting-Host: 189.156.188.82 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8992bfb9-490b-46ed-92d8-dd9529b2290f@googlegroups.com> Subject: Re: GALs and VHDL From: alanfdo97@gmail.com Injection-Date: Wed, 23 May 2018 17:34:06 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1443 X-Received-Body-CRC: 3488902850 Xref: reader02.eternal-september.org comp.lang.vhdl:9325 I have the same error, but, I'm using the GAL 22V10D, What would be the solution. I've tried it with other forms and it works, but with this one. I'm programming with "CASE-WHEN" and I can't resolve my error.... I'm stressed... From newsfish@newsfish Thu Aug 1 00:43:41 2024 X-Received: by 2002:a0c:962f:: with SMTP id 44-v6mr1900016qvx.25.1527098038299; Wed, 23 May 2018 10:53:58 -0700 (PDT) X-Received: by 2002:a1f:2315:: with SMTP id j21-v6mr520116vkj.10.1527098038113; Wed, 23 May 2018 10:53:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no447837qto.0!news-out.google.com!k3-v6ni208qtj.0!nntp.google.com!x25-v6no447828qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 10:53:57 -0700 (PDT) In-Reply-To: <8346c89c-8ab3-47d8-bb89-792d00252bb4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> <8346c89c-8ab3-47d8-bb89-792d00252bb4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Wed, 23 May 2018 17:53:58 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 7 Xref: reader02.eternal-september.org comp.lang.vhdl:9326 > Have you also tried: > if Ctrl_uf /=3D 0 then I finally tried that out of desperation, yes, that does work. However, this= won't solve my problem when I want to change the endstop from zero. Eventu= ally, I will have different addition/subtraction values, the endstops will = need to account for these so that I don't overflow, but baby steps... From newsfish@newsfish Thu Aug 1 00:43:42 2024 X-Received: by 2002:ac8:b4e:: with SMTP id m14-v6mr2091607qti.31.1527100026917; Wed, 23 May 2018 11:27:06 -0700 (PDT) X-Received: by 2002:a1f:b40b:: with SMTP id d11-v6mr531539vkf.1.1527100026631; Wed, 23 May 2018 11:27:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no460582qto.0!news-out.google.com!k3-v6ni208qtj.0!nntp.google.com!x25-v6no460576qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 11:27:06 -0700 (PDT) In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Wed, 23 May 2018 18:27:06 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 11 Xref: reader02.eternal-september.org comp.lang.vhdl:9327 To prove to myself that I will have problems, I moved my end stops: if Ctrl_Up = HI then if Ctrl_uf < 65530 then ... if Ctrl_Dn = HI then if Ctrl_uf > 10 then both controls fail. As it currently stands, the only comparisons I can get to work are: /= 0 and < 65535 From newsfish@newsfish Thu Aug 1 00:43:42 2024 X-Received: by 2002:a37:7e83:: with SMTP id z125-v6mr2115754qkc.16.1527101990401; Wed, 23 May 2018 11:59:50 -0700 (PDT) X-Received: by 2002:a1f:88d2:: with SMTP id k201-v6mr548305vkd.9.1527101990142; Wed, 23 May 2018 11:59:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no472657qto.0!news-out.google.com!k3-v6ni208qtj.0!nntp.google.com!x25-v6no472652qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 11:59:49 -0700 (PDT) In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <120044c7-db35-4b4f-8817-14a6b2e1893a@googlegroups.com> Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Wed, 23 May 2018 18:59:50 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 11 Xref: reader02.eternal-september.org comp.lang.vhdl:9328 Just for fun, I changed Ctrl_uf to a shared variable and did the following: if Ctrl_Dn = HI then Ctrl_uf := x"0F00"; if Ctrl_uf > 10 then Ctrl_uf := x"0EFF"; end if; end if; The result? 0F00 This similuates absolutely fine, the result is 0EFF as expected. I now suspect this is 'just' an issue with xilinx not compiling properly for some reason, I shall post on their forums. :( From newsfish@newsfish Thu Aug 1 00:43:42 2024 X-Received: by 2002:a0c:b626:: with SMTP id f38-v6mr2611603qve.1.1527120647907; Wed, 23 May 2018 17:10:47 -0700 (PDT) X-Received: by 2002:a1f:9613:: with SMTP id y19-v6mr706029vkd.8.1527120647674; Wed, 23 May 2018 17:10:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!news.redatomik.org!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!x25-v6no579571qto.0!news-out.google.com!k3-v6ni229qtj.0!nntp.google.com!x25-v6no579566qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 17:10:47 -0700 (PDT) In-Reply-To: <120044c7-db35-4b4f-8817-14a6b2e1893a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> <120044c7-db35-4b4f-8817-14a6b2e1893a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1e593dc5-c529-44f8-b399-9782d4e335f1@googlegroups.com> Subject: Re: This If statement fails to be true From: KJ Injection-Date: Thu, 24 May 2018 00:10:47 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1408 X-Received-Body-CRC: 3050339842 Xref: reader02.eternal-september.org comp.lang.vhdl:9329 It could be that Xilinx software is treating the 8000 as a signed number rather than unsigned. Kevin From newsfish@newsfish Thu Aug 1 00:43:43 2024 X-Received: by 2002:a37:9e95:: with SMTP id h143-v6mr3095962qke.38.1527142037288; Wed, 23 May 2018 23:07:17 -0700 (PDT) X-Received: by 2002:a1f:3614:: with SMTP id d20-v6mr849959vka.5.1527142037058; Wed, 23 May 2018 23:07:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no685643qto.0!news-out.google.com!p41-v6ni212qtp.1!nntp.google.com!x25-v6no685641qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 May 2018 23:07:16 -0700 (PDT) In-Reply-To: <1e593dc5-c529-44f8-b399-9782d4e335f1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.3.235.244; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 80.3.235.244 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> <120044c7-db35-4b4f-8817-14a6b2e1893a@googlegroups.com> <1e593dc5-c529-44f8-b399-9782d4e335f1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <304bf190-9d24-4081-826d-03a5b904391e@googlegroups.com> Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Thu, 24 May 2018 06:07:17 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 5 Xref: reader02.eternal-september.org comp.lang.vhdl:9330 On Thursday, 24 May 2018 01:10:50 UTC+1, KJ wrote: > It could be that Xilinx software is treating the 8000 as a signed number rather than unsigned. > > Kevin I did briefly ponder that, but it fails with any value. I changed the top-end check away from 65535 and that then fails too. Also see the post prior to yours, clearly something is quite wrong :( From newsfish@newsfish Thu Aug 1 00:43:43 2024 X-Received: by 2002:a0c:d8e8:: with SMTP id w37-v6mr805018qvj.56.1527149551687; Thu, 24 May 2018 01:12:31 -0700 (PDT) X-Received: by 2002:a1f:9613:: with SMTP id y19-v6mr911159vkd.8.1527149551474; Thu, 24 May 2018 01:12:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder4.usenet.farm!feed.usenet.farm!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no723702qto.0!news-out.google.com!p41-v6ni236qtp.1!nntp.google.com!x25-v6no723694qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 May 2018 01:12:31 -0700 (PDT) In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1b2dcc00-3b65-4b08-ad77-9842ae48bed3@googlegroups.com> Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Thu, 24 May 2018 08:12:31 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 3 Xref: reader02.eternal-september.org comp.lang.vhdl:9331 As a work-around I have used unsigned instead of ufixed then converted it to ufixed later where it's used in another process for some maths. Why does ufixed insist on extending the vector size while unsigned doesn't when doing +/-? My subtraction ends up as a simple: Ctrl_uf := Ctrl_uf - 1; From newsfish@newsfish Thu Aug 1 00:43:43 2024 X-Received: by 2002:a0c:86ef:: with SMTP id 44-v6mr5030qvg.53.1527200862152; Thu, 24 May 2018 15:27:42 -0700 (PDT) X-Received: by 2002:a1f:808:: with SMTP id 8-v6mr1366909vki.13.1527200861952; Thu, 24 May 2018 15:27:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no1077054qto.0!news-out.google.com!k3-v6ni369qtj.0!nntp.google.com!x25-v6no1077048qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 May 2018 15:27:41 -0700 (PDT) In-Reply-To: <1b2dcc00-3b65-4b08-ad77-9842ae48bed3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:40e:100:efa0:a4a2:ba7e:41fc:2a25; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2601:40e:100:efa0:a4a2:ba7e:41fc:2a25 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> <1b2dcc00-3b65-4b08-ad77-9842ae48bed3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <83d6b5e6-0119-4989-a0fe-9d481b8caf78@googlegroups.com> Subject: Re: This If statement fails to be true From: KJ Injection-Date: Thu, 24 May 2018 22:27:42 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 17 Xref: reader02.eternal-september.org comp.lang.vhdl:9332 ufixed adds a bit because mathematically that is the correct thing to do wh= en adding or subtracting. This corrects a 'deficiency' with the unsigned t= ype. Of course many times one does want modulo arithmetic in which case uns= igned may be a better type to use...and using ufixed in those situations re= quires adding resize function calls. I would think that if you take your test case, add a copy where the only di= fference is the type used and a conversion from ufixed to unsigned and show= that you get two different outputs that would be an awfully strong bug cas= e to let Xilinx chew on. Have you tried defining a ufixed constant with the to_ufixed function and t= hen using that constant in the > comparison. There is no reason that a bug = free tool would work any differently, but if it does work it gives you a se= cond workaround.=20 Kevin Jennings=20 From newsfish@newsfish Thu Aug 1 00:43:44 2024 X-Received: by 2002:a0c:c20a:: with SMTP id l10-v6mr772658qvh.35.1527239884287; Fri, 25 May 2018 02:18:04 -0700 (PDT) X-Received: by 2002:a25:cf13:: with SMTP id f19-v6mr15627ybg.5.1527239884096; Fri, 25 May 2018 02:18:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!2.eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!x25-v6no1293653qto.0!news-out.google.com!k3-v6ni478qtj.0!nntp.google.com!x25-v6no1293646qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 May 2018 02:18:03 -0700 (PDT) In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <31c04182-03b4-4efa-b2bb-1d0789d90b73@googlegroups.com> Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Fri, 25 May 2018 09:18:04 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1626 X-Received-Body-CRC: 4179081421 Xref: reader02.eternal-september.org comp.lang.vhdl:9333 I see, that makes sense. I have raised the issue on the xilinx forums: https://forums.xilinx.com/t5/Simulation-and-Verification/Simple-If-statement-simulates-correctly-but-fails-in-hardware/td-p/858986 I haven't yet done an unsigned/ufixed comparative test, that could be well worth doing! I did try using a constant ufixed, it didn't make any difference. From newsfish@newsfish Thu Aug 1 00:43:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: This If statement fails to be true Date: Wed, 30 May 2018 11:35:29 -0500 Organization: A noiseless patient Spider Lines: 46 Message-ID: References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 May 2018 16:35:31 -0000 (UTC) Injection-Info: h2725194.stratoserver.net; posting-host="1cab234cea333df6a6f78a14180997ef"; logging-data="3171"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19xleWIdLdtnL1LxKz8cidNMELMQfCIACs=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:gTBQJDTUXsOV0FDT/AUi70WNw6A= In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Xref: reader02.eternal-september.org comp.lang.vhdl:9334 On 2018-05-23 10:32, David Perry wrote: > I have a simple if statment: > If Ctrl_uf > to_ufixed(0, 15, 0) then > > Ctrl_uf is: > Signal Ctrl_uf : ufixed(15 downto 0) := x"8000"; > it is never 0 for the purposes of trying to get this to work. > The code after the if statement is never enabled, if I comment out the if/end if then the code gets used. > > For completeness here's a bit more code: > > if Ctrl_Up = HI then > if Ctrl_uf < to_ufixed(65535, 15, 0) then > CtrlCalc_uf := Ctrl_uf + to_ufixed(1, 15, 0); > Ctrl_uf <= CtrlCalc_uf(15 downto 0); > end if; > else > if Ctrl_Dn = HI then > if Ctrl_uf > to_ufixed(0, 15, 0) then > CtrlCalc_uf := Ctrl_uf - to_ufixed(1, 15, 0); > Ctrl_uf <= CtrlCalc_uf(15 downto 0); > end if; > end if; > end if; > > essentially, Ctrl_Up increments the value of Ctrl_uf correctly, but Ctrl_Dn doesn't and the signal is definitely there, if I comment out the problem 'if' statement, it works but without the end-stop protection. > > Any ideas? > Why make it so hard? Why not just code something like this? Signal Ctrl_uf : integer range 0 to 65535:=32768; if Ctrl_Up = HI then if Ctrl_uf < 65535 then Ctrl_uf <= Ctrl_uf+1; end if; elsif Ctrl_Dn = HI then if Ctrl_uf > 0 then Ctrl_uf <= Ctrl_uf-1; end if; end if; This should simulate an synthesize just fine. Charles Bailey From newsfish@newsfish Thu Aug 1 00:43:44 2024 X-Received: by 2002:ac8:3558:: with SMTP id z24-v6mr3141600qtb.21.1527759173056; Thu, 31 May 2018 02:32:53 -0700 (PDT) X-Received: by 2002:a81:6ec1:: with SMTP id j184-v6mr224719ywc.7.1527759172811; Thu, 31 May 2018 02:32:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!x25-v6no480012qto.0!news-out.google.com!p41-v6ni1435qtp.1!nntp.google.com!x25-v6no480005qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 May 2018 02:32:52 -0700 (PDT) In-Reply-To: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <35fdc14d-bc82-4972-beae-db3d4f9d75fa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: This If statement fails to be true From: David Perry Injection-Date: Thu, 31 May 2018 09:32:53 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 4 Xref: reader02.eternal-september.org comp.lang.vhdl:9335 I originally did it with ufixed because I use the number in some maths else= where, which is also ufixed, the idea was to use the same types to make lif= e easier. Irrespective of that, the problem seems to be real and the conseq= uences could be quite bad if it is wider reaching than the problems I've fo= und. From newsfish@newsfish Thu Aug 1 00:43:45 2024 X-Received: by 2002:ac8:1868:: with SMTP id n37-v6mr1600502qtk.43.1528858971269; Tue, 12 Jun 2018 20:02:51 -0700 (PDT) X-Received: by 2002:a81:4b49:: with SMTP id y70-v6mr135269ywa.1.1528858971057; Tue, 12 Jun 2018 20:02:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h2-v6no430292qtp.0!news-out.google.com!a20-v6ni42qtj.1!nntp.google.com!h2-v6no430288qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Jun 2018 20:02:50 -0700 (PDT) In-Reply-To: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=189.237.205.198; posting-account=EbhiYwoAAADr9suluaKngb73-e7M9VGJ NNTP-Posting-Host: 189.237.205.198 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5d2ad8b4-2c78-4041-9d0e-8cbf6f05ecc0@googlegroups.com> Subject: Re: GALs and VHDL From: abner.diaz@ieee.org Injection-Date: Wed, 13 Jun 2018 03:02:51 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 60 Xref: reader02.eternal-september.org comp.lang.vhdl:9336 On Wednesday, June 15, 2016 at 9:41:35 AM UTC-6, silverdr wrote: > Hello group (and please have understanding for a newbie in the subject). >=20 > I'd like to make use of GAL chips for a relatively simple logic I need to= build. Nine inputs to five outputs, purely combinatorial, non-clocked. I w= rote VHDL design and testbench and successfully tested it on edaplayground.= com. Now, I'd like to synthesise it and then comes some questions: >=20 > - what software (preferably but not necessarily free as in speech and ope= n-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, A= tmel and one or two more vendors (don't remember exactly now). >=20 > - are the synthesised files compatible across different vendors' chips? >=20 > - If there is a GAL (16V8 for example) which has eight inputs and eight O= utput Logic MacroCells, can some of those OLMCs/pins be configured and used= as inputs too? Judging by the specs/datasheet "yes" but would like to conf= irm that. >=20 >=20 > So far I downloaded and installed the ispLEVER from Lattice, which is sti= ll available and supports "obsolete" devices like GALs. The problem is that= when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project = I get output like: >=20 > ******* > Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -t= arget ispGAL -pro ' >=20 >=20 > Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights re= served. > Version : 2.0.00.17.20.15 >=20 > Done sucessfully with exit code 1. > Error output EDIF file c:/documents and settings/silverdr/my documents/so= urces/vhdl/r512/r512vhdl.edi > Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 >=20 > Done: failed with exit code: 0002. > ******* >=20 > and am stuck at it. >=20 > I know there is a CUPL software available from Atmel, and it should be ab= le to synthesise designs for GALs but I would prefer to stick to VHDL, whic= h I assume is going to stay with me for some time to come. Therefore rewrit= ing the design into CUPL is probably the last resort. >=20 > I'd be grateful for some clues/hints/pointers. >=20 > --=20 > silverdr I have the same problem... when I do Synthesize there appears the next erro= r: Error output EDIF file c:/isplever_classic2_0/examples/ESumRes.edi Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 ... How did you fix it? From newsfish@newsfish Thu Aug 1 00:43:45 2024 X-Received: by 2002:a37:9e4c:: with SMTP id h73-v6mr2954862qke.15.1528907173290; Wed, 13 Jun 2018 09:26:13 -0700 (PDT) X-Received: by 2002:a25:d98a:: with SMTP id q132-v6mr287275ybg.0.1528907173114; Wed, 13 Jun 2018 09:26:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h2-v6no680221qtp.0!news-out.google.com!u13-v6ni156qtg.0!nntp.google.com!h2-v6no680214qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 13 Jun 2018 09:26:12 -0700 (PDT) In-Reply-To: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.203.240.234; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.203.240.234 References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: simple unsigned maths problem with if statement From: gnuarm.deletethisbit@gmail.com Injection-Date: Wed, 13 Jun 2018 16:26:13 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 66 Xref: reader02.eternal-september.org comp.lang.vhdl:9337 On Thursday, February 22, 2018 at 6:38:54 AM UTC-5, David Perry wrote: > I'm having an issue with a simple if statement: >=20 > if ClampIn_u + DMD_u < x"FFFF" then --this doesn't work :( > ClampIn_u :=3D ClampIn_u + DMD_u; > else > ClampIn_u :=3D x"FFFF"; > end if; >=20 > What happens is the addition always occurs, I end up overflowing and I ge= t the wrong result. >=20 > I tried making the right hand side of the if bigger in attempt to make it= work: >=20 > if ClampIn_u + DMD_u < x"0FFFF" then >=20 > but that fails in the same way. >=20 > If I rearrange the maths (subtract DMD_u from both sides): >=20 > if ClampIn_u < x"FFFF" - DMD_u then >=20 > this works. >=20 > DMD_u is an unsigned 16 bit signal, ClampIn_u is an unsigned 16 bit varia= ble. >=20 > I'm struggling to find an explanation, I can see why my original might fa= il but I would have expected "0FFFF" to work. >=20 > Any insight would be appreciated :) This thread is getting a bit old in the tooth, but at least it is still the= same year, ;)=20 I see the problem (from the perspective of an old school hardware designer)= as being one of not considering what hardware will be produced from your d= escription. After all, HDL stands for "Hardware Description" Language and = to produce the best code I think the resulting hardware should be considere= d when writing code.=20 The hardware produced by this code should be an adder followed by a multipl= exer with the carry out of the adder used to control the mux. In fact, it = really isn't even a mux, but just a set of OR gates to force the output to = a 1. So this would utilize two 4 input LUTs for each input bit to produce = a result. Even better yet would be if the tools were clever enough to comb= ine the OR gates with the adder for 1 LUT per bit, but I'm not sure the too= ls are quite up to it. Still, the key is using the carry out of the adder = to control the OR gates.=20 I would write this as a 17 bit addition outside of the conditional statemen= t. Then use the msb (which the tools should understand is the carry out of= the lower 16 bits) to drive the conditional which selects either the addit= ion result or the max 16 bit value. =20 MyTemp17b_u :=3D '0' & ClampIn_u + DMD_u; if (MyTemp17b_u(MyTemp17b_u'high) =3D '1') then=20 Result :=3D x"FFFF";=20 else=20 Result :=3D MyTemp17b_u; endif;=20 To me this is more clear and I am pretty confident of knowing what hardware= will be produced by the code.=20 Rick C. From newsfish@newsfish Thu Aug 1 00:43:45 2024 X-Received: by 2002:a37:1397:: with SMTP id 23-v6mr3150375qkt.25.1528914644066; Wed, 13 Jun 2018 11:30:44 -0700 (PDT) X-Received: by 2002:a25:e0d3:: with SMTP id x202-v6mr309360ybg.7.1528914643801; Wed, 13 Jun 2018 11:30:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!newsreader5.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!h2-v6no720467qtp.0!news-out.google.com!u13-v6ni156qtg.0!nntp.google.com!h2-v6no720463qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 13 Jun 2018 11:30:43 -0700 (PDT) In-Reply-To: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.3.235.244; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 80.3.235.244 References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1fd8878a-4c9d-4b61-ae7a-f18f09e805e1@googlegroups.com> Subject: Re: simple unsigned maths problem with if statement From: David Perry Injection-Date: Wed, 13 Jun 2018 18:30:44 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1515 X-Received-Body-CRC: 242569599 Xref: reader02.eternal-september.org comp.lang.vhdl:9338 Oddly enough, I'm trying to move away from throwing down gates (I filled a spartan 3AN 1400 with schematics), but there are times when I think to myself, you know, I could throw this down in a few minutes if I didn't do it 'properly' using VHDL... From newsfish@newsfish Thu Aug 1 00:43:46 2024 X-Received: by 2002:aed:3c72:: with SMTP id u47-v6mr215264qte.45.1528936391134; Wed, 13 Jun 2018 17:33:11 -0700 (PDT) X-Received: by 2002:a25:d68d:: with SMTP id n135-v6mr394850ybg.6.1528936391041; Wed, 13 Jun 2018 17:33:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!newsreader5.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!h2-v6no850002qtp.0!news-out.google.com!a20-v6ni189qtj.1!nntp.google.com!h2-v6no849999qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 13 Jun 2018 17:33:10 -0700 (PDT) In-Reply-To: <1fd8878a-4c9d-4b61-ae7a-f18f09e805e1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.203.240.234; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.203.240.234 References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> <1fd8878a-4c9d-4b61-ae7a-f18f09e805e1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ea276a6-3cbd-4a81-9f72-42e175278237@googlegroups.com> Subject: Re: simple unsigned maths problem with if statement From: gnuarm.deletethisbit@gmail.com Injection-Date: Thu, 14 Jun 2018 00:33:11 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2562 X-Received-Body-CRC: 3826425516 Xref: reader02.eternal-september.org comp.lang.vhdl:9339 On Wednesday, June 13, 2018 at 2:30:45 PM UTC-4, David Perry wrote: > Oddly enough, I'm trying to move away from throwing down gates (I filled = a spartan 3AN 1400 with schematics), but there are times when I think to my= self, you know, I could throw this down in a few minutes if I didn't do it = 'properly' using VHDL... Sorry, I'm not clear on what you are saying. Are you saying you could work= faster by not considering how your code is synthesized? Yes, that is cert= ainly true. Or are you saying VHDL is a overstuffed pig of a language and = you would just prefer to be laying down gates? I would not totally disagre= e with that either. =20 A long time ago one of the posters in c.a.f was famous for very high speed = pipelined designs done in modular, hierarchical schematics. He resisted st= aunchly the movement to HDL... until he was taught how he could accomplish = the same sort of library driven, modular, hierarchical designs in VHDL whic= h in addition could be version controlled like any other software. That wa= s when I realized I had no reason to regret having switched to VHDL (other = than possibly not having switched to Verilog).=20 Rick C. From newsfish@newsfish Thu Aug 1 00:43:46 2024 X-Received: by 2002:a37:1311:: with SMTP id d17-v6mr1117804qkh.21.1528978425961; Thu, 14 Jun 2018 05:13:45 -0700 (PDT) X-Received: by 2002:a0d:dd09:: with SMTP id g9-v6mr146883ywe.6.1528978425565; Thu, 14 Jun 2018 05:13:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!h2-v6no1069789qtp.0!news-out.google.com!a20-v6ni310qtj.1!nntp.google.com!h2-v6no1069785qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 Jun 2018 05:13:45 -0700 (PDT) In-Reply-To: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.123.98.173; posting-account=rgRstAgAAAC7K0feT2ahQOjsi4sTksRc NNTP-Posting-Host: 79.123.98.173 References: <887f993c-b7db-453e-911f-9ec33b98d91f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <362f436c-6152-40f7-9424-a306f7a97b82@googlegroups.com> Subject: Re: simple unsigned maths problem with if statement From: David Perry Injection-Date: Thu, 14 Jun 2018 12:13:45 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1452 X-Received-Body-CRC: 2571636069 Xref: reader02.eternal-september.org comp.lang.vhdl:9340 Prefer to lay down gates and ditch the VHDL. There are times when I think VHDL might be easier for certain tasks, then I start writing it and wish I'd implemented a schematic.... From newsfish@newsfish Thu Aug 1 00:43:46 2024 X-Received: by 2002:a0c:9373:: with SMTP id e48-v6mr3173186qve.6.1529166140205; Sat, 16 Jun 2018 09:22:20 -0700 (PDT) X-Received: by 2002:a25:d68d:: with SMTP id n135-v6mr272785ybg.6.1529166140058; Sat, 16 Jun 2018 09:22:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder4.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h2-v6no2042556qtp.0!news-out.google.com!a20-v6ni723qtj.1!nntp.google.com!h2-v6no2042548qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 16 Jun 2018 09:22:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.185.58.59; posting-account=oxReiwoAAABA_AObfhLESj8Pqha1sBTJ NNTP-Posting-Host: 94.185.58.59 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ec06b2d-6c7f-4ef1-8da1-dd0e5dc34420@googlegroups.com> Subject: Image/video processing on a Cyclone IV with VHDL and MatLab? From: FPGAnewbie Injection-Date: Sat, 16 Jun 2018 16:22:20 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 15 Xref: reader02.eternal-september.org comp.lang.vhdl:9341 Hey All, Iam a bit new to FPGAs, so please forgive me for my stupid questions. The plan is to develop a face detection system, the camera would be integrated to a DE2-115 board and the result (faces marked or bounded by boxes) would be displayed in a VGA monitor. Again since Iam a bit new to VHDL, i found a code that integrates the camera and the DE2-115 board, the code also displays video stream on a VGA screen. Separately i wrote in MatLab a simple face detection code for a given picture. The reason I used MatLab is because I kina have a bit more understanding (not expert level) in it. Is there anyway to combine the 2? I was thinking of maybe splitting video stream into frames and then applying the face detection code on it. I did look into MatLab to VHDL conversion using Simulink, but is that advisable? Iam open to any other method as well. God bless. From newsfish@newsfish Thu Aug 1 00:43:47 2024 X-Received: by 2002:a37:32c8:: with SMTP id y191-v6mr8216809qky.43.1529376817996; Mon, 18 Jun 2018 19:53:37 -0700 (PDT) X-Received: by 2002:a81:9a4f:: with SMTP id r76-v6mr723347ywg.0.1529376817723; Mon, 18 Jun 2018 19:53:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h2-v6no3146169qtp.0!news-out.google.com!a20-v6ni991qtj.1!nntp.google.com!h2-v6no3146160qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 18 Jun 2018 19:53:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=189.249.150.12; posting-account=0FwgcQoAAACdUGVPgWsLXmEUNIYix8G4 NNTP-Posting-Host: 189.249.150.12 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <248b845d-1361-47b6-9eec-82c41a507322@googlegroups.com> Subject: FIGLI DI PUTTANONE ELISA ISOARDI E MATTEO SALVINI STAN CREANDO LISTE DI PROSCRIZIONE ASSASSINE, SI, ASSASSINE! PER AMMAZZARE, FACENDO PASSARE OMICIDI DA LORO ORDINATI, PER FINTI SUICIDI, MALORI, INCIDENTI, OLTRE CHE TSO KILLER. COME GIA' ACCADETTE... From: SIMONA PREMOLI EX AMANTE DI MARINA BERLUSCONI Injection-Date: Tue, 19 Jun 2018 02:53:37 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 105 Xref: reader02.eternal-september.org comp.lang.vhdl:9342 FIGLI DI PUTTANONE ELISA ISOARDI E MATTEO SALVINI STAN CREANDO LISTE DI PRO= SCRIZIONE ASSASSINE, SI, ASSASSINE! PER AMMAZZARE, FACENDO PASSARE OMICIDI = DA LORO ORDINATI, PER FINTI SUICIDI, MALORI, INCIDENTI, OLTRE CHE TSO KILLE= R. COME GIA' ACCADETTE...... NON PER NIENTE, A RAFFICA, FRA IL 2001 ED IL 2= 006. ALLORCHE' IL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI, INSIEME A= I KUKLUKLANISTI HITLERIANI DI LEGA LADRONA, ORDINAVANO DI "DISARTICOLARE LA= VITA IN MANIERA TRAUMATICA", OSSIA DI UCCIDERE FACENDO PASSARE IL TUTTO PE= R QUALSIASI COSA CHE NON FOSSE OMICIDIO MA CHE OMICIDIO SUPER STRA ERA, CHI= UNQUE CHE NON LECCASSE STE MERDE SANGUINARIE, KILLER, FASCIOMAFIOSE E NAZIN= DRANGHETISTE http://www.pmli.it/sismicolpivanemiciberlusconi.htm=20 IO IN PERSONA, SIMONA PREMOLI, NOTA IN TUTTO IL MONDO PER ESSERE STATA L'EX= AMANTE LESBICA DI MARINA BERLUSCONI, E PER BEN 13 ANNI, OLTRE CHE PER ESSE= RE EX AGENTE SEGRETO DELLA CIA ED IN DIVERSI PAESI DEL PIANETA ( SIA IN BER= LUSCONIA-LEGALADRONUSCONIA, COME A WASHINGTON DC, IN PUERTO RICO, REPUBBLIC= A DOMINICANA, INGHILTERRA, SVIZZERA, ECT ECT), HO RICICLATO ALL'ESTERO MARI= DI EURO CRIMINALISSIMI, STRA RUBATI O FRUTTO DI MEGA MAZZETTE, DA PARTE DI= LEGA LADRONA ( FAMOSI 48 MILIONI DI EURO STRA FOTTUTI DA LEGA LADRONA, PIU= ' MEGA TANGENTI CHE IL PEZZO DI MERDA, VERME HITLERIANO, COCAINOMANE BASTAR= DO MATTEO SALVINI, HA BECCATO NEGLI ULTIMI ANNI DAI SUOI KAMERADEN NAZISTEN= VIKTOR ORBAN, VLADIMIR PUTIN,=20 https://torino.corriere.it/sport/18_maggio_06/de-benedetti-salvini-antisemi= ta-finanziato-putin-leghista-querelo-8b0a05bc-5140-11e8-b393-1dfa8344f8a7.s= html=20 DONALD "PEDOPHILE" TRUMP https://www.huffingtonpost.com/entry/donald-trump-= rape-case_us_581a31a5e4b0c43e6c1d9834 ED IL NOTO COME "POMPINARO DI AUGUSTO= PINOCHET" MIKE POMPEO... NON PER NIENTE, TRATTASI DI STESSISSIMA COSA CHE = LEGA LADRONA USAVA CONCRETIZZARE, NEI FAMOSI ANNI 2001-2006, CON ALTRI DITT= ATORI QUALI GHEDDAFI, MUBARAK E BEN ALI'. http://www.marcogregoretti.it/verita-nascoste/la-lega-nord-era-finanziata-d= a-gheddafi-gossip-elettorale-contro-il-centrodestra-o-storia-vera/ )! CIAO A TUTTI. SONO SIMONA PREMOLI, EX AMANTE DI MARINA BERLUSCONI PER BEN 1= 3 ANNI ED EX AGENTE DELLA CIA IN DIVERSI PAESI DEL MONDO ( BERLUSCONIA-LEGA= LARONUSCONIA, USA, PUERTO RICO, REPUBBLICA DOMINICANA, INGHILTERRA, SVIZZER= A, ECT ECT).=20 https://twitter.com/premolisimona?lang=3Den https://twitter.com/PremoliSimona/status/937885752003723265 https://twitter.com/premolisimona/status/876055837420158976 https://twitter.com/PremoliSimona/status/946915645756715009 https://twitter.com/PremoliSimona/status/946923968245784576 https://twitter.com/PremoliSimona/status/977570748847050754 https://plus.google.com/113646548587006228899 https://it.linkedin.com/pub/dir/Simona/Premoli COME PRIMA CITATO, SONO STATA PER DECENNI DIETRO TANTI RICICLAGGI DI SOLDI = CRIMINALISSIMI, DIREI ASSASSINI, DI LEGA LADRONA: SI, IL PARTITO DI ESTREMI= SSIMA DESTRA DI QUEL FIGLIO DI PUTTANA NAZISTA, RAZZISTA, KUKLUKLANISTA, TU= TT'UNO CON CAMORRA, COSA NOSTRA E E NDRANGHETA, DI MATTEO SALVINI. BEN SPUT= TANATO DA GRANDI GIORNALISTI DE L'ESPRESSO, QUI: https://manueldelia.com/2018/04/lespresso-padani-offshore-the-malta-connect= ion-for-italian-politics-and-money/ http://espresso.repubblica.it/inchieste/2018/05/31/news/alla-lega-sovranist= a-di-matteo-salvini-piace-offshore-1.323128 http://espresso.repubblica.it/inchieste/2018/04/13/news/i-soldi-offshore-de= lla-fondazione-targata-lega-1.320530 http://espresso.repubblica.it/inchieste/2018/03/28/news/i-conti-segreti-di-= matteo-salvini-1.320080 .=20 E DA AMMIRABILISSIMO GEORGE SOROS QUI: http://www.repubblica.it/economia/2018/06/03/news/soros_preoccupato_della_v= icinanza_del_nuovo_governo_con_la_russia_-198062920/ SON PURE STATA PER TANTISSIMO TEMPO, COMPLICE, COLLUSA, "INTIMISSIMA" COLLA= BORATRICE DEL ^NEOLD^ PIDUISTA, NONCHE' MEGA RICICLA SOLDI DI MAFIE DI TUTT= O IL MONDO: GIANPIERO SAMOR=C3=8C DEL CRIMINALISSIMO MOVIMENTO "MODERATI IN= RIVOLUZIONE", SI, MA DI TIPO MALAVITOSO". ORA PERO' MI INCAZZO E DICO BAST= A A STA FOGNA DI COSA NOSTRA, CAMORRA E NDRANGHETA FINANZIARIA CHE DA SEMPR= E STI PEZZI DI MERDA BERLUSCONAZISTI E PADANAZISTI RAPPRESENTANO ( VI ASSIC= URO, SPESSO PURE PEDOFILI, STRAGISTI ED ASSASSINI, IN QUANTO ORDINANTI DOZZ= INE DI STRAGI E MIGLIAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI ED = INCIDENTI, IL TUTTO VIA VARIE LORO LOGGE MASSONICHE OMICIDA....NE ERO DENTR= O, QUINDI SO' QUESTO ALLA PERFEZIONE PER AVERLO VISSUTO, NON SOLO VISTO... = I BASTARDI ASSASSINI E STRAGISTI SILIVO BERLUSCONI, MASSIMO DORIS ED ENNIO = DORIS ORDINANO DOZZINE DI STRAGI E MIGLIAIA DI OMICIDI MASCHERATI DA FINTI = SUICIDI, MALORI ED INCIDENTI, IL TUTTO VIA VARIE LORO LOGGE MASSONICHE KILL= ER, COME ANCHE ATTRAVERSO MAFIA, CAMORRA, NDRANGHETA, A CUI LAVANO MONTAGNE= DI SOLDI ZUPPI DI SANGUE DI MORTI AMMAZATI, ED ANCOR PIU', ATTRAVERSO LORO= SANGUINARIE NUOVE OVRA E GESTAPO, SIA PUBBLICHE CHE PRIVATE) . GUARDATE BENE QUESTA CHART, ORA, PLS https://www.worldcoinindex.com/coin/eidoo LEGA LADRONA HA RICICLATO 22 MILIONI DI EURO ( PARTE DEI FAMOSI 200 MILIONI= E NON SOLO 48 MILIONI DI EURO RUBATI DA PARTE DI LEGA LADRONA) IN QUESTO I= CO. ATTRAVERSO IL PIU' GRANDE CRIMINALE DELLA FINANZA MONDIALE: TOPO DI FOG= NA, GIA' FINITO 3 VOLTE IN GALERA, PAOLO BARRAI, NATO A MILANO IL 28.6.1965= ( CHE STA A LUGANO, ORA, PER NON FINIRE IN CARCERE A MILANO... PER UNA 4TA= VOLTA... FA PURE RIMA, WAGLIO'). QUESTA ICO HA SEMPRE AVUTO VOLUMI BASSISS= IMI ( SCAMBI PER UNA QUALCHE DECINA DI MIGLIAIA DI EURO AL GIORNO). MA DOPO= CHE IN DATA 3.6.18 HO INIZIATO A SCRIVERE DEI MEGA RICICLAGGI DI SOLDI LER= CISSIMI DI LEGA LADRONA IN CRIMINALISSIMA EIDOO, IN DATA 4 E 5.6.18, LA STE= SSA LEGA LADRONA, HA SUPER STRA OVVIAMENTE DATO ORDINE DI VENDERE EIDOO PER= UN TOTALE DI 11 MILIONI DI EURO. COL STRA PIENO INTENTO DI MONETIZZARE E Q= UINDI FAR SPARIRE LORO CRIMINALISSIMI SOLDI. PIU' PROVA DI COSI', CHE STO P= ONENDO LE DITA SU GIUSTISSIME LORO PIAGHE? IO VOGLIO O MOVIMENTO S STELLE P= IU' PD A PALAZZO CHIGI (MA PD SENZA LA MERDA BERLUSCORROTTA DI MATTEO RENZI= E SUA GANG). O LA RIVOLUZIONE ED A TUTTI I COSTI ( NIENTE NAZISMO DI LEGA = LADRONA NEL MIO PAESE: RESISTENZA ANTI ASSASSINI SWASTIKATI PADANI E DA SUB= ITO)! AVANTI TUTTA. QUESTO ORGANIZZERO' A TUTTI I COSTI!!! E DA CENTINAIA D= I LOGGE MASSONICHE DI TUTTO IL PIANETA TERRA!!!!!!!!!!=20 =E3=80=80 INFINE, UNA COSA DA DONNA, CHE HO PROPRIO SUL GROPPONE!=20 CHE SCHIFOSA PUTTANA E' ELISA ISOARDI: TROIA, NAZISTA, RAZZISTA. A 15 ANNI = LO PRENDEVA NEL CULO E NELLA FIGA, CONTEMPORANEAMENTE, E PER SOLI 30 EURO D= I ALLORA, SIA DA ERNESTO PREATONI, CHE DA FLAVIO BRIATORE ( COME DETTOMI DA= I DUE, DI PERSONA). LA SCORSA ESTATE SCOPAVA ALLO STESSO TEMPO, UN AVVOCATO= CRIMINALE, VICINISSIMO A NDRANGHETA, CAMORRA E A COSA NOSTRA, TALE MATTEO = PLACIDI... E LA BESTIA HITLERIANA, MEGA FREGA SOLDI, FASCISTA, KUKLUKLANIST= A, COCAINOMANE, CORROTTA, INSOMMA, IL NOTO FIGLIO DI TROIONA, BASTARDO, ASS= ASSINO MATTEO SALVINI! From newsfish@newsfish Thu Aug 1 00:43:47 2024 X-Received: by 2002:ac8:3417:: with SMTP id u23-v6mr8661461qtb.9.1529376829718; Mon, 18 Jun 2018 19:53:49 -0700 (PDT) X-Received: by 2002:a25:e0d3:: with SMTP id x202-v6mr760859ybg.7.1529376829387; Mon, 18 Jun 2018 19:53:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder4.usenet.farm!feed.usenet.farm!border1.nntp.ams1.giganews.com!nntp.giganews.com!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.69.MISMATCH!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!h2-v6no3146251qtp.0!news-out.google.com!a20-v6ni991qtj.1!nntp.google.com!h2-v6no3146250qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 18 Jun 2018 19:53:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=189.249.150.12; posting-account=0FwgcQoAAACdUGVPgWsLXmEUNIYix8G4 NNTP-Posting-Host: 189.249.150.12 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <15387175-c2d9-4163-9968-91f9c52ca254@googlegroups.com> Subject: IL BASTARDO ASSASSINO MATTEO SALVINI (I CUI FIGLI, FIGLI PURE "DI NAZITROIE", FEDERICO SALVINI E MIRTA SALVINI, SI DOVREBBER STRA VERGOGNARE) STA CREANDO LISTE DI PROSCRIZIONE ASSASSINE, SI, ASSASSINE! PER AMMAZZARE, FACENDO PASSARE OMICIDI DA LUI.. From: SIMONA PREMOLI EX AMANTE DI MARINA BERLUSCONI Injection-Date: Tue, 19 Jun 2018 02:53:49 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 8731 X-Received-Body-CRC: 2976078605 Lines: 105 Xref: reader02.eternal-september.org comp.lang.vhdl:9343 IL BASTARDO ASSASSINO MATTEO SALVINI (I CUI FIGLI, FIGLI PURE "DI NAZITROI= E", FEDERICO SALVINI E MIRTA SALVINI, SI DOVREBBER STRA VERGOGNARE) STA CRE= ANDO LISTE DI PROSCRIZIONE ASSASSINE, SI, ASSASSINE! PER AMMAZZARE, FACENDO= PASSARE OMICIDI DA LUI.......... ORDINATI, PER FINTI SUICIDI, MALORI, INCI= DENTI, OLTRE CHE TSO KILLER. COME GIA' ACCADETTE, NON PER NIENTE, A RAFFICA= , FRA IL 2001 ED IL 2006. ALLORCHE' IL PEDOFILO SPAPPOLA MAGISTRATI SILVIO = BERLUSCONI, INSIEME AI KUKLUKLANISTI HITLERIANI DI LEGA LADRONA, ORDINAVANO= DI "DISARTICOLARE LA VITA IN MANIERA TRAUMATICA", OSSIA DI UCCIDERE FACEND= O PASSARE IL TUTTO PER QUALSIASI COSA CHE NON FOSSE OMICIDIO MA CHE OMICIDI= O SUPER STRA ERA, CHIUNQUE CHE NON LECCASSE STE MERDE SANGUINARIE, KILLER, = FASCIOMAFIOSE E NAZINDRANGHETISTE http://www.pmli.it/sismicolpivanemiciberlusconi.htm=20 IO IN PERSONA, SIMONA PREMOLI, NOTA IN TUTTO IL MONDO PER ESSERE STATA L'EX= AMANTE LESBICA DI MARINA BERLUSCONI, E PER BEN 13 ANNI, OLTRE CHE PER ESSE= RE EX AGENTE SEGRETO DELLA CIA ED IN DIVERSI PAESI DEL PIANETA ( SIA IN BER= LUSCONIA-LEGALADRONUSCONIA, COME A WASHINGTON DC, IN PUERTO RICO, REPUBBLIC= A DOMINICANA, INGHILTERRA, SVIZZERA, ECT ECT), HO RICICLATO ALL'ESTERO MARI= DI EURO CRIMINALISSIMI, STRA RUBATI O FRUTTO DI MEGA MAZZETTE, DA PARTE DI= LEGA LADRONA ( FAMOSI 48 MILIONI DI EURO STRA FOTTUTI DA LEGA LADRONA, PIU= ' MEGA TANGENTI CHE IL PEZZO DI MERDA, VERME HITLERIANO, COCAINOMANE BASTAR= DO MATTEO SALVINI, HA BECCATO NEGLI ULTIMI ANNI DAI SUOI KAMERADEN NAZISTEN= VIKTOR ORBAN, VLADIMIR PUTIN,=20 https://torino.corriere.it/sport/18_maggio_06/de-benedetti-salvini-antisemi= ta-finanziato-putin-leghista-querelo-8b0a05bc-5140-11e8-b393-1dfa8344f8a7.s= html=20 DONALD "PEDOPHILE" TRUMP https://www.huffingtonpost.com/entry/donald-trump-= rape-case_us_581a31a5e4b0c43e6c1d9834 ED IL NOTO COME "POMPINARO DI AUGUSTO= PINOCHET" MIKE POMPEO... NON PER NIENTE, TRATTASI DI STESSISSIMA COSA CHE = LEGA LADRONA USAVA CONCRETIZZARE, NEI FAMOSI ANNI 2001-2006, CON ALTRI DITT= ATORI QUALI GHEDDAFI, MUBARAK E BEN ALI'. http://www.marcogregoretti.it/verita-nascoste/la-lega-nord-era-finanziata-d= a-gheddafi-gossip-elettorale-contro-il-centrodestra-o-storia-vera/ )! CIAO A TUTTI. SONO SIMONA PREMOLI, EX AMANTE DI MARINA BERLUSCONI PER BEN 1= 3 ANNI ED EX AGENTE DELLA CIA IN DIVERSI PAESI DEL MONDO ( BERLUSCONIA-LEGA= LARONUSCONIA, USA, PUERTO RICO, REPUBBLICA DOMINICANA, INGHILTERRA, SVIZZER= A, ECT ECT).=20 https://twitter.com/premolisimona?lang=3Den https://twitter.com/PremoliSimona/status/937885752003723265 https://twitter.com/premolisimona/status/876055837420158976 https://twitter.com/PremoliSimona/status/946915645756715009 https://twitter.com/PremoliSimona/status/946923968245784576 https://twitter.com/PremoliSimona/status/977570748847050754 https://plus.google.com/113646548587006228899 https://it.linkedin.com/pub/dir/Simona/Premoli COME PRIMA CITATO, SONO STATA PER DECENNI DIETRO TANTI RICICLAGGI DI SOLDI = CRIMINALISSIMI, DIREI ASSASSINI, DI LEGA LADRONA: SI, IL PARTITO DI ESTREMI= SSIMA DESTRA DI QUEL FIGLIO DI PUTTANA NAZISTA, RAZZISTA, KUKLUKLANISTA, TU= TT'UNO CON CAMORRA, COSA NOSTRA E E NDRANGHETA, DI MATTEO SALVINI. BEN SPUT= TANATO DA GRANDI GIORNALISTI DE L'ESPRESSO, QUI: https://manueldelia.com/2018/04/lespresso-padani-offshore-the-malta-connect= ion-for-italian-politics-and-money/ http://espresso.repubblica.it/inchieste/2018/05/31/news/alla-lega-sovranist= a-di-matteo-salvini-piace-offshore-1.323128 http://espresso.repubblica.it/inchieste/2018/04/13/news/i-soldi-offshore-de= lla-fondazione-targata-lega-1.320530 http://espresso.repubblica.it/inchieste/2018/03/28/news/i-conti-segreti-di-= matteo-salvini-1.320080 .=20 E DA AMMIRABILISSIMO GEORGE SOROS QUI: http://www.repubblica.it/economia/2018/06/03/news/soros_preoccupato_della_v= icinanza_del_nuovo_governo_con_la_russia_-198062920/ SON PURE STATA PER TANTISSIMO TEMPO, COMPLICE, COLLUSA, "INTIMISSIMA" COLLA= BORATRICE DEL ^NEOLD^ PIDUISTA, NONCHE' MEGA RICICLA SOLDI DI MAFIE DI TUTT= O IL MONDO: GIANPIERO SAMOR=C3=8C DEL CRIMINALISSIMO MOVIMENTO "MODERATI IN= RIVOLUZIONE", SI, MA DI TIPO MALAVITOSO". ORA PERO' MI INCAZZO E DICO BAST= A A STA FOGNA DI COSA NOSTRA, CAMORRA E NDRANGHETA FINANZIARIA CHE DA SEMPR= E STI PEZZI DI MERDA BERLUSCONAZISTI E PADANAZISTI RAPPRESENTANO ( VI ASSIC= URO, SPESSO PURE PEDOFILI, STRAGISTI ED ASSASSINI, IN QUANTO ORDINANTI DOZZ= INE DI STRAGI E MIGLIAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI ED = INCIDENTI, IL TUTTO VIA VARIE LORO LOGGE MASSONICHE OMICIDA....NE ERO DENTR= O, QUINDI SO' QUESTO ALLA PERFEZIONE PER AVERLO VISSUTO, NON SOLO VISTO... = I BASTARDI ASSASSINI E STRAGISTI SILIVO BERLUSCONI, MASSIMO DORIS ED ENNIO = DORIS ORDINANO DOZZINE DI STRAGI E MIGLIAIA DI OMICIDI MASCHERATI DA FINTI = SUICIDI, MALORI ED INCIDENTI, IL TUTTO VIA VARIE LORO LOGGE MASSONICHE KILL= ER, COME ANCHE ATTRAVERSO MAFIA, CAMORRA, NDRANGHETA, A CUI LAVANO MONTAGNE= DI SOLDI ZUPPI DI SANGUE DI MORTI AMMAZATI, ED ANCOR PIU', ATTRAVERSO LORO= SANGUINARIE NUOVE OVRA E GESTAPO, SIA PUBBLICHE CHE PRIVATE) . GUARDATE BENE QUESTA CHART, ORA, PLS https://www.worldcoinindex.com/coin/eidoo LEGA LADRONA HA RICICLATO 22 MILIONI DI EURO ( PARTE DEI FAMOSI 200 MILIONI= E NON SOLO 48 MILIONI DI EURO RUBATI DA PARTE DI LEGA LADRONA) IN QUESTO I= CO. ATTRAVERSO IL PIU' GRANDE CRIMINALE DELLA FINANZA MONDIALE: TOPO DI FOG= NA, GIA' FINITO 3 VOLTE IN GALERA, PAOLO BARRAI, NATO A MILANO IL 28.6.1965= ( CHE STA A LUGANO, ORA, PER NON FINIRE IN CARCERE A MILANO... PER UNA 4TA= VOLTA... FA PURE RIMA, WAGLIO'). QUESTA ICO HA SEMPRE AVUTO VOLUMI BASSISS= IMI ( SCAMBI PER UNA QUALCHE DECINA DI MIGLIAIA DI EURO AL GIORNO). MA DOPO= CHE IN DATA 3.6.18 HO INIZIATO A SCRIVERE DEI MEGA RICICLAGGI DI SOLDI LER= CISSIMI DI LEGA LADRONA IN CRIMINALISSIMA EIDOO, IN DATA 4 E 5.6.18, LA STE= SSA LEGA LADRONA, HA SUPER STRA OVVIAMENTE DATO ORDINE DI VENDERE EIDOO PER= UN TOTALE DI 11 MILIONI DI EURO. COL STRA PIENO INTENTO DI MONETIZZARE E Q= UINDI FAR SPARIRE LORO CRIMINALISSIMI SOLDI. PIU' PROVA DI COSI', CHE STO P= ONENDO LE DITA SU GIUSTISSIME LORO PIAGHE? IO VOGLIO O MOVIMENTO S STELLE P= IU' PD A PALAZZO CHIGI (MA PD SENZA LA MERDA BERLUSCORROTTA DI MATTEO RENZI= E SUA GANG). O LA RIVOLUZIONE ED A TUTTI I COSTI ( NIENTE NAZISMO DI LEGA = LADRONA NEL MIO PAESE: RESISTENZA ANTI ASSASSINI SWASTIKATI PADANI E DA SUB= ITO)! AVANTI TUTTA. QUESTO ORGANIZZERO' A TUTTI I COSTI!!! E DA CENTINAIA D= I LOGGE MASSONICHE DI TUTTO IL PIANETA TERRA!!!!!!!!!!=20 =E3=80=80 INFINE, UNA COSA DA DONNA, CHE HO PROPRIO SUL GROPPONE!=20 CHE SCHIFOSA PUTTANA E' ELISA ISOARDI: TROIA, NAZISTA, RAZZISTA. A 15 ANNI = LO PRENDEVA NEL CULO E NELLA FIGA, CONTEMPORANEAMENTE, E PER SOLI 30 EURO D= I ALLORA, SIA DA ERNESTO PREATONI, CHE DA FLAVIO BRIATORE ( COME DETTOMI DA= I DUE, DI PERSONA). LA SCORSA ESTATE SCOPAVA ALLO STESSO TEMPO, UN AVVOCATO= CRIMINALE, VICINISSIMO A NDRANGHETA, CAMORRA E A COSA NOSTRA, TALE MATTEO = PLACIDI... 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From newsfish@newsfish Thu Aug 1 00:43:47 2024 X-Received: by 2002:a37:aa4e:: with SMTP id t75-v6mr5359007qke.2.1532005268876; Thu, 19 Jul 2018 06:01:08 -0700 (PDT) X-Received: by 2002:a5b:60f:: with SMTP id d15-v6mr1013450ybq.6.1532005268501; Thu, 19 Jul 2018 06:01:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!f6-v6no1066047qth.0!news-out.google.com!u13-v6ni530qtg.0!nntp.google.com!f6-v6no1066044qth.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Jul 2018 06:01:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.229.253.9; posting-account=djiNsgoAAADvPOF9hYCv4lLb8bDaDs6L NNTP-Posting-Host: 41.229.253.9 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4d114758-cd63-4e74-a2dd-cd24f4e07faa@googlegroups.com> Subject: code source AES From: addali.achraf@gmail.com Injection-Date: Thu, 19 Jul 2018 13:01:08 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 0 Xref: reader02.eternal-september.org comp.lang.vhdl:9344 bonjour tous les monde je cherche code source de cryptage et decryptage en vhdl From newsfish@newsfish Thu Aug 1 00:43:48 2024 X-Received: by 2002:ae9:c118:: with SMTP id z24-v6mr5971485qki.34.1532287806638; Sun, 22 Jul 2018 12:30:06 -0700 (PDT) X-Received: by 2002:a25:8203:: with SMTP id q3-v6mr200483ybk.1.1532287806436; Sun, 22 Jul 2018 12:30:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!s10-v6no793664qth.0!news-out.google.com!e39-v6ni110qtb.0!nntp.google.com!s10-v6no793659qth.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 22 Jul 2018 12:30:06 -0700 (PDT) In-Reply-To: <4d114758-cd63-4e74-a2dd-cd24f4e07faa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=89.98.20.115; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 89.98.20.115 References: <4d114758-cd63-4e74-a2dd-cd24f4e07faa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: code source AES From: Igmar Palsenberg Injection-Date: Sun, 22 Jul 2018 19:30:06 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 3 X-Received-Bytes: 1480 X-Received-Body-CRC: 4175052265 Xref: reader02.eternal-september.org comp.lang.vhdl:9345 On Thursday, 19 July 2018 15:01:10 UTC+2, Addali Achraf wrote: > bonjour tous les monde je cherche code source de cryptage et decryptage en vhdl Try again in English. From newsfish@newsfish Thu Aug 1 00:43:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: Re: code source AES Date: Mon, 23 Jul 2018 22:17:14 +0300 Organization: Aioe.org NNTP Server Lines: 11 Message-ID: References: <4d114758-cd63-4e74-a2dd-cd24f4e07faa@googlegroups.com> NNTP-Posting-Host: Zcja1ntJPCfIb14q3TAYOQ.user.gioia.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.0 X-Notice: Filtered by postfilter v. 0.8.3 X-Antivirus: AVG (VPS 180723-4, 23/07/2018), Outbound message Content-Language: en-US X-Antivirus-Status: Clean Xref: reader02.eternal-september.org comp.lang.vhdl:9346 On 7/19/2018 4:01 PM, addali.achraf@gmail.com wrote: > bonjour tous les monde je cherche code source de cryptage et decryptage en vhdl > https://github.com/pnvamshi/Hardware-Implementation-of-AES-VHDL --- Cet email a fait l'objet d'une analyse antivirus par AVG. http://www.avg.com From newsfish@newsfish Thu Aug 1 00:43:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!news.uni-stuttgart.de!news-1.dfn.de!news.dfn.de!news.hs-bremen.de!.POSTED!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: code source AES Date: Fri, 27 Jul 2018 12:02:17 +0200 Organization: Hochschule Bremen Lines: 14 Message-ID: References: <4d114758-cd63-4e74-a2dd-cd24f4e07faa@googlegroups.com> NNTP-Posting-Host: sta-13-193.fk4.hs-bremen.de Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.hs-bremen.de 1532685737 20098 194.94.26.193 (27 Jul 2018 10:02:17 GMT) X-Complaints-To: usenet@news.hs-bremen.de NNTP-Posting-Date: Fri, 27 Jul 2018 10:02:17 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 In-Reply-To: <4d114758-cd63-4e74-a2dd-cd24f4e07faa@googlegroups.com> Content-Language: de-DE Xref: reader02.eternal-september.org comp.lang.vhdl:9347 On 19.07.2018 15:01, addali.achraf@gmail.com wrote: > bonjour tous les monde je cherche code source de cryptage et decryptage en vhdl > bonjour trouvez le code puor AES et autres cores a opencores.org. Hello Addali, use english language in the forum, to reach more people. You can find the VHDL sources for AES and many other IP cores at opencores.org . Kind regards Eilert From newsfish@newsfish Thu Aug 1 00:43:49 2024 X-Received: by 2002:a37:4d4a:: with SMTP id a71-v6mr2930859qkb.18.1533259006777; Thu, 02 Aug 2018 18:16:46 -0700 (PDT) X-Received: by 2002:a0d:cb03:: with SMTP id n3-v6mr120401ywd.0.1533259006408; Thu, 02 Aug 2018 18:16:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder4.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!e8-v6no496144qtp.0!news-out.google.com!g23-v6ni197qtp.0!nntp.google.com!e8-v6no496139qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 2 Aug 2018 18:16:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.52.168.190; posting-account=h5h-SwoAAADcc_e83pZ0Y3HaAOZ8ZvpK NNTP-Posting-Host: 108.52.168.190 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: PipelineC From: Julian Kemmerer Injection-Date: Fri, 03 Aug 2018 01:16:46 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 16 Xref: reader02.eternal-september.org comp.lang.vhdl:9348 Hi folks, I have a little project I've been working on to make a better HDL-like language. It's a subset of C so should be familiar. I am using a Digilent Arty Artix-35T board and have a working UDP example. I am looking for opinions on current progress and ideas for what features/projects to pursue next. Also, if you like correcting bad python - heyo! Check it out eh: https://github.com/JulianKemmerer/PipelineC Thanks, Julian From newsfish@newsfish Thu Aug 1 00:43:49 2024 X-Received: by 2002:a37:b185:: with SMTP id a127-v6mr4593463qkf.6.1533316697245; Fri, 03 Aug 2018 10:18:17 -0700 (PDT) X-Received: by 2002:a81:a611:: with SMTP id d17-v6mr171009ywh.2.1533316697041; Fri, 03 Aug 2018 10:18:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!feeder2.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!e8-v6no763393qtp.0!news-out.google.com!e6-v6ni275qte.1!nntp.google.com!e8-v6no763392qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Aug 2018 10:18:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.199.241.231; posting-account=iWFbVQoAAAAJOPUo5toSs2fFNVw8BQDU NNTP-Posting-Host: 128.199.241.231 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9f764590-fd7f-4e7e-868d-7cb50d34b2e6@googlegroups.com> Subject: Electric Circuits 7th edition by Nilsson From: solutionsbookteam@gmail.com Injection-Date: Fri, 03 Aug 2018 17:18:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 1109 Xref: reader02.eternal-september.org comp.lang.vhdl:9349 solutions book team=20 s o l u t i o n s b o o k t e a m @ h o t m a i l . c o m solutionsbookteam(at)hotmail(dot)com=20 solutionsbookteam@hotmail.com We're a team for providing solution manuals to help students in their=20 study.=20 We sell the books in a soft copy, PDF format.=20 We will find any book or solution manual for you.=20 Just email us:=20 s o l u t i o n s b o o k t e a m @ h o t m a i l . c o m List of some books we have=20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=20 A Course in Modern Mathematical Physics by Peter Szekeres A First Course in Abstract Algebra By John B. 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Levi Applied Statistics And Probability For Engineers , 2nd ed , By Montgomery, = Runger Applied Statistics And Probability For Engineers 3rd edition By Montgomery,= Runger Applied Statistics And Probability For Engineers 4th edition By Montgomery,= Runger Applied Strength of Materials 4th Edition By Robert L. Mott Artificial Intelligence A Modern Approach , By Russell and Norvig , 2nd ed Artificial Intelligence A Modern Approach , By S. Russell, P. Norvig , 3rd = ed Artificial Intelligence A ModernApproach 2nd edition by StuartJ. Russelland= , Peter Norvig Assembly Language for Intel-Based Computers,3ed, by Kip R. Irvine Astronomy Today , McMillan & Chaisson , 5th ed Atkins' Physical Chemistry ,Peter Atkins and Julio de Paula ,10th ed Auditing & assurance services , By Louwers & Sinason & Straeser & Ramsy , 2= nd ed Auditing and Assurance Services , By Arens. Elder and Beasley and Randal J.= Elder , 13th ed Automatic control systems , By Benjamin C. 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Deitel C++ How to Program, 3rd edition By Deitel & Nieto Calculus , By (Narberg , Purcell , Rigdon) , 8th Edition (Solutions Manual = and Test Bank) , Prentice Hall 2000 Calculus , By James Stewart , 4th ed Calculus 5th Edition By James Stewart Calculus 8th Ed by Larson, Hostetler, Edwards Calculus A Complete Course 6th Edition by R.A. Adams calculus An intuitive And physical approach , 2nd ed , By Morris Kline Calculus Early Transcedentals ,By Stewart , 6th ed Calculus Early Transcedentals ,By Stewart ,5th ed Calculus Early Transcendental - Edwards, Penney - 6ed Calculus Early Transcendental Functions , By R. Smith, R. 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Marion Classical Electrodynamics , By John David Jackson , 3rd ed Classical Electrodynamics 2nd Edition by John David Jackson by Kasper van W= ijk Classical Mechanics - An Undergraduate Text by R. Douglas Gregory Classical Mechanics 2nd edition By Goldstein & Safko classical thermodynamics of Non-Electrolyte , By H. C. Van ness 1st ed CMOS Digital Integrated Circuits 3rd edition By Sung-Mo Kang,Yusuf Leblebic= i CMOS VLSI Design 3e by ananymous College Physics , By Faughn and Serway and vuille , 6th ed COLLEGE PHYSICS , by SERWAY AND VUILLE=E2=80=99S , 9th ed Communication Networks Fundamental Concepts and Key Architectures Alberto L= eon-Garcia Communication Systems 4th ed by bruce carlson Communication Systems 4th edition by Simon Haykin Communication Systems Engineering - Second Edition John G. Proakis Masoud S= alehi Complex Variables and Applications , JW Brown , RV Churchill , 8th ed(2009) complex Variables and applications ,James Ward Brown ,7th ed complex variables with applications ,A. David wunsch ,3th ed Computational Techniques for Fluid Dynamics (Scientific Computation) by Kar= kenahalli Srinivas, Clive A. J. Fletcher Computer Networking A Top-Down Approach 3rd Edition by James F.Kurose,Keith= W. Ross Computer Networks - 4th Edition by Andrew S. Tanenbaum Computer Organization 5th edition by Hamacher,Vranesic and Zaky Computer Organization and Design The HardwareSoftware Interface, 3rd editio= n by David A. Patterson, John L. Hennessy, Computer-Controlled Systems 3rd edition by Karl J. Astrom Comunicacion Satelital , Timothy Pratt & Charles Bostian , 2nd ed concepts and applications of finite element analysis , Robert Cook and Davi= d s. Malkus and Michael E. Plesha , 4th ed Concepts of Programming Languages 7th edition Solutions Manual by Robert Se= besta Contemporary Engineering Economics , By Chan S. Park , 4t ed Contemporary Engineering Economy , By William G. Sullivan and Elin M. Wicks= and C. Patrick Koelling , 5th ed Contemporary Linear Algebra , Howard Anton and Robert C. Busby , 1st ed Control systems Principles and Design 2nd Edition by Madan Gopal Control systems engineering , By Norman Nise , 6th ed Control Systems Engineering 4th edition by Norman S. Nise Convection Heat Transfer ,By Adrian Bejan , 3rd ed Corporate Finance solution manual 6th Edition by Ross Cost Accounting , By Horngren , 12th ed Cost Accounting , By Horngren , 13th ed Cost Accounting , By William K. Carter , 14th ed Craig's Soil Mechanics 7th Edition Cryptography and network security-principles and practice 4th ed. By Willia= m Stallings Data and computer communications 7th edition William Stallings Data Communications and Networking 4th edition by Behroz Forouzan Database Management Systems 3rd edition Raghu Ramakrishnan Johannes Gehrke Database System Concepts , A. Silberschatz and H. Korth and S. Sudarshan , = 4th ed Design of Analog CMOS Integrated Circuits Behzad Razavi Design of Concrete Structures , By Arthur H. Nilson , 14th ed Design of Nonlinear Control Systems with the Highest Derivative in Feedback= 1st Edition by Valery D. Yurkevich [student solution manual] Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edit= ion by Franco, Sergio Device Electronics for Integrated Circuits 3rd edition by Muller Kamins Differential Equation , by Richard Bronson 3rd ed Differential Equations and Boundary Value Problems , Edwards & & Penney = , 2nd ed differential equations and boundary value problems computing and modeling ,= By Edwards and Penney , 4th ed differential equations and linear algebra , Jerry Farlow & Beverly H. West = & james-e-hall & jean-marie-mcdill , 2nd ed Differential Equations with Boundary Value Problems 2nd Edition by JOHNPOLK= ING and DAVID ARNOLD Differential Equations with Boundary Value Problems, 2nd edition by John Po= lking Digital and Analog Communication Systems 7th Edition by Leon W. Couch Digital Communication 4th edition by Proakis Digital Communications 5th edition by John Proakis Digital Communications Fundamentals and Applications, 2nd Edition by Bernar= d sklar Digital Control and state variable methods - M.Gopal Digital Design 2nd Edition by M. Morris Mano,Michael D. Ciletti Digital Design 3rd Edition by M. Morris Mano,Michael D. Ciletti Digital Design 4th edition Morris Mano Digital Design-Principles and Practices 3rd Edition by John F. Wakerly [sel= ected problems] Digital Fundamentals 9th edition by Thomas L. Floyd Digital Image Processing 2nd edition by Rafael C. Gonzalez Digital Integrated Circuits 2nd edition by Rabaey Digital Integrated Circuits by Thomas A. DeMassa & Zack Ciccone Digital Logic Design 2nd edition by M. Morris Mano Digital Signal Processing - A Modern Introduction, 1st Edition Cengage lear= ning Ashok Ambardar Digital Signal Processing , Proakis and Manolakis , 1st ed Digital Signal Processing ; A Computer-Based Approach 1st edition By sanji= t K. Mitra Digital Signal Processing 2nd Edition by Mitra Digital Signal Processing 3nd Edition by Mitra Digital Signal Processing 4th edition by John G. Proakis and Dimitri s G. M= anolakis Digital Signal processing Acomputer - based Approach , By Sanjit K. Mitra Digital Signal Processing by Thomas J. Cavicchi Digital signal processing proakis manolakis Digital Signal Processing Signals, Systems, and Filters Andreas Antoniou Digital Signal Processing Using Matlab 2nd edition by Vinay K Ingle Proakis Digital Systems-Principles and Applications 10th Ed. by Ronald Tocci, Neal = S. Widmer & Gregory L. Moss Discretas mathematics , By Richard Johnsonbaugh , 6th ed Discrete and Combinatorial Mathematics , By R. Grimaldi , 5ed Part 1 Discrete Mathematics with Applications Third Edition By Susanna S. Epp discrete Time control systems (Sistemas de control en tiempo discreto) , 2n= d ed , Katsuhiko ogata Discrete Time Signal Processing 2nd Edition, by Alan V. Oppenheim Discrete time signal processing 3rd edition by Oppenheim Dise?o con Amplificadores Operacionales y Circuitos Integrados Anal?gicos(D= esign with Operational Amplifiers and Analog Integrated Circuits) , By Serg= io Franco , 3th ed Dynamics of Mechanical Systems , By Carl T. F. Ross , 7th ed Dynamics Structures theory and applications to earthquake engineering , By = Anil K. Chopra , 3th ed Econometric Analysis 5th Edition by William H. Greene Economic engineering , L. Blank and A. Tarkin , 6th ed Electric Circuits 7th edition by Nilsson Electric Circuits 8th edition by Nilsson Electric Machinery 6th Edition by Fitzgerald Kingsley Electric Machinery and Power System Fundamentals 1st edition by Stephen Cha= pman Electric Machinery Fundamentals 4th edition by Stephen J. Chapman Electric machines , By Jesus Fraile Mora , 5th ed Electric Machines Analysis and Design Applying MATLAB by Jim Cathey Electrical Engineering Principles and Applications 3rd edition by Allan R. = Hambley Electrical Machines, Drives and Power Systems 6th edition By Theodore Wildi Electrical Properties of Materials ,Solymar & Walsh , 7th ed Electricity and magnetism (Electricidad y Magnetismo) , By Raymond A. Serwa= y , 6th ed Electricity and magnetism , By Raymond A. Serway , 3rd ed electricity and magnetism Vol.II , Edward M. Purcell , 2nd ed Electromagnetic Fields and Energy 1st Ed. by Haus and Melcher Electromagnetics for Engineers by Ulaby Electromagnetism Major American Universities Ph.D. Qualifying Questions and= Solutions by Lim Yung-Kuo Electron Paramagnetic Resonance ,Victor Chechik, Emma Carter, and Damien Mu= rphy ,2016 Electronic Circuit Analysis and Design 2nd edition by Donald A. Neamen Electronic devices - electron flow version 4th edition by thomas l.floyd Electronic Devices and Circuit Theory 8th Ed. with Lab Solutions, and Test= Item File by Robert Boylestad Electronic Devices and electronic devices , By thomas L. Floyd , 6th ed Electronic Devices-6th Edition by Thomas L. Floyd Electronic Physics by Strabman Elementary Applied Partial Differential Equations with Fourier Series and B= oundary Value Problems , PrenticeHall , R.Haberman (1987) Elementary Differential Equations , 8th ed. , By Werner Kohler, Lee Johnson Elementary Differential Equations , Penny , 5th ed Elementary Differential Equations , Werner Kohler & Lee Johnson , 1st ed Elementary Differential Equations 8th edition by Boyce Elementary Differential Equations And Boundary Value Problems, 7Th Edition = by Boyce And Diprima Elementary Differential Equations and Elementary Differential Equations wit= h Boundary Value Problems , William F. Trench , 2000 Elementary Linear Algebra with Applications 9th by Howard Anton, Chris Rorr= es Elementary Linear Algebra With Applications 10E , Howard Anton, Chris Rorre= s Elementary Mechanics and Thermodynamics by Jhon W. Norbury , 1st ed Elementary Number Theory and Its Applications, 5th edition by Kenneth H. Ro= sen Elementary Number Theory and Its Applications, 6th Ed. By Kenneth H. Rosen Elementary Principles of Chemical Processes 3rd edition by Richard M. Felde= r,Ronald W. Rousseau Elementary statistics Using the Graphing Calculator , Mario F. Triola 2005 Elements of Chemical Reaction Engineering, 3rd Edition by H. Scott Fogler Elements of Deductive Inference , By Joseph Bessie and Stuart Glennan , 1st= ed Elements of electromagnetics 2nd edition by sadiku Elements of electromagnetics 3rd edition by sadiku Elements of Power System Analysis 4th edition by William D. Stevenson Embedded Microcomputer Systems Real Time Interfacing 2nd Edition by Jonatha= n W. Valvano Energy Science ,Principles, Technologies, and Impacts ,Andrews & Jelley ,3t= h e Energy Systems Engineering evaluation and implementation , Francis M Vanek = and Louis D Albright , 1st ed Engineering Circuit Analysis 6th edition by Hayt Engineering Circuit Analysis 7th edition by Hayt Engineering Electromagnetics - 7th Ed. - Hayt Engineering Electromagnetics 2d Edition by Nathan Ida Engineering Electromagnetics 6th Edition by William H. Hayt Jr. and Hohn A.= Buck Engineering Fluid Mechanics 7th edition by Clayton T. Crowe, Donald F. Elge= r & John A. Roberson engineering materials science , By milton ohring , 1st ed Engineering Mathematics 4th edition by John Bird Engineering Mathematics 4th Edition by NEWNES Engineering Mechanic STATICS 10th Ed. R.C. Hibbeler Engineering Mechanics - Dynamics 2 Edition by Riley and Sturges Engineering Mechanics - Dynamics 11th edition by R. C. Hibbeler Engineering Mechanics - STATICS 4th E - Bedford and Fowler Engineering mechanics - statics 10th edition by R. C. Hibbeler engineering mechanics dynamics , By Boresi and schmidt , 1st ed engineering mechanics Dynamics , By Meriam & Kraige & palm , 3rd ed engineering mechanics Dynamics , By Meriam & Kraige & palm , 5rd ed engineering mechanics dynamics , By Meriam and kraige , 6th ed Engineering mechanics Dynamics 4th Ed. by Bedford and Fowler Engineering Mechanics Dynamics 5th J.L Meriam Engineering Mechanics of Solids , By Egor P. Popov , 2nd ed engineering mechanics statics , By Bedford and fowler , 5th ed engineering mechanics statics , By R. C. Hibbeler , 8th ed engineering mechanics statics , By R. C. Hibbeler , 10th ed Engineering Mechanics Statics , By R.C.Hibbeler , 12th ed Engineering Mechanics Statics 6th edition by J.L Meriam Engineering Mechanics Statics 11th Edition By R.C.Hibbeler engineering mechanics statistics , By Meriam & Kraige & palm , 4th ed engineering mechanics statistics , By Meriam & Kraige & palm , 6th ed Engineering Probability and Statistics for Engineers and Scientists Engineering Statistics , By Montgomery , 4th ed Engineering Vibration , 3rd ed , Daniel J. Inman English Grammar Understanding the Basics , By Cambridge , 1st ed Environmental Chemistry , vanLoon & Duffy , 3th ed Experiments with Economic Principles , By Theodore Bergstrom And J. Miller = , 1st ed Feedback Control of Dynamic Systems 4th edition by G. F. Franklin, J. D. Po= well, A. Emami Field and Wave Electromagnetics 2nd Edition by Wesley Cheng Field and Wave Electromagnetics International Edition by David K Financial Accounting , By Harrison and Horngren , 8th ed Financial Accounting information for decisions , John J. Wild , 4th ed Financial Instruments , John Hull , 4ed FINITE MATHEMATICS , Lial , Greenwell & Ritchey , 8th ed Fluid Mechanics , By Frank M. White , 5th ed Fluid mechanics , By Merle C. Potter and David C. Wiggert , 3rd ed Fluid Mechanics , By Russell C. Hibbeler , 1st ed Fluid Mechanics , Munson , 7th ed Fluid Mechanics 1st edition by CENGEL Fluid Mechanics 5th Edition by White Fluid Mechanics and Thermodynamics of Turbomachinery , By Dixon and Hall , = 5th ed Fluid Mechanics Fundamentals and Applications , By Cengel and Cimbala , 1st= ed Fluid Mechanics With Engineering Applications 10th edition by E. John Finne= more, Joseph B Franzini Foundations of Colloid Science ,Hunter ,2nd ed Foundations of International Macroeconomics , By Obstfeld and Rogoff , 1st = ed Foundations of Molecular Structure Determination ,Simon Duckett, Bruce Gilb= ert, and Martin Cockett ,2nd ed Fracture mechanics fundamentals and applications 2nd edition by Northam And= erson Fund of Corporate Finance , by Richard A. Brealey , 4th ed Fundamental of Electric Circuits 3rd editoin by C. K. Alexander M. N. O. Sa= diku Fundamental of engineering electromagnetics by David Cheng Fundamentals od Finanial Management , James Van Horne and John Wachowicz , = 12th ed Fundamentals of Aerodynamics , By John D. Anderson , 3rd ed Fundamentals of Analytical Chemistry , By Holler and Crouch , 9th ed Fundamentals of Applied Electromagnetics , By Faeeaz T. Ulaby Fundamentals of corporate finance , By Ross and Jordan and Westerfield , 8t= h ed Fundamentals of Diferential Equations , By Nagle and Saff and Snider , 6th = ed Fundamentals of differential equations , 7ed.-Pearson (2008) , By R. Kent N= agle , Edward B. Saff , A. David Snider Fundamentals of differntial equations , R. kent nagle & Edward b.saff & A. = David snider , 7th ed Fundamentals of Digital Logic with VDL Desing , By S. Brown and Z. Vranesic= , 1st ed Fundamentals of Digital Logic with Verilog Design 1st edition by S. Brown Z= . Vranesic Fundamentals of Digital Logic with VHDL Design, 1st edt. by S. Brown, Z. Vr= anesic Fundamentals of Digital Signal Processing using MATLAB , By Sandra L. Harri= s and Robert J. Schilling , 2nd Ed Fundamentals of Electric Circuits , 5th ed fundamentals of electric circuits , By Alexander and Sadiku , 4th ed Fundamentals of Electric Circuits 2nd edition by C. K. Alexander M. N. O. S= adiku Fundamentals of Electric Circuits, 3rd edition by C. K. Alexander M. N. O. = Sadiku fundamentals of engineering thermodynamics , By Moran & Shapiro , 5th ed fundamentals of engineering thermodynamics , By Moran & Shapiro , 6th ed Fundamentals of engineering thermodynamics by m. j. moran h. n. shapiro Fundamentals of Financial Management , and E. Brigham, J. Houston , 12th ed Fundamentals of Fluid mechanics 4th edition by Munson Fundamentals of Fluid Mechanics Student Solutions Manual, 3rd Edition [Stud= ent solution manual] Fundamentals of heat and mass transfer , By Incropera & Lavine & Dewitt & B= ergman , 5th ed Fundamentals of heat and mass transfer , By Incropera & Lavine & Dewitt & B= ergman , 6th ed Fundamentals of Heat and Mass Transfer 4th edition by Incropera & Dewitt Fundamentals of logic design 5th edition by Charles Roth Fundamentals of Machine Component Design - 3rd edition by Robert C. Juvinal= l and Kurt M. Marshek Fundamentals of Machine Component Design 4th edition by Robert C. Juvinall,= Kurt M. Marshek Fundamentals of Machine Component Desing , By R. Juvinall. K. Marshek , 1st Fundamentals of Machine Elements , By Steven Schmid and Bernard Hamrock and= Bo. Jacobson , 2nd ed fundamentals of manufacturing , By philip D. Rufe , 2nd ed FUNDAMENTALS OF MODERN MANUFACTURING , (MATERIALS, PROCESSES, AND SYSTEMS) = , By MIKELL P. GROOVER , 2nd ed FUNDAMENTALS OF MODERN MANUFACTURING , (MATERIALS, PROCESSES, AND SYSTEMS) = , By MIKELL P. GROOVER , 3rd ed FUNDAMENTALS OF MODERN MANUFACTURING , (MATERIALS, PROCESSES, AND SYSTEMS) = , By MIKELL P. GROOVER , 4th ed Fundamentals of Momentum, Heat, and Mass Transfer , By Welty and Wicks and = Wilson and Rorrer , 5th ed Fundamentals of Organic Chemistry , By Solomon , 5th ed Fundamentals of Physics (Extended) , by Halliday , Resnick & J. Walker , 9t= h ed , pp.1643, (Wiley, 2011) Fundamentals of Physics 7th edition by Halliday, Resnick and Walker Fundamentals of physics 8th edition by Halliday, Resnick and Walker Fundamentals of Physics Extended , By Halliday and Resnick , 8th ed fundamentals of physics Vol.1 vol.2 , By Halliday and Resnick , 6th ed Fundamentals of Power Electronics 2nd edition by R.W. Erickson Fundamentals of Power Semiconductor Devices 1st Ed. by B. Jayant Baliga Fundamentals of Quantum Mechanics for solid state electronics and optics , = By C.L. Tang , 1st ed Fundamentals of signals and systems , By Michael J. Roberts . 1st ed Fundamentals of Signals and systems using web and matlab third edition by E= dward W. Kamen, Bonnie S Heck Fundamentals of Solid-State Electronics by Chih-Tang Sah Fundamentals of Thermal Fluid Sciences by Yunus A. Cengel, Robert H. Turner= , Yunus Cengel, Robert Turner Fundamentals of Thermodynamics by Richard Sonntag Claus Borgnakke Gordon Va= n Wylen Fundamentals of Wireless Communication by Tse and Viswanath General Chemistry , By Ebbing and Gammon , 10th ed General Chemistry, Principles and Modern Applications , By Petrucci and Har= wood and Herring , 8th ed general organic and biological chemist structures of life , By Karen C. Tim= berlake , 2nd ed Guide for Microprocessors and Interfacing , By Douglas Hail , 2nd ed Heat and Mass transfer A practical Approach , Yunus A. Cengel , 3rd ed Heat Transfer A Practical Approach 2nd edition by Yunus A. Cengel, Yunus Ce= ngel How English Works A Grammar Handbook with Readings Instructor's Manual by A= nn Raimes Hydraulics in Civil and Environmental Engineering , 4th ed , by Chadwick & = Morfett Heating ventilating and air conditioning Analysis and Design , By McQuiston= and Parker and Spitler , 6th ed Inorganic Chemistry ,Almond, Spillman & Page Interfacial Science An Introduction ,Geoffrey Barnes and Ian Gentle ,2nd ed Intermediate Accounting , By Kieso , 13th ed International Trade , By Robert Feenstra and Alan Taylor , 2nd ed Introduction to Abstract Algebra, Solutions Manual , By W. Keith Nicholson = , 4th ed , 2012 Introduction to Algorithms 2nd edition by Philip Bille Introduction to Algorithms 2nd Edition by Thomas H. Cormen INTRODUCTION TO chemical engineering thermodynamics , By J.R. Elliot and C.= T. Lira , 1st ed INTRODUCTION TO chemical engineering thermodynamics , Smith & Van Ness , 7t= h ed Introduction to chemical engineering thermodynamics 6th edition by j. m. sm= ith Introduction to Communication Systems , 2nd ed , By Ferrel G. Stremler Introduction to Communication Systems 3rd Edition by Stremler Introduction to Computing and Programming with JAVA-A Multimedia Approach 1= st Edition by Mark Guzdial and Barbara Ericson Introduction to Econometrics , By Stock and Watson , 1st ed Introduction to electric circuits 6th edition by Dorf Svaboda Introduction to Electric Circuits 7th edition by Richard C. Dorf & James A.= Svoboda Introduction to elementary particles by D.Griffiths Introduction to Eletrodynamics 3rd ed By David J. Griffiths Introduction to Environmental Engineering and Science 3rd Edition Introduction to Ergonomics By Robert Bridger introduction to fluid mechanics , by Fox and McDonald , 7th ed introduction to fluid mechanics , By Munson and young and Huebsch , 5th ed Introduction to fluid mechanics 5th edition by fox and mcdonald Introduction to fluid mechanics 6th edition by fox and mcdonald Introduction To Fourier Optics , Joseph W. Goodman , 3th ed , 2005 INTRODUCTION TO GRAPH THEORY , Douglas B. West , 2nd ed Introduction to Java Programming 7th edition by Y. Daniel Liang Introduction to Linear Algebra 3rd Edition By Gilbert Strang Introduction to Linear Programming 1st Edition by L. N. Vaserstein [student= solution manual] Introduction to Management Accounting , By Charles T. Horngren and Gary L. = Sundem and William O. Stratton and David Burgstahler and Jeff Schatzberg , = 14th ed Introduction to Managerial Accounting , By Garrison and Noreen and Brewer ,= 5th ed Introduction to Probabilit , By Dimitri P. Bertsekas and John N. Tsitsiklis= , 1st ed Introduction to Probability and Statistics , By Barbara M. Beaver , 12th Ed Introduction to Probability Models , (10th Ed) , By Sheldon M. Ross Introduction to Quantum Mechanics (1995) by David J. Griffiths , 2nd=20 Introduction to Solid State Physics by Charles Kittel Introduction to Statics and Dynamics , By Ruina & Pratap , 1st ed Introduction to the Theory of Computation , By Michael Sipser , 1st ed Introduction to Thermal Systems Engineering , M. Moran. H. Shapiro , 1st ed Introduction to Thermodynamics and Heat Transfer , yunus A. cengel , 2nd e= d Introduction to VLSI Circuits and Systems John P Uyemura Introduction to Wireless Systems by P.M. Shankar Introductory Circuit Analysis , By Robert L. Boylestad , 11th ed Introductory Econometrics A Modern Approach , Jeffrey M. Wooldridge , 2ed introductory elements of the chemical process , By Felder & Rousseau Investment Analysis and Portfolio Management , By Reilly and Brown , 7th ed Investments Analysis and Management , By Charles P. Jones , 11th ed IP Telephony Solution guide IT Networking Labs by Tom Cavaiani Java How to Program, 5th Edition By Harvey M. Deitel, Paul J. Deitel Java Programming 10-Minute , By Mark Watson , 1st ed Journey into Mathematics An Introduction to Proofs (Book and solution manua= l) by Joseph J. Rotman KC's Problems and Solutions for Microelectronic Circuits, Fourth Edition by= Adel S. Sedra, K. C. Smith, Kenneth C. Smith Labview for engineers 1st edition by R.W. Larsen Linear Algebra and Its Applications by David C. Lay Linear Algebra by Otto Bretscher Linear Algebra with Applications 6th edition by Leon Linear circuit analysis 2nd edition by R. A. DeCarlo and P. Lin Linear circuit analysis Time Domain. phasor. and laplace transform approach= es , By DeCarlo and Pen-Min-Lin , 2nd ed Linear dynamic systems and signals by Zoran Gajic with matlab experiments a= nd power point slides Linear Systems And Signals 1st edition by B P Lathi Logic and Computer Design Fundamentals 3rd Edition by Morris Mano & Charles= Kime Solutions Logic and Computer Design Fundamentals 4th Edition by Morris Mano Logic Computer Desing Fundamentals , Mano and Kime , 2nd ed machine design an integrated approach , Robert L. Norton , 3rd ed Machine Elements , By Bernard Hamrock , 1st ed Macroeconomics -N.G. Mankiw , 5th ed Managerial Accounting , By Hansen and Mowen , 8th ed managerial Accounting , Garrison and Noreen and Brewer , 11th ed managerial Accounting , Garrison and Noreen and Brewer , 13th ed Managerial Accounting 11th edition by Eric W. Noreen, Peter C. Brewer, Ray = H. Garrison Manufacturing Engineering and Technology , By Serope Kalpakjian and Steven = Schmid , 5th ed Matem?ticas para Administraci?n y Econom?a ( Mathematics for Administration= and Economics ) , By Ernest Haeussler, Richard Paul , 12th ed Materials and Processes in Manufacturing 9th edition by E. Paul DeGarmo, So= lutions Manual by Barney E. Klamecki Materials Science and Engineering 6th edition by Callister Materials Science and Engineering 7th edition by Callister materials science and engineering an introduction By William D. Callister ,= 6th ed materials science and engineering an introduction By William D. Callister ,= 7th ed Materials Science by Milton Ohring Mathematical Methods for Physicists Answers to Miscellaneous Problems , By = George B. Arfken , 5th ed Mathematical Methods for Physicists Answers to Miscellaneous Problems , By = George B. Arfken , 7th ed Mathematical Methods for Physics and Engineering 3rd Edition by K. F. Riley= , M. P. Hobson Mathematical Methods in the Physical Sciences , 3rd ed , By Mary L. Boas Mathematical Models in Biology An Introduction by Elizabeth S. Allman, John= A. Rhodes Mathematical Olympiad in China Problems and Solutions Mathematical Proofs A Transition to Advanced Mathematics. 2nd Ed By Gary Ch= artrand, Albert D. Polimeni, Ping Zhang Mathematical Statistics with Applications , Dennis Wackerly , 7th ed Mathematical Techniques ,Dominic Jordan and Peter Smith ,4th ed Mathematics for Administration and Economics , By Ernest Haeussler, Richard= Paul , 12th ed Mathematics for Economists by Carl P. Simon Lawrence Blume mathematics for physicists , By Susan Lea , 1st ed Mathematics for Physicists , Lea , 2nd ed Maths for Chemistry ,Paul Monk and Lindsey J. Munro ,2nd ed Maths for Science ,Sally Jordan, Shelagh Ross, and Pat Murphy ,2012 MATLAB Programming for Engineers by tephen J. Chapman, Cengage Learning ( m= files) Matrix Analysis and Applied Linear Algebra By Carl D. Meyer [Book and solut= ion manual] Mechanical Behavior of Materials , By Norman E. Dowling , 3rd ed Mechanical Design of Machine Elements and Machines 1st Edition by Collins Mechanical Engineering Design 7th Edition by Shigley Mechanical Engineering Design 8th edition by Shigley Mechanical Engineering Desing , Shigley , 7th ed Mechanical Vibrations , By Singiresu S. Rao , 5th ed Mechanical Vibrations , Singiresu Rao , 3th ed Mechanical Vibrations , Singiresu Rao , 4th ed Mechanical Vibrations 3rd edition by Singiresu Rao Mechanics for engineers dynamics , By russell C. Hibbeler , 13th ed Mechanics of Fluids , By Victor Streeter , 9th ed mechanics of fluids , by Irving H. Shames , 4th ed Mechanics of Fluids 5th Edition by Frank White Mechanics of Fluids 8th edition by Massey Mechanics of Materials , an integrated learning , Timothy A. Philpot , 2nd = ed mechanics of materials , By Beer and Johnston and Dewolf , 3rd ed mechanics of materials , By ferdinand P. Beer & E. Russell & Dewolf , 4th e= d mechanics of materials , By ferdinand P. Beer & E. Russell & Dewolf , 5th e= d mechanics of materials , By ferdinand P. Beer & E. Russell & Dewolf , 6th e= d mechanics of materials , By Hibbeler , 5th ed Mechanics of Materials , By Hibbeler , 8th ed Mechanics of Materials , By James Gere and Barry Goodno , 7th ed Mechanics of Materials , By James M. Gere & Stephen Timoshenko , 5th ed Mechanics of Materials , By R. C. Hibbeler , 4th ed Mechanics of Materials , By R. C. Hibbeler , 9th ed mechanics of materials , By Riley & Sturges , 6th ed Mechanics of Materials 3rd Edition by Beer Mechanics of Materials 4th edition By Hibbeler Chapter 12 mechanics of materials 6th edition by James Gere Mechanics of Materials 6th edition by R. C. Hibbeler Mechanics of Materials 7th edition by R. C. Hibbeler mechanics of materials james gere 5th edition mechanics of solids , by Carl T. F. Ross , 1st ed Microcomputers Systems Real Time Interfacing , By Jonathan W. Valvano , 2nd= ed Microelectronic Circuit Design , By Richard C. Jaeger and Travis N. Blalock= , 4rd ed Microelectronic Circuit Design 2nd Ed. - Richard C. Jaeger and Travis N. Bl= alock Microelectronic Circuit Design 3rd Ed. - Richard C. Jaeger and Travis N. Bl= alock Microelectronic Circuit Design 3rd edition by R. Jaeger Microelectronic Circuits , By Adel S. Sedra, Kenneth C. Smith , 7th ed Microelectronic circuits 5th edition by Adel S. Sedra kennethSmith Microelectronic Circuits and Devices , Mark N. Horenstein , 2nd ed Microelectronic Circuuits , By Sedra and smith , 4th ed Microelectronics 1 & 2 by Dr. Wen Ching Chang Microelectronics Circuit Analysis and Design , Donald A. Neamen , 3th ed Microelectronics Circuit Analysis and Design , Donald A. Neamen , 4th ed Microprocessors and Interfacing-Programming and Hardware 2nd Edition by Dou= glas V. Hall Microwave and RF design of wireless systems by Pozar Microwave Engineering 2nd edition by David M Pozar Microwave Engineering 3rd Ed. by David M Pozar Microwave transistor amplifiers analysis and design 2nd edition by Guillerm= o Gonzalez Millman - Microelectronics digital and analog circuits and systems by Thoma= s V. Papathomas Mobile Communications 2nd Ed. by Jochen H. Schiller Modeling and Analysis of Dynamic Systems , By C. Close, D. Frederick, J. Ne= well , 3rd ed modern control engineering , By Katsuhiko Ogata , 4th ed modern control engineering , By Katsuhiko Ogata , 5th ed Modern Control Engineering 3rd edition by K. OGATA Modern Control Systems 11th edition by Richard C. Dorf Robert H Bishop Modern Control Systems, 12th Edition By Richard C. Dorf, Robert H. Bishop Modern Digital and Analog Communications Systems 3rd edition by B P Lathi Modern Digital Signal Processing by Roberto Cristi Modern physics , By Forsci , 2nd ed Modern Physics , By Serway , 3rd ed Modern physics , By thornton and rex , 3rd ed Modern physics By Randy Harris Molecular Quantum Mechanics ,Peter W. Atkins and Ronald S. Friedman ,5th ed Multivariable Calculus , by Dan clegg & Barbara Frank & James Stewart , 6th= ed Multivariable Calculus , Dan Clegg & Barbara Frank , 5th ed Multivariable Calculus 4th edition by Stewart Dan Clegg Barbara Frank Musculoskeletal Function An Anatomy and Kinesiology Laboratory Manual by Do= rtha Esch Esch Nanoengineering of Structural, Functional and Smart Materials Network Flows Theory, Algorithms, And Applications by Ravindra K. Ahuja, Th= omas L. Magnanti, and James B. Orlin Network Simulation Experiments Manual (The Morgan Kaufmann Series in Networ= king) by Emad Aboelela networks flows theory algorithms and applications , By Ahuja and Magnant a= nd Orlin , 1st ed Neural networks and learning machines 3rd edition by Simon S. Haykin NMR The Toolkit (How Pulse Sequences Work) ,Peter Hore, Jonathan Jones, and= Stephen Wimperis ,2nd ed Nonlinear Programming 2nd Edition by Dimitri P. Bertsekas Nuclear Magnetic Resonance ,Peter Hore ,2nd ed Numerical Analysis 8th ed. By Richard L. Burden, J Douglas Faires Numerical Methods for Engineers , By Chapra and canale , 5th ed Numerical Methods for Engineers , by Steven C. Chapra & Raymond P.Canale , = 6th ed Numerical Methods For Engineers 4th edition by Chapra Numerical Solution of Partial Differential Equations An Introduction by K. = W. Morton, D. F. Mayers Operating Systems 4th Edition by Stallings operations research , By Hamdy A. Taha , 9th ed Optimal Control Theory An Introduction By Donald E. Kirk Optimization of chemical processes by Edgar himmelblau Options, Futures and Other Derivatives 5th Edition by John Hull, John C. Hu= ll Options, Futures and Other Derivatives, 4th Edition by John Hull, John C. H= ull Organic Chemistry , 6th Ed (2006) , L.G. Wade Organic Chemistry , By John McMurry , 8th ed Organic Chemistry , By Jonathan Clayden , Nick Greeves , Stuart Warren and = Peter Wothers , 1st ed Organic Chemistry , By Paula Yurkanis , 5th ed Organic Chemistry , David Klein , 1st ed Organic Chemistry ,Cook & Cranwell Organic Chemistry ,Tadashi Okuyama and Howard Maskill ,2013 Organic chemistry 4th edition by Robert C. Athkins and Francis Carey Organic chemistry 5th edition by Robert C. Athkins and Francis Carey Organic Chemistry 7th Edition by Susan McMurry Organic Chemistry 8th ed. , L.Wade , J. Simek Partial Differential Equations With Fourier Series And Boundary Value Probl= ems 2nd Edition By Nakhle H.Asmar partical differential equations , NAKHL=C2=B4E H.ASMAR , 2nd ed Physical Chemistry , By Peter Atkins & Julio de Paula , 7th ed physical chemistry , peter Atkins , 9th ed Physical Chemistry ,Elliott & Page Physical Chemistry ,Quanta, Matter, and Change ,Peter Atkins, Julio de Paul= a, and Ronald Friedman ,2nd ed Physical Chemistry 7th edition by Peter Atkins and Julio de Paula Physical Chemistry 8th edition by Peter Atkins and Julio de Paula Physical Chemistry by Prem Dhawan Physics , Cutnell & Johnson , 9th ed physics , James s.Walker , 2nd ed Physics 5th Edition by Halliday , Resnick , Krane Physics for Engineering and Science , By Hans Ohanian , 3rd ed Physics for Science and Engineering , By Raymond A. Serway , 6th ed Physics for Science and Engineering , By Raymond A. Serway , 7th ed Physics for Science and Tecnology , By Paul A. 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Duncan, Sarma Mu= lkutla .S Precalculus Essentials , Michael Sullivan , 7th Edition principles and applications of electrical engineering , By Giorgio Rizzoni = , 1st ed or 3rd ed Principles and Applications of Electrical Engineering 2nd Ed. by Giorgio Ri= zzoni Principles and Applications of Electrical Engineering 4th edition by Giorgi= o Rizzoni Principles and Practices of Automatic Process Control , By Smith & corripio= , 3rd ed Principles Heat Transfer , By Frank kreith & Raj M. Manglik & Mark S. bohn = , 7th ed Principles of Communications Systems, Modulation and Noise 5th Edition by W= illiam H. Tranter and Rodger E. Ziemer Principles of Computer Hardware ,Alan Clements ,4th ed Principles of Corporate Finance , Brealey , 7ed Principles of Digital Communication and Coding 1st edition by Andrew J. Vit= erbi and Jim K. Omura principles of electrical engineering materials and devices , By S.O. Kasap = , 2nd ed Principles of Electronic Materials and Devices 3rd edition By Safa O. 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R= appaport X-Ray Crystallography ,William Clegg ,2nd ed Zill's a First Course in Differential Equations with Modeling Applications = (7th ed.) and Zill & Cullen's Diferential Equations with Boundary-Value Pro= blems (5th ed.) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=20 If your request isn't in the list , we will find it for you, just=20 contact us=20 s o l u t i o n s b o o k t e a m @ h o t m a i l . c o m solutionsbookteam(at)hotmail(dot)com=20 From newsfish@newsfish Thu Aug 1 00:43:49 2024 X-Received: by 2002:ac8:6655:: with SMTP id j21-v6mr4400084qtp.11.1533319356945; Fri, 03 Aug 2018 11:02:36 -0700 (PDT) X-Received: by 2002:a81:a611:: with SMTP id d17-v6mr174547ywh.2.1533319356539; Fri, 03 Aug 2018 11:02:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.fr7!futter-mich.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!e8-v6no777475qtp.0!news-out.google.com!e6-v6ni275qte.1!nntp.google.com!e8-v6no777471qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Aug 2018 11:02:36 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.199.99.114; posting-account=bHOQ0woAAAC4tFmIPjvxVw_RjmNs2ETy NNTP-Posting-Host: 128.199.99.114 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <49dbe75c-df76-40eb-863e-4206654d6fac@googlegroups.com> Subject: Electric Circuits 8th edition by Nilsson From: solutionsmanualteam@gmail.com Injection-Date: Fri, 03 Aug 2018 18:02:36 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 59115 X-Received-Body-CRC: 3309706689 Xref: reader02.eternal-september.org comp.lang.vhdl:9350 Lines: 1109 solutions book team=20 s o l u t i o n s b o o k t e a m @ h o t m a i l . c o m solutionsbookteam(at)hotmail(dot)com=20 solutionsbookteam@hotmail.com We're a team for providing solution manuals to help students in their=20 study.=20 We sell the books in a soft copy, PDF format.=20 We will find any book or solution manual for you.=20 Just email us:=20 s o l u t i o n s b o o k t e a m @ h o t m a i l . c o m List of some books we have=20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=20 A Course in Modern Mathematical Physics by Peter Szekeres A First Course in Abstract Algebra By John B. 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Levi Applied Statistics And Probability For Engineers , 2nd ed , By Montgomery, = Runger Applied Statistics And Probability For Engineers 3rd edition By Montgomery,= Runger Applied Statistics And Probability For Engineers 4th edition By Montgomery,= Runger Applied Strength of Materials 4th Edition By Robert L. Mott Artificial Intelligence A Modern Approach , By Russell and Norvig , 2nd ed Artificial Intelligence A Modern Approach , By S. Russell, P. Norvig , 3rd = ed Artificial Intelligence A ModernApproach 2nd edition by StuartJ. Russelland= , Peter Norvig Assembly Language for Intel-Based Computers,3ed, by Kip R. Irvine Astronomy Today , McMillan & Chaisson , 5th ed Atkins' Physical Chemistry ,Peter Atkins and Julio de Paula ,10th ed Auditing & assurance services , By Louwers & Sinason & Straeser & Ramsy , 2= nd ed Auditing and Assurance Services , By Arens. Elder and Beasley and Randal J.= Elder , 13th ed Automatic control systems , By Benjamin C. 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Marion Classical Electrodynamics , By John David Jackson , 3rd ed Classical Electrodynamics 2nd Edition by John David Jackson by Kasper van W= ijk Classical Mechanics - An Undergraduate Text by R. Douglas Gregory Classical Mechanics 2nd edition By Goldstein & Safko classical thermodynamics of Non-Electrolyte , By H. C. Van ness 1st ed CMOS Digital Integrated Circuits 3rd edition By Sung-Mo Kang,Yusuf Leblebic= i CMOS VLSI Design 3e by ananymous College Physics , By Faughn and Serway and vuille , 6th ed COLLEGE PHYSICS , by SERWAY AND VUILLE=E2=80=99S , 9th ed Communication Networks Fundamental Concepts and Key Architectures Alberto L= eon-Garcia Communication Systems 4th ed by bruce carlson Communication Systems 4th edition by Simon Haykin Communication Systems Engineering - Second Edition John G. Proakis Masoud S= alehi Complex Variables and Applications , JW Brown , RV Churchill , 8th ed(2009) complex Variables and applications ,James Ward Brown ,7th ed complex variables with applications ,A. David wunsch ,3th ed Computational Techniques for Fluid Dynamics (Scientific Computation) by Kar= kenahalli Srinivas, Clive A. J. Fletcher Computer Networking A Top-Down Approach 3rd Edition by James F.Kurose,Keith= W. Ross Computer Networks - 4th Edition by Andrew S. Tanenbaum Computer Organization 5th edition by Hamacher,Vranesic and Zaky Computer Organization and Design The HardwareSoftware Interface, 3rd editio= n by David A. Patterson, John L. Hennessy, Computer-Controlled Systems 3rd edition by Karl J. Astrom Comunicacion Satelital , Timothy Pratt & Charles Bostian , 2nd ed concepts and applications of finite element analysis , Robert Cook and Davi= d s. Malkus and Michael E. Plesha , 4th ed Concepts of Programming Languages 7th edition Solutions Manual by Robert Se= besta Contemporary Engineering Economics , By Chan S. Park , 4t ed Contemporary Engineering Economy , By William G. Sullivan and Elin M. Wicks= and C. Patrick Koelling , 5th ed Contemporary Linear Algebra , Howard Anton and Robert C. Busby , 1st ed Control systems Principles and Design 2nd Edition by Madan Gopal Control systems engineering , By Norman Nise , 6th ed Control Systems Engineering 4th edition by Norman S. Nise Convection Heat Transfer ,By Adrian Bejan , 3rd ed Corporate Finance solution manual 6th Edition by Ross Cost Accounting , By Horngren , 12th ed Cost Accounting , By Horngren , 13th ed Cost Accounting , By William K. Carter , 14th ed Craig's Soil Mechanics 7th Edition Cryptography and network security-principles and practice 4th ed. By Willia= m Stallings Data and computer communications 7th edition William Stallings Data Communications and Networking 4th edition by Behroz Forouzan Database Management Systems 3rd edition Raghu Ramakrishnan Johannes Gehrke Database System Concepts , A. Silberschatz and H. Korth and S. Sudarshan , = 4th ed Design of Analog CMOS Integrated Circuits Behzad Razavi Design of Concrete Structures , By Arthur H. Nilson , 14th ed Design of Nonlinear Control Systems with the Highest Derivative in Feedback= 1st Edition by Valery D. Yurkevich [student solution manual] Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edit= ion by Franco, Sergio Device Electronics for Integrated Circuits 3rd edition by Muller Kamins Differential Equation , by Richard Bronson 3rd ed Differential Equations and Boundary Value Problems , Edwards & & Penney = , 2nd ed differential equations and boundary value problems computing and modeling ,= By Edwards and Penney , 4th ed differential equations and linear algebra , Jerry Farlow & Beverly H. West = & james-e-hall & jean-marie-mcdill , 2nd ed Differential Equations with Boundary Value Problems 2nd Edition by JOHNPOLK= ING and DAVID ARNOLD Differential Equations with Boundary Value Problems, 2nd edition by John Po= lking Digital and Analog Communication Systems 7th Edition by Leon W. Couch Digital Communication 4th edition by Proakis Digital Communications 5th edition by John Proakis Digital Communications Fundamentals and Applications, 2nd Edition by Bernar= d sklar Digital Control and state variable methods - M.Gopal Digital Design 2nd Edition by M. Morris Mano,Michael D. Ciletti Digital Design 3rd Edition by M. Morris Mano,Michael D. Ciletti Digital Design 4th edition Morris Mano Digital Design-Principles and Practices 3rd Edition by John F. Wakerly [sel= ected problems] Digital Fundamentals 9th edition by Thomas L. Floyd Digital Image Processing 2nd edition by Rafael C. Gonzalez Digital Integrated Circuits 2nd edition by Rabaey Digital Integrated Circuits by Thomas A. DeMassa & Zack Ciccone Digital Logic Design 2nd edition by M. Morris Mano Digital Signal Processing - A Modern Introduction, 1st Edition Cengage lear= ning Ashok Ambardar Digital Signal Processing , Proakis and Manolakis , 1st ed Digital Signal Processing ; A Computer-Based Approach 1st edition By sanji= t K. Mitra Digital Signal Processing 2nd Edition by Mitra Digital Signal Processing 3nd Edition by Mitra Digital Signal Processing 4th edition by John G. Proakis and Dimitri s G. M= anolakis Digital Signal processing Acomputer - based Approach , By Sanjit K. Mitra Digital Signal Processing by Thomas J. Cavicchi Digital signal processing proakis manolakis Digital Signal Processing Signals, Systems, and Filters Andreas Antoniou Digital Signal Processing Using Matlab 2nd edition by Vinay K Ingle Proakis Digital Systems-Principles and Applications 10th Ed. by Ronald Tocci, Neal = S. Widmer & Gregory L. Moss Discretas mathematics , By Richard Johnsonbaugh , 6th ed Discrete and Combinatorial Mathematics , By R. Grimaldi , 5ed Part 1 Discrete Mathematics with Applications Third Edition By Susanna S. Epp discrete Time control systems (Sistemas de control en tiempo discreto) , 2n= d ed , Katsuhiko ogata Discrete Time Signal Processing 2nd Edition, by Alan V. Oppenheim Discrete time signal processing 3rd edition by Oppenheim Dise?o con Amplificadores Operacionales y Circuitos Integrados Anal?gicos(D= esign with Operational Amplifiers and Analog Integrated Circuits) , By Serg= io Franco , 3th ed Dynamics of Mechanical Systems , By Carl T. F. Ross , 7th ed Dynamics Structures theory and applications to earthquake engineering , By = Anil K. Chopra , 3th ed Econometric Analysis 5th Edition by William H. Greene Economic engineering , L. Blank and A. Tarkin , 6th ed Electric Circuits 7th edition by Nilsson Electric Circuits 8th edition by Nilsson Electric Machinery 6th Edition by Fitzgerald Kingsley Electric Machinery and Power System Fundamentals 1st edition by Stephen Cha= pman Electric Machinery Fundamentals 4th edition by Stephen J. Chapman Electric machines , By Jesus Fraile Mora , 5th ed Electric Machines Analysis and Design Applying MATLAB by Jim Cathey Electrical Engineering Principles and Applications 3rd edition by Allan R. = Hambley Electrical Machines, Drives and Power Systems 6th edition By Theodore Wildi Electrical Properties of Materials ,Solymar & Walsh , 7th ed Electricity and magnetism (Electricidad y Magnetismo) , By Raymond A. Serwa= y , 6th ed Electricity and magnetism , By Raymond A. Serway , 3rd ed electricity and magnetism Vol.II , Edward M. Purcell , 2nd ed Electromagnetic Fields and Energy 1st Ed. by Haus and Melcher Electromagnetics for Engineers by Ulaby Electromagnetism Major American Universities Ph.D. Qualifying Questions and= Solutions by Lim Yung-Kuo Electron Paramagnetic Resonance ,Victor Chechik, Emma Carter, and Damien Mu= rphy ,2016 Electronic Circuit Analysis and Design 2nd edition by Donald A. Neamen Electronic devices - electron flow version 4th edition by thomas l.floyd Electronic Devices and Circuit Theory 8th Ed. with Lab Solutions, and Test= Item File by Robert Boylestad Electronic Devices and electronic devices , By thomas L. Floyd , 6th ed Electronic Devices-6th Edition by Thomas L. Floyd Electronic Physics by Strabman Elementary Applied Partial Differential Equations with Fourier Series and B= oundary Value Problems , PrenticeHall , R.Haberman (1987) Elementary Differential Equations , 8th ed. , By Werner Kohler, Lee Johnson Elementary Differential Equations , Penny , 5th ed Elementary Differential Equations , Werner Kohler & Lee Johnson , 1st ed Elementary Differential Equations 8th edition by Boyce Elementary Differential Equations And Boundary Value Problems, 7Th Edition = by Boyce And Diprima Elementary Differential Equations and Elementary Differential Equations wit= h Boundary Value Problems , William F. Trench , 2000 Elementary Linear Algebra with Applications 9th by Howard Anton, Chris Rorr= es Elementary Linear Algebra With Applications 10E , Howard Anton, Chris Rorre= s Elementary Mechanics and Thermodynamics by Jhon W. Norbury , 1st ed Elementary Number Theory and Its Applications, 5th edition by Kenneth H. Ro= sen Elementary Number Theory and Its Applications, 6th Ed. By Kenneth H. Rosen Elementary Principles of Chemical Processes 3rd edition by Richard M. Felde= r,Ronald W. Rousseau Elementary statistics Using the Graphing Calculator , Mario F. Triola 2005 Elements of Chemical Reaction Engineering, 3rd Edition by H. Scott Fogler Elements of Deductive Inference , By Joseph Bessie and Stuart Glennan , 1st= ed Elements of electromagnetics 2nd edition by sadiku Elements of electromagnetics 3rd edition by sadiku Elements of Power System Analysis 4th edition by William D. Stevenson Embedded Microcomputer Systems Real Time Interfacing 2nd Edition by Jonatha= n W. Valvano Energy Science ,Principles, Technologies, and Impacts ,Andrews & Jelley ,3t= h e Energy Systems Engineering evaluation and implementation , Francis M Vanek = and Louis D Albright , 1st ed Engineering Circuit Analysis 6th edition by Hayt Engineering Circuit Analysis 7th edition by Hayt Engineering Electromagnetics - 7th Ed. - Hayt Engineering Electromagnetics 2d Edition by Nathan Ida Engineering Electromagnetics 6th Edition by William H. Hayt Jr. and Hohn A.= Buck Engineering Fluid Mechanics 7th edition by Clayton T. Crowe, Donald F. Elge= r & John A. Roberson engineering materials science , By milton ohring , 1st ed Engineering Mathematics 4th edition by John Bird Engineering Mathematics 4th Edition by NEWNES Engineering Mechanic STATICS 10th Ed. R.C. Hibbeler Engineering Mechanics - Dynamics 2 Edition by Riley and Sturges Engineering Mechanics - Dynamics 11th edition by R. C. Hibbeler Engineering Mechanics - STATICS 4th E - Bedford and Fowler Engineering mechanics - statics 10th edition by R. C. Hibbeler engineering mechanics dynamics , By Boresi and schmidt , 1st ed engineering mechanics Dynamics , By Meriam & Kraige & palm , 3rd ed engineering mechanics Dynamics , By Meriam & Kraige & palm , 5rd ed engineering mechanics dynamics , By Meriam and kraige , 6th ed Engineering mechanics Dynamics 4th Ed. by Bedford and Fowler Engineering Mechanics Dynamics 5th J.L Meriam Engineering Mechanics of Solids , By Egor P. Popov , 2nd ed engineering mechanics statics , By Bedford and fowler , 5th ed engineering mechanics statics , By R. C. Hibbeler , 8th ed engineering mechanics statics , By R. C. Hibbeler , 10th ed Engineering Mechanics Statics , By R.C.Hibbeler , 12th ed Engineering Mechanics Statics 6th edition by J.L Meriam Engineering Mechanics Statics 11th Edition By R.C.Hibbeler engineering mechanics statistics , By Meriam & Kraige & palm , 4th ed engineering mechanics statistics , By Meriam & Kraige & palm , 6th ed Engineering Probability and Statistics for Engineers and Scientists Engineering Statistics , By Montgomery , 4th ed Engineering Vibration , 3rd ed , Daniel J. Inman English Grammar Understanding the Basics , By Cambridge , 1st ed Environmental Chemistry , vanLoon & Duffy , 3th ed Experiments with Economic Principles , By Theodore Bergstrom And J. Miller = , 1st ed Feedback Control of Dynamic Systems 4th edition by G. F. Franklin, J. D. Po= well, A. Emami Field and Wave Electromagnetics 2nd Edition by Wesley Cheng Field and Wave Electromagnetics International Edition by David K Financial Accounting , By Harrison and Horngren , 8th ed Financial Accounting information for decisions , John J. Wild , 4th ed Financial Instruments , John Hull , 4ed FINITE MATHEMATICS , Lial , Greenwell & Ritchey , 8th ed Fluid Mechanics , By Frank M. White , 5th ed Fluid mechanics , By Merle C. Potter and David C. Wiggert , 3rd ed Fluid Mechanics , By Russell C. Hibbeler , 1st ed Fluid Mechanics , Munson , 7th ed Fluid Mechanics 1st edition by CENGEL Fluid Mechanics 5th Edition by White Fluid Mechanics and Thermodynamics of Turbomachinery , By Dixon and Hall , = 5th ed Fluid Mechanics Fundamentals and Applications , By Cengel and Cimbala , 1st= ed Fluid Mechanics With Engineering Applications 10th edition by E. John Finne= more, Joseph B Franzini Foundations of Colloid Science ,Hunter ,2nd ed Foundations of International Macroeconomics , By Obstfeld and Rogoff , 1st = ed Foundations of Molecular Structure Determination ,Simon Duckett, Bruce Gilb= ert, and Martin Cockett ,2nd ed Fracture mechanics fundamentals and applications 2nd edition by Northam And= erson Fund of Corporate Finance , by Richard A. Brealey , 4th ed Fundamental of Electric Circuits 3rd editoin by C. K. Alexander M. N. O. Sa= diku Fundamental of engineering electromagnetics by David Cheng Fundamentals od Finanial Management , James Van Horne and John Wachowicz , = 12th ed Fundamentals of Aerodynamics , By John D. Anderson , 3rd ed Fundamentals of Analytical Chemistry , By Holler and Crouch , 9th ed Fundamentals of Applied Electromagnetics , By Faeeaz T. Ulaby Fundamentals of corporate finance , By Ross and Jordan and Westerfield , 8t= h ed Fundamentals of Diferential Equations , By Nagle and Saff and Snider , 6th = ed Fundamentals of differential equations , 7ed.-Pearson (2008) , By R. Kent N= agle , Edward B. Saff , A. David Snider Fundamentals of differntial equations , R. kent nagle & Edward b.saff & A. = David snider , 7th ed Fundamentals of Digital Logic with VDL Desing , By S. Brown and Z. Vranesic= , 1st ed Fundamentals of Digital Logic with Verilog Design 1st edition by S. Brown Z= . Vranesic Fundamentals of Digital Logic with VHDL Design, 1st edt. by S. Brown, Z. Vr= anesic Fundamentals of Digital Signal Processing using MATLAB , By Sandra L. Harri= s and Robert J. Schilling , 2nd Ed Fundamentals of Electric Circuits , 5th ed fundamentals of electric circuits , By Alexander and Sadiku , 4th ed Fundamentals of Electric Circuits 2nd edition by C. K. Alexander M. N. O. S= adiku Fundamentals of Electric Circuits, 3rd edition by C. K. Alexander M. N. O. = Sadiku fundamentals of engineering thermodynamics , By Moran & Shapiro , 5th ed fundamentals of engineering thermodynamics , By Moran & Shapiro , 6th ed Fundamentals of engineering thermodynamics by m. j. moran h. n. shapiro Fundamentals of Financial Management , and E. Brigham, J. Houston , 12th ed Fundamentals of Fluid mechanics 4th edition by Munson Fundamentals of Fluid Mechanics Student Solutions Manual, 3rd Edition [Stud= ent solution manual] Fundamentals of heat and mass transfer , By Incropera & Lavine & Dewitt & B= ergman , 5th ed Fundamentals of heat and mass transfer , By Incropera & Lavine & Dewitt & B= ergman , 6th ed Fundamentals of Heat and Mass Transfer 4th edition by Incropera & Dewitt Fundamentals of logic design 5th edition by Charles Roth Fundamentals of Machine Component Design - 3rd edition by Robert C. Juvinal= l and Kurt M. Marshek Fundamentals of Machine Component Design 4th edition by Robert C. Juvinall,= Kurt M. Marshek Fundamentals of Machine Component Desing , By R. Juvinall. K. Marshek , 1st Fundamentals of Machine Elements , By Steven Schmid and Bernard Hamrock and= Bo. Jacobson , 2nd ed fundamentals of manufacturing , By philip D. Rufe , 2nd ed FUNDAMENTALS OF MODERN MANUFACTURING , (MATERIALS, PROCESSES, AND SYSTEMS) = , By MIKELL P. GROOVER , 2nd ed FUNDAMENTALS OF MODERN MANUFACTURING , (MATERIALS, PROCESSES, AND SYSTEMS) = , By MIKELL P. GROOVER , 3rd ed FUNDAMENTALS OF MODERN MANUFACTURING , (MATERIALS, PROCESSES, AND SYSTEMS) = , By MIKELL P. GROOVER , 4th ed Fundamentals of Momentum, Heat, and Mass Transfer , By Welty and Wicks and = Wilson and Rorrer , 5th ed Fundamentals of Organic Chemistry , By Solomon , 5th ed Fundamentals of Physics (Extended) , by Halliday , Resnick & J. Walker , 9t= h ed , pp.1643, (Wiley, 2011) Fundamentals of Physics 7th edition by Halliday, Resnick and Walker Fundamentals of physics 8th edition by Halliday, Resnick and Walker Fundamentals of Physics Extended , By Halliday and Resnick , 8th ed fundamentals of physics Vol.1 vol.2 , By Halliday and Resnick , 6th ed Fundamentals of Power Electronics 2nd edition by R.W. Erickson Fundamentals of Power Semiconductor Devices 1st Ed. by B. Jayant Baliga Fundamentals of Quantum Mechanics for solid state electronics and optics , = By C.L. Tang , 1st ed Fundamentals of signals and systems , By Michael J. Roberts . 1st ed Fundamentals of Signals and systems using web and matlab third edition by E= dward W. Kamen, Bonnie S Heck Fundamentals of Solid-State Electronics by Chih-Tang Sah Fundamentals of Thermal Fluid Sciences by Yunus A. Cengel, Robert H. Turner= , Yunus Cengel, Robert Turner Fundamentals of Thermodynamics by Richard Sonntag Claus Borgnakke Gordon Va= n Wylen Fundamentals of Wireless Communication by Tse and Viswanath General Chemistry , By Ebbing and Gammon , 10th ed General Chemistry, Principles and Modern Applications , By Petrucci and Har= wood and Herring , 8th ed general organic and biological chemist structures of life , By Karen C. Tim= berlake , 2nd ed Guide for Microprocessors and Interfacing , By Douglas Hail , 2nd ed Heat and Mass transfer A practical Approach , Yunus A. Cengel , 3rd ed Heat Transfer A Practical Approach 2nd edition by Yunus A. Cengel, Yunus Ce= ngel How English Works A Grammar Handbook with Readings Instructor's Manual by A= nn Raimes Hydraulics in Civil and Environmental Engineering , 4th ed , by Chadwick & = Morfett Heating ventilating and air conditioning Analysis and Design , By McQuiston= and Parker and Spitler , 6th ed Inorganic Chemistry ,Almond, Spillman & Page Interfacial Science An Introduction ,Geoffrey Barnes and Ian Gentle ,2nd ed Intermediate Accounting , By Kieso , 13th ed International Trade , By Robert Feenstra and Alan Taylor , 2nd ed Introduction to Abstract Algebra, Solutions Manual , By W. Keith Nicholson = , 4th ed , 2012 Introduction to Algorithms 2nd edition by Philip Bille Introduction to Algorithms 2nd Edition by Thomas H. Cormen INTRODUCTION TO chemical engineering thermodynamics , By J.R. Elliot and C.= T. Lira , 1st ed INTRODUCTION TO chemical engineering thermodynamics , Smith & Van Ness , 7t= h ed Introduction to chemical engineering thermodynamics 6th edition by j. m. sm= ith Introduction to Communication Systems , 2nd ed , By Ferrel G. Stremler Introduction to Communication Systems 3rd Edition by Stremler Introduction to Computing and Programming with JAVA-A Multimedia Approach 1= st Edition by Mark Guzdial and Barbara Ericson Introduction to Econometrics , By Stock and Watson , 1st ed Introduction to electric circuits 6th edition by Dorf Svaboda Introduction to Electric Circuits 7th edition by Richard C. Dorf & James A.= Svoboda Introduction to elementary particles by D.Griffiths Introduction to Eletrodynamics 3rd ed By David J. Griffiths Introduction to Environmental Engineering and Science 3rd Edition Introduction to Ergonomics By Robert Bridger introduction to fluid mechanics , by Fox and McDonald , 7th ed introduction to fluid mechanics , By Munson and young and Huebsch , 5th ed Introduction to fluid mechanics 5th edition by fox and mcdonald Introduction to fluid mechanics 6th edition by fox and mcdonald Introduction To Fourier Optics , Joseph W. Goodman , 3th ed , 2005 INTRODUCTION TO GRAPH THEORY , Douglas B. West , 2nd ed Introduction to Java Programming 7th edition by Y. Daniel Liang Introduction to Linear Algebra 3rd Edition By Gilbert Strang Introduction to Linear Programming 1st Edition by L. N. Vaserstein [student= solution manual] Introduction to Management Accounting , By Charles T. Horngren and Gary L. = Sundem and William O. Stratton and David Burgstahler and Jeff Schatzberg , = 14th ed Introduction to Managerial Accounting , By Garrison and Noreen and Brewer ,= 5th ed Introduction to Probabilit , By Dimitri P. Bertsekas and John N. Tsitsiklis= , 1st ed Introduction to Probability and Statistics , By Barbara M. Beaver , 12th Ed Introduction to Probability Models , (10th Ed) , By Sheldon M. Ross Introduction to Quantum Mechanics (1995) by David J. Griffiths , 2nd=20 Introduction to Solid State Physics by Charles Kittel Introduction to Statics and Dynamics , By Ruina & Pratap , 1st ed Introduction to the Theory of Computation , By Michael Sipser , 1st ed Introduction to Thermal Systems Engineering , M. Moran. H. Shapiro , 1st ed Introduction to Thermodynamics and Heat Transfer , yunus A. cengel , 2nd e= d Introduction to VLSI Circuits and Systems John P Uyemura Introduction to Wireless Systems by P.M. Shankar Introductory Circuit Analysis , By Robert L. Boylestad , 11th ed Introductory Econometrics A Modern Approach , Jeffrey M. Wooldridge , 2ed introductory elements of the chemical process , By Felder & Rousseau Investment Analysis and Portfolio Management , By Reilly and Brown , 7th ed Investments Analysis and Management , By Charles P. Jones , 11th ed IP Telephony Solution guide IT Networking Labs by Tom Cavaiani Java How to Program, 5th Edition By Harvey M. Deitel, Paul J. Deitel Java Programming 10-Minute , By Mark Watson , 1st ed Journey into Mathematics An Introduction to Proofs (Book and solution manua= l) by Joseph J. Rotman KC's Problems and Solutions for Microelectronic Circuits, Fourth Edition by= Adel S. Sedra, K. C. Smith, Kenneth C. Smith Labview for engineers 1st edition by R.W. Larsen Linear Algebra and Its Applications by David C. Lay Linear Algebra by Otto Bretscher Linear Algebra with Applications 6th edition by Leon Linear circuit analysis 2nd edition by R. A. DeCarlo and P. Lin Linear circuit analysis Time Domain. phasor. and laplace transform approach= es , By DeCarlo and Pen-Min-Lin , 2nd ed Linear dynamic systems and signals by Zoran Gajic with matlab experiments a= nd power point slides Linear Systems And Signals 1st edition by B P Lathi Logic and Computer Design Fundamentals 3rd Edition by Morris Mano & Charles= Kime Solutions Logic and Computer Design Fundamentals 4th Edition by Morris Mano Logic Computer Desing Fundamentals , Mano and Kime , 2nd ed machine design an integrated approach , Robert L. Norton , 3rd ed Machine Elements , By Bernard Hamrock , 1st ed Macroeconomics -N.G. Mankiw , 5th ed Managerial Accounting , By Hansen and Mowen , 8th ed managerial Accounting , Garrison and Noreen and Brewer , 11th ed managerial Accounting , Garrison and Noreen and Brewer , 13th ed Managerial Accounting 11th edition by Eric W. Noreen, Peter C. Brewer, Ray = H. Garrison Manufacturing Engineering and Technology , By Serope Kalpakjian and Steven = Schmid , 5th ed Matem?ticas para Administraci?n y Econom?a ( Mathematics for Administration= and Economics ) , By Ernest Haeussler, Richard Paul , 12th ed Materials and Processes in Manufacturing 9th edition by E. Paul DeGarmo, So= lutions Manual by Barney E. Klamecki Materials Science and Engineering 6th edition by Callister Materials Science and Engineering 7th edition by Callister materials science and engineering an introduction By William D. Callister ,= 6th ed materials science and engineering an introduction By William D. Callister ,= 7th ed Materials Science by Milton Ohring Mathematical Methods for Physicists Answers to Miscellaneous Problems , By = George B. Arfken , 5th ed Mathematical Methods for Physicists Answers to Miscellaneous Problems , By = George B. Arfken , 7th ed Mathematical Methods for Physics and Engineering 3rd Edition by K. F. Riley= , M. P. Hobson Mathematical Methods in the Physical Sciences , 3rd ed , By Mary L. Boas Mathematical Models in Biology An Introduction by Elizabeth S. Allman, John= A. Rhodes Mathematical Olympiad in China Problems and Solutions Mathematical Proofs A Transition to Advanced Mathematics. 2nd Ed By Gary Ch= artrand, Albert D. Polimeni, Ping Zhang Mathematical Statistics with Applications , Dennis Wackerly , 7th ed Mathematical Techniques ,Dominic Jordan and Peter Smith ,4th ed Mathematics for Administration and Economics , By Ernest Haeussler, Richard= Paul , 12th ed Mathematics for Economists by Carl P. Simon Lawrence Blume mathematics for physicists , By Susan Lea , 1st ed Mathematics for Physicists , Lea , 2nd ed Maths for Chemistry ,Paul Monk and Lindsey J. Munro ,2nd ed Maths for Science ,Sally Jordan, Shelagh Ross, and Pat Murphy ,2012 MATLAB Programming for Engineers by tephen J. Chapman, Cengage Learning ( m= files) Matrix Analysis and Applied Linear Algebra By Carl D. Meyer [Book and solut= ion manual] Mechanical Behavior of Materials , By Norman E. Dowling , 3rd ed Mechanical Design of Machine Elements and Machines 1st Edition by Collins Mechanical Engineering Design 7th Edition by Shigley Mechanical Engineering Design 8th edition by Shigley Mechanical Engineering Desing , Shigley , 7th ed Mechanical Vibrations , By Singiresu S. Rao , 5th ed Mechanical Vibrations , Singiresu Rao , 3th ed Mechanical Vibrations , Singiresu Rao , 4th ed Mechanical Vibrations 3rd edition by Singiresu Rao Mechanics for engineers dynamics , By russell C. Hibbeler , 13th ed Mechanics of Fluids , By Victor Streeter , 9th ed mechanics of fluids , by Irving H. Shames , 4th ed Mechanics of Fluids 5th Edition by Frank White Mechanics of Fluids 8th edition by Massey Mechanics of Materials , an integrated learning , Timothy A. Philpot , 2nd = ed mechanics of materials , By Beer and Johnston and Dewolf , 3rd ed mechanics of materials , By ferdinand P. Beer & E. Russell & Dewolf , 4th e= d mechanics of materials , By ferdinand P. Beer & E. Russell & Dewolf , 5th e= d mechanics of materials , By ferdinand P. Beer & E. Russell & Dewolf , 6th e= d mechanics of materials , By Hibbeler , 5th ed Mechanics of Materials , By Hibbeler , 8th ed Mechanics of Materials , By James Gere and Barry Goodno , 7th ed Mechanics of Materials , By James M. Gere & Stephen Timoshenko , 5th ed Mechanics of Materials , By R. C. Hibbeler , 4th ed Mechanics of Materials , By R. C. Hibbeler , 9th ed mechanics of materials , By Riley & Sturges , 6th ed Mechanics of Materials 3rd Edition by Beer Mechanics of Materials 4th edition By Hibbeler Chapter 12 mechanics of materials 6th edition by James Gere Mechanics of Materials 6th edition by R. C. Hibbeler Mechanics of Materials 7th edition by R. C. Hibbeler mechanics of materials james gere 5th edition mechanics of solids , by Carl T. F. Ross , 1st ed Microcomputers Systems Real Time Interfacing , By Jonathan W. Valvano , 2nd= ed Microelectronic Circuit Design , By Richard C. Jaeger and Travis N. Blalock= , 4rd ed Microelectronic Circuit Design 2nd Ed. - Richard C. Jaeger and Travis N. Bl= alock Microelectronic Circuit Design 3rd Ed. - Richard C. Jaeger and Travis N. Bl= alock Microelectronic Circuit Design 3rd edition by R. Jaeger Microelectronic Circuits , By Adel S. Sedra, Kenneth C. Smith , 7th ed Microelectronic circuits 5th edition by Adel S. Sedra kennethSmith Microelectronic Circuits and Devices , Mark N. Horenstein , 2nd ed Microelectronic Circuuits , By Sedra and smith , 4th ed Microelectronics 1 & 2 by Dr. Wen Ching Chang Microelectronics Circuit Analysis and Design , Donald A. Neamen , 3th ed Microelectronics Circuit Analysis and Design , Donald A. Neamen , 4th ed Microprocessors and Interfacing-Programming and Hardware 2nd Edition by Dou= glas V. Hall Microwave and RF design of wireless systems by Pozar Microwave Engineering 2nd edition by David M Pozar Microwave Engineering 3rd Ed. by David M Pozar Microwave transistor amplifiers analysis and design 2nd edition by Guillerm= o Gonzalez Millman - Microelectronics digital and analog circuits and systems by Thoma= s V. Papathomas Mobile Communications 2nd Ed. by Jochen H. Schiller Modeling and Analysis of Dynamic Systems , By C. Close, D. Frederick, J. Ne= well , 3rd ed modern control engineering , By Katsuhiko Ogata , 4th ed modern control engineering , By Katsuhiko Ogata , 5th ed Modern Control Engineering 3rd edition by K. OGATA Modern Control Systems 11th edition by Richard C. Dorf Robert H Bishop Modern Control Systems, 12th Edition By Richard C. Dorf, Robert H. Bishop Modern Digital and Analog Communications Systems 3rd edition by B P Lathi Modern Digital Signal Processing by Roberto Cristi Modern physics , By Forsci , 2nd ed Modern Physics , By Serway , 3rd ed Modern physics , By thornton and rex , 3rd ed Modern physics By Randy Harris Molecular Quantum Mechanics ,Peter W. Atkins and Ronald S. Friedman ,5th ed Multivariable Calculus , by Dan clegg & Barbara Frank & James Stewart , 6th= ed Multivariable Calculus , Dan Clegg & Barbara Frank , 5th ed Multivariable Calculus 4th edition by Stewart Dan Clegg Barbara Frank Musculoskeletal Function An Anatomy and Kinesiology Laboratory Manual by Do= rtha Esch Esch Nanoengineering of Structural, Functional and Smart Materials Network Flows Theory, Algorithms, And Applications by Ravindra K. Ahuja, Th= omas L. Magnanti, and James B. Orlin Network Simulation Experiments Manual (The Morgan Kaufmann Series in Networ= king) by Emad Aboelela networks flows theory algorithms and applications , By Ahuja and Magnant a= nd Orlin , 1st ed Neural networks and learning machines 3rd edition by Simon S. Haykin NMR The Toolkit (How Pulse Sequences Work) ,Peter Hore, Jonathan Jones, and= Stephen Wimperis ,2nd ed Nonlinear Programming 2nd Edition by Dimitri P. Bertsekas Nuclear Magnetic Resonance ,Peter Hore ,2nd ed Numerical Analysis 8th ed. By Richard L. Burden, J Douglas Faires Numerical Methods for Engineers , By Chapra and canale , 5th ed Numerical Methods for Engineers , by Steven C. Chapra & Raymond P.Canale , = 6th ed Numerical Methods For Engineers 4th edition by Chapra Numerical Solution of Partial Differential Equations An Introduction by K. = W. Morton, D. F. Mayers Operating Systems 4th Edition by Stallings operations research , By Hamdy A. Taha , 9th ed Optimal Control Theory An Introduction By Donald E. Kirk Optimization of chemical processes by Edgar himmelblau Options, Futures and Other Derivatives 5th Edition by John Hull, John C. Hu= ll Options, Futures and Other Derivatives, 4th Edition by John Hull, John C. H= ull Organic Chemistry , 6th Ed (2006) , L.G. Wade Organic Chemistry , By John McMurry , 8th ed Organic Chemistry , By Jonathan Clayden , Nick Greeves , Stuart Warren and = Peter Wothers , 1st ed Organic Chemistry , By Paula Yurkanis , 5th ed Organic Chemistry , David Klein , 1st ed Organic Chemistry ,Cook & Cranwell Organic Chemistry ,Tadashi Okuyama and Howard Maskill ,2013 Organic chemistry 4th edition by Robert C. Athkins and Francis Carey Organic chemistry 5th edition by Robert C. Athkins and Francis Carey Organic Chemistry 7th Edition by Susan McMurry Organic Chemistry 8th ed. , L.Wade , J. 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Lewis Ford (ISBN 9780321697066) University Physics with Modern Physics , Young , 13th ed university physics with modern physics Vol.1 , By Sears and ford and freedm= an , 11th ed university physics with modern physics Vol.2 , By Sears and ford and freedm= an , 11th ed Vector Calculus , Linear Algebra and Differential Forms 2nd Edition by Hubb= ard and Burke Vector Mechanics For Engineers Static, By R.C.Hibbeler , 12th ed Vector Mechanics for Engineers , Dynamics 6th edition by Beer vector mechanics for engineers Dynamics , By Beer & Johnston , 7th ed Vector Mechanics for Engineers Dynamics , By Beer & Johnston , 10th ed Vector Mechanics for Engineers Dynamics 7th Edition by Beer vector mechanics for engineers static , by Hibbeler , 6th ed Vector Mechanics for Engineers STATICS , By Beer & Johnston , 10th ed Vector Mechanics for Engineers Statics and Dynamics 8th edition by Beer vector mechanics for engineers statistics , By Beer & Johnston , 7th ed Vector Mechanics For Static Engineers , By Beer & Johnston , 9th ed Vector Mechanics For Static Engineers , By Beer & Johnston , 10th ed Vector Mechanics For Static Engineers , By Hibbeler , 12th ed Vector Mechanics Statics 7th Edition by Beer and Johnston VHDL for Engineers International Edition by Kenneth L. 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R= appaport X-Ray Crystallography ,William Clegg ,2nd ed Zill's a First Course in Differential Equations with Modeling Applications = (7th ed.) and Zill & Cullen's Diferential Equations with Boundary-Value Pro= blems (5th ed.) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=20 If your request isn't in the list , we will find it for you, just=20 contact us=20 s o l u t i o n s b o o k t e a m @ h o t m a i l . c o m solutionsbookteam(at)hotmail(dot)com From newsfish@newsfish Thu Aug 1 00:43:49 2024 X-Received: by 2002:ac8:642:: with SMTP id e2-v6mr12973409qth.28.1534269581081; Tue, 14 Aug 2018 10:59:41 -0700 (PDT) X-Received: by 2002:a25:c5d2:: with SMTP id v201-v6mr278924ybe.4.1534269580665; Tue, 14 Aug 2018 10:59:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!e8-v6no225820qtp.0!news-out.google.com!w13-v6ni100qto.1!nntp.google.com!e8-v6no225812qtp.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Aug 2018 10:59:40 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.88.243.231; posting-account=IG2V5QoAAADWNB-jCtBjZSg45IY7zzEI NNTP-Posting-Host: 212.88.243.231 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: CRIMINALISSIMO RELAIS DEI MANDORLI DELLA SATANISTA ASSASSINA ANNA LOSAPIO (Via Luigi Calvetti, 9, 24127 Bergamo BG, Italia). VI SI RICICLANO SOLDI DI MAFIA SICULA E MAFIA FRANCESE: DEI MARSIGLIESI. SOLDI FATTI ARRIVARE DA UN NOSTRO FRATELLO MASSONE.. From: ANTONIO BINNI - BASTA COL PEDOFILO BERLUSCONI Injection-Date: Tue, 14 Aug 2018 17:59:41 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 84543 X-Received-Body-CRC: 3795828431 Xref: reader02.eternal-september.org comp.lang.vhdl:9351 CRIMINALISSIMO RELAIS DEI MANDORLI DELLA SATANISTA ASSASSINA ANNA LOSAPIO (= Via Luigi Calvetti, 9, 24127 Bergamo BG, Italia). VI SI RICICLANO SOLDI DI = MAFIA SICULA E MAFIA FRANCESE: DEI MARSIGLIESI. SOLDI FATTI ARRIVARE DA UN = NOSTRO FRATELLO MASSONE..... MOLTO MALAVITOSO: GIUSEPPE LOSAPIO, PADRE DELL= A SATANISTA ASSASSINA ANNA LOSAPIO, CHE STA A PARIGI ( E CHE RICICLA POI TA= NTISSIMI ALTRI SOLDI MAFIOSI IN CRIMINALE AZIENDA UGGIANO https://www.uggia= no.it/chi-siamo/ ). NE SCRIVE MARIA GRAZIA CRUPI, UN'ALTRA NOSTRA SORELLA M= ASSONA. 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ORA SONO UN PENTIT= O PERO', E COME FANNO I PENTITI DI MAFIA, VOGLIO SPUTTANARE GLI ASSASSINI, = SI, ASSASSINI, COME PURE STRAGISTI, PEDOFILI, MEGA COCAINOMANI, MEGA LAVATR= ICI FINANZIARIE, BASTARDI OMICIDA DITTATORI CHE SONO I BERLUSCONI, I DORIS,= I LOSAPIO, I BOSSI, I MARONI E I SALVINI E SU TUTTI I SITI DEL MONDO. LA P= AROLA, ORA, AD UN TESTO DICENTE GIUSTISSIME COSE, DA PARTE DI UN ALTRA PENT= ITA COME ME, A LIVELLO " DI BERLUSCONAZISMO E PADANAZISMO": LA PRIMA CITATA= MARIA GRAZIA CRUPI. PER BEN 12 ANNI AMANTE LESBICA DI MARINA BERLUSCONI E = CINGHIA, FRA NDRANGHETA, COSA NOSTRA, CAMORRA, FAMIGLIA BERLUSCONI E FAMIGL= IA LOSAPIO, A SCOPO DI LAVAGGIO DI PROVENTI MEGA ASSASSINI. - CIAO A TUTTI. SONO LA NOTA MASSONA DI ALTO GRADO, VICENTISSIMA PORNOSTAR ED= INSEGNANTE A MILANO: MARIA GRAZIA CRUPI. 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E' UN OMOSESSUALE PERSO, PRESTO, MOLTO PROBABILM= ENTE, SI FARA' ANCHE LA OPERAZIONE E DIVERRA' TRANS! http://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi IO, VINCENTISSIMA MASSONA, PORNOSTAR ( SEMPRE, ASSOLUTAMENTE, PERO', CON MA= SCHERINA: PER NON RISCHIARE DI PERDERE IL PUR SEMPRE COMODO E FACILE STIPEN= DIO DI DELLA PUBBLICA ISTRUZIONE) E ( COME ACCENNATO) INSEGNANTE MARIA GRAZ= IA CRUPI https://yt3.ggpht.com/a-/AJLlDp0JZgJt3slrUkUEWnWHjDcrVnCJYCft00OO8A=3Ds900-= mo-c-c0xffffffff-rj-k-no https://3.bp.blogspot.com/-dEkP1eE298c/WhONlbcQUuI/AAAAAAAAAKc/l3NqwLZT4VAM= 3xndpUyMEN0w5EsWttc7wCK4BGAYYCw/s113/AAEAAQAAAAAAAAL4AAAAJGIzZjk4YzFjLWQ1Zj= ctNGI0ZC1hYmU4LWFiODIzNzQ4ODY5Yw%255B1%255D.jpg ( COME DICEVO, SON ANCHE INSEGNANTE IN MILANO: ISTITUTI ROSA LUXEMBURG, ETT= ORE CONTI, ECT ECT.. TROVATE TUTTO QUI http://www.istruzione.lombardia.gov.= it/milano/wp-content/uploads/2013/07/Elenco-trasferimenti-definitiviIIgr.pd= f ) CHIAMATA LA " REGINA CALABRESEDDA DEGLI AMATORIAL PORN FILMS EX AMANTE LES= BICISSIMA DI MARINA BERLUSCONI". AMATORIAL PORN FILMS CHE HO FATTO A CENTIN= AIA, CENTINAIA E CENTINAIA IN VITA MIA. DI CUI ALMENO 70 PROPRIO NELLA VILL= A SATANISTA E NAZISTA, VILLA SATA-N-AZISTA DI ARCORE-HARDCORE https://www.ilfattoquotidiano.it/premium/articoli/le-notti-di-arcore-una-se= tta-del-male-con-tuniche-e-riti/ AMATORIAL PORN FILMS, SIA STRAIGHT, CHE LESBO, CHE ANCHE CON ALCUNI CAVALLI= , CHE HO GIRATO AD INIZIARE DA QUANDO AVEVO SEDICI ANNI E MEZZO, ALLORCHE' = IN MIA CALABRIA. ECCO UNA MANCIATA DI FOTO, SU MIGLIAIA E MIGLIAIA CHE HO https://4.bp.blogspot.com/-qkTlyigYRQM/WQsbwxkPZzI/AAAAAAAAALo/MGN1QnRh4Gcw= joiFO96u3-1bFXqWqegDQCK4B/s113/1443711887.76214.jpg http://b2.woxcdn.com/pics-final-2/fc3/909/fc39090be6f548a25aeec380b2ea36e2.= jpg https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcTOWSvw8gFuU_9mESWWP= FXldj2fp9uf71O-7d6iwFZh2B7IKO2RuQ https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcRQbZWcnN5tKpb_ra-np= 8v8mAfAGLrNU-7CkH7hUy8HCoWuhR6KFA http://scopateitaliane.it/fotovideo/4161.jpg RI ECCOMI ANCORA QUI, QUESTA VOLTA WITH ANOTHER PARRUCCA, MENTRE LECCO DA D= IETRO UNA MASSONA DI ORIGINI CALABRESI, DI NOTA FAMIGLIA BERLUSCONIANISSIMA= E LEGHISTISSIMA DI NDRANGHETA. COME ME, TRAPIANTATA ANCHE LEI A MILANO http://b1.woxcdn.com/pics-final-2/ced/ba8/cedba85d41629e8e0faa7f179b8f447a.= jpg ORMAI SONO SULLA SOGLIA DI FARE IL MIO MILLESIMO AMATORIAL PORN FILM, MA, A= TTENZIONE ASSOLUTA, POR FAVOR, SEMPRE CON MASCHERINA. PER NON PERDERE IL MI= O PUR SEMPRE COMODO SALARIO DEL MINISTERO DELL'ISTRUZIONE. FILM PORNO, DICE= VO, CHE HO FATTO A CENTINAIA E CENTINAIA, ORMAI E' TEMPO DI DIRE A MIGLIAIA= , FRA UN'ORGIA E L'ALTRA CON LA LESBICA NAZISTA, LAVA SOLDI MAFIOSI, ASSASS= INA, MEGA COCAINOMANE, CRIMINALISSIMA MARINA BERLUSCONI. OLTRE CHE CON LA L= ESBICA CAMORRISTA FRANCESCA PASCALE, LA LESBICA SATANISTA SIMONA PREMOLI, L= A LESBICA PURE SATANISTA DEBORAH PERAZZOLI, LA LESBICA PIU' SATANISTA DI TU= TTE, LA CRIMINALISSIMA ANNA LOSAPIO DI RELAIS I MANDORLI http://www.relaisd= eimandorli.it/ DI METAMEDICINA http://it.metamedecine.com/k_member/anna-los= apio/ E DI SERENDIPITA' http://www.serendipita.it/consulente-anna-losapio .= ED ANCORA, LA LESBICISSIMA "CHICLEFREAK" MARIA DE FILIPPI, LA LESBICONA SA= TANAZISTA GIULIA BONGIORNO, OSSIA L' AVVOCATO PIU' AMATO DA COSA NOSTRA, CA= MORRA E NDRANGHETA..OLTRE CHE CON LA "SCIUTA PAZZA" SARA TOMMASI, CON LA ZU= RIGHESE LAETITA BISSET ORA LAETITIA WAGNER ZAPPA, LA LESBICA CHE SI FINGE D= I SINISTRA ALBA PARTIETTI... E TANTE ALTRE LESBICHE O BISESSUALI , SPESSO P= URE DEPRAVATISSIME, DI ARCORE-HARDCORE... ED IL TUTTO FRA CHILI E CHILI DI = COCAINA E MONTAGNE DI CASH MAFIOSO ) LA ( APPENA CITATA FRA PARENTESI) ALTRETTANTO MASSONA, PORNOSTAR ED "ESPERT= A IN LINGUE" SIMONA PREMOLI https://plus.google.com/113646548587006228899 https://twitter.com/premolisimona https://it.linkedin.com/pub/dir/Simona/Premoli E TANTE ALTRE LESBICHE O BISESSUALI ABBIAMO LECCATO LA FIGA DI MARINA BERLU= SCONI X DECENNI, DECENNI E DECENNI! IO E SIMONA PREMOLI ABBIAMO FATTE ORGE = LESBICHE SU ORGE LESBICHE, CORREDATE DA CHILI DI COCAINA E PACCONI DI CASH = MAFIOSO, CON, COME PRIMA CITATO FRA PARENTESI, MARINA BERLUSCONI, MARIA DE = FILIPPI, DEBORAH PERAZZOLI, ANNA LOSAPIO DI RELAIS I MANDORLI, METAMEDICINA= E SERENDIPITA' ( http://www.serendipita.it/consulente-anna-losapio ), MARA= CARFAGNA (" SEMPRE DALLA CALDA FREGNA" COME OGNI GIORNO LA NICKEVAMO), MIC= HELLE BONEV, MICHELLE HUNZICKER E LA SUA AMANTE ^OCCULTISSIMAMENTE^ MASSONA= , NAZIFASCISTA E FILO MAFIOSA GIULIA BONGIORNO ( L' AVVOCATO PIU' AMATO DA = COSA NOSTRA, CAMORRA E NDRANGHETA)... ENSEMBLE ALLA CAMORRISTA FRANCESCA PA= SCALE ( LA VERA AMANTE DELLA HITLERIANA CRIMINALE MARINA BERLUSCONI, ALTRO = CHE AMANTE DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI... CHE, NON P= ER NIENTE, GIUSTAMENTE, IN PUBBLICO, TRATTA COSI' http://www.huffingtonpost= .it/2014/09/21/pascale-braccetto-berlusconi_n_5856594.html ), SARA TOMMASI = ( CHE NE ACCENNA QUI https://infosannio.wordpress.com/2011/02/09/sara-tomma= si-basta-con-le-marchette-nel-giro-di-marina-berlusconi/ ) E LA FANTASTICA = PORNOSTAR LAETITIA BISSET ORA LAETITIA WAGNER ZAPPA, CHE NE SCRIVE ALTRETTA= NTO CHIARAMENTE QUI https://disqus.com/by/laetitiabissetmarinaberlusc/ ) QUELLO CHE MI FA INCAZZARE TANTO E' CHE NONOSTANTE QUESTI SIANO TUTTI INDIS= CUTIBILI FATTI, FATTI, FATTI, UNA BASTARDA DITTATURA NEO FRANCHISTA, NEO SA= LAZARIANA, NEO PINOCHETTIANA, NEO HITLERIANA, NEO MUSSOLINIANA, BASTARDISSI= MAMENTE NEO PIDUISTA: IMPONE SILENZIO TOTALE SU TUTTO QUESTO! BASTA BERLUSC= ONAZISTA E BERLUSCOMAFIOSA OMERTA'! BASTA, BASTA, BASTA, BASTA, BASTA. FACC= IAMO LA RIVOLUZIONE, VIVA IL MOVIMENTO 5 STELLE, RIVOLUZIONE, RIVOLUZIONE, = RIVOLUZIONE, RIVOLUZIONEEEEEEEEEEEEEEEEEEEEEEEEEEEEE!!! TUTTO IL MONDO SI UNISCA A NOI IN QUESTO CORO DA MEGA STADIO " PEDOFILO BER= LUSCONI PER SEMPRE FUORI DAI COGLIONI"! " MILLE RIVOLUZIONI CONTRO I STRAGI= STI BERLUSCONI"!!! RITORNELLO DI DOVUTISSIMA CANZONE CHE STIAMO PREPARANDO IO E LA MIA AMANTE = LESBICISSIMA SIMONA PREMOLI, ORA, PLEASE: "ITALIA DEGRADATA A BERLUSCONIA DEI NAZISTI, LAVA SOLDI MAFIOSI DAVIDE SERR= A, LUIGI BERLUSCONI, MARCO CARRAI E PAOLO BARRAI, SE NON LI SBATTI IN GALER= A, VEDRAI CHE MORIRAI ( E SE MORISSE QUESTA MERDA DI ITALIA DEGRADATISSIMA = A BERLUSCONIA, FACENDO COSI' RINASCERE UNA ITALIA VERA, INDIPENDENTE, ETICA= , DEMOCRATICA, PER BENE, VINCENTE, COME QUELLA DI SANDRO PERTINI ED OSCAR L= UIGI SCALFARO, SAREBBE SOLO UNA MERAVIGLIOSA COSA) AL PUNTO DI CUI ACCENNAVO ALL'INIZIO, ORA, PLEASE ... IL CIUCCIA E PRENDI MEGA CAZZI A GO GO LUIGI BERLUSCONI (BACIO RICCHIONESCH= ISSIMO QUI http://www.si24.it/wp-content/uploads/2017/07/luigi-berlusconi--= 600x300.jpg ) NATO IN FIGHETTINA ARLESHEIM (CH) IL 27.9.1988.... L'OMOSESSU= ALE ^OCCULTO^ LUIGI BERLUSCONI http://www.leggo.it/gossip/news/luigi_berlus= coni_bacio_sulla_bocca_ad_un_amico_la_barba-2548577.html DI BASTARDAMENTE CRIMINALE ELIGOTECH AMSTERAM, BASTARDAMENTE CRIMINALE SOLD= O LTD LONDON E BASTARDAMENTE CRIMINALE BANCA MEDIOLANUM (CHE RICICLANO MONT= AGNE DI =E2=82=AC MAFIOSI, ESATTAMENTE COME FACEVA LA CRIMINALISSIMA BANCA = RASINI DI SUO NONNO, TOPO DI FOGNA LUIGI BERLUSCONI ....O COME FACEVA E FA = ORA PIU' CHE MAI, LA FININVEST DEL PEDOFILO DILANIANTE FALCONE E BORSELLINO= : SILVIO BERLUSCONI http://www.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commission= ate-berlusconi/ E DELLA CRIMINALISSIMA, HITLERIANA, ^OCCULTA" LESBICA MARINA BERLUSCONI ) INSIEME AL BERLUS-CO-RROTTO VERME MARCO CARRAI DI CGNAL, CREA NAZITECNOLOGI= CHE NUOVE OVRA E GHESTAPO! COL NOTO ANTI SEMITA, GIA' 3 VOLTE FINITO IN CAR= CERE, PAOLO BARRAI, NATO A MILANO IL 28.6.1965 ( FINITO IN CARCERE PURE IN = BRASILE, ED ANCHE PER PEDOFILIA OMOSESSUALE: INCULAVA LI I BAMBINI, NE SCRI= VEREMO PRESTO http://www.rotadosertao.com/images/fotos/fotos_noticias/testao.jpg http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 )!= UNITI AL MEGA RICICLA SOLDI ALTRETTANTO CRIMINALI: CAROGNA SCHIFOSA, MEGA = FIGLIO E MARITO DI PUTTANONE, DAVIDE SERRA DI ALGEBRIS INVESTMENTS ( NON PE= R NIENTE, SOCIO DEI VERMI MEGA RICICLA SOLDI MAFIOSI: ENNIO DORIS, MASSIMO = DORIS, GIOVANNI PIROVANO ED OSCAR DI MONTIGNY DI BANCA MEDIOLANUM, COSANOST= RANUM, CAMORRANUM, NDRANGOLANUM, HITLERANUM)! E COL TUTTO CONNESSO ALL'ECON= OMISTA NOTORIAMENTE PEDERASTA E NAZISTA PAOLO CARDEN=C3=80, NATO A MACERATA= IL 2.19.1971 E RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, N= UMERO 41. DI CRIMINALISSIMA CARDENA' CONSULTING, BASATA A FALERONE, VIA MAR= IA MONTESSORI 6 63837 FALERONE - criminalissimo numero di telefono Tel: 073= 4.710786 - altro criminalissimo numero di telefono 3335915666, criminalissi= ma e mail info@cardenaconsulting.it criminalissima email formazione@cardena= consulting.it - P.IVA: 01840990442) E CRIMINALISSIMO BLOG VINCITORI E VINTI= . IL BASTARDO MALAVITOSO PAOLO CARDEN=C3=80, SEMPRE IN CRAVATTA STILE "COLL= ETTI LERCI", RICICLA SOLDI ASSASSINI DEI MEGA OMICIDA DI COSA NOSTRA, CRISA= FULLI DI MILANO https://it.wikipedia.org/wiki/Crisafulli_(clan) )!!! E A PROPOSITO DEL PRIMA CITATO, VERME CRIMINALISSIMO, PEDOFILO, ASSASSINO P= AOLO BARRAI NATO A MILANO IL 28.6.1965..... E' DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TERRORISTA = NAZISTA, RAZZISTA, LADRO, TRUFFATORE, SEMPRE FALSO, MEGA COCAINOMANE, MANDA= NTE DI TANTISSIMI OMICIDI, QUINDI, ASSASSINO PAOLO BARRAI! NOTO PEDOFIL-O-M= OSESSUALE GIA' FACENTE FILM PORNO CON BAMBINI, RAGAZZINI E... TENETEVI DURI= SSIMO, PLEASE, ANCHE CON CAVALLI, AD INIZIO ANNI 2000... COME PRESTO PROVER= EMO http://webmail.dev411.com/p/gg/google-appengine/155cgjbg0b/c-c-c-ciuccia-ca= zzi-di-cavallo-paolo-barrai-di-wmo-e-bsi-italia-srl-una-volta-cacciato-e-fa= tto-condannare-a-galera-da-citibank-prima-di-spennare-polli-via-web-fece-fi= lm-pedopornomosessuali-e-con-cavalli-ciucciando-e-prendendo-cazzi-equini-e https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai https://it-it.facebook.com/public/Truffati-Da-Paolo-Barrai http://code.activestate.com/lists/python-list/706609/ https://productforums.google.com/forum/#!topic/blogger/GTmd4a1TkxM http://www.caffe.ch/stories/Economia/37256_spregiudicati_affaristi_di_front= iera/ NATO A MILANO IL 28.6.1965. NONCHE' MEGA RICICLA SOLDI MAFIOSI E POLITICO-C= RIMINALI, OSSIA FRUTTO DI MEGA RUBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LA= DRONA ( 48 MILIONI RUBATI CHE POI SARANNO COME MINIMO 200 E NON "SOLO" 48 https://www.nextquotidiano.it/49-milioni-la-lega-ladrona-deve-allitalia/ http://www.ilsole24ore.com/art/notizie/2017-09-14/renzi-salvini-fa-morale-m= a-lega-ha-rubato-soldi-194056.shtml?uuid=3DAEWLnMTC http://espresso.repubblica.it/inchieste/2017/09/28/news/esclusivo-salvini-h= a-usato-i-soldi-della-truffa-di-bossi-1.311009 E DI MANDANTE DI CENTINAIA DI OMICIDI "MASCHERATI" DA FINTI MALORI, INCIDEN= TI, SUICIDI, COME, TANTO QUANTO, STRAGISTA SPAPPOLA MAGISTRATI, E NAZIFASCI= STA DITTATORE E PEDOFILO: SILVIO BERLUSCONI https://www.youtube.com/watch?v=3DFFxooBwjIIc http://www.antimafiaduemila.com/home/primo-piano/68166-berlusconi-soldi-e-b= oss-mafiosi-negli-appunti-di-falcone.html https://www.ilfattoquotidiano.it/2017/12/08/mafia-lappunto-dimenticato-scri= tto-da-giovanni-falcone-berlusconi-paga-i-boss-di-cosa-nostra/4027104/ http://www.repubblica.it/politica/2017/10/31/news/mafia_e_stragi_del_93_ber= lusconi_indagato-179825283/ https://ifarabutti.wordpress.com/tag/i-soldi-sporchi-di-berlusconi/ http://ricerca.repubblica.it/repubblica/archivio/repubblica/1984/10/04/ecco= -come-riciclavano-soldi-sporchi.html https://www.ilfattoquotidiano.it/2011/05/19/silvio-riciclava-i-soldi-della-= mafia/112167/ https://www.youtube.com/watch?v=3DvXsjFhA587I https://it.wikipedia.org/wiki/Banca_Rasini http://www.today.it/rassegna/berlusconi-mafia-emilio-fede.html )! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERRORISTA D= I ESTREMA DESTRA, SANGUINARIO ASSASSINO PAOLO BARRAI. NON PER NIENTE, GIA' = STATO IN GALERA 3 VOLTE. OPINIONI TUTTE TERRIFICANTI SU DI LUI! MEGA TRUFFA= TORE E MEGA RICICLA CASH ASSASSINO VIA CRIMINALISSIMA CRYPTOLAB S A (CH), C= RIMINALISSIMA CRYPTOPOLIS (CH), CRIMINALISSIMA BITINCUBATOR VENTURES (CH), = VIA CRIMINALISSIMA BLOCKCHAININVEST LUGANO (CH), VIA CRIMINALISSIMA WMO SAG= L LUGANO (CH), VIA CRIMINALISSIMA WORLD MAN OPPORTUNITIES LUGANO (CH), VIA = CRIMINALISSIMA WMO SA PANAMA, VIA CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCR= ATE 26 MILANO! NOTO PEDOFIL-O-MOSESSUALE SODOMIZZA BAMBINI! CACCIATO DA CITIBANK A SBERLE,= PER MEGA FRODI CHE LI FACEVA! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI D= I TANTISSIME PERSONE ( HA SUL GROPPONE 500 DENUNCE DI UOMINI E DONNE A CUI = HA AZZERATO TUTTO QUEL CHE AVEVANO, PERSONE DI MEZZA EUROPA, NON SOLO DI TU= TTA FASCIOMAFIOSA DITTATURA DI BERLUSCONIA-RENZUSCONIA-ETERNAMENTEP2ISTONIA= )! FALSO&LADRO&TRUFFATORE! DIFFAMA SUL WEB A FINI "BERLUSCONAZISTI E PADANA= ZISTI"! FONDATORE DEI NUOVI MEG-A-SSASSINI TERRORISTI DI ESTREMA DESTRA: "I= NAR SON TORNATI"! FONDATORE DEL, PROSSIMAMENTE, DI FREQUENTE OMICIDA: "KU = KLUK KLAN PADANO"! CONDANNATO AL CARCERE BEN TRE VOLTE, FRA CUI A MILANO ED= IN BRASILE ( A PORTO SEGURO: 8 ANNI E PURE PER PEDERASTIA OMOSESSUALE, RIP= ETO, PURE PER PEDERASTIA OMOSESSUALE)! MULTATO DA CONSOB 70.000 =E2=82=AC! = DESTABILIZZA L'ITALIA PER FILO NAZISTI SERVIZI SEGRETI DI MEZZO MONDO ( ITA= LIA, DICEVAMO, DA 30 ANNI, GIUSTISSIMAMENTE, NAZIONE SCHIFATA IN TUTTO IL M= ONDO, IN QUANTO FASCIOMAFIOSA DITTATURA DI BERLUSCONIA-RENZUSCONIA-ETERNAME= NTEP2ISTONIA..NON PER NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITALIA DA = SECOLI, DALLA TIRANNI-A-SSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIAT, PI= RELLI, LUXOTTICA, MERLONI, PARMALAT, QUASI TUTTA LA MODA, QUASI TUTTO L' AL= IMENTARE, OLTRE CHE MIGLIAIA E MIGLIAIA DI ALTRE... E CHE SIA CHIARO PLS, C= HE IDDIO BENEDICA I GRANDI PM CHE NON SOPPORTANO IL CANCRO DEL MONDO INTERO= , SILVIO BERLUSCONI... COME HENRY WOODCOCK, ILDA BOCASSINI, NINO DI MATTEO,= ROBERTO SCARPINATO E CHIUNQUE ALTRO DI QUESTA AMMIREVOLISSIMA CATEGORIA)! FA CRIMINI SU CRIMINI E NAZI-ST-ALKING, IL MANDANTE DI OMICIDI, IL VERME AS= SASSINO PAOLO PIETRO BARRAI! SU INTERNET! SU ORDINE DEI STRAGISTI, PEDOFILI= SILVIO BERLUSCONI, PAOLO BERLUSCONI ED UBALDO LIVOLSI DI FININVEST ( CHE D= A ANNI FAN GLI ADOLPH HITLER MISTI AD AL CAPONE DEL WEB, ANCHE, MA DI CERTO= , NON SOLO, CON QUEL VERME SCHIFOSO DI GIULIO OCCHIONERO http://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhionero= _chi_sono_i_due_arrestati-155752442/ http://roma.repubblica.it/cronaca/2017/07/17/news/roma_-171015653/ ). INNEGGIANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GRAND= ISSIMAMENTE FECE CON FALCONE E BORSELLINO"! PAROLE DETTE CENTO VOLTE DALL' = ASSASSINO PAZZO, MEGA COCAINOMANE, NAZISTA PAOLO PIETRO BARRAI NATO A MILAN= O IL 28.6.1965! ORGANIZZANTE LA "SUICIDATA KILLER" DI DI DAVID ROSSI DI MONTE PASCHI, CREDE= TECI O MENO, INSIEME AL MANAGEMENT SIA DI MONTE PASCHI CHE DI BANCA MEDIOLA= NUM ( VIA MASSONERIE ASSASSINE CHE PRESTO, QUI SOTTO, MENZIONEREMO)! MA ORA... VAMONOS BABIES, VAMONOS, VAMONOS, LET'S GO...... E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZISTA, RAZZISTA, LADRO, TRUFFATORE, SEMPRE FALSO, MEGA COCAINOMAN= E, MANDANTE DI TANTI OMICIDI, QUINDI BASTARDO ASSASSINO PAOLO BARRAI! NATO = A MILANO IL 28.6.1965. NONCHE' MEGA RICICLA SOLDI MAFIOSI E POLITICO-CRIMIN= ALI, OSSIA FRUTTO DI MEGA RUBERIE E MEGA MAZZETTE, TARGATE LEGA LADRONA ( 4= 8 MILIONI DI EURO RUBATI, CHE POI SON ALMENO 60 SE NON 200, I MILIONI DI EU= RO STRA RUBATI https://www.nextquotidiano.it/49-milioni-la-lega-ladrona-deve-allitalia/ http://www.ilsole24ore.com/art/notizie/2017-09-14/renzi-salvini-fa-morale-m= a-lega-ha-rubato-soldi-194056.shtml?uuid=3DAEWLnMTC http://espresso.repubblica.it/inchieste/2017/09/28/news/esclusivo-salvini-h= a-usato-i-soldi-della-truffa-di-bossi-1.311009 E DI MANDANTE DI CENTINAIA DI OMICIDI "MASCHERATI" DA FINTI MALORI, INCIDEN= TI, SUICIDI, COME, TANTO QUANTO, STRAGISTA SPAPPOLA MAGISTRATI, NAZIFASCIST= A DITTATORE, NONCHE' ACCLARATISSIMO PEDOFILO: SILVIO BERLUSCONI https://www.youtube.com/watch?v=3DFFxooBwjIIc http://www.antimafiaduemila.com/home/primo-piano/68166-berlusconi-soldi-e-b= oss-mafiosi-negli-appunti-di-falcone.html http://www.repubblica.it/politica/2017/10/31/news/mafia_e_stragi_del_93_ber= lusconi_indagato-17982528 https://ifarabutti.wordpress.com/tag/i-soldi-sporchi-di-berlusconi/ http://ricerca.repubblica.it/repubblica/archivio/repubblica/1984/10/04/ecco= -come-riciclavano-soldi-sporchi.html https://www.ilfattoquotidiano.it/2011/05/19/silvio-riciclava-i-soldi-della-= mafia/112167/ https://www.youtube.com/watch?v=3DvXsjFhA587I https://it.wikipedia.org/wiki/Banca_Rasini http://www.today.it/rassegna/berlusconi-mafia-emilio-fede.html )! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERRORISTA D= I ESTREMA DESTRA, SANGUINARIO ASSASSINO PAOLO BARRAI. ARTEFICE DI MOLTE SPA= RIZIONI COLLEGATE AD OMICIDI SATANISTI, SPECIE IN MARCHE, PIEMONTE E LOMBAR= DIA ( IN UNIONE CON ALTRETTANTI NOTI SATANISTI ASSASSINI PAOLO E STEFANO CA= RDEN=C3=80 DI CRIMINALISSIMA CARDEN=C3=80 CONSULTING FALERONE E CON NOTE SA= TANISTE ASSASSINE ELISA COGNO E PIERA CLERICO DI ALBA DI CRIMINALISSIMA FRU= IMEX E DI FONDAZIONE FERRERO. http://www.cronachemaceratesi.it/2015/05/25/allarme-persone-scomparse-163-a= -macerata-500-nelle-marche/661329/ https://www.corriereadriatico.it/marche/marche_persone_scomparse_minori-660= 674.html https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ http://www.omnimilano.it/news_visualizza.php?Id=3D16672 ) TERRORISTA NAZISTA, RAZZISTA, LADRO, TRUFFATORE, SEMPRE FALSO, MEGA COCAINO= MANE, MANDANTE DI TANTI OMICIDI, QUINDI, BASTARDO ASSASSINO PAOLO BARRAI: G= IA' STATO IN GALERA 3 VOLTE. MEGA TRUFFATORE, CRIMINALE DI PIU' EFFERATA SPECIE PAOLO BARRAI MEGA RICICLA CASH ASSASSINO, COME DI LEGA LADRONA E SPAPPOLA MAGISTRATI, PE= DOFILO SILVIO BERLUSCONI - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA BITINCUBATOR VENTURES (CH), - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA CRYPTOPOLYS S. A. (CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA CRYPTOLAB S. A. (CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA BITMAX.CH (CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA EIDOO CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA BLOCKCHAININVEST CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA WMO SAGL LUGANOCH) . VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA WORLD MAN OPPORTUNITIES LUGANO (CH= ) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA WMO SA PANAMA - VIA CRIMINALISSIMA BHB, CRIMINALISSIMA NETWORKBLOCKCHAINLABIT E CRIMINALI= SSIMA ASSOB.IT DI ALTRETTANTO NOTO TERRORISTA NAZIFASCISTA, MEGA RICICLA SO= LDI MAFIOSI E MANDANTE DI OMICIDI: GIACOMO ZUCCO http://es.listoso.com/android-developers/2017-08/msg00208.html https://it.linkedin.com/in/giacomozucco https://es.linkedin.com/in/giacomozucco - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 M= ILANO DI SUO PADRE, GIA' CONDANNATO AL CARCERE TANTE VOLTE, IN PASSATO: PER= PEDOFILIA, TRUFFA E RICICLAGGIO DI PROVENTI KILLER.. VERME DELINQUENTISSIM= O, SEMPRE DENTRO E FUORI SAN VITTORE: VINCENZO BARRAI NATO A MILANO IL IL 3= .5.1938 E RESIDENTE A MILANO IN VIA PADOVA 282! http://markmail.org/message/lxrvezqxbmpoawcd STO VERME DEPRAVATO E PAZZO DI PAOLO PIETRO BARRAI NATO A MILANO IL 28.6.19= 65 E' ANCHE UN NOTO PEDOFIL-O-MOSESSUALE SODOMIZZA BAMBINI E RAGAZZINI! CAC= CIATO, FRA L'ALTRO, DA CITIBANK, A SBERLE ( E FATTO CONDANNARE AL CARCERE, = COME PRIMA CITATO, DA CITIBANK) PER MEGA FRODI E TRUFFE CHE LI LO STESSO FA= CEVA ( DA GRANDE BANCHIERE GIULIO DI CERBO, POI, NON PER NIENTE, FATTO AMMA= ZZARE DA PAOLO BARRAI VIA SUOI CONTATTI NAZIFASCISTI CHE HA PRESSO LA CIA, = LA NSA E SERVIZI SEGRETI STILE GLADIO, DI QUELLA MERDA DITTATORIALE CHE E' = BERLUSCONIA-RENZUSCONIA, AHIME', EX REPUBBLICA DEMOCRATICA ITALIANA)! IL FI= UNZIONARIO DI CITIBANK, IN GROSSI GUAI, A SEGUITO DI MEGA LADROCINI FATTI D= A PAOLO BARRAI E PIETRO TERENZIO, COME DA FINALE DI QUESTO ARTICOLO DI REPU= BBLICA, ERA PROPRIO IL VERME SANGUINARIO PAOLO PIETRO BARRAI http://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19/maxi= -evasione-da-400-miliardi-terenzio-sotto-torchio.html PER NON DIRE DI QUANTO L' AZZERA RISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI, = SBAGLI SEMPRE IN BORSA! AZZERI I RISPARMI DI TANTISSIME PERSONE ( HA SUL GR= OPPONE 500 DENUNCE DI UOMINI E DONNE A CUI HA ANNIENTATO TUTTO QUEL CHE AVE= VANO ... DI MEZZA EUROPA, NON SOLO DI TUTTA FASCIOMAFIOSA DITTATURA DI BERL= USCONIA-RENZUSCONIA-ETERNAMENTEP2ISTONIA)! SEMPRE FALSO&LADRO&TRUFFATORE! D= IFFAMA SUL WEB A FINI "BERLUSCONAZISTI E PADANAZISTI"! FONDATORE DEI NUOVI = MEG-A-SSASSINI TERRORISTI DI ESTREMA DESTRA: "I NAR SON TORNATI"! FONDATORE= DEL, PROSSIMAMENTE, DI FREQUENTE OMICIDA: "KU KLUK KLAN PADANO"! CONDANNAT= O AL CARCERE BEN TRE VOLTE ( SPECIE, MA NON SOLO) A MILANO ED IN BRASILE ( = A PORTO SEGURO: 8 ANNI, PER RICICLAGGIO DI SOLDI MAFIOSI EFFETTUATO PRESSO = HSBC http://it.cultura.linguistica.narkive.com/XV3Bw8gY/sono-simona-premoli-ex-a= mante-lesbica-di-marina-berlusconi-e-per-ben-13-anni-e-13-ani-che-mi-sono:i= .2.10.thumb TRUFFA, PROPOGANDA NAZISTA E RAZZISTA, LADROCINIO, MINACCE, ESTORSIONE E PU= RE PER PEDERASTIA OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg )! MULTATO DA CONSOB BEN 70.000 =E2=82=AC ( ORA, IL VISCIDO BERLUSCONICCHIO GI= USEPPE VEGAS, VISCIDO BERLUSCONICCHIO TANTO QUANTO IL CRIMINALE PAOLO BARRA= I STESSO, SU RICHESTA DEL PEDOFILO MAXIMO DI ARCORE-HARDCORE, SILVIO BERLUS= CONI, STA FACENDO IMBOSCARE LA NOTIZIA, SU INTERNET, MA ECCO I LINKS ORIGIN= ALI A PROPOSITO http://www.bluerating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un= -ex-promotore-che-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://groups.google.com/forum/#!topic/qc.politique/XjdEpV1zGxY STO VERME DI PAOLO BARRAI, PER NON RISCHIARE DI PASSARE DECENNI A SAN VITTO= RE, COME ACCADUTO AL PADRE PEDOFILO VINCENZO BARRAI, E' QUINDI SCAPPATO IN = SVIZZERA. OVE PERO', IN CANTON TICINO E CANTON GRIRIONI E' SOTTO 22 INCHIES= TE, PER QUESTO, PER EVITARE MANETTE ELVETICHE, ORA INTENDE SCAPPARE A LONDR= A ( VEDI FINALE DI QUESTO SUO, COME AL SOLITO, DISONESTISSIMO E PUZZOLENTIS= SIMAMENTE FASCISTA ARTICOLO http://ilpunto-borsainvestimenti.blogspot.mx/20= 17/12/trumps-il-miglior-presidente-degli.html ) FA CRIMINI SU CRIMINI E NAZI-ST-ALKING, IL MANDANTE DI OMICIDI, IL VERME AS= SASSINO PAOLO PIETRO BARRAI! SU INTERNET! SU ORDINE DEI STRAGISTI, PEDOFILI= SILVIO BERLUSCONI, PAOLO BERLUSCONI, ENNIO DORIS, MASSIMO DORIS, OSCAR DI = MONTIGNY ED UBALDO LIVOLSI ( CHE DA ANNI FANNO GLI ADOLPH HITLER MISTI AD A= L CAPONE DEL WEB, ANCHE, MA DI CERTO, NON SOLO, CON QUEL VERME SCHIFOSO DI = GIULIO OCCHIONERO http://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhionero= _chi_sono_i_due_arrestati-155752442/ http://roma.repubblica.it/cronaca/2017/07/17/news/roma_-171015653/ ). INNEGGIANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GRAND= ISSIMAMENTE FECE CON FALCONE E BORSELLINO"! PAROLE DETTE CENTO VOLTE DALL' = ASSASSINO PAZZO, MEGA COCAINOMANE, NAZISTA, OMICIDA PAOLO PIETRO BARRAI NAT= O A MILANO IL 28.6.1965! ORGANIZZANTE LA "SUICIDATA KILLER" DI DAVID ROSSI DI MONTE PASCHI, CREDETEC= I O MENO, INSIEME AL MANAGEMENT SIA DI MONTE PASCHI CHE DI BANCA MAFIOLANUM= , NAZISTANUM, MEDIOLANUM ( VIA MASSONERIA ASSASSINA DI SILVIO BERLUSCONI, C= HIAMATA IL DRAGO, DI CUI E' PARTE, COME NE SON PARTE I VERTICI DI MONTE PAS= CHI E DI BANCA MAFIOLANUM, NAZISTANUM, MEDIOLANUM .. LOGGIA BERLUSCONAZISTA= " IL DRAGO" DI ARCORE-HARDCORE, ASSOLUTA NUOVA P2, ESATTAMENTE SANGUINARIA= E KILLER COME ERA LA P2 https://it-it.facebook.com/notes/contro-linformazione-manipolata/un-capo-ma= ssone-rivela-berlusconi-ha-fondato-la-sua-loggia-%C3%A8-l%C3%AC-che-si-deci= de-no/437022599774/ http://www.ilsussidiario.net/News/Politica/2017/11/2/SILVIO-BERLUSCONI-P2-E= -MAFIA-Le-inchieste-sulle-stragi-del-1993-e-la-macchina-del-fango/790452/ )= ! MA ORA... VAMONOS BABIES, VAMONOS, VAMONOS, LET'S GO, LET'S GOOOOOO...... - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA EIDOO, DIRETTA DAL VERME MALAVITOSO, NDRANGHETISTA CALABRESE NATAL= E M. FERRARA O NATALE FERRARA CHE SIA https://medium.com/@nataleferrara https://groups.google.com/forum/#!topic/comp.lang.python/a7hWErJ0dP0 https://groups.google.com/forum/#!topic/comp.lang.python/6T61cCR1EbY https://twitter.com/nataleferrara ( EXTREMELY CRIMINAL EIDOO.... YOUR VERY HOODLUM ASSET EXPERIENCE, MEGA MAF= IA MONEY LAUNDERER FOR COSA NOSTRA, NDRANGHETA, CAMORRA AND ASSASSIN RUSSIA= N GANSGTERS, NOT FOR NOTHING, CLOSE TO PRINCIPAL OF HUNDREDS OD MURDERS AND= SLAUGHTERS: ASCERTAINED PEDOPHILE SILVIO BERLUSCONI) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA CRYPTOPOLYS E CRYPTOLAB S A http://www.rotadosertao.com/images/fotos/fotos_noticias/testao.jpg https://pbs.twimg.com/media/CIB3862WcAA8F7c.png https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg http://www.caffe.ch/stories/Economia/37256_spregiudicati_affaristi_di_front= iera/ https://productforums.google.com/forum/#!topic/blogger/GTmd4a1TkxM ( OVE MEGA RICICLA SOLDI MAFIOSI COL NOTO VERME KUKLUKLANISTA, NAZIFASCISTA= , MEGA RICICLA SOLDI MAFIOSI, BASTARDO VERO ARON CAMPONOVO DI MALAVITOSISSI= MA TANTO QUANTO IBEX CAPITAL LTD, MALAVITOSISSIMA TANTO QUANTO MONCLER SUIS= SE LTD, MALAVITOSISSIMA TANTO QUANTO IBEX SERVICES LTD https://media.licdn.com/mpr/mpr/shrinknp_200_200/AAEAAQAAAAAAAAOJAAAAJDdmMT= E5ZGU0LTRiYTgtNDZhZS04MjI3LWRhNGVjZTRkM2QyOA.jpg http://www.moneyhouse.ch/it/p/aron-camponovo ED INSIEME AL NOTO RAZZISTA, KUKLUKLANISTA, HITLERIANO, MEGA RICICLA SOLDI = DI MALAVITE DI TUTTO IL MONDO E PURE ACCERTATO PEDOFILO: OLIVER CAMPONOVO D= I CAMPONOVO STRATEGY http://www.moneyhouse.ch/p/oliver-camponovo TUTT'UNO CON LA NDRANGHETA, INSIEME, BEN APPUNTO, AL PEZZO DI MERDA ASSASSI= NO, CRIMINALISSIMO PAOLO PIETRO BARRAI https://www.pressreader.com/switzerland/laregione/20171207/281874413739928 http://www.giornaledelticino.ch/41167/soldi-%E2%80%9Ctriangolati%E2%80%9D-d= ella-ndrangheta-due-condanne-bellinzona https://www.cdt.ch/ticino/bellinzona/191575/mafia-in-ticino-nuova-condanna https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ https://www.laregione.ch/cantone/mendrisiotto/1228182/affari-della--ndrangh= eta-in-ticino--alla-sbarra-l-uomo-di-fiducia-della-cosca--l-ex-municipale-d= i-chiasso-e-la-moglie-del-fratello-del-boss http://www.area7.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della-ndra= ngheta-29f7ee00 ) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA CRYPTOLAB SA (CH) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA BITMAX.CH - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI BLOCKC= HAIN INVEST (CH) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA BIGBITGOLD E CRIMINALISSIMA BIGBIT (CH) -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA, MEGA RICICLA SOLDI MAFIOSI WORLD MAN OPPORTUNITIES LUGANO (CH) https://www.moneyhouse.ch/it/company/world-man-opportunities-sagl-176913463= 31 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA, SEMPRE MEGA RICICLA SOLDI MAFIOSI, BITINCUBATOR VENTURES GRONO (CH= ) ( AFFIANCATO IN QUESTO DA QUEL NOTO MALAVITOSO, RICICLA SOLDI ASSASSINI DI = CLAUDIO LEVRINI DI BLEVIO https://www.moneyhouse.ch/it/person/levrini-claudio-133823793501 DI MALAVITOSA BITCOIN FOUNDATION, E, BEN APPUNTO, DI CRIMINALISSIMA BITINCU= BATOR VENTURES GRONO https://www.moneyhouse.ch/en/company/bitincubator-ventures-sa-12554072241 ) -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA ASSOB.= IT DI ALTRETTANTO NOTO TERRORISTA NAZIFASCISTA, MEGA RICICLA SOLDI MAFIOSI = VIA BITCOINS E MANDANTE DI OMICIDI: GIACOMO ZUCCO http://es.listoso.com/android-developers/2017-08/msg00208.html https://it.linkedin.com/in/giacomozucco https://es.linkedin.com/in/giacomozucco -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA WMO SA PANAMA ( https://plus.google.com/108961714786994835238/posts/9zrBkh9csJZ https://www.scribd.com/doc/307086915/Riccacosta-S-A-PAOLO-BARRAI-REGISTRO-P= UBLICO-PANAMA-Mercato-Libero POSTA INSIEME ALLE FAMOSISSIME IN PANAMA CITY COME "PUTAS MEGA LAVA DINERO = ASESINO" DIGNA PEREZ MARTINEZ Y TATIANA MAGDALENA BARAHONA ... BEN NOTA IN = TUTTO MONDO COME TATIANA MAGDALENA "LA BALDRACCONA" AVENDO LAVORATO PER DEC= ENNI IN NIGHT CLUBS COLOMBIANI ED AVENDO FATTO IN COLOMBIA MIGLIAIA DI FILM= PORNO) IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINAL= ISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO DI SUO PADRE, GIA' CONDANNAT= O AL CARCERE TANTE VOLTE, IN PASSATO: PER PEDOFILIA, TRUFFA E RICICLAGGIO D= I PROVENTI KILLER.. VERME DELINQUENTISSIMO, SEMPRE DENTRO E FUORI SAN VITTO= RE: VINCENZO BARRAI NATO A MILANO IL IL 3.5.1938 E RESIDENTE A MILANO IN VI= A PADOVA 282! http://markmail.org/message/lxrvezqxbmpoawcd -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI FORZA I= TALIA MAFIOSA, FORZA ITALIA CAMORRISTA, FORZA ITALIA NDRANGHETISTA... DE VE= RDAD http://www.globalist.it/politics/articolo/2009525/il-pm-forza-italia-punto-= di-riferimento-di-cosa-nostra-ndrangheta-e-camorra.html https://www.ilfattoquotidiano.it/2017/07/26/stragi-pm-di-reggio-le-mafie-si= -fermarono-quando-trovarono-in-forza-italia-la-struttura-con-cui-relazionar= si/3756080/ IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI LEGA LAD= RONA ( PER LA QUALE IMBOSCA ALL' ESTERO I FAMOSI 48-60 MILIONI DI EURO RUBA= TI DALLA STESSA http://espresso.repubblica.it/inchieste/2017/09/28/news/esclusivo-salvini-h= a-usato-i-soldi-della-truffa-di-bossi-1.311009 ) -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI QUOTIDI= ANO IL GIORNALE E QUOTIDIANO LIBERO ( MA NAZISTA), OVE FA LE TRAME PIU' ASS= ASSINE, COL FIGLIO DI PUTTANA HITERLIANO E NAZI-ST-ALKER PAOLO BERLUSCONI, = COL FIGLIO DI PUTTANA HITERLIANO E NAZI-ST-ALKER ALESSANDRO SALLUSTI, COL F= IGLIO DI PUTTANA HITERLIANO E NAZI-ST-ALKER PIETRO SENALDI, COL FIGLIO DI P= UTTANA HITERLIANO E NAZI-ST-ALKER VITTORIO FELTRI, COL FIGLIO DI PUTTANA HI= TERLIANO E NAZI-ST-ALKER FRANCO BECHIS E COL FIGLIO DI PUTTANA HITERLIANO E= NAZI-ST-ALKER FAUSTO CARIOTI! - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI TANTIS= SIMI GRUPPI TERRORISTI DI ESTREMA DESTRA ED ANTI SEMITI ( TIPO I DA LUI APP= ENA FONDATI " I NAR SON TORNATI" -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI VARI GR= UPPI ASSASSINI DEL KU KLUK KLAN - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI SANGUI= NARIA MASSONERIA ROSACROCIANA DEL BASTARDO KILLER CLAUDIO MAZZUCCO ( NON SIAMO PER NULLA ANTI MASSONICI A PRESCINDERE, PENSIAMO APPIENO CHE LA= MASSONERIA ABBIA AVUTO FRA SE ALCUNI TRA I MIGLIORI UOMINI DI TUTTI I TEMP= I, COME GALILEO GALILEI, MAHATMA GANDHI, MARTIN LUTHER KING E PARECCHI ALTR= I.. https://labuonastrada.wordpress.com/2014/11/21/secondo-gioele-magaldi-marti= n-luther-king-era-massone/ MA I MASSONI ASSASSINI, NAZIFASCISTI E FILO MAFIOSI, ALIAS I MASSONI DI STA= MPO "BERLUSCONAZISTA E PADANAZISTA" CI FAN STRA SCHIFO E NE SIAM FERISSIMI = BOUT IT .. QUI NE PARLA GIULIANO DI BERNARDO STESSO https://www.youtube.com= /watch?v=3DYA-ryJ-2kPU NOI SCRIVIAMO DI FATTI, FATTI, FATTI.. " FATTI QUOTI= DIANI" O MENO... NON DI CHIACCHERE AT ALL) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI "BERLU= SCONAZIFASCISTA" GRAN LOGGIA D'ITALIA DEL MEGA RICICLA SOLDI MAFIOSI ANTONI= O BINNI ( NON SIAMO PER NULLA ANTI MASSONICI A PRESCINDERE, PENSIAMO APPIEN= O CHE LA MASSONERIA ABBIA AVUTO FRA SE ALCUNI TRA I MIGLIORI UOMINI DI TUTT= I I TEMPI, COME GALILEO GALILEI, MAHATMA GANDHI, MARTIN LUTHER KING E PAREC= CHI ALTRI.. https://labuonastrada.wordpress.com/2014/11/21/secondo-gioele-magaldi-marti= n-luther-king-era-massone/ MA I MASSONI ASSASSINI, NAZIFASCISTI E FILO MAFIOSI, ALIAS I MASSONI DI STA= MPO "BERLUSCONAZISTA E PADANAZISTA" CI FAN STRA SCHIFO E NE SIAM FERISSIMI = BOUT IT .. QUI NE PARLA GIULIANO DI BERNARDO STESSO https://www.youtube.com= /watch?v=3DYA-ryJ-2kPU NOI SCRIVIAMO DI FATTI, FATTI.. " FATTI QUOTIDIANI" = O MENO... NON DI CHIACCHERE AT ALL) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA SAN= GUINARISSIMA LOGGIA "SATA-N-AZISTA", ORGANIZZANTE DOZZINE DI STRAGI E CENTI= NAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI ED INCIDENTI, LOGGIA PE= RSONALE DI SPAPPOLA MAGISTRATI E PEDOFILO MAXIMO SILVIO BERLUSCONI, CHIAMAT= A " IL DRAGO ( DI ARCORE-HARDCORE) https://it-it.facebook.com/notes/contro-linformazione-manipolata/un-capo-ma= ssone-rivela-berlusconi-ha-fondato-la-sua-loggia-=C3=A8-l=C3=AC-che-si-deci= de-no/437022599774/ http://www.centroparadesha.it/ude/articoli/1156-549-la-loggia-del-drago-di-= galeazzi-pinotti ( NON SIAMO PER NULLA ANTI MASSONICI A PRESCINDERE, PENSIAMO APPIENO CHE LA= MASSONERIA ABBIA AVUTO FRA SE ALCUNI TRA I MIGLIORI UOMINI DI TUTTI I TEMP= I, COME GALILEO GALILEI, MAHATMA GANDHI, MARTIN LUTHER KING E PARECCHI ALTR= I.. https://labuonastrada.wordpress.com/2014/11/21/secondo-gioele-magaldi-marti= n-luther-king-era-massone/ MA I MASSONI ASSASSINI, NAZIFASCISTI E FILO MAFIOSI, ALIAS I MASSONI DI STA= MPO "BERLUSCONAZISTA E PADANAZISTA" CI FAN STRA SCHIFO E NE SIAM FERISSIMI = BOUT IT .. QUI NE PARLA GIULIANO DI BERNARDO STESSO https://www.youtube.com= /watch?v=3DYA-ryJ-2kPU NOI SCRIVIAMO DI FATTI, FATTI, FATTI.. " FATTI QUOTI= DIANI" O MENO... NON DI CHIACCHERE AT ALL) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI GRAN L= OGGIA ITALIA MASSONICA DEL MALAVITOSO BANCHIERE GIUSEPPE SABATO DI BANCA ES= PERIA ( GRUPPO BANCARIO PARZIALMENTE DELLO SPAPPOLA MAGISTRATI, NONCHE' ACC= LARATISSIMO PEDOFILO SILVIO BERLUSCONI) https://www.avvocatisenzafrontiere.it/?p=3D1788 https://groups.google.com/forum/#!topic/mozilla.reps.council/n0UahGyuFVw ( NON SIAMO PER NULLA ANTI MASSONICI A PRESCINDERE, PENSIAMO APPIENO CHE LA= MASSONERIA ABBIA AVUTO FRA SE ALCUNI TRA I MIGLIORI UOMINI DI TUTTI I TEMP= I, COME GALILEO GALILEI, MAHATMA GANDHI, MARTIN LUTHER KING E PARECCHI ALTR= I.. https://labuonastrada.wordpress.com/2014/11/21/secondo-gioele-magaldi-marti= n-luther-king-era-massone/ MA I MASSONI ASSASSINI, NAZIFASCISTI E FILO MAFIOSI, ALIAS I MASSONI DI STA= MPO "BERLUSCONAZISTA E PADANAZISTA" CI FAN STRA SCHIFO E NE SIAM FERISSIMI = BOUT IT .. QUI NE PARLA GIULIANO DI BERNARDO STESSO https://www.youtube.com= /watch?v=3DYA-ryJ-2kPU NOI SCRIVIAMO DI FATTI, FATTI, FATTI.. " FATTI QUOTI= DIANI" O MENO... NON DI CHIACCHERE AT ALL) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA MAL= AVITOSA ELIGOTECH, DELL'OMOSESSUALE ^OCCULTO^, SEMPRE SCOPATO SBORRATO IN C= ULO: LUIGI BERLUSCONI ( MA TRA IL SILENZIO NAZISTA CHE IL PEDOFILO SPAPPOLA= MAGISTRATI SILVIO BERLUSCONI IMPONE) http://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi https://www.leggo.it/gossip/news/luigi_berlusconi_bacio_sulla_bocca_ad_un_a= mico_la_barba-2548577.html - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA CRI= MINALISSIMA, MEGA RICICLA CASH MAFIOSO, SOLDO LTD ROMA O CRIMINALISSIMA, ME= GA RICICLA CASH MAFIOSO, SOLDO FINANCIAL SERVICES LTD DEI VERMI MALAVITOSI = STESSI LUIGI BERLUSCONI ED ANDREA GAUDENZI https://beta.companieshouse.gov.uk/company/09233754 https://www.agimeg.it/politica/giochi-luigi-berlusconi-andrea-gaudenzi-inve= stono-soldo-ltd-societa-costituita-gualandri-fondatore-gioco-digitale ( NIPOTE DEL TOPO DI FOGNA LUIGI BERLUSCONI, A SUA VOLTA, BESTIA CRIMINALIS= SIMA A " KAPO' " DELLA CHIUSA PER MEGA RICICLAGGIO DI SOLDI MAFIOSI, BANCA = RASINI http://www.beveraedintorni.com/lettere-deliranti/3382-la-banca-rasini-sciol= ta-per-mafia-e-la-famiglia-berlusconi.html http://temi.repubblica.it/micromega-online/mafia-politica-e-affari-sette-do= mande-al-cavaliere/?printpage=3Dundefined http://www.uonna.it/ragnatela4.htm E FIGLIO DI NOTO PEDOFILO SILVIO BERLUSCONI http://www.elafter.com/foro/showthread.php?t=3D948509 http://www.pressreader.com/italy/libero/20091220/281552286967928 https://www.youtube.com/watch?v=3DDeNisVOfssc http://www.democraticidavvero.it/adon.pl?act=3Ddoc&doc=3D5241 FIGLIO DI NOTO MANDANTE DI DOZZINE DI STRAGI SILVIO BERLUSCONI http://www.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commission= ate-berlusconi/ http://www.ilfattoquotidiano.it/2017/06/09/graviano-e-berlusconi-peter-gome= z-ricostruisce-le-stragi-del-1993/3648613/ FIGLIO DI NOTO MANDANTE DI CENTINAIA E CENTINAIA DI OMICIDI MASCHERATI DA F= INTI SUICIDI, MALORI ED INCIDENTI: SILVIO BERLUSCONI http://www.ilsecoloxix.it/p/genova/2012/07/27/APxMHy2C-scrivere_berlusconi_= assassino.shtml http://www.pmli.it/sismicolpivanemiciberlusconi.htm ) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA MAL= AVITOSISSIMA CGNAL DEL PEZZO DI MERDA BERLUS-CO-RROTTTISSIMO MARCO CARRAI http://www.liberoquotidiano.it/news/politica/12333673/marco-carrai-inchiest= a-consip-fondato-club-forza-italia.html http://www.liberoquotidiano.it/news/politica/11905690/silvio-berlusconi-mar= co-carrai-societa-.html http://espresso.repubblica.it/plus/articoli/2016/10/17/news/marco-carrai-l-= amico-che-mette-matteo-renzi-nei-guai-1.285898 - IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA = MERDA FASCIOMAFIOSA E MEGA RICICLA SOLDI LERCI DI ENNIO DORIS E MASSIMO DOR= IS: BANCA MEDIOLANUM, COSANOSTRANUM, CAMORRANUM, NDRANGOLANUM, LAVALAVAPERC= OCALEROSCOLOMBIANUM, NAZISTANUM http://ricerca.repubblica.it/repubblica/archivio/repubblica/2009/01/24/rici= claggio-arrestato-sciume-avvocato-della-finanza-milanese.html?ref=3Dsearch https://www.ilfattoquotidiano.it/2013/04/02/fisco-chiede-a-mediolanum-344-m= ilioni-riflettori-sulle-operazioni-in-irlanda/549322/ http://www.repubblica.it/cronaca/2010/10/18/news/quella_villa_d_avanzo-8169= 812/ -IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIM= INALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO http://google-guice.narkive.com/aPNDvjEA/criminali-bastardi-di-bsi-italia-s= rl-via-socrate-26-milano-paolo-barrai-e-vincenzo-barrai-noti RAPPRESENTATA DA UN NOTO PEDERASTA E MEGA RICICLA SOLDI MAFIOSI, CONDANNATO= IN ANNI PASSATI A DIVERSI ANNI DI GALERA PER TUTTO IL SOPRA CITATO: VERME = BASTARDISSIMO VINCENZO BARRAI http://markmail.org/message/hbiib64yeyqpvaei ABITANTE IN VIA PADOVA 282 A MILANO E NATO A MILANO IL 3.5.1938 - IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI, FINIT= O, "APPENA APPENA" 3 VOLTE IN GALERA ( UNA DI QUESTE 3 VOLTE, FINITO IN GAL= ERA IN BRASILE E PURE PER PEDOFILIA OMOSESSUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg TANTO PER INIZIARE..NELLA NAZIMAFIOSA DITTATURA DI BERLUSCONIA, VIA FINECO,= LAVA CASH ASSASSINO, VIA PROMOTORE FINANZIARIO VICINISSIMO PURE A NDRANGHE= TA, CAMORRA E COSA NOSTRA: ALDO ACQUISTAPACE DI CREDIT SUISSE MILANO https://www.linkedin.com/in/aldo-acquistapace-820a85b0 (fratello del noto delinquente Marco Acquistapace di Londra, facente miglia= ia e migliaia di efferati crimini via Synergy Global Management Limited....= trattasi di un altro colletto mega lercio, super riciclante soldi mafiosi = provenienti da killer di Puglia, Sicilia, Calabria, Campania, ma anche da C= olombia, Romania ed Albania... da anni ed anni al centro di centinaia e cen= tinaia di scandali, truffe e ruberie di ogni.. http://corrieredelmezzogiorno.corriere.it/bari/notizie/cronaca/2013/20-giug= no-2013/soldi-fisco-finiti-uno-yacht-lussoa-processo-evasione-11-milioni-22= 21769688150.shtml ... ovviamente, scandali, truffe e ruberie tutte targate, ^neopiduistissima= mente^, fasciomafioso, ladro, truffatore, mega pallonaro, nazidittatore, la= vatrice di proventi super assassini, stragista spappola magistrati, deprava= to lecca fighe di zoccole 14 enni marocchine, vomitevole pedofilo Silvio Be= rlusconi). ADELANTE BABY, ADELANTE, ADELANTE.... VAMONOS BABIES, VAMONOS, VAMONOS, LET'S GOOOOOOOOOO NON FATEVI ROVINARE DAL FIGLIO DI PUTTANA CRIMINALISSIMO PAOLO PIETRO BARRA= I NATO A MILANO IL 28.6.1965! FA AZZERARE I RISPARMI DI TUTTI, SEMPRE! INDA= GATO DA PROCURA DI LUGANO! INDAGATO DA 7 PROCURE ITALIANE, DA POLIZIA ITALI= ANA E GUARDIA DI FINANZA ITALIANA! INDAGATO DA EUROPOL ED INTERPOL! CON, SU= L GROPPONE, BEN 70.000 EURO DI MULTA DA PARTE DI CONSOB! CONDANNATO A GALER= A IN MILANO! CONDANNATO AD 8 ANNI DI CARCERE IN BRASILE ( ANCHE PER PEDOFIL= IA OMOSESSUALE, RIPETO, ANCHE PRE PEDOFILIA OMOSESSUALE)! INDAGATO PESANTIS= SIMAMENTE A PANAMA, IN GERMANIA, PORTOGALLO ED INGHILTERRA! NOTO NAZIRAZZIS= TA ASSASSINO DEL KU KLUK KLAN PADANO, SVIZZERO, INGLESE ED AMERICANO! FAMOS= ISSIMO TRUFFATORE, LADRO, FALSONE, NAZI-ST-ALKER VIA INTERNET! SBAGLIA SEMP= RE E STRA SEMPRE IN BORSA! Siamo un foltissimo guppo di risparmiatori truffati dal criminale, gia' tre= volte in galera, Paolo Barrai di malavitosissime societa' Bsi Italia srl, = Wmo Sa Panama, World man opportunities Lugano! Multato da Consob per ben 70.000 euro per sue mega frodi su fotovoltaico http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html https://www.adviseonly.com/blog/investire/mercati-finanziari/il-trading-dei= -miracoli/ http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion Condannato al carcere in Brasile per estorsioni, stalking via internet, min= acce di morte, pedofilia omosessuale, proprio cosi', pedofilia omosessuale.= Oltre che ladrate, truffe, mega riciclaggio di proventi mafiosi, propagand= a nazista e razzista! Come questi articoli ( pero', di appena inizio indagi= ne) dimostrano! Poi, il tutto e' divenuto, ben appunto condanna al carcere = e per tanti anni... ovvio che il Renato Vallanzasca in cravatta, Paolo Barr= ai, in Brasile non mette piu' piede... ha paura delle gattabuie locali http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg POSSO SOLO RIPETERLO!!!!!!! E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZIRAZZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965= . http://google-guice.narkive.com/aPNDvjEA/criminali-bastardi-di-bsi-italia-s= rl-via-socrate-26-milano-paolo-barrai-e-vincenzo-barrai-noti NONCHE' RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI MEGA RUB= ERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA E STRAGISTA SPAPPOLA MAGISTR= ATI, NONCHE', TANTO QUANTO, NAZIFASCISTA DITTATORE E PEDOFILO: SILVIO BERLU= SCONI! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERRO= RISTA NAZISTA ED ASSASSINO, PAOLO BARRAI. NON PER NIENTE, GIA' STATO IN GAL= ERA 3 VOLTE. OPINIONI TUTTE TERRIFICANTI SU DI LUI! MEGA TRUFFATORE E MEGA = RICICLA CASH ASSASSINO VIA CRIMINALISSIMA BLOCKCHAIN INVEST O VIA CRIMINALI= SSIMA BLOCKCHAININVEST CHE SIA, OLTRE CHE VIA CRIMINALISSIMA WMO SAGL LUGAN= O, CRIMINALISSIMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PAN= AMA E CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO! NOTO PEDOFIL-= O-MOSESSUALE SODOMIZZA BAMBINI E RAGAZZINI! CACCIATO DA CITIBANK A SBERLE, = PER MEGA FRODI CHE LI FACEVA! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI DI= TANTISSIME PERSONE! FALSO&LADRO&TRUFFATORE! DIFFAMA SUL WEB A FINI NAZI-RA= ZZISTI! FONDATORE DEI NUOVI MEGASSASSINI TERRORISTI DI ESTREMISSIMA DESTRA:= "NUOVI NAR"! FONDATORE DEL, PROSSIMAMENTE, DI FREQUENTE, OMICIDA: KU KLUK = KLAN PADANO! CONDANNATO AL CARCERE A MILANO ED IN BRASILE ( 8 ANNI E PURE P= ER PEDERASTIA OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE)! MULTAT= O DA CONSOB 70.000 =E2=82=AC! DESTABILIZZA L'ITALIA PER FILO NAZISTI SERVIZ= I SEGRETI SVIZZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTISSIMAMENTE, NAZION= E SCHIFATA IN TUTTO IL MONDO, IN QUANTO FASCIOMAFIOSA DITTATURA DI BERLUSCO= NIA.. NON PER NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITALIA DA SECOLI, = DALLA TIRANNIASSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIAT, PIRELLI, LUX= OTTICA, MERLONI E MIGLIAIA E MIGLIAIA DI ALTRE... E CHE SIA CHIARO, PLS, CH= E IDDIO BENEDICA I GRANDI PM CHE NON SOPPORTANTO IL CANCRO DEL MONDO INTERO= , SILVIO BERLUSCONI, COME HENRY WOODCOCK, ILDA BOCASSINI E CHIUNQUE ALTRO D= I QUESTA AMMIREVOLISSIMA CATEGORIA)! FA CRIMINI SU CRIMINI E NAZI-ST-ALKING= , SU INTERNET, SU ORDINE DEI PUZZONI CRIMINALISSIM SILVIO BERLUSCONI, PAOLO= BERLUSCONI ED UBALDO LIVOLSI DI FININVEST ( CHE DA ANNI FANNO GLI ADOLPH H= ITLER MISTI AD AL CAPONE, DEL WEB, ANCHE, MA DI CERTO, NON SOLO, CON QUEL V= ERME SCHIFOSAMENTE TERRORISTA DI GIULIO OCCHIONERO). INNEGGIANTE ALLO SPAPP= OLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GRANDISSIMAMENTE FECE CON F= ALCONE E BORSELLINO"! PAROLE SUE, DETTE SPESSISSIMO! ORGANIZZANTE OMICIDIO = DI DAVID ROSSI DI MONTE PASCHI! Ho tantissimo da scrivere sul gia' 3 volte finito in galera, accertatissimo= pedofilo omosessuale, ladro, truffatore, sempre falso, nazi-st-alker, mand= ante di omicidi ( spesso, ma non sempre, mascherati da finti incidenti, mal= ori o "suicidate"... come quando fece ammazzare David Rossi di Monte Paschi= , ma ne scrivero' in dettagli molto presto), mega ricicla soldi mafiosi e/o= politico-criminali (piu' tanto di orrido altro), arrestato gia' 3 volte, P= aolo Barrai, nato a Milano il 28.6.1965 e gia' residente a Milano in Via Ip= podromo 105! Come presto meglio sottolineeremo, multato dalla Consob ben 70= .000 euro! http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html https://www.adviseonly.com/blog/investire/mercati-finanziari/il-trading-dei= -miracoli/ http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion Ho tantissimo da scrivere su sto Renato Vallanzasca ( in quanto ad indole m= alavitosa) misto ad Ugo Fantozzi ( in quanto ad essere il piu' grande ciula= , perdente, cane in Borsa, brucia risparmi di tutti e sempre, sia esso su a= zioni, criptovalute, valute, obbligazioni, materie prime, case, diamanti, o= ro fisico, qualsiasi tipo di investimento... con la differenza che Ugo Fant= ozzi era simpatico e per bene a sua nettissima differenza) della finanza pi= u' filo mafiosa e ricicla soldi mafiosi che esista. In criminalissima Fineco... - attraverso arrogantissimo promotore finanziario Luca Morelli (o arroganti= ssimo e delinquente promotore finanziario Luca Giovanni Morelli che sia) https://it.linkedin.com/in/luca-morelli-4210321 - ED ATTRAVERSO I NOTI MASSONI ASSASSINI, SI, ASSASSINI, TUTT' UNO, TRA L'A= LTRO, CON COSA NOSTRA, NDRANGHETA, MAFIA CINESE E MAFIA RUSSA, PAOLO CARDEN= =C3=80 E STEFANO CARDEN=C3=80 DI CRIMINALISSIMA CARDEN=C3=80 CONSULTING DI = VIA MONTESSORI 6 E 8 DI FALERONE IN PROVINCIA DI FERMO.. CE NE PARLA UNO CH= E CI HA LAVORATO PER ANNI, INSIEME, ORA DA LORO DISSOCIATOSI, ALL' INTERNO = DELLA PROSSIMA, DOVUTA.... "NON PICCOLISSIMA" PARENTESI ( E' CRIMINALISSIMA= LA CARDEN=C3=80 CONSULTING DI VIA MONTESSORI 6, FALERONE, VIA MONTESSORI 6= E 8...... DA ANNI RICICLA SOLDI ASSASSINI DI COSA NOSTRA, CAMORRA, NDRANGH= ETA, MAFIA CINESE E MAFIA RUSSA, QUEST'ULTIMA, CHE NON PER NIENTE, LAVO' PR= IMI PROPRI =E2=82=AC OMICIDA, A LIVELLO MONDIALE, ESATTAMENTE NELLE MARCHE.= .. E I VERMI SCHIFOSI CHE LA RAPPRESENTANO, I BASTARDI EFFERATI CRIMINALI S= TEFANO CARDENA' E PAOLO CARDENA' SONO DUE "SATA-N-AZISTI" PEDOFILI INCULA B= AMBINI, SGOZZA BAMBINI ED UCCIDI BAMBINI A RAFFICA... REGISTI DI CENTINAIA = E CENTINAIA DI OMICIDI E SPARIZIONI DI PERSONE ACCADUTI NELLA LORO SATANIST= ISSIMA MACERATA E MARCHE IN GENERE, COME DA QUESTO ARTICOLO http://www.cronachemaceratesi.it/2015/05/25/allarme-persone-scomparse-163-a= -macerata-500-nelle-marche/661329/ CRIMINALE CARDEN=C3=80 E PARTNERS DI VIA MONTESSORI 6, 63837 FALERONE (FM) = - Tel: 0734.710786 - sua malavitosissima e mail: info@cardenaconsulting.it = - P.IVA: 01840990442..... DA ANNI RICICLA SOLDI ASSASSINI DI COSA NOSTRA, C= AMORRA E MAFIA RUSSA, CHE, COME DICEVAMO, NON PER NIENTE LAVO' PRIMI PROPRI= =E2=82=AC OMICIDA PROPRIO NELLE MARCHE... E PAOLO CARDENA' E PURE BEN NOTO= PEDOFILO.... IL MASSONE PEDERASTA INCULA BAMBINI PAOLO CARDEN=C3=80 HA UN = BLOG CRIMINALISSIMO... VINCITORI E VINTI... NOI SAREMO I VINCITORI CHE METT= EREMO LUI, I SUOI MEGA CRIMINI E MEGA BALLE, SPALLE AL MURO.... MENTRE LUI = SARA' IL VINTISSIMO... IL VERME DELINQUENTISSIMO PAOLO CARDEN=C3=81, NATO A= MACERATA IL 2.19.1971 E RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMB= ERTO I, NUMERO 41, OLTRE AD ESSER NOTO PEDOFILO E' UN PORCO MEGA RICICLA SO= LDI MAFIOSI PER I SUPER KILLER DI COSA NOSTRA, CRISAFULLI DI MILANO..... E = PER I PORCI MEGA RICICLA SOLDI ASSASSINI DI MALAVITE DI MEZZO MONDO.. ENNIO= DORIS E MASSIMO DORIS DI MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOLANUM,= NAZISTANUM.... BUT AGAIN AND AGAIN AND AGAIN AND AGAIN.... CHI =C3=88 DAVV= ERO STO SCHIFOSO PEDOFIL-O-MOSESSUALE STUPRANTE, BAMBINI ED ADOLESCENTI, CH= IAMANTESI PAOLO CARDEN=C3=80 RESIDENTE A PENNA SAN GIOVANNI, VIA UMBERTO I,= NUMERO 41... DI BASTARDAMENTE CRIMINALE CARDEN=C3=80 CONSULTING, BASATA IN= VIA MONTESSORI 6, 63837 FALERONE Tel: 0734.710786.....E DI MEGA TRUFFATORE= BLOG VINCITORI E VINTI..... CHE ESISTE PER FAR ABBOCCARE I "CIULA DEL WEB"= , CHE CADENDO NELLE TRAPPOLE DI SUOI MEGA FALLIMENTARI SERVIZI, SEMPRE PERD= ONO TUTTI I PROPRI RISPARMI, SIA PER LA TOTALE INCOMPETENZA DI PAOLO CARDEN= =C3=80 A PROPOSITO DI MERCATI FINANZIARI MONDIALI, SIA PER LA INDOLE SEMPRE= ESTREMAMENTE TRUFFALDINA DEL VERME CRIMINALISSIMO PAOLO CARDEN=C3=80 STESS= O... BUT AGAIN AND AGAIN AND AGAIN AND AGAIN.... CHI E' IL BASTARDISSIMO CR= IMINALE, PURE NOTI PEDERASTA ED ASSASSINI PAOLO CARDEN=C3=80 http://a.mytre= nd.it/authors/1385.jpg UNITO ED IL VERME CRIMINALE STEFANO CARDEN=C3=80 http://www.formazione-lavoro.eu/img/public/stefano.jpg FACENTE DA DECENNI TRUFFE SU TRUFFE E MEGA RICICLAGGI DI CASH MAFIOSO DAGLI= UFFICI DI Via Maria Montessori, 8, 63020 Falerone FM, Italia Telefono: +39= 0734 710786 ...criminalissima email info@cardenaconsulting.it e altra crim= inalissima email formazione@cardenaconsulting.it..ED ANCOR PRIMA.. CHI SONO= IO? MI VOLETE FARE FUORI IN QUANTO DICO LA VERITA' ^?^.... COSA CHE NELLA = FASCIOMAFIOSA ITALIA, DA 40 ANNI DITTATURA NAZINDRANGHETISTA DI BERLUSCONIA= , ACCADE DA MILLENNI.... SONO UN FUORI USCITO DA QUEL PARTITO STRA COLMO DI= COSA NOSTRA, CAMORRA, NDRANGHETA E CATTIVERIA ANTI DEMOCRATICA DI ESTREMIS= SIMA DESTRA CHE E' FORZA ITALIA ... DI STO VERME CRIMINALE DI PAOLO CARDEN= =C3=81, CHE IN FORZA ITALIA, INSIEME AL AMEGA RICICLA SOLDI MAFIOSI DIEGO D= ELLA VALLE, FA LA LAVATRICE DI CAPITALI ASSASSINI, ASSASSINI, CHE PIU' ASAS= SINI NON POTREBBERO ESSERE... DI LUII SO' TUTTO, E QUINDI, COME DICONO A NA= PULE, ORA MI "HAGGIA PROPRIO SFUGA' " .... PROFESSIONALLY SPEAKING, SI DEFI= NISCE "PRIVATE BANKER"...MA NON DICE CHE UNICI SUOI CLIENTI SONO I MAFIOSI = ASSASSINI CRISAFULLI DI MILANO... UNA DELLE FAMIGLIE DI COSA NOSTRA PIU' BA= STARDAMENTE KILLER DI TUTTI I TEMPI... E POI, COME CITATO, IL VOMITEVOLE PE= DERASTA PAOLO CARDEN=C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI E' PURE= NOTISSIMO PEDOFIL-O-MOSESSUALE ... QUI E' IN UNA FOTO CHE GLI ABBIAMO FATT= O, MENTRE, IN MUTANDE, FISSAVA, CON SGUARDO DA DEPRAVATO SESSUALE MAXIMO, U= N BAMBINO DI OTTO ANNI, NELLE ADIACENZE DI UN CAMPO ROM PADANO, VICINO A CO= LOGNO MONZESE, VICINO A SUA MAFIASET-CAMORRASET-NDRANGASET-NAZISTSET MEDIAS= ET...DA CUI ERA APPENA USCITO.... http://a.mytrend.it/authors/1385.jpg DICEVAMO CHE IN DETTA FOTO ... http://a.mytrend.it/authors/1385.jpg .... IL PEDERASTA INCULA ED AMMAZZA BAMBINI PAOLO CARDEN=C3=80 OSSERVA IN M= ANIERA DEPRAVATISSIMA UN BAMBINO ROM DI OTTO ANNI.... CHE MEZZ'ORA DOPO INC= ULERA' A SANGUE...... PRESTO OGNI COSA SU MIGLIAIA DI SITI, ANCHE DI PLUTON= IO E MARTE, NON SOLO DI QUESTO PIANETA SEMPRE PIU' "PICCIRIDDU PICCIRIDDU" = .. USO SLANG SICILIANO, PER FAR SENTIRE IL MEGA RICICLA CASH DI COSA NOSTRA= , PAOLO CARDEN=C3=81, COME SE IN UNA "COSA SUA" AAAA".... E POI... IL BLOGG= ER PEDERASTA, NAZISTA, RAZZISTA, RICICLA CASH MAFIOSO PAOLO CARDEN=C3=81 DI= CRIMINALISSIMO BLOG VINCITORI E VINTI... RAGLIEREBBE SU INTERNET CHE FAREB= BE IL PRIVATE BANKER.. MA, COME "FORSE" CITATO, NON AGGIUNGE CHE I SUOI SOL= I 2 CLIENTI SONO LE FAMIGLIE MAFIOSE ED ASSASSINE CAGNETTI E CRISAFULLI DI = MILANO.. E POI... COME E' LO SCHIFOSO PEDERASTA PAOLO CARDEN=C3=80, NELLA V= ITA PRIVATA ^?^ COI PANTALONI ABBASSATI ^?^ 5 SERE ALLA SETTIMANA ANDAVA IN= LOCALI ^OCCULTISSIMI^ DI TIPO ESTREMAMENTE PERVERTITO APERTI SOLO A MASSON= I OMOSESSUALI LEGHISTI E BERLUSCONIANI.... CI VA' COL PARI PEDERASTA GIULIO= TREMONTI, I CUI AMANTI OMOSESSUALISSIMI ERANO I NAZISTI, ANZI, SATA-N.AZIS= TI MARCO BROTTO, EX CENTROSIM E BANCA LEONARDO, ED ANCOR PIU' IL PAZZO ASSA= SSINO ALEXANDER BOETTCHER .. QUELLO CHE SI RIEMPIVA DI COCAINA E FACEVA SFR= EGIARE CON ACIDO ASSASSINO TANTA GENTE INNOCENTE, INNOCUA, PER BENE.. MASSO= NE BERLUSCO-N-AZISTA E PADA-N-AZISTA ALEXANDER BOETTCHER, COLUI CHE SI DEFI= NIVA SE STESSO UN PERICOLOSISSIMO DEPRAVATO SESSUALE http://www.dagospia.com/rubrica-29/cronache/sono-deviato-sessuale-martina-l= evato-era-sadomasochismo-124763.htm VI ERA UN DEAL BERLUSCONICCHIO CHE ERA QUESTO.... ALEXANDER BOETTCHER INCUL= AVA L'OMOSESSUALE ^OCCULTISSIMO^ GIULIO TREMONTI ..COME QUESTO TWITTER ACCO= UNT FA STRA INTUIRE https://twitter.com/alexanboettcher E L ^ OCCULTISSIMO^ MASSONE LAVA SOLDI MAFIOSI, OMOSESSUALE DI TIPO PERVERT= ITO, GIULIO TREMONTI, CERCAVA DI FARLO SFONDARE IN POLITICA.. ALLA FINE, PE= RO', L'UNICA COSA SFONDATA ERANO LA PROSTATA E L' ANO DEL CULACCHIONE "CHIC= LE FREAK", DEL MASSONE ^OCCULTISSIMAMENTE^ GAY DI TIPO SEMPRE PIU' PEDERAS= TA: GIULIO TREMONTI STESSO! - Ed attraverso criminalissima Banca Mediolanum dei banchieri malavitosi Ca= rlo Secchi ( puzzone schifoso, sempre a tramare a morte, via Trilaterale) O= scar di Montigny, Ennio Doris, Massimo Doris e Giovanni Pirovano http://www.mediolanum.com/ITA/12231_profili-manageriali.html - Ed attraverso malavitosissima Arner Bank Lugano dei colletti lerci stile = "topi di fogna" Giovanni Schraemli, Gabriele Gandolfi e Roland M=C3=BCller-= Ineichen http://www.arnerbank.ch/?view=3D2242 - Ed attraverso malavitosissima BancaStato Lugano dei bastardi criminali Be= rnardino Bulla, Fabrizio Cieslakiewicz, Daniele Albisetti e Claudio Genasci https://www.bancastato.ch/bancastato/chi-siamo/Corporate-Governance/Direzio= ne-generale.html - Ed attraverso criminalissima Tax and Finance Lugano, di quel porco schifo= so, lurido, puzzone, mega ricicla cash mafioso che e' Gerardo Segat https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.moneyhouse.ch/it/p/gerardo-segat ( a cui era unito, un altro porco schifoso, lurido, puzzone, mega ricicla c= ash mafioso, Andrea Baroni, ex Tax and Finance, non per niente finito in ga= lera http://carlofesta.blog.ilsole24ore.com/2015/10/10/intrigo-internazionale-la= rresto-di-baroni-socio-delladvisor-di-mr-bee-sul-milan/ ) - Ed attraverso malavitosissima InvestireOggi.it del topo di fogna albanese= Bogdan Bultrini, mega ricicla cash assassino di Mala, ben appunto, Albanes= e, ma anche Bulgara, Rumena, Turca e Russa https://it.linkedin.com/in/bogdan-bultrini-62132220 - COME ATTRAVERSO IL NOTO CRIMINALISSIMO PEDOFIL-O-MOSESSUALE STEFANO BASSI= DE IL GRANDE BLUFF E DI TORINO https://groups.google.com/forum/#!topic/comp.lang.python/0_mkZKCAs74 CHE QUI VEDETE NELLA SUA PERVERSIONE DI PEDOFILO INCULA ED AMMAZZA BAMBINI.= A PETTO NUDO VA' SU INTERNET, STO CESSO BRUTTISSIMO E PEDERASTA DI TORINO.= NONCHE' SATANAZISTA KILLER STEFANO BASSI: IL SODOMIZZA ED UCCIDI BAMBINI D= E IL GRANDE BLUFF. https://talkmusic.site/talkmusic/qMGXY1CfSjU/che-tristezza-i-soldidice-il-c= lassico-fallito-radical-chic-italopiteco-ma-vaffanculooooo TUTT'UNO CON LA NDRANGHETA E DA ANNI. CINTURA FRA ASSASSINI CALABRESI BASAT= I IN PIEMONTE, BEN NOTO SPAPPOLA MAGISTRATI E PEDOFILO SILVIO BERLUSCONI E = LEGA LADRONA. LAVATRICE FINANZIARIA DEI KILLER NDRANGHETISTI CROTONESI DELL= E FAMIGLIE OMICIDA VRENNA E MEGNA, VERI E PROPRI PADRONI DI MEZZO PIEMONTE. PER NON DIRE, POI, DEL BASTARDO NAZIRAZZISTA E MEGA RICICLA SOLDI MAFIOSI: = GIACOMO ZUCCO DI CRIMINALISSIMA BHB-BLOCKCHAINLAB, BLOCKCHAINLABIT, ASSOB.I= T E WMO SA PANAMA ( NONCHE' DI HITLERIANI TEA PARTIES) https://1.bp.blogspot.com/-e_LRApIYQrc/WEKCZf1swNI/AAAAAAAAjSU/JVphLLcsq60h= ZSLv3QddLrWif6UEkBQdwCLcB/s1600/barrai%2Bzucco.jpg TRATTASI DI QUESTO NANETTO CON FACCIA DA TIPICO SEGAIOLO COMPULSIVO https://i.ytimg.com/vi/VhfifMuKc74/maxresdefault.jpg QUI A PROCESSO, A MILANO, PER UNO DEI SUOI SOLITI TANTISSIMI CRIMINI "BERLU= SCONICCHI" https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico SCHIFOSO KU KLUK KLANISTA. CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI DA MATT= INA A SERA. E, PER LO STESSO PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI= , LA MERDA MALAVITOSA GIACOMO ZUCCO, MEGA RICICLA SOLDI ASSASSINI DI BEN 7 = NDRINE BASATE NEL MILANESE ( FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PA= SQUALE MORABITO). COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! PER NON AGGIUNGERE DEL PARI PEDERASTA ED AZZERA RISPARMI FEDERICO IZZI, DET= TO ZIO ROMOLO https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/FKY_roBbVQ4 ( MEGA RICICLA CASH MALAVITOSISSIMO DEI GIRI LERCI DI MAFIA CAPITALE E DI C= AMORRISTI PRESENTI NEL BASSO LAZIO https://meloniclaudio.wordpress.com/2016/12/30/la-camorra-a-roma-e-nel-lazi= o/ http://www.adnkronos.com/fatti/cronaca/2016/03/04/blitz-contro-camorra-nel-= casertano-nel-basso-lazio-arresti_Ee3CRNYmUmhxiTgmJJK3kI.html http://www.iltempo.it/cronache/2013/11/02/gallery/i-veleni-della-camorra-ne= l-basso-lazio-913245/ ). O DEL PARI PEDERASTA MAURIZIO BARBERO DI TECHNOSKY MONTESETTEPANI https://groups.google.com/forum/#!search/MAURIZIO$20BARBERO%7Csort:relevanc= e/comp.soft-sys.matlab/YvZMKV-5VPM/jWEwnxs-UCEJ https://groups.google.com/forum/#!topic/free.it.discussioni.divorzio/D8bxM3= OVbLg https://twitter.com/mlnews_com?lang=3Des SEMPRE IN THAILANDIA A STUPRARE BAMBINI SU BAMBINI https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/hDk33qscjro ( ED IL NOTO PEDOFILO MAURIZIO BARBERO DI TECHNOSKY MONTESETTEPANI ERA CIO'= CHE UNIVA I CREATORI DI NUOVE OVRA E GESTAPO, I BASTARDI CRIMINALI UBALDO = LIVOLSI, FRANCESCA OCCHIONERO E GIULIO OCCHIONERO AD ENAV http://www.ilfattoquotidiano.it/2017/01/13/giulio-occhionero-un-cyberspione= -che-piu-maldestro-non-si-puo/3312745/ http://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_inchiesta-= 155753314/ DI CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA S= ERVIZI SEGRETI DI ESTREMA DESTRA, SPESSISSIMO ASSASSINI, E' IN PIENO, PARTE= ). E a proposito del pregiudicato, gia' stra condannato a galera Ubaldo Livols= i di criminalissima Livolsi - Iaquinta and partners e di Fininvest, nota in= tutto il mondo come (Ma)Fi(a)Ninvest... Trattasi anche lui di viscidissimo= pedofilo che paga ragazzini perche' lo inculino ( i Berlusconiani stanno a= i pedofili, come il sole sta ad Habana Cuba a luglio... e da sempre..ad ini= ziare dal pedofilo dei pedofili numero uno al mondo: Silvio Berlusconi http://www.elmundo.es/elmundo/2010/11/03/internacional/1288770719.html http://www.huffingtonpost.it/2015/03/26/intervista-gianni-boncompagni_n_694= 5522.html http://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-senat= ore-a-vita-un-pedofilo/14626/ ). Pure assassino. Proprio cosi': pure assassino! Organizzava tanti omicidi fr= a il 2001 ed il 2006, omicidi mascherati da finti suicidi, malori ed incide= nti. Il tutto targato "disarticolazioni attraverso mezzi traumatici (ossia = killer)" http://forum.enti.it/viewtopic.php?t=3D66625 http://www.ariannaeditrice.it/articolo.php?id_articolo=3D6352 http://www.omniauto.it/forum/index.php?showtopic=3D17113 https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://www.grnet.it/news/95-news/852-segreto-di-stato-sulle-schedature-ille= gali-berlusconi-salva-pollari-a-pompa http://ferdinandoimposimato.blogspot.pt/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pt/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l Non siamo comunisti, ma anche questo link dice cose interessantissime a pro= posito http://www.pmli.it/sismicolpivanemiciberlusconi.htm Schifezze mega omicida che il pezzo di merda assassino Ubaldo Livolsi prima= faceva col suo amante omosessuale Pio Pompa, noto in tutto il mondo come "= er pompinaro" Pio Pompa ( cuginetto de "er nuovo pompinaro" Mike Pompeo dei= prima citati, ku kluk klanisti Tea Parties e della nazifascista e nazimafi= osa Cia attuale). E con lo schifoso verme, anche lui noto pederasta, Giulio= Occhionero ( massone sata-n-azista del Goi). Fra l'altro sto verme viscidi= ssimo di Ubaldo Livolsi da decenni mega ricicla cash assassino di Matteo Me= ssina Denaro. E di certo non solo. E' gia' stato condannato al carcere per = il caso Finparthttp://www.repubblica.it/economia/finanza/2012/04/03/news/cr= ac_finpart_livolsi_condannato-32697350/ Era dietro le piu' lercie puzzone trame dei furbetti del quartierino. Fa pe= dinare abusivamente. Intecetta telefonate abusivamente. Come detto, organiz= za nuove Ovra e Gestapo assassine. Sia pubbliche che private. Dovrebbe esse= re in carcere, ora, a spompinarsi col noto "er pompinaro" Pio Pompa ed il s= uo partner gay, nonche' terrorista nazifascista killer, Giulio Occhionero! STA BESTIA SCHIFOSA DI PAOLO BARRAI RICICLA CASH KILLER ANCHE ATTRAVERSO UN= 'ALTRA SOCIETA' CRIMINALISSIMA: LA FRUIMEX DI TORINO, ALBA ... E "BLOGSPOT"= . SOCIETA' ESTREMAMENTE MALAVITOSA CHE RICICLA TANTI SOLDI MAFIOSI, ESATTAM= ENTE DELLA NDRANGHETA ( VIA FAMIGLIE MEGASSASSINE CALABRESI BELFIORE E CREA= , NOTORIAMENTE, CONTROLLANTI TUTTA TORINO), MA ANCHE DI COSA NOSTRA E CAMOR= RA (SOCIETA' CRIMINALISSIMA, MEGA RICICLA SOLDI MAFIOSI FRUIMEX DI VIA NICO= LA FABRIZI 44 10145 TORINO Tel: 011746342 COME ANCHE SOCIETA' CRIMINALISSIM= A, MEGA RICICLA SOLDI MAFIOSI FRUIMEX DI ALBA: LOCALITA' SAN CASSIANO 15 - = 12051) https://www.guidamonaci.it/gmbig/main.php?p=3Dcomp_prof01&id=3D154326093763= 838 BASTARDAMENTE MALAVITOSA FRUIMEX "KAPEGGIATA" DA DUE SCHIFOSE PROSTITUTE DI= ESTREMISSIMA DESTRA, SEMPRE AD ARCORE-HARDCORE A FARE SESSO ANALE. E DA AN= NI ( VANNO A FARE SESSO ANALE AD HARDCORE-ARCORE DA TANTI ANNI... E PURE DA= "TANTI ANI"). NOTA MIGNOTTONA NAZIFASCISTA PIERA CLERICO, BEN APPUNTO, DEL= LA FRUIMEX ( MADRE) https://groups.google.com/forum/#!topic/comp.lang.python/T3V3zB9FRtU https://it-it.facebook.com/public/Piera-Fruimex E NOTA MEGA TROIA, SEMPRE NAZIFASCISTA, ELISA COGNO DELLA ^SATA-N-AZISTA^ F= ONDAZIONE FERRERO E PURE DELLA FRUIMEX ( FIGLIA) http://www.jlaforums.com/viewtopic.php?t=3D251058941 http://www.impresaitalia.info/mstdb80753147/fruimex-di-cogno-elisa-e-c-sas/= alba.aspx COME SAPETE, IL MONDO DEL BITCOIN E DELLA BLOCKCHAIN SERVE, AL 99,99999%, S= OLO A RICICLARE SOLDI ASSASSINI! DI MAFIE DI TUTTO IL MONDO! E DI TERRORIST= I KILLER DI ESTREMA DESTRA ( QUALE E' DA SEMPRE PAOLO BARRAI E TUTTI I VERM= I SOPRA QUI CITATI)! http://www.ilsole24ore.com/art/commenti-e-idee/2017-01-24/bitcoin-riciclagg= io-invisibile-mafie-e-terrorismo-internazionale-164825.shtml?uuid=3DAEISiAH http://fortune.com/2012/12/18/bitcoin-looks-primed-for-money-laundering/ https://www.bloomberg.com/news/articles/2016-11-11/hong-kong-central-bank-f= lags-blockchain-money-laundering-risk DA QUI CHE ALTRI CRIMINI SU CRIMINI A LIVELLO DI RICICLAGGIO VENGONO EFFETT= UATI FRA IL GIA' TRE VOLTE IN GALERA, PAOLO BARRAI ED IL DELINQUENTE SCHIFO= SO RICCARDO CASATTA DI MALAVITOSE ETERNITY WALLS E GIA' CITATA BLOCKCHAINLA= B! COME FRA IL NOTO PEDOFIL-O-MOSESSUALE, TRUFFATORE, BRUCIANTE O LADRANTE I R= ISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI E L'AL CAPONE DI LONDRA, CHIAMATO D= A TUTTI "THE CRIMINAL BEAST": THOMAS BERTANI FROM ORACLIZE. ONE OF WORST MA= FIA MONEY LAUNDERERS PRESENT IN THE CITY. PROPRIO COSI', A LONDRA LO CHIAMA= NO TUTTI " LA BESTIA CRIMINALE" A THOMAS BERTANI DI ORACLIZE. UNO DEI MASSI= MI RICICLATORI DI CASH DEI MAFIE DI MEZZO MONDO DELLA CITY (INSIEME AL MEGA= VERME, PARIMENTI CRIMINALISSIMO, DAVIDE SERRA DI ALGEBRIS, TWITTER E FACEB= OOK... NON PER NIENTE SOCIO DEI PORCI DI COSA NOSTRA PRIMA CITATI DI BANCA = MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOLANUM, NAZISTANUM... COME VEDETE= , QUADRIAMO OGNI COSA E SEMPRE.. MA NON METTIAMO ORA, TROPPA CARNE A FUOCO,= PLEASE.. TROPPA CARNE PUO' ANCHE DIVENIRE INDIGESTA... OGNI COSA LA DESCRI= VEREMO SU DIVERSI TESTI AND REAL SOON). Io, Gianni Panni, sono uno dei tantissimi da lui truffato. L'efferato crimi= nale Paolo Barrai nato a Milano il 28.6.1965 mi ha azzerato tutti i risparm= i. Come accaduto anche a centinaia e centinaia di altre persone come me https://www.facebook.com/public/Truffati-Da-Paolo-Barrai http://www.today.it/user/profile/truffati/16094703496099/ Si. Sono Gianni Panni di Modena (dovuto nick name per ovvi motivi di auto p= rotezione). Manager della Maserati ( in questo caso per davvero: nessuna " = nick profession"). giannipanni@gmx.com Come tutti sanno, sto verme malavitoso di Paolo Barrai, e' stato condannato= da Consob a pagare ben 70.000 euro di multa per mega truffa fatta da sto v= erminoso, vi assicuro, pure pederasta sodomizza bambini (ne scrivero' molto= presto), che e' Paolo Barrai di criminalissima Bsi Italia srl di Via Socra= te 26 Milano, criminalissima Blochain Invest o criminalissima Blockchainini= nvest che sia ( che controlla insieme ad un altro schifoso verme mega ricic= la soldi mafiosi, via bitcoins, Natale Ferrara di Naters o verme mega ricic= la soldi mafiosi, via criminalissima Eidoo, Natale Massimiliano Ferrara di = Naters, o verme mega ricicla soldi mafiosi via criminalissima Eidoo, Natale= M. Ferrara di Naters che sia https://twitter.com/nataleferrara unito poi, al citato, sempre mega ricicla cash assassino di Cosa Nostra, Ca= morra e Ndrangheta, Giacomo Zucco https://groups.google.com/forum/#!topic/android-chennai/t9Ob_1wXFd8 che lava capitali assassini tanto quanto, via criminalissime BHB-Blockchain= labit e AssoB.it Non per niente, noto nazista, razzista, mega kuklukklanista, rappresentante= i terroristi assasini di estremissima destra, Tea Parties, nel verminaio s= wastikato di "loro" Berlusconia-Renzusconia-Gentilusconia-Salvinusconia-Cal= endusconia or whatever disgusting and horrid you may wanna call it). Per no= n parlare della criminalissima World Man Opportunities di Via Mazzini 14, 6= 900 Lugano, criminalissima WMO Sagl Lugano alias criminalissima Wmo Sa Pana= ma e criminalissimo blog Mercato "Merdato" Libero. Multa connessa a sua meg= a frode sul fotovoltaico http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html https://www.adviseonly.com/blog/investire/mercati-finanziari/il-trading-dei= -miracoli/ http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion Come e' stato condannato al carcere in Brasile, otto anni di galera sentenz= iatissimi. Per pedofilia omosessuale, furto, truffa, minacce di morte, tent= ativi di estorsione uniti a stalking via internet, riciclaggio di soldi maf= iosi, propaganda razzista, propaganda nazifascista. Ecco i links di inizio = indagine. Ora vi e' la sentenza. E' scappato da Porto Seguro, di notte, in = pieno carnevale 2011, per fuggire a processo e galera ( ed ovviamente, da a= llora, di piedi in Brasile non ne ha mai piu' messi: perbacco che coinciden= zuzza bedda). Fate voi di che schifoso topo di fogna parliamo quando parlia= mo di sto colerico ratto criminale che da sempre e' Paolo Barrai (o ratto c= riminalissimo "Paolo Pietro Barrai" nato a Milano il 28.6.1965..... come si= fa chiamare all'estero, truffaldinamente, e quindi, come da suo solito... = per vigliaccamente depistare Google) http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 Condannato al carcere a Milano ad inizio anni 2000. "Il funzionario di Citibank che faceva criminalissimi finti conti bancari e= criminalissime finte transazioni bancarie" come da finale del seguente art= icolo, era assolutissimamente lui http://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19/maxi= -evasione-da-400-miliardi-terenzio-sotto-torchio.html Cacciato a sberle, poi, da Citibank e fatto condannare al carcere da stessa= Citibank. Il, vi assicuro, pure frequentissimo mandante di omicidi ( mascherati da fi= nti suicidi, malori, incidenti, o meno), Paolo Barrai, e' uno degli assolut= issimi killer di David Rossi di Monte Paschi. Unito in questo ai masso-n-az= ifascisti, assassini, mega ricicla soldi mafiosi: verme criminale, nonche' pedofilo spappola magistrati Silvio Berlusconi. Un= ito al gia' in galera, notissimo verme criminale Paolo Berlusconi. And agai= n and again and again: verme criminale Marina Berlusconi di mega ricicla so= ldi assassini Fininvest, verme criminale Fedele Confalonieri di mega ricicl= a soldi assassini Fininvest e Mediaset, verme criminale Pasquale Cannatelli= di mega ricicla soldi assassini Fininvest (noto come "o Ndranghetista pazz= o", in quanto unitissimo alla cosca del noto assassino Sebastiano Romeo det= to " U Staccu", per via delle tante teste che ha decapitato in vita sua), v= erme criminale Yves Confalonieri di mega ricicla soldi assassini Fininvest = e Mediaset, verme criminale Ennio Doris di mega ricicla soldi assassini Ban= ca Mediolanum, verme criminale Massimo Doris di mega ricicla soldi assassin= i Banca Mediolanum, verme criminale Edoardo Lombardi di mega ricicla soldi = assassini Banca Mediolanum, verme criminale Ettore Parlato Spadafora di meg= a ricicla soldi assassini Banca Mediolanum, verme criminale Luigi Del Fabbr= o di mega ricicla soldi assassini Banca Mediolanum, verme criminale Annalis= a Sara Doris di mega ricicla soldi assassini Banca Mediolanum, verme crimin= ale Luigi Berlusconi di mega ricicla soldi assassini Banca Mediolanum, verm= e criminale Bruno Bianchi di mega ricicla soldi assassini Banca Mediolanum,= verme criminale Paolo Gualtieri di mega ricicla soldi assassini Banca Medi= olanum ( indagato al momento da mille procure per maree di pesantissimi rea= ti finananziari), verme criminale Angelo Renoldi di mega ricicla soldi assa= ssini Banca Mediolanum, verme criminale Carlos Javier Tusquets di mega rici= cla soldi assassini Banca Mediolanum, verme criminale Francesca Meneghel di= mega ricicla soldi assassini Mediaset, verme criminale Adriano Alberto Ang= eli di mega ricicla soldi assassini Banca Mediolanum, verme criminale Marco= Giuliani di mega ricicla soldi assassini Banca Mediolanum, verme criminale= Gianluca Bosisio di mega ricicla soldi assassini Banca Mediolanum, verme c= riminale Angelo Lietti di mega ricicla soldi assassini Banca Mediolanum, ve= rme criminale Luca Maria Rovere di mega ricicla soldi assassini Banca Medio= lanum, verme criminale Carlo Secchi di mega ricicla soldi assassini Banca M= ediolanum e verme criminale Oscar di Montigny di mega ricicla soldi assassi= ni Banca Mediolanum, verme criminale Giuliano Adreani di mega ricicla soldi= assassini Mediaset, verme criminale Franco Bruni di mega ricicla soldi ass= assini Mediaset, verme criminale Mauro Crippa di mega ricicla soldi assassi= ni Mediaset, verme criminale Bruno Ermolli di mega ricicla soldi assassini = Mediaset, verme criminale Fernando Napolitano di mega ricicla soldi assassi= ni Mediaset, "vermona, zoccolona, bagasciona" criminale Gina Nieri di mega = ricicla soldi assassini Mediaset, verme criminale Marco Giordani di mega ri= cicla soldi assassini Mediaset, verme criminale Niccol=C3=B2 Querci di mega= ricicla soldi assassini Mediaset, verme criminale Stefano Sala di mega ric= icla soldi assassini Mediaset, verme criminale Carlo Secchi di mega ricicla= soldi assassini Mediaset, verme criminale Ubaldo Livolsi di mega ricicla s= oldi assassini Fininvest (gia' condannato al carcere), verme criminale Robe= rto Poli di mega ricicla soldi assassini Fininvest, verme criminale Salvato= re Sciascia di mega ricicla soldi assassini Fininvest (questi altri, invece= , in Fininvest, alias, ^Ma^Fi^a^ninvest), verme criminale Adriano Galliani = di mega ricicla soldi assassini Fininvest ( dittatore per decenni del dopat= issimo, sempre compra partite e compra arbitri, Milan... ahahah... che non = vuole mai nessuno, non per niente.. tanto e' vero che alla fine, il mega ri= cicla soldi killer della Triade, Silvio Berlusconi, ha fatto finta di molla= rlo alla Triade stessa), verme criminale Giuseppe Sabato di mega ricicla so= ldi assassini Banca Esperia, verme criminale Andrea Cingoli di mega ricicla= soldi assassini Banca Esperia, verme criminale Vittorio Volpi di mega rici= cla soldi assassini Banca Esperia e verme criminale Edoardo Lombardi di meg= a ricicla soldi assassini Banca Esperia ( questi altri ancora, in nazimafio= sissima Banca Esperia). I VERMI NAZISTI, LADRI, TRUFFATORI, MAFIOSI, CORROTTI E CORRUTTORI, LAVA SO= LDI MAFIOSI, STRAGISTI, PEDOFILI MATTEO SALVINI, ENNIO DORIS E SILVIO BERLU= SCONI (PER SEMPRE FUORI DAI COG.IONI) HAN CHIESTO (DICIAMO "CHIESTO SMAZZET= TANDO") A GOOGLE DI DIMINUIRE LO SPAZIO DEDICATO AI COMMENTI, QUI, IN QUANT= O BEN SANNO CHE SCRIVIAMO ASSOLUTE VERITA', CHE OVVIAMENTE, LI IMBARAZZANO = IMMENSAMEN TE. PIU' USAN QUESTI METODI HITLERIANI E RIININESI ( OSSIA BERLU= SCONIANISSIMI), METODI ASSASSINI DI DEMOCRAZIA, GIUSTIZIA E LIBERTA', PIU' = CI SCATENEREMO A SCRIVERE "67 ORE AL GIORNO, 40 GIORNI AL MESE, 400 GIORNI = ALL'ANNO". From newsfish@newsfish Thu Aug 1 00:43:50 2024 X-Received: by 2002:a0c:9b88:: with SMTP id o8-v6mr11844099qve.43.1535842877460; Sat, 01 Sep 2018 16:01:17 -0700 (PDT) X-Received: by 2002:a25:3857:: with SMTP id f84-v6mr247642yba.3.1535842877360; Sat, 01 Sep 2018 16:01:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!2.eu.feeder.erje.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z10-v6no1766578qtb.0!news-out.google.com!k67-v6ni985qte.1!nntp.google.com!z10-v6no1766567qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 1 Sep 2018 16:01:17 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.72.89.229; posting-account=DKCk5AoAAADuTmBz3NxXwr7PwEqi12YT NNTP-Posting-Host: 62.72.89.229 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5fc533c7-57ad-4ef1-a416-9f55bf2c9711@googlegroups.com> Subject: generate VHDL testbench from requirements From: Bobby Injection-Date: Sat, 01 Sep 2018 23:01:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 25 Xref: reader02.eternal-september.org comp.lang.vhdl:9352 Hi I have a very simple VHDL as my DUT (device under test). I would like to g= enerate a VHDL test bench for this DUT based on the 'requirements'. I wrote= its (DUT) functions in simple text as 'requirements' . Now through the h= elp of my grammar, I can give the requirement input to my grammar to gener= ate a parser in Java or Python.=20 Questions: =20 (1) Considering my end goal, i.e. to generate VHDL TB, =20 a java parser would be better or python ?=20 (2) Given the generated python parser from grammar,=20 will any kind of python scripting will help me to generate=20 the testbench in VHDL for my DUT ? My confusion at this point=20 is that most of all the literature I am reading=20 suggests linguistic techniques. Any non-linguistic technique ?=20 (3) Any technique to go on further with java parser ?=20 Looking forward for suggestions :-) From newsfish@newsfish Thu Aug 1 00:43:50 2024 X-Received: by 2002:a0c:c930:: with SMTP id r45-v6mr17358463qvj.47.1536055385184; Tue, 04 Sep 2018 03:03:05 -0700 (PDT) X-Received: by 2002:a25:d10a:: with SMTP id i10-v6mr249749ybg.0.1536055385065; Tue, 04 Sep 2018 03:03:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z10-v6no2541430qtb.0!news-out.google.com!i36-v6ni1450qti.0!nntp.google.com!z10-v6no2541428qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Sep 2018 03:03:04 -0700 (PDT) In-Reply-To: <5fc533c7-57ad-4ef1-a416-9f55bf2c9711@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <5fc533c7-57ad-4ef1-a416-9f55bf2c9711@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <57ebb662-10a0-4943-801f-3364153dd9af@googlegroups.com> Subject: Re: generate VHDL testbench from requirements From: Thomas Stanka Injection-Date: Tue, 04 Sep 2018 10:03:05 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 31 Xref: reader02.eternal-september.org comp.lang.vhdl:9353 Am Sonntag, 2. September 2018 01:01:19 UTC+2 schrieb Bobby: > I have a very simple VHDL as my DUT (device under test). I would like to = generate a VHDL test bench for this DUT based on the 'requirements'. I wro= te its (DUT) functions in simple text as 'requirements' . Now through the= help of my grammar, I can give the requirement input to my grammar to gen= erate a parser in Java or Python.=20 >=20 > Questions: =20 >=20 > (1) Considering my end goal, i.e. to generate VHDL TB, =20 > a java parser would be better or python ?=20 >=20 > (2) Given the generated python parser from grammar,=20 > will any kind of python scripting will help me to generate=20 > the testbench in VHDL for my DUT ? My confusion at this point=20 > is that most of all the literature I am reading=20 > suggests linguistic techniques. Any non-linguistic technique ?=20 For writing a parser I would prefer python over java, but in the end take t= he one you think will provide best results from you.=20 The more interessting point is converting requirements in a testbench. Even if you formulated your requirements biunique so parsing will lead to c= orrect "understanding", I feel it very hard to formulate general testbench = structures. Maybe it is possible to convert them in assertions, but ensurin= g a testcase is triggering an assertion is farm from beeing simple unless y= ou have a very specific set of assertions (eg. trigger A leads to response = B within C clock cycles). regards, Thomas From newsfish@newsfish Thu Aug 1 00:43:50 2024 X-Received: by 2002:a37:1f92:: with SMTP id n18-v6mr17770216qkh.16.1536082937111; Tue, 04 Sep 2018 10:42:17 -0700 (PDT) X-Received: by 2002:a25:4151:: with SMTP id o78-v6mr393786yba.4.1536082936901; Tue, 04 Sep 2018 10:42:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsreader4.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!z10-v6no2663933qtb.0!news-out.google.com!i36-v6ni1507qti.0!nntp.google.com!z10-v6no2663931qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Sep 2018 10:42:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.62.223.243; posting-account=km0guAoAAAAXEWJpKf0MvWFtFuBHA6hz NNTP-Posting-Host: 193.62.223.243 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> Subject: automatic indexing for bus assembly in VHDL From: "glenn.christian@gmail.com" Injection-Date: Tue, 04 Sep 2018 17:42:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4686 X-Received-Body-CRC: 4007899502 Xref: reader02.eternal-september.org comp.lang.vhdl:9354 Hi, I am trying to find a way in VHDL of assigning arbitrary length signals to = a bus, and programmatically assigning the bus indices for these signals. A = very simple example is given below, where I am manually assigning the three= differing length signals to one bus: ***************************************************************** library ieee; use ieee.std_logic_1164.all; entity bus_top is=20 port ( bus_out : out std_logic_vector(5 downto 0) ); end bus_top; architecture rtl of bus_top is signal b : std_logic_vector(2 downto 0) :=3D "101"; signal c : std_logic_vector(1 downto 0) :=3D "11"; signal d : std_logic_vector(0 downto 0) :=3D "0"; begin -- Bus assembly ---- bus_out(0) <=3D b(0); bus_out(1) <=3D b(1); bus_out(2) <=3D b(2); bus_out(3) <=3D c(0); bus_out(4) <=3D c(1); bus_out(5) <=3D d(0); =20 end rtl; **************************************************************** This simulates and synthesises as expected, to a constantly driven "011101"= output. Of course my real application is much more complicated than this, = and involves assembling many more signals, of differing lengths, on to the = bus, and I do not want to have to manually change all the indices, when the= size of one of the signals changes. I would like to find a way to automati= cally provide the bus indices using, for example, the signal's 'length attr= ibutes, in a similar way to the following: **************************************************************** library ieee; use ieee.std_logic_1164.all; entity bus_top is=20 port ( bus_out : out std_logic_vector(5 downto 0) ); end bus_top; architecture rtl of bus_top is signal b : std_logic_vector(2 downto 0) :=3D "101"; signal c : std_logic_vector(1 downto 0) :=3D "11"; signal d : std_logic_vector(0 downto 0) :=3D "0"; begin -- Bus assembly ---- bus_assemble: process (b,c,d) variable bus_ind : integer :=3D 0; begin bus_out <=3D (others =3D> '0'); -- avoids latch inference bus_out(bus_ind+b'length-1 downto bus_ind) <=3D b; bus_ind :=3D bus_ind + b'length; bus_out(bus_ind+c'length-1 downto bus_ind) <=3D c; bus_ind :=3D bus_ind + c'length; bus_out(bus_ind+d'length-1 downto bus_ind) <=3D d; end process; =20 end rtl; **************************************************************** Note the above code is not the correct solution as, although it appears to = simulate correctly, the logic being sythesised is far more complex with man= y LUTs being inferred for what is just a static assignment. I feel it must = be possible in VHDL to do this such that the synthesis tool will 'unroll' t= he statements in the same way as in the first example, eg for the indices t= o be calculated by the tools at compile-time rather than on the FPGA at run= -time. This would require that the signals are assigned sequentially, and s= ome way to keep track of the previous value of the bus index, but I have no= t been able to find the right construct for this: I have looked at processe= s (as above), regular loops, generate loops, functions and procedures. Can = anyone shed some light on how to do this? I am aware there are other ways t= o achieve similar results, such as simple concatenation, or using a higher = level programming language to automatically generate/annotate the VHDL, but= I would like to understand how to do this in the manner above. Many thanks for your help, Glenn. From newsfish@newsfish Thu Aug 1 00:43:51 2024 X-Received: by 2002:ac8:838:: with SMTP id u53-v6mr18554306qth.16.1536093334025; Tue, 04 Sep 2018 13:35:34 -0700 (PDT) X-Received: by 2002:a25:ba44:: with SMTP id z4-v6mr400096ybj.7.1536093333624; Tue, 04 Sep 2018 13:35:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.fr7!futter-mich.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!z10-v6no2714625qtb.0!news-out.google.com!i36-v6ni1538qti.0!nntp.google.com!z10-v6no2714620qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Sep 2018 13:35:33 -0700 (PDT) In-Reply-To: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=207.242.234.14; posting-account=w728HAoAAAAF2xrMb6mkfbhZUlYwqJjV NNTP-Posting-Host: 207.242.234.14 References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: automatic indexing for bus assembly in VHDL From: KKoorndyk Injection-Date: Tue, 04 Sep 2018 20:35:33 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5648 X-Received-Body-CRC: 3416587690 Xref: reader02.eternal-september.org comp.lang.vhdl:9355 On Tuesday, September 4, 2018 at 1:42:19 PM UTC-4, glenn.c...@gmail.com wro= te: > Hi, >=20 > I am trying to find a way in VHDL of assigning arbitrary length signals t= o a bus, and programmatically assigning the bus indices for these signals. = A very simple example is given below, where I am manually assigning the thr= ee differing length signals to one bus: > ***************************************************************** > library ieee; > use ieee.std_logic_1164.all; >=20 > entity bus_top is=20 > port ( > bus_out : out std_logic_vector(5 downto 0) > ); > end bus_top; >=20 > architecture rtl of bus_top is >=20 > signal b : std_logic_vector(2 downto 0) :=3D "101"; > signal c : std_logic_vector(1 downto 0) :=3D "11"; > signal d : std_logic_vector(0 downto 0) :=3D "0"; >=20 > begin > -- Bus assembly ---- > bus_out(0) <=3D b(0); > bus_out(1) <=3D b(1); > bus_out(2) <=3D b(2); > bus_out(3) <=3D c(0); > bus_out(4) <=3D c(1); > bus_out(5) <=3D d(0); > =20 > end rtl; > **************************************************************** >=20 > This simulates and synthesises as expected, to a constantly driven "01110= 1" output. Of course my real application is much more complicated than this= , and involves assembling many more signals, of differing lengths, on to th= e bus, and I do not want to have to manually change all the indices, when t= he size of one of the signals changes. I would like to find a way to automa= tically provide the bus indices using, for example, the signal's 'length at= tributes, in a similar way to the following: >=20 > **************************************************************** > library ieee; > use ieee.std_logic_1164.all; >=20 > entity bus_top is=20 > port ( > bus_out : out std_logic_vector(5 downto 0) > ); > end bus_top; >=20 > architecture rtl of bus_top is >=20 > signal b : std_logic_vector(2 downto 0) :=3D "101"; > signal c : std_logic_vector(1 downto 0) :=3D "11"; > signal d : std_logic_vector(0 downto 0) :=3D "0"; >=20 > begin > -- Bus assembly ---- > bus_assemble: process (b,c,d) > variable bus_ind : integer :=3D 0; > begin > bus_out <=3D (others =3D> '0'); -- avoids latch inference > bus_out(bus_ind+b'length-1 downto bus_ind) <=3D b; > bus_ind :=3D bus_ind + b'length; > bus_out(bus_ind+c'length-1 downto bus_ind) <=3D c; > bus_ind :=3D bus_ind + c'length; > bus_out(bus_ind+d'length-1 downto bus_ind) <=3D d; > end process; > =20 > end rtl; > **************************************************************** > Note the above code is not the correct solution as, although it appears t= o simulate correctly, the logic being sythesised is far more complex with m= any LUTs being inferred for what is just a static assignment. I feel it mus= t be possible in VHDL to do this such that the synthesis tool will 'unroll'= the statements in the same way as in the first example, eg for the indices= to be calculated by the tools at compile-time rather than on the FPGA at r= un-time. This would require that the signals are assigned sequentially, and= some way to keep track of the previous value of the bus index, but I have = not been able to find the right construct for this: I have looked at proces= ses (as above), regular loops, generate loops, functions and procedures. Ca= n anyone shed some light on how to do this? I am aware there are other ways= to achieve similar results, such as simple concatenation, or using a highe= r level programming language to automatically generate/annotate the VHDL, b= ut I would like to understand how to do this in the manner above. >=20 > Many thanks for your help, >=20 > Glenn. Do you have a copy of The Designer's Guide to VHDL by Peter Ashenden? It's= the "VHDL Bible". In the 3rd Edition, refer to section 4.1.3 Array Attrib= utes. I haven't done exactly what you're looking for, but I regularly use 'length= attribute to reduce the amount of code that needs to be updated or rewritt= en when an array width (or length) changes, such as a data bus. To make my= code more reusable, it's pretty standard to use a Generic to define the bu= s width and then it just cascades through the rest of the module design wit= hout any additional intervention. From newsfish@newsfish Thu Aug 1 00:43:51 2024 X-Received: by 2002:a37:4d4a:: with SMTP id a71-v6mr18269717qkb.18.1536100930199; Tue, 04 Sep 2018 15:42:10 -0700 (PDT) X-Received: by 2002:a25:76cf:: with SMTP id r198-v6mr112212ybc.5.1536100930040; Tue, 04 Sep 2018 15:42:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!z10-v6no18373qtb.0!news-out.google.com!i36-v6ni15qti.0!nntp.google.com!z10-v6no18371qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Sep 2018 15:42:09 -0700 (PDT) In-Reply-To: <57ebb662-10a0-4943-801f-3364153dd9af@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.72.89.229; posting-account=DKCk5AoAAADuTmBz3NxXwr7PwEqi12YT NNTP-Posting-Host: 62.72.89.229 References: <5fc533c7-57ad-4ef1-a416-9f55bf2c9711@googlegroups.com> <57ebb662-10a0-4943-801f-3364153dd9af@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0b979a1d-b42a-4b4f-817f-8812abc2ace7@googlegroups.com> Subject: Re: generate VHDL testbench from requirements From: Bobby Injection-Date: Tue, 04 Sep 2018 22:42:10 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 47 Xref: reader02.eternal-september.org comp.lang.vhdl:9356 Hi Thomas Though I discussed these questions verbally with some colleagues, but so fa= r the most reasonable reply I got is from you. Thanks ! your points make se= nse..... I also thought on these points i.e. 'assertions'. May be System Ve= rilog assertions can also be considered. I would really be interested to know why you consider python better than ja= va for writing parser ?=20 On Tuesday, September 4, 2018 at 12:03:06 PM UTC+2, Thomas Stanka wrote: > Am Sonntag, 2. September 2018 01:01:19 UTC+2 schrieb Bobby: > > I have a very simple VHDL as my DUT (device under test). I would like t= o generate a VHDL test bench for this DUT based on the 'requirements'. I w= rote its (DUT) functions in simple text as 'requirements' . Now through t= he help of my grammar, I can give the requirement input to my grammar to g= enerate a parser in Java or Python.=20 > >=20 > > Questions: =20 > >=20 > > (1) Considering my end goal, i.e. to generate VHDL TB, =20 > > a java parser would be better or python ?=20 > >=20 > > (2) Given the generated python parser from grammar,=20 > > will any kind of python scripting will help me to generate=20 > > the testbench in VHDL for my DUT ? My confusion at this point= =20 > > is that most of all the literature I am reading=20 > > suggests linguistic techniques. Any non-linguistic technique ?= =20 >=20 > For writing a parser I would prefer python over java, but in the end take= the one you think will provide best results from you.=20 >=20 > The more interessting point is converting requirements in a testbench. > Even if you formulated your requirements biunique so parsing will lead to= correct "understanding", I feel it very hard to formulate general testbenc= h structures. Maybe it is possible to convert them in assertions, but ensur= ing a testcase is triggering an assertion is farm from beeing simple unless= you have a very specific set of assertions (eg. trigger A leads to respons= e B within C clock cycles). >=20 > regards, >=20 > Thomas From newsfish@newsfish Thu Aug 1 00:43:51 2024 X-Received: by 2002:a0c:d921:: with SMTP id p30-v6mr20096167qvj.7.1536169139352; Wed, 05 Sep 2018 10:38:59 -0700 (PDT) X-Received: by 2002:a25:3857:: with SMTP id f84-v6mr446399yba.3.1536169139083; Wed, 05 Sep 2018 10:38:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder4.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z10-v6no295078qtb.0!news-out.google.com!i36-v6ni196qti.0!nntp.google.com!z10-v6no295077qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Sep 2018 10:38:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.62.223.243; posting-account=km0guAoAAAAXEWJpKf0MvWFtFuBHA6hz NNTP-Posting-Host: 193.62.223.243 References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <25ee64cd-90bd-45e8-82f5-def139e1c801@googlegroups.com> Subject: Re: automatic indexing for bus assembly in VHDL From: glennchid Injection-Date: Wed, 05 Sep 2018 17:38:59 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 158 Xref: reader02.eternal-september.org comp.lang.vhdl:9357 On Tuesday, September 4, 2018 at 9:35:35 PM UTC+1, KKoorndyk wrote: > On Tuesday, September 4, 2018 at 1:42:19 PM UTC-4, glenn.c...@gmail.com w= rote: > > Hi, > >=20 > > I am trying to find a way in VHDL of assigning arbitrary length signals= to a bus, and programmatically assigning the bus indices for these signals= . A very simple example is given below, where I am manually assigning the t= hree differing length signals to one bus: > > ***************************************************************** > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity bus_top is=20 > > port ( > > bus_out : out std_logic_vector(5 downto 0) > > ); > > end bus_top; > >=20 > > architecture rtl of bus_top is > >=20 > > signal b : std_logic_vector(2 downto 0) :=3D "101"; > > signal c : std_logic_vector(1 downto 0) :=3D "11"; > > signal d : std_logic_vector(0 downto 0) :=3D "0"; > >=20 > > begin > > -- Bus assembly ---- > > bus_out(0) <=3D b(0); > > bus_out(1) <=3D b(1); > > bus_out(2) <=3D b(2); > > bus_out(3) <=3D c(0); > > bus_out(4) <=3D c(1); > > bus_out(5) <=3D d(0); > > =20 > > end rtl; > > **************************************************************** > >=20 > > This simulates and synthesises as expected, to a constantly driven "011= 101" output. Of course my real application is much more complicated than th= is, and involves assembling many more signals, of differing lengths, on to = the bus, and I do not want to have to manually change all the indices, when= the size of one of the signals changes. I would like to find a way to auto= matically provide the bus indices using, for example, the signal's 'length = attributes, in a similar way to the following: > >=20 > > **************************************************************** > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity bus_top is=20 > > port ( > > bus_out : out std_logic_vector(5 downto 0) > > ); > > end bus_top; > >=20 > > architecture rtl of bus_top is > >=20 > > signal b : std_logic_vector(2 downto 0) :=3D "101"; > > signal c : std_logic_vector(1 downto 0) :=3D "11"; > > signal d : std_logic_vector(0 downto 0) :=3D "0"; > >=20 > > begin > > -- Bus assembly ---- > > bus_assemble: process (b,c,d) > > variable bus_ind : integer :=3D 0; > > begin > > bus_out <=3D (others =3D> '0'); -- avoids latch inference > > bus_out(bus_ind+b'length-1 downto bus_ind) <=3D b; > > bus_ind :=3D bus_ind + b'length; > > bus_out(bus_ind+c'length-1 downto bus_ind) <=3D c; > > bus_ind :=3D bus_ind + c'length; > > bus_out(bus_ind+d'length-1 downto bus_ind) <=3D d; > > end process; > > =20 > > end rtl; > > **************************************************************** > > Note the above code is not the correct solution as, although it appears= to simulate correctly, the logic being sythesised is far more complex with= many LUTs being inferred for what is just a static assignment. I feel it m= ust be possible in VHDL to do this such that the synthesis tool will 'unrol= l' the statements in the same way as in the first example, eg for the indic= es to be calculated by the tools at compile-time rather than on the FPGA at= run-time. This would require that the signals are assigned sequentially, a= nd some way to keep track of the previous value of the bus index, but I hav= e not been able to find the right construct for this: I have looked at proc= esses (as above), regular loops, generate loops, functions and procedures. = Can anyone shed some light on how to do this? I am aware there are other wa= ys to achieve similar results, such as simple concatenation, or using a hig= her level programming language to automatically generate/annotate the VHDL,= but I would like to understand how to do this in the manner above. > >=20 > > Many thanks for your help, > >=20 > > Glenn. >=20 > Do you have a copy of The Designer's Guide to VHDL by Peter Ashenden? It= 's the "VHDL Bible". In the 3rd Edition, refer to section 4.1.3 Array Attr= ibutes. >=20 > I haven't done exactly what you're looking for, but I regularly use 'leng= th attribute to reduce the amount of code that needs to be updated or rewri= tten when an array width (or length) changes, such as a data bus. To make = my code more reusable, it's pretty standard to use a Generic to define the = bus width and then it just cascades through the rest of the module design w= ithout any additional intervention. Thanks for the reply. Yes, I do have a copy of Ashenden, and I can see that= attributes are generally very useful - I just mentioned them as an example= in my original post though. I suspect my problem is due to the synthesis tool (Vivado in this case) fai= ling to recognise that the assignments to the bus are actually static (as i= n my first example) and inferring logic for this. No doubt this is not help= ed by my use of a variable to keep track of the index value, and the combin= atorial process.=20 In the end I managed to achieve what I wanted, at least for this simple exa= mple case, using a procedure: ***************************************************************** library ieee; use ieee.std_logic_1164.all; entity bus_top is=20 port ( bus_out : out std_logic_vector(9 downto 0) :=3D (others =3D> '0') ); end bus_top; architecture rtl of bus_top is signal b : std_logic_vector(2 downto 0) :=3D "101"; signal c : std_logic_vector(1 downto 0) :=3D "11"; signal d : std_logic_vector(0 downto 0) :=3D "0"; procedure bus_assemble ( x, y, z : std_logic_vector; signal outbus : out st= d_logic_vector) is variable bus_ind : integer :=3D 0; begin outbus(bus_ind+x'length-1 downto bus_ind) <=3D x; bus_ind :=3D bus_ind + x'length; outbus(bus_ind+y'length-1 downto bus_ind) <=3D y; bus_ind :=3D bus_ind + y'length; outbus(bus_ind+z'length-1 downto bus_ind) <=3D z; end bus_assemble; begin -- Bus assembly ---- bus_assemble ( b, c, d, bus_out); end rtl; ****************************************************************** Unfortunately, though, this will not help in the general case where I have = an arbitrary number of signals to concatenate onto the bus, unless there is= a way to collect together multiple vectors of differing lengths in kind of= array ... I suspect I will just have to use the regular concatenation operator, and c= alculate the necessary size of the bus by adding together the lengths of th= e individual signals. Thanks again for you help. From newsfish@newsfish Thu Aug 1 00:43:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: automatic indexing for bus assembly in VHDL Date: Wed, 5 Sep 2018 11:48:43 -0700 Organization: A noiseless patient Spider Lines: 348 Message-ID: References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> <25ee64cd-90bd-45e8-82f5-def139e1c801@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: base64 Injection-Date: Wed, 5 Sep 2018 18:48:45 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="2089461f79da0e023819e8f2bbc4b0b2"; logging-data="22667"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+WTha/cs4A6UfnDbdkfzjN" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 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id j4-v6mr945333qkd.9.1536241299993; Thu, 06 Sep 2018 06:41:39 -0700 (PDT) X-Received: by 2002:a25:d10a:: with SMTP id i10-v6mr30260ybg.0.1536241299814; Thu, 06 Sep 2018 06:41:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!z10-v6no580002qtb.0!news-out.google.com!k67-v6ni322qte.1!nntp.google.com!z10-v6no579996qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Sep 2018 06:41:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.62.223.243; posting-account=km0guAoAAAAXEWJpKf0MvWFtFuBHA6hz NNTP-Posting-Host: 193.62.223.243 References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> <25ee64cd-90bd-45e8-82f5-def139e1c801@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c268935-2232-416e-8bb1-48c7779843d0@googlegroups.com> Subject: Re: automatic indexing for bus assembly in VHDL From: glennchid Injection-Date: Thu, 06 Sep 2018 13:41:39 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9359 On Wednesday, September 5, 2018 at 7:48:47 PM UTC+1, Rob Gaddi wrote: > On 09/05/2018 10:38 AM, glennchid wrote: > > On Tuesday, September 4, 2018 at 9:35:35 PM UTC+1, KKoorndyk wrote: > >> On Tuesday, September 4, 2018 at 1:42:19 PM UTC-4, glenn.c...@gmail.co= m wrote: > >>> Hi, > >>> > >>> I am trying to find a way in VHDL of assigning arbitrary length signa= ls to a bus, and programmatically assigning the bus indices for these signa= ls. A very simple example is given below, where I am manually assigning the= three differing length signals to one bus: > >>> ***************************************************************** > >>> library ieee; > >>> use ieee.std_logic_1164.all; > >>> > >>> entity bus_top is > >>> port ( > >>> bus_out : out std_logic_vector(5 downto 0) > >>> ); > >>> end bus_top; > >>> > >>> architecture rtl of bus_top is > >>> > >>> signal b : std_logic_vector(2 downto 0) :=3D "101"; > >>> signal c : std_logic_vector(1 downto 0) :=3D "11"; > >>> signal d : std_logic_vector(0 downto 0) :=3D "0"; > >>> > >>> begin > >>> -- Bus assembly ---- > >>> bus_out(0) <=3D b(0); > >>> bus_out(1) <=3D b(1); > >>> bus_out(2) <=3D b(2); > >>> bus_out(3) <=3D c(0); > >>> bus_out(4) <=3D c(1); > >>> bus_out(5) <=3D d(0); > >>> =20 > >>> end rtl; > >>> **************************************************************** > >>> > >>> This simulates and synthesises as expected, to a constantly driven "0= 11101" output. Of course my real application is much more complicated than = this, and involves assembling many more signals, of differing lengths, on t= o the bus, and I do not want to have to manually change all the indices, wh= en the size of one of the signals changes. I would like to find a way to au= tomatically provide the bus indices using, for example, the signal's 'lengt= h attributes, in a similar way to the following: > >>> > >>> **************************************************************** > >>> library ieee; > >>> use ieee.std_logic_1164.all; > >>> > >>> entity bus_top is > >>> port ( > >>> bus_out : out std_logic_vector(5 downto 0) > >>> ); > >>> end bus_top; > >>> > >>> architecture rtl of bus_top is > >>> > >>> signal b : std_logic_vector(2 downto 0) :=3D "101"; > >>> signal c : std_logic_vector(1 downto 0) :=3D "11"; > >>> signal d : std_logic_vector(0 downto 0) :=3D "0"; > >>> > >>> begin > >>> -- Bus assembly ---- > >>> bus_assemble: process (b,c,d) > >>> variable bus_ind : integer :=3D 0; > >>> begin > >>> bus_out <=3D (others =3D> '0'); -- avoids latch inference > >>> bus_out(bus_ind+b'length-1 downto bus_ind) <=3D b; > >>> bus_ind :=3D bus_ind + b'length; > >>> bus_out(bus_ind+c'length-1 downto bus_ind) <=3D c; > >>> bus_ind :=3D bus_ind + c'length; > >>> bus_out(bus_ind+d'length-1 downto bus_ind) <=3D d; > >>> end process; > >>> =20 > >>> end rtl; > >>> **************************************************************** > >>> Note the above code is not the correct solution as, although it appea= rs to simulate correctly, the logic being sythesised is far more complex wi= th many LUTs being inferred for what is just a static assignment. I feel it= must be possible in VHDL to do this such that the synthesis tool will 'unr= oll' the statements in the same way as in the first example, eg for the ind= ices to be calculated by the tools at compile-time rather than on the FPGA = at run-time. This would require that the signals are assigned sequentially,= and some way to keep track of the previous value of the bus index, but I h= ave not been able to find the right construct for this: I have looked at pr= ocesses (as above), regular loops, generate loops, functions and procedures= . Can anyone shed some light on how to do this? I am aware there are other = ways to achieve similar results, such as simple concatenation, or using a h= igher level programming language to automatically generate/annotate the VHD= L, but I would like to understand how to do this in the manner above. > >>> > >>> Many thanks for your help, > >>> > >>> Glenn. > >> > >> Do you have a copy of The Designer's Guide to VHDL by Peter Ashenden? = It's the "VHDL Bible". In the 3rd Edition, refer to section 4.1.3 Array A= ttributes. > >> > >> I haven't done exactly what you're looking for, but I regularly use 'l= ength attribute to reduce the amount of code that needs to be updated or re= written when an array width (or length) changes, such as a data bus. To ma= ke my code more reusable, it's pretty standard to use a Generic to define t= he bus width and then it just cascades through the rest of the module desig= n without any additional intervention. > >=20 > > Thanks for the reply. Yes, I do have a copy of Ashenden, and I can see = that attributes are generally very useful - I just mentioned them as an exa= mple in my original post though. > >=20 > > I suspect my problem is due to the synthesis tool (Vivado in this case)= failing to recognise that the assignments to the bus are actually static (= as in my first example) and inferring logic for this. No doubt this is not = helped by my use of a variable to keep track of the index value, and the co= mbinatorial process. > >=20 > > In the end I managed to achieve what I wanted, at least for this simple= example case, using a procedure: > > ***************************************************************** > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity bus_top is > > port ( > > bus_out : out std_logic_vector(9 downto 0) :=3D (others =3D> '0') > > ); > > end bus_top; > >=20 > > architecture rtl of bus_top is > >=20 > > signal b : std_logic_vector(2 downto 0) :=3D "101"; > > signal c : std_logic_vector(1 downto 0) :=3D "11"; > > signal d : std_logic_vector(0 downto 0) :=3D "0"; > >=20 > > procedure bus_assemble ( x, y, z : std_logic_vector; signal outbus : ou= t std_logic_vector) is > > variable bus_ind : integer :=3D 0; > > begin > > outbus(bus_ind+x'length-1 downto bus_ind) <=3D x; > > bus_ind :=3D bus_ind + x'length; > > outbus(bus_ind+y'length-1 downto bus_ind) <=3D y; > > bus_ind :=3D bus_ind + y'length; > > outbus(bus_ind+z'length-1 downto bus_ind) <=3D z; > > end bus_assemble; > >=20 > > begin > > -- Bus assembly ---- > > bus_assemble ( b, c, d, bus_out); > > end rtl; > > ****************************************************************** > > Unfortunately, though, this will not help in the general case where I h= ave an arbitrary number of signals to concatenate onto the bus, unless ther= e is a way to collect together multiple vectors of differing lengths in kin= d of array ... > > I suspect I will just have to use the regular concatenation operator, a= nd calculate the necessary size of the bus by adding together the lengths o= f the individual signals. > >=20 > > Thanks again for you help. > >=20 >=20 > I can't think of anything to help the general case; you can't really=20 > iterate over "ragged arrays" in VHDL, because there isn't really a=20 > concept of such. VHDL-2018 will let you iterate over record types, but= =20 > that doesn't help you right now. >=20 > One thing I tend to do fairly often is to create record types for my=20 > structured data and create custom pack/unpack functions that turn the=20 > entire record into std_logic_vector and back. To build up those=20 > pack/unpacks, I use the following code; which I freely invite you or=20 > anyone else to have at: >=20 > --- >=20 > -------------------------------------------------------------------------= ------ >=20 > -- Title : Useful Standard Functions Library >=20 > -------------------------------------------------------------------------= ------ >=20 > -- File : standard_functions.vhd >=20 > -- Author : Rob Gaddi >=20 > -- Company : Highland Technology, Inc. >=20 > -- Created : 14-Feb-2012 >=20 > -- Last update: 14-Feb-2012 >=20 > -- Platform : Independent >=20 > -- Standard : VHDL 93 - 08 >=20 > -------------------------------------------------------------------------= ------ >=20 > -- Description: Useful standard functions. >=20 > -------------------------------------------------------------------------= ------ >=20 > -- Revision History: >=20 > -------------------------------------------------------------------------= ------ >=20 >=20 >=20 > library ieee; >=20 > use ieee.std_logic_1164.all; >=20 > use ieee.numeric_std.all; >=20 >=20 >=20 > package standard_functions is >=20 >=20 >=20 > ---------------------------------------------------------------------= -- >=20 > -- Base 2 Logarithms > --------------------------------------------------------------------= --- >=20 >=20 >=20 > --! ceil(log2(x)) >=20 > --! This is also the number of bits required to represent >=20 > --! x possible choices. clog2(4) =3D 2, clog2(5) =3D 3 >=20 > pure function clog2(x : in positive) return natural; >=20 >=20 >=20 > --! floor(log2(x)) >=20 > --! This is also the index (with the LSB as bit 0) of the >=20 > --! uppermost 1 bit for a given number represented in >=20 > --! binary. flog2(4) =3D 2, flog2(5) =3D 2 >=20 > pure function flog2(x : in positive) return natural; >=20 >=20 >=20 > --! Number of bits needed to represent a given number in >=20 > --! binary form. nbits(4) =3D 3, nbits(5) =3D 3, nbits(-4) =3D 4 >=20 > pure function nbits(x : in integer) return positive; >=20 >=20 >=20 > --------------------------------------------------------------------= --- >=20 > -- Conversion Functions > --------------------------------------------------------------------= --- >=20 >=20 >=20 > --! Converts an integer straight into a std_logic_vector. >=20 > pure function TO_SLV(data : in integer; bits : in positive) return= =20 > std_logic_vector; >=20 >=20 >=20 > --! Converts a logic value to std_logic using active-high rules. >=20 > pure function POS_LOGIC(x : in boolean) return std_logic; >=20 >=20 >=20 > --! Converts a logic value to std_logic using active-low rules. >=20 > pure function NEG_LOGIC(x : in boolean) return std_logic; >=20 >=20 >=20 > --------------------------------------------------------------------= --- >=20 > -- Record conversion functions > --------------------------------------------------------------------= --- >=20 >=20 >=20 > -- These are useful when having to turn arbitrary data collections >=20 > -- into std_logic_vector, generally for use with IP cores. >=20 > -- >=20 > -- pack is used to line up multiple pieces of data in one >=20 > -- std_logic_vector; using a running variable that will reflect >=20 > -- the index of the LSB of the next data to write. >=20 > -- >=20 > -- unpack is the reverse, pulling data off a vector. >=20 > -- >=20 > -- These shouldn't be used to construct bitfields that will be >=20 > -- made accessible to the outside world; they're really just for >=20 > -- packing things up internally. Generally, you'll composite >=20 > -- these together to make larger functions that turn an entire >=20 > -- record type into and back from a std_logic_vector. >=20 > -- >=20 >=20 >=20 > procedure pack( >=20 > target : inout std_logic_vector; >=20 > idx : inout integer; >=20 > nd : in std_logic_vector >=20 > ); >=20 > procedure pack( >=20 > target : inout std_logic_vector; >=20 > idx : inout integer; >=20 > nd : in std_logic >=20 > ); >=20 > procedure pack( >=20 > target : inout std_logic_vector; >=20 > idx : inout integer; >=20 > nd : in unsigned >=20 > ); >=20 > procedure pack( >=20 > target : inout std_logic_vector; >=20 > idx : inout integer; >=20 > nd : in signed >=20 > ); >=20 >=20 >=20 > procedure unpack ( >=20 > source : in std_logic_vector; >=20 > idx : inout integer; >=20 > dat : out std_logic_vector >=20 > ); >=20 > procedure unpack ( >=20 > source : in std_logic_vector; >=20 > idx : inout integer; >=20 > dat : out std_logic >=20 > ); >=20 > procedure unpack ( >=20 > source : in std_logic_vector; >=20 > idx : inout integer; >=20 > dat : out unsigned >=20 > ); >=20 > procedure unpack ( >=20 > source : in std_logic_vector; >=20 > idx : inout integer; >=20 > dat : out signed >=20 > ); >=20 >=20 >=20 > --------------------------------------------------------------------= --- >=20 > -- Comparison Functions > --------------------------------------------------------------------= --- >=20 >=20 >=20 > --! Performs a "counter comparison", in which only bits expected >=20 > --! to be '1' are actually checked. This is equivalent to a full >=20 > --! equality compare when used on an up-counter, but can take >=20 > --! substantially less logic because bits expected to be zero >=20 > --! aren't checked. For instance, to compare a counter to the >=20 > --! constant value 17 requires only 2 bits to be compared. >=20 > pure function counter_eq(x : in unsigned; constant tgt : in natural) >=20 > return boolean; >=20 >=20 >=20 > pure function counter_eq(x : in natural; constant tgt : in natural) >=20 > return boolean; >=20 >=20 >=20 > end package standard_functions; >=20 >=20 >=20 > package body standard_functions is >=20 >=20 >=20 > --------------------------------------------------------------------= --- >=20 > -- Base 2 Logarithms > --------------------------------------------------------------------= --- >=20 >=20 >=20 > pure function flog2 (x : in positive) return natural is >=20 > variable temp, log: natural; >=20 > begin >=20 > temp :=3D x / 2; >=20 > log :=3D 0; >=20 > while (temp /=3D 0) loop >=20 > temp :=3D temp/2; >=20 > log :=3D log + 1; >=20 > end loop; >=20 > return log; >=20 > end function flog2; >=20 >=20 >=20 > pure function clog2 (x : in positive) return natural is >=20 > begin >=20 > if (x =3D 1) then >=20 > return 1; >=20 > else >=20 > return 1 + flog2(x - 1); >=20 > end if; >=20 > end function clog2; >=20 >=20 >=20 > pure function nbits(x : in integer) return positive is >=20 > begin >=20 > if (x < 0) then >=20 > return 2 + flog2(-x); >=20 > elsif (x =3D 0) then >=20 > return 1; >=20 > else >=20 > return 1 + flog2(x); >=20 > end if; >=20 > end function nbits; >=20 >=20 >=20 > --------------------------------------------------------------------= --- >=20 > -- Conversion Functions > --------------------------------------------------------------------= --- >=20 >=20 >=20 > pure function TO_SLV( data : in integer; >=20 > bits : in positive) >=20 > return std_logic_vector is >=20 > begin >=20 > if (data < 0) then >=20 > return STD_LOGIC_VECTOR(TO_SIGNED(data, bits)); >=20 > else >=20 > return STD_LOGIC_VECTOR(TO_UNSIGNED(data, bits)); >=20 > end if; >=20 > end function TO_SLV; >=20 >=20 >=20 > pure function POS_LOGIC(x : in boolean) return std_logic is >=20 > begin >=20 > if x then >=20 > return '1'; >=20 > else >=20 > return '0'; >=20 > end if; >=20 > end function POS_LOGIC; >=20 >=20 >=20 > --! Converts a logic value to std_logic using active-low rules. >=20 > pure function NEG_LOGIC(x : in boolean) return std_logic is >=20 > begin >=20 > if x then >=20 > return '0'; >=20 > else >=20 > return '1'; >=20 > end if; >=20 > end function NEG_LOGIC; >=20 >=20 >=20 > --------------------------------------------------------------------= --- >=20 > -- Record conversion functions > --------------------------------------------------------------------= --- >=20 >=20 >=20 > procedure pack( >=20 > target : inout std_logic_vector; >=20 > idx : inout integer; >=20 > nd : in std_logic_vector >=20 > ) is >=20 > begin >=20 > target(idx + nd'length - 1 downto idx) :=3D nd; >=20 > idx :=3D idx + nd'length; >=20 > end procedure pack; >=20 >=20 >=20 > procedure pack( >=20 > target : inout std_logic_vector; >=20 > idx : inout integer; >=20 > nd : in std_logic >=20 > ) is >=20 > begin >=20 > target(idx) :=3D nd; >=20 > idx :=3D idx + 1; >=20 > end procedure pack; >=20 >=20 >=20 > procedure pack( >=20 > target : inout std_logic_vector; >=20 > idx : inout integer; >=20 > nd : in unsigned >=20 > ) is >=20 > begin >=20 > target(idx + nd'length - 1 downto idx) :=3D STD_LOGIC_VECTOR(nd)= ; >=20 > idx :=3D idx + nd'length; >=20 > end procedure pack; >=20 >=20 >=20 > procedure pack( >=20 > target : inout std_logic_vector; >=20 > idx : inout integer; >=20 > nd : in signed >=20 > ) is >=20 > begin >=20 > target(idx + nd'length - 1 downto idx) :=3D STD_LOGIC_VECTOR(nd)= ; >=20 > idx :=3D idx + nd'length; >=20 > end procedure pack; >=20 >=20 >=20 > --------------------------------------------------------------------= -- >=20 >=20 >=20 > procedure unpack ( >=20 > source : in std_logic_vector; >=20 > idx : inout integer; >=20 > dat : out std_logic_vector >=20 > ) is >=20 > begin >=20 > dat :=3D source(idx + dat'length - 1 downto idx); >=20 > idx :=3D idx + dat'length; >=20 > end procedure unpack; >=20 >=20 >=20 > procedure unpack ( >=20 > source : in std_logic_vector; >=20 > idx : inout integer; >=20 > dat : out std_logic >=20 > ) is >=20 > begin >=20 > dat :=3D source(idx); >=20 > idx :=3D idx + 1; >=20 > end procedure unpack; >=20 >=20 >=20 > procedure unpack ( >=20 > source : in std_logic_vector; >=20 > idx : inout integer; >=20 > dat : out unsigned >=20 > ) is >=20 > begin >=20 > dat :=3D UNSIGNED(source(idx + dat'length - 1 downto idx)); >=20 > idx :=3D idx + dat'length; >=20 > end procedure unpack; >=20 >=20 >=20 > procedure unpack ( >=20 > source : in std_logic_vector; >=20 > idx : inout integer; >=20 > dat : out signed >=20 > ) is >=20 > begin >=20 > dat :=3D SIGNED(source(idx + dat'length - 1 downto idx)); >=20 > idx :=3D idx + dat'length; >=20 > end procedure unpack; >=20 >=20 >=20 > --------------------------------------------------------------------= --- >=20 > -- Comparison Functions > --------------------------------------------------------------------= --- >=20 >=20 >=20 > pure function counter_eq(x : in unsigned; constant tgt : in natural) >=20 > return boolean is >=20 >=20 >=20 > variable target : unsigned(x'range); >=20 > begin >=20 > target :=3D TO_UNSIGNED(tgt, target'length); >=20 > for i in target'range loop >=20 > if (target(i) =3D '1') and (x(i) /=3D '1') then >=20 > return false; >=20 > end if; >=20 > end loop; >=20 > return true; >=20 > end function counter_eq; >=20 >=20 >=20 > pure function counter_eq(x : in natural; constant tgt : in natural) >=20 > return boolean is >=20 >=20 >=20 > variable counter : unsigned(31 downto 0); >=20 > begin >=20 > counter :=3D TO_UNSIGNED(x, 32); >=20 > return counter_eq(counter, tgt); >=20 > end function counter_eq; >=20 >=20 >=20 > end package body standard_functions; >=20 >=20 >=20 > --=20 > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > Email address domain is currently out of order. See above to fix. Many thanks Rob, the functions look very useful. In fact, your 'pack' proce= dure appears to do exactly what I was originally wanting! It had not occurr= ed to me to define the ports as inout though. The problem though is that th= e synthesis still infers a lot of logic to do this. I suspect the reason fo= r this is that I need to make the procedure calls from within a process, in= order for them to be executed sequentially. Is there another to achieve se= quential execution without using a process block? My new code is below, usi= ng your 'pack' procedure. Maybe you can see some problem with this? *********************************************** library ieee; use ieee.std_logic_1164.all; entity bus_top is=20 port ( bus_out : out std_logic_vector(5 downto 0) :=3D (others =3D> '0') ); end bus_top; architecture rtl of bus_top is signal b : std_logic_vector(2 downto 0) :=3D "101"; signal c : std_logic_vector(1 downto 0) :=3D "11"; signal d : std_logic_vector(0 downto 0) :=3D "0"; procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in std_logic_vector ) is begin target(idx + nd'length - 1 downto idx) :=3D nd; idx :=3D idx + nd'length; end procedure pack; begin =20 BUS_ASSEMBLE : process variable bus_tmp : std_logic_vector(5 downto 0) :=3D (others =3D> '0'); variable idx : integer :=3D 0; begin bus_tmp :=3D (others =3D> '0'); pack (bus_tmp, idx, b); pack (bus_tmp, idx, c); pack (bus_tmp, idx, d); bus_out(bus_tmp'length-1 downto 0) <=3D bus_tmp; wait; end process BUS_ASSEMBLE; =20 end rtl; ************************************************************ From newsfish@newsfish Thu Aug 1 00:43:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: automatic indexing for bus assembly in VHDL Date: Thu, 6 Sep 2018 09:39:57 -0700 Organization: A noiseless patient Spider Lines: 442 Message-ID: References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> <25ee64cd-90bd-45e8-82f5-def139e1c801@googlegroups.com> <7c268935-2232-416e-8bb1-48c7779843d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: base64 Injection-Date: Thu, 6 Sep 2018 16:39:59 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="1bfc5c32e21441109bcd5c1ac04f79a3"; logging-data="11562"; mail-complaints-to="abuse@eternal-september.org"; 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eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z10-v6no650195qtb.0!news-out.google.com!i36-v6ni414qti.0!nntp.google.com!z10-v6no650193qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Sep 2018 11:14:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.62.223.243; posting-account=km0guAoAAAAXEWJpKf0MvWFtFuBHA6hz NNTP-Posting-Host: 193.62.223.243 References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> <25ee64cd-90bd-45e8-82f5-def139e1c801@googlegroups.com> <7c268935-2232-416e-8bb1-48c7779843d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <31e9d39d-4ddd-49db-ba4c-fe1fd254d6f4@googlegroups.com> Subject: Re: automatic indexing for bus assembly in VHDL From: glennchid Injection-Date: Thu, 06 Sep 2018 18:14:50 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 950 Xref: reader02.eternal-september.org comp.lang.vhdl:9361 On Thursday, September 6, 2018 at 5:40:01 PM UTC+1, Rob Gaddi wrote: > On 09/06/2018 06:41 AM, glennchid wrote: > > On Wednesday, September 5, 2018 at 7:48:47 PM UTC+1, Rob Gaddi wrote: > >> On 09/05/2018 10:38 AM, glennchid wrote: > >>> On Tuesday, September 4, 2018 at 9:35:35 PM UTC+1, KKoorndyk wrote: > >>>> On Tuesday, September 4, 2018 at 1:42:19 PM UTC-4, glenn.c...@gmail.= com wrote: > >>>>> Hi, > >>>>> > >>>>> I am trying to find a way in VHDL of assigning arbitrary length sig= nals to a bus, and programmatically assigning the bus indices for these sig= nals. A very simple example is given below, where I am manually assigning t= he three differing length signals to one bus: > >>>>> ***************************************************************** > >>>>> library ieee; > >>>>> use ieee.std_logic_1164.all; > >>>>> > >>>>> entity bus_top is > >>>>> port ( > >>>>> bus_out : out std_logic_vector(5 downto 0) > >>>>> ); > >>>>> end bus_top; > >>>>> > >>>>> architecture rtl of bus_top is > >>>>> > >>>>> signal b : std_logic_vector(2 downto 0) :=3D "101"; > >>>>> signal c : std_logic_vector(1 downto 0) :=3D "11"; > >>>>> signal d : std_logic_vector(0 downto 0) :=3D "0"; > >>>>> > >>>>> begin > >>>>> -- Bus assembly ---- > >>>>> bus_out(0) <=3D b(0); > >>>>> bus_out(1) <=3D b(1); > >>>>> bus_out(2) <=3D b(2); > >>>>> bus_out(3) <=3D c(0); > >>>>> bus_out(4) <=3D c(1); > >>>>> bus_out(5) <=3D d(0); > >>>>> =20 > >>>>> end rtl; > >>>>> **************************************************************** > >>>>> > >>>>> This simulates and synthesises as expected, to a constantly driven = "011101" output. Of course my real application is much more complicated tha= n this, and involves assembling many more signals, of differing lengths, on= to the bus, and I do not want to have to manually change all the indices, = when the size of one of the signals changes. I would like to find a way to = automatically provide the bus indices using, for example, the signal's 'len= gth attributes, in a similar way to the following: > >>>>> > >>>>> **************************************************************** > >>>>> library ieee; > >>>>> use ieee.std_logic_1164.all; > >>>>> > >>>>> entity bus_top is > >>>>> port ( > >>>>> bus_out : out std_logic_vector(5 downto 0) > >>>>> ); > >>>>> end bus_top; > >>>>> > >>>>> architecture rtl of bus_top is > >>>>> > >>>>> signal b : std_logic_vector(2 downto 0) :=3D "101"; > >>>>> signal c : std_logic_vector(1 downto 0) :=3D "11"; > >>>>> signal d : std_logic_vector(0 downto 0) :=3D "0"; > >>>>> > >>>>> begin > >>>>> -- Bus assembly ---- > >>>>> bus_assemble: process (b,c,d) > >>>>> variable bus_ind : integer :=3D 0; > >>>>> begin > >>>>> bus_out <=3D (others =3D> '0'); -- avoids latch inference > >>>>> bus_out(bus_ind+b'length-1 downto bus_ind) <=3D b; > >>>>> bus_ind :=3D bus_ind + b'length; > >>>>> bus_out(bus_ind+c'length-1 downto bus_ind) <=3D c; > >>>>> bus_ind :=3D bus_ind + c'length; > >>>>> bus_out(bus_ind+d'length-1 downto bus_ind) <=3D d; > >>>>> end process; > >>>>> =20 > >>>>> end rtl; > >>>>> **************************************************************** > >>>>> Note the above code is not the correct solution as, although it app= ears to simulate correctly, the logic being sythesised is far more complex = with many LUTs being inferred for what is just a static assignment. I feel = it must be possible in VHDL to do this such that the synthesis tool will 'u= nroll' the statements in the same way as in the first example, eg for the i= ndices to be calculated by the tools at compile-time rather than on the FPG= A at run-time. This would require that the signals are assigned sequentiall= y, and some way to keep track of the previous value of the bus index, but I= have not been able to find the right construct for this: I have looked at = processes (as above), regular loops, generate loops, functions and procedur= es. Can anyone shed some light on how to do this? I am aware there are othe= r ways to achieve similar results, such as simple concatenation, or using a= higher level programming language to automatically generate/annotate the V= HDL, but I would like to understand how to do this in the manner above. > >>>>> > >>>>> Many thanks for your help, > >>>>> > >>>>> Glenn. > >>>> > >>>> Do you have a copy of The Designer's Guide to VHDL by Peter Ashenden= ? It's the "VHDL Bible". In the 3rd Edition, refer to section 4.1.3 Array= Attributes. > >>>> > >>>> I haven't done exactly what you're looking for, but I regularly use = 'length attribute to reduce the amount of code that needs to be updated or = rewritten when an array width (or length) changes, such as a data bus. To = make my code more reusable, it's pretty standard to use a Generic to define= the bus width and then it just cascades through the rest of the module des= ign without any additional intervention. > >>> > >>> Thanks for the reply. Yes, I do have a copy of Ashenden, and I can se= e that attributes are generally very useful - I just mentioned them as an e= xample in my original post though. > >>> > >>> I suspect my problem is due to the synthesis tool (Vivado in this cas= e) failing to recognise that the assignments to the bus are actually static= (as in my first example) and inferring logic for this. No doubt this is no= t helped by my use of a variable to keep track of the index value, and the = combinatorial process. > >>> > >>> In the end I managed to achieve what I wanted, at least for this simp= le example case, using a procedure: > >>> ***************************************************************** > >>> library ieee; > >>> use ieee.std_logic_1164.all; > >>> > >>> entity bus_top is > >>> port ( > >>> bus_out : out std_logic_vector(9 downto 0) :=3D (others =3D> '0') > >>> ); > >>> end bus_top; > >>> > >>> architecture rtl of bus_top is > >>> > >>> signal b : std_logic_vector(2 downto 0) :=3D "101"; > >>> signal c : std_logic_vector(1 downto 0) :=3D "11"; > >>> signal d : std_logic_vector(0 downto 0) :=3D "0"; > >>> > >>> procedure bus_assemble ( x, y, z : std_logic_vector; signal outbus : = out std_logic_vector) is > >>> variable bus_ind : integer :=3D 0; > >>> begin > >>> outbus(bus_ind+x'length-1 downto bus_ind) <=3D x; > >>> bus_ind :=3D bus_ind + x'length; > >>> outbus(bus_ind+y'length-1 downto bus_ind) <=3D y; > >>> bus_ind :=3D bus_ind + y'length; > >>> outbus(bus_ind+z'length-1 downto bus_ind) <=3D z; > >>> end bus_assemble; > >>> > >>> begin > >>> -- Bus assembly ---- > >>> bus_assemble ( b, c, d, bus_out); > >>> end rtl; > >>> ****************************************************************** > >>> Unfortunately, though, this will not help in the general case where I= have an arbitrary number of signals to concatenate onto the bus, unless th= ere is a way to collect together multiple vectors of differing lengths in k= ind of array ... > >>> I suspect I will just have to use the regular concatenation operator,= and calculate the necessary size of the bus by adding together the lengths= of the individual signals. > >>> > >>> Thanks again for you help. > >>> > >> > >> I can't think of anything to help the general case; you can't really > >> iterate over "ragged arrays" in VHDL, because there isn't really a > >> concept of such. VHDL-2018 will let you iterate over record types, bu= t > >> that doesn't help you right now. > >> > >> One thing I tend to do fairly often is to create record types for my > >> structured data and create custom pack/unpack functions that turn the > >> entire record into std_logic_vector and back. To build up those > >> pack/unpacks, I use the following code; which I freely invite you or > >> anyone else to have at: > >> > >> --- > >> > >> ----------------------------------------------------------------------= --------- > >> > >> -- Title : Useful Standard Functions Library > >> > >> ----------------------------------------------------------------------= --------- > >> > >> -- File : standard_functions.vhd > >> > >> -- Author : Rob Gaddi > >> > >> -- Company : Highland Technology, Inc. > >> > >> -- Created : 14-Feb-2012 > >> > >> -- Last update: 14-Feb-2012 > >> > >> -- Platform : Independent > >> > >> -- Standard : VHDL 93 - 08 > >> > >> ----------------------------------------------------------------------= --------- > >> > >> -- Description: Useful standard functions. > >> > >> ----------------------------------------------------------------------= --------- > >> > >> -- Revision History: > >> > >> ----------------------------------------------------------------------= --------- > >> > >> > >> > >> library ieee; > >> > >> use ieee.std_logic_1164.all; > >> > >> use ieee.numeric_std.all; > >> > >> > >> > >> package standard_functions is > >> > >> > >> > >> -----------------------------------------------------------------= ------ > >> > >> -- Base 2 Logarithms > >> ----------------------------------------------------------------= ------- > >> > >> > >> > >> --! ceil(log2(x)) > >> > >> --! This is also the number of bits required to represent > >> > >> --! x possible choices. clog2(4) =3D 2, clog2(5) =3D 3 > >> > >> pure function clog2(x : in positive) return natural; > >> > >> > >> > >> --! floor(log2(x)) > >> > >> --! This is also the index (with the LSB as bit 0) of the > >> > >> --! uppermost 1 bit for a given number represented in > >> > >> --! binary. flog2(4) =3D 2, flog2(5) =3D 2 > >> > >> pure function flog2(x : in positive) return natural; > >> > >> > >> > >> --! Number of bits needed to represent a given number in > >> > >> --! binary form. nbits(4) =3D 3, nbits(5) =3D 3, nbits(-4) =3D = 4 > >> > >> pure function nbits(x : in integer) return positive; > >> > >> > >> > >> ----------------------------------------------------------------= ------- > >> > >> -- Conversion Functions > >> ----------------------------------------------------------------= ------- > >> > >> > >> > >> --! Converts an integer straight into a std_logic_vector. > >> > >> pure function TO_SLV(data : in integer; bits : in positive) retu= rn > >> std_logic_vector; > >> > >> > >> > >> --! Converts a logic value to std_logic using active-high rules. > >> > >> pure function POS_LOGIC(x : in boolean) return std_logic; > >> > >> > >> > >> --! Converts a logic value to std_logic using active-low rules. > >> > >> pure function NEG_LOGIC(x : in boolean) return std_logic; > >> > >> > >> > >> ----------------------------------------------------------------= ------- > >> > >> -- Record conversion functions > >> ----------------------------------------------------------------= ------- > >> > >> > >> > >> -- These are useful when having to turn arbitrary data collecti= ons > >> > >> -- into std_logic_vector, generally for use with IP cores. > >> > >> -- > >> > >> -- pack is used to line up multiple pieces of data in one > >> > >> -- std_logic_vector; using a running variable that will reflect > >> > >> -- the index of the LSB of the next data to write. > >> > >> -- > >> > >> -- unpack is the reverse, pulling data off a vector. > >> > >> -- > >> > >> -- These shouldn't be used to construct bitfields that will be > >> > >> -- made accessible to the outside world; they're really just fo= r > >> > >> -- packing things up internally. Generally, you'll composite > >> > >> -- these together to make larger functions that turn an entire > >> > >> -- record type into and back from a std_logic_vector. > >> > >> -- > >> > >> > >> > >> procedure pack( > >> > >> target : inout std_logic_vector; > >> > >> idx : inout integer; > >> > >> nd : in std_logic_vector > >> > >> ); > >> > >> procedure pack( > >> > >> target : inout std_logic_vector; > >> > >> idx : inout integer; > >> > >> nd : in std_logic > >> > >> ); > >> > >> procedure pack( > >> > >> target : inout std_logic_vector; > >> > >> idx : inout integer; > >> > >> nd : in unsigned > >> > >> ); > >> > >> procedure pack( > >> > >> target : inout std_logic_vector; > >> > >> idx : inout integer; > >> > >> nd : in signed > >> > >> ); > >> > >> > >> > >> procedure unpack ( > >> > >> source : in std_logic_vector; > >> > >> idx : inout integer; > >> > >> dat : out std_logic_vector > >> > >> ); > >> > >> procedure unpack ( > >> > >> source : in std_logic_vector; > >> > >> idx : inout integer; > >> > >> dat : out std_logic > >> > >> ); > >> > >> procedure unpack ( > >> > >> source : in std_logic_vector; > >> > >> idx : inout integer; > >> > >> dat : out unsigned > >> > >> ); > >> > >> procedure unpack ( > >> > >> source : in std_logic_vector; > >> > >> idx : inout integer; > >> > >> dat : out signed > >> > >> ); > >> > >> > >> > >> ----------------------------------------------------------------= ------- > >> > >> -- Comparison Functions > >> ----------------------------------------------------------------= ------- > >> > >> > >> > >> --! Performs a "counter comparison", in which only bits expected > >> > >> --! to be '1' are actually checked. This is equivalent to a ful= l > >> > >> --! equality compare when used on an up-counter, but can take > >> > >> --! substantially less logic because bits expected to be zero > >> > >> --! aren't checked. For instance, to compare a counter to the > >> > >> --! constant value 17 requires only 2 bits to be compared. > >> > >> pure function counter_eq(x : in unsigned; constant tgt : in natu= ral) > >> > >> return boolean; > >> > >> > >> > >> pure function counter_eq(x : in natural; constant tgt : in natur= al) > >> > >> return boolean; > >> > >> > >> > >> end package standard_functions; > >> > >> > >> > >> package body standard_functions is > >> > >> > >> > >> ----------------------------------------------------------------= ------- > >> > >> -- Base 2 Logarithms > >> ----------------------------------------------------------------= ------- > >> > >> > >> > >> pure function flog2 (x : in positive) return natural is > >> > >> variable temp, log: natural; > >> > >> begin > >> > >> temp :=3D x / 2; > >> > >> log :=3D 0; > >> > >> while (temp /=3D 0) loop > >> > >> temp :=3D temp/2; > >> > >> log :=3D log + 1; > >> > >> end loop; > >> > >> return log; > >> > >> end function flog2; > >> > >> > >> > >> pure function clog2 (x : in positive) return natural is > >> > >> begin > >> > >> if (x =3D 1) then > >> > >> return 1; > >> > >> else > >> > >> return 1 + flog2(x - 1); > >> > >> end if; > >> > >> end function clog2; > >> > >> > >> > >> pure function nbits(x : in integer) return positive is > >> > >> begin > >> > >> if (x < 0) then > >> > >> return 2 + flog2(-x); > >> > >> elsif (x =3D 0) then > >> > >> return 1; > >> > >> else > >> > >> return 1 + flog2(x); > >> > >> end if; > >> > >> end function nbits; > >> > >> > >> > >> ----------------------------------------------------------------= ------- > >> > >> -- Conversion Functions > >> ----------------------------------------------------------------= ------- > >> > >> > >> > >> pure function TO_SLV( data : in integer; > >> > >> bits : in positive) > >> > >> return std_logic_vector is > >> > >> begin > >> > >> if (data < 0) then > >> > >> return STD_LOGIC_VECTOR(TO_SIGNED(data, bits)); > >> > >> else > >> > >> return STD_LOGIC_VECTOR(TO_UNSIGNED(data, bits)); > >> > >> end if; > >> > >> end function TO_SLV; > >> > >> > >> > >> pure function POS_LOGIC(x : in boolean) return std_logic is > >> > >> begin > >> > >> if x then > >> > >> return '1'; > >> > >> else > >> > >> return '0'; > >> > >> end if; > >> > >> end function POS_LOGIC; > >> > >> > >> > >> --! Converts a logic value to std_logic using active-low rules. > >> > >> pure function NEG_LOGIC(x : in boolean) return std_logic is > >> > >> begin > >> > >> if x then > >> > >> return '0'; > >> > >> else > >> > >> return '1'; > >> > >> end if; > >> > >> end function NEG_LOGIC; > >> > >> > >> > >> ----------------------------------------------------------------= ------- > >> > >> -- Record conversion functions > >> ----------------------------------------------------------------= ------- > >> > >> > >> > >> procedure pack( > >> > >> target : inout std_logic_vector; > >> > >> idx : inout integer; > >> > >> nd : in std_logic_vector > >> > >> ) is > >> > >> begin > >> > >> target(idx + nd'length - 1 downto idx) :=3D nd; > >> > >> idx :=3D idx + nd'length; > >> > >> end procedure pack; > >> > >> > >> > >> procedure pack( > >> > >> target : inout std_logic_vector; > >> > >> idx : inout integer; > >> > >> nd : in std_logic > >> > >> ) is > >> > >> begin > >> > >> target(idx) :=3D nd; > >> > >> idx :=3D idx + 1; > >> > >> end procedure pack; > >> > >> > >> > >> procedure pack( > >> > >> target : inout std_logic_vector; > >> > >> idx : inout integer; > >> > >> nd : in unsigned > >> > >> ) is > >> > >> begin > >> > >> target(idx + nd'length - 1 downto idx) :=3D STD_LOGIC_VECTOR= (nd); > >> > >> idx :=3D idx + nd'length; > >> > >> end procedure pack; > >> > >> > >> > >> procedure pack( > >> > >> target : inout std_logic_vector; > >> > >> idx : inout integer; > >> > >> nd : in signed > >> > >> ) is > >> > >> begin > >> > >> target(idx + nd'length - 1 downto idx) :=3D STD_LOGIC_VECTOR= (nd); > >> > >> idx :=3D idx + nd'length; > >> > >> end procedure pack; > >> > >> > >> > >> ----------------------------------------------------------------= ------ > >> > >> > >> > >> procedure unpack ( > >> > >> source : in std_logic_vector; > >> > >> idx : inout integer; > >> > >> dat : out std_logic_vector > >> > >> ) is > >> > >> begin > >> > >> dat :=3D source(idx + dat'length - 1 downto idx); > >> > >> idx :=3D idx + dat'length; > >> > >> end procedure unpack; > >> > >> > >> > >> procedure unpack ( > >> > >> source : in std_logic_vector; > >> > >> idx : inout integer; > >> > >> dat : out std_logic > >> > >> ) is > >> > >> begin > >> > >> dat :=3D source(idx); > >> > >> idx :=3D idx + 1; > >> > >> end procedure unpack; > >> > >> > >> > >> procedure unpack ( > >> > >> source : in std_logic_vector; > >> > >> idx : inout integer; > >> > >> dat : out unsigned > >> > >> ) is > >> > >> begin > >> > >> dat :=3D UNSIGNED(source(idx + dat'length - 1 downto idx)); > >> > >> idx :=3D idx + dat'length; > >> > >> end procedure unpack; > >> > >> > >> > >> procedure unpack ( > >> > >> source : in std_logic_vector; > >> > >> idx : inout integer; > >> > >> dat : out signed > >> > >> ) is > >> > >> begin > >> > >> dat :=3D SIGNED(source(idx + dat'length - 1 downto idx)); > >> > >> idx :=3D idx + dat'length; > >> > >> end procedure unpack; > >> > >> > >> > >> ----------------------------------------------------------------= ------- > >> > >> -- Comparison Functions > >> ----------------------------------------------------------------= ------- > >> > >> > >> > >> pure function counter_eq(x : in unsigned; constant tgt : in natu= ral) > >> > >> return boolean is > >> > >> > >> > >> variable target : unsigned(x'range); > >> > >> begin > >> > >> target :=3D TO_UNSIGNED(tgt, target'length); > >> > >> for i in target'range loop > >> > >> if (target(i) =3D '1') and (x(i) /=3D '1') then > >> > >> return false; > >> > >> end if; > >> > >> end loop; > >> > >> return true; > >> > >> end function counter_eq; > >> > >> > >> > >> pure function counter_eq(x : in natural; constant tgt : in natur= al) > >> > >> return boolean is > >> > >> > >> > >> variable counter : unsigned(31 downto 0); > >> > >> begin > >> > >> counter :=3D TO_UNSIGNED(x, 32); > >> > >> return counter_eq(counter, tgt); > >> > >> end function counter_eq; > >> > >> > >> > >> end package body standard_functions; > >> > >> > >> > >> --=20 > >> Rob Gaddi, Highland Technology -- www.highlandtechnology.com > >> Email address domain is currently out of order. See above to fix. > >=20 > > Many thanks Rob, the functions look very useful. In fact, your 'pack' p= rocedure appears to do exactly what I was originally wanting! It had not oc= curred to me to define the ports as inout though. The problem though is tha= t the synthesis still infers a lot of logic to do this. I suspect the reaso= n for this is that I need to make the procedure calls from within a process= , in order for them to be executed sequentially. Is there another to achiev= e sequential execution without using a process block? My new code is below,= using your 'pack' procedure. Maybe you can see some problem with this? > >=20 > > *********************************************** > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity bus_top is > > port ( > > bus_out : out std_logic_vector(5 downto 0) :=3D (others =3D> '0') > > ); > > end bus_top; > >=20 > > architecture rtl of bus_top is > >=20 > > signal b : std_logic_vector(2 downto 0) :=3D "101"; > > signal c : std_logic_vector(1 downto 0) :=3D "11"; > > signal d : std_logic_vector(0 downto 0) :=3D "0"; > >=20 > > procedure pack( > > target : inout std_logic_vector; > > idx : inout integer; > > nd : in std_logic_vector > > ) is > > begin > > target(idx + nd'length - 1 downto idx) :=3D nd; > > idx :=3D idx + nd'length; > > end procedure pack; > >=20 > > begin > > =20 > > BUS_ASSEMBLE : process > >=20 > > variable bus_tmp : std_logic_vector(5 downto 0) :=3D (others =3D> '0= '); > > variable idx : integer :=3D 0; > >=20 > > begin > > bus_tmp :=3D (others =3D> '0'); > > pack (bus_tmp, idx, b); > > pack (bus_tmp, idx, c); > > pack (bus_tmp, idx, d); > > bus_out(bus_tmp'length-1 downto 0) <=3D bus_tmp; > > wait; > > end process BUS_ASSEMBLE; > > =20 > > end rtl; > > ************************************************************ > >=20 >=20 > Your procedure only sets idx to 0 at the beginning of time, not at the=20 > beginning of each execution. Then again, your wait waits for all of=20 > time, so that's not helping you either. >=20 > Rather than write a process, you could write it as a function. >=20 > function pack_vectors(b, c, d: std_logic_vector) return std_logic_vector > variable bus_tmp : std_logic_vector(5 downto 0) :=3D (others =3D> '0')= ; > variable idx : integer :=3D 0; > begin > pack(bus_tmp, idx, b); > pack(bus_tmp, idx, c); > pack(bus_tmp, idx, d); > return bus_tmp; > end function pack_vectors; >=20 > ... >=20 > bus_out <=3D pack_vectors(b, c, d); >=20 > But your process-based approach should work too. >=20 > BUS_ASSEMBLE : process(b, c, d) > variable bus_tmp : std_logic_vector(bus_out'range); > variable idx : integer; > begin > bus_tmp :=3D (others =3D> '0'); > idx :=3D 0; > pack (bus_tmp, idx, b); > pack (bus_tmp, idx, c); > pack (bus_tmp, idx, d); > bus_out <=3D bus_tmp; > end process BUS_ASSEMBLE; >=20 > --=20 > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > Email address domain is currently out of order. See above to fix. Many thanks Rob, that's fantastic! So it turns out that the process in my o= riginal example would have worked too, had I correctly reset the index valu= e on each iteration, as you pointed out. Still it's more readable, and look= s a bit neater to use your procedure, especially if concatenating lots of s= ignals. Cheers! From newsfish@newsfish Thu Aug 1 00:43:53 2024 X-Received: by 2002:ac8:1112:: with SMTP id c18-v6mr9512000qtj.13.1536672985403; Tue, 11 Sep 2018 06:36:25 -0700 (PDT) X-Received: by 2002:a25:84d2:: with SMTP id x18-v6mr265139ybm.6.1536672985262; Tue, 11 Sep 2018 06:36:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder3.usenet.farm!feed.usenet.farm!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z10-v6no2680745qtb.0!news-out.google.com!i36-v6ni1570qti.0!nntp.google.com!z10-v6no2680743qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 11 Sep 2018 06:36:25 -0700 (PDT) In-Reply-To: <0b979a1d-b42a-4b4f-817f-8812abc2ace7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <5fc533c7-57ad-4ef1-a416-9f55bf2c9711@googlegroups.com> <57ebb662-10a0-4943-801f-3364153dd9af@googlegroups.com> <0b979a1d-b42a-4b4f-817f-8812abc2ace7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8cae9cc7-0874-4304-b11a-2a6b41bf684f@googlegroups.com> Subject: Re: generate VHDL testbench from requirements From: Thomas Stanka Injection-Date: Tue, 11 Sep 2018 13:36:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 29 Xref: reader02.eternal-september.org comp.lang.vhdl:9362 Am Mittwoch, 5. September 2018 00:42:11 UTC+2 schrieb Bobby: > Hi Thomas >=20 > Though I discussed these questions verbally with some colleagues, but so = far the most reasonable reply I got is from you. Thanks ! your points make = sense..... I also thought on these points i.e. 'assertions'. May be System = Verilog assertions can also be considered. For assertions you could even use VHDL. System Verilog and PSL just provide= additional syntax to reduce the code overhead. But they require learning n= ew syntax and may requrie more expensive licenses for the tools.=20 The general problem is how to convert general requirements in some formal s= tandardized test. This is very depending on the question how your requireme= nts look alike.=20 For every code you write I am sure you will find a document called "Specifi= cation" that will not work for your approach. I guess it is far easier to define a certain set of requirements in a struc= tured way that can be parsed and converted than writing code for a general = requirement specification.=20 =20 > I would really be interested to know why you consider python better than = java for writing parser ?=20 My java experience is maybe outdated (mostly last century), but read in a s= tring from file and parse it for its contents was then something consuming = far more code effort than in python. =20 From newsfish@newsfish Thu Aug 1 00:43:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: automatic indexing for bus assembly in VHDL Date: Thu, 13 Sep 2018 23:11:10 -0500 Organization: A noiseless patient Spider Lines: 106 Message-ID: References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 14 Sep 2018 04:11:14 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="6d1a8ed8471c2e248441edbe801a0466"; logging-data="13736"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18o6EGRQdfvOToe+3bXD83Ocj82S0MlioA=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:pu9LlVHqxPz6kTCpcZx+OaiRsYQ= In-Reply-To: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> Xref: reader02.eternal-september.org comp.lang.vhdl:9363 On 2018-09-04 12:42, glenn.christian@gmail.com wrote: > Hi, > > I am trying to find a way in VHDL of assigning arbitrary length signals to a bus, and programmatically assigning the bus indices for these signals. A very simple example is given below, where I am manually assigning the three differing length signals to one bus: > ***************************************************************** > library ieee; > use ieee.std_logic_1164.all; > > entity bus_top is > port ( > bus_out : out std_logic_vector(5 downto 0) > ); > end bus_top; > > architecture rtl of bus_top is > > signal b : std_logic_vector(2 downto 0) := "101"; > signal c : std_logic_vector(1 downto 0) := "11"; > signal d : std_logic_vector(0 downto 0) := "0"; > > begin > -- Bus assembly ---- > bus_out(0) <= b(0); > bus_out(1) <= b(1); > bus_out(2) <= b(2); > bus_out(3) <= c(0); > bus_out(4) <= c(1); > bus_out(5) <= d(0); > > end rtl; > **************************************************************** > > This simulates and synthesises as expected, to a constantly driven "011101" output. Of course my real application is much more complicated than this, and involves assembling many more signals, of differing lengths, on to the bus, and I do not want to have to manually change all the indices, when the size of one of the signals changes. I would like to find a way to automatically provide the bus indices using, for example, the signal's 'length attributes, in a similar way to the following: > > **************************************************************** > library ieee; > use ieee.std_logic_1164.all; > > entity bus_top is > port ( > bus_out : out std_logic_vector(5 downto 0) > ); > end bus_top; > > architecture rtl of bus_top is > > signal b : std_logic_vector(2 downto 0) := "101"; > signal c : std_logic_vector(1 downto 0) := "11"; > signal d : std_logic_vector(0 downto 0) := "0"; > > begin > -- Bus assembly ---- > bus_assemble: process (b,c,d) > variable bus_ind : integer := 0; > begin > bus_out <= (others => '0'); -- avoids latch inference > bus_out(bus_ind+b'length-1 downto bus_ind) <= b; > bus_ind := bus_ind + b'length; > bus_out(bus_ind+c'length-1 downto bus_ind) <= c; > bus_ind := bus_ind + c'length; > bus_out(bus_ind+d'length-1 downto bus_ind) <= d; > end process; > > end rtl; > **************************************************************** > Note the above code is not the correct solution as, although it appears to simulate correctly, the logic being sythesised is far more complex with many LUTs being inferred for what is just a static assignment. I feel it must be possible in VHDL to do this such that the synthesis tool will 'unroll' the statements in the same way as in the first example, eg for the indices to be calculated by the tools at compile-time rather than on the FPGA at run-time. This would require that the signals are assigned sequentially, and some way to keep track of the previous value of the bus index, but I have not been able to find the right construct for this: I have looked at processes (as above), regular loops, generate loops, functions and procedures. Can anyone shed some light on how to do this? I am aware there are other ways to achieve similar results, such as simple concatenation, or using a higher level programming language to automatically generate/annotate the VHDL, but I would like to und erstand how to do this in the manner above. > > Many thanks for your help, > > Glenn. > It sure seems like we are trying to make this too hard. This looks like a good application for a package. How about something like this: PACKAGE bus_lengths_pkg is constant sigBlen : integer:=3; constant sigClen : integer:=2; constant sigDlen : integer:=1; constant busoutlen : integer:=sigBlen+sigClen+sigDlen; END bus_lengths_pkg; library ieee; use ieee.std_logic_1164.all; use work.bus_lengths_pkg.all; entity bus_top is port ( bus_out : out std_logic_vector(busoutlen-1 downto 0) ); end bus_top; architecture rtl of bus_top is signal b : std_logic_vector(busBlen-1 downto 0) := "101"; signal c : std_logic_vector(busClen-1 downto 0) := "11"; signal d : std_logic_vector(busDlen-1 downto 0) := "0"; begin bus_out <= d & c & b; end rtl; From newsfish@newsfish Thu Aug 1 00:43:53 2024 X-Received: by 2002:a0c:9dd5:: with SMTP id p21-v6mr7934398qvf.62.1537176024694; Mon, 17 Sep 2018 02:20:24 -0700 (PDT) X-Received: by 2002:a5b:2cf:: with SMTP id h15-v6mr220975ybp.2.1537176024423; Mon, 17 Sep 2018 02:20:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z10-v6no1578604qtb.0!news-out.google.com!i36-v6ni847qti.0!nntp.google.com!z10-v6no1578595qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Sep 2018 02:20:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.62.223.243; posting-account=km0guAoAAAAXEWJpKf0MvWFtFuBHA6hz NNTP-Posting-Host: 193.62.223.243 References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: automatic indexing for bus assembly in VHDL From: glennchid Injection-Date: Mon, 17 Sep 2018 09:20:24 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 6 Xref: reader02.eternal-september.org comp.lang.vhdl:9364 Thanks Charles, I was aware I could use the concatenation operator (&), and simply calculat= e the required length of the resultant output bus, however I wanted a way t= o assign to arbitrary parts of the bus without necessarily considering it's= total length, which might be fixed to something like 128 bits. The approac= h above with the combinatorial process pretty bus accomplishes this. Best wishes, Glenn. From newsfish@newsfish Thu Aug 1 00:43:54 2024 X-Received: by 2002:a0c:b488:: with SMTP id c8-v6mr12003786qve.19.1537392421044; Wed, 19 Sep 2018 14:27:01 -0700 (PDT) X-Received: by 2002:a81:9285:: with SMTP id j127-v6mr264100ywg.6.1537392420839; Wed, 19 Sep 2018 14:27:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!z10-v6no483664qtb.0!news-out.google.com!i36-v6ni215qti.0!nntp.google.com!z10-v6no483659qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Sep 2018 14:27:00 -0700 (PDT) In-Reply-To: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5c222871-4752-4619-aaed-de6785a2e190@googlegroups.com> Subject: Re: automatic indexing for bus assembly in VHDL From: KJ Injection-Date: Wed, 19 Sep 2018 21:27:00 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9365 On Tuesday, September 4, 2018 at 1:42:19 PM UTC-4, glennchid wrote: > Hi, >=20 > I am trying to find a way in VHDL of assigning arbitrary length signals t= o a > bus, and programmatically assigning the bus indices for these signals. A= =20 > very simple example is given below, where I am manually assigning the thr= ee=20 > differing length signals to one bus: What I do is to define a record and two functions that convert between that= record and std_ulogic_vector. If you change the width of a field or add/s= ubtract fields all that needs to be edited is the record definition and the= to/from functions. There is no editing of anyplace where record elements = are used, unless of course you've hard-coded in something such as 'bus.b <= =3D "000";' and you change 'b' to be a four element vector instead of three= . If the overall bus length is flexible then you would have to be a little fa= ncier inside the to_std_ulogic_vector function to define the return vector = length. This method synthesizes as expected, no actual logic is created when going = through either the to_std_ulogic_vector or the from_std_ulogic_vector; to_s= td_ulogic_vector(from_std_ulogic_vector(x)) synthesizes to 'x'. Since the = record definition and the functions are all generally together in the sourc= e code, you're only editing a handful of lines that are all right near each= other. Not sure if this helps your particular application, but I think it's at lea= st close. Here is an example type t_CODE_FIFO_DATA is record End_MCU: std_ulogic_vector(22 downto 22); End_Rst_Interval: std_ulogic_vector(21 downto 21); -- Note: N= ot necessarily active at end of image Code_Type: std_ulogic_vector(20 downto 20); Consecutive_Zeros: std_ulogic_vector(19 downto 16); Significant_Bits: std_ulogic_vector(15 downto 12); Is_Zero: std_ulogic_vector(11 downto 11); Magnitude: std_ulogic_vector(10 downto 0); end record t_CODE_FIFO_DATA; function To_Std_ULogic_Vector(L: t_CODE_FIFO_DATA) return std_ulogic_ve= ctor is variable RetVal: std_ulogic_vector(22 downto 0); begin RetVal(L.End_MCU'range) :=3D L.End_MCU; RetVal(L.End_Rst_Interval'range) :=3D L.End_Rst_Interval; RetVal(L.Code_Type'range) :=3D L.Code_Type; RetVal(L.Consecutive_Zeros'range) :=3D L.Consecutive_Zeros; RetVal(L.Significant_Bits'range) :=3D L.Significant_Bits; RetVal(L.Is_Zero'range) :=3D L.Is_Zero; RetVal(L.Magnitude'range) :=3D L.Magnitude; return(RetVal); end function To_Std_ULogic_Vector; function From_Std_ULogic_Vector(L: std_ulogic_vector) return t_CODE_FIF= O_DATA is variable Lx: std_ulogic_vector(L'length - 1 downto 0); variable RetVal: t_CODE_FIFO_DATA; begin Lx :=3D L; RetVal.End_MCU :=3D Lx(RetVal.End_MCU'range); RetVal.End_Rst_Interval :=3D Lx(RetVal.End_Rst_Interval'range); RetVal.Code_Type :=3D Lx(RetVal.Code_Type'range); RetVal.Consecutive_Zeros :=3D Lx(RetVal.Consecutive_Zeros'range)= ; RetVal.Significant_Bits :=3D Lx(RetVal.Significant_Bits'range); RetVal.Is_Zero :=3D Lx(RetVal.Is_Zero'range); RetVal.Magnitude :=3D Lx(RetVal.Magnitude'range); return(RetVal); end function From_Std_ULogic_Vector; Kevin Jennings From newsfish@newsfish Thu Aug 1 00:43:54 2024 X-Received: by 2002:aed:2595:: with SMTP id x21-v6mr12180600qtc.44.1537432512853; Thu, 20 Sep 2018 01:35:12 -0700 (PDT) X-Received: by 2002:a25:2483:: with SMTP id k125-v6mr125606ybk.5.1537432512509; Thu, 20 Sep 2018 01:35:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!z10-v6no661607qtb.0!news-out.google.com!i36-v6ni241qti.0!nntp.google.com!z10-v6no661596qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Sep 2018 01:35:12 -0700 (PDT) In-Reply-To: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2a02:a312:c541:1600:2cf5:ca05:4f02:bde6; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 2a02:a312:c541:1600:2cf5:ca05:4f02:bde6 References: <1a1836a1-7f74-44f8-89ba-461a09c38226@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <95a96676-e04f-462e-bbc3-de02ba1f3373@googlegroups.com> Subject: Re: automatic indexing for bus assembly in VHDL From: Jim Lewis Injection-Date: Thu, 20 Sep 2018 08:35:12 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9366 Like Rob and KJ I also like a record based approach, however, if you don't there are a couple of things you can do. If you just wanted to brute force what you are doing it is: bus_out <= d & c & b ; If you assigned ranges that match where they go on the bus then you could make your code a little easier: signal b : std_logic_vector(2 downto 0) := "101"; signal c : std_logic_vector(4 downto 3) := "11"; signal d : std_logic_vector(5 downto 5) := "0"; begin -- Bus assembly ---- bus_assemble: process (b,c,d) variable bus_ind : integer := 0; begin bus_out <= (others => '0'); -- avoids latch inference bus_out(b'range) <= b; bus_out(c'range) <= c; bus_out(d'range) <= d; end process; end rtl; From newsfish@newsfish Thu Aug 1 00:43:54 2024 X-Received: by 2002:a37:1ae2:: with SMTP id l95-v6mr807772qkh.16.1537858497344; Mon, 24 Sep 2018 23:54:57 -0700 (PDT) X-Received: by 2002:a25:b29c:: with SMTP id k28-v6mr21505ybj.3.1537858497202; Mon, 24 Sep 2018 23:54:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!z10-v6no1601419qtb.0!news-out.google.com!i36-v6ni560qti.0!nntp.google.com!z10-v6no1601417qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Sep 2018 23:54:56 -0700 (PDT) In-Reply-To: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=49.206.253.254; posting-account=xGSeWgkAAACf4IsYcH9AGZ52I8ObJy1z NNTP-Posting-Host: 49.206.253.254 References: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <195ec9ef-1738-4265-818e-88458d3f859a@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: basavarajjamboti12@gmail.com Injection-Date: Tue, 25 Sep 2018 06:54:57 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9367 On Thursday, May 29, 2014 at 5:01:30 AM UTC+5:30, Brandon Spiteri wrote: > Hi, > thanks a lot for the help, I managed to understand a lot and perform some simulations with success. > I followed the flow chart and got the correct sequences on the logic analyser for the transmission (MOSI) > > Now I have this dilemma on how to amalgamate the DRDY pin of the ADC mentioned: > > http://datasheets.maximintegrated.com/en/ds/MAX1415-MAX1416.pdf > page. 29 is the flow chart > > with the SPI code found here: > > https://www.eewiki.net/display/LOGIC/Serial+Peripheral+Interface+(SPI)+Master+(VHDL) > > If I understand correctly, this is used mainly when reading from MISO. Is it a good idea to > use DRDY as an enable for SCLK in order to wait for the data to be ready? Or is there a better way? > > thanks > > > On Thursday, 1 May 2014 13:12:23 UTC+2, Brandon Spiteri wrote: > > Hi, > > > > I have managed to transmit some character (one after the other) using this code from; > > > > > > > > http://eewiki.net/pages/viewpage.action?pageId=4096096 > > > > > > > > I used continuous mode and I got the right characters on MOSI, one after the other, the only thing is that there are 4 clock cycles of high impedance between each 8-bit char. Is this oki? > > > > > > > > I am planning to interface with MAX1416 ADC. > > > > > > > > > > > > Also, I need to simulate an SPI input coming from the ADC. What is the best way to do it? > > > > > > > > Shall I use the same method I used for transmitting but this time in the test bench? > > > > > > > > I am using quartus and ModelSim. > > > > > > > > thanks From newsfish@newsfish Thu Aug 1 00:43:54 2024 X-Received: by 2002:a37:2302:: with SMTP id j2-v6mr839311qkj.31.1537858577741; Mon, 24 Sep 2018 23:56:17 -0700 (PDT) X-Received: by 2002:a0d:ea0b:: with SMTP id t11-v6mr20135ywe.6.1537858577662; Mon, 24 Sep 2018 23:56:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!z10-v6no1601794qtb.0!news-out.google.com!i36-v6ni560qti.0!nntp.google.com!z10-v6no1601785qtb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Sep 2018 23:56:17 -0700 (PDT) In-Reply-To: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=49.206.253.254; posting-account=xGSeWgkAAACf4IsYcH9AGZ52I8ObJy1z NNTP-Posting-Host: 49.206.253.254 References: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2339afba-9174-42ab-b767-01ad194d490a@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: basavarajjamboti12@gmail.com Injection-Date: Tue, 25 Sep 2018 06:56:17 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9368 can you send the code in vhdl Please From newsfish@newsfish Thu Aug 1 00:43:55 2024 X-Received: by 2002:a37:dd14:: with SMTP id n20-v6mr20670265qki.43.1539789545766; Wed, 17 Oct 2018 08:19:05 -0700 (PDT) X-Received: by 2002:a25:d245:: with SMTP id j66-v6mr338063ybg.2.1539789545479; Wed, 17 Oct 2018 08:19:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!e2-v6no3059662qtc.0!news-out.google.com!o27-v6ni1648qtk.1!nntp.google.com!e2-v6no3059658qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Oct 2018 08:19:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=145.128.201.99; posting-account=xQx-6woAAAD1dSQb63-suXm_HkQ_GXIS NNTP-Posting-Host: 145.128.201.99 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ad5422b-5460-4be6-a226-6b4551fbc275@googlegroups.com> Subject: E' SEMPRE SBORRATISSIMO IN CULO: LUIGI BERLUSCONI! CON PADRE LO SCHIFOSO PEDOFILO SILVIO BERLUSCONI! CON PADRE L'ASSASSINO MEGA MANDANTE DI OMICIDI SILVIO BERLUSCONI. CON PADRE LO STRAGISTA SPAPPOLA MAGISTRATI SILVIO BERLUSCONI! E CON FIDANZATA UN .. From: MariaGrazia Crupi Examantedi Marina-Berlusconi Injection-Date: Wed, 17 Oct 2018 15:19:05 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9369 E' SEMPRE SBORRATISSIMO IN CULO: LUIGI BERLUSCONI! CON PADRE LO SCHIFOSO PE= DOFILO SILVIO BERLUSCONI! CON PADRE L'ASSASSINO MEGA MANDANTE DI OMICIDI SI= LVIO BERLUSCONI. CON PADRE LO STRAGISTA SPAPPOLA MAGISTRATI SILVIO BERLUSCO= NI! E CON FIDANZATA UN ............ ^MASSONE DI COSA NOSTRA ^ CON LA BARBA https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg E NON, COME FIDANZATA, LA NOTA PUTTANONA COCAINOMANE FEDERICA FUMAGALLI, DA= ANNI SCOPATA DA TANTISSIMI COCAINOMANI COME LEI, IN MILLE CLUB PRIVE' DELL= A INTERA FOGNA NAZISTA E MAFIOSA DI BERLUSCONIA, COME COSI', DI MONTECARLO = E SVIZZERA! 1 E POI: VADA IN GALERA IL MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI, NON S= U WIKIPEDIA. MEGA RICICLA SOLDI MAFIOSI BASTARDO LUIGI BERLUSCONI: COME I P= EZZI DI MERDA CRIMINALISSIMI SUOI NONNO E PADRE DICEVO.. ANYWAY... E' SEMPRE SBORRATO TUTTO DENTRO AL CULO: LUIGI BERLUSCON= I! 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QUESTO: https://www.tuttouomi= ni.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-amico.jpg CIAO A TUTTI. SONO LA VICENTISSIMA PORNOSTAR ED INSEGNANTE A MILANO: MARIA = GRAZIA CRUPI. NATA IL 30.10.1969. E' SEMPRE, SEMPRE E STRA SEMPRE SBORRATO NEL CULO: LUIGI BERLUSCONI! CON FI= DANZATA UN ^MASSONE MAFIOSO^ CON LA BARBA https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg E NON CON FIDANZATA, LA NOTA ZOCCOLA FEDERICA FUMAGALLI, DA ANNI SCOPATA DA= TUTTI, IN MILLE CLUB PRIVE' DI INTERA FOGNA NAZISTA E MAFIOSA DI BERLUSCON= IA. COME COSI', DI MONTECARLO, INGHILTERRA E SVIZZERA! DICEVO.. E' SEMPRE SBORRATO TUTTO DENTRO AL CULO: LUIGI BERLUSCONI! CON FID= ANZATA UN ^MASSONE MAFIOSO^ CON LA BARBA https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg ^MASSONE MAFIOSO^ DELLA MEGA ASSASSINA GRAN LOGGIA DEL DRAGO DEL DITTATORE = FASCISTA, NDRANGHETISTA, CAMORRA, DI COSA NOSTRA, OLTRE CHE STRAGISTA SPAPP= OLA MAGISTRATI, MANDANTE DI MIGLIAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI= , MALORI, INCIDENTI, NOTO PEDOFILO SILVIO BERLUSCONI!!! RICICLA VALANGHE DI SOLDI MAFIOSI IL RICCHIIONE SEMPRE COL CULO PIENO DI SB= ORRA, IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINA= LISSIMA B CINQUE SRL. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERL= USCONI DI CRIMINALISSIMA MEDIASET ALIAS MAFIASET, CAMORRASET, NDRANGASET, N= AZISTSET.=20 =20 =20 =20 =20 =20 =20 2 IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSI= MA FININVEST ALIAS (MA)FI(A)NINVEST. IL DELINQUENTISSIMO RICICLA SOLDI MAFI= OSI LUIGI DI CRIMINALISSIMA MOLMED. IL DELINQUENTISSIMO RICICLA SOLDI MAFIO= SI LUIGI BERLUSCONI DI CRIMINALISSIMA HOLDING ITALIANA QUATTORDICESIMA SPA = (GIA' CASSAFORTE MAFIOSISSIMA DI STEFANO BONTATE PRIMA E TOTO RIINA, POI...= CASPITERINA CHE SOCI PER BENE, CASPITERINA, WAGLIO'). IL DELINQUENTISSIMO R= ICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA H 14 ( SEMPRE GIA' = CASSAFORTE MAFIOSA DI STEFANO BONTATE PRIMA E TOTO RIINA, POI...CASPITERINA= CHE SOCI PER BENE, CASPITERINA, WAGLIO'). IL DELINQUENTISSIMO RICICLA SOL= DI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA SERI JAKAL GROUP. IL DELINQUE= NTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ITHACA SR= L. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALIS= SIMA DI U-START. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI= DI CRIMINALISSIMA SOLDO LTD. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LU= IGI BERLUSCONI DI CRIMINALISSIMA SOLDO FINANCIAL SERVICES. IL DELINQUENTISS= IMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA MEDIOLANUM, MA= FIOLANUM, CAMORRANUM, NDRANGOLANUM, RICICLANUMPERCOCALEROSCOLOMBIANUM, NAZI= STANUM, HITLERANUM, PINOCHETTANUM. IL DELINQUENTISSIMO RICICLA SOLDI MAFIO= SI LUIGI BERLUSCONI DI CRIMINALISSIMA XLAB. IL DELINQUENTISSIMO RICICLA SO= LDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA HOLDING DI INVESTIMENTI B5. = =20 IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIM= A ABOCA DI SAN SEPOLCRO. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI B= ERLUSCONI DI CRIMINALISSIMA PAYLEVEN. IL DELINQUENTISSIMO RICICLA SOLDI MA= FIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ROCKET INTERNET. IL DELINQUENTISSI= MO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ELIGOTECH AMSTE= RDAM. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINA= LISSIMA CGNAL DEL TOPO DI FOGNA BERLUSCORROTTISSIMO MARCO CARRAI. IL DELINQ= UENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ALGEBRI= S DEL FIGLIO DI PUTTANA, ANZI, FIGLIO DI PUTTA-NA-ZISTA MEGA RICICLA SOLDI = MAFIOSI TANTO QUANTO: DAVIDE SERRA. IL DELINQUENTISSIMO RICICLA SOLDI MAFI= OSI LUIGI BERLUSCONI DI CRIMINALISSIMA SIREFID ( IL TUTTO INSIEME AD UN ALT= RO VERME MEGA RICICLA SOLDI MAFIOSI, LA BESTIA CRIMINALISSIMA GIORGIO VALAG= UZZA, NON PER NIENTE, EX DI GIA' NAZISTA JP MORGAN). IL DELINQUENTISSIMO RI= CICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA CRYPTOLAB E CRYPTOPO= LIS DI NOTO PEDOFILO ASSASSINO PAOLO BARRAI ( DI FALLIMENTARISSIMO BLOG MER= CATO "MERDATO" LIBERO). IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BER= LUSCONI DI CRIMINALISSIMA EIDOO DI VERME DELLA NDRANGHETA: NATALE FERRARA D= A REGGIO CALABRIA ( CRIMINALISSIMA EIDOO DI VERME DELLA NDRANGHETA: NATALE = MASSIMILIANO FERRARA DA REGGIO CALABRIA). PIU' DI TANTISSIMA ALTRA MERDA FI= NANZIARIO-CRIMINALE, FASCIOMAFIOSA, BERLUSCONICCHIA VARIA! SI, SI, E' PROPRIO COSI'. IL MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI E' UN NAZIRICCHIONE, UN CULA= CCHIONE, UN FEMMINONE SEMPRE SBORRATO PROFONDAMENTE DENTRO AL CULO ( NON SO= NO OMOFOBO O ANTI GAY, ASSOLUTISSIMAMENTE NO, ANZI, COME DETTO, MI DANNO AN= CHE A ME, OGNI TANTO, DEL GAY, DICO DI PIU', HO SEMPRE ODIATO QUANDO LEGGO = CHE ALCUNI GAYS VENGONO PICCHIATI QUASI A MORTE, O PROPRIO UCCISI, SOLO IN = QUANTO, BEN APPUNTO, GAYS: MA VISTO CHE I BERLUSCONI HAN NAZISTAMENTE SEMPR= E ODIATO, UMILIATO E DERISO GLI OMOSESSUALI E VISTO CHE COME LORO SOLITO, S= TANNO CASTRANDO MORTALMENTE LA LIBERTA' DI STAMPA, PER NON FAR SAPERE CHE L= ORO FIGLIO, IL NAZI RICCHIONE LUIGI BERLUSCONI, IL CRIMINALISSIMO RICICLA S= OLDI MAFIOSI LUIGI BERLUSCONI, PRENDE MEGA CAZZI IN CULO OGNI GIORNO E BEVE= LITRI E LITRI DI SBORRA, OGNI ANNO, CI PENSIAMO NOI A FARLO SAPERE ED AL P= IANETA TERRA TUTTO). E DI TIPO MOLTO MA MOLTO DEPRAVATO (AMA IL BERLUSCONI'= S DOUBLE ANAL STYLE, OSSIA, PRENDERE DUE MEGA CAZZI IN CULO, CONTEMPORANEME= NTE, CHE SCHIFO, PUAH)!=20 =20 =20 =20 =20 =20 =20 3 CRIMINALISSIMO MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI: CON PADRE L'ASS= ASSINO NAZIMAFIOSO, STRAGISTA SPAPPOLA MAGISTRATI, MANDANTE DI MIGLIAIA DI = OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI, VISCIDISSIMO PEDOFI= LO SILVIO BERLUSCONI! E CON FIDANZATA UN NOTO MASSONE DI COSA NOSTRA, CON L= A BARBA. QUESTO: https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-= bacio-gay-estate-amico.jpg E NON CON FIDANZATA LA NOTA TROIA, SEMPRE SCOPATA DA TUTTI IN MILLE CLUB PR= IVE, LA NOTA COCAINOMANE PUTTANA SEMPRE PENETRATA NEL CULO: FEDERICA FUMAGA= LLI. CIAO A TUTTI DA ME, ORA. SONO LA NOTA, VICENTISSIMA PORNOSTAR ED INSEGNANTE= : MARIA GRAZIA CRUPI. NATA IL 30.10.1969. https://yt3.ggpht.com/a-/ACSszfGYKnNA7XEP81l-T0eLaUTs8OwxdR6vxCtIFg=3Ds900-= mo-c-c0xffffffff-rj-k-no https://yt3.ggpht.com/a-/AJLlDp0JZgJt3slrUkUEWnWHjDcrVnCJYCft00OO8A=3Ds900-= mo-c-c0xffffffff-rj-k-no http://it.cultura.linguistica.italiano.narkive.com/jDPPWzSr/hi-babies-son-l= a-pornostar-insegnante-maria-grazia-crupi-facebook-maria-grazia-mari-crupi-= maria:i.1.4.thumb http://it.cultura.linguistica.italiano.narkive.com/jDPPWzSr/hi-babies-son-l= a-pornostar-insegnante-maria-grazia-crupi-facebook-maria-grazia-mari-crupi-= maria:i.1.3.thumb =20 NOTA IN TUTTO IL GLOBO TERRESTRE, ANCHE, PER ESSER STATA L' EX AMANTE LESBI= CA DI MARINA BERLUSCONI E PER BEN 12 ANNI ( FRA MONTAGNE DI CASH MAFIOSO, Q= UINTALI DI COCAINA, ORDINI DI OMICIDI E STRAGI: I BERLUSCONI SONO PIU' MALA= VITOSI ASSASSINI DI AL CAPONE E TOTO RIINA MESSI INSIEME, VE LO STRA ASSICU= RO) https://plus.google.com/108636656730606836659 https://plus.google.com/102103531009107965093 https://plus.google.com/100248419268040066274 ED ORA FATEMI URLARE CON TUTTE LE MIE FORZE, PLEASE, MI RIPETERO', MOLTO PR= OBABILMENTE, MA PER IL BENE DELLA UMANITA' TUTTA, LO FACCIO E LIETISSIMAMEN= TE! L'IMMENSO PRENDI CAZZI IN CULO LUIGI BERLUSCONI (FIDANZATA-WIKIPEDIA-PADRE = SPAPPOLA MAGISTRATI E SBAUSCIA TROIE POCO PIU' CHE BAMBINE, SILVIO BERLUSCO= NI..... " PER SEMPRE FUORI DAI COGLIONI") STA IMBASTENDO IN GIRO PER IL MON= DO, VERE E PROPRIE OVRA E GESTAPO ASSASSINE DEL WEB, COL PRIMA CITATO MERDO= NE BERLUSCONICCHIO MARCO CARRAI DI CGNAL E COL NAZI-ST-ALKER, ACCERTATO PED= ERASTA INCULA BAMBINI, FREQUENTISSIMO MANDANTE DI OMICIDI, GIA' TRE VOLTE F= INITO IN CARCERE: PAOLO BARRAI NATO A MILANO IL 28.6.1965 ( O FREQUENTISSIM= O MANDANTE DI OMICIDI, GIA' TRE VOLTE FINITO IN CARCERE: PAOLO PIETRO BARRA= I NATO A MILANO IL 28.6.1965 CHE SIA)!!! E SIA CHIARO, PLEASE: IO SONO MARI= A GRAZIA CRUPI DI MILANO. SONO L'EX AMANTE LESBICA DI MARINA BERLUSCONI.=20 LE HO LECCATO LA FIGA E LE HO MESSI AGGEGGI SESSUALI NEL CULO PER BEN 12 AN= NI ( ED AGGEGGI SESSUALI MOLTO MOLTO PERVERTITI, LO VOLEVA LEI, ME LO IMPOE= NVA LEI). SE VI E' UNA AMICA INTIMA DI LGBT QUELLA SONO PROPRIO IO. MA DEBB= O URLARE UNA COSA, ADESSO: LUIGI BERLUSCONI PRENDE CAZZI DI 30 CM IN SU FIN= O ALLA PROSTATA, FA BOCCHINI SU BOCCHINI E BEVE LITRI SU LITRI DI SBORRA. http://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi E' UN OMOSESSUALE PERSO, PRESTO, MOLTO PROBABILMENTE, SI FARA' ANCHE LA OPE= RAZIONE E DIVERRA' TRANS, MA NESSUNO E STRA NESSUNO HA IL CORAGGIO DI SCRIV= ERNE: STRACCERO' IO IL LERCIO DRAPPO DI OMERTA' BERLUSCONAZISTA E BERLUSCOM= AFIOSA, ALLORA! IL CIUCCIA E PRENDI MEGA CAZZI A GO GO LUIGI BERLUSCONI (BACIO RICCHIONESCH= ISSIMO QUI https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg ) NATO IN FIGHETTINA ARLESHEIM (CH) IL 27.9.1988. SI, PROPRIO LUI= : L'OMOSESSUALE ^OCCULTO^ LUIGI BERLUSCONI DI BASTARDAMENTE CRIMINALE ELIGO= TECH AMSTERAM, BASTARDAMENTE CRIMINALE SOLDO LTD LONDON E BASTARDAMENTE CRI= MINALE BANCA MEDIOLANUM (CHE RICICLANO MONTAGNE DI =E2=82=AC MAFIOSI, ESATT= AMENTE COME FACEVA LA CRIMINALISSIMA BANCA RASINI DI SUO NONNO, TOPO DI FOG= NA LUIGI BERLUSCONI ....O COME FACEVA E FA ORA PIU' CHE MAI, LA FININVEST D= EL PEDOFILO DILANIANTE FALCONE E BORSELLINO: SILVIO BERLUSCONI http://www.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commission= ate-berlusconi/ =20 =20 =20 =20 =20 =20 4 E DELLA CRIMINALISSIMA, HITLERIANA, ^OCCULTA" LESBICA MARINA BERLUSCONI https://twitter.com/premolisimona/status/876055837420158976 ) INSIEME AL BERLUS-CO-RROTTO VERME MARCO CARRAI DI CGNAL, CREA NAZITECNOLOGI= CHE NUOVE OVRA E GHESTAPO! COL NOTO ANTI SEMITA, GIA' 3 VOLTE FINITO IN CAR= CERE, PAOLO BARRAI, NATO A MILANO IL 28.6.1965 ( FINITO IN CARCERE PURE IN = BRASILE, ED ANCHE PER PEDOFILIA OMOSESSUALE: INCULAVA LI I BAMBINI, NE SCRI= VEREMO PRESTO http://www.rotadosertao.com/images/fotos/fotos_noticias/testao.jpg http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg )! COL TUTTO, PER FINIRE, UNITISSIMO ALL'ECONOMISTA NOTORIAMENTE MOLTO PEDOFIL= O, NAZISTA ED ASSASSINO PAOLO CARDEN=C3=80 DI SAN PAOLO INVEST E MALAVITOSA= MEDIOLANUM STESSA. http://www.py.cz/pipermail/python/2017-September/013036.html https://a.mytrend.it/authors/1385.jpg =20 NATO A MACERATA IL 2.19.1971 E RESIDENTE A PENNA SAN GIOVANNI (MACERATA), V= IA UMBERTO I, NUMERO 41. COME ANCHE IN VIA POZZO 105, 63837 FALERONE (FM) h= ttps://www.commoditiestrading.it/public/autori/635338392358575000_Cardena.j= pg STO MERDAIO MEGA OMICIDA ERA DIETRO LO STUPRO DI GRUPPO EFFETTUATO A PAMELA= MASTROPIETRO. http://nomassoneriamacerata.blogspot.com/2018/02/lomicidio-di-pamela-mastro= pietro.html A CUI HA FATTO SEGUITO UN RITUALE MASSONICO NAZIFASCISTA, EFFETTUATO PROPRI= O DAL SATANISTA ASSASSINO E PEDOFILO PAOLO CARDENA', PORTANTE ALLA DIVISION= E DEL CORPO DI PAMELA ( EFFETTUATA DA MEDICI LEGALI MASSONI SANGUINARI, COM= E AI TEMPI DEL MOSTRO DI FIRENZE: FRATELLI CRIMINALISSIMI DEI PAZZI OMICIDA= PAOLO CARDENA' E STEFANO CARDENA' DI CRIMINALISSIME CARDENA' AND PARTNERS = E CARDENA' CONSULTING). QUESTO LINK QUADRA OGNI COSA, A PROPOSITO http://m.dagospia.com/clamoroso-a-macerata-sospetti-su-un-giro-di-baby-squi= llo-dietro-l-omicidio-di-pamela-mastropietro-171763 HAN POI TROVATO 4 LORO SCUGNIZZI MALAVITOSI NIGERIANI PER GIRARE A LORO OGN= I COLPA ( I QUALI, ORA, IN CARCERE, DALTRONDE, AVRANNO VITTO E ALLOGGIO PER= UN TOT DI TEMPO, PIU' TANTI SOLDI QUA E LA, RICEVUTI DA QUESTI MASSONI ASS= ASSINI, PER STARE ZITTI.. COSI' CHE FRA QUALCHE ANNO USCIRANNO DALLE CELLE = E SARANNO PURE BENESTANTI).=20 DI QUESTO NE SCRIVONO E DICONO NOTI MASSONI DI ESTREMA DESTRA STESSA, QUALI= FABIO FRABETTI, PAOLO FRANCESCHETTI E SPECIALMENTE GIANFRANCO CARPEORO, IN= REALTA', A LIVELLO DI VERO NOME E COGNOME, GIANFRANCO PECORARO, ( CHE, VIA= MARI DI LOGGE MASSONICHE, SON ADDENTRO DA UNA VITA A QUESTO TIPO DI OMICID= I, QUINDI, SANNO ALLA PERFEZIONE OGNI COSA ED AMMIREVOLISSIMAMENTE CE NE FA= NNO SAPERE) http://petalidiloto.com/2018/02/due-parole-sullomicidio-pamela-mastropietro= .html http://petalidiloto.com/2012/12/intervista-carpeoro-su-massoneria-e.html QUESTO E' SONO UN ANTIPASTINO. I PIATTI FORTI ARRIVERANNO AL PIU' PRESTO PO= SSIBILE. O IL PEDOFILO SPAPPOLA MAGISTRATI... O IL NAZIMAFIOSO ASSASINO SILVIO BERLUSCONI.. O IL DITTATORE COCAINOMANE DISTRUGGI VITE ALTRUI SILVIO BERLUSCONI.. .. AMMETTE IL MALE INGIUSTIFICATISSIMO FATTO, .. AMMETTE IL MALE DAVVERO INGIUSTISSIMO ED OMICIDA, FATTO ( SA' BENISSIMO = A CHE E CHI MI RIFERISCO). E RISARCISCE. O LA GIUSTIZIA LA FARO' IO. NEI SU= OI CONFRONTI E NEI CONFRONTI DI TUTTI I PORCI E VERMI CHE RADONO AL SUOLO V= ITE DI INNOCENTI, PER LUI! PER SUA BORIA, SATANAZIFASCISMO, COCAINA, SOLDI = MAFIOSI, ARROGANZA, ORGE PEDOFILESCHE, SCORCIATOIE SOCIALI, PREPOTENZA, EGO= CENTRISMO, ANTIDEMOCRAZIA, PERVERSIONE, CORRUZIONE, COSA NOSTRA, CAMORRA, N= DRANGHETA, SACRA CORONA UNITA, VANITA', BRAMA DI CAMMINARE A MORTE SULLE ES= ISTENZE ALTRUI. O FATTI O CAZZI AMARI, DA ORA E PER SEMPRE, PER GLI ASSASSI= NI, STRAGISTI, NAZIMAFIOSI, EFFERATISSIMI CRIMINALI IN FIGHETTINA E RUBATA = CRAVATTA: BERLUSCONI! =20 From newsfish@newsfish Thu Aug 1 00:43:55 2024 X-Received: by 2002:ac8:2373:: with SMTP id b48-v6mr27609290qtb.43.1539964218597; Fri, 19 Oct 2018 08:50:18 -0700 (PDT) X-Received: by 2002:a81:7bd7:: with SMTP id w206-v6mr389834ywc.3.1539964218295; Fri, 19 Oct 2018 08:50:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!e5-v6no745638qtr.0!news-out.google.com!o27-v6ni4671qtk.1!nntp.google.com!e5-v6no745634qtr.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Oct 2018 08:50:17 -0700 (PDT) In-Reply-To: <22905eed-b074-47d9-a6cc-bc8dacdd14a9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=186.49.61.45; posting-account=lFCc5wkAAADfJ2VuusayjtaOtGPaRbHG NNTP-Posting-Host: 186.49.61.45 References: <22905eed-b074-47d9-a6cc-bc8dacdd14a9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Fizzim - the free finite state machine design tool adds VHDL ! From: nestorbattaglia1957@gmail.com Injection-Date: Fri, 19 Oct 2018 15:50:18 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9370 El jueves, 27 de febrero de 2014, 21:01:03 (UTC-2), zimmerdesi...@gmail.com= escribi=C3=B3: > fizzim (www.fizzim.pl) is a free, open source fsm design tool. The gui r= uns in java and the backend code generator is in perl. It was originally w= ritten to output verilog, then systemverilog was added, and now vhdl. >=20 > The vhdl version is in beta test. You can download it from www.fizzim.co= m. Feedback is appreciated. >=20 > Paul Zimmer > Zimmer Design Services I have been using this design tool for some time now, but now I need to con= vert the state diagrams to the VHDL language. Where can I download this sof= tware version? thanks you From newsfish@newsfish Thu Aug 1 00:43:55 2024 X-Received: by 2002:ac8:893:: with SMTP id v19-v6mr5364254qth.40.1539968228789; Fri, 19 Oct 2018 09:57:08 -0700 (PDT) X-Received: by 2002:a25:b29c:: with SMTP id k28-v6mr440186ybj.3.1539968228636; Fri, 19 Oct 2018 09:57:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!e5-v6no843951qtr.0!news-out.google.com!l35-v6ni911qte.0!nntp.google.com!e5-v6no843938qtr.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Oct 2018 09:57:08 -0700 (PDT) In-Reply-To: <22905eed-b074-47d9-a6cc-bc8dacdd14a9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <22905eed-b074-47d9-a6cc-bc8dacdd14a9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <600f03f8-6b07-4854-b492-b885231a10e3@googlegroups.com> Subject: Re: Fizzim - the free finite state machine design tool adds VHDL ! From: gnuarm.deletethisbit@gmail.com Injection-Date: Fri, 19 Oct 2018 16:57:08 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9371 On Thursday, February 27, 2014 at 6:01:03 PM UTC-5, zimmerdesi...@gmail.com wrote: > fizzim (www.fizzim.pl) is a free, open source fsm design tool. The gui runs in java and the backend code generator is in perl. It was originally written to output verilog, then systemverilog was added, and now vhdl. > > The vhdl version is in beta test. You can download it from www.fizzim.com. Feedback is appreciated. I wanted to take a look at your tool and found a page about "Running fizzim on Windoz without cygwin". But the page appears to either have been hacked or is laced with advertising... or maybe both. You might want to check your web site. Ahhh, as I poked around I see a post about the web site being "back up". I guess someone is targeting you. I know that sucks. But all these posts seem to be very old, from 2015. Haven't you fixed the web site since then? Oh crap! Nestor replied to a post from 2014 and all of this is pretty long in the tooth!!! I would bet the tool is no longer even supported. The latest download is from 2016. Rick C. From newsfish@newsfish Thu Aug 1 00:43:56 2024 X-Received: by 2002:ac8:1289:: with SMTP id y9-v6mr1756007qti.30.1540903154841; Tue, 30 Oct 2018 05:39:14 -0700 (PDT) X-Received: by 2002:a0d:d703:: with SMTP id z3-v6mr32381ywd.7.1540903154010; Tue, 30 Oct 2018 05:39:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!e5-v6no2507758qtr.0!news-out.google.com!c29-v6ni2738qtg.1!nntp.google.com!e5-v6no2507751qtr.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Oct 2018 05:39:13 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.35.236.150; posting-account=xQx-6woAAAD1dSQb63-suXm_HkQ_GXIS NNTP-Posting-Host: 195.35.236.150 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: E' SEMPRE SBORRATO IN CULO: LUIGI BERLUSCONI! CON PADRE IL DEPRAVATO PEDOFILO SILVIO BERLUSCONI! CON PADRE L'ASSASSINO MEGA MANDANTE DI OMICIDI SILVIO BERLUSCONI! CON PADRE LO STRAGISTA SPAPPOLA MAGISTRATI SILVIO BERLUSCONI! E CON FIDANZATA UN....... From: MariaGrazia Crupi Examantedi Marina-Berlusconi Injection-Date: Tue, 30 Oct 2018 12:39:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9372 E' SEMPRE SBORRATO IN CULO: LUIGI BERLUSCONI! CON PADRE IL DEPRAVATO PEDOFI= LO SILVIO BERLUSCONI! CON PADRE L'ASSASSINO MEGA MANDANTE DI OMICIDI SILVIO= BERLUSCONI! CON PADRE LO STRAGISTA SPAPPOLA MAGISTRATI SILVIO BERLUSCONI! = E CON FIDANZATA UN......... ^MASSONE DI COSA NOSTRA^ CON LA BARBA! https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg E NON, COME FIDANZATA, LA NOTA PUTTANONA COCAINOMANE FEDERICA FUMAGALLI, DA= ANNI SCOPATA DA TANTISSIMI COCAINOMANI COME LEI, IN MILLE CLUB PRIVE' DELL= A INTERA FOGNA NAZISTA E MAFIOSA DI BERLUSCONIA, COME COSI', DI MONTECARLO = E SVIZZERA! 1 E POI: VADA IN GALERA IL MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI, NON S= U WIKIPEDIA. MEGA RICICLA SOLDI MAFIOSI BASTARDO LUIGI BERLUSCONI: COME I P= EZZI DI MERDA CRIMINALISSIMI SUOI NONNO E PADRE DICEVO.. ANYWAY... E' SEMPRE SBORRATO TUTTO DENTRO AL CULO: LUIGI BERLUSCON= I! CON FIDANZATA UN ^MASSONE MAFIOSO^ CON LA BARBA https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg ^MASSONE MAFIOSO^ DELLA MEGA ASSASSINA GRAN LOGGIA DEL DRAGO DEL DITTATORE = FASCIOMAFIOSO, STRAGISTA SPAPPOLA MAGISTRATI, MANDANTE DI MIGLIAIA DI OMICI= DI MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI, NOTO PEDOFILO SILVIO BER= LUSCONI!!! SI, SI, E' PROPRIO COSI'. IL MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA HOLDING IT= ALIANA QUATTORDICESIMA E' UB FROCIO, CULACCHIONE, FEMMINONE SEMPRE SBORRATO= PROFONDAMENTE DENTRO AL CULO, MA DI TIPO MOLTO MA MOLTO DEPRAVATO (AMA IL = BERLUSCONI'S DOUBLE ANAL STYLE, OSSIA, PRENDERE DUE MEGA CAZZI IN CULO, CON= TEMPORANEMENTE, CHE SCHIFO, PUAH)! CON PADRE L'ASSASSINO NAZIMAFIOSO, STRAG= ISTA SPAPPOLA MAGISTRATI, MANDANTE DI MIGLIAIA DI OMICIDI MASCHERATI DA FIN= TI SUICIDI, MALORI, INCIDENTI: PEDOFILO SILVIO BERLUSCONI! E CON FIDANZATA = UN NOTO MASSONE DI COSA NOSTRA, CON LA BARBA. QUESTO: https://www.tuttouomi= ni.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-amico.jpg CIAO A TUTTI. SONO LA VICENTISSIMA PORNOSTAR ED INSEGNANTE A MILANO: MARIA = GRAZIA CRUPI. NATA IL 30.10.1969. E' SEMPRE, SEMPRE E STRA SEMPRE SBORRATO NEL CULO: LUIGI BERLUSCONI! CON FI= DANZATA UN ^MASSONE MAFIOSO^ CON LA BARBA https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg E NON CON FIDANZATA, LA NOTA ZOCCOLA FEDERICA FUMAGALLI, DA ANNI SCOPATA DA= TUTTI, IN MILLE CLUB PRIVE' DI INTERA FOGNA NAZISTA E MAFIOSA DI BERLUSCON= IA. COME COSI', DI MONTECARLO, INGHILTERRA E SVIZZERA! DICEVO.. E' SEMPRE SBORRATO TUTTO DENTRO AL CULO: LUIGI BERLUSCONI! CON FID= ANZATA UN ^MASSONE MAFIOSO^ CON LA BARBA https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg ^MASSONE MAFIOSO^ DELLA MEGA ASSASSINA GRAN LOGGIA DEL DRAGO DEL DITTATORE = FASCISTA, NDRANGHETISTA, CAMORRA, DI COSA NOSTRA, OLTRE CHE STRAGISTA SPAPP= OLA MAGISTRATI, MANDANTE DI MIGLIAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI= , MALORI, INCIDENTI, NOTO PEDOFILO SILVIO BERLUSCONI!!! RICICLA VALANGHE DI SOLDI MAFIOSI IL RICCHIIONE SEMPRE COL CULO PIENO DI SB= ORRA, IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINA= LISSIMA B CINQUE SRL. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERL= USCONI DI CRIMINALISSIMA MEDIASET ALIAS MAFIASET, CAMORRASET, NDRANGASET, N= AZISTSET.=20 =20 =20 =20 =20 =20 =20 2 IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSI= MA FININVEST ALIAS (MA)FI(A)NINVEST. IL DELINQUENTISSIMO RICICLA SOLDI MAFI= OSI LUIGI DI CRIMINALISSIMA MOLMED. IL DELINQUENTISSIMO RICICLA SOLDI MAFIO= SI LUIGI BERLUSCONI DI CRIMINALISSIMA HOLDING ITALIANA QUATTORDICESIMA SPA = (GIA' CASSAFORTE MAFIOSISSIMA DI STEFANO BONTATE PRIMA E TOTO RIINA, POI...= CASPITERINA CHE SOCI PER BENE, CASPITERINA, WAGLIO'). IL DELINQUENTISSIMO R= ICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA H 14 ( SEMPRE GIA' = CASSAFORTE MAFIOSA DI STEFANO BONTATE PRIMA E TOTO RIINA, POI...CASPITERINA= CHE SOCI PER BENE, CASPITERINA, WAGLIO'). IL DELINQUENTISSIMO RICICLA SOL= DI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA SERI JAKAL GROUP. IL DELINQUE= NTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ITHACA SR= L. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALIS= SIMA DI U-START. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI= DI CRIMINALISSIMA SOLDO LTD. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LU= IGI BERLUSCONI DI CRIMINALISSIMA SOLDO FINANCIAL SERVICES. IL DELINQUENTISS= IMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA MEDIOLANUM, MA= FIOLANUM, CAMORRANUM, NDRANGOLANUM, RICICLANUMPERCOCALEROSCOLOMBIANUM, NAZI= STANUM, HITLERANUM, PINOCHETTANUM. IL DELINQUENTISSIMO RICICLA SOLDI MAFIO= SI LUIGI BERLUSCONI DI CRIMINALISSIMA XLAB. IL DELINQUENTISSIMO RICICLA SO= LDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA HOLDING DI INVESTIMENTI B5. = =20 IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIM= A ABOCA DI SAN SEPOLCRO. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI B= ERLUSCONI DI CRIMINALISSIMA PAYLEVEN. IL DELINQUENTISSIMO RICICLA SOLDI MA= FIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ROCKET INTERNET. IL DELINQUENTISSI= MO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ELIGOTECH AMSTE= RDAM. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINA= LISSIMA CGNAL DEL TOPO DI FOGNA BERLUSCORROTTISSIMO MARCO CARRAI. IL DELINQ= UENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ALGEBRI= S DEL FIGLIO DI PUTTANA, ANZI, FIGLIO DI PUTTA-NA-ZISTA MEGA RICICLA SOLDI = MAFIOSI TANTO QUANTO: DAVIDE SERRA. IL DELINQUENTISSIMO RICICLA SOLDI MAFI= OSI LUIGI BERLUSCONI DI CRIMINALISSIMA SIREFID ( IL TUTTO INSIEME AD UN ALT= RO VERME MEGA RICICLA SOLDI MAFIOSI, LA BESTIA CRIMINALISSIMA GIORGIO VALAG= UZZA, NON PER NIENTE, EX DI GIA' NAZISTA JP MORGAN). IL DELINQUENTISSIMO RI= CICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA CRYPTOLAB E CRYPTOPO= LIS DI NOTO PEDOFILO ASSASSINO PAOLO BARRAI ( DI FALLIMENTARISSIMO BLOG MER= CATO "MERDATO" LIBERO). IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BER= LUSCONI DI CRIMINALISSIMA EIDOO DI VERME DELLA NDRANGHETA: NATALE FERRARA D= A REGGIO CALABRIA ( CRIMINALISSIMA EIDOO DI VERME DELLA NDRANGHETA: NATALE = MASSIMILIANO FERRARA DA REGGIO CALABRIA). PIU' DI TANTISSIMA ALTRA MERDA FI= NANZIARIO-CRIMINALE, FASCIOMAFIOSA, BERLUSCONICCHIA VARIA! SI, SI, E' PROPRIO COSI'. IL MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI E' UN NAZIRICCHIONE, UN CULA= CCHIONE, UN FEMMINONE SEMPRE SBORRATO PROFONDAMENTE DENTRO AL CULO ( NON SO= NO OMOFOBO O ANTI GAY, ASSOLUTISSIMAMENTE NO, ANZI, COME DETTO, MI DANNO AN= CHE A ME, OGNI TANTO, DEL GAY, DICO DI PIU', HO SEMPRE ODIATO QUANDO LEGGO = CHE ALCUNI GAYS VENGONO PICCHIATI QUASI A MORTE, O PROPRIO UCCISI, SOLO IN = QUANTO, BEN APPUNTO, GAYS: MA VISTO CHE I BERLUSCONI HAN NAZISTAMENTE SEMPR= E ODIATO, UMILIATO E DERISO GLI OMOSESSUALI E VISTO CHE COME LORO SOLITO, S= TANNO CASTRANDO MORTALMENTE LA LIBERTA' DI STAMPA, PER NON FAR SAPERE CHE L= ORO FIGLIO, IL NAZI RICCHIONE LUIGI BERLUSCONI, IL CRIMINALISSIMO RICICLA S= OLDI MAFIOSI LUIGI BERLUSCONI, PRENDE MEGA CAZZI IN CULO OGNI GIORNO E BEVE= LITRI E LITRI DI SBORRA, OGNI ANNO, CI PENSIAMO NOI A FARLO SAPERE ED AL P= IANETA TERRA TUTTO). E DI TIPO MOLTO MA MOLTO DEPRAVATO (AMA IL BERLUSCONI'= S DOUBLE ANAL STYLE, OSSIA, PRENDERE DUE MEGA CAZZI IN CULO, CONTEMPORANEME= NTE, CHE SCHIFO, PUAH)!=20 =20 =20 =20 =20 =20 =20 3 CRIMINALISSIMO MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI: CON PADRE L'ASS= ASSINO NAZIMAFIOSO, STRAGISTA SPAPPOLA MAGISTRATI, MANDANTE DI MIGLIAIA DI = OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI, VISCIDISSIMO PEDOFI= LO SILVIO BERLUSCONI! E CON FIDANZATA UN NOTO MASSONE DI COSA NOSTRA, CON L= A BARBA. QUESTO: https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-= bacio-gay-estate-amico.jpg E NON CON FIDANZATA LA NOTA TROIA, SEMPRE SCOPATA DA TUTTI IN MILLE CLUB PR= IVE, LA NOTA COCAINOMANE PUTTANA SEMPRE PENETRATA NEL CULO: FEDERICA FUMAGA= LLI. CIAO A TUTTI DA ME, ORA. SONO LA NOTA, VICENTISSIMA PORNOSTAR ED INSEGNANTE= : MARIA GRAZIA CRUPI. NATA IL 30.10.1969. https://yt3.ggpht.com/a-/ACSszfGYKnNA7XEP81l-T0eLaUTs8OwxdR6vxCtIFg=3Ds900-= mo-c-c0xffffffff-rj-k-no https://yt3.ggpht.com/a-/AJLlDp0JZgJt3slrUkUEWnWHjDcrVnCJYCft00OO8A=3Ds900-= mo-c-c0xffffffff-rj-k-no http://it.cultura.linguistica.italiano.narkive.com/jDPPWzSr/hi-babies-son-l= a-pornostar-insegnante-maria-grazia-crupi-facebook-maria-grazia-mari-crupi-= maria:i.1.4.thumb http://it.cultura.linguistica.italiano.narkive.com/jDPPWzSr/hi-babies-son-l= a-pornostar-insegnante-maria-grazia-crupi-facebook-maria-grazia-mari-crupi-= maria:i.1.3.thumb =20 NOTA IN TUTTO IL GLOBO TERRESTRE, ANCHE, PER ESSER STATA L' EX AMANTE LESBI= CA DI MARINA BERLUSCONI E PER BEN 12 ANNI ( FRA MONTAGNE DI CASH MAFIOSO, Q= UINTALI DI COCAINA, ORDINI DI OMICIDI E STRAGI: I BERLUSCONI SONO PIU' MALA= VITOSI ASSASSINI DI AL CAPONE E TOTO RIINA MESSI INSIEME, VE LO STRA ASSICU= RO) https://plus.google.com/108636656730606836659 https://plus.google.com/102103531009107965093 https://plus.google.com/100248419268040066274 ED ORA FATEMI URLARE CON TUTTE LE MIE FORZE, PLEASE, MI RIPETERO', MOLTO PR= OBABILMENTE, MA PER IL BENE DELLA UMANITA' TUTTA, LO FACCIO E LIETISSIMAMEN= TE! L'IMMENSO PRENDI CAZZI IN CULO LUIGI BERLUSCONI (FIDANZATA-WIKIPEDIA-PADRE = SPAPPOLA MAGISTRATI E SBAUSCIA TROIE POCO PIU' CHE BAMBINE, SILVIO BERLUSCO= NI..... " PER SEMPRE FUORI DAI COGLIONI") STA IMBASTENDO IN GIRO PER IL MON= DO, VERE E PROPRIE OVRA E GESTAPO ASSASSINE DEL WEB, COL PRIMA CITATO MERDO= NE BERLUSCONICCHIO MARCO CARRAI DI CGNAL E COL NAZI-ST-ALKER, ACCERTATO PED= ERASTA INCULA BAMBINI, FREQUENTISSIMO MANDANTE DI OMICIDI, GIA' TRE VOLTE F= INITO IN CARCERE: PAOLO BARRAI NATO A MILANO IL 28.6.1965 ( O FREQUENTISSIM= O MANDANTE DI OMICIDI, GIA' TRE VOLTE FINITO IN CARCERE: PAOLO PIETRO BARRA= I NATO A MILANO IL 28.6.1965 CHE SIA)!!! E SIA CHIARO, PLEASE: IO SONO MARI= A GRAZIA CRUPI DI MILANO. SONO L'EX AMANTE LESBICA DI MARINA BERLUSCONI.=20 LE HO LECCATO LA FIGA E LE HO MESSI AGGEGGI SESSUALI NEL CULO PER BEN 12 AN= NI ( ED AGGEGGI SESSUALI MOLTO MOLTO PERVERTITI, LO VOLEVA LEI, ME LO IMPOE= NVA LEI). SE VI E' UNA AMICA INTIMA DI LGBT QUELLA SONO PROPRIO IO. MA DEBB= O URLARE UNA COSA, ADESSO: LUIGI BERLUSCONI PRENDE CAZZI DI 30 CM IN SU FIN= O ALLA PROSTATA, FA BOCCHINI SU BOCCHINI E BEVE LITRI SU LITRI DI SBORRA. http://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi E' UN OMOSESSUALE PERSO, PRESTO, MOLTO PROBABILMENTE, SI FARA' ANCHE LA OPE= RAZIONE E DIVERRA' TRANS, MA NESSUNO E STRA NESSUNO HA IL CORAGGIO DI SCRIV= ERNE: STRACCERO' IO IL LERCIO DRAPPO DI OMERTA' BERLUSCONAZISTA E BERLUSCOM= AFIOSA, ALLORA! IL CIUCCIA E PRENDI MEGA CAZZI A GO GO LUIGI BERLUSCONI (BACIO RICCHIONESCH= ISSIMO QUI https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg ) NATO IN FIGHETTINA ARLESHEIM (CH) IL 27.9.1988. SI, PROPRIO LUI= : L'OMOSESSUALE ^OCCULTO^ LUIGI BERLUSCONI DI BASTARDAMENTE CRIMINALE ELIGO= TECH AMSTERAM, BASTARDAMENTE CRIMINALE SOLDO LTD LONDON E BASTARDAMENTE CRI= MINALE BANCA MEDIOLANUM (CHE RICICLANO MONTAGNE DI =E2=82=AC MAFIOSI, ESATT= AMENTE COME FACEVA LA CRIMINALISSIMA BANCA RASINI DI SUO NONNO, TOPO DI FOG= NA LUIGI BERLUSCONI ....O COME FACEVA E FA ORA PIU' CHE MAI, LA FININVEST D= EL PEDOFILO DILANIANTE FALCONE E BORSELLINO: SILVIO BERLUSCONI http://www.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commission= ate-berlusconi/ =20 =20 =20 =20 =20 =20 4 E DELLA CRIMINALISSIMA, HITLERIANA, ^OCCULTA" LESBICA MARINA BERLUSCONI https://twitter.com/premolisimona/status/876055837420158976 ) INSIEME AL BERLUS-CO-RROTTO VERME MARCO CARRAI DI CGNAL, CREA NAZITECNOLOGI= CHE NUOVE OVRA E GHESTAPO! COL NOTO ANTI SEMITA, GIA' 3 VOLTE FINITO IN CAR= CERE, PAOLO BARRAI, NATO A MILANO IL 28.6.1965 ( FINITO IN CARCERE PURE IN = BRASILE, ED ANCHE PER PEDOFILIA OMOSESSUALE: INCULAVA LI I BAMBINI, NE SCRI= VEREMO PRESTO http://www.rotadosertao.com/images/fotos/fotos_noticias/testao.jpg http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg )! COL TUTTO, PER FINIRE, UNITISSIMO ALL'ECONOMISTA NOTORIAMENTE MOLTO PEDOFIL= O, NAZISTA ED ASSASSINO PAOLO CARDEN=C3=80 DI SAN PAOLO INVEST E MALAVITOSA= MEDIOLANUM STESSA. http://www.py.cz/pipermail/python/2017-September/013036.html https://a.mytrend.it/authors/1385.jpg =20 NATO A MACERATA IL 2.19.1971 E RESIDENTE A PENNA SAN GIOVANNI (MACERATA), V= IA UMBERTO I, NUMERO 41. COME ANCHE IN VIA POZZO 105, 63837 FALERONE (FM) h= ttps://www.commoditiestrading.it/public/autori/635338392358575000_Cardena.j= pg STO MERDAIO MEGA OMICIDA ERA DIETRO LO STUPRO DI GRUPPO EFFETTUATO A PAMELA= MASTROPIETRO. http://nomassoneriamacerata.blogspot.com/2018/02/lomicidio-di-pamela-mastro= pietro.html A CUI HA FATTO SEGUITO UN RITUALE MASSONICO NAZIFASCISTA, EFFETTUATO PROPRI= O DAL SATANISTA ASSASSINO E PEDOFILO PAOLO CARDENA', PORTANTE ALLA DIVISION= E DEL CORPO DI PAMELA ( EFFETTUATA DA MEDICI LEGALI MASSONI SANGUINARI, COM= E AI TEMPI DEL MOSTRO DI FIRENZE: FRATELLI CRIMINALISSIMI DEI PAZZI OMICIDA= PAOLO CARDENA' E STEFANO CARDENA' DI CRIMINALISSIME CARDENA' AND PARTNERS = E CARDENA' CONSULTING). QUESTO LINK QUADRA OGNI COSA, A PROPOSITO http://m.dagospia.com/clamoroso-a-macerata-sospetti-su-un-giro-di-baby-squi= llo-dietro-l-omicidio-di-pamela-mastropietro-171763 HAN POI TROVATO 4 LORO SCUGNIZZI MALAVITOSI NIGERIANI PER GIRARE A LORO OGN= I COLPA ( I QUALI, ORA, IN CARCERE, DALTRONDE, AVRANNO VITTO E ALLOGGIO PER= UN TOT DI TEMPO, PIU' TANTI SOLDI QUA E LA, RICEVUTI DA QUESTI MASSONI ASS= ASSINI, PER STARE ZITTI.. COSI' CHE FRA QUALCHE ANNO USCIRANNO DALLE CELLE = E SARANNO PURE BENESTANTI).=20 DI QUESTO NE SCRIVONO E DICONO NOTI MASSONI DI ESTREMA DESTRA STESSA, QUALI= FABIO FRABETTI, PAOLO FRANCESCHETTI E SPECIALMENTE GIANFRANCO CARPEORO, IN= REALTA', A LIVELLO DI VERO NOME E COGNOME, GIANFRANCO PECORARO, ( CHE, VIA= MARI DI LOGGE MASSONICHE, SON ADDENTRO DA UNA VITA A QUESTO TIPO DI OMICID= I, QUINDI, SANNO ALLA PERFEZIONE OGNI COSA ED AMMIREVOLISSIMAMENTE CE NE FA= NNO SAPERE) http://petalidiloto.com/2018/02/due-parole-sullomicidio-pamela-mastropietro= .html http://petalidiloto.com/2012/12/intervista-carpeoro-su-massoneria-e.html QUESTO E' SONO UN ANTIPASTINO. I PIATTI FORTI ARRIVERANNO AL PIU' PRESTO PO= SSIBILE. O IL PEDOFILO SPAPPOLA MAGISTRATI... O IL NAZIMAFIOSO ASSASINO SILVIO BERLUSCONI.. O IL DITTATORE COCAINOMANE DISTRUGGI VITE ALTRUI SILVIO BERLUSCONI.. .. AMMETTE IL MALE INGIUSTIFICATISSIMO FATTO, .. AMMETTE IL MALE DAVVERO INGIUSTISSIMO ED OMICIDA, FATTO ( SA' BENISSIMO = A CHE E CHI MI RIFERISCO). E RISARCISCE. O LA GIUSTIZIA LA FARO' IO. NEI SU= OI CONFRONTI E NEI CONFRONTI DI TUTTI I PORCI E VERMI CHE RADONO AL SUOLO V= ITE DI INNOCENTI, PER LUI! PER SUA BORIA, SATANAZIFASCISMO, COCAINA, SOLDI = MAFIOSI, ARROGANZA, ORGE PEDOFILESCHE, SCORCIATOIE SOCIALI, PREPOTENZA, EGO= CENTRISMO, ANTIDEMOCRAZIA, PERVERSIONE, CORRUZIONE, COSA NOSTRA, CAMORRA, N= DRANGHETA, SACRA CORONA UNITA, VANITA', BRAMA DI CAMMINARE A MORTE SULLE ES= ISTENZE ALTRUI. O FATTI O CAZZI AMARI, DA ORA E PER SEMPRE, PER GLI ASSASSI= NI, STRAGISTI, NAZIMAFIOSI, EFFERATISSIMI CRIMINALI IN FIGHETTINA E RUBATA = CRAVATTA: BERLUSCONI! 5=20 MA ORA VOGLIO PARLARE DI ME, SI, PROPRIO DI ME! CIAO A TUTTI. SONO LA VICENTISSIMA PORNOSTAR, INSEGNANTE A MILANO, MASSONA = DI ALTO GRADO, INFORMATRICE DI SERVIZI SEGRETI DI MEZZO MONDO: MARIA GRAZIA= CRUPI. NATA IL 30.10.1969. NOTA IN TUTTO IL PIANETA TERRA PER ESSER STATA = PER BEN 12 ANNI, LA PIU' FOCOSA FRA TANTISSIME AMANTI LESBICHE DI MARINA BE= RLUSCONI (=20 https://plus.google.com/108636656730606836659 https://plus.google.com/102103531009107965093 https://plus.google.com/100248419268040066274 ) ED ORA FATEMI URLARE CON TUTTE LE MIE FORZE, PLEASE.... L'IMMENSO PRENDI CAZZI IN CULO LUIGI BERLUSCONI (FIDANZATA-WIKIPEDIA-PADRE = SPAPPOLA MAGISTRATI E SBAUSCIA TROIE POCO PIU' CHE BAMBINE, "SILVIO BERLUSC= ON PER SEMPRE FUORI DAI COGLIONI") DI CRIMINALISSIMA FININVEST ALIAS (MA)FI= (A)NINVEST, CRIMINALISSIMA MOLMED SPA, CRIMINALISSIMA HOLDING ITALIANA QUAT= TORDICESIMA SPA ALIAS CRIMINALISSIMA H14 (GIA' CASSAFORTE DI COSA NOSTRA: D= I STEFANO BONTATE, PRIMA E TOTO RIINA, POI), CRIMINALISSIMA BANCA MEDIOLANU= M MAFIOLANUM CAMORRANUM NDRANGOLANUM LAVALAVAPERCOCALEROSCOLOMBIANUM NAZIST= ANUM (OVE RICICLA SOLDI ASSASSINI A RAFFICA PROPRIO COME ACCADEVA NELLA SCH= IFOSA, MALAVITOSA, DAVVERO BASTARDA BANCA RASINI DEL TOPO DI FOGNA LUIGI BE= RLUSCONI "NONNO" http://susannaambivero.blogspot.com/2009/08/rasini-la-banca-di-berlusconi-e= -della.html COME, D' ALTRONDE, NELLA MALAVITOSISSIMA FININVEST DEL SUO PEZZO DI MERDA P= ADRE, NOTO PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI, COME DA QUESTO G= RANDISSIMO, FANATASTICO, INARRIVABILE DOUMENTARIO https://www.youtube.com/watch?v=3DFFxooBwjIIc ED ARTICOLO http://www.antimafiaduemila.com/home/primo-piano/68166-berlusconi-soldi-e-b= oss-mafiosi-negli-appunti-di-falcone.html ), CRIMINALISSIMA SOLDO LTD ROM= A, CRIMINALISSIMA SOLDO FINANCIAL SERVICES LTD, CRIMINALISSIMA ELIGOTECH AM= STERDAM, CRIMINALISSIMA CGNAL DI TOPO DI FOGNA BERLUSCORROTTISSIMO MARCO CA= RRAI, CRIMINALISSIMA ALGEBRIS DI MEGA RICICLA SOLDI MAFIOSI DAVIDE SERRA ED= ALTRA MERDA NAZIMAFIOSA BERLUSCONICCHIA VARIA STA CREANDO NUOVE OVRA E GHE= STAPO DEL WEB!! COL PRIMA CITATO MERDONE BERLUSCONICCHIO MARCO CARRAI DI CG= NAL, COL NAZI-ST-ALKER, ACCERTATO PEDERASTA INCULA BAMBINI, FREQUENTISSIMO = MANDANTE DI OMICIDI, GIA' TRE VOLTE FINITO IN CARCERE: PAOLO BARRAI NATO A = MILANO IL 28.6.1965 ( O FREQUENTISSIMO MANDANTE DI OMICIDI, GIA' TRE VOLTE = FINITO IN CARCERE: PAOLO PIETRO BARRAI NATO A MILANO IL 28.6.1965 CHE SIA)!= !! E SIA CHIARO, PLEASE: IO SONO MARIA GRAZIA CRUPI DI MILANO. SONO L'EX AM= ANTE LESBICA DI MARINA BERLUSCONI. GLI HO LECCATO LA FIGA E GLI HO MESSI AG= GEGGI SESSUALI NEL DI DIETRO PER BEN 13 ANNI. SE VI E' UNA AMICA INTIMA DI = LGBT QUELLA SONO PROPRIO IO. MA DEBBO URLARE UNA COSA, ADESSO: LUIGI BERLUS= CONI PRENDE CAZZI DI 30 CM IN SU FINO ALLA PROSTATA, FA BOCCHINI SU BOCCHIN= I E BEVE LITRI SU LITRI DI SBORRA. E' UN OMOSESSUALE PERSO, PRESTO, MOLTO P= ROBABILMENTE, SI FARA' ANCHE LA OPERAZIONE E DIVERRA' TRANS! http://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi IO, VINCENTISSIMA MASSONA, PORNOSTAR ( SEMPRE, ASSOLUTAMENTE, PERO', CON MA= SCHERINA: PER NON RISCHIARE DI PERDERE IL PUR SEMPRE COMODO E FACILE STIPEN= DIO DI DELLA PUBBLICA ISTRUZIONE) E ( COME ACCENNATO) INSEGNANTE MARIA GRAZ= IA CRUPI https://yt3.ggpht.com/a-/AJLlDp0JZgJt3slrUkUEWnWHjDcrVnCJYCft00OO8A=3Ds900-= mo-c-c0xffffffff-rj-k-no https://3.bp.blogspot.com/-dEkP1eE298c/WhONlbcQUuI/AAAAAAAAAKc/l3NqwLZT4VAM= 3xndpUyMEN0w5EsWttc7wCK4BGAYYCw/s113/AAEAAQAAAAAAAAL4AAAAJGIzZjk4YzFjLWQ1Zj= ctNGI0ZC1hYmU4LWFiODIzNzQ4ODY5Yw%255B1%255D.jpg ( COME DICEVO, SON ANCHE INSEGNANTE IN MILANO: ISTITUTI ROSA LUXEMBURG, ETT= ORE CONTI, ECT ECT.. TROVATE TUTTO QUI http://www.istruzione.lombardia.gov.= it/milano/wp-content/uploads/2013/07/Elenco-trasferimenti-definitiviIIgr.pd= f ) CHIAMATA LA " REGINA CALABRESEDDA DEGLI AMATORIAL PORN FILMS EX AMANTE LES= BICISSIMA DI MARINA BERLUSCONI". AMATORIAL PORN FILMS CHE HO FATTO A CENTIN= AIA, CENTINAIA E CENTINAIA IN VITA MIA. DI CUI ALMENO 70 PROPRIO NELLA VILL= A SATANISTA E NAZISTA, VILLA SATA-N-AZISTA DI ARCORE-HARDCORE https://www.ilfattoquotidiano.it/premium/articoli/le-notti-di-arcore-una-se= tta-del-male-con-tuniche-e-riti/ AMATORIAL PORN FILMS, SIA STRAIGHT, CHE LESBO, CHE ANCHE CON ALCUNI CAVALLI= , CHE HO GIRATO AD INIZIARE DA QUANDO AVEVO SEDICI ANNI E MEZZO, ALLORCHE' = IN MIA CALABRIA. ECCO UNA MANCIATA DI FOTO, SU MIGLIAIA E MIGLIAIA CHE HO https://4.bp.blogspot.com/-qkTlyigYRQM/WQsbwxkPZzI/AAAAAAAAALo/MGN1QnRh4Gcw= joiFO96u3-1bFXqWqegDQCK4B/s113/1443711887.76214.jpg http://b2.woxcdn.com/pics-final-2/fc3/909/fc39090be6f548a25aeec380b2ea36e2.= jpg https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcTOWSvw8gFuU_9mESWWP= FXldj2fp9uf71O-7d6iwFZh2B7IKO2RuQ http://scopateitaliane.it/fotovideo/4161.jpg https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcRQbZWcnN5tKpb_ra-np= 8v8mAfAGLrNU-7CkH7hUy8HCoWuhR6KFA RI ECCOMI ANCORA QUI, QUESTA VOLTA WITH ANOTHER PARRUCCA, MENTRE LECCO DA D= IETRO UNA MASSONA DI ORIGINI CALABRESI, DI NOTA FAMIGLIA BERLUSCONIANISSIMA= E LEGHISTISSIMA DI NDRANGHETA. COME ME, TRAPIANTATA ANCHE LEI A MILANO http://b1.woxcdn.com/pics-final-2/ced/ba8/cedba85d41629e8e0faa7f179b8f447a.= jpg ORMAI SONO SULLA SOGLIA DI FARE IL MIO MILLESIMO AMATORIAL PORN FILM, MA, A= TTENZIONE ASSOLUTA, POR FAVOR, SEMPRE CON MASCHERINA. PER NON PERDERE IL MI= O PUR SEMPRE COMODO SALARIO DEL MINISTERO DELL'ISTRUZIONE. FILM PORNO, DICE= VO, CHE HO FATTO A CENTINAIA E CENTINAIA, ORMAI E' TEMPO DI DIRE A MIGLIAIA= , FRA UN'ORGIA E L'ALTRA CON LA LESBICA NAZISTA, LAVA SOLDI MAFIOSI, ASSASS= INA, MEGA COCAINOMANE, CRIMINALISSIMA MARINA BERLUSCONI. OLTRE CHE CON LA L= ESBICA CAMORRISTA FRANCESCA PASCALE, LA LESBICA SATANISTA SIMONA PREMOLI, L= A LESBICA PURE SATANISTA DEBORAH PERAZZOLI, LA LESBICA PIU' SATANISTA DI TU= TTE, LA MANDANTE DI OMCIDI ANNA LOSAPIO DI LAVA SOLDI MAFIOSI, CRIMINALISSI= MO RELAIS DEI MANDORLI DI VIA LUIGI CALVETTI 9 A BERGAMO=20 http://www.relaisdeimandorli.it/ DI LAVA SOLDI MAFIOSI, CRIMINALISSIMA METAMEDICINA http://it.metamedecine.c= om/k_member/anna-losapio/ E DI LAVA SOLDI MAFIOSI, CRIMINALISSIMA SERENDIPITA' http://www.serendipita= .it/consulente-anna-losapio ED ANCORA, LA LESBICISSIMA "CHICLEFREAK" MARIA DE FILIPPI, LA LESBICONA SAT= ANAZISTA GIULIA BONGIORNO, OSSIA L' AVVOCATO PIU' AMATO DA COSA NOSTRA, CAM= ORRA E NDRANGHETA..OLTRE CHE CON LA "SCIUTA PAZZA" SARA TOMMASI, CON LA ZUR= IGHESE LAETITA BISSET ORA LAETITIA WAGNER ZAPPA, LA LESBICA CHE SI FINGE DI= SINISTRA ALBA PARTIETTI... E TANTE ALTRE LESBICHE O BISESSUALI , SPESSO PU= RE DEPRAVATISSIME, DI ARCORE-HARDCORE... ED IL TUTTO FRA CHILI E CHILI DI C= OCAINA E MONTAGNE DI CASH MAFIOSO ) LA ( APPENA CITATA FRA PARENTESI) ALTRETTANTO MASSONA, PORNOSTAR ED "ESPERT= A IN LINGUE" SIMONA PREMOLI https://plus.google.com/113646548587006228899 https://plus.google.com/115986687335585757334 https://plus.google.com/112260635418591459571 https://twitter.com/premolisimona https://it.linkedin.com/pub/dir/Simona/Premoli E TANTE ALTRE LESBICHE O BISESSUALI ABBIAMO LECCATO LA FIGA DI MARINA BERLU= SCONI X DECENNI, DECENNI E DECENNI! IO E SIMONA PREMOLI ABBIAMO FATTE ORGE = LESBICHE SU ORGE LESBICHE, CORREDATE DA CHILI DI COCAINA E PACCONI DI CASH = MAFIOSO, CON, COME PRIMA CITATO FRA PARENTESI, MARINA BERLUSCONI, MARIA DE = FILIPPI, DEBORAH PERAZZOLI, ANNA LOSAPIO DI CRIMINALISSIMI RELAIS I MANDORL= I, METAMEDICINA E SERENDIPITA' MARA CARFAGNA (" SEMPRE DALLA CALDA FREGNA" = COME OGNI GIORNO LA NICKEVAMO), MICHELLE BONEV, MICHELLE HUNZICKER E LA SUA= AMANTE ^OCCULTISSIMAMENTE^ MASSONA, NAZIFASCISTA E FILO MAFIOSA GIULIA BON= GIORNO ( L' AVVOCATO PIU' AMATO DA COSA NOSTRA, CAMORRA E NDRANGHETA)... EN= SEMBLE ALLA CAMORRISTA FRANCESCA PASCALE ( LA VERA AMANTE DELLA HITLERIANA = CRIMINALE MARINA BERLUSCONI, ALTRO CHE AMANTE DEL PEDOFILO SPAPPOLA MAGISTR= ATI SILVIO BERLUSCONI... CHE, NON PER NIENTE, GIUSTAMENTE, IN PUBBLICO, TRA= TTA COSI' http://www.huffingtonpost.it/2014/09/21/pascale-braccetto-berlusc= oni_n_5856594.html ), SARA TOMMASI ( CHE NE ACCENNA QUI https://infosanni= o.wordpress.com/2011/02/09/sara-tommasi-basta-con-le-marchette-nel-giro-di-= marina-berlusconi/ ) E LA FANTASTICA PORNOSTAR LAETITIA BISSET ORA LAETIT= IA WAGNER ZAPPA, CHE NE SCRIVE ALTRETTANTO CHIARAMENTE QUI https://disqus.com/by/laetitiabissetmarinaberlusc/ ) QUELLO CHE MI FA INCAZZARE TANTO E' CHE NONOSTANTE QUESTI SIANO TUTTI INDIS= CUTIBILI FATTI, FATTI, FATTI, UNA BASTARDA DITTATURA NEO FRANCHISTA, NEO SA= LAZARIANA, NEO PINOCHETTIANA, NEO HITLERIANA, NEO MUSSOLINIANA, BASTARDISSI= MAMENTE NEO PIDUISTA: IMPONE SILENZIO TOTALE SU TUTTO QUESTO! BASTA BERLUSC= ONAZISTA E BERLUSCOMAFIOSA OMERTA'! BASTA, BASTA, BASTA, BASTA, BASTA. FACC= IAMO LA RIVOLUZIONE, VIVA IL MOVIMENTO 5 STELLE, RIVOLUZIONE, RIVOLUZIONE, = RIVOLUZIONE, RIVOLUZIONEEEEEEEEEEEEEEEEEEEEEEEEEEEEE!!! TUTTO IL MONDO SI UNISCA A NOI IN QUESTO CORO DA MEGA STADIO " PEDOFILO BER= LUSCONI PER SEMPRE FUORI DAI COGLIONI"! " MILLE RIVOLUZIONI CONTRO I STRAGI= STI BERLUSCONI"!!! RITORNELLO DI DOVUTISSIMA CANZONE CHE STIAMO PREPARANDO IO E LA MIA AMANTE = LESBICISSIMA SIMONA PREMOLI, ORA, PLEASE: "ITALIA DEGRADATA A BERLUSCONIA DEI NAZISTI, LAVA SOLDI MAFIOSI DAVIDE SERR= A, LUIGI BERLUSCONI, MARCO CARRAI E PAOLO BARRAI, SE NON LI SBATTI IN GALER= A, VEDRAI CHE MORIRAI ( E SE MORISSE QUESTA MERDA DI ITALIA DEGRADATISSIMA = A BERLUSCONIA, FACENDO COSI' RINASCERE UNA ITALIA VERA, INDIPENDENTE, ETICA= , DEMOCRATICA, PER BENE, VINCENTE, COME QUELLA DI SANDRO PERTINI ED OSCAR L= UIGI SCALFARO, SAREBBE SOLO UNA MERAVIGLIOSA COSA) AL PUNTO DI CUI ACCENNAVO ALL'INIZIO, ORA, PLEASE ... IL CIUCCIA E PRENDI MEGA CAZZI A GO GO LUIGI BERLUSCONI (BACIO RICCHIONESCH= ISSIMO QUI https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg ) NATO IN FIGHETTINA ARLESHEIM (CH) IL 27.9.1988.... L'OMOSESSUAL= E ^OCCULTO^ LUIGI BERLUSCONI https://it.blastingnews.com/tv-gossip/2017/07/gossip-luigi-berlusconi-e-omo= sessuale-ecco-come-ha-reagito-il-padre-001847471.html DI BASTARDAMENTE CRIMINALE ELIGOTECH AMSTERAM, BASTARDAMENTE CRIMINALE SOLD= O LTD LONDON E BASTARDAMENTE CRIMINALE BANCA MEDIOLANUM (CHE RICICLANO MONT= AGNE DI =E2=82=AC MAFIOSI, ESATTAMENTE COME FACEVA LA CRIMINALISSIMA BANCA = RASINI DI SUO NONNO, TOPO DI FOGNA LUIGI BERLUSCONI ....O COME FACEVA E FA = ORA PIU' CHE MAI, LA FININVEST DEL PEDOFILO DILANIANTE FALCONE E BORSELLINO= : SILVIO BERLUSCONI http://www.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commission= ate-berlusconi/ E DELLA CRIMINALISSIMA, HITLERIANA, ^OCCULTA" LESBICA MARINA BERLUSCONI ) INSIEME AL BERLUS-CO-RROTTO VERME MARCO CARRAI DI CGNAL, CREA NAZITECNOLOGI= CHE NUOVE OVRA E GHESTAPO! COL NOTO ANTI SEMITA, GIA' 3 VOLTE FINITO IN CAR= CERE, PAOLO BARRAI, NATO A MILANO IL 28.6.1965 ( FINITO IN CARCERE PURE IN = BRASILE, ED ANCHE PER PEDOFILIA OMOSESSUALE: INCULAVA LI I BAMBINI, NE SCRI= VEREMO PRESTO http://www.rotadosertao.com/images/fotos/fotos_noticias/testao.jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 )!= UNITI AL MEGA RICICLA SOLDI ALTRETTANTO CRIMINALI: CAROGNA SCHIFOSA, MEGA = FIGLIO E MARITO DI PUTTANONE, DAVIDE SERRA DI ALGEBRIS INVESTMENTS ( NON PE= R NIENTE, SOCIO DEI VERMI MEGA RICICLA SOLDI MAFIOSI: ENNIO DORIS, MASSIMO = DORIS, GIOVANNI PIROVANO ED OSCAR DI MONTIGNY DI BANCA MEDIOLANUM, COSANOST= RANUM, CAMORRANUM, NDRANGOLANUM, HITLERANUM)! E COL TUTTO CONNESSO ALL'ECON= OMISTA NOTORIAMENTE PEDERASTA E NAZISTA PAOLO CARDEN=C3=80, NATO A MACERATA= IL 2.19.1971 E RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, N= UMERO 41. DI CRIMINALISSIMA CARDENA' CONSULTING, BASATA A FALERONE, VIA MAR= IA MONTESSORI 6 63837 FALERONE - criminalissimo numero di telefono Tel: 073= 4.710786 - altro criminalissimo numero di telefono 3335915666, criminalissi= ma e mail info@cardenaconsulting.it criminalissima email formazione@cardena= consulting.it - P.IVA: 01840990442) E CRIMINALISSIMO BLOG VINCITORI E VINTI= . IL BASTARDO MALAVITOSO PAOLO CARDEN=C3=80, SEMPRE IN CRAVATTA STILE "COLL= ETTI LERCI", RICICLA SOLDI ASSASSINI DEI MEGA OMICIDA DI COSA NOSTRA, CRISA= FULLI DI MILANO https://it.wikipedia.org/wiki/Crisafulli_(clan) )!!! E A PROPOSITO DEL PRIMA CITATO, VERME CRIMINALISSIMO, PEDOFILO, ASSASSINO P= AOLO BARRAI NATO A MILANO IL 28.6.1965..... E' DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TERRORISTA = NAZISTA, RAZZISTA, LADRO, TRUFFATORE, SEMPRE FALSO, MEGA COCAINOMANE, MANDA= NTE DI TANTISSIMI OMICIDI, QUINDI, ASSASSINO PAOLO BARRAI! NOTO PEDOFIL-O-M= OSESSUALE GIA' FACENTE FILM PORNO CON BAMBINI, RAGAZZINI E... TENETEVI DURI= SSIMO, PLEASE, ANCHE CON CAVALLI, AD INIZIO ANNI 2000... COME PRESTO PROVER= EMO https://groups.google.com/forum/#!topic/android-chennai/l5zK3C9uv5k https://groups.google.com/forum/#!msg/it.politica/UBDEmF5BDdM/wfnwJkFsDAAJ https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai https://it-it.facebook.com/public/Truffati-Da-Paolo-Barrai http://code.activestate.com/lists/python-list/706609/ https://productforums.google.com/forum/#!topic/blogger/GTmd4a1TkxM http://www.caffe.ch/stories/Economia/37256_spregiudicati_affaristi_di_front= iera/ NATO A MILANO IL 28.6.1965. NONCHE' MEGA RICICLA SOLDI MAFIOSI E POLITICO-C= RIMINALI, OSSIA FRUTTO DI MEGA RUBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LA= DRONA ( 48 MILIONI RUBATI CHE POI SARANNO COME MINIMO 200 E NON "SOLO" 48 https://www.nextquotidiano.it/49-milioni-la-lega-ladrona-deve-allitalia/ http://www.ilsole24ore.com/art/notizie/2017-09-14/renzi-salvini-fa-morale-m= a-lega-ha-rubato-soldi-194056.shtml?uuid=3DAEWLnMTC http://espresso.repubblica.it/inchieste/2017/09/28/news/esclusivo-salvini-h= a-usato-i-soldi-della-truffa-di-bossi-1.311009 E DI MANDANTE DI CENTINAIA DI OMICIDI "MASCHERATI" DA FINTI MALORI, INCIDEN= TI, SUICIDI, COME, TANTO QUANTO, STRAGISTA SPAPPOLA MAGISTRATI, E NAZIFASCI= STA DITTATORE E PEDOFILO: SILVIO BERLUSCONI https://www.youtube.com/watch?v=3DFFxooBwjIIc http://www.antimafiaduemila.com/home/primo-piano/68166-berlusconi-soldi-e-b= oss-mafiosi-negli-appunti-di-falcone.html https://www.ilfattoquotidiano.it/2017/12/08/mafia-lappunto-dimenticato-scri= tto-da-giovanni-falcone-berlusconi-paga-i-boss-di-cosa-nostra/4027104/ http://www.repubblica.it/politica/2017/10/31/news/mafia_e_stragi_del_93_ber= lusconi_indagato-179825283/ https://ifarabutti.wordpress.com/tag/i-soldi-sporchi-di-berlusconi/ http://ricerca.repubblica.it/repubblica/archivio/repubblica/1984/10/04/ecco= -come-riciclavano-soldi-sporchi.html https://www.ilfattoquotidiano.it/2011/05/19/silvio-riciclava-i-soldi-della-= mafia/112167/ https://www.youtube.com/watch?v=3DvXsjFhA587I https://it.wikipedia.org/wiki/Banca_Rasini http://www.today.it/rassegna/berlusconi-mafia-emilio-fede.html )! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERRORISTA D= I ESTREMA DESTRA, SANGUINARIO ASSASSINO PAOLO BARRAI. NON PER NIENTE, GIA' = STATO IN GALERA 3 VOLTE. OPINIONI TUTTE TERRIFICANTI SU DI LUI! MEGA TRUFFA= TORE E MEGA RICICLA CASH ASSASSINO VIA CRIMINALISSIMA CRYPTOLAB S A (CH), C= RIMINALISSIMA CRYPTOPOLIS (CH), CRIMINALISSIMA BITINCUBATOR VENTURES (CH), = VIA CRIMINALISSIMA BLOCKCHAININVEST LUGANO (CH), VIA CRIMINALISSIMA WMO SAG= L LUGANO (CH), VIA CRIMINALISSIMA WORLD MAN OPPORTUNITIES LUGANO (CH), VIA = CRIMINALISSIMA WMO SA PANAMA, VIA CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCR= ATE 26 MILANO! NOTO PEDOFIL-O-MOSESSUALE SODOMIZZA BAMBINI! CACCIATO DA CITIBANK A SBERLE,= PER MEGA FRODI CHE LI FACEVA! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI D= I TANTISSIME PERSONE ( HA SUL GROPPONE 500 DENUNCE DI UOMINI E DONNE A CUI = HA AZZERATO TUTTO QUEL CHE AVEVANO, PERSONE DI MEZZA EUROPA, NON SOLO DI TU= TTA FASCIOMAFIOSA DITTATURA DI BERLUSCONIA-RENZUSCONIA-ETERNAMENTEP2ISTONIA= )! FALSO&LADRO&TRUFFATORE! DIFFAMA SUL WEB A FINI "BERLUSCONAZISTI E PADANA= ZISTI"! FONDATORE DEI NUOVI MEG-A-SSASSINI TERRORISTI DI ESTREMA DESTRA: "I= NAR SON TORNATI"! FONDATORE DEL, PROSSIMAMENTE, DI FREQUENTE OMICIDA: "KU = KLUK KLAN PADANO"! CONDANNATO AL CARCERE BEN TRE VOLTE, FRA CUI A MILANO ED= IN BRASILE ( A PORTO SEGURO: 8 ANNI E PURE PER PEDERASTIA OMOSESSUALE, RIP= ETO, PURE PER PEDERASTIA OMOSESSUALE)! MULTATO DA CONSOB 70.000 =E2=82=AC! = DESTABILIZZA L'ITALIA PER FILO NAZISTI SERVIZI SEGRETI DI MEZZO MONDO ( ITA= LIA, DICEVAMO, DA 30 ANNI, GIUSTISSIMAMENTE, NAZIONE SCHIFATA IN TUTTO IL M= ONDO, IN QUANTO FASCIOMAFIOSA DITTATURA DI BERLUSCONIA-RENZUSCONIA-ETERNAME= NTEP2ISTONIA..NON PER NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITALIA DA = SECOLI, DALLA TIRANNI-A-SSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIAT, PI= RELLI, LUXOTTICA, MERLONI, PARMALAT, QUASI TUTTA LA MODA, QUASI TUTTO L' AL= IMENTARE, OLTRE CHE MIGLIAIA E MIGLIAIA DI ALTRE... E CHE SIA CHIARO PLS, C= HE IDDIO BENEDICA I GRANDI PM CHE NON SOPPORTANO IL CANCRO DEL MONDO INTERO= , SILVIO BERLUSCONI... COME HENRY WOODCOCK, ILDA BOCASSINI, NINO DI MATTEO,= ROBERTO SCARPINATO E CHIUNQUE ALTRO DI QUESTA AMMIREVOLISSIMA CATEGORIA)! FA CRIMINI SU CRIMINI E NAZI-ST-ALKING, IL MANDANTE DI OMICIDI, IL VERME AS= SASSINO PAOLO PIETRO BARRAI! SU INTERNET! SU ORDINE DEI STRAGISTI, PEDOFILI= SILVIO BERLUSCONI, PAOLO BERLUSCONI ED UBALDO LIVOLSI DI FININVEST ( CHE D= A ANNI FAN GLI ADOLPH HITLER MISTI AD AL CAPONE DEL WEB, ANCHE, MA DI CERTO= , NON SOLO, CON QUEL VERME SCHIFOSO DI GIULIO OCCHIONERO http://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhionero= _chi_sono_i_due_arrestati-155752442/ http://roma.repubblica.it/cronaca/2017/07/17/news/roma_-171015653/ ). INNEGGIANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GRAND= ISSIMAMENTE FECE CON FALCONE E BORSELLINO"! PAROLE DETTE CENTO VOLTE DALL' = ASSASSINO PAZZO, MEGA COCAINOMANE, NAZISTA PAOLO PIETRO BARRAI NATO A MILAN= O IL 28.6.1965! ORGANIZZANTE LA "SUICIDATA KILLER" DI DI DAVID ROSSI DI MONTE PASCHI, CREDE= TECI O MENO, INSIEME AL MANAGEMENT SIA DI MONTE PASCHI CHE DI BANCA MEDIOLA= NUM ( VIA MASSONERIE ASSASSINE CHE PRESTO, QUI SOTTO, MENZIONEREMO)! MA ORA... VAMONOS BABIES, VAMONOS, VAMONOS, LET'S GO...... E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZISTA, RAZZISTA, LADRO, TRUFFATORE, SEMPRE FALSO, MEGA COCAINOMAN= E, MANDANTE DI TANTI OMICIDI, QUINDI BASTARDO ASSASSINO PAOLO BARRAI! NATO = A MILANO IL 28.6.1965. NONCHE' MEGA RICICLA SOLDI MAFIOSI E POLITICO-CRIMIN= ALI, OSSIA FRUTTO DI MEGA RUBERIE E MEGA MAZZETTE, TARGATE LEGA LADRONA ( 4= 8 MILIONI DI EURO RUBATI, CHE POI SON ALMENO 60 SE NON 200, I MILIONI DI EU= RO STRA RUBATI https://www.nextquotidiano.it/49-milioni-la-lega-ladrona-deve-allitalia/ http://www.ilsole24ore.com/art/notizie/2017-09-14/renzi-salvini-fa-morale-m= a-lega-ha-rubato-soldi-194056.shtml?uuid=3DAEWLnMTC http://espresso.repubblica.it/inchieste/2017/09/28/news/esclusivo-salvini-h= a-usato-i-soldi-della-truffa-di-bossi-1.311009 E DI MANDANTE DI CENTINAIA DI OMICIDI "MASCHERATI" DA FINTI MALORI, INCIDEN= TI, SUICIDI, COME, TANTO QUANTO, STRAGISTA SPAPPOLA MAGISTRATI, NAZIFASCIST= A DITTATORE, NONCHE' ACCLARATISSIMO PEDOFILO: SILVIO BERLUSCONI https://www.youtube.com/watch?v=3DFFxooBwjIIc http://www.antimafiaduemila.com/home/primo-piano/68166-berlusconi-soldi-e-b= oss-mafiosi-negli-appunti-di-falcone.html http://www.repubblica.it/politica/2017/10/31/news/mafia_e_stragi_del_93_ber= lusconi_indagato-17982528 https://ifarabutti.wordpress.com/tag/i-soldi-sporchi-di-berlusconi/ http://ricerca.repubblica.it/repubblica/archivio/repubblica/1984/10/04/ecco= -come-riciclavano-soldi-sporchi.html https://www.ilfattoquotidiano.it/2011/05/19/silvio-riciclava-i-soldi-della-= mafia/112167/ https://www.youtube.com/watch?v=3DvXsjFhA587I https://it.wikipedia.org/wiki/Banca_Rasini http://www.today.it/rassegna/berlusconi-mafia-emilio-fede.html )! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERRORISTA D= I ESTREMA DESTRA, SANGUINARIO ASSASSINO PAOLO BARRAI. ARTEFICE DI MOLTE SPA= RIZIONI COLLEGATE AD OMICIDI SATANISTI, SPECIE IN MARCHE, PIEMONTE E LOMBAR= DIA ( IN UNIONE CON ALTRETTANTI NOTI SATANISTI ASSASSINI PAOLO E STEFANO CA= RDEN=C3=80 DI CRIMINALISSIMA CARDEN=C3=80 CONSULTING FALERONE E CON NOTE SA= TANISTE ASSASSINE ELISA COGNO E PIERA CLERICO DI ALBA DI CRIMINALISSIMA FRU= IMEX E DI FONDAZIONE FERRERO. http://www.cronachemaceratesi.it/2015/05/25/allarme-persone-scomparse-163-a= -macerata-500-nelle-marche/661329/ https://www.corriereadriatico.it/marche/marche_persone_scomparse_minori-660= 674.html http://www.lastampa.it/2015/08/01/cuneo/scomparsi-da-anni-resta-il-mistero-= Q1u3ZmsLrLVEH43wjtxC8N/pagina.html https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ http://www.nuovasocieta.it/il-diavolo-nella-citta-della-sindone-intervista-= ad-un-satanista-non-siamo-solo-messe-nere/ ) TERRORISTA NAZISTA, RAZZISTA, LADRO, TRUFFATORE, SEMPRE FALSO, MEGA COCAINO= MANE, MANDANTE DI TANTI OMICIDI, QUINDI, BASTARDO ASSASSINO PAOLO BARRAI: G= IA' STATO IN GALERA 3 VOLTE. MEGA TRUFFATORE, CRIMINALE DI PIU' EFFERATA SPECIE PAOLO BARRAI MEGA RICICLA CASH ASSASSINO, COME DI LEGA LADRONA E SPAPPOLA MAGISTRATI, PE= DOFILO SILVIO BERLUSCONI - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA BITINCUBATOR VENTURES (CH), - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA CRYPTOPOLYS S. A. (CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA CRYPTOLAB S. A. (CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA BITMAX.CH (CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA EIDOO CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA BLOCKCHAININVEST CH) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA WMO SAGL LUGANOCH) . VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA WORLD MAN OPPORTUNITIES LUGANO (CH= ) - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA WMO SA PANAMA - VIA CRIMINALISSIMA BHB, CRIMINALISSIMA NETWORKBLOCKCHAINLABIT E CRIMINALI= SSIMA ASSOB.IT DI ALTRETTANTO NOTO TERRORISTA NAZIFASCISTA, MEGA RICICLA SO= LDI MAFIOSI E MANDANTE DI OMICIDI: GIACOMO ZUCCO http://es.listoso.com/android-developers/2017-08/msg00208.html https://groups.google.com/forum/#!topic/android-chennai/t9Ob_1wXFd8 - VIA LAVA SOLDI MAFIOSI, CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 M= ILANO DI SUO PADRE, GIA' CONDANNATO AL CARCERE TANTE VOLTE, IN PASSATO: PER= PEDOFILIA, TRUFFA E RICICLAGGIO DI PROVENTI KILLER.. VERME DELINQUENTISSIM= O, SEMPRE DENTRO E FUORI SAN VITTORE: VINCENZO BARRAI NATO A MILANO IL IL 3= .5.1938 E RESIDENTE A MILANO IN VIA PADOVA 282! http://markmail.org/message/lxrvezqxbmpoawcd STO VERME DEPRAVATO E PAZZO DI PAOLO PIETRO BARRAI NATO A MILANO IL 28.6.19= 65 E' ANCHE UN NOTO PEDOFIL-O-MOSESSUALE SODOMIZZA BAMBINI E RAGAZZINI! CAC= CIATO, FRA L'ALTRO, DA CITIBANK, A SBERLE ( E FATTO CONDANNARE AL CARCERE, = COME PRIMA CITATO, DA CITIBANK) PER MEGA FRODI E TRUFFE CHE LI LO STESSO FA= CEVA ( DA GRANDE BANCHIERE GIULIO DI CERBO, POI, NON PER NIENTE, FATTO AMMA= ZZARE DA PAOLO BARRAI VIA SUOI CONTATTI NAZIFASCISTI CHE HA PRESSO LA CIA, = LA NSA E SERVIZI SEGRETI STILE GLADIO, DI QUELLA MERDA DITTATORIALE CHE E' = BERLUSCONIA-RENZUSCONIA, AHIME', EX REPUBBLICA DEMOCRATICA ITALIANA)! IL FI= UNZIONARIO DI CITIBANK, IN GROSSI GUAI, A SEGUITO DI MEGA LADROCINI FATTI D= A PAOLO BARRAI E PIETRO TERENZIO, COME DA FINALE DI QUESTO ARTICOLO DI REPU= BBLICA, ERA PROPRIO IL VERME SANGUINARIO PAOLO PIETRO BARRAI http://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19/maxi= -evasione-da-400-miliardi-terenzio-sotto-torchio.html PER NON DIRE DI QUANTO L' AZZERA RISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI, = SBAGLI SEMPRE IN BORSA! AZZERI I RISPARMI DI TANTISSIME PERSONE ( HA SUL GR= OPPONE 500 DENUNCE DI UOMINI E DONNE A CUI HA ANNIENTATO TUTTO QUEL CHE AVE= VANO ... DI MEZZA EUROPA, NON SOLO DI TUTTA FASCIOMAFIOSA DITTATURA DI BERL= USCONIA-RENZUSCONIA-ETERNAMENTEP2ISTONIA)! SEMPRE FALSO&LADRO&TRUFFATORE! D= IFFAMA SUL WEB A FINI "BERLUSCONAZISTI E PADANAZISTI"! FONDATORE DEI NUOVI = MEG-A-SSASSINI TERRORISTI DI ESTREMA DESTRA: "I NAR SON TORNATI"! FONDATORE= DEL, PROSSIMAMENTE, DI FREQUENTE OMICIDA: "KU KLUK KLAN PADANO"! CONDANNAT= O AL CARCERE BEN TRE VOLTE ( SPECIE, MA NON SOLO) A MILANO ED IN BRASILE ( = A PORTO SEGURO: 8 ANNI, PER RICICLAGGIO DI SOLDI MAFIOSI EFFETTUATO PRESSO = HSBC http://it.cultura.linguistica.narkive.com/XV3Bw8gY/sono-simona-premoli-ex-a= mante-lesbica-di-marina-berlusconi-e-per-ben-13-anni-e-13-ani-che-mi-sono:i= .2.10.thumb TRUFFA, PROPOGANDA NAZISTA E RAZZISTA, LADROCINIO, MINACCE, ESTORSIONE E PU= RE PER PEDERASTIA OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216https://groups.google.com/forum/#!msg/comp.lang.python/mq4dXDzd-MQ/Veuwn= pj7BgAJ http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg )! MULTATO DA CONSOB BEN 70.000 =E2=82=AC ( ORA, IL VISCIDO BERLUSCONICCHIO GI= USEPPE VEGAS, VISCIDO BERLUSCONICCHIO TANTO QUANTO IL CRIMINALE PAOLO BARRA= I STESSO, SU RICHESTA DEL PEDOFILO MAXIMO DI ARCORE-HARDCORE, SILVIO BERLUS= CONI, STA FACENDO IMBOSCARE LA NOTIZIA, SU INTERNET, MA ECCO I LINKS ORIGIN= ALI A PROPOSITO http://www.bluerating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un= -ex-promotore-che-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://groups.google.com/forum/#!topic/qc.politique/XjdEpV1zGxY STO VERME DI PAOLO BARRAI, PER NON RISCHIARE DI PASSARE DECENNI A SAN VITTO= RE, COME ACCADUTO AL PADRE PEDOFILO VINCENZO BARRAI, E' QUINDI SCAPPATO IN = SVIZZERA. OVE PERO', IN CANTON TICINO E CANTON GRIRIONI E' SOTTO 22 INCHIES= TE, PER QUESTO, PER EVITARE MANETTE ELVETICHE, ORA INTENDE SCAPPARE A LONDR= A ( VEDI FINALE DI QUESTO SUO, COME AL SOLITO, DISONESTISSIMO E PUZZOLENTIS= SIMAMENTE FASCISTA ARTICOLO http://ilpunto-borsainvestimenti.blogspot.mx/20= 17/12/trumps-il-miglior-presidente-degli.html ) FA CRIMINI SU CRIMINI E NAZI-ST-ALKING, IL MANDANTE DI OMICIDI, IL VERME AS= SASSINO PAOLO PIETRO BARRAI! SU INTERNET! SU ORDINE DEI STRAGISTI, PEDOFILI= SILVIO BERLUSCONI, PAOLO BERLUSCONI, ENNIO DORIS, MASSIMO DORIS, OSCAR DI = MONTIGNY ED UBALDO LIVOLSI ( CHE DA ANNI FANNO GLI ADOLPH HITLER MISTI AD A= L CAPONE DEL WEB, ANCHE, MA DI CERTO, NON SOLO, CON QUEL VERME SCHIFOSO DI = GIULIO OCCHIONERO http://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhionero= _chi_sono_i_due_arrestati-155752442/ http://roma.repubblica.it/cronaca/2017/07/17/news/roma_-171015653/ ). INNEGGIANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GRAND= ISSIMAMENTE FECE CON FALCONE E BORSELLINO"! PAROLE DETTE CENTO VOLTE DALL' = ASSASSINO PAZZO, MEGA COCAINOMANE, NAZISTA, OMICIDA PAOLO PIETRO BARRAI NAT= O A MILANO IL 28.6.1965! ORGANIZZANTE LA "SUICIDATA KILLER" DI DAVID ROSSI DI MONTE PASCHI, CREDETEC= I O MENO, INSIEME AL MANAGEMENT SIA DI MONTE PASCHI CHE DI BANCA MAFIOLANUM= , NAZISTANUM, MEDIOLANUM ( VIA MASSONERIA ASSASSINA DI SILVIO BERLUSCONI, C= HIAMATA IL DRAGO, DI CUI E' PARTE, COME NE SON PARTE I VERTICI DI MONTE PAS= CHI E DI BANCA MAFIOLANUM, NAZISTANUM, MEDIOLANUM .. LOGGIA BERLUSCONAZISTA= " IL DRAGO" DI ARCORE-HARDCORE, ASSOLUTA NUOVA P2, ESATTAMENTE SANGUINARIA= E KILLER COME ERA LA P2 https://it-it.facebook.com/notes/contro-linformazione-manipolata/un-capo-ma= ssone-rivela-berlusconi-ha-fondato-la-sua-loggia-%C3%A8-l%C3%AC-che-si-deci= de-no/437022599774/ http://www.ilsussidiario.net/News/Politica/2017/11/2/SILVIO-BERLUSCONI-P2-E= -MAFIA-Le-inchieste-sulle-stragi-del-1993-e-la-macchina-del-fango/790452/ )= ! MA ORA... VAMONOS BABIES, VAMONOS, VAMONOS, LET'S GO, LET'S GOOOOOO...... - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA EIDOO, DIRETTA DAL VERME MALAVITOSO, NDRANGHETISTA DI REGGIO CALAB= RIA NATALE M. FERRARA O VERME MALAVITOSO, NDRANGHETISTA DI REGGIO CALABRIA = NATALE FERRARA CHE SIA http://rbnsn.com/pipermail/info-vax_rbnsn.com/2015-May/077000.html https://groups.google.com/forum/#!topic/android-chennai/l5zK3C9uv5k=20 https://groups.google.com/forum/#!msg/it.politica/UBDEmF5BDdM/wfnwJkFsDAA ( EXTREMELY CRIMINAL EIDOO.... YOUR VERY HOODLUM ASSET EXPERIENCE, MEGA MAF= IA MONEY LAUNDERER FOR COSA NOSTRA, NDRANGHETA, CAMORRA AND ASSASSIN RUSSIA= N GANSGTERS, NOT FOR NOTHING, CLOSE TO PRINCIPAL OF HUNDREDS OD MURDERS AND= SLAUGHTERS: ASCERTAINED PEDOPHILE SILVIO BERLUSCONI) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA CRYPTOPOLYS E CRYPTOLAB S A http://www.rotadosertao.com/images/fotos/fotos_noticias/testao.jpg https://pbs.twimg.com/media/CIB3862WcAA8F7c.png https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg http://www.caffe.ch/stories/Economia/37256_spregiudicati_affaristi_di_front= iera/ https://productforums.google.com/forum/#!topic/blogger/GTmd4a1TkxM ( OVE MEGA RICICLA SOLDI MAFIOSI COL NOTO VERME KUKLUKLANISTA, NAZIFASCISTA= , MEGA RICICLA SOLDI MAFIOSI, BASTARDO VERO ARON CAMPONOVO DI MALAVITOSISSI= MA TANTO QUANTO IBEX CAPITAL LTD, MALAVITOSISSIMA TANTO QUANTO MONCLER SUIS= SE LTD, MALAVITOSISSIMA TANTO QUANTO IBEX SERVICES LTD http://www.moneyhouse.ch/it/p/aron-camponovo ED INSIEME AL NOTO RAZZISTA, KUKLUKLANISTA, HITLERIANO, MEGA RICICLA SOLDI = DI MALAVITE DI TUTTO IL MONDO E PURE ACCERTATO PEDOFILO: OLIVER CAMPONOVO D= I CAMPONOVO STRATEGY http://www.moneyhouse.ch/p/oliver-camponovo TUTT'UNO CON LA NDRANGHETA, INSIEME, BEN APPUNTO, AL PEZZO DI MERDA ASSASSI= NO, CRIMINALISSIMO PAOLO PIETRO BARRAI https://www.pressreader.com/switzerland/laregione/20171207/281874413739928 http://www.giornaledelticino.ch/41167/soldi-%E2%80%9Ctriangolati%E2%80%9D-d= ella-ndrangheta-due-condanne-bellinzona https://www.cdt.ch/ticino/bellinzona/191575/mafia-in-ticino-nuova-condanna https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ https://www.laregione.ch/cantone/mendrisiotto/1228182/affari-della--ndrangh= eta-in-ticino--alla-sbarra-l-uomo-di-fiducia-della-cosca--l-ex-municipale-d= i-chiasso-e-la-moglie-del-fratello-del-boss http://www.area7.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della-ndra= ngheta-29f7ee00 ) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA CRYPTOLAB SA (CH) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA BITMAX.CH - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI BLOCKC= HAIN INVEST (CH) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA BIGBITGOLD E CRIMINALISSIMA BIGBIT (CH) -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA, MEGA RICICLA SOLDI MAFIOSI WORLD MAN OPPORTUNITIES LUGANO (CH) https://www.moneyhouse.ch/it/company/world-man-opportunities-sagl-176913463= 31 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA, SEMPRE MEGA RICICLA SOLDI MAFIOSI, BITINCUBATOR VENTURES GRONO (CH= ) ( AFFIANCATO IN QUESTO DA QUEL NOTO MALAVITOSO, RICICLA SOLDI ASSASSINI DI = CLAUDIO LEVRINI DI BLEVIO https://www.moneyhouse.ch/it/person/levrini-claudio-133823793501 DI MALAVITOSA BITCOIN FOUNDATION, E, BEN APPUNTO, DI CRIMINALISSIMA BITINCU= BATOR VENTURES GRONO https://www.moneyhouse.ch/en/company/bitincubator-ventures-sa-12554072241 = ) -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA ASSOB.= IT DI ALTRETTANTO NOTO TERRORISTA NAZIFASCISTA, MEGA RICICLA SOLDI MAFIOSI = VIA BITCOINS E MANDANTE DI OMICIDI: GIACOMO ZUCCO http://es.listoso.com/android-developers/2017-08/msg00208.html https://medium.com/@giacomozucco83 -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA WMO SA PANAMA ( https://plus.google.com/108961714786994835238/posts/9zrBkh9csJZ https://www.scribd.com/doc/307086915/Riccacosta-S-A-PAOLO-BARRAI-REGISTRO-P= UBLICO-PANAMA-Mercato-Libero POSTA INSIEME ALLE FAMOSISSIME IN PANAMA CITY COME "PUTAS MEGA LAVA DINERO = ASESINO" DIGNA PEREZ MARTINEZ Y TATIANA MAGDALENA BARAHONA ... BEN NOTA IN = TUTTO MONDO COME TATIANA MAGDALENA "LA BALDRACCONA" AVENDO LAVORATO PER DEC= ENNI IN NIGHT CLUBS COLOMBIANI ED AVENDO FATTO IN COLOMBIA MIGLIAIA DI FILM= PORNO) IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINAL= ISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO DI SUO PADRE, GIA' CONDANNAT= O AL CARCERE TANTE VOLTE, IN PASSATO: PER PEDOFILIA, TRUFFA E RICICLAGGIO D= I PROVENTI KILLER.. VERME DELINQUENTISSIMO, SEMPRE DENTRO E FUORI SAN VITTO= RE: VINCENZO BARRAI NATO A MILANO IL IL 3.5.1938 E RESIDENTE A MILANO IN VI= A PADOVA 282! http://markmail.org/message/lxrvezqxbmpoawcd -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI FORZA I= TALIA MAFIOSA, FORZA ITALIA CAMORRISTA, FORZA ITALIA NDRANGHETISTA... DE VE= RDAD http://www.globalist.it/politics/articolo/2009525/il-pm-forza-italia-punto-= di-riferimento-di-cosa-nostra-ndrangheta-e-camorra.html https://www.ilfattoquotidiano.it/2017/07/26/stragi-pm-di-reggio-le-mafie-si= -fermarono-quando-trovarono-in-forza-italia-la-struttura-con-cui-relazionar= si/3756080/ IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI LEGA LAD= RONA ( PER LA QUALE IMBOSCA ALL' ESTERO I FAMOSI 48-60 MILIONI DI EURO RUBA= TI DALLA STESSA http://espresso.repubblica.it/inchieste/2017/09/28/news/esclusivo-salvini-h= a-usato-i-soldi-della-truffa-di-bossi-1.311009 ) -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI QUOTIDI= ANO IL GIORNALE E QUOTIDIANO LIBERO ( MA NAZISTA), OVE FA LE TRAME PIU' ASS= ASSINE, COL FIGLIO DI PUTTANA HITERLIANO E NAZI-ST-ALKER PAOLO BERLUSCONI, = COL FIGLIO DI PUTTANA HITERLIANO E NAZI-ST-ALKER ALESSANDRO SALLUSTI, COL F= IGLIO DI PUTTANA HITERLIANO E NAZI-ST-ALKER PIETRO SENALDI, COL FIGLIO DI P= UTTANA HITERLIANO E NAZI-ST-ALKER VITTORIO FELTRI, COL FIGLIO DI PUTTANA HI= TERLIANO E NAZI-ST-ALKER FRANCO BECHIS E COL FIGLIO DI PUTTANA HITERLIANO E= NAZI-ST-ALKER FAUSTO CARIOTI! - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI TANTIS= SIMI GRUPPI TERRORISTI DI ESTREMA DESTRA ED ANTI SEMITI ( TIPO I DA LUI APP= ENA FONDATI " I NAR SON TORNATI" -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI VARI GR= UPPI ASSASSINI DEL KU KLUK KLAN - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI SANGUI= NARIA MASSONERIA ROSACROCIANA DEL BASTARDO KILLER CLAUDIO MAZZUCCO ( NON SIAMO PER NULLA ANTI MASSONICI A PRESCINDERE, PENSIAMO APPIENO CHE LA= MASSONERIA ABBIA AVUTO FRA SE ALCUNI TRA I MIGLIORI UOMINI DI TUTTI I TEMP= I, COME GALILEO GALILEI, MAHATMA GANDHI, MARTIN LUTHER KING E PARECCHI ALTR= I.. https://labuonastrada.wordpress.com/2014/11/21/secondo-gioele-magaldi-marti= n-luther-king-era-massone/ MA I MASSONI ASSASSINI, NAZIFASCISTI E FILO MAFIOSI, ALIAS I MASSONI DI STA= MPO "BERLUSCONAZISTA E PADANAZISTA" CI FAN STRA SCHIFO E NE SIAM FERISSIMI = BOUT IT .. QUI NE PARLA GIULIANO DI BERNARDO STESSO https://www.youtube.com/watch?v=3DYA-ryJ-2kPU NOI SCRIVIAMO DI FATTI, FATTI= , FATTI.. " FATTI QUOTIDIANI" O MENO... NON DI CHIACCHERE AT ALL) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI "BERLU= SCONAZIFASCISTA" GRAN LOGGIA D'ITALIA DEL MEGA RICICLA SOLDI MAFIOSI ANTONI= O BINNI ( NON SIAMO PER NULLA ANTI MASSONICI A PRESCINDERE, PENSIAMO APPIEN= O CHE LA MASSONERIA ABBIA AVUTO FRA SE ALCUNI TRA I MIGLIORI UOMINI DI TUTT= I I TEMPI, COME GALILEO GALILEI, MAHATMA GANDHI, MARTIN LUTHER KING E PAREC= CHI ALTRI.. https://labuonastrada.wordpress.com/2014/11/21/secondo-gioele-magaldi-marti= n-luther-king-era-massone/ MA I MASSONI ASSASSINI, NAZIFASCISTI E FILO MAFIOSI, ALIAS I MASSONI DI STA= MPO "BERLUSCONAZISTA E PADANAZISTA" CI FAN STRA SCHIFO E NE SIAM FERISSIMI = BOUT IT .. QUI NE PARLA GIULIANO DI BERNARDO STESSO https://www.youtube.com/watch?v=3DYA-ryJ-2kPU NOI SCRIVIAMO DI FATTI, FATTI= .. " FATTI QUOTIDIANI" O MENO... NON DI CHIACCHERE AT ALL) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA SAN= GUINARISSIMA LOGGIA "SATA-N-AZISTA", ORGANIZZANTE DOZZINE DI STRAGI E CENTI= NAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI ED INCIDENTI, LOGGIA PE= RSONALE DI SPAPPOLA MAGISTRATI E PEDOFILO MAXIMO SILVIO BERLUSCONI, CHIAMAT= A " IL DRAGO ( DI ARCORE-HARDCORE) https://it-it.facebook.com/notes/contro-linformazione-manipolata/un-capo-ma= ssone-rivela-berlusconi-ha-fondato-la-sua-loggia-=C3=A8-l=C3=AC-che-si-deci= de-no/437022599774/ http://www.centroparadesha.it/ude/articoli/1156-549-la-loggia-del-drago-di-= galeazzi-pinotti ( NON SIAMO PER NULLA ANTI MASSONICI A PRESCINDERE, PENSIAMO APPIENO CHE LA= MASSONERIA ABBIA AVUTO FRA SE ALCUNI TRA I MIGLIORI UOMINI DI TUTTI I TEMP= I, COME GALILEO GALILEI, MAHATMA GANDHI, MARTIN LUTHER KING E PARECCHI ALTR= I.. https://labuonastrada.wordpress.com/2014/11/21/secondo-gioele-magaldi-marti= n-luther-king-era-massone/ MA I MASSONI ASSASSINI, NAZIFASCISTI E FILO MAFIOSI, ALIAS I MASSONI DI STA= MPO "BERLUSCONAZISTA E PADANAZISTA" CI FAN STRA SCHIFO E NE SIAM FERISSIMI = BOUT IT .. QUI NE PARLA GIULIANO DI BERNARDO STESSO https://www.youtube.com= /watch?v=3DYA-ryJ-2kPUNOI SCRIVIAMO DI FATTI, FATTI, FATTI.. " FATTI QUOTID= IANI" O MENO... NON DI CHIACCHERE AT ALL) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI GRAN L= OGGIA ITALIA MASSONICA DEL MALAVITOSO BANCHIERE GIUSEPPE SABATO DI BANCA ES= PERIA ( GRUPPO BANCARIO PARZIALMENTE DELLO SPAPPOLA MAGISTRATI, NONCHE' ACC= LARATISSIMO PEDOFILO SILVIO BERLUSCONI) https://www.avvocatisenzafrontiere.it/?p=3D1788 https://groups.google.com/forum/#!topic/mozilla.reps.council/n0UahGyuFVw ( NON SIAMO PER NULLA ANTI MASSONICI A PRESCINDERE, PENSIAMO APPIENO CHE LA= MASSONERIA ABBIA AVUTO FRA SE ALCUNI TRA I MIGLIORI UOMINI DI TUTTI I TEMP= I, COME GALILEO GALILEI, MAHATMA GANDHI, MARTIN LUTHER KING E PARECCHI ALTR= I.. https://labuonastrada.wordpress.com/2014/11/21/secondo-gioele-magaldi-marti= n-luther-king-era-massone/ MA I MASSONI ASSASSINI, NAZIFASCISTI E FILO MAFIOSI, ALIAS I MASSONI DI STA= MPO "BERLUSCONAZISTA E PADANAZISTA" CI FAN STRA SCHIFO E NE SIAM FERISSIMI = BOUT IT .. QUI NE PARLA GIULIANO DI BERNARDO STESSO https://www.youtube.com= /watch?v=3DYA-ryJ-2kPUNOI SCRIVIAMO DI FATTI, FATTI, FATTI.. " FATTI QUOTID= IANI" O MENO... NON DI CHIACCHERE AT ALL) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA MAL= AVITOSA ELIGOTECH, DELL'OMOSESSUALE ^OCCULTO^, SEMPRE SCOPATO SBORRATO IN C= ULO: LUIGI BERLUSCONI ( MA TRA IL SILENZIO NAZISTA CHE IL PEDOFILO SPAPPOLA= MAGISTRATI SILVIO BERLUSCONI IMPONE) http://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA CRI= MINALISSIMA, MEGA RICICLA CASH MAFIOSO, SOLDO LTD ROMA O CRIMINALISSIMA, ME= GA RICICLA CASH MAFIOSO, SOLDO FINANCIAL SERVICES LTD DEI VERMI MALAVITOSI = STESSI LUIGI BERLUSCONI ED ANDREA GAUDENZI https://beta.companieshouse.gov.uk/company/09233754 https://www.agimeg.it/politica/giochi-luigi-berlusconi-andrea-gaudenzi-inve= stono-soldo-ltd-societa-costituita-gualandri-fondatore-gioco-digitale ( NIPOTE DEL TOPO DI FOGNA LUIGI BERLUSCONI, A SUA VOLTA, BESTIA CRIMINALIS= SIMA A " KAPO' " DELLA CHIUSA PER MEGA RICICLAGGIO DI SOLDI MAFIOSI, BANCA = RASINI http://www.beveraedintorni.com/lettere-deliranti/3382-la-banca-rasini-sciol= ta-per-mafia-e-la-famiglia-berlusconi.html http://temi.repubblica.it/micromega-online/mafia-politica-e-affari-sette-do= mande-al-cavaliere/?printpage=3Dundefined http://www.uonna.it/ragnatela4.htm E FIGLIO DI NOTO PEDOFILO SILVIO BERLUSCONI https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ http://www.elafter.com/foro/showthread.php?t=3D948509 https://gamefaqs.gamespot.com/boards/261-politics/66554542 https://www.youtube.com/watch?v=3DDeNisVOfssc FIGLIO DI NOTO MANDANTE DI DOZZINE DI STRAGI SILVIO BERLUSCONI http://www.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commission= ate-berlusconi/ http://www.ilfattoquotidiano.it/2017/06/09/graviano-e-berlusconi-peter-gome= z-ricostruisce-le-stragi-del-1993/3648613/ FIGLIO DI NOTO MANDANTE DI CENTINAIA E CENTINAIA DI OMICIDI MASCHERATI DA F= INTI SUICIDI, MALORI ED INCIDENTI: SILVIO BERLUSCONI http://www.ilsecoloxix.it/p/genova/2012/07/27/APxMHy2C-scrivere_berlusconi_= assassino.shtml http://www.pmli.it/sismicolpivanemiciberlusconi.htm ) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA MAL= AVITOSISSIMA CGNAL DEL PEZZO DI MERDA BERLUS-CO-RROTTTISSIMO MARCO CARRAI https://www.huffingtonpost.it/2015/06/17/carrai-luigi-berlusconi-fanno-affa= ri_n_7601310.html http://www.liberoquotidiano.it/news/politica/12333673/marco-carrai-inchiest= a-consip-fondato-club-forza-italia.html http://www.liberoquotidiano.it/news/politica/11905690/silvio-berlusconi-mar= co-carrai-societa-.html http://espresso.repubblica.it/plus/articoli/2016/10/17/news/marco-carrai-l-= amico-che-mette-matteo-renzi-nei-guai-1.285898 - IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA = MERDA FASCIOMAFIOSA E MEGA RICICLA SOLDI LERCI DI ENNIO DORIS E MASSIMO DOR= IS: BANCA MEDIOLANUM, COSANOSTRANUM, CAMORRANUM, NDRANGOLANUM, LAVALAVAPERC= OCALEROSCOLOMBIANUM, NAZISTANUM http://ricerca.repubblica.it/repubblica/archivio/repubblica/2009/01/24/rici= claggio-arrestato-sciume-avvocato-della-finanza-milanese.html?ref=3Dsearch https://www.ilfattoquotidiano.it/2013/04/02/fisco-chiede-a-mediolanum-344-m= ilioni-riflettori-sulle-operazioni-in-irlanda/549322/ http://www.repubblica.it/cronaca/2010/10/18/news/quella_villa_d_avanzo-8169= 812/ -IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIM= INALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO http://google-guice.narkive.com/aPNDvjEA/criminali-bastardi-di-bsi-italia-s= rl-via-socrate-26-milano-paolo-barrai-e-vincenzo-barrai-noti RAPPRESENTATA DA UN NOTO PEDERASTA E MEGA RICICLA SOLDI MAFIOSI, CONDANNATO= IN ANNI PASSATI A DIVERSI ANNI DI GALERA PER TUTTO IL SOPRA CITATO: VERME = BASTARDISSIMO VINCENZO BARRAI http://markmail.org/message/hbiib64yeyqpvaei ABITANTE IN VIA PADOVA 282 A MILANO E NATO A MILANO IL 3.5.1938 - IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI, FINIT= O, "APPENA APPENA" 3 VOLTE IN GALERA ( UNA DI QUESTE 3 VOLTE, FINITO IN GAL= ERA IN BRASILE E PURE PER PEDOFILIA OMOSESSUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg TANTO PER INIZIARE..NELLA NAZIMAFIOSA DITTATURA DI BERLUSCONIA, VIA FINECO,= LAVA CASH ASSASSINO, VIA PROMOTORE FINANZIARIO VICINISSIMO PURE A NDRANGHE= TA, CAMORRA E COSA NOSTRA: ALDO ACQUISTAPACE DI CREDIT SUISSE MILANO https://groups.google.com/forum/#!topic/alt.comp.anti-virus/Iq8tv8n8wps (fratello del noto delinquente Marco Acquistapace di Londra, facente miglia= ia e migliaia di efferati crimini via Synergy Global Management Limited....= trattasi di un altro colletto mega lercio, super riciclante soldi mafiosi = provenienti da killer di Puglia, Sicilia, Calabria, Campania, ma anche da C= olombia, Romania ed Albania... da anni ed anni al centro di centinaia e cen= tinaia di scandali, truffe e ruberie di ogni.. http://corrieredelmezzogiorno.corriere.it/bari/notizie/cronaca/2013/20-giug= no-2013/soldi-fisco-finiti-uno-yacht-lussoa-processo-evasione-11-milioni-22= 21769688150.shtml ... ovviamente, scandali, truffe e ruberie tutte targate, ^neopiduistissima= mente^, fasciomafioso, ladro, truffatore, mega pallonaro, nazidittatore, la= vatrice di proventi super assassini, stragista spappola magistrati, deprava= to lecca fighe di zoccole 14 enni marocchine, vomitevole pedofilo Silvio Be= rlusconi). ADELANTE BABY, ADELANTE, ADELANTE.... VAMONOS BABIES, VAMONOS, VAMONOS, LET'S GOOOOOOOOOO NON FATEVI ROVINARE DAL FIGLIO DI PUTTANA CRIMINALISSIMO PAOLO PIETRO BARRA= I NATO A MILANO IL 28.6.1965! FA AZZERARE I RISPARMI DI TUTTI, SEMPRE! INDA= GATO DA PROCURA DI LUGANO! INDAGATO DA 7 PROCURE ITALIANE, DA POLIZIA ITALI= ANA E GUARDIA DI FINANZA ITALIANA! INDAGATO DA EUROPOL ED INTERPOL! CON, SU= L GROPPONE, BEN 70.000 EURO DI MULTA DA PARTE DI CONSOB! CONDANNATO A GALER= A IN MILANO! CONDANNATO AD 8 ANNI DI CARCERE IN BRASILE ( ANCHE PER PEDOFIL= IA OMOSESSUALE, RIPETO, ANCHE PRE PEDOFILIA OMOSESSUALE)! INDAGATO PESANTIS= SIMAMENTE A PANAMA, IN GERMANIA, PORTOGALLO ED INGHILTERRA! NOTO NAZIRAZZIS= TA ASSASSINO DEL KU KLUK KLAN PADANO, SVIZZERO, INGLESE ED AMERICANO! FAMOS= ISSIMO TRUFFATORE, LADRO, FALSONE, NAZI-ST-ALKER VIA INTERNET! SBAGLIA SEMP= RE E STRA SEMPRE IN BORSA! Siamo un foltissimo guppo di risparmiatori truffati dal criminale, gia' tre= volte in galera, Paolo Barrai di malavitosissime societa' Bsi Italia srl, = Wmo Sa Panama, World man opportunities Lugano! Multato da Consob per ben 70.000 euro per sue mega frodi su fotovoltaico http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://groups.google.com/forum/#!topic/alt.tv.homicide/KlPMYZEmGIY https://groups.google.com/forum/#!topic/iceusers/Raz_KSxP3tE Condannato al carcere in Brasile per estorsioni, stalking via internet, min= acce di morte, pedofilia omosessuale, proprio cosi', pedofilia omosessuale.= Oltre che ladrate, truffe, mega riciclaggio di proventi mafiosi, propagand= a nazista e razzista! Come questi articoli ( pero', di appena inizio indagi= ne) dimostrano! Poi, il tutto e' divenuto, ben appunto condanna al carcere = e per tanti anni... ovvio che il Renato Vallanzasca in cravatta, Paolo Barr= ai, in Brasile non mette piu' piede... ha paura delle gattabuie locali http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg POSSO SOLO RIPETERLO!!!!!!! E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZIRAZZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965= . http://google-guice.narkive.com/aPNDvjEA/criminali-bastardi-di-bsi-italia-s= rl-via-socrate-26-milano-paolo-barrai-e-vincenzo-barrai-noti NONCHE' RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI MEGA RUB= ERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA E STRAGISTA SPAPPOLA MAGISTR= ATI, NONCHE', TANTO QUANTO, NAZIFASCISTA DITTATORE E PEDOFILO: SILVIO BERLU= SCONI! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERRO= RISTA NAZISTA ED ASSASSINO, PAOLO BARRAI. NON PER NIENTE, GIA' STATO IN GAL= ERA 3 VOLTE. OPINIONI TUTTE TERRIFICANTI SU DI LUI! MEGA TRUFFATORE E MEGA = RICICLA CASH ASSASSINO VIA CRIMINALISSIMA BLOCKCHAIN INVEST O VIA CRIMINALI= SSIMA BLOCKCHAININVEST CHE SIA, OLTRE CHE VIA CRIMINALISSIMA WMO SAGL LUGAN= O, CRIMINALISSIMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PAN= AMA E CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO! NOTO PEDOFIL-= O-MOSESSUALE SODOMIZZA BAMBINI E RAGAZZINI! CACCIATO DA CITIBANK A SBERLE, = PER MEGA FRODI CHE LI FACEVA! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI DI= TANTISSIME PERSONE! FALSO&LADRO&TRUFFATORE! DIFFAMA SUL WEB A FINI NAZI-RA= ZZISTI! FONDATORE DEI NUOVI MEGASSASSINI TERRORISTI DI ESTREMISSIMA DESTRA:= "NUOVI NAR"! FONDATORE DEL, PROSSIMAMENTE, DI FREQUENTE, OMICIDA: KU KLUK = KLAN PADANO! CONDANNATO AL CARCERE A MILANO ED IN BRASILE ( 8 ANNI E PURE P= ER PEDERASTIA OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE)! MULTAT= O DA CONSOB 70.000 =E2=82=AC! DESTABILIZZA L'ITALIA PER FILO NAZISTI SERVIZ= I SEGRETI SVIZZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTISSIMAMENTE, NAZION= E SCHIFATA IN TUTTO IL MONDO, IN QUANTO FASCIOMAFIOSA DITTATURA DI BERLUSCO= NIA.. NON PER NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITALIA DA SECOLI, = DALLA TIRANNIASSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIAT, PIRELLI, LUX= OTTICA, MERLONI E MIGLIAIA E MIGLIAIA DI ALTRE... E CHE SIA CHIARO, PLS, CH= E IDDIO BENEDICA I GRANDI PM CHE NON SOPPORTANTO IL CANCRO DEL MONDO INTERO= , SILVIO BERLUSCONI, COME HENRY WOODCOCK, ILDA BOCASSINI E CHIUNQUE ALTRO D= I QUESTA AMMIREVOLISSIMA CATEGORIA)! FA CRIMINI SU CRIMINI E NAZI-ST-ALKING= , SU INTERNET, SU ORDINE DEI PUZZONI CRIMINALISSIM SILVIO BERLUSCONI, PAOLO= BERLUSCONI ED UBALDO LIVOLSI DI FININVEST ( CHE DA ANNI FANNO GLI ADOLPH H= ITLER MISTI AD AL CAPONE, DEL WEB, ANCHE, MA DI CERTO, NON SOLO, CON QUEL V= ERME SCHIFOSAMENTE TERRORISTA DI GIULIO OCCHIONERO). INNEGGIANTE ALLO SPAPP= OLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GRANDISSIMAMENTE FECE CON F= ALCONE E BORSELLINO"! PAROLE SUE, DETTE SPESSISSIMO! ORGANIZZANTE OMICIDIO = DI DAVID ROSSI DI MONTE PASCHI! Ho tantissimo da scrivere sul gia' 3 volte finito in galera, accertatissimo= pedofilo omosessuale, ladro, truffatore, sempre falso, nazi-st-alker, mand= ante di omicidi ( spesso, ma non sempre, mascherati da finti incidenti, mal= ori o "suicidate"... come quando fece ammazzare David Rossi di Monte Paschi= , ma ne scrivero' in dettagli molto presto), mega ricicla soldi mafiosi e/o= politico-criminali (piu' tanto di orrido altro), arrestato gia' 3 volte, P= aolo Barrai, nato a Milano il 28.6.1965 e gia' residente a Milano in Via Ip= podromo 105! Come presto meglio sottolineeremo, multato dalla Consob ben 70= .000 euro! http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html https://www.adviseonly.com/blog/investire/mercati-finanziari/il-trading-dei= -miracoli/ http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion Ho tantissimo da scrivere su sto Renato Vallanzasca ( in quanto ad indole m= alavitosa) misto ad Ugo Fantozzi ( in quanto ad essere il piu' grande ciula= , perdente, cane in Borsa, brucia risparmi di tutti e sempre, sia esso su a= zioni, criptovalute, valute, obbligazioni, materie prime, case, diamanti, o= ro fisico, qualsiasi tipo di investimento... con la differenza che Ugo Fant= ozzi era simpatico e per bene a sua nettissima differenza) della finanza pi= u' filo mafiosa e ricicla soldi mafiosi che esista. - ATTRAVERSO I NOTI MASSONI ASSASSINI, SI, ASSASSINI, TUTT' UNO, TRA L'ALTR= O, CON COSA NOSTRA, NDRANGHETA, MAFIA CINESE E MAFIA RUSSA, PAOLO CARDEN=C3= =80 E STEFANO CARDEN=C3=80 DI CRIMINALISSIMA CARDEN=C3=80 CONSULTING DI VIA= MONTESSORI 6 E 8 DI FALERONE IN PROVINCIA DI FERMO.. CE NE PARLA UNO CHE C= I HA LAVORATO PER ANNI, INSIEME, ORA DA LORO DISSOCIATOSI, ALL' INTERNO DEL= LA PROSSIMA, DOVUTA.... "NON PICCOLISSIMA" PARENTESI ( E' CRIMINALISSIMA LA= CARDEN=C3=80 CONSULTING DI VIA MONTESSORI 6, FALERONE, VIA MONTESSORI 6 E = 8...... DA ANNI RICICLA SOLDI ASSASSINI DI COSA NOSTRA, CAMORRA, NDRANGHETA= , MAFIA CINESE E MAFIA RUSSA, QUEST'ULTIMA, CHE NON PER NIENTE, LAVO' PRIMI= PROPRI =E2=82=AC OMICIDA, A LIVELLO MONDIALE, ESATTAMENTE NELLE MARCHE... = E I VERMI SCHIFOSI CHE LA RAPPRESENTANO, I BASTARDI EFFERATI CRIMINALI STEF= ANO CARDENA' E PAOLO CARDENA' SONO DUE "SATA-N-AZISTI" PEDOFILI INCULA BAMB= INI, SGOZZA BAMBINI ED UCCIDI BAMBINI A RAFFICA... REGISTI DI CENTINAIA E C= ENTINAIA DI OMICIDI E SPARIZIONI DI PERSONE ACCADUTI NELLA LORO SATANISTISS= IMA MACERATA E MARCHE IN GENERE, COME DA QUESTO ARTICOLO http://www.cronachemaceratesi.it/2015/05/25/allarme-persone-scomparse-163-a= -macerata-500-nelle-marche/661329/ CRIMINALE CARDEN=C3=80 E PARTNERS DI VIA MONTESSORI 6, 63837 FALERONE (FM) = - Tel: 0734.710786 - sua malavitosissima e mail: info@cardenaconsulting.it = - P.IVA: 01840990442..... DA ANNI RICICLA SOLDI ASSASSINI DI COSA NOSTRA, C= AMORRA E MAFIA RUSSA, CHE, COME DICEVAMO, NON PER NIENTE LAVO' PRIMI PROPRI= =E2=82=AC OMICIDA PROPRIO NELLE MARCHE... E PAOLO CARDENA' E PURE BEN NOTO= PEDOFILO.... IL MASSONE PEDERASTA INCULA BAMBINI PAOLO CARDEN=C3=80 HA UN = BLOG CRIMINALISSIMO... VINCITORI E VINTI... NOI SAREMO I VINCITORI CHE METT= EREMO LUI, I SUOI MEGA CRIMINI E MEGA BALLE, SPALLE AL MURO.... MENTRE LUI = SARA' IL VINTISSIMO... IL VERME DELINQUENTISSIMO PAOLO CARDEN=C3=81, NATO A= MACERATA IL 2.19.1971 E RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMB= ERTO I, NUMERO 41, OLTRE AD ESSER NOTO PEDOFILO E' UN PORCO MEGA RICICLA SO= LDI MAFIOSI PER I SUPER KILLER DI COSA NOSTRA, CRISAFULLI DI MILANO..... E = PER I PORCI MEGA RICICLA SOLDI ASSASSINI DI MALAVITE DI MEZZO MONDO.. ENNIO= DORIS E MASSIMO DORIS DI MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOLANUM,= NAZISTANUM.... BUT AGAIN AND AGAIN AND AGAIN AND AGAIN.... CHI =C3=88 DAVV= ERO STO SCHIFOSO PEDOFIL-O-MOSESSUALE STUPRANTE, BAMBINI ED ADOLESCENTI, CH= IAMANTESI PAOLO CARDEN=C3=80 RESIDENTE A PENNA SAN GIOVANNI, VIA UMBERTO I,= NUMERO 41... DI BASTARDAMENTE CRIMINALE CARDEN=C3=80 CONSULTING, BASATA IN= VIA MONTESSORI 6, 63837 FALERONE Tel: 0734.710786.....E DI MEGA TRUFFATORE= BLOG VINCITORI E VINTI..... CHE ESISTE PER FAR ABBOCCARE I "CIULA DEL WEB"= , CHE CADENDO NELLE TRAPPOLE DI SUOI MEGA FALLIMENTARI SERVIZI, SEMPRE PERD= ONO TUTTI I PROPRI RISPARMI, SIA PER LA TOTALE INCOMPETENZA DI PAOLO CARDEN= =C3=80 A PROPOSITO DI MERCATI FINANZIARI MONDIALI, SIA PER LA INDOLE SEMPRE= ESTREMAMENTE TRUFFALDINA DEL VERME CRIMINALISSIMO PAOLO CARDEN=C3=80 STESS= O... BUT AGAIN AND AGAIN AND AGAIN AND AGAIN.... CHI E' IL BASTARDISSIMO CR= IMINALE, PURE NOTI PEDERASTA ED ASSASSINI PAOLO CARDEN=C3=80 https://a.mytr= end.it/authors/1385.jpg UNITO ED IL VERME CRIMINALE STEFANO CARDEN=C3=80 http://www.formazione-lavoro.eu/img/public/stefano.jpg FACENTE DA DECENNI TRUFFE SU TRUFFE E MEGA RICICLAGGI DI CASH MAFIOSO DAGLI= UFFICI DI Via Maria Montessori, 8, 63020 Falerone FM, Italia Telefono: +39= 0734 710786 ...criminalissima email info@cardenaconsulting.it e altra crim= inalissima email formazione@cardenaconsulting.it..ED ANCOR PRIMA.. CHI SONO= IO? MI VOLETE FARE FUORI IN QUANTO DICO LA VERITA' ^?^.... COSA CHE NELLA = FASCIOMAFIOSA ITALIA, DA 40 ANNI DITTATURA NAZINDRANGHETISTA DI BERLUSCONIA= , ACCADE DA MILLENNI.... SONO UN FUORI USCITO DA QUEL PARTITO STRA COLMO DI= COSA NOSTRA, CAMORRA, NDRANGHETA E CATTIVERIA ANTI DEMOCRATICA DI ESTREMIS= SIMA DESTRA CHE E' FORZA ITALIA ... DI STO VERME CRIMINALE DI PAOLO CARDEN= =C3=81, CHE IN FORZA ITALIA, INSIEME AL AMEGA RICICLA SOLDI MAFIOSI DIEGO D= ELLA VALLE, FA LA LAVATRICE DI CAPITALI ASSASSINI, ASSASSINI, CHE PIU' ASAS= SINI NON POTREBBERO ESSERE... DI LUII SO' TUTTO, E QUINDI, COME DICONO A NA= PULE, ORA MI "HAGGIA PROPRIO SFUGA' " .... PROFESSIONALLY SPEAKING, SI DEFI= NISCE "PRIVATE BANKER"...MA NON DICE CHE UNICI SUOI CLIENTI SONO I MAFIOSI = ASSASSINI CRISAFULLI DI MILANO... UNA DELLE FAMIGLIE DI COSA NOSTRA PIU' BA= STARDAMENTE KILLER DI TUTTI I TEMPI... E POI, COME CITATO, IL VOMITEVOLE PE= DERASTA PAOLO CARDEN=C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI E' PURE= NOTISSIMO PEDOFIL-O-MOSESSUALE ... QUI E' IN UNA FOTO CHE GLI ABBIAMO FATT= O, MENTRE, IN MUTANDE, FISSAVA, CON SGUARDO DA DEPRAVATO SESSUALE MAXIMO, U= N BAMBINO DI OTTO ANNI, NELLE ADIACENZE DI UN CAMPO ROM PADANO, VICINO A CO= LOGNO MONZESE, VICINO A SUA MAFIASET-CAMORRASET-NDRANGASET-NAZISTSET MEDIAS= ET...DA CUI ERA APPENA USCITO.... https://a.mytrend.it/authors/1385.jpg DICEVAMO CHE IN DETTA FOTO ... https://a.mytrend.it/authors/1385.jpg .... IL PEDERASTA INCULA ED AMMAZZA BAMBINI PAOLO CARDEN=C3=80 OSSERVA IN M= ANIERA DEPRAVATISSIMA UN BAMBINO ROM DI OTTO ANNI.... CHE MEZZ'ORA DOPO INC= ULERA' A SANGUE...... PRESTO OGNI COSA SU MIGLIAIA DI SITI, ANCHE DI PLUTON= IO E MARTE, NON SOLO DI QUESTO PIANETA SEMPRE PIU' "PICCIRIDDU PICCIRIDDU" = .. USO SLANG SICILIANO, PER FAR SENTIRE IL MEGA RICICLA CASH DI COSA NOSTRA= , PAOLO CARDEN=C3=81, COME SE IN UNA "COSA SUA" AAAA".... E POI... IL BLOGG= ER PEDERASTA, NAZISTA, RAZZISTA, RICICLA CASH MAFIOSO PAOLO CARDEN=C3=81 DI= CRIMINALISSIMO BLOG VINCITORI E VINTI... RAGLIEREBBE SU INTERNET CHE FAREB= BE IL PRIVATE BANKER.. MA, COME "FORSE" CITATO, NON AGGIUNGE CHE I SUOI SOL= I 2 CLIENTI SONO LE FAMIGLIE MAFIOSE ED ASSASSINE CAGNETTI E CRISAFULLI DI = MILANO.. E POI... COME E' LO SCHIFOSO PEDERASTA PAOLO CARDEN=C3=80, NELLA V= ITA PRIVATA ^?^ COI PANTALONI ABBASSATI ^?^ 5 SERE ALLA SETTIMANA ANDAVA IN= LOCALI ^OCCULTISSIMI^ DI TIPO ESTREMAMENTE PERVERTITO APERTI SOLO A MASSON= I OMOSESSUALI LEGHISTI E BERLUSCONIANI.... CI VA' COL PARI PEDERASTA GIULIO= TREMONTI, I CUI AMANTI OMOSESSUALISSIMI ERANO I NAZISTI, ANZI, SATA-N.AZIS= TI MARCO BROTTO, EX CENTROSIM E BANCA LEONARDO, ED ANCOR PIU' IL PAZZO ASSA= SSINO ALEXANDER BOETTCHER .. QUELLO CHE SI RIEMPIVA DI COCAINA E FACEVA SFR= EGIARE CON ACIDO ASSASSINO TANTA GENTE INNOCENTE, INNOCUA, PER BENE.. MASSO= NE BERLUSCO-N-AZISTA E PADA-N-AZISTA ALEXANDER BOETTCHER, COLUI CHE SI DEFI= NIVA SE STESSO UN PERICOLOSISSIMO DEPRAVATO SESSUALE http://www.dagospia.com/rubrica-29/cronache/sono-deviato-sessuale-martina-l= evato-era-sadomasochismo-124763.htm VI ERA UN DEAL BERLUSCONICCHIO CHE ERA QUESTO.... ALEXANDER BOETTCHER INCUL= AVA L'OMOSESSUALE ^OCCULTISSIMO^ GIULIO TREMONTI ..COME QUESTO TWITTER ACCO= UNT FA STRA INTUIRE https://twitter.com/alexanboettcher E L ^ OCCULTISSIMO^ MASSONE LAVA SOLDI MAFIOSI, OMOSESSUALE DI TIPO PERVERT= ITO, GIULIO TREMONTI, CERCAVA DI FARLO SFONDARE IN POLITICA.. ALLA FINE, PE= RO', L'UNICA COSA SFONDATA ERANO LA PROSTATA E L' ANO DEL CULACCHIONE "CHIC= LE FREAK", DEL MASSONE ^OCCULTISSIMAMENTE^ GAY DI TIPO SEMPRE PIU' PEDERAS= TA: GIULIO TREMONTI STESSO! - Ed attraverso criminalissima Banca Mediolanum dei banchieri malavitosi Ca= rlo Secchi ( puzzone schifoso, sempre a tramare a morte, via Trilaterale) O= scar di Montigny, Ennio Doris, Massimo Doris e Giovanni Pirovano http://www.mediolanum.com/ITA/12231_profili-manageriali.html - Ed attraverso malavitosissima Arner Bank Lugano dei colletti lerci stile = "topi di fogna" Giovanni Schraemli, Gabriele Gandolfi e Roland M=C3=BCller-= Ineichen http://www.arnerbank.ch/?view=3D2242 - Ed attraverso malavitosissima BancaStato Lugano dei bastardi criminali Be= rnardino Bulla, Fabrizio Cieslakiewicz, Daniele Albisetti e Claudio Genasci https://www.bancastato.ch/bancastato/chi-siamo/Corporate-Governance/Direzio= ne-generale.html - Ed attraverso criminalissima Tax and Finance Lugano, di quel porco schifo= so, lurido, puzzone, mega ricicla cash mafioso che e' Gerardo Segat https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.moneyhouse.ch/it/p/gerardo-segat ( a cui era unito, un altro porco schifoso, lurido, puzzone, mega ricicla c= ash mafioso, Andrea Baroni, ex Tax and Finance, non per niente finito in ga= lera http://carlofesta.blog.ilsole24ore.com/2015/10/10/intrigo-internazionale-la= rresto-di-baroni-socio-delladvisor-di-mr-bee-sul-milan/ ) - Ed attraverso malavitosissima InvestireOggi.it del topo di fogna albanese= Bogdan Bultrini, mega ricicla cash assassino di Mala, ben appunto, Albanes= e, ma anche Bulgara, Rumena, Turca e Russa https://it.linkedin.com/in/bogdan-bultrini-62132220 - COME ATTRAVERSO IL NOTO CRIMINALISSIMO PEDOFIL-O-MOSESSUALE STEFANO BASSI= DE IL GRANDE BLUFF E DI TORINO https://groups.google.com/forum/#!topic/comp.lang.python/0_mkZKCAs74 CHE QUI VEDETE NELLA SUA PERVERSIONE DI PEDOFILO INCULA ED AMMAZZA BAMBINI.= A PETTO NUDO VA' SU INTERNET, STO CESSO BRUTTISSIMO E PEDERASTA DI TORINO.= NONCHE' SATANAZISTA KILLER STEFANO BASSI: IL SODOMIZZA ED UCCIDI BAMBINI D= E IL GRANDE BLUFF. https://talkmusic.site/talkmusic/qMGXY1CfSjU/che-tristezza-i-soldidice-il-c= lassico-fallito-radical-chic-italopiteco-ma-vaffanculooooo TUTT'UNO CON LA NDRANGHETA E DA ANNI. CINTURA FRA ASSASSINI CALABRESI BASAT= I IN PIEMONTE, BEN NOTO SPAPPOLA MAGISTRATI E PEDOFILO SILVIO BERLUSCONI E = LEGA LADRONA. LAVATRICE FINANZIARIA DEI KILLER NDRANGHETISTI CROTONESI DELL= E FAMIGLIE OMICIDA VRENNA E MEGNA, VERI E PROPRI PADRONI DI MEZZO PIEMONTE. PER NON DIRE, POI, DEL BASTARDO NAZIRAZZISTA E MEGA RICICLA SOLDI MAFIOSI: = GIACOMO ZUCCO DI CRIMINALISSIMA BHB-BLOCKCHAINLAB, BLOCKCHAINLABIT, ASSOB.I= T E WMO SA PANAMA ( NONCHE' DI HITLERIANI TEA PARTIES) https://1.bp.blogspot.com/-e_LRApIYQrc/WEKCZf1swNI/AAAAAAAAjSU/JVphLLcsq60h= ZSLv3QddLrWif6UEkBQdwCLcB/s1600/barrai%2Bzucco.jpg TRATTASI DI QUESTO NANETTO CON FACCIA DA TIPICO SEGAIOLO COMPULSIVO https://i.ytimg.com/vi/VhfifMuKc74/maxresdefault.jpg QUI A PROCESSO, A MILANO, PER UNO DEI SUOI SOLITI TANTISSIMI CRIMINI "BERLU= SCONICCHI" https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico SCHIFOSO KU KLUK KLANISTA. CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI DA MATT= INA A SERA. E, PER LO STESSO PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI= , LA MERDA MALAVITOSA GIACOMO ZUCCO, MEGA RICICLA SOLDI ASSASSINI DI BEN 7 = NDRINE BASATE NEL MILANESE ( FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PA= SQUALE MORABITO). COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! PER NON AGGIUNGERE DEL PARI PEDERASTA ED AZZERA RISPARMI FEDERICO IZZI, DET= TO ZIO ROMOLO https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/FKY_roBbVQ4 ( MEGA RICICLA CASH MALAVITOSISSIMO DEI GIRI LERCI DI MAFIA CAPITALE E DI C= AMORRISTI PRESENTI NEL BASSO LAZIO https://meloniclaudio.wordpress.com/2016/12/30/la-camorra-a-roma-e-nel-lazi= o/ http://www.adnkronos.com/fatti/cronaca/2016/03/04/blitz-contro-camorra-nel-= casertano-nel-basso-lazio-arresti_Ee3CRNYmUmhxiTgmJJK3kI.html http://www.iltempo.it/cronache/2013/11/02/gallery/i-veleni-della-camorra-ne= l-basso-lazio-913245/ ). O DEL PARI PEDERASTA MAURIZIO BARBERO DI TECHNOSKY MONTESETTEPANI https://groups.google.com/forum/#!search/MAURIZIO$20BARBERO%7Csort:relevanc= e/comp.soft-sys.matlab/YvZMKV-5VPM/jWEwnxs-UCEJ https://groups.google.com/forum/#!topic/free.it.discussioni.divorzio/D8bxM3= OVbLg https://twitter.com/mlnews_com?lang=3Des SEMPRE IN THAILANDIA A STUPRARE BAMBINI SU BAMBINI https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/hDk33qscjro ( ED IL NOTO PEDOFILO MAURIZIO BARBERO DI TECHNOSKY MONTESETTEPANI ERA CIO'= CHE UNIVA I CREATORI DI NUOVE OVRA E GESTAPO, I BASTARDI CRIMINALI UBALDO = LIVOLSI, FRANCESCA OCCHIONERO E GIULIO OCCHIONERO AD ENAV http://www.ilfattoquotidiano.it/2017/01/13/giulio-occhionero-un-cyberspione= -che-piu-maldestro-non-si-puo/3312745/ http://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_inchiesta-= 155753314/ DI CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA S= ERVIZI SEGRETI DI ESTREMA DESTRA, SPESSISSIMO ASSASSINI, E' IN PIENO, PARTE= ). E a proposito del pregiudicato, gia' stra condannato a galera Ubaldo Livols= i di criminalissima Livolsi - Iaquinta and partners e di Fininvest, nota in= tutto il mondo come (Ma)Fi(a)Ninvest... Trattasi anche lui di viscidissimo= pedofilo che paga ragazzini perche' lo inculino ( i Berlusconiani stanno a= i pedofili, come il sole sta ad Habana Cuba a luglio... e da sempre..ad ini= ziare dal pedofilo dei pedofili numero uno al mondo: Silvio Berlusconi http://www.elmundo.es/elmundo/2010/11/03/internacional/1288770719.html http://www.huffingtonpost.it/2015/03/26/intervista-gianni-boncompagni_n_694= 5522.html http://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-senat= ore-a-vita-un-pedofilo/14626/ ). Pure assassino. Proprio cosi': pure assassino! Organizzava tanti omicidi fr= a il 2001 ed il 2006, omicidi mascherati da finti suicidi, malori ed incide= nti. Il tutto targato "disarticolazioni attraverso mezzi traumatici (ossia = killer)" http://forum.enti.it/viewtopic.php?t=3D66625 http://www.ariannaeditrice.it/articolo.php?id_articolo=3D6352 http://www.omniauto.it/forum/index.php?showtopic=3D17113 https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://www.grnet.it/news/95-news/852-segreto-di-stato-sulle-schedature-ille= gali-berlusconi-salva-pollari-a-pompa http://ferdinandoimposimato.blogspot.pt/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pt/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l Non siamo comunisti, ma anche questo link dice cose interessantissime a pro= posito http://www.pmli.it/sismicolpivanemiciberlusconi.htm Schifezze mega omicida che il pezzo di merda assassino Ubaldo Livolsi prima= faceva col suo amante omosessuale Pio Pompa, noto in tutto il mondo come "= er pompinaro" Pio Pompa ( cuginetto de "er nuovo pompinaro" Mike Pompeo dei= prima citati, ku kluk klanisti Tea Parties e della nazifascista e nazimafi= osa Cia attuale). E con lo schifoso verme, anche lui noto pederasta, Giulio= Occhionero ( massone sata-n-azista del Goi). Fra l'altro sto verme viscidi= ssimo di Ubaldo Livolsi da decenni mega ricicla cash assassino di Matteo Me= ssina Denaro. E di certo non solo. E' gia' stato condannato al carcere per = il caso Finparthttp://www.repubblica.it/economia/finanza/2012/04/03/news/cr= ac_finpart_livolsi_condannato-32697350/ Era dietro le piu' lercie puzzone trame dei furbetti del quartierino. Fa pe= dinare abusivamente. Intecetta telefonate abusivamente. Come detto, organiz= za nuove Ovra e Gestapo assassine. Sia pubbliche che private. Dovrebbe esse= re in carcere, ora, a spompinarsi col noto "er pompinaro" Pio Pompa ed il s= uo partner gay, nonche' terrorista nazifascista killer, Giulio Occhionero! STA BESTIA SCHIFOSA DI PAOLO BARRAI RICICLA CASH KILLER ANCHE ATTRAVERSO UN= 'ALTRA SOCIETA' CRIMINALISSIMA: LA FRUIMEX DI TORINO, ALBA ... E "BLOGSPOT"= . SOCIETA' ESTREMAMENTE MALAVITOSA CHE RICICLA TANTI SOLDI MAFIOSI, ESATTAM= ENTE DELLA NDRANGHETA ( VIA FAMIGLIE MEGASSASSINE CALABRESI BELFIORE E CREA= , NOTORIAMENTE, CONTROLLANTI TUTTA TORINO), MA ANCHE DI COSA NOSTRA E CAMOR= RA (SOCIETA' CRIMINALISSIMA, MEGA RICICLA SOLDI MAFIOSI FRUIMEX DI VIA NICO= LA FABRIZI 44 10145 TORINO Tel: 011746342 COME ANCHE SOCIETA' CRIMINALISSIM= A, MEGA RICICLA SOLDI MAFIOSI FRUIMEX DI ALBA: LOCALITA' SAN CASSIANO 15 - = 12051) http://www.impresaitalia.info/mstdb80753147/fruimex-di-cogno-elisa-e-c-sas/= alba.aspx https://www.guidamonaci.it/gmbig/main.php?p=3Dcomp_prof01&id=3D154326093763= 838 BASTARDAMENTE MALAVITOSA FRUIMEX "KAPEGGIATA" DA DUE SCHIFOSE PROSTITUTE DI= ESTREMISSIMA DESTRA, SEMPRE AD ARCORE-HARDCORE A FARE SESSO ANALE. E DA AN= NI ( VANNO A FARE SESSO ANALE AD HARDCORE-ARCORE DA TANTI ANNI... E PURE DA= "TANTI ANI"). NOTA MIGNOTTONA NAZIFASCISTA PIERA CLERICO, BEN APPUNTO, DEL= LA FRUIMEX ( MADRE) https://groups.google.com/forum/#!topic/comp.lang.python/T3V3zB9FRtU https://it-it.facebook.com/public/Piera-Fruimex E NOTA MEGA TROIA, SEMPRE NAZIFASCISTA, ELISA COGNO DELLA ^SATA-N-AZISTA^ F= ONDAZIONE FERRERO E PURE DELLA FRUIMEX ( FIGLIA) https://groups.google.com/forum/#!search/ELISA$20COGNO%7Csort:relevance/us-= it-technical-recruitement-group/5CdzmytBnWE/iG9KBVIdAwAJ https://groups.google.com/forum/#!search/ELISA$20COGNO%7Csort:relevance/rec= .photo.equipment.35mm/ozflCyBuGhY/XkSoJzuoZ5IJ https://www.guidamonaci.it/gmbig/main.php?p=3Dcomp_prof01&id=3D154326093763= 838 http://www.impresaitalia.info/mstdb80753147/fruimex-di-cogno-elisa-e-c-sas/= alba.aspx COME SAPETE, IL MONDO DEL BITCOIN E DELLA BLOCKCHAIN SERVE, AL 99,99999%, S= OLO A RICICLARE SOLDI ASSASSINI! DI MAFIE DI TUTTO IL MONDO! E DI TERRORIST= I KILLER DI ESTREMA DESTRA ( QUALE E' DA SEMPRE PAOLO BARRAI E TUTTI I VERM= I SOPRA QUI CITATI)! http://www.ilsole24ore.com/art/commenti-e-idee/2017-01-24/bitcoin-riciclagg= io-invisibile-mafie-e-terrorismo-internazionale-164825.shtml?uuid=3DAEISiAH http://fortune.com/2012/12/18/bitcoin-looks-primed-for-money-laundering/ https://www.bloomberg.com/news/articles/2016-11-11/hong-kong-central-bank-f= lags-blockchain-money-laundering-risk DA QUI CHE ALTRI CRIMINI SU CRIMINI A LIVELLO DI RICICLAGGIO VENGONO EFFETT= UATI FRA IL GIA' TRE VOLTE IN GALERA, PAOLO BARRAI ED IL DELINQUENTE SCHIFO= SO RICCARDO CASATTA DI MALAVITOSE ETERNITY WALLS E GIA' CITATA BLOCKCHAINLA= B! COME FRA IL NOTO PEDOFIL-O-MOSESSUALE, TRUFFATORE, BRUCIANTE O LADRANTE I R= ISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI E L'AL CAPONE DI LONDRA, CHIAMATO D= A TUTTI "THE CRIMINAL BEAST": THOMAS BERTANI FROM ORACLIZE. ONE OF WORST MA= FIA MONEY LAUNDERERS PRESENT IN THE CITY. PROPRIO COSI', A LONDRA LO CHIAMA= NO TUTTI " LA BESTIA CRIMINALE" A THOMAS BERTANI DI ORACLIZE. UNO DEI MASSI= MI RICICLATORI DI CASH DEI MAFIE DI MEZZO MONDO DELLA CITY (INSIEME AL MEGA= VERME, PARIMENTI CRIMINALISSIMO, DAVIDE SERRA DI ALGEBRIS, TWITTER E FACEB= OOK... NON PER NIENTE SOCIO DEI PORCI DI COSA NOSTRA PRIMA CITATI DI BANCA = MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOLANUM, NAZISTANUM... COME VEDETE= , QUADRIAMO OGNI COSA E SEMPRE.. MA NON METTIAMO ORA, TROPPA CARNE A FUOCO,= PLEASE.. TROPPA CARNE PUO' ANCHE DIVENIRE INDIGESTA... OGNI COSA LA DESCRI= VEREMO SU DIVERSI TESTI AND REAL SOON). I VERMI NAZISTI, LADRI, TRUFFATORI, MAFIOSI, CORROTTI E CORRUTTORI, LAVA SO= LDI MAFIOSI, STRAGISTI, PEDOFILI MATTEO SALVINI, ENNIO DORIS E SILVIO BERLU= SCONI (PER SEMPRE FUORI DAI COG.IONI) HAN CHIESTO (DICIAMO "CHIESTO SMAZZET= TANDO") A GOOGLE DI DIMINUIRE LO SPAZIO DEDICATO AI COMMENTI, QUI, IN QUANT= O BEN SANNO CHE SCRIVIAMO ASSOLUTE VERITA', CHE OVVIAMENTE, LI IMBARAZZANO = IMMENSAMEN TE. PIU' USAN QUESTI METODI HITLERIANI E RIININESI ( OSSIA BERLU= SCONIANISSIMI), METODI ASSASSINI DI DEMOCRAZIA, GIUSTIZIA E LIBERTA', PIU' = CI SCATENEREMO A SCRIVERE "67 ORE AL GIORNO, 40 GIORNI AL MESE, 400 GIORNI = ALL'ANNO". From newsfish@newsfish Thu Aug 1 00:43:56 2024 X-Received: by 2002:ac8:2e6e:: with SMTP id s43mr5730069qta.38.1541081728966; Thu, 01 Nov 2018 07:15:28 -0700 (PDT) X-Received: by 2002:a25:39d0:: with SMTP id g199-v6mr87904yba.2.1541081728618; Thu, 01 Nov 2018 07:15:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!2.eu.feeder.erje.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!e5-v6no3913265qtr.0!news-out.google.com!c29-v6ni4432qtg.1!nntp.google.com!e5-v6no3913261qtr.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Nov 2018 07:15:28 -0700 (PDT) In-Reply-To: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.152.156.88; posting-account=G_kdTgoAAAAO0rNQzePtQF4V6Wu3ReYV NNTP-Posting-Host: 5.152.156.88 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <73d0c777-0558-4c19-8b67-e14eb86854d4@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: surf.vhdl@gmail.com Injection-Date: Thu, 01 Nov 2018 14:15:28 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9373 On Friday, 21 June 2013 18:10:25 UTC+2, lkp wrote: > Hi, > > I am new to VHDL design. I want to design Galois field 2^m multiplier. First I want to start with Galois field 4 bit multiplier then 8 bit and then m bit multiplier. So please help me out with it.Any suggestion will be helpful. here you can find an example https://surf-vhdl.com/how-to-implement-galois-multiplier-in-vhdl/ From newsfish@newsfish Thu Aug 1 00:43:56 2024 X-Received: by 2002:a24:5495:: with SMTP id t143-v6mr6708997ita.34.1541108678557; Thu, 01 Nov 2018 14:44:38 -0700 (PDT) X-Received: by 2002:a81:57cd:: with SMTP id l196-v6mr112557ywb.4.1541108678380; Thu, 01 Nov 2018 14:44:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder3.usenet.farm!feed.usenet.farm!feeder.erje.net!2.eu.feeder.erje.net!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!z5-v6no181209ite.0!news-out.google.com!l70-v6ni493itb.0!nntp.google.com!75-v6no183064itm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Nov 2018 14:44:38 -0700 (PDT) In-Reply-To: <73d0c777-0558-4c19-8b67-e14eb86854d4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2606:a000:e14b:a00:a5a8:44be:9ca:a5ee; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2606:a000:e14b:a00:a5a8:44be:9ca:a5ee References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> <73d0c777-0558-4c19-8b67-e14eb86854d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <37708a77-86b3-4678-bfa3-26183bbcdca6@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: gnuarm.deletethisbit@gmail.com Injection-Date: Thu, 01 Nov 2018 21:44:38 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1900 X-Received-Body-CRC: 1868129878 Xref: reader02.eternal-september.org comp.lang.vhdl:9374 On Thursday, November 1, 2018 at 10:15:30 AM UTC-4, surf...@gmail.com wrote: > On Friday, 21 June 2013 18:10:25 UTC+2, lkp wrote: > > Hi, > > > > I am new to VHDL design. I want to design Galois field 2^m multiplier. First I want to start with Galois field 4 bit multiplier then 8 bit and then m bit multiplier. So please help me out with it.Any suggestion will be helpful. > > here you can find an example > https://surf-vhdl.com/how-to-implement-galois-multiplier-in-vhdl/ You are about five years too late... Rick C. From newsfish@newsfish Thu Aug 1 00:43:57 2024 X-Received: by 2002:a05:660c:205:: with SMTP id y5mr863364itj.30.1541615030086; Wed, 07 Nov 2018 10:23:50 -0800 (PST) X-Received: by 2002:a0d:d703:: with SMTP id z3-v6mr14418ywd.7.1541615029342; Wed, 07 Nov 2018 10:23:49 -0800 (PST) Newsgroups: comp.lang.vhdl Date: Wed, 7 Nov 2018 10:23:49 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.66.7.216; posting-account=GGSAwgoAAAD5iopikSuiUZu11vJOaEQL NNTP-Posting-Host: 87.66.7.216 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <03ffbfc4-0aac-4155-9366-be53297c0ed9@googlegroups.com> Subject: FILTHY MAFIA MONEY LAUNDERER GORDON SINGER FROM NAZIST ELLIOTT (WELL KNOWN HOMOSEXUAL PEDOPHILE ALSO) LAUNDERS ASSASSIN $ SINCE A LIFE TIME. TOGETHER AT WORST CRIMINAL OF ALL WORLD AND ALL TIMES "WHILE WEARING A TIE"! A PEDOPHILE LIKE HIM BUT ALSO... From: SIMONA-PREMOLI EXLESBIANAMANTE-DE MARINA-BERLUSCONI Injection-Date: Wed, 07 Nov 2018 18:23:50 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.166.216.MISMATCH!g188-v6no969itg.0!news-out.google.com!n199-v6ni871itn.0!nntp.google.com!g188-v6no966itg.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader02.eternal-september.org comp.lang.vhdl:9375 FILTHY MAFIA MONEY LAUNDERER GORDON SINGER FROM NAZIST ELLIOTT (WELL KNOWN = HOMOSEXUAL PEDOPHILE ALSO) LAUNDERS ASSASSIN $ SINCE A LIFE TIME. TOGETHER = AT WORST CRIMINAL OF ALL WORLD AND ALL TIMES "WHILE WEARING A TIE"! A PEDOP= HILE LIKE HIM BUT ALSO...........PRINCIPAL OF MURDERS AND SLAUGHTERS: RUTHL= ESS KILLER SILVIO BERLUSCONI!!! WHY DO I SAY THIS? LET'S START FROM THIS FOLLOWING POINT, NOW, PLEASE. NAZIST AND DEPRAVED PEDOPHILE DONALD TRUMP https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://www.snopes.com/news/2016/06/23/donald-trump-rape-lawsuit/ TOGETHER AT FASCIST HOMICIDE VLADIMIR PUTIN https://www.rferl.org/a/browder-putin-russia/29385305.htmlN USES CORRUPT, PROTECTOR OF CAMORRA, NDRANGHETA & COSA NOSTRA, AS WELL AS RA= CIST, KUKLUKLANIST, SCAMMERS, LIARS, THIEFTS, MAFIA MONEY LAUNDERERS, PRINC= IPAL OF HUNDREDS OF (MASKED) HOMICIDES AND DOZENS OF SLAUGHTERS, MEGA CRIMI= NAL DICTATORS AND ASSASSIN MATTEO SALVINI AND SILVIO BERLUSCONI, TO DESTABI= LIZE, THEN DESTROY, THEN DISINTEGRATE EUROPE!!! HI, I'M SIMONA PREMOLI. FOR 13 YEARS MARINA BERLUSCONI'S NUMBER ONE LESBIAN= LOVER ( BETWEEN HUNDREDS AND HUNDREDS). https://plus.google.com/113646548587006228899 https://twitter.com/premolisimona?lang=3Des https://twitter.com/premolisimona/status/876056110033235969 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 EX CIA AGENT IN MANY COUNTRIES OF THE WORLD ( IN MY CITY OF MILAN, IN ROME,= IN LONDON, IN ZURICH, IN BERLIN, IN DOMINICAN REPUBLIC, IN PUERTO RICO, IN= WASHINGTON DC). VERY WELL KNOWN PORNSTAR. http://it.cultura.linguistica.narkive.com/XV3Bw8gY/sono-simona-premoli-ex-a= mante-lesbica-di-marina-berlusconi-e-per-ben-13-anni-e-13-ani-che-mi-sono:i= .1.1.thumb FEMALE FREEMASON OF VERY HIGH DEGREE. INTEPRETER ( ITALIAN, ENGISH, SPANISH= ). EXTREMELY DIRTY MONEY LAUNDERER FOR NAZIST ASSASSIN MATTEO SALVINI FROM = LEGA NORD ( BETTER KNOWN AS LEGA LADRONA) AND FOR MEGA PRINCIPAL OF MURDERS= AND SLAUGHTERS, SLIMY PEDOPHILE SILVIO BERLUSCONI. SONO SIMONA PREMOLI DI MILANO. PER 13 ANNI, NUMERO UNO, FRA CENTINAIA E CEN= TINAIA DI AMANTI LESBICHE DI MEGA COCAINOMANE, RICICLA SOLDI MAFIOSI, CRIMI= NALISSIMA MARINA BERLUSCONI. https://plus.google.com/113646548587006228899 https://twitter.com/premolisimona?lang=3Des https://twitter.com/premolisimona/status/876056110033235969 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 EX AGENTE CIA IN MIA CITTA' DI MILANO, COME IN ROMA, BERLINO, ZURIGO, LONDR= A, REPUBBLICA DOMINICANA, PORTORICO, WASHINGTON DC. SCATENATA PORNOSTAR DA = VARI ANNI. https://it.cultura.linguistica.narkive.com/XV3Bw8gY/sono-simona-premoli-ex-= amante-lesbica-di-marina-berlusconi-e-per-ben-13-anni-e-13-ani-che-mi-sono:= i.1.1.thumb GRAN MAESTRO MASSONICO. INTERPRETE ( IN TANTI DICONO, CHE PIU' CHE INTERPRE= TE, CHE SONO " ESPERTISSIMA NELL'USO DELLA LINGUA" E NON HAN NEANCHE TUTTI = I TORTI). RICICLATRICE DI SOLDI CRIMINALISSIMI PER CONTO DI LEGA LADRONA ( = FAMOSI 49 MILIONI RUBATI, MA NON SOLO) E DI PEDOFILO, SPAPPOLA MAGISTRATI S= ILVIO BERLUSCONI. ECCO IL MIO TESTO, DICENTE, VE LO ASSICURO, ASSOLUTISSIME E DIMOSTABILISSIM= E VERITA'. IL FIGLIO DI PUTTANA ASSASSINO MATTEO SALVINI (I CUI FIGLI NAZISTI FIGLI MI= RTA SALVINI E FEDERICO SALVINI, FIGLI PURE DI NOTE "FASCISTROIE" GIULIA MAR= TINELLI E FABRIZIA IELUZZI, DI LUI, UN GIORNO, SI STRA VERGOGNERANNO), INSI= EME ALLA SCOPATA IN CULO DA MILLE MASSONI FILO MAFIOSI, NOTA PUTTANA ELISA = ISOARDI ( MEGA COCAINOMANE TROIA ELISA ISOARDI, PURE SU INSTAGRAM), STA CRE= ANDO LISTE DI PROSCRIZIONE OMICIDA! SI, OMICIDA (HA FATTO CREPARE 2000 PERS= ONE IN MARE, STO HITLERIANO KILLER DI MATTEO SALVINI, DA QUANDO COLERIZZA I= L VIMINALE https://www.ilfattoquotidiano.it/2018/06/28/migranti-romano-salvini-spieghi= -in-parlamento-morte-120-persone-scontro-con-borgonovo-che-lascia-la-trasmi= ssione/4458573/ http://www.ilsussidiario.net/News/Cronaca/2018/7/17/Saviano-choc-contro-Sal= vini-ti-eccitano-bimbi-morti-in-mare-Caso-Open-Arms-Ministro-Malavita-assas= sino-/830817/ E TUTTE LE UCCISIONI E VIOLENZE FISICHE A MIGRANTI DEGLI ULTIMI MESI, SON D= OVUTE, VOLUTE, INCITATE ED ORGANIZZATE DA LUI: E DI QUESTO NON NE PARLO CHI= SSA' QUANTO, IO, NE PARLA IL PER BENE PRESIDENTE DELLA REPUBBLICA SERGIO MA= TTARELLA, NON PER NIENTE, DI AMMIRABILE, NON "BERLUSCORROTTO" TIPO DI CENTR= O SINISTRA https://www.corriere.it/politica/18_luglio_25/mattarella-il-veleno-razzismo= -continua-creare-barriere-societa-b1f70e9e-8fee-11e8-9e3d-9a7bf81b9c8e.shtm= l ..... OGNI TANTO, QUESTO FIGLIO MEGA COCAINOMANE E BASTARDO FIGLIO DI NAZIS= TROIA MATTEO SALVINI (TWITTER, FACEBOOK, INSTAGRAM, WIKIPEDIA) FA FOTO CON = VENDITORI DI COLORE O FA ELEGGERE SUOI SCHIFOSI, CORROTTISSIMI, LECCA CULO = DI COLORE, MA E' TUTTO PURO DEPISTAGGIO, CONOSCO PERSONALISSIMAMENTE STO TO= PO DI FOGNA DI MATTEO SALVINI DA 20 ANNI, SO' CHE E' DA SEMPRE RAZZISTISSIM= O, BASTA VEDERE QUI, COME UMILIAVA A MORTE I GRANDI UOMINI E DONNE EI NAPUL= E https://www.politicaeattualita.it/2018/02/26/quando-matteo-salvini-cantava-= senti-che-puzza-scappano-anche-i-cani-stanno-arrivando-i-napoletani-video/ = )! 1 PER AMMAZZARE: FACENDO PASSARE OMICIDI DA LUI ORDINATI, PER "SOLITI" FINTI = SUICIDI, MALORI, INCIDENTI! OLTRE CHE TSO KILLER! COME GIA' ACCADETTE, NON = PER NIENTE, A RAFFICA, FRA IL 2001 ED IL 2006, COME FRA IL 2008 ED IL 2011.= ALLORCHE' IL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI, INSIEME AI KU= KLUKLANISTI, NDRANGHETISTI E NAZISTI ASSASSINI DI LEGA LADRONA, ORDINO' DI = "DISARTICOLARE LA VITA IN MANIERA TRAUMATICA", OSSIA DI UCCIDERE FACENDO PA= SSARE IL TUTTO PER QUALSIASI COSA CHE PARESSE NON UN OMICIDIO, MA CHE OMICI= DIO STRA ERA, CHIUNQUE NON LECCASSE IL DI DIETRO DELLE MERDE SANGUINARIE, A= SSASSINE, FASCIOMAFIOSE E NAZINDRANGHETISTE, CHE ALTRO, TUTTI QUESTI, NON S= ONO ( PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI IN PRIMIS)! COME QUAND= O GLI ASSASSINI MATTEO SALVINI, ROBERTO MARONI ED UMBERTO BOSSI ORDINARONO = E DAVANTI AI MIEI OCCHI, DI " SBULLONARE A MORTE" GLI ELICOTTERI DI GIORGIO= PANTO E PAOLO ALBERTI, FACENDO SFRACELLARE MORTALMENTE I DUE AL SUOLO. PER= FAR LORO AGARE L' ESSERE PASSATI CON OTTIMO ROMANO PRODI, NEL 2006!!! 2 =20 =20 IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://www.beppegrillo.it/linformazione-dellolio-di-ricino/ https://www.ariannaeditrice.it/articolo.php?id_articolo=3D6352 http://www.beppegrillo.it/linformazione-dellolio-di-ricino/ =20 =20 3 ED ANCORA http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://forum.enti.it/viewtopic.php?t=3D66625 http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm =20 =20 4 ALTRE DUE COSE, PLEASE. PRIMA. GLI ATTENTATI DI VARIO TIPO A CREMONA, TREVISO E BERGAMO, LEGA LADRO= NA, NAZISTA ED ASSASSINA, SE LI FA DA SOLI. PER FAR PASSARE IL NUOVO BASTAR= DO ADOLPH HITLER, CHE E' E STRA E' MATTEO SALVINI, PER VITTIMA. QUANDO E' S= OLO UN BAS.ARDO, ASSASSINO CARNEFICE. AFFINCHE' POSSA ESSERE OMICIDA PAZZO = CARNEFICE ANCORA DI PIU'. CLASSICA TATTICA DEL LUPO CHE SI METTE LA TESTA D= I AGNELLO, PER, DI NOTTE, POTER SBRANARTI MEGLIO. http://studiovanelli.com/wp-content/uploads/2017/03/Eliseu-Antonio-Gomes_E.= A.G._UBE-Blogs_UniC3A3o-de-Blogueiros-EvangC3A9licos_falso-pastor-pastor-jo= io.jpg SECONDA IMPORTANTISSIMA COSA. E' DA SEMPRE UNA SATANISTA E NAZISTA, OSSIA, = UNA SATANAZISTA PUTTANA: ELISA ISOARDI (FIGLI - INSTAGRAM). I CUI GENITORI,= NON PER NIENTE, SONO UN MASSONE PLURI OMICIDA DI CUNEO, CHE, NEGLI ANNI 80= E 90, HA AMMAZZATO E SOTTERRATO NEI BOSCHI LOCALI, ALMENO 60 PERSONE. COME= DA COTANTO DI SEGUENTI LINKS http://www.lastampa.it/2015/08/01/cuneo/scomparsi-da-anni-resta-il-mistero-= Q1u3ZmsLrLVEH43wjtxC8N/pagina.html https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ ED UNA NOTA TROIA SEMPRE SCOPATA DENTRO AL CULO: IRMA ISOARDI ( TROIONA COM= E ELISA ISOARDI: SANGUE MARCIO MAI MENTE). CHE NEGLI ANNI 80 E 90, SI CHIAV= AVANO TUTTI, SIA NELLA FIGA CHE NEL DI DIETRO, NEI CLUB PRIVE' DI FRANCIA, = PIEMONTE, LIGURIA E LOMBARDIA. COME IN TANTE SETTE SATANICHE E LOGGE MASSON= ICHE, SEMPRE DI FRANCIA, PIEMONTE, LIGURIA E LOMBARDIA. DOPO QUESTO DOVUTISSIMO ANTIPASTINO, ORA I PIATTI FORTI. PRIMA, PERO', IF YOU DON'T MIND, MI PRESENTO. SONO SIMONA PREMOLI. NOTISSIMA PORNOSTAR INTERNAZIONALE. LAUREATA IN SCIENZ= E POLITICHE ALLA CATTOLICA DI MILANO. "ASSOLUTA ESPERTA NELL'USO DELLA LING= UA" INTESO NEL SENSO CHE SONO INTERPRETE ( MA ANCHE INTESO IN "ALTRI SENSI"= ). E SPECIALMENTE: EX AGENTE CIA. A MILANO, IN TANTE ALTRE VARIE CITTA' DI BER= LUSCONIA-LEGALADRONUSCONIA-RENZUSCONIA-DIMAIOUSCONIA, COME A WASHINGTON DC,= IN PUERTO RICO, REPUBBLICA DOMINICANA, INGHILTERRA, SVIZZERA, ECT ECT. MA = ANCOR PIU' DI TUTTO CIO', SONO NOTA IN TUTTO IL GLOBO TERRESTRE PER ESSERE = STATA L'EX AMANTE LESBICA DELLA DEPRAVATA NAZIMAFIOSA MARINA BERLUSCONI. E = PER BEN 13 ANNI. https://plus.google.com/113646548587006228899 https://twitter.com/premolisimona?lang=3Des https://twitter.com/premolisimona/status/876056110033235969 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 MA SI, MI LASCIO ANDARE.. " MI SPOGLIO DI TUTTO"... HO APPENA FINITO DI GIR= ARE A MIAMI IL MIO GRANDISSIMO NUOVO PORN MOVIE, DAL TITOLO LUNGO, MA ELOQU= ENTISSIMO " LECCO LA FIGA DI MARINA BERLUSCONI, GIORNO E NOTTE, ANCHE NEI S= UOI UFFICI DI (MA)FI(A)NINVEST " . IN ANTEPRIMA MONDIALE, SI, MONDIALE, VI = FACCIO VEDERE UNA VINCENTISSIMA FOTO DEL FILM http://it.cultura.linguistica.narkive.com/XV3Bw8gY/sono-simona-premoli-ex-a= mante-lesbica-di-marina-berlusconi-e-per-ben-13-anni-e-13-ani-che-mi-sono:i= .1.1.thumb AL PUNTO CHE DAVVERO CONTA, ORA. MENTRE ERO AGENTE CIA ( PARTE PIU' DI ESTR= EMA DESTRA DELLA CIA), HO RICICLATO ALL'ESTERO MARI DI EURO CRIMINALISSIMI,= STRA RUBATI O FRUTTO DI MEGA MAZZETTE ( NOTI 49 MILIONI FREGATISSIMI E DI = CERTO NON SOLO), PER LEGA LADRONA ( CHE CON QUESTA ULTIMA MANOVRA CON 40 MI= LIARDI DI DEBITO INTENDE RUBARE E PRENDERE MAZZETTE PER ALTRI 490 MILIONI D= I EURO, NON "SOLO" 49). =20 =20 =20 5 E PER IL PEDOFILO SPAPPOLA MAGISTRATI: SILVIO BERLUSCONI. TUTTE IMMENSE FRO= DI, TRUFFE E MEGA TANGENTI CHE I PEZZI DI MERDA, HITLERIANI, COCAINOMANI, = CORROTTI, NDRANGHETISTI, LADRI ED ASSASSINI UMBERTO BOSSI, ROBERTO MARONI, = MATTEO SALVINI, ENNIO DORIS, MASSIMO DORIS, SILVIO BERLUSCONI E FEDELE CONF= ALONIERI, HAN BECCATO NEGLI ULTIMI ANNI DAI LORO ... - KAMERADEN NAZISTEN, BLOODTHIRSTY ASSASSIN VLADIMIR PUTIN ( THAT SCARE US = LESS THAN ZERO, WHEN "IT" SEND US HIS NAZIST MEGA SON OF FASCIST BITCHES FR= OM HIS RUSSIAN GESTAPOS, AS IT HAPPENES YESTERDAY, TO TRY TO INTIMIDATE US,= WHILE WE SCRIEAM AND SHOUT PURE TRUTHS, VIA COMPUTER: WE ALWAYS TELL THEM,= AT LEAST, ENORMOUS "FUCK OFF", TO SHOW THEM BELOW ZERO FEARS, EXACTLY AS I= T HAPPENED IN 24 HOURS AGO, MAKING THEM RUN AWAY). AND HIS FASCIST COCK SUC= KERS, MEGA RUSSIAN MAFIA MONEY LAUNDERES SILVIO BERLUSCONI, DONALD TRUMP AN= D VIKTOR ORBAN https://torino.corriere.it/sport/18_maggio_06/de-benedetti-salvini-antisemi= ta-finanziato-putin-leghista-querelo-8b0a05bc-5140-11e8-b393-1dfa8344f8a7.s= html OLTRE CHE DA BASTARD, CORRUPT, NAZIFASCIST WORM LEWIS EISENBERG, HITLERIAN = KAPO' OF PINOCHETTIAN US EMBASSY IN NAZIMAFIOSA TIRANNY OF BERLUSCONIA.....= . TO NOT TALK BOUT BEFORE MENTIONES DONALD "STINKY PEDOPHILE" TRUMP https://www.huffingtonpost.com/entry/donald-trump-rape-case_us_581a31a5e4b0= c43e6c1d9834 https://www.snopes.com/fact-check/are-we-not-going-to-talk-about-trump/ YES, MEGA COCAINE TAKER DONALD TRUMP (NAZIST KAPO' OF THE WHITE "POWDER" HO= USE, FOR WHO, I WD REPEAT SAME SPEECH DONE BEFORE FOR NAZIST ASSASSIN VLADI= MIR PUTIN, IN CASE WD BE MEGA HITLERIAN EXCREMENT DONALD TRUMP TO SEND US S= EWER RATS FROM HIS FASCIST PRESENT KIND OF CIA TO TRY TO INTIMIDATE US). MA= CCARTIST, MAFIOSO, MEGA MAFIA MONEY LAUNDERER, MEGA COCAINE TAKER, DEPRAVED= , PERVERT, PEDOPHILE DONALD TRUMP ( WHO IS ALSO THREATENING WITH THE STYLE = OF HIS BASTARD IDOL AL CAPONE, VIOLENCE, IF HE'LL LOOSE, AS HE ABSOLUTELY S= HOULD, NEXT US MID TERM ELECTIONS https://www.theguardian.com/us-news/2018/aug/28/donald-trump-midterms-priva= te-meeting-church-antifa ), SINCE ALWAYS, FINANCIAL WASHING MACHINE FOR RUS= SIAN MAFIA, CHINESE MAFIA CALLED TRIADE, SICILIAN MAFIA, NAPULITAN MAFIA, C= ALABRESIEDDA MAFIA, COLOMBIAN MAFIA http://www.newsweek.com/trump-russian-italian-mafia-fusion-785524 https://www.theaustralian.com.au/news/investigations/donald-trump-the-deals= -and-the-mafia-dons/news-story/40c61d98c72c3ba10064357c047ee8ce?nk=3D07c238= 2e7c9003d0828e92d735514bac-1532970957 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia http://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-ref= use-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html EXACTLY THE SAME .... REGARDING - NAZIFASCIST, RACIST, KUKLUKLANIST, AS MUCH AS STINKY MAFIA MONEY LAUNDERE= R AND PEDOPHILE PAUL SINGER FROM ELLIOTT FUND ( WHO IS A SLIMY, COWARD, HID= DEN, PEDERAST KIND OF HOMOSEXUAL, NO ONE HAS COURAGE TO TELL THAT, BUT I HA= VE IT AND SUPER STRA HAVE IT ) http://ryansorba.blogspot.com/2017/05/paul-singers-gay-agenda-punish-pay-of= f.html ME, PERSONALLY, SIMONA PREMOLI, I HAVE BEEN FOR 13 YEARS, MARINA BERLUSCONI= 'S HOTTEST LESBIAN LOVER, SO, IF THERE IS A LGBT FELLA, THAT'S ME.... BUT S= LIMY, COWARD, HIDDEN, SATANIC, NAZIST, MAFIOSI, PEDOPHILE KIND OF HOMOSEXUA= LS LIKE PAUL SINGER FROM ELLIOTT FUND, I DON'T LIKE THEM... SO I WILL SCREA= M AND SHOUT THIS, IN MILLIONS OF SITES OF ALL THIS PLANET .. FROM NOW ON...= AND BY THE WAY... "THE REAL POINT OF MY IMMENSE ANGER, EVEN MORE THAN IS K= ILLING PEDERASTY", IS THE FOLLOWING: SHAME ON YOU, NAZIST MAFIA MONEY LAUND= ERER AND WELL KNOWN PEDOPHILE HOMOSEXUAL PAUL SINGER FROM ELLIOTT FUND TO S= UPPORT ANOTHER PEDOPHILE LIKE YOU, FURTHERMORE ASSASSIN, MEGA PRINCIPAL OF = HUNDREDS OF MURDERS AND VERY BLOODTHIRSTY SLAUGHTERS LIKE HOMICIDE DICTATOR= SILVIO BERLUSCONI: SHAME ON YOU!!!!!!!!!!!!!!!!!!!!! https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ ) =20 =20 =20 6 - NAZIFASCIST RACIST KUKLUKLANIST PIG AS WELL AS MEGA MAFIA MONEY LAUNDERER= , AND ALSO SLIMY AND PERVERT KIND OF HOMOSEXUAL: GORDON SINGER FROM ELLIOTT= FUND - NAZIFASCIST RACIST KUKLUKLANIST PIG AS WELL AS MEGA MAFIA MONEY LAUNDERER= AND ALSO EVEN MORE SLIMY AND DEPRAVED KIND OD HOMOSEXUAL ANDREW SINGER FRO= M ELLIOTT FUND ( WHO DOES LOT OF VERY PERVERT ORGIES WITH VERY YOUNG BOYS E= VERYWHERE IN THE WORLD, NO ONE HAS COURAGE TO TELL THAT, BUT, AGAIN, I HAVE= IT AND SUPER STRA HAVE IT http://ryansorba.blogspot.com/2017/05/paul-singers-gay-agenda-punish-pay-of= f.html ) TO NOT WRITE BOUT BASTARD NAZIST, RACIST, KUKLKLANIST, COCAINE TAKER AND PE= DOPHILE STEVE BANNON WITH HIS SHITTY, KILLING, HITLERIAN PROPAGANDA RETROSP= ECTIVE COL TUTTO COORDINATO DAL NOTO IN TUTTO IL MONDO COME " ER POMPINARO DE AUGU= STO PINOCHET": MIKE POMPEO ( FAMOSO COLLEGA ED ONONIMO DI UN ALTRO NOTISSIM= O "POMPINARO DE AUGUSTO PINOCHET": " PIO POMPA"). A PROPOSITO DEL PRIMA CITATO, TUTTI I PRIMA DESCRITTI MEGA CRIMINI DI LEGA = LADRONA, RAZZISTA, NAZISTA, NDRANGHETISTA ED ASSASSINA, SONO GEMELLI DEGLI = STESSI CHE LEGA LADRONA, RAZZISTA, NAZISTA ED ASSASSINA, USAVA CONCRETIZZAR= E, NEI FAMOSI ANNI 2001-2006. FACENDOSI STECCARE IN GIRO PER IL MONDO, DA A= LTRI DITTATORI ASSASSINI QUALI GHEDDAFI, MUBARAK E BEN ALI' http://www.marcogregoretti.it/verita-nascoste/la-lega-nord-era-finanziata-d= a-gheddafi-gossip-elettorale-contro-il-centrodestra-o-storia-vera/ CIAO A TUTTI. SONO SIMONA PREMOLI, EX AMANTE DI MARINA BERLUSCONI PER BEN 1= 3 ANNI ED EX AGENTE DELLA CIA IN DIVERSI PAESI DEL MONDO ( BERLUSCONIA-LEGA= LADRONUSCONIA, USA, PUERTO RICO, REPUBBLICA DOMINICANA, INGHILTERRA, SVIZZE= RA, ECT ECT). https://plus.google.com/113646548587006228899 https://twitter.com/premolisimona?lang=3Den https://twitter.com/PremoliSimona/status/937885752003723265 https://twitter.com/premolisimona/status/876055837420158976 https://twitter.com/PremoliSimona/status/946915645756715009 https://twitter.com/PremoliSimona/status/946923968245784576 https://twitter.com/PremoliSimona/status/977570748847050754 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 =20 =20 =20 7 COME PRIMA CITATO, SONO STATA PER DECENNI DIETRO TANTI RICICLAGGI DI SOLDI = CRIMINALISSIMI DI LEGA LADRONA ( IN SVIZZERA, A PANAMA, ALLE BAHAMAS, ALLE = CAYMAN, ALLE SEYCHELLES, SPECIALMENTE AD HONG KONG, PRESSO WELL KNOWN KUKLU= KKLANIST, SATANAZIST, MEGA MAFIA MONEY LAUNDERER AND ALSO WELL KNOWN PEDOPH= ILE DANIEL HEGGLIN EX MORGAN STANLEY LONDON AND HONG KONG .. OR KUKLUKKLANI= ST, SATANAZIST, MEGA MAFIA MONEY LAUNDERER AND PEDOPHILE DANIEL "DANNY" HEG= GLIN EX MORGAN STANLEY LONDON AND HONG KONG..OR KUKLUKKLANIST, SATANAZIST, = MEGA MAFIA MONEY LAUNDERER AND PEDOPHILE DANIEL ROBERT HEGGLIN EX MORGAN ST= ANLEY LONDON AND HONG KONG). BASTARD ASSASSIN SON OF A BITCH DANIEL HEGGLIN= NOW WASHING KILLING MAFIA'S CASH BY SEVENOAKS, REALM THERAPEUTICS PLC AND = FOR SURE NOT ONLY https://alt.business.misc.narkive.com/iTvPQU8e/bastard-assassins-daniel-heg= glin-ex-morgan-stanley-arrested-3-times-paolo-barrai-mercato-libero-mkg- https://www.py.cz/pipermail/python/2017-March/012858.html NOTO "FIDUCIARY" DI TIPO CRIMINALISSIMO, DELLE NOTE BESTIE ASSASSINE DI COS= A NOSTRA, "QUANDO IN CRAVATTA": SILVIO BERLUSCONI, FEDELE CONFALONIERI, MAR= CELLO DELL'UTRI, MASSIMO DORIS, ENNIO DORIS. OSCAR DI MONTIGNY. SI, VOGLIO SPUTTANARE AL MASSIMO, STO PARTITO DI ESTREMISSIMA DESTRA, PRIMA= ANTI MERIDIONALI ( BASTA VEDERE QUESTO VIDEO DAVVERO BASTARDO https://vide= o.repubblica.it/politica/quando-salvini-cantava-senti-che-puzza-arrivano-i-= napoletani/291156/291766 ), POI, ANTI EROI DI CENTRO SINISTRA, POI ANTI ROM= , POI ANTI PERSONE DI COLORE, POI ANTI EBREI, DI QUEL FIGLIO DI PUTTANA HIT= LERIANO E RAZZISTISSIMO, TUTT'UNO CON COSA NOSTRA E E NDRANGHETA, CHIAMATO = " ASSASSINO MATTEO SALVINI ( CHE SE BEN NOTATE, STA INIZIANDOSI A MEGA CAGA= RE SOTTO NEI CONFRONTI DI FINANZA MONDIALE, UE ED EROICI PM AGRIGENTINI, EF= FETTUANDO RETROMARCE SU RETROMARCE A GO GO: MERDACCIA DI QUAQUARQUA CHE ALT= RO NON E' ". GIA' BEN SMERDATO DA GRANDI GIORNALISTI DE L'ESPRESSO, E NON S= OLO, QUI: http://espresso.repubblica.it/inchieste/2018/07/04/news/soldi-lega-la-lette= ra-che-incastra-salvini-1.324561?ref=3DRHRR-BE http://espresso.repubblica.it/inchieste/2018/05/31/news/alla-lega-sovranist= a-di-matteo-salvini-piace-offshore-1.323128 http://espresso.repubblica.it/inchieste/2018/04/13/news/i-soldi-offshore-de= lla-fondazione-targata-lega-1.320530 http://espresso.repubblica.it/inchieste/2018/03/28/news/i-conti-segreti-di-= matteo-salvini-1.320080 http://www.ilsussidiario.net/News/Cronaca/2018/6/3/L-Espresso-contro-la-Leg= a-Gli-affari-dei-cassieri-di-Salvini-holding-in-Lussemburgo-ragnatela-di-fi= duciarie/823987// COME DA AMMIRABILISSIMO GEORGE SOROS QUI: http://www.repubblica.it/economia/2018/06/03/news/soros_preoccupato_della_v= icinanza_del_nuovo_governo_con_la_russia_-198062920/). ED AGGIUNIGAMO UN ALTRA IMPORTANTISSIMA COSA, ORA, PLEASE. IO SIMONA PREMOL= I, SON PURE STATA PER TANTISSIMO TEMPO, COMPLICE, COLLUSA, "INTIMISSIMA" CO= LLABORATRICE DEL ^NEOLD^ PIDUISTA, NONCHE' MEGA RICICLA SOLDI DI MILLE MAFI= E: GIANPIERO SAMOR=C3=8C DEL CRIMINALISSIMO MOVIMENTO "MODERATI IN RIVOLUZI= ONE", ( MODERATI... DI TIPO MALAVITOSISSIMO). ORA PERO' MI INCAZZO E DICO B= ASTA A STA FOGNA DI COSA NOSTRA, CAMORRA E NDRANGHETA FINANZIARIA CHE DA SE= MPRE STI PEZZI DI MERDA BERLUSCONAZISTI E PADANAZISTI RAPPRESENTANO ( VI AS= SICURO, SPESSO, PURE PEDOFILI, STUPRA UOMINI E DONNE, IMMENSAMENTE COCAINOM= ANI, STRAGISTI ED ASSASSINI, IN QUANTO ORDINANTI DOZZINE DI STRAGI E MIGLIA= IA DI OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI ED INCIDENTI, IL TUTTO VI= A VARIE LORO LOGGE MASSONICHE OMICIDA). =20 =20 =20 8 NE ERO DENTRO. E DA LORO "LO PRENDEVO IN CONTINUAZIONE DENTRO". QUINDI SO' = QUESTO ALLA PERFEZIONE PER AVER VISSUTO TUTTO QUESTO, NON SOLO VISTO. I BAS= TARDI ASSASSINI E STRAGISTI SILVIO BERLUSCONI, PAOLO BERLUSCONI, MARINA BER= LUSCONI, OSCAR DI MONTIGNY, PAOLO BARRAI, GIOVANNI PUIROVANO, MASSIMO DORIS= ED ENNIO DORIS ORDINANO DOZZINE DI STRAGI E MIGLIAIA DI OMICIDI MASCHERATI= DA FINTI SUICIDI, MALORI ED INCIDENTI, IL TUTTO VIA VARIE LORO LOGGE MASSO= NICHE KILLER, COME ANCHE ATTRAVERSO MAFIA, CAMORRA, NDRANGHETA, A CUI LAVAN= O MONTAGNE DI SOLDI ZUPPI DI SANGUE DI MORTI AMMAZZATI, ED ANCOR PIU', ATTR= AVERSO LORO SANGUINARIE NUOVE OVRA E GESTAPO, SIA PUBBLICHE CHE PRIVATE) . GUARDATE BENE QUESTA CHART, ORA, PLS https://www.worldcoinindex.com/coin/eidoo LEGA LADRONA HA RICICLATO 22 MILIONI DI EURO, IN QUESTA FALLIMENTARISSIMA I= CO ( PARTE DEI FAMOSI 200 MILIONI E NON SOLO 48 MILIONI DI EURO RUBATI DA P= ARTE DI LEGA LADRONA). ATTRAVERSO IL PIU' GRANDE CRIMINALE DELLA FINANZA MO= NDIALE: TOPO DI FOGNA, GIA' FINITO 3 VOLTE IN GALERA, PAOLO BARRAI, NATO A = MILANO IL 28.6.1965 ( O TOPO DI FOGNA, PIU' GRANDE CRIMINALE DELLA FINANZA = MONDIALE, GIA' FINITO 3 VOLTE IN GALERA, PAOLO PIETRO BARRAI, NATO A MILANO= IL 28.6.1965 CHE STA A LUGANO, ORA, PER NON FINIRE IN CARCERE A MILANO... = PER UNA 4TA VOLTA... FA PURE RIMA, WAGLIO'). QUESTA ICO HA SEMPRE AVUTO VOL= UMI BASSISSIMI ( SCAMBI PER UNA QUALCHE DECINA DI MIGLIAIA DI EURO AL GIORN= O). MA DOPO CHE IN DATA 3.6.18 HO INIZIATO A SCRIVERE ALL OVER THE WORLD, D= EI MEGA RICICLAGGI DI SOLDI LERCISSIMI DI LEGA LADRONA IN CRIMINALISSIMA E = FALLIMENTARISSIMA EIDOO ( ORA IL PEZZO DI MERDA, NAZIMAFIOSO, PEDOFILO DONA= LD TRUMP HA ORDINATO DI FARLA LINKARE ALL'ORO FISICO PER FARNE SALIRE IL PR= EZZO: BUONO A SAPERCI, CI FAREMO UN MARE DI SOLDI ANCHE NOI, VISTO CHE CONO= SCIAMO LE SUE, COME AL SOLITO, MEGA TRUFFALDINE INTENZIONI). NEI GIORNI SUB= ITO A SEGUIRE, LA STESSA, DA NOI SGAMATISSIMA, LEGA LADRONA, HA SUPER STRA = DATO ORDINE DI VENDERE EIDOO PER UN TOTALE DI 22 MILIONI DI EURO. COL STRA = PIENO INTENTO DI MONETIZZARE TUTTO ( CON PERDITE DEL 50 PER CENTO E PASSA..= .... AHAHHA, CHE DEFICENTI ED IDIOTA A LIVELLO IMMENSO). E QUINDI FAR SPARI= RE LORO CRIMINALISSIMI SOLDI. PIU' PROVA DI COSI', CHE STO PONENDO DITA SU = GIUSTISSIME LORO MALAVITOSE PIAGHE? IO VOGLIO O MOVIMENTO S STELLE ED INTER= O CENTRO SINISTRA A PALAZZO CHIGI (MA SENZA LA MERDA BERLUSCORROTTA DI MAT= TEO RENZI, SENZA LA MERDA BERLUSCORROTTA DI CARLO CALENDA, SENZA LA MERDA B= ERLUSCORROTTA DI MARIA ELENA BOSCHI, SENZA LA MERDA BERLUSCORROTTA DI MATTE= O ORFINI, SENZA LA MERDA BERLUSCORROTTA DI LUCA LOTTI, SENZA LA MERDA BERLU= SCORROTTA DI LORENZO GUERINI E LORO BERLUSMAZZETTATA GANG VARIA... DATE IL = PAESE A LEU UNITO AD UN PD CAPEGGIATO DA MICHELE EMILIANO ED OLIVIERO TOSCA= NI, FONDENDO IL TUTTO AD UN M5S GUIDATO DA ALFONSO BONAFEDE O ROBERTO FICO,= CHE SIA ANTI PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI AL CALOR BIANC= O, ED IL NOSTRO PAESE AVRA' UN MEGA BOOM DI SUCCESSO). O LA RIVOLUZIONE ED = A TUTTI I COSTI ( NIENTE NAZISMO, RAZZISMO, KUKLUKLANISMO, MAFIA, CAMORRA E= NDRANGHETA DI LEGA LADRONA NEL MIO PAESE: RESISTENZA ANTI ASSASSINI SWASTI= KATI E NDRANGHETISTI PADANI DA SUBITO)! AVANTI TUTTA! QUESTO ORGANIZZERO' A= TUTTI I COSTI!!! E CON CENTINAIA SERVIZI SEGRETI DI TUTTO IL PIANETA TERRA= , COL TUTTO DIRETTO FAL GENIO DELLA FINANZA E POLITICA MONDIALE, L'EROE GEO= RGE SOROS: MIO AMICO " INTIMISSIMO" DA TANTI ANNI !!!!!!! =20 =20 =20 9 INFINE, UNA COSA DA DONNA, CHE HO PROPRIO SULLA BOCCA DELLO STOMACO! CHE SCHIFOSA PUTTANA E' ELISA ISOARDI: TROIA, RAZZISTA, SATANAZISTA ( DIETR= O TANTI OMICIDI E SPARIZIONI SATANISTE ACCADUTE NEL CUNEENSE http://www.lastampa.it/2015/08/01/cuneo/scomparsi-da-anni-resta-il-mistero-= Q1u3ZmsLrLVEH43wjtxC8N/pagina.html OMICIDI E SPARIZIONI MESSI INSIEME DA LEI E DA SUA CAMERATA, PUTTANONA E SA= TANAZISTA TANTO QUANTO, TROIONA ASSASSINA ELISA COGNO DI FONDAZIONE FERRERO= E CRIMINALISSIMA FRUIMEX DI ALBA https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcTHQttqmomN5UqEFCqaQ= oHfDaGoM5h3v-CQKio0lUpRaNYK_fWd ). IN RAI SOLO ED ESCLUSIVAMENTE IN QUANTO = CIUCCIA E PRENDE IN CULO E FIGA MILLE CAZZI SU CAZZI DI HITLERIANI PADANI. = PER NULLA, SOLO QUELLO DELLA MERDA SWASTIKATA, OMICIDA E CORNUTONA: MATTEO = SALVINI. A 16 ANNI, LA NAZISTROIA ELISA ISOARDI GIA' LO PRENDEVA NELL'ANO E= NELLA VAGINA, CONTEMPORANEAMENTE, E PER SOLI 30 EURO DI ALLORA. SIA DA ERN= ESTO PREATONI, CHE DA FLAVIO BRIATORE ( COME DETTOMI DAI DUE, DI PERSONA E = TANTE VOLTE) http://www.today.it/gossip/love-corn/elisa-isoardi-briatore-insieme.html LA SCORSA ESTATE SCOPAVA ALLO STESSO TEMPO, UN AVVOCATO CRIMINALE, VICINISS= IMO A NDRANGHETA, CAMORRA E MAFIA, TALE MATTEO PLACIDI E NEGLI STESSISSIMI GIORNI, ANCHE LA BESTIA HITLERIANA, MEGA FREGA SOLDI, F= ASCISTA, KUKLUKLANISTA, COCAINOMANE, CORROTTA, INSOMMA, IL NOTO FIGLIO DI P= UTTANA, RAZZISTA, PAZZO DA RINCHIUDERE, NAZISTASSASSINO MATTEO SALVINI !!!S= IMONA PREMOLI. FOLLOW ME, BABY, ON ... https://plus.google.com/113646548587006228899 https://plus.google.com/116623248459204832762 https://plus.google.com/111758080075778412781 https://twitter.com/premolisimona?lang=3Des https://twitter.com/premolisimona/status/876055837420158976 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 ALSO FOLLOW ME, BABY, ON... https://groups.google.com/forum/#!topic/it.sport.calcio.milan/LrFDw8c8PQ0 From newsfish@newsfish Thu Aug 1 00:43:57 2024 X-Received: by 2002:a05:660c:8d2:: with SMTP id g18mr816922itl.2.1541794343465; Fri, 09 Nov 2018 12:12:23 -0800 (PST) X-Received: by 2002:a25:50cd:: with SMTP id e196-v6mr100525ybb.0.1541794343341; Fri, 09 Nov 2018 12:12:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!news.muarf.org!nntpfeed.proxad.net!feeder1-1.proxad.net!proxad.net!feeder1-2.proxad.net!209.85.166.216.MISMATCH!g188-v6no780577itg.0!news-out.google.com!n199-v6ni1130itn.0!nntp.google.com!g188-v6no780575itg.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Nov 2018 12:12:23 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.66.7.216; posting-account=IrEjCgoAAAD7Xu3yovPq55XCEnUmnODH NNTP-Posting-Host: 87.66.7.216 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> Subject: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI OMICIDA A LUGANO! From: ANDREAS NIGG BANK VONTOBEL ZURICH Injection-Date: Fri, 09 Nov 2018 20:12:23 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9376 FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMA= NO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E CO= L PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA = SOLDI OMICIDA A LUGANO! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Barrai. Di delinquentissima Bigbit, delinquentissima Bgbit Ne= ws Channel e delinquentissima @bigbitnewschannel. Attraverso i quali strume= nti, lui ed il fallitissimo, idiota, davvero deficente, incapace, falliment= are trader Federico Izzi di Roma (che campa, di fatto, riciclando soldi maf= iosi e facendo film pedopornofrafici, tanto e' vero che sta merda criminali= ssima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da chiunqu= e, come "Er Zio Romolo incula bambini e pure come Er Zio Romolo della Camor= ra"). Sti due pezzi di merda criminalissimi spennano " i polli del web=C2= =A8, vendendo loro abbonamenti annuali su criptovalute e non solo, totalmen= te fallimentari ( delinquentissimo servizio chiamato Bigbit) Che ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mostra= rvi centinaia di casi, venuti, disperati, a piangersene da me, a proposito)= . Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno scara= faggio della Ndrangheta ( e di fallimentarissima Eidoo). Si, proprio cosi',= insieme al figlio di puttana Natale Massimiliano Ferrara di Reggio Calabri= a, uno scarafaggio della Ndrangheta ( e di fallimentarissima Eidoo). Imbosc= atosi qui in Svizzera, per non finire in galera, ben appunto, a Reggio Cala= bria. Che ha rifilato a la merda di Ico completamente fallimentare chiamata= Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone na= zipedofilo Donald Trump sta cercando di tirargli su detta merda, il tutto, = ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, tira su, co= me al solito, anche, i suoi tre grammi giornalieri di cocaina, presso la Wh= ite "Powder" House) . Torniamo in ogni caso, ora, al punto iniziale, bitte.= Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo c= acciato immediatamente il ladrone, truffatore, pure mandante di omicidi e n= otissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truf= fatore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai n= ato a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. F= ra i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri,= il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la = Mafia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto = fiduciario di ndrangheta)! Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, che come Er Zio Romolo della Camorra"). Nien= te merda nella nuova Finter Bank Zurich. Il puzzo della merda, scusate il t= emine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega = omicida dal figlio di puttana criminalissimo Fabrizio Cieslakiewicz di Banc= a dello Stato Lugano, dal figlio di puttana criminalissimo Daniele Albisett= i di Banca dello Stato Lugano, dal figlio di puttana criminalissimo Claudio= Genasci di Banca dello Stato Lugano, dal figlio di puttana criminalissimo = Patrick Lafranchi di Banca dello Stato Lugano, dal figlio di puttana crimin= alissimo Gabriele Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH. From newsfish@newsfish Thu Aug 1 00:43:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!news.nask.pl!news.nask.org.pl!newsfeed2.atman.pl!newsfeed.atman.pl!.POSTED!not-for-mail From: gof@somewhere.invalid (Adam Wysocki) Newsgroups: comp.lang.vhdl Subject: VHDL-2008 first steps and simulator for Linux Date: Thu, 8 Mar 2018 12:54:32 +0000 (UTC) Organization: ATMAN - ATM S.A. Lines: 95 Message-ID: NNTP-Posting-Host: vps.chmurka.net X-Trace: node2.news.atman.pl 1520513672 12259 81.4.124.88 (8 Mar 2018 12:54:32 GMT) X-Complaints-To: usenet@atman.pl NNTP-Posting-Date: Thu, 8 Mar 2018 12:54:32 +0000 (UTC) User-Agent: tin/2.4.1-20161224 ("Daill") (UNIX) (Linux/4.4.50-v7+ (armv7l)) Cancel-Lock: sha1:FhN1Dpgm+EcXCYsgnI2p6VBhh1s= Xref: reader01.eternal-september.org comp.lang.vhdl:9377 Hi, I started learning VHDL from the book "The Designer's Guide To VHDL" (third edition) and I'm trying to make my first steps in it. One of the exercises at the end of the first chapter asks to write an entity declaration and a behavioral architecture body of a simple multiplexer. Two inputs ('a' and 'b'), one selection input ('sel') and one output, 'z', becoming 'a' if sel is 0, or 'b' if sel is 1. I wrote the following code: #v+ entity mux2 is port (a, b, sel: in bit; z: out bit); end entity mux2; architecture mux2_behav of mux2 is begin mux2: process is begin if sel then z <= b after 5ns; else z <= a after 5ns; end if; end process mux2; end architecture mux2_behav; #v- (without test bench yet) and now I wanted to simulate it (I'm not sure if it's possible without writing a test bench, but at least I want to have a semantically correct architecture body). Debian's apt-cache finds two simulators: fauhdlc - experimental VHDL compiler and interpreter freehdl - VHDL simulator for Linux Unfortunately, gvhdl (freehdl's frontend) says that: #v+ $ gvhdl ch1-10.vhdl gvhdl: FreeHDL root path is '/usr'. gvhdl: executing '/usr/bin/freehdl-v2cc -m ch1-10._main_.cc -L /usr/share/freehdl/lib -o ch1-10.cc ch1-10.vhdl' ch1-10.vhdl: in mux2(mux2_behav): ch1-10.vhdl:7: sel does not match required type BOOLEAN, its type could be: /usr/share/freehdl/lib/std/standard.vhdl:6: BIT v2cc: ch1-10.vhdl: 1 errors gvhdl: Compilation failed! Died at /usr/bin/gvhdl line 211. #v- fauhdl doesn't recognize '5ns' symbol: #v+ $ fauhdlc ch1-10.vhdl ERROR> ch1-10.vhdl:8: Symbol '5ns' undefined. ERROR> ch1-10.vhdl:10: Symbol '5ns' undefined. #v- and after commenting it out says something similar to gvhdl: #v+ $ fauhdlc ch1-10.vhdl ERROR> ch1-10.vhdl:7: Type error for . #v- I understand that the statement "if sel then" is invalid for 'sel' being a bit type, and not a boolean type. This leads to my questions: 1. What am I doing wrong? Is it illegal to compare bits this way, or is it legal only since a certain VHDL language version? The book says that it's legal, but examples from the book fail with similar messages. 2. I don't know the VHDL version simulated by these two simulators, and if they support VHDL-2008 or not. I read that comments /* ... */ are illegal in VHDL versions prior to 2008, so I tried them in these simulators and they complained, so I guess they support an older VHDL version. I don't see any option to switch them to the 2008 version. 3. What simulators do you use or recommend? I prefer Linux ones (it would be much easier for me), but if there are no reasonable ones, I can use Windows ones as well. I want them only to test and simulate my code snippets during learning. My final goal is to be able to make models suitable for synthesis and upload into CPLD and FPGA devices. Thank you! -- [ Adam Wysocki :: Warsaw, Poland ] [ Email: a@b a=grp b=chmurka.net ] [ Web: http://www.chmurka.net/ ] From newsfish@newsfish Thu Aug 1 00:43:58 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: VHDL-2008 first steps and simulator for Linux Date: Tue, 20 Nov 2018 10:06:04 +0200 Organization: An impatient and LOUD arachnid Lines: 30 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain Injection-Info: reader01.eternal-september.org; posting-host="7e1c83b219b99f35be0dee6d70ca70e5"; logging-data="23237"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Dkqq1CZIXuPdJaxfI7DCM" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) Cancel-Lock: sha1:tIvDFOKNB3nsToLfHs55wYsdxGk= sha1:lxyTfz8Y0qtBGzRTlCVFLhJ5dfQ= Xref: reader01.eternal-september.org comp.lang.vhdl:9378 gof@somewhere.invalid (Adam Wysocki) writes: > fauhdl doesn't recognize '5ns' symbol: Usually the time unit is specified separately from the value, so 5 ns instead of 5ns. > 1. What am I doing wrong? Is it illegal to compare bits this way, or is it > legal only since a certain VHDL language version? The book says that it's > legal, but examples from the book fail with similar messages. AFAIK, VHDL 2008 is needed for this kind of comparison. > 3. What simulators do you use or recommend? I prefer Linux ones (it would > be much easier for me), but if there are no reasonable ones, I can use > Windows ones as well. I want them only to test and simulate my code > snippets during learning. My final goal is to be able to make models > suitable for synthesis and upload into CPLD and FPGA devices. I use Modelsim and Questa for work. Some FPGA vendors (at least Intel) provide a free, "starter edition" of Modelsim for free. Which is usually some versions behind and slows down if your design gets larger than some limit. Great for small designs though. Of the free simulators I've tried GHDL very briefly in Debian Linux some time ago. GHDL is currently not in the package repositories so I built from source which was somewhat complicated. And took up a surprising amount of space I needed for other stuff so I deleted it. Also I have no good idea on how well it supports VHDL 2008, support is described as "partial" in the readme (https://github.com/ghdl/ghdl). From newsfish@newsfish Thu Aug 1 00:43:58 2024 X-Received: by 2002:ac8:287b:: with SMTP id 56mr7172052qtr.14.1542896570950; Thu, 22 Nov 2018 06:22:50 -0800 (PST) X-Received: by 2002:a81:450:: with SMTP id 77mr158892ywe.6.1542896570547; Thu, 22 Nov 2018 06:22:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!v55no2920738qtk.0!news-out.google.com!m21ni5133qta.0!nntp.google.com!v55no2920730qtk.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Nov 2018 06:22:50 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2405:204:9498:6ea3:1466:39f3:2ea:5b4; posting-account=CvCyDAoAAACwpRoXfYw4KIzXPsnaon22 NNTP-Posting-Host: 2405:204:9498:6ea3:1466:39f3:2ea:5b4 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e7cced4-17c5-4a47-914d-a44cfc6de8f7@googlegroups.com> Subject: converting input string into prefix or postfix format From: viraj.deochake16@vit.edu Injection-Date: Thu, 22 Nov 2018 14:22:50 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9379 Hello, I am trying to implement a basic calculator in vhdl. I need to convert the input string (eg. 2+3*4-10/5)into a prefix or postfix format so that priorities of operations can be sorted out. Is their any way available? From newsfish@newsfish Thu Aug 1 00:43:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder.erje.net!2.eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx27.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: converting input string into prefix or postfix format Newsgroups: comp.lang.vhdl References: <0e7cced4-17c5-4a47-914d-a44cfc6de8f7@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 MIME-Version: 1.0 In-Reply-To: <0e7cced4-17c5-4a47-914d-a44cfc6de8f7@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 181122-4, 22/11/2018), Outbound message X-Antivirus-Status: Clean Lines: 11 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 22 Nov 2018 17:06:44 UTC Organization: virginmedia.com Date: Thu, 22 Nov 2018 17:06:46 +0000 X-Received-Bytes: 1415 X-Received-Body-CRC: 981426135 Xref: reader01.eternal-september.org comp.lang.vhdl:9380 On 22/11/2018 14:22, viraj.deochake16@vit.edu wrote: > Hello, I am trying to implement a basic calculator in vhdl. I need to convert the input string (eg. 2+3*4-10/5)into a prefix or postfix format so that priorities of operations can be sorted out. Is their any way available? > My 5 second advice would be to google some C/C+/Python/.. implementation and then translate into VHDL. In effect you need an FSM and a Stack both are fairly easy to do in VHDL. Good luck, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:43:59 2024 X-Received: by 2002:a37:ab12:: with SMTP id u18mr15264031qke.51.1547933737904; Sat, 19 Jan 2019 13:35:37 -0800 (PST) X-Received: by 2002:a81:7a02:: with SMTP id v2mr254971ywc.3.1547933737257; Sat, 19 Jan 2019 13:35:37 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!v55no3556152qtk.0!news-out.google.com!m21ni2555qta.0!nntp.google.com!v55no3556151qtk.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 19 Jan 2019 13:35:36 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=89.154.158.148; posting-account=fqiLNwoAAACxh6M36Pnzf8NP-rvFKYRV NNTP-Posting-Host: 89.154.158.148 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: =?UTF-8?Q?LO_SCHIFOSO_NAZISTA_FEDERICO_SALVINI_SI_VERGOGNERA=27_?= =?UTF-8?Q?DEL_FIGLIO_DI_PUTTANA_PADRE_CHE_HA_IN_MATTEO_SALVINI=2E_E_DI_L?= =?UTF-8?Q?UI_SI_VERGOGNERA=27_PURE_LA_FASCISTROIA_FABRIZIA_IELUZZI_=28_CHE?= =?UTF-8?Q?_NASCONDEVA_A_CASA_DEL_SUO_CRIMINALISSIMO_PADRE_LINO_IELUZZI?= =?UTF-8?Q?=2C_2_MILIONI_DI_=E2=82=AC=2E=2E?= From: SIMONA PREMOLI EX MARINA-BERLUSCONI-S LESBIAN-LOVER Injection-Date: Sat, 19 Jan 2019 21:35:37 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9381 LO SCHIFOSO NAZISTA FEDERICO SALVINI SI VERGOGNERA' DEL FIGLIO DI PUTTANA P= ADRE CHE HA IN MATTEO SALVINI. E DI LUI SI VERGOGNERA' PURE LA FASCISTROIA = FABRIZIA IELUZZI ( CHE NASCONDEVA A CASA DEL SUO CRIMINALISSIMO PADRE LINO = IELUZZI, 2 MILIONI DI =E2=82=AC..... DI DIAMANTI, OVVIA PARTE DEI 49 MILION= I RUBATI DA LEGA LADRONA) ! IL PEZZO DI MERDA ASSASSINO MATTEO SALVINI FA L= A PUBBLICITA' ALLA MERDOSA NUTELLA, IN QUANTO I CRIMINALISSIMI FERRERO, SON= DA SEMPRE FASCISTI, RAZZISTI E SATANISTI COME LUI. "Mio figlio, passato dalle Bestie di Satana alla Lega Nord" https://www.youtube.com/watch?v=3DCrfIbm-9wHY http://www.dagospia.com/rubrica-3/politica/ldquo-vade-retro-salvini-rdquo-n= dash-copertina-39-39-famiglia-179527.htm 1 LO FA ANCHE IN QUANTO ALLA CRIMINALISSIMA FONDAZIONE FERRERO DI ALBA E PUR= E ALLA CRIMINALISSIMA FRUIMEX SAS DI ALBA, LAVORA UNA NOTA PUTTANA LUCIFERI= NA, HITLERIANA, RAZZISTA E MOLTO ASSASSINA TANTO QUANTO: ELISA COGNO https://www.instagram.com/p/Bcc0zWonbtv/ (DIETRO TANTI OMICIDI DA LEI ESEGUITI, DI SATANISTI, AVVENUTI IN SUA ZONA https://www.altriconfini.it/2013/06/lombra-delle-sette-sataniche-nei-suicid= i-in-provincia-di-cuneo/ https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.notizieprovita.it/notizie-dallitalia/satanismo-in-fiera-da-vita= -a-proteste-indignate/ PARTE PURE DELLA SETTA SANGUINARISSIMA PIEMONTESE " AMMAZZIAMO PER SATANA"= E DI MERDONI SVASTIKATI DI BLOOD AND HONOR). CHE E' BEN APPUNTO DI ALBA (S= CRIVEREMO DI LEI ANCHE ALLA FINE DI QUESTO TESTO). ED E' PAPPA E CICCIA CON= IL NOTO PADANAZISTA, SATANISTA E PURE MOLTO OMICIDA MAURIZIO BARBERO DI TE= CHNOSKY MONTESETTEPANI, https://it.linkedin.com/in/maurizio-barbero-a521978 https://pbs.twimg.com/profile_images/698221802565279744/7hEZuIO__400x400.jp= g IL TUTTO E' CONNESSISSIMO ALLA MEGA TROIA ANCORA PIU' SATANISTA E NAZIFASC= ISTA: ELISA ISOARDI! NON PER NIENTE, ANCHE LEI DI CUNEO ( COME DI CUNEO E' = LA KAPO' PUZZONA DI TUTTI STI TOPI DI FOGNA ASSASSINI, LA MOSTRUOSA BAGASCI= A, MEGA COCAINOMANE, SEMPRE CON MILLE CAZZI IN CULO: DANIELA SANTANCHE' ...= O MOSTRUOSA BAGASCIA, MEGA COCAINOMANE, SEMPRE CON MILLE CAZZI IN CULO: DA= NIELA GARNERO SANTANCHE' ). =20 2 AND NEVER FORGET, PLEASE: IL MARITO, FIGLIO E CAMERATA DI PUTTANE MATTEO SA= LVINI STA CREANDO LISTE DI PROSCRIZIONE OMICIDA, SI OMICIDA ( BASTA CHE GUA= RDATE QUESTI NAZISTISSIMI, ASSASSINI DI DEMOCRAZIA, ARTICOLI E VIDEOS https://globalist.it/media/2018/12/15/un-cartello-con-scritto-ama-il-prossi= mo-tuo-picchiato-e-portato-via-a-forza-dal-comizio-di-salvini-2034955.html https://www.lastampa.it/2018/12/15/italia/jacopo-e-natalia-fermati-in-piazz= a-per-il-cartello-ama-il-prossimo-tuo-vlBRbvbI1ikvQEpMpLKprO/pagina.html https://it.blastingnews.com/cronaca/2018/11/roma-casalinga-60enne-da-del-bu= ffone-a-salvini-fermata-e-denunciata-002771157.html https://www.youtube.com/watch?v=3D3ENKQI5f5tA PER NON PARLARE DI COME ABBIA FATTO CREPARE 5000 PERSONE IN MARE, STO TOPO = DI FOGNA OMICIDA DI MATTEO SALVINI, DA QUANDO COLERIZZA IL VIMINALE https:/= /www.ilfattoquotidiano.it/2018/06/28/migranti-romano-salvini-spieghi-in-par= lamento-morte-120-persone-scontro-con-borgonovo-che-lascia-la-trasmissione/= 4458573/ )! BUT FIRST, LET'S GO WORLDWIDE WITH THIS, BABY! MAFIOSO, FASCIST, DEPRAVED PEDOPHILE DONALD TRUMP TOGETHER AT NAZIST KILLER= VLADIMIR PUTIN USE CORRUPT, PROTECTOR OF CAMORRA, NDRANGHETA & COSA NOSTRA= , AS WELL AS RACIST, KUKLUKLANIST, SCAMMERS, LIARS, THIEFTS, MAFIA MONEY LA= UNDERERS, PRINCIPAL OF.....HUNDREDS OF (MASKED) HOMICIDES AND DOZENS OF SLA= UGHTERS, MEGA CRIMINAL DICTATORS AND ASSASSIN MATTEO SALVINI AND SILVIO BER= LUSCONI, TO DESTABILIZE, THEN DESTROY, THEN DISINTEGRATE EUROPE!!! ED ORA VAMOS A FARE LA STORIA, DE VERDAD !!!!!! BY SIMONA PREMOLI. FOR 13 YEARS MARINA BERLUSCONI'S NUMBER ONE LESBIAN LOV= ER ( BETWEEN HUNDREDS). EX CIA AGENT IN MANY COUNTRIES OF THE WORLD ( IN MY= CITY OF MILAN, IN LONDON, IN ZURICH, IN BERLIN, IN DOMINICAN REPUBLIC, IN = PUERTO RICO, IN WASHINGTON DC). VERY WELL KNOWN MASKED PORNSTAR. FEMALE FRE= EMASON OF VERY HIGH DEGREE. INTEPRETER ( ITALIAN, ENGISH, SPANISH). DIRTY M= ONEY LAUNDERER FOR NAZIST ASSASSIN MATTEO SALVINI FROM LEGA NORD ( BETTER K= NOWN AS LEGA LADRONA) AND FOR MEGA PRINCIPAL OF MURDERS AND SLAUGHTERS, SLI= MY, CRIMINAL PEDOPHILE SILVIO BERLUSCONI. BY SIMONA PREMOLI DI MILANO. PER 13 ANNI, NUMERO UNO, FRA CENTINAIA E CENT= INAIA DI AMANTI LESBICHE DI MEGA COCAINOMANE, CRIMINALISSIMA MARINA BERLUSC= ONI. EX AGENTE CIA IN MIA CITTA' DI MILANO, COME IN ROMA, BERLINO, ZURIGO, = LONDRA, REPUBBLICA DOMINICANA, PORTORICO, WASHINGTON DC. CONOSCIUTISSIMA E = CALDISSIMA PORNOSTAR, MA SEMPRE E SOLO CON MASCHERINA, PER, OVVIAMENTE, NON= INTRALCIARE MIEI MOLTO IMPORTANTI LAVORI SOPRA CITATI. GRAN MAESTRO MASSON= ICO. INTERPRETE ( IN TANTI DICONO, CHE PIU' CHE INTERPRETE, CHE SONO " ESPE= RTISSIMA NELL'USO DELLA LINGUA). RICICLATRICE DI SOLDI CRIMINALISSIMI DI LE= GA LADRONA ( FAMOSI 49 MILIONI RUBATI, MA NON SOLO) E DI SPAPPOLA MAIGSTRAT= I, NONCHE' VOMITEVOLE PEDOFILO SILVIO BERLUSCONI. ECCO ORA UN MIO TESTO, DICENTE, VE LO ASSICURO, TANTE ASSOLUTISSIME E DIM= OSTRABILISSIME VERITA'. IL FIGLIO DI PUTTANA ASSASSINO MATTEO SALVINI (I CUI FIGLI NAZISTI FIGLI M= IRTA SALVINI E FEDERICO SALVINI, FIGLI PURE DI NOTE "FASCISTROIE" GIULIA MA= RTINELLI E FABRIZIA IELUZZI, DI LUI, UN GIORNO, SI STRA VERGOGNERANNO), INS= IEME ALLA SCOPATA IN CULO DA MILLE MASSONI FILO MAFIOSI, NOTA PUTTANA ELISA= ISOARDI ( MEGA COCAINOMANE TROIA ELISA ISOARDI, PURE SU INSTAGRAM), STA CR= EANDO LISTE DI PROSCRIZIONE OMICIDA! SI, OMICIDA! HA FATTO CREPARE 2000 PER= SONE IN MARE, STO HITLERIANO KILLER DI MATTEO SALVINI, DA QUANDO COLERIZZA = IL VIMINALE https://www.ilfattoquotidiano.it/2018/06/28/migranti-romano-salvini-spieghi= -in-parlamento-morte-120-persone-scontro-con-borgonovo-che-lascia-la-trasmi= ssione/4458573/ http://www.ilsussidiario.net/News/Cronaca/2018/7/17/Saviano-choc-contro-Sal= vini-ti-eccitano-bimbi-morti-in-mare-Caso-Open-Arms-Ministro-Malavita-assas= sino-/830817/ 3 E TUTTE LE UCCISIONI E VIOLENZE FISICHE A MIGRANTI DEGLI ULTIMI MESI, SON = DOVUTE, VOLUTE, INCITATE ED ORGANIZZATE DA LUI: E DI QUESTO NON NE PARLO CH= ISSA' QUANTO, IO, NE PARLA IL PER BENE PRESIDENTE DELLA REPUBBLICA SERGIO M= ATTARELLA, NON PER NIENTE, DI AMMIRABILE, NON "BERLUSCORROTTO" TIPO DI CENT= RO SINISTRA https://www.corriere.it/politica/18_luglio_25/mattarella-il-veleno-razzismo= -continua-creare-barriere-societa-b1f70e9e-8fee-11e8-9e3d-9a7bf81b9c8e.shtm= l OGNI TANTO, QUESTO FIGLIO MEGA COCAINOMANE E BASTARDO FIGLIO DI NAZISTROIA = MATTEO SALVINI (TWITTER, FACEBOOK, INSTAGRAM, WIKIPEDIA) FA FOTO CON VENDIT= ORI DI COLORE O FA ELEGGERE SUOI SCHIFOSI, CORROTTISSIMI, LECCA CULO DI COL= ORE, MA E' TUTTO PURO DEPISTAGGIO, CONOSCO PERSONALISSIMAMENTE STO TOPO DI = FOGNA DI MATTEO SALVINI DA 20 ANNI, SO' CHE E' DA SEMPRE RAZZISTISSIMO, BAS= TA VEDERE QUI, COME UMILIAVA A MORTE I GRANDI UOMINI E DONNE EI NAPULE https://www.politicaeattualita.it/2018/02/26/quando-matteo-salvini-cantava-= senti-che-puzza-scappano-anche-i-cani-stanno-arrivando-i-napoletani-video/ = ! IL FIGLIO DI PUTTANA MATTEO SALVINI VUOLE FAR AMMAZZARE CHIUNQUE LO FOTOGR= AFI PER IL NUOVO ADOLPH HITLER ASSASSINO CHE EGLI ALTRO NON E', FACENDO PAS= SARE OMICIDI DA LUI ORDINATI, PER "SOLITI" FINTI SUICIDI, MALORI, INCIDENTI= ! OLTRE CHE TSO KILLER! COME GIA' ACCADETTE, NON PER NIENTE, A RAFFICA, FRA IL 2001 ED IL 2006, COM= E FRA IL 2008 ED IL 2011. ALLORCHE' IL PEDOFILO SPAPPOLA MAGISTRATI SILVIO = BERLUSCONI, INSIEME AI KUKLUKLANISTI, NDRANGHETISTI E NAZISTI ASSASSINI DI = LEGA LADRONA, ORDINO' DI "DISARTICOLARE LA VITA IN MANIERA TRAUMATICA", OSS= IA DI UCCIDERE FACENDO PASSARE IL TUTTO PER QUALSIASI COSA CHE PARESSE NON = UN OMICIDIO, MA CHE OMICIDIO STRA ERA, CHIUNQUE NON LECCASSE IL DI DIETRO D= ELLE MERDE SANGUINARIE, ASSASSINE, FASCIOMAFIOSE E NAZINDRANGHETISTE, CHE A= LTRO, TUTTI QUESTI, NON SONO ( PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCO= NI IN PRIMIS)! COME QUANDO GLI ASSASSINI MATTEO SALVINI, ROBERTO MARONI ED UMBERTO BOSSI = ORDINARONO E DAVANTI AI MIEI OCCHI, DI " SBULLONARE A MORTE" GLI ELICOTTERI= DI GIORGIO PANTO E PAOLO ALBERTI, FACENDO SFRACELLARE MORTALMENTE I DUE AL= SUOLO. PER FAR LORO AGARE L' ESSERE PASSATI CON OTTIMO ROMANO PRODI, NEL 2= 006!!! IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-= SEGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ =20 =20 =20 =20 =20 =20 4 E POI ANCORA.. http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://forum.enti.it/viewtopic.php?t=3D66625 http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm =20 =20 =20 =20 =20 =20 5 E STRA ANCORA.. https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 https://www.agoravox.it/Documenti-segreti-made-in-Italy.html https://www.ariannaeditrice.it/articolo.php?id_articolo=3D6352 ALTRE DUE COSE, PLEASE. PRIMA. GLI ATTENTATI DI VARIO TIPO A CREMONA, TREVISO E BERGAMO, LEGA LADR= ONA, NAZISTA ED ASSASSINA, SE LI FA DA SOLI. PER FAR PASSARE IL NUOVO BASTA= RDO ADOLPH HITLER, CHE E' E STRA E' MATTEO SALVINI, PER VITTIMA. QUANDO E' = SOLO UN BAS.ARDO, ASSASSINO CARNEFICE. AFFINCHE' POSSA ESSERE OMICIDA PAZZO= CARNEFICE ANCORA DI PIU'. CLASSICA TATTICA DEL LUPO CHE SI METTE LA TESTA = DI AGNELLO, PER, DI NOTTE, POTER SBRANARTI MEGLIO. http://studiovanelli.com/wp-content/uploads/2017/03/Eliseu-Antonio-Gomes_E.= A.G._UBE-Blogs_UniC3A3o-de-Blogueiros-EvangC3A9licos_falso-pastor-pastor-jo= io.jpg SECONDA IMPORTANTISSIMA COSA. E' DA SEMPRE UNA SATANISTA E NAZISTA, OSSIA,= UNA SATANAZISTA PUTTANA: ELISA ISOARDI (FIGLI - INSTAGRAM). I CUI GENITORI= , NON PER NIENTE, SONO UN MASSONE PLURI OMICIDA DI CUNEO, CHE, NEGLI ANNI 8= 0 E 90, HA AMMAZZATO E SOTTERRATO NEI BOSCHI LOCALI, ALMENO 60 PERSONE. COM= E DA COTANTO DI SEGUENTI LINKS http://www.lastampa.it/2015/08/01/cuneo/scomparsi-da-anni-resta-il-mistero-= Q1u3ZmsLrLVEH43wjtxC8N/pagina.html https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ ED UNA NOTA PUTTANONA SEMPRE SCOPATA DENTRO AL CULO: IRMA ISOARDI ( TROION= A COME ELISA ISOARDI: SANGUE MARCIO MAI MENTE). CHE NEGLI ANNI 80 E 90, SI = CHIAVAVANO TUTTI, SIA NELLA FIGA CHE NELL'ANO, NEI CLUB PRIVE' DI FRANCIA, = PIEMONTE, LIGURIA E LOMBARDIA. COME IN TANTE SETTE SATANICHE E LOGGE MASSON= ICHE, SEMPRE DI FRANCIA, PIEMONTE, LIGURIA E LOMBARDIA. DOPO QUESTO DOVUTISSIMO ANTIPASTINO, ORA I PIATTI FORTI. PRIMA, PERO', IF YOU DON'T MIND, MI PRESENTO. SONO SIMONA PREMOLI. NOTA PORNOSTAR IN TUTTO IL MONDO. LAUREATA IN SCIENZE= POLITICHE ALLA CATTOLICA DI MILANO. "ASSOLUTA ESPERTA NELL'USO DELLA LINGU= A" INTESO NEL SENSO CHE SONO INTERPRETE ( MA ANCHE INTESO IN "ALTRI SENSI")= . =20 =20 =20 =20 =20 6 E SPECIALMENTE: EX AGENTE CIA A LIVELLO MONDIALE. A MILANO, COME IN TANTE = ALTRE VARIE CITTA' DI BERLUSCONIA-LEGALADRONUSCONIA-RENZUSCONIA-DIMAIOUSCON= IA, COME A WASHINGTON DC, IN PUERTO RICO, REPUBBLICA DOMINICANA, INGHILTERR= A, SVIZZERA, ECT ECT. MA ANCOR PIU' DI TUTTO CIO', SONO NOTA IN TUTTO IL GL= OBO TERRESTRE PER ESSERE STATA L'EX AMANTE LESBICA DELLA DEPRAVATA NAZIMAFI= OSA MARINA BERLUSCONI. E PER BEN 13 ANNI. https://plus.google.com/113646548587006228899 https://twitter.com/premolisimona?lang=3Des https://twitter.com/premolisimona/status/876056110033235969 https://profile.theguardian.com/user/id/12251903?page=3D1 AL PUNTO CHE DAVVERO CONTA, ORA. MENTRE ERO AGENTE CIA ( PARTE PIU' DI EST= REMA DESTRA DELLA CIA), HO RICICLATO ALL'ESTERO MARI DI EURO CRIMINALISSIMI= , STRA RUBATI O FRUTTO DI MEGA MAZZETTE ( NOTI 49 MILIONI FREGATISSIMI E DI= CERTO NON SOLO), PER LEGA LADRONA ( CHE CON QUESTA ULTIMA MANOVRA CON 40 M= ILIARDI DI DEBITO INTENDE RUBARE E PRENDERE MAZZETTE PER ALTRI 490 MILIONI = DI EURO, NON "SOLO" 49). E PER IL PEDOFILO SPAPPOLA MAGISTRATI: SILVIO BERLUSCONI. TUTTE IMMENSE FR= ODI, TRUFFE E MEGA TANGENTI CHE I PEZZI DI MERDA, HITLERIANI, COCAINOMANI, = CORROTTI, NDRANGHETISTI, LADRI ED ASSASSINI UMBERTO BOSSI, ROBERTO MARONI, = MATTEO SALVINI, ENNIO DORIS, MASSIMO DORIS, SILVIO BERLUSCONI E FEDELE CONF= ALONIERI, HAN BECCATO NEGLI ULTIMI ANNI DAI LORO ... - KAMERADEN NAZISTEN, BLOODTHIRSTY ASSASSIN VLADIMIR PUTIN ( THAT SCARE US= LESS THAN ZERO, WHEN "IT" SEND US HIS NAZIST MEGA SON OF FASCIST BITCHES F= ROM HIS RUSSIAN GESTAPOS, AS IT HAPPENES YESTERDAY, TO TRY TO INTIMIDATE US= , WHILE WE SCRIEAM AND SHOUT PURE TRUTHS, VIA COMPUTER: WE ALWAYS TELL THEM= , AT LEAST, ENORMOUS "FUCK OFF", TO SHOW THEM BELOW ZERO FEARS, EXACTLY AS = IT HAPPENED IN 24 HOURS AGO, MAKING THEM RUN AWAY). AND HIS FASCIST COCK SU= CKERS, MEGA RUSSIAN MAFIA MONEY LAUNDERES SILVIO BERLUSCONI, DONALD TRUMP A= ND VIKTOR ORBAN https://torino.corriere.it/sport/18_maggio_06/de-benedetti-salvini-antisemi= ta-finanziato-putin-leghista-querelo-8b0a05bc-5140-11e8-b393-1dfa8344f8a7.s= html OLTRE CHE DA BASTARD, CORRUPT, NAZIFASCIST WORM LEWIS EISENBERG, HITLERIAN= KAPO' OF PINOCHETTIAN US EMBASSY IN NAZIMAFIOSA TIRANNY OF BERLUSCONIA....= .. TO NOT TALK BOUT BEFORE MENTIONES DONALD "STINKY PEDOPHILE" TRUMP https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.huffingtonpost.com/entry/donald-trump-rape-case_us_581a31a5e4b0= c43e6c1d9834 https://www.snopes.com/fact-check/are-we-not-going-to-talk-about-trump/ =20 =20 =20 =20 =20 7 YES, MEGA COCAINE TAKER DONALD TRUMP (NAZIST KAPO' OF THE WHITE "POWDER" H= OUSE, FOR WHO, I WD REPEAT SAME SPEECH DONE BEFORE FOR NAZIST ASSASSIN VLAD= IMIR PUTIN, IN CASE WD BE MEGA HITLERIAN EXCREMENT DONALD TRUMP TO SEND US = SEWER RATS FROM HIS FASCIST PRESENT KIND OF CIA TO TRY TO INTIMIDATE US). M= ACCARTIST, MAFIOSO, MEGA MAFIA MONEY LAUNDERER, MEGA COCAINE TAKER, DEPRAVE= D, PERVERT, PEDOPHILE DONALD TRUMP ( WHO IS ALSO THREATENING WITH THE STYLE= OF HIS BASTARD IDOL AL CAPONE, VIOLENCE, IF HE'LL LOOSE, AS HE ABSOLUTELY = SHOULD, NEXT US MID TERM ELECTIONS https://www.theguardian.com/us-news/2018/aug/28/donald-trump-midterms-priva= te-meeting-church-antifa ), SINCE ALWAYS, FINANCIAL WASHING MACHINE FOR RU= SSIAN MAFIA, CHINESE MAFIA CALLED TRIADE, SICILIAN MAFIA, NAPULITAN MAFIA, = CALABRESIEDDA MAFIA, COLOMBIAN MAFIA http://www.newsweek.com/trump-russian-italian-mafia-fusion-785524 https://www.theaustralian.com.au/news/investigations/donald-trump-the-deals= -and-the-mafia-dons/news-story/40c61d98c72c3ba10064357c047ee8ce?nk=3D07c238= 2e7c9003d0828e92d735514bac-1532970957 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia http://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-ref= use-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html EXACTLY THE SAME .... REGARDING - NAZIFASCIST, RACIST, KUKLUKLANIST, AS MUCH AS STINKY MAFIA MONEY LAUNDER= ER AND PEDOPHILE PAUL SINGER FROM ELLIOTT FUND ( WHO IS A SLIMY, COWARD, HI= DDEN, PEDERAST KIND OF HOMOSEXUAL, NO ONE HAS COURAGE TO TELL THAT, BUT I H= AVE IT AND SUPER STRA HAVE IT ) http://ryansorba.blogspot.com/2017/05/paul-singers-gay-agenda-punish-pay-of= f.html ME, PERSONALLY, SIMONA PREMOLI, I HAVE BEEN FOR 13 YEARS, MARINA BERLUSCON= I'S HOTTEST LESBIAN LOVER, SO, IF THERE IS A LGBT FELLA, THAT'S ME.... BUT = SLIMY, COWARD, HIDDEN, SATANIC, NAZIST, MAFIOSI, PEDOPHILE KIND OF HOMOSEXU= ALS LIKE PAUL SINGER FROM ELLIOTT FUND, I DON'T LIKE THEM... SO I WILL SCRE= AM AND SHOUT THIS, IN MILLIONS OF SITES OF ALL THIS PLANET .. FROM NOW ON..= . AND BY THE WAY... "THE REAL POINT OF MY IMMENSE ANGER, EVEN MORE THAN IS = KILLING PEDERASTY", IS THE FOLLOWING: SHAME ON YOU, NAZIST MAFIA MONEY LAUN= DERER AND WELL KNOWN PEDOPHILE HOMOSEXUAL PAUL SINGER FROM ELLIOTT FUND TO = SUPPORT ANOTHER PEDOPHILE LIKE YOU, FURTHERMORE ASSASSIN, MEGA PRINCIPAL OF= HUNDREDS OF MURDERS AND VERY BLOODTHIRSTY SLAUGHTERS LIKE HOMICIDE DICTATO= R SILVIO BERLUSCONI: SHAME ON YOU!!!!!!!!!!!!!!!!!!!!! https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ ) - NAZIFASCIST RACIST KUKLUKLANIST PIG AS WELL AS MEGA MAFIA MONEY LAUNDERE= R, AND ALSO SLIMY AND PERVERT KIND OF HOMOSEXUAL: GORDON SINGER FROM ELLIOT= T FUND - NAZIFASCIST RACIST KUKLUKLANIST PIG AS WELL AS MEGA MAFIA MONEY LAUNDERE= R AND ALSO EVEN MORE SLIMY AND DEPRAVED KIND OD HOMOSEXUAL ANDREW SINGER FR= OM ELLIOTT FUND ( WHO DOES LOT OF VERY PERVERT ORGIES WITH VERY YOUNG BOYS = EVERYWHERE IN THE WORLD, NO ONE HAS COURAGE TO TELL THAT, BUT, AGAIN, I HAV= E IT AND SUPER STRA HAVE IT http://ryansorba.blogspot.com/2017/05/paul-singers-gay-agenda-punish-pay-of= f.html ) TO NOT WRITE BOUT BASTARD NAZIST, RACIST, KUKLKLANIST, COCAINE TAKER AND P= EDOPHILE STEVE BANNON WITH HIS SHITTY, KILLING, HITLERIAN PROPAGANDA RETROS= PECTIVE. =20 =20 =20 =20 =20 =20 8 COL TUTTO COORDINATO DAL NOTO IN TUTTO IL MONDO COME " ER POMPINARO DE AUG= USTO PINOCHET": MIKE POMPEO ( FAMOSO COLLEGA ED ONONIMO DI UN ALTRO NOTISSI= MO "POMPINARO DE AUGUSTO PINOCHET": " PIO POMPA"). PER NON PARLARE DEL PEZZO DI MERDA, NAZIFASCISTA, STALKER ASSASSINO VIA IN= TERNET, NOTISSIMO PEDOFILO LUCA MORISI DI LEGA LADRONA, TWITTER E LINKEDIN ( SON OF A BITCH AND WELL KNOWN PEDOPHILE LUCA MORISI: ASSASSIN, NAZIST, S= OCIAL MEDIA STRATEGIST) https://it.linkedin.com/in/luca-morisi-315b10b E PER NON RIPARLARE DEL BASTARDO ASSASSINO GENNARO VECCHIONE DEL DIS ( FIG= LIO DI CANE GENNARO VECCHIONE, NOTO PER ESSERE ANCHE UN DEPRAVATISSIMO RICC= HIONE) ED IL PEZZO DI MERDA MEGA OMICIDA LUCIANO CARTA DELL'AISE ( CHE VUOL= E AMMAZZARE CHIUNQUE NON SIA NAZIFASCISTA COME LUI E LA CAROGNA MEGA KILLER= MATTEO SALVINI, OVUNQUE NEL MONDO, FATE VOI CHE RISPETTO PER LA DEMOCRAZIA= , STI RATTI COLERICI ABBIANO). TRATTASI DI DUE TOPI DI FOGNA, CORROTTISSIMI= DA SILVIO BERLUSCONI E LEGA LADRONA, QUANDO A KAPO' DELLA GUARDIA DI FINAN= ZA. DI CUI RIVELERO' TANTISSIMI ALTRI PARTICOLARI, PROSSIMAMENTE. A PROPOSITO DEL PRIMA CITATO, TUTTI I PRIMA DESCRITTI MEGA CRIMINI DI LEGA= LADRONA, RAZZISTA, NAZISTA, NDRANGHETISTA ED ASSASSINA, SONO GEMELLI DEGLI= STESSI CHE LEGA LADRONA, RAZZISTA, NAZISTA ED ASSASSINA, USAVA CONCRETIZZA= RE, NEI FAMOSI ANNI 2001-2006. FACENDOSI STECCARE IN GIRO PER IL MONDO, DA = ALTRI DITTATORI ASSASSINI QUALI GHEDDAFI, MUBARAK E BEN ALI' http://www.marcogregoretti.it/verita-nascoste/la-lega-nord-era-finanziata-d= a-gheddafi-gossip-elettorale-contro-il-centrodestra-o-storia-vera/ CIAO A TUTTI. SONO SIMONA PREMOLI, EX AMANTE DI MARINA BERLUSCONI PER BEN = 13 ANNI ED EX AGENTE DELLA CIA IN DIVERSI PAESI DEL MONDO ( BERLUSCONIA-LEG= ALADRONUSCONIA, USA, PUERTO RICO, REPUBBLICA DOMINICANA, INGHILTERRA, SVIZZ= ERA, ECT ECT). https://plus.google.com/113646548587006228899 https://twitter.com/premolisimona?lang=3Den https://twitter.com/PremoliSimona/status/937885752003723265 https://twitter.com/premolisimona/status/876055837420158976 https://twitter.com/PremoliSimona/status/946915645756715009 https://twitter.com/PremoliSimona/status/946923968245784576 https://twitter.com/PremoliSimona/status/977570748847050754 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 =20 =20 =20 =20 =20 9 COME PRIMA CITATO, SONO STATA PER DECENNI DIETRO TANTI RICICLAGGI DI SOLDI = CRIMINALISSIMI DI LEGA LADRONA ( IN SVIZZERA, A PANAMA, ALLE BAHAMAS, ALLE = CAYMAN, ALLE SEYCHELLES, SPECIALMENTE AD HONG KONG, PRESSO WELL KNOWN KUKLU= KKLANIST, SATANAZIST, MEGA MAFIA MONEY LAUNDERER AND ALSO WELL KNOWN PEDOPH= ILE DANIEL HEGGLIN EX MORGAN STANLEY LONDON AND HONG KONG .. OR KUKLUKKLANI= ST, SATANAZIST, MEGA MAFIA MONEY LAUNDERER AND PEDOPHILE DANIEL "DANNY" HEG= GLIN EX MORGAN STANLEY LONDON AND HONG KONG). BASTARD ASSASSIN SON OF A BIT= CH DANIEL HEGGLIN NOW WASHING KILLING MAFIA'S CASH BY SEVENOAKS, REALM THER= APEUTICS PLC AND FOR SURE NOT ONLY https://alt.business.misc.narkive.com/iTvPQU8e/bastard-assassins-daniel-heg= glin-ex-morgan-stanley-arrested-3-times-paolo-barrai-mercato-libero-mkg- https://www.py.cz/pipermail/python/2017-March/012858.html https://lists.mozilla.org/pipermail/dev-platform/2014-September/006516.html NOTO "FIDUCIARY" DI TIPO CRIMINALISSIMO, DELLE NOTE BESTIE ASSASSINE DI CO= SA NOSTRA, "QUANDO IN CRAVATTA": SILVIO BERLUSCONI, FEDELE CONFALONIERI, MA= RCELLO DELL'UTRI, MASSIMO DORIS, ENNIO DORIS. OSCAR DI MONTIGNY. SI, VOGLIO SPUTTANARE AL MASSIMO, STO PARTITO DI ESTREMISSIMA DESTRA, PRIM= A ANTI MERIDIONALI ( BASTA VEDERE QUESTO VIDEO DAVVERO BASTARDO https://vid= eo.repubblica.it/politica/quando-salvini-cantava-senti-che-puzza-arrivano-i= -napoletani/291156/291766 ), POI, ANTI EROI DI CENTRO SINISTRA, POI ANTI RO= M, POI ANTI PERSONE DI COLORE, POI ANTI EBREI, DI QUEL FIGLIO DI PUTTANA HI= TLERIANO E RAZZISTISSIMO, TUTT'UNO CON COSA NOSTRA E E NDRANGHETA, CHIAMATO= " ASSASSINO MATTEO SALVINI ( CHE SE BEN NOTATE, STA INIZIANDOSI A MEGA CAG= ARE SOTTO NEI CONFRONTI DI FINANZA MONDIALE, UE ED EROICI PM AGRIGENTINI, E= FFETTUANDO RETROMARCE SU RETROMARCE A GO GO: MERDACCIA DI QUAQUARQUA CHE AL= TRO NON E' ". GIA' BEN SMERDATO DA GRANDI GIORNALISTI DE L'ESPRESSO, E NON = SOLO, QUI: http://espresso.repubblica.it/inchieste/2018/07/04/news/soldi-lega-la-lette= ra-che-incastra-salvini-1.324561?ref=3DRHRR-BE http://espresso.repubblica.it/inchieste/2018/05/31/news/alla-lega-sovranist= a-di-matteo-salvini-piace-offshore-1.323128 http://espresso.repubblica.it/inchieste/2018/04/13/news/i-soldi-offshore-de= lla-fondazione-targata-lega-1.320530 http://espresso.repubblica.it/inchieste/2018/03/28/news/i-conti-segreti-di-= matteo-salvini-1.320080 http://www.ilsussidiario.net/News/Cronaca/2018/6/3/L-Espresso-contro-la-Leg= a-Gli-affari-dei-cassieri-di-Salvini-holding-in-Lussemburgo-ragnatela-di-fi= duciarie/823987// COME DA AMMIRABILISSIMO GEORGE SOROS QUI: http://www.repubblica.it/economia/2018/06/03/news/soros_preoccupato_della_v= icinanza_del_nuovo_governo_con_la_russia_-198062920/ ). ED AGGIUNIGAMO UN ALTRA IMPORTANTISSIMA COSA, ORA, PLEASE. IO SIMONA PREMO= LI, SON PURE STATA PER TANTISSIMO TEMPO, COMPLICE, COLLUSA, "INTIMISSIMA" C= OLLABORATRICE DEL ^NEOLD^ PIDUISTA, NONCHE' MEGA RICICLA SOLDI DI MILLE MAF= IE: GIANPIERO SAMOR=C3=8C DEL CRIMINALISSIMO MOVIMENTO "MODERATI IN RIVOLUZ= IONE", ( MODERATI... DI TIPO MALAVITOSISSIMO). ORA PERO' MI INCAZZO E DICO = BASTA A STA FOGNA DI COSA NOSTRA, CAMORRA E NDRANGHETA FINANZIARIA CHE DA S= EMPRE STI PEZZI DI MERDA BERLUSCONAZISTI E PADANAZISTI RAPPRESENTANO ( VI A= SSICURO, SPESSO, PURE PEDOFILI, STUPRA UOMINI E DONNE, IMMENSAMENTE COCAINO= MANI, STRAGISTI ED ASSASSINI, IN QUANTO ORDINANTI DOZZINE DI STRAGI E MIGLI= AIA DI OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI ED INCIDENTI, IL TUTTO V= IA VARIE LORO LOGGE MASSONICHE OMICIDA). =20 =20 =20 =20 =20 =20 10 NE ERO DENTRO. E DA LORO "LO PRENDEVO IN CONTINUAZIONE DENTRO". QUINDI SO'= QUESTO ALLA PERFEZIONE PER AVER VISSUTO TUTTO QUESTO, NON SOLO VISTO. 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NEI GIORNI SU= BITO A SEGUIRE, LA STESSA, DA NOI SGAMATISSIMA, LEGA LADRONA, HA SUPER STRA= DATO ORDINE DI VENDERE EIDOO PER UN TOTALE DI 22 MILIONI DI EURO. COL STRA= PIENO INTENTO DI MONETIZZARE TUTTO ( CON PERDITE DEL 50 PER CENTO E PASSA.= ..... AHAHHA, CHE DEFICENTI ED IDIOTA A LIVELLO IMMENSO). E QUINDI FAR SPAR= IRE LORO CRIMINALISSIMI SOLDI. PIU' PROVA DI COSI', CHE STO PONENDO DITA SU= GIUSTISSIME LORO MALAVITOSE PIAGHE? IO VOGLIO O MOVIMENTO S STELLE ED INTE= RO CENTRO SINISTRA A PALAZZO CHIGI (MA SENZA LA MERDA BERLUSCORROTTA DI MAT= TEO RENZI, SENZA LA MERDA BERLUSCORROTTA DI CARLO CALENDA, SENZA LA MERDA B= ERLUSCORROTTA DI MARIA ELENA BOSCHI, SENZA LA MERDA BERLUSCORROTTA DI MATTE= O ORFINI, SENZA LA MERDA BERLUSCORROTTA DI LUCA LOTTI, SENZA LA MERDA BERLU= SCORROTTA DI LORENZO GUERINI E LORO BERLUSMAZZETTATA GANG VARIA... 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FOLLOW ME, SWEET SWEET BABY, ON ... https://plus.google.com/113646548587006228899 https://plus.google.com/116623248459204832762 https://plus.google.com/111758080075778412781 https://profile.theguardian.com/user/id/12251903?page=3D1 https://twitter.com/premolisimona?lang=3Des https://twitter.com/premolisimona/status/876055837420158976 From newsfish@newsfish Thu Aug 1 00:43:59 2024 X-Received: by 2002:a0c:981c:: with SMTP id c28mr13778063qvd.51.1549654396909; Fri, 08 Feb 2019 11:33:16 -0800 (PST) X-Received: by 2002:a25:1144:: with SMTP id 65mr224775ybr.0.1549654396833; Fri, 08 Feb 2019 11:33:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no1324794qta.0!news-out.google.com!f18ni983qto.0!nntp.google.com!m21no1324785qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 Feb 2019 11:33:16 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.234.91.250; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.234.91.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> Subject: x^2 From: stchebel@gmail.com Injection-Date: Fri, 08 Feb 2019 19:33:16 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 2 Xref: reader01.eternal-september.org comp.lang.vhdl:9382 x : std_logic_vector(12 downto 0); -- unsigned integer Should be implemented in spartan-6 but without using on chip multiplicators. Any ideas for an efficient code? From newsfish@newsfish Thu Aug 1 00:44:00 2024 X-Received: by 2002:a37:4d55:: with SMTP id a82mr14371646qkb.41.1549682255543; Fri, 08 Feb 2019 19:17:35 -0800 (PST) X-Received: by 2002:a25:ab82:: with SMTP id v2mr230802ybi.3.1549682255425; Fri, 08 Feb 2019 19:17:35 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!m21no1951243qta.0!news-out.google.com!q39ni2875qtk.1!nntp.google.com!m21no1951239qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 Feb 2019 19:17:35 -0800 (PST) In-Reply-To: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: x^2 From: gnuarm.deletethisbit@gmail.com Injection-Date: Sat, 09 Feb 2019 03:17:35 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 26 Xref: reader01.eternal-september.org comp.lang.vhdl:9383 On Friday, February 8, 2019 at 2:33:18 PM UTC-5, stch...@gmail.com wrote: > x : std_logic_vector(12 downto 0); -- unsigned integer >=20 > Should be implemented in spartan-6 but without using on chip multiplicato= rs. Any ideas for an efficient code? Personally, I find multipliers to be a PITA to code. One thing you have in= your favor for calculating a square is that all the results will be positi= ve or zero. So you don't need a bipolar multiplication. Just take the abs= olute value of your input before the multiply assuming the input is signed = as opposed to unsigned. =20 I see in your comment "unsigned integer" which means you can either convert= your input SLV to an unsigned type or to an integer type with a range of 0= to 4095 before you multiply to form the square. Keep in mind your result = will need twice as many bits if you want to retain full resolution. I assume this is a class assignment? Does your instructor care if the algo= rithm is small, fast, easy to code or some combination? A simple approach = for positive number multiplies is shift and add. A more complex, but small= er implementation (and maybe faster as well) is a Booth's algorithm or mayb= e a modified Booth's algorithm.=20 Oh yeah, please use numeric_std and not std_logic_arith. If you don't know= why, just ask. That's one point that most people here get.=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: x^2 Date: Sat, 09 Feb 2019 09:49:43 +0100 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: reader02.eternal-september.org; posting-host="2951126b10af06c697ac2674b6fe4b94"; logging-data="18484"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18o7IdeprTx+YeLKMVPt7LG" User-Agent: Groundhog Newsreader for Android Cancel-Lock: sha1:TJPA6dkt52eaQCCdK97uGXFDlXs= In-Reply-To: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> Xref: reader01.eternal-september.org comp.lang.vhdl:9384 On Fri, 8 Feb 2019 11:33:16 -0800 (PST), stchebel@gmail.com wrote: > Should be implemented in spartan-6 but without using on chip multiplicators. Any ideas for an efficient code? Search for the attribute MULT_STYLE in the XST User Guide for Spartan6. Bart Fox From newsfish@newsfish Thu Aug 1 00:44:00 2024 X-Received: by 2002:ac8:4918:: with SMTP id e24mr16178183qtq.15.1549721867658; Sat, 09 Feb 2019 06:17:47 -0800 (PST) X-Received: by 2002:a5b:30c:: with SMTP id j12mr257803ybp.5.1549721867328; Sat, 09 Feb 2019 06:17:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsreader4.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no2694290qta.0!news-out.google.com!f18ni1801qto.0!nntp.google.com!m21no2694281qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Feb 2019 06:17:47 -0800 (PST) In-Reply-To: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <89cfc212-e51c-4ad1-bf1b-2af33656c8b2@googlegroups.com> Subject: Re: x^2 From: KJ Injection-Date: Sat, 09 Feb 2019 14:17:47 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 2099 X-Received-Body-CRC: 993536152 Xref: reader01.eternal-september.org comp.lang.vhdl:9385 On Friday, February 8, 2019 at 2:33:18 PM UTC-5, stch...@gmail.com wrote: > x : std_logic_vector(12 downto 0); -- unsigned integer > > Should be implemented in spartan-6 but without using on chip multiplicators. Any ideas for an efficient code? What is your definition of 'efficient'? Here are a few: - Minimal coding effort, most easily supportable: Then XSquared <= unsigned(x) * unsigned(x);. If there are no multipliers in the target device, the synthesizer will handle implementing it without them, you don't have to do anything. - Highest performance, but with long latency: With no hardware multiplier, you'll need to pipeline the steps yourself to achieve whatever it is you're looking to achieve. - Fewest logic cells: No particular suggestions here since this is not something I've looked into for multiplying. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:00 2024 X-Received: by 2002:a37:4e8a:: with SMTP id c132mr17622119qkb.13.1549777723928; Sat, 09 Feb 2019 21:48:43 -0800 (PST) X-Received: by 2002:a25:8e0c:: with SMTP id p12mr281671ybl.4.1549777723749; Sat, 09 Feb 2019 21:48:43 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no3862637qta.0!news-out.google.com!f18ni2385qto.0!nntp.google.com!m21no3862635qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Feb 2019 21:48:43 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.234.91.250; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.234.91.250 References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <619633ff-2389-4721-9c4c-af6500800bf2@googlegroups.com> Subject: Re: x^2 From: stchebel@gmail.com Injection-Date: Sun, 10 Feb 2019 05:48:43 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 35 Xref: reader01.eternal-september.org comp.lang.vhdl:9386 W dniu sobota, 9 lutego 2019 04:17:37 UTC+1 u=C5=BCytkownik gnuarm.del...@g= mail.com napisa=C5=82: > On Friday, February 8, 2019 at 2:33:18 PM UTC-5, stch...@gmail.com wrote: > > x : std_logic_vector(12 downto 0); -- unsigned integer > >=20 > > Should be implemented in spartan-6 but without using on chip multiplica= tors. Any ideas for an efficient code? >=20 > Personally, I find multipliers to be a PITA to code. One thing you have = in your favor for calculating a square is that all the results will be posi= tive or zero. So you don't need a bipolar multiplication. Just take the a= bsolute value of your input before the multiply assuming the input is signe= d as opposed to unsigned. =20 >=20 > I see in your comment "unsigned integer" which means you can either conve= rt your input SLV to an unsigned type or to an integer type with a range of= 0 to 4095 before you multiply to form the square. Keep in mind your resul= t will need twice as many bits if you want to retain full resolution. >=20 > I assume this is a class assignment? Does your instructor care if the al= gorithm is small, fast, easy to code or some combination? A simple approac= h for positive number multiplies is shift and add. A more complex, but sma= ller implementation (and maybe faster as well) is a Booth's algorithm or ma= ybe a modified Booth's algorithm.=20 >=20 > Oh yeah, please use numeric_std and not std_logic_arith. If you don't kn= ow why, just ask. That's one point that most people here get.=20 >=20 > Rick C. Thanks a lot Rick for your comprehensive answer. Multiplication should be d= one in one clock cycle @40MHz. I have some ideas but first I will experimen= t with 4-bit input words. Yes, in fact I don't know why do you suggest to u= se numeric_std instead of logis_std. Could you explain, please. Stachu From newsfish@newsfish Thu Aug 1 00:44:01 2024 X-Received: by 2002:ac8:3077:: with SMTP id g52mr2615932qte.4.1549778026830; Sat, 09 Feb 2019 21:53:46 -0800 (PST) X-Received: by 2002:a25:ab82:: with SMTP id v2mr284567ybi.3.1549778026737; Sat, 09 Feb 2019 21:53:46 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no3867652qta.0!news-out.google.com!f18ni2385qto.0!nntp.google.com!m21no3867642qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Feb 2019 21:53:46 -0800 (PST) In-Reply-To: <89cfc212-e51c-4ad1-bf1b-2af33656c8b2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.234.91.250; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.234.91.250 References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> <89cfc212-e51c-4ad1-bf1b-2af33656c8b2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6a38ff86-0808-4a16-9ce1-c0481a2cefb6@googlegroups.com> Subject: Re: x^2 From: stchebel@gmail.com Injection-Date: Sun, 10 Feb 2019 05:53:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 25 Xref: reader01.eternal-september.org comp.lang.vhdl:9387 W dniu sobota, 9 lutego 2019 15:17:49 UTC+1 u=C5=BCytkownik KJ napisa=C5=82= : > On Friday, February 8, 2019 at 2:33:18 PM UTC-5, stch...@gmail.com wrote: > > x : std_logic_vector(12 downto 0); -- unsigned integer > >=20 > > Should be implemented in spartan-6 but without using on chip multiplica= tors. Any ideas for an efficient code? >=20 > What is your definition of 'efficient'? Here are a few: > - Minimal coding effort, most easily supportable: Then XSquared <=3D uns= igned(x) * unsigned(x);. If there are no multipliers in the target device,= the synthesizer will handle implementing it without them, you don't have t= o do anything. > - Highest performance, but with long latency: With no hardware multiplie= r, you'll need to pipeline the steps yourself to achieve whatever it is you= 're looking to achieve. > - Fewest logic cells: No particular suggestions here since this is not s= omething I've looked into for multiplying. >=20 > Kevin Jennings Thanks Kevin for your answer. The solution should be somehow balanced speed= /coding complexity. The goal is to have a multiplier running @40MHz. Multip= lication should be performed in onw clock cycle. Stachu From newsfish@newsfish Thu Aug 1 00:44:01 2024 X-Received: by 2002:aed:36ea:: with SMTP id f97mr17393120qtb.60.1549781066339; Sat, 09 Feb 2019 22:44:26 -0800 (PST) X-Received: by 2002:a81:9984:: with SMTP id q126mr265001ywg.5.1549781066184; Sat, 09 Feb 2019 22:44:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!news.redatomik.org!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!85.12.16.69.MISMATCH!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no3918470qta.0!news-out.google.com!f18ni2385qto.0!nntp.google.com!m21no3918463qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Feb 2019 22:44:25 -0800 (PST) In-Reply-To: <619633ff-2389-4721-9c4c-af6500800bf2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> <619633ff-2389-4721-9c4c-af6500800bf2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54161e1f-8eac-4ebf-af1a-6d668f50fabb@googlegroups.com> Subject: Re: x^2 From: gnuarm.deletethisbit@gmail.com Injection-Date: Sun, 10 Feb 2019 06:44:26 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4566 X-Received-Body-CRC: 3827814091 Xref: reader01.eternal-september.org comp.lang.vhdl:9388 On Sunday, February 10, 2019 at 12:48:45 AM UTC-5, stch...@gmail.com wrote: > W dniu sobota, 9 lutego 2019 04:17:37 UTC+1 u=C5=BCytkownik gnuarm.del...= @gmail.com napisa=C5=82: > > On Friday, February 8, 2019 at 2:33:18 PM UTC-5, stch...@gmail.com wrot= e: > > > x : std_logic_vector(12 downto 0); -- unsigned integer > > >=20 > > > Should be implemented in spartan-6 but without using on chip multipli= cators. Any ideas for an efficient code? > >=20 > > Personally, I find multipliers to be a PITA to code. One thing you hav= e in your favor for calculating a square is that all the results will be po= sitive or zero. So you don't need a bipolar multiplication. Just take the= absolute value of your input before the multiply assuming the input is sig= ned as opposed to unsigned. =20 > >=20 > > I see in your comment "unsigned integer" which means you can either con= vert your input SLV to an unsigned type or to an integer type with a range = of 0 to 4095 before you multiply to form the square. Keep in mind your res= ult will need twice as many bits if you want to retain full resolution. > >=20 > > I assume this is a class assignment? Does your instructor care if the = algorithm is small, fast, easy to code or some combination? A simple appro= ach for positive number multiplies is shift and add. A more complex, but s= maller implementation (and maybe faster as well) is a Booth's algorithm or = maybe a modified Booth's algorithm.=20 > >=20 > > Oh yeah, please use numeric_std and not std_logic_arith. If you don't = know why, just ask. That's one point that most people here get.=20 > >=20 > > Rick C. >=20 > Thanks a lot Rick for your comprehensive answer. Multiplication should be= done in one clock cycle @40MHz. I have some ideas but first I will experim= ent with 4-bit input words. Yes, in fact I don't know why do you suggest to= use numeric_std instead of logis_std. Could you explain, please. std_logic_vector (SLV) is not a numeric oriented type. I'm getting a bit r= usty in my VHDL so there may be libraries that let you perform math on SLV = (like addition) but one of the intents of typing in VHDL is to clearly indi= cate the meaning of the data type you are using. That's why they have the = various data types such as signed and unsigned. numeric_std provides math = operators for signed and unsigned types and that's what I recommend since i= t allows you to clearly indicate what you intend and makes your intent obvi= ous to anyone else reading the code. =20 Do you know which algorithm you want to implement? =20 BTW, you can apply any of the algorithms I mentioned to logic in a single c= lock cycle. Rather than using the same logic elements iteratively in multi= ple clock cycles, you would instantiate the same functionality multiple tim= es in succession. This can be done as sequential code in a function or pro= cess or you can use a generate statement to iteratively define your logic. = =20 Wow! It has been a while since I actually wrote any VHDL and I'm really rus= ty on this. I'm having trouble picturing the code.=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:01 2024 X-Received: by 2002:a0c:9211:: with SMTP id a17mr2766185qva.19.1549834936778; Sun, 10 Feb 2019 13:42:16 -0800 (PST) X-Received: by 2002:a25:8042:: with SMTP id a2mr281379ybn.2.1549834936363; Sun, 10 Feb 2019 13:42:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no5053611qta.0!news-out.google.com!f18ni2991qto.0!nntp.google.com!m21no5053605qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 Feb 2019 13:42:15 -0800 (PST) In-Reply-To: <36B0468F.2016173@mentorg.com>#1/1> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=131.247.244.52; posting-account=tOlxywoAAAD4atO_lRFYSda4ABNA2pFC NNTP-Posting-Host: 131.247.244.52 References: <36B0468F.2016173@mentorg.com>#1/1> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> Subject: Re: printf() function like C in VHDL ? From: Rubel Ahmed Injection-Date: Sun, 10 Feb 2019 21:42:16 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 7 Xref: reader01.eternal-september.org comp.lang.vhdl:9389 On Thursday, January 28, 1999 at 3:00:00 AM UTC-5, Jerome Chaix wrote: > Is there an existing function in VHDL which is the equivalent of > printf(%d, var) in language C ? I do the following and it works for me. though I am a noob. assert false report "show me what you got: "&integer'image(myVar) severity NOTE; From newsfish@newsfish Thu Aug 1 00:44:02 2024 X-Received: by 2002:a37:4f0e:: with SMTP id d14mr18542476qkb.45.1549839937896; Sun, 10 Feb 2019 15:05:37 -0800 (PST) X-Received: by 2002:a25:a203:: with SMTP id b3mr307443ybi.6.1549839937751; Sun, 10 Feb 2019 15:05:37 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no5168986qta.0!news-out.google.com!q39ni4741qtk.1!nntp.google.com!m21no5168985qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 Feb 2019 15:05:37 -0800 (PST) In-Reply-To: <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <36B0468F.2016173@mentorg.com>#1/1> <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3170c49e-9a63-4b8a-8bd6-e1e96fe9d621@googlegroups.com> Subject: Re: printf() function like C in VHDL ? From: KJ Injection-Date: Sun, 10 Feb 2019 23:05:37 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9390 On Sunday, February 10, 2019 at 4:42:18 PM UTC-5, Rubel Ahmed wrote: > On Thursday, January 28, 1999 at 3:00:00 AM UTC-5, Jerome Chaix wrote: > I do the following and it works for me. though I am a noob. >=20 > assert false > report "show me what you got: "&integer'image(myVar) severity NOTE; You can also simply use the 'report' without having to 'assert'. When the = report clause is used as part of an assert statement, the default severity = is ERROR, but when you just use the report statement by itself, the default= severity is 'NOTE'[1]. So an even simpler equivalent to 'printf' would be report "show me what you got: "&integer'image(myVar); Kevin Jennings [1] Refer to sections 10.3 (Assertion statement) and 10.4 (Report statement= ). From newsfish@newsfish Thu Aug 1 00:44:02 2024 X-Received: by 2002:a37:5b83:: with SMTP id p125mr19499427qkb.57.1549840100942; Sun, 10 Feb 2019 15:08:20 -0800 (PST) X-Received: by 2002:a25:1144:: with SMTP id 65mr313702ybr.0.1549840100833; Sun, 10 Feb 2019 15:08:20 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no5172889qta.0!news-out.google.com!q39ni4741qtk.1!nntp.google.com!m21no5172878qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 Feb 2019 15:08:20 -0800 (PST) In-Reply-To: <6a38ff86-0808-4a16-9ce1-c0481a2cefb6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> <89cfc212-e51c-4ad1-bf1b-2af33656c8b2@googlegroups.com> <6a38ff86-0808-4a16-9ce1-c0481a2cefb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: x^2 From: KJ Injection-Date: Sun, 10 Feb 2019 23:08:20 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9391 On Sunday, February 10, 2019 at 12:53:48 AM UTC-5, stch...@gmail.com wrote: > W dniu sobota, 9 lutego 2019 15:17:49 UTC+1 u=C5=BCytkownik KJ napisa=C5= =82: > > On Friday, February 8, 2019 at 2:33:18 PM UTC-5, stch...@gmail.com wrot= e: > > > x : std_logic_vector(12 downto 0); -- unsigned integer > > >=20 > > > Should be implemented in spartan-6 but without using on chip multipli= cators. Any ideas for an efficient code? > >=20 > > What is your definition of 'efficient'? Here are a few: > > - Minimal coding effort, most easily supportable: Then XSquared <=3D u= nsigned(x) * unsigned(x);. If there are no multipliers in the target devic= e, the synthesizer will handle implementing it without them, you don't have= to do anything. > > - Highest performance, but with long latency: With no hardware multipl= ier, you'll need to pipeline the steps yourself to achieve whatever it is y= ou're looking to achieve. > > - Fewest logic cells: No particular suggestions here since this is not= something I've looked into for multiplying. > >=20 > > Kevin Jennings >=20 > Thanks Kevin for your answer. The solution should be somehow balanced spe= ed/coding complexity. The goal is to have a multiplier running @40MHz. Mult= iplication should be performed in onw clock cycle. >=20 > Stachu Then start by synthesizing "XSquared <=3D unsigned(x) * unsigned(x);" and r= un it through your tools. If Fmax > 40 MHz, you don't need to invest any m= ore time or effort in trying to find a 'better' implementation. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:02 2024 X-Received: by 2002:a0c:b650:: with SMTP id q16mr19939360qvf.22.1549866966536; Sun, 10 Feb 2019 22:36:06 -0800 (PST) X-Received: by 2002:a81:528b:: with SMTP id g133mr310450ywb.1.1549866966416; Sun, 10 Feb 2019 22:36:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!news.redatomik.org!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no5689081qta.0!news-out.google.com!q39ni5122qtk.1!nntp.google.com!m21no5689078qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 Feb 2019 22:36:06 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:147:4002:f4bf:34e7:26b:e7cd:2445; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:34e7:26b:e7cd:2445 References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> <89cfc212-e51c-4ad1-bf1b-2af33656c8b2@googlegroups.com> <6a38ff86-0808-4a16-9ce1-c0481a2cefb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: x^2 From: gnuarm.deletethisbit@gmail.com Injection-Date: Mon, 11 Feb 2019 06:36:06 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3334 X-Received-Body-CRC: 2042692949 Xref: reader01.eternal-september.org comp.lang.vhdl:9392 On Sunday, February 10, 2019 at 6:08:22 PM UTC-5, KJ wrote: > On Sunday, February 10, 2019 at 12:53:48 AM UTC-5, stch...@gmail.com wrot= e: > > W dniu sobota, 9 lutego 2019 15:17:49 UTC+1 u=C5=BCytkownik KJ napisa= =C5=82: > > > On Friday, February 8, 2019 at 2:33:18 PM UTC-5, stch...@gmail.com wr= ote: > > > > x : std_logic_vector(12 downto 0); -- unsigned integer > > > >=20 > > > > Should be implemented in spartan-6 but without using on chip multip= licators. Any ideas for an efficient code? > > >=20 > > > What is your definition of 'efficient'? Here are a few: > > > - Minimal coding effort, most easily supportable: Then XSquared <=3D= unsigned(x) * unsigned(x);. If there are no multipliers in the target dev= ice, the synthesizer will handle implementing it without them, you don't ha= ve to do anything. > > > - Highest performance, but with long latency: With no hardware multi= plier, you'll need to pipeline the steps yourself to achieve whatever it is= you're looking to achieve. > > > - Fewest logic cells: No particular suggestions here since this is n= ot something I've looked into for multiplying. > > >=20 > > > Kevin Jennings > >=20 > > Thanks Kevin for your answer. The solution should be somehow balanced s= peed/coding complexity. The goal is to have a multiplier running @40MHz. Mu= ltiplication should be performed in onw clock cycle. > >=20 > > Stachu >=20 > Then start by synthesizing "XSquared <=3D unsigned(x) * unsigned(x);" and= run it through your tools. If Fmax > 40 MHz, you don't need to invest any= more time or effort in trying to find a 'better' implementation. >=20 > Kevin Jennings That will likely use the built in multipliers and he doesn't want that. Mo= st likely the teacher said to not use the multipliers.=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: x^2 Date: Mon, 11 Feb 2019 10:04:34 -0800 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 11 Feb 2019 18:04:36 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="e0ed877c91c30d565c05718d92133e1b"; logging-data="19731"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/bQdfA48DfIzqltTybwxR4" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 Cancel-Lock: sha1:eQnqISKbmhStLjlFiuLk6k0anOY= In-Reply-To: <11fbbb0a-91a7-453f-b120-c22707e0f3af@googlegroups.com> Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9393 On 2/8/19 11:33 AM, stchebel@gmail.com wrote: > x : std_logic_vector(12 downto 0); -- unsigned integer > > Should be implemented in spartan-6 but without using on chip multiplicators. Any ideas for an efficient code? > And, per your other instructions, have it execute in one cycle? Sure, block RAM. With only one input you'd have an 8k address space, and the result of the square is 24b wide. In Spartan-6, configured as a single-port ROM, you'll get 8k*2b per BRAM, so you'd need 12 BRAMs. Bit of an expensive solution, but not unheard of. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:44:03 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp1-1.free.fr!not-for-mail Subject: Re: printf() function like C in VHDL ? Newsgroups: comp.lang.vhdl References: <36B0468F.2016173@mentorg.com> <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> From: Nicolas Matringe Date: Mon, 11 Feb 2019 22:22:47 +0100 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr-classic Content-Transfer-Encoding: 7bit Lines: 14 Message-ID: <5c61e7a7$0$3533$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 11 Feb 2019 22:22:47 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1549920167 news-4.free.fr 3533 88.185.146.198:26269 X-Complaints-To: abuse@proxad.net Xref: reader01.eternal-september.org comp.lang.vhdl:9394 On 10/02/2019 22:42, Rubel Ahmed wrote: > On Thursday, January 28, 1999 at 3:00:00 AM UTC-5, Jerome Chaix wrote: >> Is there an existing function in VHDL which is the equivalent of >> printf(%d, var) in language C ? > > I do the following and it works for me. though I am a noob. > > assert false > report "show me what you got: "&integer'image(myVar) severity NOTE; Do you realize you just replied to a 20 years old thread ? Nicolas From newsfish@newsfish Thu Aug 1 00:44:03 2024 X-Received: by 2002:a37:94c4:: with SMTP id w187mr237916qkd.15.1549921527012; Mon, 11 Feb 2019 13:45:27 -0800 (PST) X-Received: by 2002:a0d:d8d6:: with SMTP id a205mr2802ywe.6.1549921526753; Mon, 11 Feb 2019 13:45:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no1504080qta.0!news-out.google.com!f18ni341qto.0!nntp.google.com!m21no1504072qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 11 Feb 2019 13:45:26 -0800 (PST) In-Reply-To: <5c61e7a7$0$3533$426a34cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2607:fe50:0:810c:85c9:d187:9cac:647; posting-account=tOlxywoAAAD4atO_lRFYSda4ABNA2pFC NNTP-Posting-Host: 2607:fe50:0:810c:85c9:d187:9cac:647 References: <36B0468F.2016173@mentorg.com> <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> <5c61e7a7$0$3533$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2630ba51-8a42-40c0-8236-5bbfe4457722@googlegroups.com> Subject: Re: printf() function like C in VHDL ? From: Rubel Ahmed Injection-Date: Mon, 11 Feb 2019 21:45:26 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1535 X-Received-Body-CRC: 1507795441 Xref: reader01.eternal-september.org comp.lang.vhdl:9395 No, i did not notice at the first look. But it felt so good to find the age of this post, i spent 10 minutes reading the History of google groups. From newsfish@newsfish Thu Aug 1 00:44:04 2024 X-Received: by 2002:ac8:2bf6:: with SMTP id n51mr245624qtn.47.1549922420052; Mon, 11 Feb 2019 14:00:20 -0800 (PST) X-Received: by 2002:a81:5f89:: with SMTP id t131mr3456ywb.2.1549922419902; Mon, 11 Feb 2019 14:00:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!m21no1538474qta.0!news-out.google.com!f18ni341qto.0!nntp.google.com!m21no1538463qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 11 Feb 2019 14:00:19 -0800 (PST) In-Reply-To: <5c61e7a7$0$3533$426a34cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.100.122.44; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 76.100.122.44 References: <36B0468F.2016173@mentorg.com> <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> <5c61e7a7$0$3533$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: printf() function like C in VHDL ? From: gnuarm.deletethisbit@gmail.com Injection-Date: Mon, 11 Feb 2019 22:00:20 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 17 Xref: reader01.eternal-september.org comp.lang.vhdl:9396 On Monday, February 11, 2019 at 4:22:50 PM UTC-5, Nicolas Matringe wrote: > On 10/02/2019 22:42, Rubel Ahmed wrote: > > On Thursday, January 28, 1999 at 3:00:00 AM UTC-5, Jerome Chaix wrote: > >> Is there an existing function in VHDL which is the equivalent of > >> printf(%d, var) in language C ? > > > > I do the following and it works for me. though I am a noob. > > > > assert false > > report "show me what you got: "&integer'image(myVar) severity NOTE; > > Do you realize you just replied to a 20 years old thread ? > > Nicolas Some things are timeless.... :) Rick C. From newsfish@newsfish Thu Aug 1 00:44:04 2024 X-Received: by 2002:ac8:4918:: with SMTP id e24mr2413838qtq.15.1549985718420; Tue, 12 Feb 2019 07:35:18 -0800 (PST) X-Received: by 2002:a81:9984:: with SMTP id q126mr4689ywg.5.1549985718260; Tue, 12 Feb 2019 07:35:18 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.unit0.net!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no3514222qta.0!news-out.google.com!f18ni1081qto.0!nntp.google.com!m21no3514214qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Feb 2019 07:35:18 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.100.122.44; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 76.100.122.44 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <38652365-a6ae-4bba-98f3-92bdea9ac752@googlegroups.com> Subject: VHDL for the Intermittent Programmer From: gnuarm.deletethisbit@gmail.com Injection-Date: Tue, 12 Feb 2019 15:35:18 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1821 X-Received-Body-CRC: 444841793 Xref: reader01.eternal-september.org comp.lang.vhdl:9397 I used to be a fluent VHDL programmer cranking out code by the pound. I ev= entually became rather fluent by developing my own style and using the same= language features consistently. Since then I have programmed a lot less o= ften and I have largely forgotten my previous habits. =20 So now if I want to program in VHDL I will need to use language references = for syntax and use of the newer features in VHDL 2008 (I know, I know, 2008= was 11 years ago, but it's still relatively new). What references do you = use? "What's in YOUR wallet?"=20 I'd also be interested in hearing what coding styles you use.=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:04 2024 X-Received: by 2002:a37:d654:: with SMTP id t81mr3270966qki.4.1550004806419; Tue, 12 Feb 2019 12:53:26 -0800 (PST) X-Received: by 2002:a25:c801:: with SMTP id y1mr61441ybf.1.1550004806260; Tue, 12 Feb 2019 12:53:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no66545qta.0!news-out.google.com!f18ni27qto.0!nntp.google.com!m21no66536qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Feb 2019 12:53:25 -0800 (PST) In-Reply-To: <38652365-a6ae-4bba-98f3-92bdea9ac752@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=51.6.106.115; posting-account=Rehf9goAAABfyx9PL8hB3Gwzl4ei9NmE NNTP-Posting-Host: 51.6.106.115 References: <38652365-a6ae-4bba-98f3-92bdea9ac752@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5b3f34da-1d6e-4485-962e-18f743b47601@googlegroups.com> Subject: Re: VHDL for the Intermittent Programmer From: dgreig@ieee.org Injection-Date: Tue, 12 Feb 2019 20:53:26 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9398 On Tuesday, February 12, 2019 at 3:35:20 PM UTC, gnuarm.del...@gmail.com wr= ote: > I used to be a fluent VHDL programmer cranking out code by the pound. I = eventually became rather fluent by developing my own style and using the sa= me language features consistently. Since then I have programmed a lot less= often and I have largely forgotten my previous habits. =20 >=20 > So now if I want to program in VHDL I will need to use language reference= s for syntax and use of the newer features in VHDL 2008 (I know, I know, 20= 08 was 11 years ago, but it's still relatively new). What references do yo= u use? "What's in YOUR wallet?"=20 >=20 > I'd also be interested in hearing what coding styles you use.=20 >=20 > Rick C. Sigasi editor https://www.sigasi.com/ might help getting back on the rack. The books by Peter J. Ashenden are to a VHDL enthusiast like a Dictionary a= nd Thesaurus are to a Crossword addict. I am an Asperger so ain't intereste= d in anything seemingly fruitless, so logic is interesting. 2008, it's going the way that C (in my opinion C is a leaky bucket full of = catchas and gotchas) transmorphed into C++ (object oriented same old bucket= with more kludge's). Good bits but with potholes. From newsfish@newsfish Thu Aug 1 00:44:05 2024 X-Received: by 2002:ac8:3826:: with SMTP id q35mr3422995qtb.31.1550007189049; Tue, 12 Feb 2019 13:33:09 -0800 (PST) X-Received: by 2002:a25:ab82:: with SMTP id v2mr59993ybi.3.1550007188922; Tue, 12 Feb 2019 13:33:08 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no131984qta.0!news-out.google.com!f18ni76qto.0!nntp.google.com!m21no131978qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Feb 2019 13:33:08 -0800 (PST) In-Reply-To: <5b3f34da-1d6e-4485-962e-18f743b47601@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:147:4002:f4bf:8c31:8af9:1dd6:c906; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:8c31:8af9:1dd6:c906 References: <38652365-a6ae-4bba-98f3-92bdea9ac752@googlegroups.com> <5b3f34da-1d6e-4485-962e-18f743b47601@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL for the Intermittent Programmer From: gnuarm.deletethisbit@gmail.com Injection-Date: Tue, 12 Feb 2019 21:33:09 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9399 On Tuesday, February 12, 2019 at 3:53:28 PM UTC-5, dgr...@ieee.org wrote: > On Tuesday, February 12, 2019 at 3:35:20 PM UTC, gnuarm.del...@gmail.com = wrote: > > I used to be a fluent VHDL programmer cranking out code by the pound. = I eventually became rather fluent by developing my own style and using the = same language features consistently. Since then I have programmed a lot le= ss often and I have largely forgotten my previous habits. =20 > >=20 > > So now if I want to program in VHDL I will need to use language referen= ces for syntax and use of the newer features in VHDL 2008 (I know, I know, = 2008 was 11 years ago, but it's still relatively new). What references do = you use? "What's in YOUR wallet?"=20 > >=20 > > I'd also be interested in hearing what coding styles you use.=20 > >=20 > > Rick C. >=20 > Sigasi editor https://www.sigasi.com/ might help getting back on the rack= . >=20 > The books by Peter J. Ashenden are to a VHDL enthusiast like a Dictionary= and Thesaurus are to a Crossword addict. I am an Asperger so ain't interes= ted in anything seemingly fruitless, so logic is interesting. >=20 > 2008, it's going the way that C (in my opinion C is a leaky bucket full o= f catchas and gotchas) transmorphed into C++ (object oriented same old buck= et with more kludge's). > Good bits but with potholes. So what is VHDL 2008 transforming into?=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: VHDL for the Intermittent Programmer Date: Tue, 12 Feb 2019 19:56:20 -0600 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <38652365-a6ae-4bba-98f3-92bdea9ac752@googlegroups.com> <5b3f34da-1d6e-4485-962e-18f743b47601@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 13 Feb 2019 01:56:21 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="3ad02be11421a0b2245ebb6e861606a1"; logging-data="3844"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18EmHSwQf9anCm6wE/McCsui17EWfWmMOA=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:PjYV8CpLTf5mSJ3EESS8qm5lP2E= In-Reply-To: <5b3f34da-1d6e-4485-962e-18f743b47601@googlegroups.com> Xref: reader01.eternal-september.org comp.lang.vhdl:9400 On 2019-02-12 14:53, dgreig@ieee.org wrote: > On Tuesday, February 12, 2019 at 3:35:20 PM UTC, gnuarm.del...@gmail.com wrote: >> I used to be a fluent VHDL programmer cranking out code by the pound. I eventually became rather fluent by developing my own style and using the same language features consistently. Since then I have programmed a lot less often and I have largely forgotten my previous habits. >> >> So now if I want to program in VHDL I will need to use language references for syntax and use of the newer features in VHDL 2008 (I know, I know, 2008 was 11 years ago, but it's still relatively new). What references do you use? "What's in YOUR wallet?" >> >> I'd also be interested in hearing what coding styles you use. >> >> Rick C. > > Sigasi editor https://www.sigasi.com/ might help getting back on the rack. > > The books by Peter J. Ashenden are to a VHDL enthusiast like a Dictionary and Thesaurus are to a Crossword addict. I am an Asperger so ain't interested in anything seemingly fruitless, so logic is interesting. > > 2008, it's going the way that C (in my opinion C is a leaky bucket full of catchas and gotchas) transmorphed into C++ (object oriented same old bucket with more kludge's). > Good bits but with potholes. > I've been retired for about 2 years now, but when I was furiously coding VHDL, my VHDL book by Peter J. Ashenden got plenty of use. It probably contains the most thorough coverage of VHDL you can find outside of the official language reference itself. VHDL 2008 introduced lots of good, welcome enhancements to the language but they don't do you much good if the tools don't support the enhancements. In 2017, tools support for VHDL 2008 was partial, miniscule, or non-existent, depending on the tool and tool vendor. In some cases, if they said they supported VHDL 2008, it was only a tiny handful of the 2008 enhancements. Charles Bailey From newsfish@newsfish Thu Aug 1 00:44:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (gtwrek) Newsgroups: comp.lang.vhdl Subject: Re: VHDL for the Intermittent Programmer Date: Wed, 13 Feb 2019 18:58:14 -0000 (UTC) Organization: Sonic Lines: 23 Message-ID: References: <38652365-a6ae-4bba-98f3-92bdea9ac752@googlegroups.com> <5b3f34da-1d6e-4485-962e-18f743b47601@googlegroups.com> Injection-Date: Wed, 13 Feb 2019 18:58:14 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="cbe6745a3cbb2a67faf70d1d633678e0"; logging-data="28116"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wtQsJSMs4oATN6+djaove" Cancel-Lock: sha1:9wyN+u5oHABCLpoXgVX8Ek85tmo= Originator: gtwrek@sonic.net (gtwrek) X-Newsreader: trn 4.0-test77 (Sep 1, 2010) Xref: reader01.eternal-september.org comp.lang.vhdl:9401 In article , Charles Bailey wrote: > >VHDL 2008 introduced lots of good, welcome enhancements to the language >but they don't do you much good if the tools don't support the >enhancements. In 2017, tools support for VHDL 2008 was partial, >miniscule, or non-existent, depending on the tool and tool vendor. In >some cases, if they said they supported VHDL 2008, it was only a tiny >handful of the 2008 enhancements. If it's any help - the Synthesizable subset of SystemVerilog was pretty much solid spec-wise in 2005 (I was building SystemVerilog designs targetting Xilinx with Mentor Precision back then.) However, the support from Xilinx really didn't come until 2016 - 11 years after the standard. So, if VHDL-2008 follow the same timeline, perhaps this year is your year! Regards, Mark From newsfish@newsfish Thu Aug 1 00:44:06 2024 X-Received: by 2002:ac8:4918:: with SMTP id e24mr1322752qtq.15.1550085325711; Wed, 13 Feb 2019 11:15:25 -0800 (PST) X-Received: by 2002:a81:5f89:: with SMTP id t131mr77796ywb.2.1550085325525; Wed, 13 Feb 2019 11:15:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.unit0.net!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no2124364qta.0!news-out.google.com!f18ni956qto.0!nntp.google.com!m21no2124362qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 13 Feb 2019 11:15:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <38652365-a6ae-4bba-98f3-92bdea9ac752@googlegroups.com> <5b3f34da-1d6e-4485-962e-18f743b47601@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL for the Intermittent Programmer From: gnuarm.deletethisbit@gmail.com Injection-Date: Wed, 13 Feb 2019 19:15:25 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1541 X-Received-Body-CRC: 1238952073 Xref: reader01.eternal-september.org comp.lang.vhdl:9402 On Wednesday, February 13, 2019 at 1:58:17 PM UTC-5, gtwrek wrote: > > So, if VHDL-2008 follow the same timeline, perhaps this year is your year! Lol! Rick C. From newsfish@newsfish Thu Aug 1 00:44:06 2024 X-Received: by 2002:a0c:881d:: with SMTP id 29mr4820745qvl.13.1550770980988; Thu, 21 Feb 2019 09:43:00 -0800 (PST) X-Received: by 2002:a81:8483:: with SMTP id u125mr419184ywf.7.1550770980667; Thu, 21 Feb 2019 09:43:00 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no4161887qta.0!news-out.google.com!y15ni3659qta.0!nntp.google.com!m21no4161878qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 21 Feb 2019 09:43:00 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.122; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.122 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> Subject: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Thu, 21 Feb 2019 17:43:00 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9403 Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I will feed it with images from this camera: OV7670 and train it in order to determine if the person in the camera is man or woman. Is there any VHDL core capable of implementing this processing? Ideally I would try to achieve real-time (delay = 1-2 sec) to decide if the picture shows man or woman. The camera I have bought is the OV7670, which takes 640x480 pictures. Can it work or I need a megapixel camera? I have, also, found a High Definition 14 MegaPixel USB camera from ebay, and I want to interface it with Virtex 5. Is something feasible? Where to start from? In the same FPGA I have to put, also, the core of the neural network and the core of the serial interface, which will output man or woman. I am thinking of CNN. Thank you... From newsfish@newsfish Thu Aug 1 00:44:06 2024 X-Received: by 2002:a0c:932a:: with SMTP id d39mr3859503qvd.35.1550876706649; Fri, 22 Feb 2019 15:05:06 -0800 (PST) X-Received: by 2002:a0d:d8d6:: with SMTP id a205mr46008ywe.6.1550876706482; Fri, 22 Feb 2019 15:05:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no2453696qta.0!news-out.google.com!y15ni1584qta.0!nntp.google.com!m21no2453685qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 Feb 2019 15:05:06 -0800 (PST) In-Reply-To: <24d645a6-73ac-458a-a004-4a6e5f668c9b@d19g2000prh.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.35.82.93; posting-account=MCuIyAoAAABhyXJvMbOBS9PDz4_d4m08 NNTP-Posting-Host: 50.35.82.93 References: <24d645a6-73ac-458a-a004-4a6e5f668c9b@d19g2000prh.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5e067040-f5fc-452c-a51c-58dd1344601d@googlegroups.com> Subject: Re: numeric_std resize function From: Rob Anderson Injection-Date: Fri, 22 Feb 2019 23:05:06 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9404 On Monday, April 27, 2009 at 12:43:25 AM UTC-7, Peter wrote: > I was surprised by how the resize function works. My intention was to > substract two 32-bit signals (std_logic_vectors, but representing 2- > complement numbers) and decrease the signal width from 32 bits to 14. > The code below does not work: > > daout <= std_logic_vector( resize((signed(tx_mix_i) - signed > (tx_mix_q)),14) ); > > But this code does: > > idaout <= std_logic_vector( signed(tx_mix_i) - signed(tx_mix_q) ); > daout <= idaout(31 downto 18); > > I seems as the rezise function selects the 14 lowest bits in the > argument instead of the 14 highest. > > Any comments? > > /Peter The resize function is to change the number of bits without changing the value. If you want to select a field you can use a variable and select the (31 downto 18) bits. From newsfish@newsfish Thu Aug 1 00:44:07 2024 X-Received: by 2002:aed:39c7:: with SMTP id m65mr5455602qte.2.1550928378962; Sat, 23 Feb 2019 05:26:18 -0800 (PST) X-Received: by 2002:a0d:d5cb:: with SMTP id x194mr81082ywd.2.1550928378802; Sat, 23 Feb 2019 05:26:18 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no3460698qta.0!news-out.google.com!y15ni2179qta.0!nntp.google.com!m21no3460691qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Feb 2019 05:26:18 -0800 (PST) In-Reply-To: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sat, 23 Feb 2019 13:26:18 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 14 Xref: reader01.eternal-september.org comp.lang.vhdl:9405 On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobbyist wrote: > Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I > will feed it with images from this camera: OV7670 and train it in order > to determine if the person in the camera is man or woman. Is there any > VHDL core capable of implementing this processing? Ideally I would try > to achieve real-time (delay = 1-2 sec) to decide if the picture shows > man or woman. The camera I have bought is the OV7670, which takes > 640x480 pictures. Can it work or I need a megapixel camera? I have, > also, found a High Definition 14 MegaPixel USB camera from ebay, and I > want to interface it with Virtex 5. Is something feasible? Where to > start from? In the same FPGA I have to put, also, the core of the > neural network and the core of the serial interface, which will output > man or woman. I am thinking of CNN. > Thank you... From newsfish@newsfish Thu Aug 1 00:44:07 2024 X-Received: by 2002:a0c:950d:: with SMTP id l13mr6254478qvl.20.1550950512994; Sat, 23 Feb 2019 11:35:12 -0800 (PST) X-Received: by 2002:a81:6d8b:: with SMTP id i133mr91422ywc.1.1550950512823; Sat, 23 Feb 2019 11:35:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no3951852qta.0!news-out.google.com!o7ni1654qta.1!nntp.google.com!m21no3951844qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Feb 2019 11:35:12 -0800 (PST) In-Reply-To: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6800fdbc-fb6f-4dfe-849b-ef03e5d9943b@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sat, 23 Feb 2019 19:35:12 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9406 On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobbyist wrote: > Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I > will feed it with images from this camera: OV7670 and train it in order > to determine if the person in the camera is man or woman. Is there any > VHDL core capable of implementing this processing? Ideally I would try > to achieve real-time (delay = 1-2 sec) to decide if the picture shows > man or woman. The camera I have bought is the OV7670, which takes > 640x480 pictures. Can it work or I need a megapixel camera? I have, > also, found a High Definition 14 MegaPixel USB camera from ebay, and I > want to interface it with Virtex 5. Is something feasible? Where to > start from? In the same FPGA I have to put, also, the core of the > neural network and the core of the serial interface, which will output > man or woman. I am thinking of CNN. > Thank you... From newsfish@newsfish Thu Aug 1 00:44:07 2024 X-Received: by 2002:ac8:7516:: with SMTP id u22mr6411110qtq.36.1550950546483; Sat, 23 Feb 2019 11:35:46 -0800 (PST) X-Received: by 2002:a25:9d8b:: with SMTP id v11mr51832ybp.3.1550950546400; Sat, 23 Feb 2019 11:35:46 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder7.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no3952754qta.0!news-out.google.com!o7ni1654qta.1!nntp.google.com!m21no3952748qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Feb 2019 11:35:46 -0800 (PST) In-Reply-To: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sat, 23 Feb 2019 19:35:46 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9407 On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobbyist wrote: > Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I > will feed it with images from this camera: OV7670 and train it in order > to determine if the person in the camera is man or woman. Is there any > VHDL core capable of implementing this processing? Ideally I would try > to achieve real-time (delay = 1-2 sec) to decide if the picture shows > man or woman. The camera I have bought is the OV7670, which takes > 640x480 pictures. Can it work or I need a megapixel camera? I have, > also, found a High Definition 14 MegaPixel USB camera from ebay, and I > want to interface it with Virtex 5. Is something feasible? Where to > start from? In the same FPGA I have to put, also, the core of the > neural network and the core of the serial interface, which will output > man or woman. I am thinking of CNN. > Thank you... Anyone to help??? From newsfish@newsfish Thu Aug 1 00:44:08 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.albasani.net!news2.arglkargh.de!news.karotte.org!news.space.net!news.m-online.net!news.bgeserver.de!bgepartei.de!news2.open-news-network.org!.POSTED.75.200.198.146.dyn.plus.net!not-for-mail From: Mike Perkins Newsgroups: comp.lang.vhdl Subject: Re: Neural Network on Xilinx Virtex 5 Date: Sat, 23 Feb 2019 19:53:43 +0000 Organization: bgeserver Message-ID: References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 23 Feb 2019 19:53:47 +0000 (UTC) Injection-Info: news2.open-news-network.org; posting-host="75.200.198.146.dyn.plus.net:146.198.200.75"; logging-data="8069"; mail-complaints-to="abuse@bgeserver.de" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 In-Reply-To: <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> Content-Language: en-GB Xref: reader01.eternal-september.org comp.lang.vhdl:9408 On 23/02/2019 19:35, Electronics_hobbyist wrote: > On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobbyist wrote: >> Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I >> will feed it with images from this camera: OV7670 and train it in order >> to determine if the person in the camera is man or woman. Is there any >> VHDL core capable of implementing this processing? Ideally I would try >> to achieve real-time (delay = 1-2 sec) to decide if the picture shows >> man or woman. The camera I have bought is the OV7670, which takes >> 640x480 pictures. Can it work or I need a megapixel camera? I have, >> also, found a High Definition 14 MegaPixel USB camera from ebay, and I >> want to interface it with Virtex 5. Is something feasible? Where to >> start from? In the same FPGA I have to put, also, the core of the >> neural network and the core of the serial interface, which will output >> man or woman. I am thinking of CNN. >> Thank you... > > Anyone to help??? I doubt anyone here can. It's all a very tall order and far easier to determine the user's map reading skills to determine sex. -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk From newsfish@newsfish Thu Aug 1 00:44:08 2024 X-Received: by 2002:a37:9b84:: with SMTP id d126mr6433691qke.32.1550953773118; Sat, 23 Feb 2019 12:29:33 -0800 (PST) X-Received: by 2002:a25:3085:: with SMTP id w127mr104446ybw.6.1550953773000; Sat, 23 Feb 2019 12:29:33 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no4029694qta.0!news-out.google.com!y15ni2497qta.0!nntp.google.com!m21no4029683qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Feb 2019 12:29:32 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sat, 23 Feb 2019 20:29:33 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9409 On Saturday, February 23, 2019 at 9:53:49 PM UTC+2, Mike Perkins wrote: > On 23/02/2019 19:35, Electronics_hobbyist wrote: > > On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobbyist wrote: > >> Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I > >> will feed it with images from this camera: OV7670 and train it in order > >> to determine if the person in the camera is man or woman. Is there any > >> VHDL core capable of implementing this processing? Ideally I would try > >> to achieve real-time (delay = 1-2 sec) to decide if the picture shows > >> man or woman. The camera I have bought is the OV7670, which takes > >> 640x480 pictures. Can it work or I need a megapixel camera? I have, > >> also, found a High Definition 14 MegaPixel USB camera from ebay, and I > >> want to interface it with Virtex 5. Is something feasible? Where to > >> start from? In the same FPGA I have to put, also, the core of the > >> neural network and the core of the serial interface, which will output > >> man or woman. I am thinking of CNN. > >> Thank you... > > > > Anyone to help??? > > I doubt anyone here can. > > It's all a very tall order and far easier to determine the user's map > reading skills to determine sex. > > > -- > Mike Perkins > Video Solutions Ltd > www.videosolutions.ltd.uk Sorry, I didn't understand. From newsfish@newsfish Thu Aug 1 00:44:08 2024 X-Received: by 2002:ac8:1aea:: with SMTP id h39mr6195524qtk.7.1550953792353; Sat, 23 Feb 2019 12:29:52 -0800 (PST) X-Received: by 2002:a25:25cf:: with SMTP id l198mr45909ybl.0.1550953792246; Sat, 23 Feb 2019 12:29:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no4030118qta.0!news-out.google.com!y15ni2497qta.0!nntp.google.com!m21no4030116qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Feb 2019 12:29:51 -0800 (PST) In-Reply-To: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5e00f86a-90c0-49a5-93b4-dc9202709a8f@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sat, 23 Feb 2019 20:29:52 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9410 On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobbyist wrote: > Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I > will feed it with images from this camera: OV7670 and train it in order > to determine if the person in the camera is man or woman. Is there any > VHDL core capable of implementing this processing? Ideally I would try > to achieve real-time (delay = 1-2 sec) to decide if the picture shows > man or woman. The camera I have bought is the OV7670, which takes > 640x480 pictures. Can it work or I need a megapixel camera? I have, > also, found a High Definition 14 MegaPixel USB camera from ebay, and I > want to interface it with Virtex 5. Is something feasible? Where to > start from? In the same FPGA I have to put, also, the core of the > neural network and the core of the serial interface, which will output > man or woman. I am thinking of CNN. > Thank you... From newsfish@newsfish Thu Aug 1 00:44:09 2024 X-Received: by 2002:a0c:d80d:: with SMTP id h13mr6350251qvj.37.1550953852698; Sat, 23 Feb 2019 12:30:52 -0800 (PST) X-Received: by 2002:a25:bac4:: with SMTP id a4mr106105ybk.1.1550953852560; Sat, 23 Feb 2019 12:30:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.albasani.net!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no4031605qta.0!news-out.google.com!y15ni2497qta.0!nntp.google.com!m21no4031597qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Feb 2019 12:30:52 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <69f625d1-4396-4c1b-a22c-2bd7028af29f@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sat, 23 Feb 2019 20:30:52 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 2768 X-Received-Body-CRC: 4008014466 Xref: reader01.eternal-september.org comp.lang.vhdl:9411 On Saturday, February 23, 2019 at 9:53:49 PM UTC+2, Mike Perkins wrote: > On 23/02/2019 19:35, Electronics_hobbyist wrote: > > On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobbyist wrote: > >> Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I > >> will feed it with images from this camera: OV7670 and train it in order > >> to determine if the person in the camera is man or woman. Is there any > >> VHDL core capable of implementing this processing? Ideally I would try > >> to achieve real-time (delay = 1-2 sec) to decide if the picture shows > >> man or woman. The camera I have bought is the OV7670, which takes > >> 640x480 pictures. Can it work or I need a megapixel camera? I have, > >> also, found a High Definition 14 MegaPixel USB camera from ebay, and I > >> want to interface it with Virtex 5. Is something feasible? Where to > >> start from? In the same FPGA I have to put, also, the core of the > >> neural network and the core of the serial interface, which will output > >> man or woman. I am thinking of CNN. > >> Thank you... > > > > Anyone to help??? > > I doubt anyone here can. > > It's all a very tall order and far easier to determine the user's map > reading skills to determine sex. > > > -- > Mike Perkins > Video Solutions Ltd > www.videosolutions.ltd.uk Sorry, I didn't understand. From newsfish@newsfish Thu Aug 1 00:44:09 2024 X-Received: by 2002:a37:9a4c:: with SMTP id c73mr7230825qke.50.1550985474368; Sat, 23 Feb 2019 21:17:54 -0800 (PST) X-Received: by 2002:a81:e8b:: with SMTP id 133mr104216ywo.0.1550985474262; Sat, 23 Feb 2019 21:17:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no4648361qta.0!news-out.google.com!o7ni2027qta.1!nntp.google.com!m21no4648354qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Feb 2019 21:17:53 -0800 (PST) In-Reply-To: <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=172.76.165.244; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 172.76.165.244 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: gnuarm.deletethisbit@gmail.com Injection-Date: Sun, 24 Feb 2019 05:17:54 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 58 Xref: reader01.eternal-september.org comp.lang.vhdl:9412 On Saturday, February 23, 2019 at 3:29:34 PM UTC-5, Electronics_hobbyist wr= ote: > On Saturday, February 23, 2019 at 9:53:49 PM UTC+2, Mike Perkins wrote: > > On 23/02/2019 19:35, Electronics_hobbyist wrote: > > > On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobby= ist wrote: > > >> Hello, I am trying to build a Neural Network on Xilinx Virtex 5, th= at I > > >> will feed it with images from this camera: OV7670 and train it in or= der > > >> to determine if the person in the camera is man or woman. Is there a= ny > > >> VHDL core capable of implementing this processing? Ideally I would t= ry > > >> to achieve real-time (delay =3D 1-2 sec) to decide if the picture sh= ows > > >> man or woman. The camera I have bought is the OV7670, which takes > > >> 640x480 pictures. Can it work or I need a megapixel camera? I have, > > >> also, found a High Definition 14 MegaPixel USB camera from ebay, and= I > > >> want to interface it with Virtex 5. Is something feasible? Where to > > >> start from? In the same FPGA I have to put, also, the core of the > > >> neural network and the core of the serial interface, which will outp= ut > > >> man or woman. I am thinking of CNN. > > >> Thank you... > > >=20 > > > Anyone to help??? > >=20 > > I doubt anyone here can. > >=20 > > It's all a very tall order and far easier to determine the user's map= =20 > > reading skills to determine sex. > >=20 > >=20 > > --=20 > > Mike Perkins > > Video Solutions Ltd > > www.videosolutions.ltd.uk >=20 > Sorry, I didn't understand. The task you are describing is a complicated problem. It would normally do= ne by first selecting a potential algorithm and writing it as a program to = run on a PC from previously captured images. This would provide a useful d= ebug environment and allow the algorithm to be evaluated and modified as ne= eded to make it work. Then once an algorithm is working it can be coded on= an FPGA. =20 The fact that you are asking for a "VHDL core" to do this shows you are not= really prepared to even start on this job yet.=20 I assume this is a class assignment. Have you been given any information o= n the sort of tools and techniques you might used to achieve your goals? I= would first review that to see if there are any likely algorithms you coul= d use.=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:09 2024 X-Received: by 2002:ac8:1b68:: with SMTP id p37mr7894570qtk.50.1551004992252; Sun, 24 Feb 2019 02:43:12 -0800 (PST) X-Received: by 2002:a25:25cf:: with SMTP id l198mr66645ybl.0.1551004992074; Sun, 24 Feb 2019 02:43:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no4997345qta.0!news-out.google.com!o7ni2235qta.1!nntp.google.com!m21no4997335qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Feb 2019 02:43:11 -0800 (PST) In-Reply-To: <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sun, 24 Feb 2019 10:43:12 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9413 On Sunday, February 24, 2019 at 7:17:56 AM UTC+2, gnuarm.del...@gmail.com w= rote: > On Saturday, February 23, 2019 at 3:29:34 PM UTC-5, Electronics_hobbyist = wrote: > > On Saturday, February 23, 2019 at 9:53:49 PM UTC+2, Mike Perkins wrote: > > > On 23/02/2019 19:35, Electronics_hobbyist wrote: > > > > On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hob= byist wrote: > > > >> Hello, I am trying to build a Neural Network on Xilinx Virtex 5, = that I > > > >> will feed it with images from this camera: OV7670 and train it in = order > > > >> to determine if the person in the camera is man or woman. Is there= any > > > >> VHDL core capable of implementing this processing? Ideally I would= try > > > >> to achieve real-time (delay =3D 1-2 sec) to decide if the picture = shows > > > >> man or woman. The camera I have bought is the OV7670, which takes > > > >> 640x480 pictures. Can it work or I need a megapixel camera? I have= , > > > >> also, found a High Definition 14 MegaPixel USB camera from ebay, a= nd I > > > >> want to interface it with Virtex 5. Is something feasible? Where t= o > > > >> start from? In the same FPGA I have to put, also, the core of the > > > >> neural network and the core of the serial interface, which will ou= tput > > > >> man or woman. I am thinking of CNN. > > > >> Thank you... > > > >=20 > > > > Anyone to help??? > > >=20 > > > I doubt anyone here can. > > >=20 > > > It's all a very tall order and far easier to determine the user's map= =20 > > > reading skills to determine sex. > > >=20 > > >=20 > > > --=20 > > > Mike Perkins > > > Video Solutions Ltd > > > www.videosolutions.ltd.uk > >=20 > > Sorry, I didn't understand. >=20 > The task you are describing is a complicated problem. It would normally = done by first selecting a potential algorithm and writing it as a program t= o run on a PC from previously captured images. This would provide a useful= debug environment and allow the algorithm to be evaluated and modified as = needed to make it work. Then once an algorithm is working it can be coded = on an FPGA. =20 >=20 > The fact that you are asking for a "VHDL core" to do this shows you are n= ot really prepared to even start on this job yet.=20 >=20 > I assume this is a class assignment. Have you been given any information= on the sort of tools and techniques you might used to achieve your goals? = I would first review that to see if there are any likely algorithms you co= uld use.=20 >=20 > Rick C. I have the freedom to choose any solution I prefer. I am thinking of Convol= ution Neural Networks as I have read papers about this. But, my main concer= n is that on FPGAs there is a memory bottleneck. On the same FPGA I should = use a core for the camera, the NN core and the serial interface core that w= ill output me the result. Is there any source/link/book that could help me = on how to start? From newsfish@newsfish Thu Aug 1 00:44:10 2024 X-Received: by 2002:aed:22ac:: with SMTP id p41mr7705417qtc.55.1551004999727; Sun, 24 Feb 2019 02:43:19 -0800 (PST) X-Received: by 2002:a0d:d8d6:: with SMTP id a205mr112947ywe.6.1551004999636; Sun, 24 Feb 2019 02:43:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no4997478qta.0!news-out.google.com!o7ni2235qta.1!nntp.google.com!m21no4997471qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Feb 2019 02:43:19 -0800 (PST) In-Reply-To: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sun, 24 Feb 2019 10:43:19 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 13 Xref: reader01.eternal-september.org comp.lang.vhdl:9414 On Thursday, February 21, 2019 at 7:43:02 PM UTC+2, Electronics_hobbyist wrote: > Hello, I am trying to build a Neural Network on Xilinx Virtex 5, that I > will feed it with images from this camera: OV7670 and train it in order > to determine if the person in the camera is man or woman. Is there any > VHDL core capable of implementing this processing? Ideally I would try > to achieve real-time (delay = 1-2 sec) to decide if the picture shows > man or woman. The camera I have bought is the OV7670, which takes > 640x480 pictures. Can it work or I need a megapixel camera? I have, > also, found a High Definition 14 MegaPixel USB camera from ebay, and I > want to interface it with Virtex 5. Is something feasible? Where to > start from? In the same FPGA I have to put, also, the core of the > neural network and the core of the serial interface, which will output > man or woman. I am thinking of CNN. > Thank you... From newsfish@newsfish Thu Aug 1 00:44:10 2024 X-Received: by 2002:a37:58b:: with SMTP id 133mr8237987qkf.31.1551020161502; Sun, 24 Feb 2019 06:56:01 -0800 (PST) X-Received: by 2002:a0d:e848:: with SMTP id r69mr116562ywe.5.1551020161382; Sun, 24 Feb 2019 06:56:01 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no5309954qta.0!news-out.google.com!y15ni3223qta.0!nntp.google.com!m21no5309945qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Feb 2019 06:56:00 -0800 (PST) In-Reply-To: <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=172.76.165.244; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 172.76.165.244 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Neural Network on Xilinx Virtex 5 From: gnuarm.deletethisbit@gmail.com Injection-Date: Sun, 24 Feb 2019 14:56:01 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 17 Xref: reader01.eternal-september.org comp.lang.vhdl:9415 On Sunday, February 24, 2019 at 5:43:13 AM UTC-5, Electronics_hobbyist wrot= e: >=20 > I have the freedom to choose any solution I prefer. I am thinking of Conv= olution Neural Networks as I have read papers about this. But, my main conc= ern is that on FPGAs there is a memory bottleneck. On the same FPGA I shoul= d use a core for the camera, the NN core and the serial interface core that= will output me the result. Is there any source/link/book that could help m= e on how to start? Before you do any writing of code, you should plan how you are going to deb= ug it, with "it" being each the algorithm and the implementation. =20 If you are just connecting prewritten modules there shouldn't be much need = to study books other than language books. Do you know which language you w= ill be using? What language are the modules written in?=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:10 2024 X-Received: by 2002:aed:3f84:: with SMTP id s4mr8311305qth.44.1551027586287; Sun, 24 Feb 2019 08:59:46 -0800 (PST) X-Received: by 2002:a25:3085:: with SMTP id w127mr138036ybw.6.1551027586163; Sun, 24 Feb 2019 08:59:46 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no5471039qta.0!news-out.google.com!y15ni3270qta.0!nntp.google.com!m21no5471028qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Feb 2019 08:59:45 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sun, 24 Feb 2019 16:59:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 22 Xref: reader01.eternal-september.org comp.lang.vhdl:9416 On Sunday, February 24, 2019 at 4:56:02 PM UTC+2, gnuarm.del...@gmail.com w= rote: > On Sunday, February 24, 2019 at 5:43:13 AM UTC-5, Electronics_hobbyist wr= ote: > >=20 > > I have the freedom to choose any solution I prefer. I am thinking of Co= nvolution Neural Networks as I have read papers about this. But, my main co= ncern is that on FPGAs there is a memory bottleneck. On the same FPGA I sho= uld use a core for the camera, the NN core and the serial interface core th= at will output me the result. Is there any source/link/book that could help= me on how to start? >=20 > Before you do any writing of code, you should plan how you are going to d= ebug it, with "it" being each the algorithm and the implementation. =20 >=20 > If you are just connecting prewritten modules there shouldn't be much nee= d to study books other than language books. Do you know which language you= will be using? What language are the modules written in?=20 >=20 > Rick C. I have built it in python. But I will program it in VHDL for obvious reason= s, i.e. faster decision of the NN if the person is man or woman... From newsfish@newsfish Thu Aug 1 00:44:11 2024 X-Received: by 2002:a0c:9188:: with SMTP id n8mr8728907qvn.3.1551035492464; Sun, 24 Feb 2019 11:11:32 -0800 (PST) X-Received: by 2002:a0d:e848:: with SMTP id r69mr121859ywe.5.1551035492349; Sun, 24 Feb 2019 11:11:32 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no5651357qta.0!news-out.google.com!y15ni3387qta.0!nntp.google.com!m21no5651350qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Feb 2019 11:11:32 -0800 (PST) In-Reply-To: <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=172.76.165.244; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 172.76.165.244 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: gnuarm.deletethisbit@gmail.com Injection-Date: Sun, 24 Feb 2019 19:11:32 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3005 X-Received-Body-CRC: 1203767596 Xref: reader01.eternal-september.org comp.lang.vhdl:9417 On Sunday, February 24, 2019 at 11:59:47 AM UTC-5, Electronics_hobbyist wro= te: > On Sunday, February 24, 2019 at 4:56:02 PM UTC+2, gnuarm.del...@gmail.com= wrote: > > On Sunday, February 24, 2019 at 5:43:13 AM UTC-5, Electronics_hobbyist = wrote: > > >=20 > > > I have the freedom to choose any solution I prefer. I am thinking of = Convolution Neural Networks as I have read papers about this. But, my main = concern is that on FPGAs there is a memory bottleneck. On the same FPGA I s= hould use a core for the camera, the NN core and the serial interface core = that will output me the result. Is there any source/link/book that could he= lp me on how to start? > >=20 > > Before you do any writing of code, you should plan how you are going to= debug it, with "it" being each the algorithm and the implementation. =20 > >=20 > > If you are just connecting prewritten modules there shouldn't be much n= eed to study books other than language books. Do you know which language y= ou will be using? What language are the modules written in?=20 > >=20 > > Rick C. >=20 > I have built it in python. But I will program it in VHDL for obvious reas= ons, i.e. faster decision of the NN if the person is man or woman... Have you programmed in VHDL before?=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:11 2024 X-Received: by 2002:aed:3525:: with SMTP id a34mr8957137qte.42.1551042553530; Sun, 24 Feb 2019 13:09:13 -0800 (PST) X-Received: by 2002:a25:e694:: with SMTP id d142mr17311ybh.4.1551042553411; Sun, 24 Feb 2019 13:09:13 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no5816849qta.0!news-out.google.com!o7ni2680qta.1!nntp.google.com!m21no5816843qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Feb 2019 13:09:13 -0800 (PST) In-Reply-To: <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.254; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.254 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Sun, 24 Feb 2019 21:09:13 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 33 Xref: reader01.eternal-september.org comp.lang.vhdl:9418 On Sunday, February 24, 2019 at 9:11:34 PM UTC+2, gnuarm.del...@gmail.com w= rote: > On Sunday, February 24, 2019 at 11:59:47 AM UTC-5, Electronics_hobbyist w= rote: > > On Sunday, February 24, 2019 at 4:56:02 PM UTC+2, gnuarm.del...@gmail.c= om wrote: > > > On Sunday, February 24, 2019 at 5:43:13 AM UTC-5, Electronics_hobbyis= t wrote: > > > >=20 > > > > I have the freedom to choose any solution I prefer. I am thinking o= f Convolution Neural Networks as I have read papers about this. But, my mai= n concern is that on FPGAs there is a memory bottleneck. On the same FPGA I= should use a core for the camera, the NN core and the serial interface cor= e that will output me the result. Is there any source/link/book that could = help me on how to start? > > >=20 > > > Before you do any writing of code, you should plan how you are going = to debug it, with "it" being each the algorithm and the implementation. =20 > > >=20 > > > If you are just connecting prewritten modules there shouldn't be much= need to study books other than language books. Do you know which language= you will be using? What language are the modules written in?=20 > > >=20 > > > Rick C. > >=20 > > I have built it in python. But I will program it in VHDL for obvious re= asons, i.e. faster decision of the NN if the person is man or woman... >=20 > Have you programmed in VHDL before?=20 >=20 > Rick C. Yes, many times, from simple digital design to FSMs. But first time I will = program Neural Networks. From newsfish@newsfish Thu Aug 1 00:44:11 2024 X-Received: by 2002:a0c:894a:: with SMTP id 10mr9397853qvq.18.1551051722527; Sun, 24 Feb 2019 15:42:02 -0800 (PST) X-Received: by 2002:a81:8483:: with SMTP id u125mr127733ywf.7.1551051722383; Sun, 24 Feb 2019 15:42:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no6025766qta.0!news-out.google.com!y15ni3551qta.0!nntp.google.com!m21no6025759qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Feb 2019 15:42:02 -0800 (PST) In-Reply-To: <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=172.76.165.244; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 172.76.165.244 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: gnuarm.deletethisbit@gmail.com Injection-Date: Sun, 24 Feb 2019 23:42:02 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 44 Xref: reader01.eternal-september.org comp.lang.vhdl:9419 On Sunday, February 24, 2019 at 4:09:14 PM UTC-5, Electronics_hobbyist wrot= e: > On Sunday, February 24, 2019 at 9:11:34 PM UTC+2, gnuarm.del...@gmail.com= wrote: > > On Sunday, February 24, 2019 at 11:59:47 AM UTC-5, Electronics_hobbyist= wrote: > > > On Sunday, February 24, 2019 at 4:56:02 PM UTC+2, gnuarm.del...@gmail= .com wrote: > > > > On Sunday, February 24, 2019 at 5:43:13 AM UTC-5, Electronics_hobby= ist wrote: > > > > >=20 > > > > > I have the freedom to choose any solution I prefer. I am thinking= of Convolution Neural Networks as I have read papers about this. But, my m= ain concern is that on FPGAs there is a memory bottleneck. On the same FPGA= I should use a core for the camera, the NN core and the serial interface c= ore that will output me the result. Is there any source/link/book that coul= d help me on how to start? > > > >=20 > > > > Before you do any writing of code, you should plan how you are goin= g to debug it, with "it" being each the algorithm and the implementation. = =20 > > > >=20 > > > > If you are just connecting prewritten modules there shouldn't be mu= ch need to study books other than language books. Do you know which langua= ge you will be using? What language are the modules written in?=20 > > > >=20 > > > > Rick C. > > >=20 > > > I have built it in python. But I will program it in VHDL for obvious = reasons, i.e. faster decision of the NN if the person is man or woman... > >=20 > > Have you programmed in VHDL before?=20 > >=20 > > Rick C. >=20 > Yes, many times, from simple digital design to FSMs. But first time I wil= l program Neural Networks. Ok, so the issues you face should be similar to the issues of using Neural = Networks in python. =20 Of course, you will need to structure the algorithm to utilize parallelism = to fully exploit the speed advantages of hardware.=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:11 2024 X-Received: by 2002:a37:c094:: with SMTP id v20mr10588049qkv.23.1551107266621; Mon, 25 Feb 2019 07:07:46 -0800 (PST) X-Received: by 2002:a25:b49:: with SMTP id 70mr8257742ybl.393.1551107266395; Mon, 25 Feb 2019 07:07:46 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no7120103qta.0!news-out.google.com!y15ni4179qta.0!nntp.google.com!m21no7120094qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 25 Feb 2019 07:07:46 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.159.112.170; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 195.159.112.170 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: =?UTF-8?Q?Your_existing_VHDL_testbench_says_=E2=80=98Hello_world=E2=80=99_?= =?UTF-8?Q?in_just_4_minutes?= From: espen.tallaksen@bitvis.no Injection-Date: Mon, 25 Feb 2019 15:07:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 38 Xref: reader01.eternal-september.org comp.lang.vhdl:9420 - and that also includes preparing the use of any UVVM Utility Library com= mand available, - for logging, checking signal values and signal stability,= waiting for signal changes, values or stability, clock generation, synchro= nization, and lots of other very useful testbench functionality. The *exhaustive* list of what to do: 1. Download from Github https://github.com/UVVM/UVVM 2. Compile Utility Library as follows: a) Inside your simulator go to =E2=80=98uvvm_util/sim=E2=80=99 b) execute: =E2=80=98source ../script/compile_src.do=E2=80=99 3. Include the library inside your testbench by adding the following lines = before your testbench entity declaration: library uvvm_util; context uvvm_util.uvvm_util_context; 4. You may now enter any utility library command inside your testbench proc= esses (or subprograms) e.g. log("Hello world"); ---- You find a full Quick reference for all these commands inside the download = (or here: https://github.com/UVVM/UVVM/blob/master/uvvm_util/doc/util_quick= _ref.pdf). This includes a command overview - followed by detailed info per= command - including type overloads, description and examples. Invest another 4 minutes and you are ready to run your first high level tra= nsaction commands on AXI4-lite, AXI4-stream, Avalon, SPI, I2C, UART and mor= e. All you need to do is to compile and include the relevant Verification I= P (e.g. bitvis_vip_uart) in the same way as for bullets 2 and 3 above, and = then just execute any UART transaction command as given in the relevant qui= ck reference (e.g. uart_transmit(x"5A", "Transmitting my first byte", clk, = tx); UVVM is the fastest growing FPGA (and ASIC) verification methodology world-= wide (acc. to Wilson Research). Invest 4 minutes and get started now. (Ther= e is plenty documentation on Github. Check out the README file for more inf= o and links to Powerpoints, Documentation, Webinars, etc.. From newsfish@newsfish Thu Aug 1 00:44:12 2024 X-Received: by 2002:a0c:adf2:: with SMTP id x47mr2009149qvc.37.1551128508829; Mon, 25 Feb 2019 13:01:48 -0800 (PST) X-Received: by 2002:a25:d24d:: with SMTP id j74mr6314652ybg.228.1551128508529; Mon, 25 Feb 2019 13:01:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no7685803qta.0!news-out.google.com!y15ni4447qta.0!nntp.google.com!m21no7685794qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 25 Feb 2019 13:01:48 -0800 (PST) In-Reply-To: <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.121; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.121 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Mon, 25 Feb 2019 21:01:48 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 48 Xref: reader01.eternal-september.org comp.lang.vhdl:9421 On Monday, February 25, 2019 at 1:42:03 AM UTC+2, gnuarm.del...@gmail.com w= rote: > On Sunday, February 24, 2019 at 4:09:14 PM UTC-5, Electronics_hobbyist wr= ote: > > On Sunday, February 24, 2019 at 9:11:34 PM UTC+2, gnuarm.del...@gmail.c= om wrote: > > > On Sunday, February 24, 2019 at 11:59:47 AM UTC-5, Electronics_hobbyi= st wrote: > > > > On Sunday, February 24, 2019 at 4:56:02 PM UTC+2, gnuarm.del...@gma= il.com wrote: > > > > > On Sunday, February 24, 2019 at 5:43:13 AM UTC-5, Electronics_hob= byist wrote: > > > > > >=20 > > > > > > I have the freedom to choose any solution I prefer. I am thinki= ng of Convolution Neural Networks as I have read papers about this. But, my= main concern is that on FPGAs there is a memory bottleneck. On the same FP= GA I should use a core for the camera, the NN core and the serial interface= core that will output me the result. Is there any source/link/book that co= uld help me on how to start? > > > > >=20 > > > > > Before you do any writing of code, you should plan how you are go= ing to debug it, with "it" being each the algorithm and the implementation.= =20 > > > > >=20 > > > > > If you are just connecting prewritten modules there shouldn't be = much need to study books other than language books. Do you know which lang= uage you will be using? What language are the modules written in?=20 > > > > >=20 > > > > > Rick C. > > > >=20 > > > > I have built it in python. But I will program it in VHDL for obviou= s reasons, i.e. faster decision of the NN if the person is man or woman... > > >=20 > > > Have you programmed in VHDL before?=20 > > >=20 > > > Rick C. > >=20 > > Yes, many times, from simple digital design to FSMs. But first time I w= ill program Neural Networks. >=20 > Ok, so the issues you face should be similar to the issues of using Neura= l Networks in python. =20 >=20 > Of course, you will need to structure the algorithm to utilize parallelis= m to fully exploit the speed advantages of hardware.=20 >=20 > Rick C. Is there a helpful book/source I could start with? From newsfish@newsfish Thu Aug 1 00:44:12 2024 X-Received: by 2002:a0c:9e4a:: with SMTP id z10mr11906070qve.42.1551154584199; Mon, 25 Feb 2019 20:16:24 -0800 (PST) X-Received: by 2002:a81:6b54:: with SMTP id g81mr16837587ywc.232.1551154583953; Mon, 25 Feb 2019 20:16:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no8282983qta.0!news-out.google.com!o7ni3911qta.1!nntp.google.com!m21no8282973qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 25 Feb 2019 20:16:23 -0800 (PST) In-Reply-To: <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=172.76.165.244; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 172.76.165.244 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <566e2a4f-701e-4157-8a78-70cd999b224d@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: gnuarm.deletethisbit@gmail.com Injection-Date: Tue, 26 Feb 2019 04:16:24 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 56 Xref: reader01.eternal-september.org comp.lang.vhdl:9422 On Monday, February 25, 2019 at 3:01:50 PM UTC-6, Electronics_hobbyist wrot= e: > On Monday, February 25, 2019 at 1:42:03 AM UTC+2, gnuarm.del...@gmail.com= wrote: > > On Sunday, February 24, 2019 at 4:09:14 PM UTC-5, Electronics_hobbyist = wrote: > > > On Sunday, February 24, 2019 at 9:11:34 PM UTC+2, gnuarm.del...@gmail= .com wrote: > > > > On Sunday, February 24, 2019 at 11:59:47 AM UTC-5, Electronics_hobb= yist wrote: > > > > > On Sunday, February 24, 2019 at 4:56:02 PM UTC+2, gnuarm.del...@g= mail.com wrote: > > > > > > On Sunday, February 24, 2019 at 5:43:13 AM UTC-5, Electronics_h= obbyist wrote: > > > > > > >=20 > > > > > > > I have the freedom to choose any solution I prefer. I am thin= king of Convolution Neural Networks as I have read papers about this. But, = my main concern is that on FPGAs there is a memory bottleneck. On the same = FPGA I should use a core for the camera, the NN core and the serial interfa= ce core that will output me the result. Is there any source/link/book that = could help me on how to start? > > > > > >=20 > > > > > > Before you do any writing of code, you should plan how you are = going to debug it, with "it" being each the algorithm and the implementatio= n. =20 > > > > > >=20 > > > > > > If you are just connecting prewritten modules there shouldn't b= e much need to study books other than language books. Do you know which la= nguage you will be using? What language are the modules written in?=20 > > > > > >=20 > > > > > > Rick C. > > > > >=20 > > > > > I have built it in python. But I will program it in VHDL for obvi= ous reasons, i.e. faster decision of the NN if the person is man or woman..= . > > > >=20 > > > > Have you programmed in VHDL before?=20 > > > >=20 > > > > Rick C. > > >=20 > > > Yes, many times, from simple digital design to FSMs. But first time I= will program Neural Networks. > >=20 > > Ok, so the issues you face should be similar to the issues of using Neu= ral Networks in python. =20 > >=20 > > Of course, you will need to structure the algorithm to utilize parallel= ism to fully exploit the speed advantages of hardware.=20 > >=20 > > Rick C. >=20 > Is there a helpful book/source I could start with? What exactly do you want help with? What sort of book are you looking for?= =20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:12 2024 X-Received: by 2002:a37:444:: with SMTP id 65mr13288368qke.51.1551171435235; Tue, 26 Feb 2019 00:57:15 -0800 (PST) X-Received: by 2002:a25:b49:: with SMTP id 70mr11441475ybl.393.1551171435130; Tue, 26 Feb 2019 00:57:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no8634413qta.0!news-out.google.com!y15ni4935qta.0!nntp.google.com!m21no8634404qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Feb 2019 00:57:14 -0800 (PST) In-Reply-To: <566e2a4f-701e-4157-8a78-70cd999b224d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=147.102.7.117; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 147.102.7.117 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> <566e2a4f-701e-4157-8a78-70cd999b224d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <711e5072-2202-4bcf-a4c8-ae33ca1d406a@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Tue, 26 Feb 2019 08:57:15 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9423 Sample code on VHDL, about Neural Networks, that is working. So I can start from somewhere to build something. From theory to practice there is a huge gap without help.. Thank you. From newsfish@newsfish Thu Aug 1 00:44:13 2024 X-Received: by 2002:a37:a3c8:: with SMTP id m191mr13591067qke.20.1551191976370; Tue, 26 Feb 2019 06:39:36 -0800 (PST) X-Received: by 2002:a25:328c:: with SMTP id y134mr6577329yby.342.1551191976175; Tue, 26 Feb 2019 06:39:36 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no9108142qta.0!news-out.google.com!o7ni4418qta.1!nntp.google.com!m21no9108132qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Feb 2019 06:39:35 -0800 (PST) In-Reply-To: <711e5072-2202-4bcf-a4c8-ae33ca1d406a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=172.76.165.244; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 172.76.165.244 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> <566e2a4f-701e-4157-8a78-70cd999b224d@googlegroups.com> <711e5072-2202-4bcf-a4c8-ae33ca1d406a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e503f32-f13e-4728-8ce9-e0e94f032679@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: gnuarm.deletethisbit@gmail.com Injection-Date: Tue, 26 Feb 2019 14:39:36 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9424 On Tuesday, February 26, 2019 at 2:57:16 AM UTC-6, Electronics_hobbyist wro= te: > Sample code on VHDL, about Neural Networks, that is working. So I can sta= rt from somewhere to build something. From theory to practice there is a hu= ge gap without help.. VHDL and Neural Networks are two totally different things. There is no nee= d to combine them into one topic for study. If you have a working algorith= m in another language, you don't really need to consider the Neural Network= s so much. You just need to port that algorithm to VHDL like you would any= algorithm. So I don't think you need or will find a book on this exact to= pic.=20 The things you will need to pay attention to are how you will adjust the al= gorithm to suit the inherent parallelism available in hardware and how you = will debug the implementation, both in simulation and in the hardware.=20 Have you given this any thought? If you have questions you can ask here. = =20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:13 2024 X-Received: by 2002:a37:a282:: with SMTP id l124mr14158183qke.39.1551206035566; Tue, 26 Feb 2019 10:33:55 -0800 (PST) X-Received: by 2002:a0d:e685:: with SMTP id p127mr19320919ywe.63.1551206035278; Tue, 26 Feb 2019 10:33:55 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no9465205qta.0!news-out.google.com!y15ni5378qta.0!nntp.google.com!m21no9465198qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Feb 2019 10:33:54 -0800 (PST) In-Reply-To: <8e503f32-f13e-4728-8ce9-e0e94f032679@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.140.90.121; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 91.140.90.121 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> <566e2a4f-701e-4157-8a78-70cd999b224d@googlegroups.com> <711e5072-2202-4bcf-a4c8-ae33ca1d406a@googlegroups.com> <8e503f32-f13e-4728-8ce9-e0e94f032679@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8db3379a-45be-465d-b050-15205e054fa8@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Tue, 26 Feb 2019 18:33:55 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 24 Xref: reader01.eternal-september.org comp.lang.vhdl:9425 On Tuesday, February 26, 2019 at 4:39:38 PM UTC+2, gnuarm.del...@gmail.com = wrote: > On Tuesday, February 26, 2019 at 2:57:16 AM UTC-6, Electronics_hobbyist w= rote: > > Sample code on VHDL, about Neural Networks, that is working. So I can s= tart from somewhere to build something. From theory to practice there is a = huge gap without help.. >=20 > VHDL and Neural Networks are two totally different things. There is no n= eed to combine them into one topic for study. If you have a working algori= thm in another language, you don't really need to consider the Neural Netwo= rks so much. You just need to port that algorithm to VHDL like you would a= ny algorithm. So I don't think you need or will find a book on this exact = topic.=20 >=20 > The things you will need to pay attention to are how you will adjust the = algorithm to suit the inherent parallelism available in hardware and how yo= u will debug the implementation, both in simulation and in the hardware.=20 >=20 > Have you given this any thought? If you have questions you can ask here.= =20 >=20 > Rick C. Thanx a lot, for the help. From newsfish@newsfish Thu Aug 1 00:44:13 2024 X-Received: by 2002:a0c:b048:: with SMTP id l8mr15440196qvc.52.1551211976515; Tue, 26 Feb 2019 12:12:56 -0800 (PST) X-Received: by 2002:a25:bb50:: with SMTP id b16mr20349675ybk.101.1551211976296; Tue, 26 Feb 2019 12:12:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no9619744qta.0!news-out.google.com!o7ni4606qta.1!nntp.google.com!m21no9619731qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Feb 2019 12:12:56 -0800 (PST) In-Reply-To: <8db3379a-45be-465d-b050-15205e054fa8@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=172.76.165.244; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 172.76.165.244 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> <566e2a4f-701e-4157-8a78-70cd999b224d@googlegroups.com> <711e5072-2202-4bcf-a4c8-ae33ca1d406a@googlegroups.com> <8e503f32-f13e-4728-8ce9-e0e94f032679@googlegroups.com> <8db3379a-45be-465d-b050-15205e054fa8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Neural Network on Xilinx Virtex 5 From: gnuarm.deletethisbit@gmail.com Injection-Date: Tue, 26 Feb 2019 20:12:56 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 34 Xref: reader01.eternal-september.org comp.lang.vhdl:9426 On Tuesday, February 26, 2019 at 12:33:57 PM UTC-6, Electronics_hobbyist wr= ote: > On Tuesday, February 26, 2019 at 4:39:38 PM UTC+2, gnuarm.del...@gmail.co= m wrote: > > On Tuesday, February 26, 2019 at 2:57:16 AM UTC-6, Electronics_hobbyist= wrote: > > > Sample code on VHDL, about Neural Networks, that is working. So I can= start from somewhere to build something. From theory to practice there is = a huge gap without help.. > >=20 > > VHDL and Neural Networks are two totally different things. There is no= need to combine them into one topic for study. If you have a working algo= rithm in another language, you don't really need to consider the Neural Net= works so much. You just need to port that algorithm to VHDL like you would= any algorithm. So I don't think you need or will find a book on this exac= t topic.=20 > >=20 > > The things you will need to pay attention to are how you will adjust th= e algorithm to suit the inherent parallelism available in hardware and how = you will debug the implementation, both in simulation and in the hardware.= =20 > >=20 > > Have you given this any thought? If you have questions you can ask her= e. =20 > >=20 > > Rick C. >=20 > Thanx a lot, for the help. What is the basis of the neural network algorithm? How is the software org= anized? I guess the key issue in performance are the high order loops, thi= ngs that are iterated in nested loops. Have you thought much about how the= y will be implemented in VHDL?=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:13 2024 X-Received: by 2002:a05:620a:1365:: with SMTP id d5mr17947qkl.28.1551261145736; Wed, 27 Feb 2019 01:52:25 -0800 (PST) X-Received: by 2002:a25:d24d:: with SMTP id j74mr1188244ybg.228.1551261145593; Wed, 27 Feb 2019 01:52:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!m21no906661qta.0!news-out.google.com!o7ni583qta.1!nntp.google.com!m21no906659qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Feb 2019 01:52:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:648:2000:7:d44f:2c41:fbb1:e523; posting-account=HDXwlAgAAABDHTD5r3vlFUQI9kvoygfo NNTP-Posting-Host: 2001:648:2000:7:d44f:2c41:fbb1:e523 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> <566e2a4f-701e-4157-8a78-70cd999b224d@googlegroups.com> <711e5072-2202-4bcf-a4c8-ae33ca1d406a@googlegroups.com> <8e503f32-f13e-4728-8ce9-e0e94f032679@googlegroups.com> <8db3379a-45be-465d-b050-15205e054fa8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f83baeb-6230-4c1b-8cf5-33a6cba5c7c8@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: Electronics_hobbyist Injection-Date: Wed, 27 Feb 2019 09:52:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 41 Xref: reader01.eternal-september.org comp.lang.vhdl:9427 On Tuesday, February 26, 2019 at 10:12:59 PM UTC+2, gnuarm.del...@gmail.com= wrote: > On Tuesday, February 26, 2019 at 12:33:57 PM UTC-6, Electronics_hobbyist = wrote: > > On Tuesday, February 26, 2019 at 4:39:38 PM UTC+2, gnuarm.del...@gmail.= com wrote: > > > On Tuesday, February 26, 2019 at 2:57:16 AM UTC-6, Electronics_hobbyi= st wrote: > > > > Sample code on VHDL, about Neural Networks, that is working. So I c= an start from somewhere to build something. From theory to practice there i= s a huge gap without help.. > > >=20 > > > VHDL and Neural Networks are two totally different things. There is = no need to combine them into one topic for study. If you have a working al= gorithm in another language, you don't really need to consider the Neural N= etworks so much. You just need to port that algorithm to VHDL like you wou= ld any algorithm. So I don't think you need or will find a book on this ex= act topic.=20 > > >=20 > > > The things you will need to pay attention to are how you will adjust = the algorithm to suit the inherent parallelism available in hardware and ho= w you will debug the implementation, both in simulation and in the hardware= .=20 > > >=20 > > > Have you given this any thought? If you have questions you can ask h= ere. =20 > > >=20 > > > Rick C. > >=20 > > Thanx a lot, for the help. >=20 > What is the basis of the neural network algorithm? How is the software o= rganized? I guess the key issue in performance are the high order loops, t= hings that are iterated in nested loops. Have you thought much about how t= hey will be implemented in VHDL?=20 >=20 > Rick C. I have build the CNN in Raspberry in python but it takes 30-40 sec to decid= e if the photo shows a man or a woman. I want to accelarate this. How much = faster can it go to the Virtex 5? Can I achieve 1-2 sec to take the decisio= n? From newsfish@newsfish Thu Aug 1 00:44:14 2024 X-Received: by 2002:aed:35a1:: with SMTP id c30mr1216837qte.57.1551276556273; Wed, 27 Feb 2019 06:09:16 -0800 (PST) X-Received: by 2002:a0d:ebcc:: with SMTP id u195mr1229611ywe.132.1551276555974; Wed, 27 Feb 2019 06:09:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m21no1267985qta.0!news-out.google.com!o7ni755qta.1!nntp.google.com!m21no1267983qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Feb 2019 06:09:15 -0800 (PST) In-Reply-To: <6f83baeb-6230-4c1b-8cf5-33a6cba5c7c8@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=172.76.165.244; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 172.76.165.244 References: <62e63177-6e2d-4d2c-98ff-0383f6129e35@googlegroups.com> <4e889bbd-d1d1-430d-a73b-a8ab0f1bfdba@googlegroups.com> <227c1839-ddc1-4324-acbf-88b6a4978f3d@googlegroups.com> <54d9fed8-d5d0-45d8-89b1-c42df46016e9@googlegroups.com> <4e39a36e-1015-47ab-bdfd-3eb6fe88c494@googlegroups.com> <784db034-3eaa-4cb4-8fad-b9122cff1026@googlegroups.com> <9f8eb2ed-5aba-4bd4-bc39-f451ecdd4f3f@googlegroups.com> <79bd49b6-8283-404e-893d-ed03360fe624@googlegroups.com> <17762a5a-e08e-4e85-8489-cf0a15409ca1@googlegroups.com> <1af73ac7-be92-4fc6-8865-6866eec08811@googlegroups.com> <566e2a4f-701e-4157-8a78-70cd999b224d@googlegroups.com> <711e5072-2202-4bcf-a4c8-ae33ca1d406a@googlegroups.com> <8e503f32-f13e-4728-8ce9-e0e94f032679@googlegroups.com> <8db3379a-45be-465d-b050-15205e054fa8@googlegroups.com> <6f83baeb-6230-4c1b-8cf5-33a6cba5c7c8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1ff22229-c9b5-46d7-bbbf-33d49df2663b@googlegroups.com> Subject: Re: Neural Network on Xilinx Virtex 5 From: gnuarm.deletethisbit@gmail.com Injection-Date: Wed, 27 Feb 2019 14:09:16 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 22 Xref: reader01.eternal-september.org comp.lang.vhdl:9428 On Wednesday, February 27, 2019 at 3:52:27 AM UTC-6, Electronics_hobbyist w= rote: >=20 > I have build the CNN in Raspberry in python but it takes 30-40 sec to dec= ide if the photo shows a man or a woman. I want to accelarate this. How muc= h faster can it go to the Virtex 5? Can I achieve 1-2 sec to take the decis= ion? What you are asking is a bit like "how long is a piece of string?" I know = nothing of the algorithm you implemented in python. The first step to spee= d this up is to identify where the processor is spending it's time. Have y= ou done that? =20 To implement this algorithm in VHDL you will need to understand the algorit= hm enough that you can figure out how to implement different parts to run i= n parallel without one part still being a huge bottle neck. So you need to= understand the timing of the code in python. Then you can figure out how = to accelerate it. Just coding it in VHDL won't automatically make it run f= aster. =20 Can you explain the neural network code? =20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:14 2024 X-Received: by 2002:ac8:1973:: with SMTP id g48mr1421764qtk.58.1551404685875; Thu, 28 Feb 2019 17:44:45 -0800 (PST) X-Received: by 2002:a81:9193:: with SMTP id i141mr1737179ywg.94.1551404685706; Thu, 28 Feb 2019 17:44:45 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.mixmin.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no576938qta.0!news-out.google.com!o7ni240qta.1!nntp.google.com!m21no576929qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Feb 2019 17:44:45 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.81.104.74; posting-account=nabjrwoAAADygAgmb13w3-FSHDn_Zy36 NNTP-Posting-Host: 2.81.104.74 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: HI. I'M AN EX BIG MAFIA MONEY LAUNDERER: STUART NEWBY FROM MONACO. EX KLEINWORT BENSON LONDON. THEN MONTANI MONACO. AS I JUST SAID, I'M AN EX ENORMOUS MAFIA'S MONEY LAUNDERER ( I DID THAT IN LONDON, IN SINGAPORE AND SINCE MAN YEARS, IN COTE D'AZUR... From: STUART-NEWBY MONTANI MONACO EX-KLEINWORTBENSON Injection-Date: Fri, 01 Mar 2019 01:44:45 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9429 HI. I'M AN EX BIG MAFIA MONEY LAUNDERER: STUART NEWBY FROM MONACO. EX KLEIN= WORT BENSON LONDON. THEN MONTANI MONACO. AS I JUST SAID, I'M AN EX ENORMOUS= MAFIA'S MONEY LAUNDERER ( I DID THAT IN LONDON, IN SINGAPORE AND SINCE MAN= YEARS, IN COTE D'AZUR......IN MONACO, IN MONTECARLO, THRU MY EXTREMELY CRI= MINAL COMPANY CALLED MONTANI )! I HAVE BEEN WASHING LOT OF MAFIA KILILING C= ASH WITH THIS PEDOPHILE FREEMASON BROTHER OF MINE, MALAVITOSO HOODED BROTHE= R OF MINE: VERY VERY CRIMINAL PAOLO BARRAI. BORN IN MILAN ON 28.6.65. BOUT = WHO I WANT TO TELL A LOT, NOW. I WANT TO MAKE SOME BIG BIG REPENTANT MAFIOS= O'S CONFESSIONS BOUT ALL THIS AND RIGHT NOW!!!!!!!!!! 1 IS A PEDOPHILE SODOMIZING CHILDREN: PAOLO PIETRO BARRAI (BITCOIN: THAT "IT"= USES X MAFIA-MONEY-LAUNDERING THRU VERY CRIMINAL EIDOO, VERY CRIMINAL CRYP= TOLAB S A, VERY CRIMINAL CRYPTOPOLIS, VERY CRIMINAL MEDICALCHAIN, VERY CRIM= INAL BITMAX, VERY CRIMINAL WMO GROUP)! EXTREMELY DANGEROUS PEDERAST PAOLO P= IETRO BARRAI WELL KNOWN ALL AROUND THE WORLD AS " THE PEDOPHILE OF BITCOIN"= ! MAFIA MONEY LAUNDERER PAOLO BARRAI BORN IN MILAN ON 28.6.65 USES BITCOIN = TO ORGANIZE THE RAPING OF CHILDREN AND TO PROMOTE PORNOGRAPHY FOR PEDOPHILE= S LIKE HIM! WE GOT LOT OF PROOVES BOUT IT!!! YES, IS HOMOSEXUAL OF PEDOPHIL= E KIND PAOLO BARRAI: BLOG "MERDATO" LIBERO ALIAS "STALKING SHIT SPREADED IN= A FREE WAY WITH NAZIST JOSEPH GOEBBELS'S STYLE". STALKING SHIT BASED ON IM= MENSE FAKE IN ORDER TO KILL EVERYONE IS NOT HITLERIAN & ANTI SEMITIC LIKE H= IM! PAOLO BARRAI IS A BASTARD ASSASSIN, PAOLO BARRAI IS A PRINCIPAL OF MANY= MURDERS! PAOLO BARRAI HAS ALREADY GONE 3 TIMES TO JAIL! PAOLO BARRAI HAS B= EEN FIRED BADLY BY CITIBANK MILAN! PAOLO BARRAI HAS BEEN VERY HEAVILY FINED= BY CONSOB! PAOLO BARRAI HAS ESCAPED FROM BRASIL AT NIGHT, GETTING A FIRST = AVAILABLE FLIGHT, IN THE MIDDLE OF CARNAVAL DAYS, TO NOT FINISH IN JAIL: FO= R EXTREMELY SERIOUS CRIMES LIKE HAVING RAPED AN 8 YEARS OLD CHILD, AS WELL = AS FOR ENORMOUS FRAUDS, MAFIA MONEY LAUNDERING, NAZIST AND RACIST PROPAGAND= A, EXECUTION OF KILLING THREATS, BLACKMAILS AND EXTORSIONS.... AND, LITTLE = SWEET CHERRY ON CAKE: PEDERAST SEX HE HAD WITH AND 8 YEARS OLD CHILD. BASTARD ASSASSIN WORM PAOLO BARRAI IS ALSO A MEGA SCAMMER, BURNING ALL SAVI= NGS OF EVERYONE FALLING IN HIS -CYBER-MEDIATIC-FINANCIAL TRAPS! AL CAPONE O= F FINANCE: PAOLO BARRAI BORN IN MILAN ON 28.6.1965 ( LAUNDERING CASH FROM C= OSA NOSTRA, CAMORRA, NDRANGHETA, AS WELL AS CRIMINAL CASH FROM NAZIRACIST M= OVEMENTS LEGA NORD AND FORZA ITALIA, IN EXTREMELY CRIMINAL EIDOO SWITZERLAN= D AND EXTREMELY CRIMINAL CRYPTOPOLIS SWITZERLAND)!!! AND.. AGAIN.. AND..AGAIN..AND..AGAIN... IS ONE OF MOST BASTARD CRIMINAL CONNECTED TO PANAMA PAPERS, STINKY WORM PAO= LO BARRAI, ALREADY THREE TIMES IN JAIL, BORN IN MILAN ON 28.6.1965 YES, I AM WRITING BOUT CRIMINAL ASSASSIN PEDOPHILE PAOLO BARRAI FROM MEDICA= LCHAIN, CRIMINAL ASSASSIN PEDOPHILE PAOLO BARRAI FROM CRYPTOLAB S A, CRIMINAL ASSASSIN PEDOPHILE PAOLO BARRAI FROM CRYPTOPOLIS, CRIMINAL ASSASSI= N PEDOPHILE PAOLO BARRAI FROM BITMAX, CRIMINAL ASSASSIN PEDOPHILE PAOLO BAR= RAI FROM VERY FAILING ICO EIDOO, ICO MEGA MAFIA MONEY LAUNDERER FOR NDRANGH= ETA, VIA STINKY DELINQUENT NETALE FERRARA FROM REGGIO CALABRIA. CAREFUL TO THIS LOUSY VERY NASTY, SAVAGE DELINQUENT: PAOLO PIETRO BARRAI EX= CITIBANK MILAN, BORN IN MILAN ON 28.06.1965, CONDEMEND TO JAIL ALREADY MAN= Y TIMES! ONE OF DIRTIEST MAFIA AND CRIMINAL COLLARS MONEY LAUNDERER IN PANAMA ( AND = NOT ONLY IN PANAMA)... EXTREMELY DELINQUENT INDIVIDUAL, ALREADY THREE TIMES= IN PRISON ( EITHER IN ITALY AND ESPECIALLY IN BRAZIL), STINKY FELONIOUS PA= OLO BARRAI (OR STINKY FELONIOUS PAOLO "PIETRO" BARRAI), BORN IN MILAN ON 28= .06.1965. 2 FROM VERY VERY CRIMINAL WMO SA PANAMA, VERY VERY CRIMINAL WORLD MAN OPPORTU= INITES VIA MAZZINI 14 LUGANO, VERY VERY CRIMINAL BSI ITALIA SRL VIA SOCRATE= 26 MILAN, VERY VERY CRIMINAL BLOG MERCATO LIBERO ( NOT FOR NOTHING, EVERYO= NE IN ITALY AND INITALIAN SPEAKING PART OF SWITZERLAND, KNOWING HOW MANY CR= IMES AND WHAT HORRIBLE KIND OF CRIMES, PAOLO BARRAI, ALWAYS DOES, CALLS THI= S BLOG: "MERDATO" LIBERO). FINED VERY HEAVILY BY CONSOB FOR MEGA FRAUDS HE DID ON PV BUSINESS AND NOT = ONLY http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html https://www.adviseonly.com/blog/investire/mercati-finanziari/il-trading-dei= -miracoli/ http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion FIRED BADLY BY CITIBANK MILAN FOR MEGA ROBERRIES, COLLECTION OF BRIBES AND = FRAUDS "IT" USED TO ORGAINZE THERE. MADE CONDEMNED TO JAIL BY CITIBANK MILA= N. CONDEMNED TO JAIL, THEN, EVEN IN BRAZIL, FOR OTHER FRAUDS, FOR MAFIA MONEY = LAUNDERING, FOR ATTEMPTED EXTORTION, FOR DEATH THREATS DONE, FOR BLACKMAILS= DONE, FOR INTERNET STALKING DONE AND ALSO ATTEMPTS OF HAVING PEDOPHILE SEX= WITH VIEW UNDERAGE LOCAL BOYS ( INFACT, SINCE ALL THIS GOT SENTENCED, EXTR= EMELY CRIMINAL PAOLO BARRAI HAS NEVER PUT A FEET IN BRAZIL ANYMORE... HERE = FOLLOWS A LINK CORRESPONDING TO THE BEGINNING OF ANY INVESTIGATION http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato ) "IT" TOTALLY BURNED, TOTALLY NULLIFY 100% OF THE SAVINGS SOME CANDID PEOPLE= HE SCRUBBED VIA INTERNET, GAVE HIM TO INVEST ( EVEN BECAUSE IN HAVING "NOS= E FOR BUSINESS", IN HAVING "BUSINESS INTUITION", PAOLO BARRAI IS AN ABSOLUT= E DONKEY: HIS PREVISIONS IN WORLDWIDE STOCKS, COMODITIES, CURRENCIES, REAL = ESTATES, ARE ALWAYS WRONG, WRONG, INCREDIBLY WRONG... ALWAYS.... WITH ZERO = EXCEPTIONS...EVERY ONE IN FINANCIAL BUSINESS CALLS HIM "REVERSAL INDICATOR"= ). "IT" HAS BEEN WASHING IN PANAMA ( IN CONNECTION WITH MOSSACK FONSECA AND= NOT ONLY), SWITZERLAND ( BY FINTER BANK ZURICH LUGANO AND BANCA STATO LUGA= NO), GERMANY, SPAIN, ESTONIA AND DUBAI, LOT AND LOT OF -ASSASSIN ITALIAN COSA NOSTRA, NDRANGHETA, CAMORRA'S CASH -ASSASSIN COLOMBIAN MAFIA CASH -ASSASSIN MEXICAN MAFIA CASH -NAZIRACIST LEGA NORD'S CASH ( COMING FROM MEGA CORRUPTION, MEGA ROBBERIES,= DIRTY BUSINESSES OF THESE KUKLUKKLANIST MIXED TO NDRANGHETIST FROM LEGA NO= RD, IN CONNECTION WITH DICTATORS LIKE PUTIN, GHEDDAFI AND LE PEN'S FAMILY) HE CALLED MANY TIMES OBAMA BARACK A BLACK BASTARD http://ilpunto-borsainvestimenti.blogspot.com/2013/01/ecco-limpatto-fiscale= -che-ha-fatto.html AN HISTERICAL FAIRY http://ilpunto-borsainvestimenti.blogspot.com/2014/03/mercato-libero-e-per-= la-grande-madre.html ( "IT" CALLS OTHER PEOPLE "FAIRY" BUT THEN ALWAYS LOOKS FOR 8, 10, 12, 14 Y= EARS OLD GYPSY MALE PROSTITUTES TO MAKE PAEDERAST SEX WITH) - FASCIST MAFIOSO DICTATOR, PRINCIPAL OF MANY MURDERS AND SLAUGHTERS, AS MU= CH AS ASCERTAINED PEDOPHILE SILVIO BERLUSCONI'S CASH http://www.mercatolibero.info/panama-mercato-libero/ INFACT, SILVIO BERLUSCONI, LEGA NORD, COSA NOSTRA, CAMORRA, NDRANGHETA, COL= OMBIAN MAFIA, MEXICAN MAFIA, ARE, SINCE ALWAYS, SAME KILLING CHOLERIC SEWER= ! 3 PS BE STRONG NOW PLS. AS JUST MENTIONED BEFORE, BUT BETTER EXPLAINED NOW, EXTR= EMELY CRIMINAL PAOLO BARRAI BORN IN MILAN ON 28.6.1965, HAS THE CARD OF WOR= LDWIDE ASSOCIATION OF PEDOPHILES: " PEDOPHILE PRIDE". "IT" SAID MANY TIMES, IN PRIVATE, "IT" HAS BECOME, SINCE VIEW YEARS, AN HOM= OSEXUAL PEDOPHILE. A PAEDERAST. AND "IT" IS PROUD TO MAKE SEX WITH BOYS JUS= T A LITTLE BIT MORE THAN CHILDREN, BEING KIDS 8, 10, 12, 14 YEARS OLD. "IT"= SAID THIS HAPPENS EVERY TIME "IT" GOES TO PANAMA, LATIN AMERICA IN GENERAL= AND THAILAND ( AND OUT OF PANAMA PAPERS ARE COMING OUT VARIOUS CASES OF PE= DOPHILES AND MAFIOSI HAVING EXTREMELY DIRTY CASH THERE: ONE OF THEIR MAIN C= RIMINAL BANKING INTERMEDIARIES WAS THIS "SURPLUS OF PRISON" WHO IS PAOLO BA= RRAI )!!!!!!!!! From newsfish@newsfish Thu Aug 1 00:44:14 2024 X-Received: by 2002:a0c:9254:: with SMTP id 20mr1611507qvz.62.1552509606961; Wed, 13 Mar 2019 13:40:06 -0700 (PDT) X-Received: by 2002:a81:2e0e:: with SMTP id u14mr1958879ywu.323.1552509606243; Wed, 13 Mar 2019 13:40:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no2607681qta.0!news-out.google.com!i54ni654qte.0!nntp.google.com!m21no2607672qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 13 Mar 2019 13:40:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=139.179.209.72; posting-account=lFKKCAoAAABqFFAO3QUpvYDnP2iKdpCM NNTP-Posting-Host: 139.179.209.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ca4d4ea-ca0b-4374-9d19-0d77e6f1ccfa@googlegroups.com> Subject: Green/Red detector and button controlled car (BASYS3/VHDL) From: utkudenizal@gmail.com Injection-Date: Wed, 13 Mar 2019 20:40:06 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9430 Hi, I am a 2nd-year ee student, and I need to make a term Project. With BAS= YS3 by using VHDL. My purpose is constructing a car which can be controlled with the buttons o= n BASYS3 ( I think I need Bluetooth module for it to RC a car). In addition= to that my car should stop when it sees red ( i think I should use a color= sensor for it) and should not work until it sees a green. These =E2=80=9Cr= ed=E2=80=9D and =E2=80=9Cgreen=E2=80=9D can be anything like green cubic to= ys. This color sensor does not have to be mounted on the car, but it would be b= etter if it is. I have very little information about basys3, vhdl, sensor design, etc. (thi= s is my first course in ee I was learning principle courses like math, phy,= cs ) I would appreciate any help. Thanks. From newsfish@newsfish Thu Aug 1 00:44:15 2024 X-Received: by 2002:a37:c206:: with SMTP id i6mr11676830qkm.40.1552518495645; Wed, 13 Mar 2019 16:08:15 -0700 (PDT) X-Received: by 2002:a25:4b83:: with SMTP id y125mr29161921yba.503.1552518495424; Wed, 13 Mar 2019 16:08:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder.erje.net!2.eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.fr7!futter-mich.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m21no2892333qta.0!news-out.google.com!i54ni844qte.0!nntp.google.com!m21no2892330qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 13 Mar 2019 16:08:15 -0700 (PDT) In-Reply-To: <5ca4d4ea-ca0b-4374-9d19-0d77e6f1ccfa@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <5ca4d4ea-ca0b-4374-9d19-0d77e6f1ccfa@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4fffd20c-06a7-49bc-b446-b4a0570af31b@googlegroups.com> Subject: Re: Green/Red detector and button controlled car (BASYS3/VHDL) From: gnuarm.deletethisbit@gmail.com Injection-Date: Wed, 13 Mar 2019 23:08:15 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2963 X-Received-Body-CRC: 3612566269 Xref: reader01.eternal-september.org comp.lang.vhdl:9431 On Wednesday, March 13, 2019 at 4:40:08 PM UTC-4, utkud...@gmail.com wrote: > Hi, I am a 2nd-year ee student, and I need to make a term Project. With B= ASYS3 by using VHDL. >=20 > My purpose is constructing a car which can be controlled with the buttons= on BASYS3 ( I think I need Bluetooth module for it to RC a car). In additi= on to that my car should stop when it sees red ( i think I should use a col= or sensor for it) and should not work until it sees a green. These =E2=80= =9Cred=E2=80=9D and =E2=80=9Cgreen=E2=80=9D can be anything like green cubi= c toys. > This color sensor does not have to be mounted on the car, but it would be= better if it is. >=20 > I have very little information about basys3, vhdl, sensor design, etc. (t= his is my first course in ee I was learning principle courses like math, ph= y, cs ) This seems like an advanced project for a second year student. Have you ha= d a course in digital logic design? I Googled basys3 and it is an FPGA boa= rd. =20 It looks like the basys 3 board has PMOD connectors for I/O. You will need= to find a light detector and possibly use red and green light detectors to= make it color sensitive I suppose. If the light detector has a threshold = you use it with a digital input. But more likely it will be a variable out= put so you will need to use an ADC input and possibly signal conditioning m= eaning an amplifier and maybe a filter.=20 I have found bluetooth to be a bit of a PITA for small circuits. The cheap= modules I bought just didn't work well. Good luck with that.=20 Rick C. From newsfish@newsfish Thu Aug 1 00:44:15 2024 X-Received: by 2002:a05:620a:164e:: with SMTP id c14mr10463598qko.38.1552933851513; Mon, 18 Mar 2019 11:30:51 -0700 (PDT) X-Received: by 2002:a81:7a94:: with SMTP id v142mr15287765ywc.221.1552933851045; Mon, 18 Mar 2019 11:30:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m21no7708621qta.0!news-out.google.com!d8ni2296qtr.1!nntp.google.com!m21no7708618qta.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 18 Mar 2019 11:30:50 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=139.179.209.244; posting-account=lFKKCAoAAABqFFAO3QUpvYDnP2iKdpCM NNTP-Posting-Host: 139.179.209.244 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Color sensor with BASYS3 VHDL From: utkudenizal@gmail.com Injection-Date: Mon, 18 Mar 2019 18:30:51 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9432 Hi, I need to make a circuit which does the following thing: When it sees a red object it will send output 0 until it sees a green objec= t (like a well colored cubic toy), after it sees green it will send output = 1 until it sees red again. ( If it is hard to implement I'm ok with just ou= tput 0 when it sees red and outputs 1 when it sees green, I mean it is ok i= f the outputs not continuous but it would be great if they are continuous)= =20 I have basys3 and have to use VHDL. I think I should use TCS34725 sensor ht= tps://www.adafruit.com/product/1334 but I'm not sure I just assumed, I woul= d be really glad if someone helps Some extra questions: If it is possible I will implement it on a toy RCcar = is it possible to connect it with Bluetooth module to get inputs or how sho= uld I do it ?- I can use another board JUST FOR CONNECTIONS my main Project= should be on BASYS-3 Thanks From newsfish@newsfish Thu Aug 1 00:44:15 2024 X-Received: by 2002:ae9:eb41:: with SMTP id b62mr21116418qkg.309.1553552977804; Mon, 25 Mar 2019 15:29:37 -0700 (PDT) X-Received: by 2002:a25:6004:: with SMTP id u4mr23788774ybb.149.1553552977650; Mon, 25 Mar 2019 15:29:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t9no2325853qtn.0!news-out.google.com!i54ni4694qte.0!nntp.google.com!t9no2325849qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 25 Mar 2019 15:29:37 -0700 (PDT) In-Reply-To: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=96.95.37.73; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 96.95.37.73 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: gnuarm.deletethisbit@gmail.com Injection-Date: Mon, 25 Mar 2019 22:29:37 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 43 Xref: reader01.eternal-september.org comp.lang.vhdl:9433 On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang wrote: > Hi Jim, glen, JK, rickman, Mike, Andy,=20 >=20 > I have filed a provisional patent application: "Systematic method of codi= ng wave pipelined circuits in HDL". If it is proved correct, the patent wil= l introduce 1 keyword, 3 permanent constants, 1 concurrent statement and fo= ur source code modules for a new library in HDL and thoroughly resolve a pe= nding problem so that every digital designer can code wave-pipelined circui= ts in HDL. >=20 > Here is the abstract of the invention: >=20 > The present invention classifies all critical paths into two basic ty= pes: a series critical path and a feedback critical path, and divides each = of wave-pipelined circuits into two components: a static logic part, called= critical path component (CPC), and a dynamic logic part, formalized into f= our wave-pipelining components (WPC) shared by all wave-pipelined circuits.= Each wave-pipelining ready code in HDL comprises two components: a WPC ins= tantiation and a CPC instantiation wire-connected and linked by a new link = statement. Each WPC has new wave constants which play the same role as gene= ric constants do, but whose initial values are determined and assigned by a= synthesizer after code analysis, so designers can use after-synthesization= information in their code before synthesization for wave-pipelining techno= logy. The responsibility of analyzing and manipulating wave-pipelining read= y code, generating and implementing wave-pipelined circuits on a design-wid= e or chip-wide scale in HDL is shifted from designers to synthesizers. >=20 > Anyone who are interested in its content is welcome to send a email reque= st to the following email address: wtx wtx @ gmail . com with title "System= atic" and he will receive the full documents: one specification, 9 drawings= and one text file in VHDL. >=20 > If one reviews the files and feels that it would be a good thing to recom= mend the application to his company to buy it, the first person to do it af= ter his recommended company does so will receive $10,000 commission fee. Did you ever get your patent? I'm curious.=20 --=20 Rick C. -- Get a 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:16 2024 X-Received: by 2002:a05:620a:124a:: with SMTP id a10mr828754qkl.59.1553611170042; Tue, 26 Mar 2019 07:39:30 -0700 (PDT) X-Received: by 2002:a25:aa6e:: with SMTP id s101mr24750635ybi.18.1553611169802; Tue, 26 Mar 2019 07:39:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no4362038qtn.0!news-out.google.com!d8ni3906qtr.1!nntp.google.com!t9no4362032qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Mar 2019 07:39:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=139.179.55.176; posting-account=lFKKCAoAAABqFFAO3QUpvYDnP2iKdpCM NNTP-Posting-Host: 139.179.55.176 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: TCS34725 Basys3 VHDL From: utkudenizal@gmail.com Injection-Date: Tue, 26 Mar 2019 14:39:30 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9434 Hi I am trying to use TCS34725 to identify Green and Red Colors, it has I2C interface and i could not find any I2C interface about this and i am not capable to write a protocol code what should I do I am stucked. I just need when it sees green it turns one led and when it sees red it turns another led. From newsfish@newsfish Thu Aug 1 00:44:16 2024 X-Received: by 2002:a0c:93ba:: with SMTP id f55mr915508qvf.12.1553611814986; Tue, 26 Mar 2019 07:50:14 -0700 (PDT) X-Received: by 2002:a81:3253:: with SMTP id y80mr26400213ywy.63.1553611811862; Tue, 26 Mar 2019 07:50:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!t9no4387998qtn.0!news-out.google.com!d8ni3906qtr.1!nntp.google.com!t9no4387951qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Mar 2019 07:50:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:147:4002:f4bf:e547:80c7:8317:176d; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:e547:80c7:8317:176d References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <733ab3d1-5f53-43d0-8d94-dc098de43ccb@googlegroups.com> Subject: Re: TCS34725 Basys3 VHDL From: gnuarm.deletethisbit@gmail.com Injection-Date: Tue, 26 Mar 2019 14:50:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 22 Xref: reader01.eternal-september.org comp.lang.vhdl:9435 On Tuesday, March 26, 2019 at 10:39:32 AM UTC-4, utkud...@gmail.com wrote: > Hi I am trying to use TCS34725 to identify Green and Red Colors, it has I= 2C interface and i could not find any I2C interface about this and i am not= capable to write a protocol code what should I do I am stucked. >=20 > I just need when it sees green it turns one led and when it sees red it t= urns another led. I2C is not as simple as SPI. More importantly the TCS34725 device you are = trying to read has it's own protocol for reading the data. You will need t= o develop an I2C interface from the I2C spec to read and write the bytes to= the TCS34725. Then you will need to design a controller which understands= which bytes need to be written and read and extract the color information.= =20 Do you understand how the TCS34725 works?=20 --=20 Rick C. - Get a 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:16 2024 X-Received: by 2002:ac8:7519:: with SMTP id u25mr121181qtq.37.1553618282036; Tue, 26 Mar 2019 09:38:02 -0700 (PDT) X-Received: by 2002:a25:44a:: with SMTP id 71mr2062342ybe.228.1553618281720; Tue, 26 Mar 2019 09:38:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no4658775qtn.0!news-out.google.com!i54ni5638qte.0!nntp.google.com!t9no4658765qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Mar 2019 09:38:01 -0700 (PDT) In-Reply-To: <733ab3d1-5f53-43d0-8d94-dc098de43ccb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=139.179.55.176; posting-account=lFKKCAoAAABqFFAO3QUpvYDnP2iKdpCM NNTP-Posting-Host: 139.179.55.176 References: <733ab3d1-5f53-43d0-8d94-dc098de43ccb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <69be7a37-030a-4bab-a0bf-7e689ce2d400@googlegroups.com> Subject: Re: TCS34725 Basys3 VHDL From: utkudenizal@gmail.com Injection-Date: Tue, 26 Mar 2019 16:38:02 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9436 On Tuesday, March 26, 2019 at 5:50:17 PM UTC+3, gnuarm.del...@gmail.com wro= te: > On Tuesday, March 26, 2019 at 10:39:32 AM UTC-4, utkud...@gmail.com wrote= : > > Hi I am trying to use TCS34725 to identify Green and Red Colors, it has= I2C interface and i could not find any I2C interface about this and i am n= ot capable to write a protocol code what should I do I am stucked. > >=20 > > I just need when it sees green it turns one led and when it sees red it= turns another led. >=20 > I2C is not as simple as SPI. More importantly the TCS34725 device you ar= e trying to read has it's own protocol for reading the data. You will need= to develop an I2C interface from the I2C spec to read and write the bytes = to the TCS34725. Then you will need to design a controller which understan= ds which bytes need to be written and read and extract the color informatio= n.=20 >=20 > Do you understand how the TCS34725 works?=20 >=20 > --=20 >=20 > Rick C. >=20 > - Get a 1,000 miles of free Supercharging > - Tesla referral code - https://ts.la/richard11209 No From newsfish@newsfish Thu Aug 1 00:44:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!buffer2.nntp.dca1.giganews.com!buffer1.nntp.dca1.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 26 Mar 2019 15:05:59 -0500 From: Joe Chisolm Subject: Re: TCS34725 Basys3 VHDL Newsgroups: comp.lang.vhdl References: <733ab3d1-5f53-43d0-8d94-dc098de43ccb@googlegroups.com> <69be7a37-030a-4bab-a0bf-7e689ce2d400@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Tue, 26 Mar 2019 15:05:59 -0500 Lines: 43 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 216.169.226.78 X-Trace: sv3-D8KVpAtXLMLReKDOv4bNKAYpAFOr7VoTOVGubLJdD6kWuqZFgEmsd062pP7INJS0o3TJndMrxTD6QeQ!q8S+AuNXPg1eYRC3OV0UMmByaRvMWnf06vEiCaynGFNLOvZelgI18S944vhO3tluASwmsIbYyfM8!CGBTyjb6QbfZmfBSb5RCXRDRHRd5uvZZNSz5 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2652 Xref: reader01.eternal-september.org comp.lang.vhdl:9437 On Tue, 26 Mar 2019 09:38:01 -0700, utkudenizal wrote: > On Tuesday, March 26, 2019 at 5:50:17 PM UTC+3, gnuarm.del...@gmail.com > wrote: >> On Tuesday, March 26, 2019 at 10:39:32 AM UTC-4, utkud...@gmail.com >> wrote: >> > Hi I am trying to use TCS34725 to identify Green and Red Colors, it >> > has I2C interface and i could not find any I2C interface about this >> > and i am not capable to write a protocol code what should I do I am >> > stucked. >> > >> > I just need when it sees green it turns one led and when it sees red >> > it turns another led. >> >> I2C is not as simple as SPI. More importantly the TCS34725 device you >> are trying to read has it's own protocol for reading the data. You >> will need to develop an I2C interface from the I2C spec to read and >> write the bytes to the TCS34725. Then you will need to design a >> controller which understands which bytes need to be written and read >> and extract the color information. >> >> Do you understand how the TCS34725 works? >> >> -- >> >> Rick C. >> >> - Get a 1,000 miles of free Supercharging - Tesla referral code - >> https://ts.la/richard11209 > > No You might want to look at using a PCA9564 parallel to i2c controller. That way you dont have to put a i2c controller in your fpga. You are still going to have to program the TCS34725 but you could write and read 8 bits parallel. -- Chisolm Republic of Texas From newsfish@newsfish Thu Aug 1 00:44:17 2024 X-Received: by 2002:ac8:22e9:: with SMTP id g38mr1086696qta.47.1553651713402; Tue, 26 Mar 2019 18:55:13 -0700 (PDT) X-Received: by 2002:a25:d601:: with SMTP id n1mr26737310ybg.342.1553651713225; Tue, 26 Mar 2019 18:55:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no975569qtn.0!news-out.google.com!i54ni308qte.0!nntp.google.com!t9no975567qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Mar 2019 18:55:12 -0700 (PDT) In-Reply-To: <69be7a37-030a-4bab-a0bf-7e689ce2d400@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <733ab3d1-5f53-43d0-8d94-dc098de43ccb@googlegroups.com> <69be7a37-030a-4bab-a0bf-7e689ce2d400@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <97bba9e6-b9ed-4026-89ea-111679127138@googlegroups.com> Subject: Re: TCS34725 Basys3 VHDL From: gnuarm.deletethisbit@gmail.com Injection-Date: Wed, 27 Mar 2019 01:55:13 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9438 On Tuesday, March 26, 2019 at 12:38:03 PM UTC-4, utkud...@gmail.com wrote: > On Tuesday, March 26, 2019 at 5:50:17 PM UTC+3, gnuarm.del...@gmail.com w= rote: > > On Tuesday, March 26, 2019 at 10:39:32 AM UTC-4, utkud...@gmail.com wro= te: > > > Hi I am trying to use TCS34725 to identify Green and Red Colors, it h= as I2C interface and i could not find any I2C interface about this and i am= not capable to write a protocol code what should I do I am stucked. > > >=20 > > > I just need when it sees green it turns one led and when it sees red = it turns another led. > >=20 > > I2C is not as simple as SPI. More importantly the TCS34725 device you = are trying to read has it's own protocol for reading the data. You will ne= ed to develop an I2C interface from the I2C spec to read and write the byte= s to the TCS34725. Then you will need to design a controller which underst= ands which bytes need to be written and read and extract the color informat= ion.=20 > >=20 > > Do you understand how the TCS34725 works?=20 > >=20 >=20 > No The TCS34725 has registers that you need to read and maybe write to configu= re the device. I looked at the data sheet once, but I don't recall the det= ails. =20 The device has light sensors behind color filters. It also has ADC device(= s) in it to convert the amount of light falling on the sensors to a numeric= value. I think you have to write it to get it to start a conversion, then= when it is done read the data. You will need to read the data sheet and u= nderstand this device before you do anything else. =20 Once you read the data sheet, return here and ask questions. I believe you= are doing this for a school project, so I'm not going to spoon feed you. = Read, try to understand, then ask questions.=20 --=20 Rick C. + Get a 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:17 2024 X-Received: by 2002:ac8:278e:: with SMTP id w14mr1343261qtw.6.1553695762929; Wed, 27 Mar 2019 07:09:22 -0700 (PDT) X-Received: by 2002:a81:2cd7:: with SMTP id s206mr31221241yws.22.1553695762706; Wed, 27 Mar 2019 07:09:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no2555855qtn.0!news-out.google.com!d8ni544qtr.1!nntp.google.com!t9no2555847qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Mar 2019 07:09:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.37.123.58; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j NNTP-Posting-Host: 24.37.123.58 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Benjamin Couillard Injection-Date: Wed, 27 Mar 2019 14:09:22 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9439 Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a =C3=A9crit= =C2=A0: > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang wrote: > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > >=20 > > I have filed a provisional patent application: "Systematic method of co= ding wave pipelined circuits in HDL". If it is proved correct, the patent w= ill introduce 1 keyword, 3 permanent constants, 1 concurrent statement and = four source code modules for a new library in HDL and thoroughly resolve a = pending problem so that every digital designer can code wave-pipelined circ= uits in HDL. > >=20 > > Here is the abstract of the invention: > >=20 > > The present invention classifies all critical paths into two basic = types: a series critical path and a feedback critical path, and divides eac= h of wave-pipelined circuits into two components: a static logic part, call= ed critical path component (CPC), and a dynamic logic part, formalized into= four wave-pipelining components (WPC) shared by all wave-pipelined circuit= s. Each wave-pipelining ready code in HDL comprises two components: a WPC i= nstantiation and a CPC instantiation wire-connected and linked by a new lin= k statement. Each WPC has new wave constants which play the same role as ge= neric constants do, but whose initial values are determined and assigned by= a synthesizer after code analysis, so designers can use after-synthesizati= on information in their code before synthesization for wave-pipelining tech= nology. The responsibility of analyzing and manipulating wave-pipelining re= ady code, generating and implementing wave-pipelined circuits on a design-w= ide or chip-wide scale in HDL is shifted from designers to synthesizers. > >=20 > > Anyone who are interested in its content is welcome to send a email req= uest to the following email address: wtx wtx @ gmail . com with title "Syst= ematic" and he will receive the full documents: one specification, 9 drawin= gs and one text file in VHDL. > >=20 > > If one reviews the files and feels that it would be a good thing to rec= ommend the application to his company to buy it, the first person to do it = after his recommended company does so will receive $10,000 commission fee. >=20 > Did you ever get your patent? I'm curious.=20 >=20 > --=20 >=20 > Rick C. >=20 > -- Get a 1,000 miles of free Supercharging > -- Tesla referral code - https://ts.la/richard11209 No grant so far... From newsfish@newsfish Thu Aug 1 00:44:17 2024 X-Received: by 2002:ac8:2562:: with SMTP id 31mr1768015qtn.16.1553710318912; Wed, 27 Mar 2019 11:11:58 -0700 (PDT) X-Received: by 2002:a25:1482:: with SMTP id 124mr32409798ybu.421.1553710318634; Wed, 27 Mar 2019 11:11:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no3099422qtn.0!news-out.google.com!i54ni1267qte.0!nntp.google.com!t9no3099420qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Mar 2019 11:11:58 -0700 (PDT) In-Reply-To: <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=74.92.187.49; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 74.92.187.49 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: gnuarm.deletethisbit@gmail.com Injection-Date: Wed, 27 Mar 2019 18:11:58 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9440 On Wednesday, March 27, 2019 at 10:09:25 AM UTC-4, Benjamin Couillard wrote= : > Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a =C3=A9cri= t=C2=A0: > > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang wrot= e: > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > >=20 > > > I have filed a provisional patent application: "Systematic method of = coding wave pipelined circuits in HDL". If it is proved correct, the patent= will introduce 1 keyword, 3 permanent constants, 1 concurrent statement an= d four source code modules for a new library in HDL and thoroughly resolve = a pending problem so that every digital designer can code wave-pipelined ci= rcuits in HDL. > > >=20 > > > Here is the abstract of the invention: > > >=20 > > > The present invention classifies all critical paths into two basi= c types: a series critical path and a feedback critical path, and divides e= ach of wave-pipelined circuits into two components: a static logic part, ca= lled critical path component (CPC), and a dynamic logic part, formalized in= to four wave-pipelining components (WPC) shared by all wave-pipelined circu= its. Each wave-pipelining ready code in HDL comprises two components: a WPC= instantiation and a CPC instantiation wire-connected and linked by a new l= ink statement. Each WPC has new wave constants which play the same role as = generic constants do, but whose initial values are determined and assigned = by a synthesizer after code analysis, so designers can use after-synthesiza= tion information in their code before synthesization for wave-pipelining te= chnology. The responsibility of analyzing and manipulating wave-pipelining = ready code, generating and implementing wave-pipelined circuits on a design= -wide or chip-wide scale in HDL is shifted from designers to synthesizers. > > >=20 > > > Anyone who are interested in its content is welcome to send a email r= equest to the following email address: wtx wtx @ gmail . com with title "Sy= stematic" and he will receive the full documents: one specification, 9 draw= ings and one text file in VHDL. > > >=20 > > > If one reviews the files and feels that it would be a good thing to r= ecommend the application to his company to buy it, the first person to do i= t after his recommended company does so will receive $10,000 commission fee= . > >=20 > > Did you ever get your patent? I'm curious.=20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > -- Get a 1,000 miles of free Supercharging > > -- Tesla referral code - https://ts.la/richard11209 >=20 > No grant so far... Ok, good luck.=20 --=20 Rick C. - Get a 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:18 2024 X-Received: by 2002:a37:a256:: with SMTP id l83mr1116281qke.14.1553722144697; Wed, 27 Mar 2019 14:29:04 -0700 (PDT) X-Received: by 2002:a0d:d581:: with SMTP id x123mr32653419ywd.244.1553722144309; Wed, 27 Mar 2019 14:29:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t9no3523290qtn.0!news-out.google.com!i54ni1429qte.0!nntp.google.com!t9no3523287qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Mar 2019 14:29:04 -0700 (PDT) In-Reply-To: <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=96.21.118.168; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j NNTP-Posting-Host: 96.21.118.168 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Benjamin Couillard Injection-Date: Wed, 27 Mar 2019 21:29:04 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 65 Xref: reader01.eternal-september.org comp.lang.vhdl:9441 Le mercredi 27 mars 2019 14:12:00 UTC-4, gnuarm.de...@gmail.com a =C3=A9cri= t=C2=A0: > On Wednesday, March 27, 2019 at 10:09:25 AM UTC-4, Benjamin Couillard wro= te: > > Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a =C3=A9c= rit=C2=A0: > > > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang wr= ote: > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > >=20 > > > > I have filed a provisional patent application: "Systematic method o= f coding wave pipelined circuits in HDL". If it is proved correct, the pate= nt will introduce 1 keyword, 3 permanent constants, 1 concurrent statement = and four source code modules for a new library in HDL and thoroughly resolv= e a pending problem so that every digital designer can code wave-pipelined = circuits in HDL. > > > >=20 > > > > Here is the abstract of the invention: > > > >=20 > > > > The present invention classifies all critical paths into two ba= sic types: a series critical path and a feedback critical path, and divides= each of wave-pipelined circuits into two components: a static logic part, = called critical path component (CPC), and a dynamic logic part, formalized = into four wave-pipelining components (WPC) shared by all wave-pipelined cir= cuits. Each wave-pipelining ready code in HDL comprises two components: a W= PC instantiation and a CPC instantiation wire-connected and linked by a new= link statement. Each WPC has new wave constants which play the same role a= s generic constants do, but whose initial values are determined and assigne= d by a synthesizer after code analysis, so designers can use after-synthesi= zation information in their code before synthesization for wave-pipelining = technology. The responsibility of analyzing and manipulating wave-pipelinin= g ready code, generating and implementing wave-pipelined circuits on a desi= gn-wide or chip-wide scale in HDL is shifted from designers to synthesizers= . > > > >=20 > > > > Anyone who are interested in its content is welcome to send a email= request to the following email address: wtx wtx @ gmail . com with title "= Systematic" and he will receive the full documents: one specification, 9 dr= awings and one text file in VHDL. > > > >=20 > > > > If one reviews the files and feels that it would be a good thing to= recommend the application to his company to buy it, the first person to do= it after his recommended company does so will receive $10,000 commission f= ee. > > >=20 > > > Did you ever get your patent? I'm curious.=20 > > >=20 > > > --=20 > > >=20 > > > Rick C. > > >=20 > > > -- Get a 1,000 miles of free Supercharging > > > -- Tesla referral code - https://ts.la/richard11209 > >=20 > > No grant so far... >=20 > Ok, good luck.=20 >=20 > --=20 >=20 > Rick C. >=20 > - Get a 1,000 miles of free Supercharging > - Tesla referral code - https://ts.la/richard11209 Well I highly doubt the OP will get a grant. From newsfish@newsfish Thu Aug 1 00:44:18 2024 X-Received: by 2002:ae9:e203:: with SMTP id c3mr1226037qkc.19.1553729781718; Wed, 27 Mar 2019 16:36:21 -0700 (PDT) X-Received: by 2002:a25:42c3:: with SMTP id p186mr32568949yba.392.1553729781570; Wed, 27 Mar 2019 16:36:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!i2pn.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t9no3788221qtn.0!news-out.google.com!i54ni1523qte.0!nntp.google.com!t9no3788211qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Mar 2019 16:36:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <707673b8-d49d-40a2-b3f5-63227a506bbb@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: gnuarm.deletethisbit@gmail.com Injection-Date: Wed, 27 Mar 2019 23:36:21 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 75 Xref: reader01.eternal-september.org comp.lang.vhdl:9442 On Wednesday, March 27, 2019 at 5:29:08 PM UTC-4, Benjamin Couillard wrote: > Le mercredi 27 mars 2019 14:12:00 UTC-4, gnuarm.de...@gmail.com a =C3=A9c= rit=C2=A0: > > On Wednesday, March 27, 2019 at 10:09:25 AM UTC-4, Benjamin Couillard w= rote: > > > Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a =C3= =A9crit=C2=A0: > > > > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang = wrote: > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > >=20 > > > > > I have filed a provisional patent application: "Systematic method= of coding wave pipelined circuits in HDL". If it is proved correct, the pa= tent will introduce 1 keyword, 3 permanent constants, 1 concurrent statemen= t and four source code modules for a new library in HDL and thoroughly reso= lve a pending problem so that every digital designer can code wave-pipeline= d circuits in HDL. > > > > >=20 > > > > > Here is the abstract of the invention: > > > > >=20 > > > > > The present invention classifies all critical paths into two = basic types: a series critical path and a feedback critical path, and divid= es each of wave-pipelined circuits into two components: a static logic part= , called critical path component (CPC), and a dynamic logic part, formalize= d into four wave-pipelining components (WPC) shared by all wave-pipelined c= ircuits. Each wave-pipelining ready code in HDL comprises two components: a= WPC instantiation and a CPC instantiation wire-connected and linked by a n= ew link statement. Each WPC has new wave constants which play the same role= as generic constants do, but whose initial values are determined and assig= ned by a synthesizer after code analysis, so designers can use after-synthe= sization information in their code before synthesization for wave-pipelinin= g technology. The responsibility of analyzing and manipulating wave-pipelin= ing ready code, generating and implementing wave-pipelined circuits on a de= sign-wide or chip-wide scale in HDL is shifted from designers to synthesize= rs. > > > > >=20 > > > > > Anyone who are interested in its content is welcome to send a ema= il request to the following email address: wtx wtx @ gmail . com with title= "Systematic" and he will receive the full documents: one specification, 9 = drawings and one text file in VHDL. > > > > >=20 > > > > > If one reviews the files and feels that it would be a good thing = to recommend the application to his company to buy it, the first person to = do it after his recommended company does so will receive $10,000 commission= fee. > > > >=20 > > > > Did you ever get your patent? I'm curious.=20 > > > >=20 > > > > --=20 > > > >=20 > > > > Rick C. > > > >=20 > > > > -- Get a 1,000 miles of free Supercharging > > > > -- Tesla referral code - https://ts.la/richard11209 > > >=20 > > > No grant so far... > >=20 > > Ok, good luck.=20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > - Get a 1,000 miles of free Supercharging > > - Tesla referral code - https://ts.la/richard11209 >=20 > Well I highly doubt the OP will get a grant. Don't know. I would like to see the application. =20 --=20 Rick C. + Get a 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:18 2024 X-Received: by 2002:a0c:d0ef:: with SMTP id b44mr2288423qvh.61.1553762709986; Thu, 28 Mar 2019 01:45:09 -0700 (PDT) X-Received: by 2002:a81:2e0e:: with SMTP id u14mr33943761ywu.323.1553762709743; Thu, 28 Mar 2019 01:45:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder7.news.weretis.net!3.eu.feeder.erje.net!feeder.erje.net!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no4699750qtn.0!news-out.google.com!d8ni1072qtr.1!nntp.google.com!t9no4699743qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Mar 2019 01:45:09 -0700 (PDT) In-Reply-To: <6ilpm3$5jj$1@goanna.cs.rmit.edu.au>#1/1> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=160.89.3.9; posting-account=u9d59QoAAABHxzXRfdAFSVmNiaKxH4L0 NNTP-Posting-Host: 160.89.3.9 References: <6ilpm3$5jj$1@goanna.cs.rmit.edu.au>#1/1> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d69638c-3d0a-498b-aea8-3d8c446ba6c8@googlegroups.com> Subject: CRC-16 VHDL From: hamzaelaloui@gmail.com Injection-Date: Thu, 28 Mar 2019 08:45:09 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9443 Can you give me any links for the vhdl code of crc 16 of 32 bits . Im stuck . And its also urgents can u help me out . Please. From newsfish@newsfish Thu Aug 1 00:44:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!buffer2.nntp.dca1.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Thu, 28 Mar 2019 04:50:21 -0500 From: Allan Herriman Subject: Re: CRC-16 VHDL Newsgroups: comp.lang.vhdl References: <6ilpm3$5jj$1@goanna.cs.rmit.edu.au> <7d69638c-3d0a-498b-aea8-3d8c446ba6c8@googlegroups.com> User-Agent: Pan/0.146 (Hic habitat felicitas; edad96d github.com/GNOME/pan.git) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Thu, 28 Mar 2019 04:50:22 -0500 Lines: 14 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 118.209.198.67 X-Trace: sv3-a7NDHvlL9lDlg908NnVM+Zsq4JqoGcOw/36DdUZst2WZ/XSYNpCJ6iFqmOPtMVHOOfnkWndI5diJjMG!SBiwtetYO5hTSYpFaMLcandNd6fhh/YsslsYTQZf9qPCTBnATZtuWVhJ3eN262yVie692X1fY+Bl!ZbdMk9LxCK3/pdHB51/csQ== X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1568 Xref: reader01.eternal-september.org comp.lang.vhdl:9444 On Thu, 28 Mar 2019 01:45:09 -0700, hamzaelaloui wrote: > Can you give me any links for the vhdl code of crc 16 of 32 bits . Im > stuck . And its also urgents can u help me out . Please. There's an online code generator here: https://www.easics.com/webtools/crctool You will need to know the polynomial. "crc 16" is ambiguous, as there are several 16 bit CRC polynomials in common use. Regards, Allan From newsfish@newsfish Thu Aug 1 00:44:19 2024 X-Received: by 2002:ae9:e849:: with SMTP id a70mr2461073qkg.34.1553775035581; Thu, 28 Mar 2019 05:10:35 -0700 (PDT) X-Received: by 2002:a25:6004:: with SMTP id u4mr36194846ybb.149.1553775035217; Thu, 28 Mar 2019 05:10:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no5064017qtn.0!news-out.google.com!i54ni2180qte.0!nntp.google.com!t9no5064012qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Mar 2019 05:10:34 -0700 (PDT) In-Reply-To: <707673b8-d49d-40a2-b3f5-63227a506bbb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=96.21.118.168; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j NNTP-Posting-Host: 96.21.118.168 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> <707673b8-d49d-40a2-b3f5-63227a506bbb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Benjamin Couillard Injection-Date: Thu, 28 Mar 2019 12:10:35 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9445 Le mercredi 27 mars 2019 19:36:23 UTC-4, gnuarm.de...@gmail.com a =C3=A9cri= t=C2=A0: > On Wednesday, March 27, 2019 at 5:29:08 PM UTC-4, Benjamin Couillard wrot= e: > > Le mercredi 27 mars 2019 14:12:00 UTC-4, gnuarm.de...@gmail.com a =C3= =A9crit=C2=A0: > > > On Wednesday, March 27, 2019 at 10:09:25 AM UTC-4, Benjamin Couillard= wrote: > > > > Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a =C3= =A9crit=C2=A0: > > > > > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxian= g wrote: > > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > > >=20 > > > > > > I have filed a provisional patent application: "Systematic meth= od of coding wave pipelined circuits in HDL". If it is proved correct, the = patent will introduce 1 keyword, 3 permanent constants, 1 concurrent statem= ent and four source code modules for a new library in HDL and thoroughly re= solve a pending problem so that every digital designer can code wave-pipeli= ned circuits in HDL. > > > > > >=20 > > > > > > Here is the abstract of the invention: > > > > > >=20 > > > > > > The present invention classifies all critical paths into tw= o basic types: a series critical path and a feedback critical path, and div= ides each of wave-pipelined circuits into two components: a static logic pa= rt, called critical path component (CPC), and a dynamic logic part, formali= zed into four wave-pipelining components (WPC) shared by all wave-pipelined= circuits. Each wave-pipelining ready code in HDL comprises two components:= a WPC instantiation and a CPC instantiation wire-connected and linked by a= new link statement. Each WPC has new wave constants which play the same ro= le as generic constants do, but whose initial values are determined and ass= igned by a synthesizer after code analysis, so designers can use after-synt= hesization information in their code before synthesization for wave-pipelin= ing technology. The responsibility of analyzing and manipulating wave-pipel= ining ready code, generating and implementing wave-pipelined circuits on a = design-wide or chip-wide scale in HDL is shifted from designers to synthesi= zers. > > > > > >=20 > > > > > > Anyone who are interested in its content is welcome to send a e= mail request to the following email address: wtx wtx @ gmail . com with tit= le "Systematic" and he will receive the full documents: one specification, = 9 drawings and one text file in VHDL. > > > > > >=20 > > > > > > If one reviews the files and feels that it would be a good thin= g to recommend the application to his company to buy it, the first person t= o do it after his recommended company does so will receive $10,000 commissi= on fee. > > > > >=20 > > > > > Did you ever get your patent? I'm curious.=20 > > > > >=20 > > > > > --=20 > > > > >=20 > > > > > Rick C. > > > > >=20 > > > > > -- Get a 1,000 miles of free Supercharging > > > > > -- Tesla referral code - https://ts.la/richard11209 > > > >=20 > > > > No grant so far... > > >=20 > > > Ok, good luck.=20 > > >=20 > > > --=20 > > >=20 > > > Rick C. > > >=20 > > > - Get a 1,000 miles of free Supercharging > > > - Tesla referral code - https://ts.la/richard11209 > >=20 > > Well I highly doubt the OP will get a grant. >=20 > Don't know. I would like to see the application. =20 >=20 > --=20 >=20 > Rick C. >=20 > + Get a 1,000 miles of free Supercharging > + Tesla referral code - https://ts.la/richard11209 https://patents.google.com/patent/US9747252B2/en From newsfish@newsfish Thu Aug 1 00:44:19 2024 X-Received: by 2002:ac8:2dcf:: with SMTP id q15mr2674871qta.2.1553775195726; Thu, 28 Mar 2019 05:13:15 -0700 (PDT) X-Received: by 2002:a25:2108:: with SMTP id h8mr10078652ybh.330.1553775195493; Thu, 28 Mar 2019 05:13:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t9no5068744qtn.0!news-out.google.com!i54ni2180qte.0!nntp.google.com!t9no5068737qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Mar 2019 05:13:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=96.21.118.168; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j NNTP-Posting-Host: 96.21.118.168 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> <707673b8-d49d-40a2-b3f5-63227a506bbb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12ba17f3-8a9a-4a80-8b36-f332bbf32f34@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Benjamin Couillard Injection-Date: Thu, 28 Mar 2019 12:13:15 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 85 Xref: reader01.eternal-september.org comp.lang.vhdl:9446 Le jeudi 28 mars 2019 08:10:38 UTC-4, Benjamin Couillard a =C3=A9crit=C2=A0= : > Le mercredi 27 mars 2019 19:36:23 UTC-4, gnuarm.de...@gmail.com a =C3=A9c= rit=C2=A0: > > On Wednesday, March 27, 2019 at 5:29:08 PM UTC-4, Benjamin Couillard wr= ote: > > > Le mercredi 27 mars 2019 14:12:00 UTC-4, gnuarm.de...@gmail.com a =C3= =A9crit=C2=A0: > > > > On Wednesday, March 27, 2019 at 10:09:25 AM UTC-4, Benjamin Couilla= rd wrote: > > > > > Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a = =C3=A9crit=C2=A0: > > > > > > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxi= ang wrote: > > > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > > > >=20 > > > > > > > I have filed a provisional patent application: "Systematic me= thod of coding wave pipelined circuits in HDL". If it is proved correct, th= e patent will introduce 1 keyword, 3 permanent constants, 1 concurrent stat= ement and four source code modules for a new library in HDL and thoroughly = resolve a pending problem so that every digital designer can code wave-pipe= lined circuits in HDL. > > > > > > >=20 > > > > > > > Here is the abstract of the invention: > > > > > > >=20 > > > > > > > The present invention classifies all critical paths into = two basic types: a series critical path and a feedback critical path, and d= ivides each of wave-pipelined circuits into two components: a static logic = part, called critical path component (CPC), and a dynamic logic part, forma= lized into four wave-pipelining components (WPC) shared by all wave-pipelin= ed circuits. Each wave-pipelining ready code in HDL comprises two component= s: a WPC instantiation and a CPC instantiation wire-connected and linked by= a new link statement. Each WPC has new wave constants which play the same = role as generic constants do, but whose initial values are determined and a= ssigned by a synthesizer after code analysis, so designers can use after-sy= nthesization information in their code before synthesization for wave-pipel= ining technology. The responsibility of analyzing and manipulating wave-pip= elining ready code, generating and implementing wave-pipelined circuits on = a design-wide or chip-wide scale in HDL is shifted from designers to synthe= sizers. > > > > > > >=20 > > > > > > > Anyone who are interested in its content is welcome to send a= email request to the following email address: wtx wtx @ gmail . com with t= itle "Systematic" and he will receive the full documents: one specification= , 9 drawings and one text file in VHDL. > > > > > > >=20 > > > > > > > If one reviews the files and feels that it would be a good th= ing to recommend the application to his company to buy it, the first person= to do it after his recommended company does so will receive $10,000 commis= sion fee. > > > > > >=20 > > > > > > Did you ever get your patent? I'm curious.=20 > > > > > >=20 > > > > > > --=20 > > > > > >=20 > > > > > > Rick C. > > > > > >=20 > > > > > > -- Get a 1,000 miles of free Supercharging > > > > > > -- Tesla referral code - https://ts.la/richard11209 > > > > >=20 > > > > > No grant so far... > > > >=20 > > > > Ok, good luck.=20 > > > >=20 > > > > --=20 > > > >=20 > > > > Rick C. > > > >=20 > > > > - Get a 1,000 miles of free Supercharging > > > > - Tesla referral code - https://ts.la/richard11209 > > >=20 > > > Well I highly doubt the OP will get a grant. > >=20 > > Don't know. I would like to see the application. =20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > + Get a 1,000 miles of free Supercharging > > + Tesla referral code - https://ts.la/richard11209 >=20 > https://patents.google.com/patent/US9747252B2/en My bad, apparently he did get his patent accepted if I understandarc correc= tly... From newsfish@newsfish Thu Aug 1 00:44:20 2024 X-Received: by 2002:ac8:21f2:: with SMTP id 47mr2765468qtz.9.1553780824716; Thu, 28 Mar 2019 06:47:04 -0700 (PDT) X-Received: by 2002:a0d:d548:: with SMTP id x69mr35040457ywd.291.1553780824551; Thu, 28 Mar 2019 06:47:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t9no5235792qtn.0!news-out.google.com!d8ni1214qtr.1!nntp.google.com!t9no5235788qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Mar 2019 06:47:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> <707673b8-d49d-40a2-b3f5-63227a506bbb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2baded37-c401-42db-b0f0-67201e0e503e@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: gnuarm.deletethisbit@gmail.com Injection-Date: Thu, 28 Mar 2019 13:47:04 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 94 Xref: reader01.eternal-september.org comp.lang.vhdl:9447 On Thursday, March 28, 2019 at 8:10:38 AM UTC-4, Benjamin Couillard wrote: > Le mercredi 27 mars 2019 19:36:23 UTC-4, gnuarm.de...@gmail.com a =C3=A9c= rit=C2=A0: > > On Wednesday, March 27, 2019 at 5:29:08 PM UTC-4, Benjamin Couillard wr= ote: > > > Le mercredi 27 mars 2019 14:12:00 UTC-4, gnuarm.de...@gmail.com a =C3= =A9crit=C2=A0: > > > > On Wednesday, March 27, 2019 at 10:09:25 AM UTC-4, Benjamin Couilla= rd wrote: > > > > > Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a = =C3=A9crit=C2=A0: > > > > > > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxi= ang wrote: > > > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > > > >=20 > > > > > > > I have filed a provisional patent application: "Systematic me= thod of coding wave pipelined circuits in HDL". If it is proved correct, th= e patent will introduce 1 keyword, 3 permanent constants, 1 concurrent stat= ement and four source code modules for a new library in HDL and thoroughly = resolve a pending problem so that every digital designer can code wave-pipe= lined circuits in HDL. > > > > > > >=20 > > > > > > > Here is the abstract of the invention: > > > > > > >=20 > > > > > > > The present invention classifies all critical paths into = two basic types: a series critical path and a feedback critical path, and d= ivides each of wave-pipelined circuits into two components: a static logic = part, called critical path component (CPC), and a dynamic logic part, forma= lized into four wave-pipelining components (WPC) shared by all wave-pipelin= ed circuits. Each wave-pipelining ready code in HDL comprises two component= s: a WPC instantiation and a CPC instantiation wire-connected and linked by= a new link statement. Each WPC has new wave constants which play the same = role as generic constants do, but whose initial values are determined and a= ssigned by a synthesizer after code analysis, so designers can use after-sy= nthesization information in their code before synthesization for wave-pipel= ining technology. The responsibility of analyzing and manipulating wave-pip= elining ready code, generating and implementing wave-pipelined circuits on = a design-wide or chip-wide scale in HDL is shifted from designers to synthe= sizers. > > > > > > >=20 > > > > > > > Anyone who are interested in its content is welcome to send a= email request to the following email address: wtx wtx @ gmail . com with t= itle "Systematic" and he will receive the full documents: one specification= , 9 drawings and one text file in VHDL. > > > > > > >=20 > > > > > > > If one reviews the files and feels that it would be a good th= ing to recommend the application to his company to buy it, the first person= to do it after his recommended company does so will receive $10,000 commis= sion fee. > > > > > >=20 > > > > > > Did you ever get your patent? I'm curious.=20 > > > > > >=20 > > > > > > --=20 > > > > > >=20 > > > > > > Rick C. > > > > > >=20 > > > > > > -- Get a 1,000 miles of free Supercharging > > > > > > -- Tesla referral code - https://ts.la/richard11209 > > > > >=20 > > > > > No grant so far... > > > >=20 > > > > Ok, good luck.=20 > > > >=20 > > > > --=20 > > > >=20 > > > > Rick C. > > > >=20 > > > > - Get a 1,000 miles of free Supercharging > > > > - Tesla referral code - https://ts.la/richard11209 > > >=20 > > > Well I highly doubt the OP will get a grant. > >=20 > > Don't know. I would like to see the application. =20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > + Get a 1,000 miles of free Supercharging > > + Tesla referral code - https://ts.la/richard11209 >=20 > https://patents.google.com/patent/US9747252B2/en When I replied I didn't notice you weren't him. =20 Looks like he got two on this topic.=20 https://patents.google.com/patent/US9575929B2/en --=20 Rick C. -+ Get a 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:20 2024 X-Received: by 2002:a0c:d928:: with SMTP id p37mr2730486qvj.40.1553784679394; Thu, 28 Mar 2019 07:51:19 -0700 (PDT) X-Received: by 2002:a25:ad93:: with SMTP id z19mr35089594ybi.393.1553784679046; Thu, 28 Mar 2019 07:51:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t9no5349087qtn.0!news-out.google.com!i54ni2319qte.0!nntp.google.com!t9no5349080qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Mar 2019 07:51:18 -0700 (PDT) In-Reply-To: <2baded37-c401-42db-b0f0-67201e0e503e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.37.123.58; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j NNTP-Posting-Host: 24.37.123.58 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> <707673b8-d49d-40a2-b3f5-63227a506bbb@googlegroups.com> <2baded37-c401-42db-b0f0-67201e0e503e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Benjamin Couillard Injection-Date: Thu, 28 Mar 2019 14:51:19 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 102 Xref: reader01.eternal-september.org comp.lang.vhdl:9448 Le jeudi 28 mars 2019 09:47:06 UTC-4, gnuarm.de...@gmail.com a =C3=A9crit= =C2=A0: > On Thursday, March 28, 2019 at 8:10:38 AM UTC-4, Benjamin Couillard wrote= : > > Le mercredi 27 mars 2019 19:36:23 UTC-4, gnuarm.de...@gmail.com a =C3= =A9crit=C2=A0: > > > On Wednesday, March 27, 2019 at 5:29:08 PM UTC-4, Benjamin Couillard = wrote: > > > > Le mercredi 27 mars 2019 14:12:00 UTC-4, gnuarm.de...@gmail.com a = =C3=A9crit=C2=A0: > > > > > On Wednesday, March 27, 2019 at 10:09:25 AM UTC-4, Benjamin Couil= lard wrote: > > > > > > Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com a= =C3=A9crit=C2=A0: > > > > > > > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tian= xiang wrote: > > > > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > > > > >=20 > > > > > > > > I have filed a provisional patent application: "Systematic = method of coding wave pipelined circuits in HDL". If it is proved correct, = the patent will introduce 1 keyword, 3 permanent constants, 1 concurrent st= atement and four source code modules for a new library in HDL and thoroughl= y resolve a pending problem so that every digital designer can code wave-pi= pelined circuits in HDL. > > > > > > > >=20 > > > > > > > > Here is the abstract of the invention: > > > > > > > >=20 > > > > > > > > The present invention classifies all critical paths int= o two basic types: a series critical path and a feedback critical path, and= divides each of wave-pipelined circuits into two components: a static logi= c part, called critical path component (CPC), and a dynamic logic part, for= malized into four wave-pipelining components (WPC) shared by all wave-pipel= ined circuits. Each wave-pipelining ready code in HDL comprises two compone= nts: a WPC instantiation and a CPC instantiation wire-connected and linked = by a new link statement. Each WPC has new wave constants which play the sam= e role as generic constants do, but whose initial values are determined and= assigned by a synthesizer after code analysis, so designers can use after-= synthesization information in their code before synthesization for wave-pip= elining technology. The responsibility of analyzing and manipulating wave-p= ipelining ready code, generating and implementing wave-pipelined circuits o= n a design-wide or chip-wide scale in HDL is shifted from designers to synt= hesizers. > > > > > > > >=20 > > > > > > > > Anyone who are interested in its content is welcome to send= a email request to the following email address: wtx wtx @ gmail . com with= title "Systematic" and he will receive the full documents: one specificati= on, 9 drawings and one text file in VHDL. > > > > > > > >=20 > > > > > > > > If one reviews the files and feels that it would be a good = thing to recommend the application to his company to buy it, the first pers= on to do it after his recommended company does so will receive $10,000 comm= ission fee. > > > > > > >=20 > > > > > > > Did you ever get your patent? I'm curious.=20 > > > > > > >=20 > > > > > > > --=20 > > > > > > >=20 > > > > > > > Rick C. > > > > > > >=20 > > > > > > > -- Get a 1,000 miles of free Supercharging > > > > > > > -- Tesla referral code - https://ts.la/richard11209 > > > > > >=20 > > > > > > No grant so far... > > > > >=20 > > > > > Ok, good luck.=20 > > > > >=20 > > > > > --=20 > > > > >=20 > > > > > Rick C. > > > > >=20 > > > > > - Get a 1,000 miles of free Supercharging > > > > > - Tesla referral code - https://ts.la/richard11209 > > > >=20 > > > > Well I highly doubt the OP will get a grant. > > >=20 > > > Don't know. I would like to see the application. =20 > > >=20 > > > --=20 > > >=20 > > > Rick C. > > >=20 > > > + Get a 1,000 miles of free Supercharging > > > + Tesla referral code - https://ts.la/richard11209 > >=20 > > https://patents.google.com/patent/US9747252B2/en >=20 > When I replied I didn't notice you weren't him. =20 >=20 > Looks like he got two on this topic.=20 >=20 > https://patents.google.com/patent/US9575929B2/en >=20 > --=20 >=20 > Rick C. >=20 > -+ Get a 1,000 miles of free Supercharging > -+ Tesla referral code - https://ts.la/richard11209 But then again, someone got a patent for a combover... Not every patent is = worth something https://patents.google.com/patent/US4022227A/en From newsfish@newsfish Thu Aug 1 00:44:20 2024 X-Received: by 2002:a0c:d928:: with SMTP id p37mr2754374qvj.40.1553785948891; Thu, 28 Mar 2019 08:12:28 -0700 (PDT) X-Received: by 2002:a25:9a41:: with SMTP id r1mr33585215ybo.295.1553785948730; Thu, 28 Mar 2019 08:12:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t9no5387722qtn.0!news-out.google.com!i54ni2358qte.0!nntp.google.com!t9no5387721qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Mar 2019 08:12:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> <707673b8-d49d-40a2-b3f5-63227a506bbb@googlegroups.com> <2baded37-c401-42db-b0f0-67201e0e503e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: gnuarm.deletethisbit@gmail.com Injection-Date: Thu, 28 Mar 2019 15:12:28 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 116 Xref: reader01.eternal-september.org comp.lang.vhdl:9449 On Thursday, March 28, 2019 at 10:51:21 AM UTC-4, Benjamin Couillard wrote: > Le jeudi 28 mars 2019 09:47:06 UTC-4, gnuarm.de...@gmail.com a =C3=A9crit= =C2=A0: > > On Thursday, March 28, 2019 at 8:10:38 AM UTC-4, Benjamin Couillard wro= te: > > > Le mercredi 27 mars 2019 19:36:23 UTC-4, gnuarm.de...@gmail.com a =C3= =A9crit=C2=A0: > > > > On Wednesday, March 27, 2019 at 5:29:08 PM UTC-4, Benjamin Couillar= d wrote: > > > > > Le mercredi 27 mars 2019 14:12:00 UTC-4, gnuarm.de...@gmail.com a= =C3=A9crit=C2=A0: > > > > > > On Wednesday, March 27, 2019 at 10:09:25 AM UTC-4, Benjamin Cou= illard wrote: > > > > > > > Le lundi 25 mars 2019 18:29:39 UTC-4, gnuarm.del...@gmail.com= a =C3=A9crit=C2=A0: > > > > > > > > On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Ti= anxiang wrote: > > > > > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > > > > > >=20 > > > > > > > > > I have filed a provisional patent application: "Systemati= c method of coding wave pipelined circuits in HDL". If it is proved correct= , the patent will introduce 1 keyword, 3 permanent constants, 1 concurrent = statement and four source code modules for a new library in HDL and thoroug= hly resolve a pending problem so that every digital designer can code wave-= pipelined circuits in HDL. > > > > > > > > >=20 > > > > > > > > > Here is the abstract of the invention: > > > > > > > > >=20 > > > > > > > > > The present invention classifies all critical paths i= nto two basic types: a series critical path and a feedback critical path, a= nd divides each of wave-pipelined circuits into two components: a static lo= gic part, called critical path component (CPC), and a dynamic logic part, f= ormalized into four wave-pipelining components (WPC) shared by all wave-pip= elined circuits. Each wave-pipelining ready code in HDL comprises two compo= nents: a WPC instantiation and a CPC instantiation wire-connected and linke= d by a new link statement. Each WPC has new wave constants which play the s= ame role as generic constants do, but whose initial values are determined a= nd assigned by a synthesizer after code analysis, so designers can use afte= r-synthesization information in their code before synthesization for wave-p= ipelining technology. The responsibility of analyzing and manipulating wave= -pipelining ready code, generating and implementing wave-pipelined circuits= on a design-wide or chip-wide scale in HDL is shifted from designers to sy= nthesizers. > > > > > > > > >=20 > > > > > > > > > Anyone who are interested in its content is welcome to se= nd a email request to the following email address: wtx wtx @ gmail . com wi= th title "Systematic" and he will receive the full documents: one specifica= tion, 9 drawings and one text file in VHDL. > > > > > > > > >=20 > > > > > > > > > If one reviews the files and feels that it would be a goo= d thing to recommend the application to his company to buy it, the first pe= rson to do it after his recommended company does so will receive $10,000 co= mmission fee. > > > > > > > >=20 > > > > > > > > Did you ever get your patent? I'm curious.=20 > > > > > > > >=20 > > > > > > > > --=20 > > > > > > > >=20 > > > > > > > > Rick C. > > > > > > > >=20 > > > > > > > > -- Get a 1,000 miles of free Supercharging > > > > > > > > -- Tesla referral code - https://ts.la/richard11209 > > > > > > >=20 > > > > > > > No grant so far... > > > > > >=20 > > > > > > Ok, good luck.=20 > > > > > >=20 > > > > > > --=20 > > > > > >=20 > > > > > > Rick C. > > > > > >=20 > > > > > > - Get a 1,000 miles of free Supercharging > > > > > > - Tesla referral code - https://ts.la/richard11209 > > > > >=20 > > > > > Well I highly doubt the OP will get a grant. > > > >=20 > > > > Don't know. I would like to see the application. =20 > > > >=20 > > > > --=20 > > > >=20 > > > > Rick C. > > > >=20 > > > > + Get a 1,000 miles of free Supercharging > > > > + Tesla referral code - https://ts.la/richard11209 > > >=20 > > > https://patents.google.com/patent/US9747252B2/en > >=20 > > When I replied I didn't notice you weren't him. =20 > >=20 > > Looks like he got two on this topic.=20 > >=20 > > https://patents.google.com/patent/US9575929B2/en > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > -+ Get a 1,000 miles of free Supercharging > > -+ Tesla referral code - https://ts.la/richard11209 >=20 > But then again, someone got a patent for a combover... Not every patent i= s worth something >=20 > https://patents.google.com/patent/US4022227A/en I won't argue that. I really never saw the utility of his patent or even t= hat it described anything "novel". He sort of said wave pipelined circuits= need these basic tools and someone needs to provide them. All the while n= ot actually appreciating nuance of what has to be done to make them work.= =20 --=20 Rick C. +- Get a 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:20 2024 X-Received: by 2002:ac8:3f5c:: with SMTP id w28mr3634760qtk.25.1553857482350; Fri, 29 Mar 2019 04:04:42 -0700 (PDT) X-Received: by 2002:a81:2e0e:: with SMTP id u14mr39098536ywu.323.1553857482155; Fri, 29 Mar 2019 04:04:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no1297561qtn.0!news-out.google.com!i54ni874qte.0!nntp.google.com!t9no1297551qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 29 Mar 2019 04:04:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2600:1700:d660:9640:5829:c410:306a:5482; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:5829:c410:306a:5482 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <5040e976-d717-431f-a840-ae150f559315@googlegroups.com> <9bf81cb4-dda0-4da2-8f86-a4f010102aed@googlegroups.com> <707673b8-d49d-40a2-b3f5-63227a506bbb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94d69ed0-741c-4114-8fc7-5db52258d328@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Fri, 29 Mar 2019 11:04:42 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9450 On Thursday, March 28, 2019 at 8:10:38 AM UTC-4, Benjamin Couillard wrote: >=20 > https://patents.google.com/patent/US9747252B2/en Weng apparently doesn't understand how standards committees work. He state= s "What the present invention hopes to do is: Invent a wave-pipelining cod= ing system as new part of HDL standards...", but standards organizations ar= e not going to accept patented info to put it into a standard since the pat= ent holder can then claim infringement by any user. If he plans to 'donate= ' the patent so that the standard organization could use it, then he could = have simply published it and put it into the public domain that way...he di= dn't. Now with the patent, he will need to submit a 'Letter of Assurance' = to the standards committees to move it forward [1]. But he does have a plan, coercion. He states "If the coding system becomes= new part of HDL standards all synthesizer manufactures will automatically = be forced to implement..." But maybe he has no particular time frame in mind. In 20 years when the pa= tent is no longer valid, the HDL standards could decide to pick it up. Ten= years later the HDL standard gets updated [2], [3], [4], and another ten y= ears later the synthesis vendors pick it up and incorporate it. Given that= time frame, I'm probably not the only one who could reasonably state "That= will happen over my dead body". If the plan is to get it into the HDL standards, then it would not seem lik= ely that anyone would license the technology from him so there is no patent= revenue to be expected...not the best business plan. As for what the patent says technically, well that is suspect as well based= on what he put out in this group earlier but I haven't reviewed the actual= patent enough at this point. Kevin Jennings [1] https://standards.ieee.org/about/policies/bylaws/sect6-7.html [2] The last VHDL update was 11 years ago in 2008. [3] The group that is putting together the next revision has been going at = it for about eight years now and is still not 'done'. They are in the ball= oting stage but have been so for quite a while. [4] The Twiki site for the proposed new standard labels it as "VHDL-2017", = so it's already two years old and has yet to hit the bookshelves (http://ww= w.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome) From newsfish@newsfish Thu Aug 1 00:44:21 2024 X-Received: by 2002:ac8:32ae:: with SMTP id z43mr4149527qta.61.1553882116974; Fri, 29 Mar 2019 10:55:16 -0700 (PDT) X-Received: by 2002:a0d:ffc5:: with SMTP id p188mr43728045ywf.40.1553882116681; Fri, 29 Mar 2019 10:55:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.alt.net!border1.nntp.dca1.giganews.com!nntp.giganews.com!t9no1827775qtn.0!news-out.google.com!i8ni174qtr.1!nntp.google.com!t9no1827768qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 29 Mar 2019 10:55:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.155.111.22; posting-account=0ftbrwoAAABgkmUtBTIQDVJV5vsKSrf3 NNTP-Posting-Host: 82.155.111.22 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <48a6cc69-9a7a-4e0c-bbe7-630da786f8fb@googlegroups.com> Subject: E' REGISTA PERICOLOSISSIMAMENTE PEDOFILO: GIUSEPPE LAZZARI ( FINITO IN CARCERE PER QUESTO https://brescia.corriere.it/notizie/cronaca/16_agosto_11/pedofilia-arrestato-regista-bresciano-giuseppe-lazzari-5e4ca24a-5fb2-11e6-bfed-33aa6b5e1635_amp.html ). From: "LUIGI BISIGNANI- MAI PIU' COL PEDOFILO BERLUSCONI" Injection-Date: Fri, 29 Mar 2019 17:55:16 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 471 Xref: reader01.eternal-september.org comp.lang.vhdl:9451 E' REGISTA PERICOLOSISSIMAMENTE PEDOFILO: GIUSEPPE LAZZARI ( FINITO IN CARC= ERE PER QUESTO https://brescia.corriere.it/notizie/cronaca/16_agosto_11/ped= ofilia-arrestato-regista-bresciano-giuseppe-lazzari-5e4ca24a-5fb2-11e6-bfed= -33aa6b5e1635_amp.html ). FA PARTE DI UNA SETTA SATANISTA MOLTISSIMO ASSASSINA. CON DENTRO I PARI SAT= ANISTI STUPRA ED AMMAZZA BAMBINI: DANIELE MINOTTI, GIULIANO FERRARA, ANSELM= A DELL'OLIO, CLAUDIO CERASA..........MARIO GIORDANO, MAURIZIO COSTANZO, GIA= NFRANCO SCANCARELLO, PAOLO BARRAI, ENNIO DORIS, MASSIMO DORIS, FEDELE CONFA= LONIERI, YVES CONFALONIERI, PIERSILVIO BERLUSCONI, LUIGI BERLUSCONI, MARINA= BERLUSCONI E TANTI ALTRI VERMI DI CUI SCRIVO QUI. OVVIAMENTE, COL TUTTO DI= RETTO DAL: ^PEDOFILO SATANISTA MAXIMO^ SILVIO BERLUSCONI! ED A PROPOSITO DEL PIU' SATANISTA ASSASSINO DI TUTTI QUESTI: IL SANGUINARIO= PAZZO, MEGA COCAINOMANE, INCULA, SGOZZA, SVENTRA, AMMAZZA E SOTTERRA BAMBI= NI, AVVOCATO NAZISTA, RICICLA SOLDI MAFIOSI, MEGA OMICIDA E SUPER SATANISTA= DI RAPALLO E GENOVA... STATE ALLA LARGHISSIMA DALL 'AVVOCATO SATANISTA, NAZISTA, PEDOFILO ED ASSAS= SINO: DANIELE MINOTTI! STATE ALLA LARGHISSIMA DALL ' AVVOCATO ^SATA-N-AZIST= A^, PEDERASTA ED OMICIDA DANIELE MINOTTI DI GENOVA, RAPALLO E SANTA MARGHER= ITA LIGURE (A DIRE "FURBASTRO" DI SUO FACEBOOK ACCOUNT)! VERME RAZZISTA, KU= KLUK KLANISTA, MEGA RICICLA SOLDI MAFIOSI! AGENTE SEGRETO IN COPERTO DI TI= PO HITLERIANO ED ASSASSINO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi FINO A POCO FA..SGOZZAVA OLTRE CHE BAMBINI SU BAMBINI, ANCHE, CANI, GATTI E= SERPENTI IN RITI SATANICI DI TUTTA LIGURIA E PIEMONTE ( COME DA QUESTI LIN= KS... I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTISSIMAMENTE = AMMAZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, P= OPRIO DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS RIPORTAN= TI EFFFERATI OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO! Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Fax +39 010 91 63 11 54 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA MASSONE NEOPIDUISTA LAVA CASH MAFIOSO! AGENTE SEGRETO DI TIPO OMICIDA! NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE ASSASSINO= DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDARE OVVI MESSAGGI= SATANISTI, SANGUINARI, KILLER https://www.flickr.com/photos/danieleminotti/ ). A CAPO, ANZI, A KAPO' DI SETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA = ASSASSINA CHIAMATA " AMMAZZIAMO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCO= NI". E' AVVOCATO PEDERASTA ED OMICIDA INCULA ED AMMAZZA BAMBINI: DANIELE MI= NOTTI DI GENOVA E RAPALLO. http://www.forum.domki.net/viewtopic.php?f=3D3&t=3D29723 UNITO IN CIO' AI DEPRAVATISSIMI SATANISTI, NAZISTI, CORROTTI E MEGA COCAINO= MANI MARIO GIORDANO, GIULIANO FERRARA ED ANSELMA DEL'OLIO ( " PAZZI MA NON = SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTATO REGISTA MOLTO MA MOLTO PEDO= FILO GIUSEPPE LAZZARI https://brescia.corriere.it/notizie/cronaca/16_agosto_09/sesso-un-11enne-ar= restato-regista-giuseppe-lazzari-5ff89ba8-5e3b-11e6-bfed-33aa6b5e1635_amp.h= tml ( CHE, COME VEDETE DA QUESTO VIDEO, NON PER NIENTE, E' PAPPA E CICCIA CON L= A PARI PEDOFILONA STUPRA NEONATI E BAMBINI ANSELMA DELL'OLIO STESSA https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). IL TUTTO INSIEME ANCHE AL = TRE VOLTE FINITO IN GALERA PAOLO BARRAI DI CRIMINALISSIMA CRYPTOPOLYS, CRIM= INALISSIMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "M= ERDATO" LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL= PEDOFILO DEL BITCOIN" https://in.memory.of.e.tern.al/it.politica/thread/42= 89803 ). ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l E POI ANCORA http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l https://www.ariannaeditrice.it/articolo.php?id_articolo=3D6352ED ). MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg https://www.money.it/IMG/arton21812.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND P= ARTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) https://www.py.cz/pipermail/python/2017-September/013036.html UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERO= NE, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi https://www.facebook.com/Rocco-Tripodi-1537588826544365/ PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A } TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/wp-content/themes/eidoo_v2/images/team/natale_ferrara.jpg AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://scontent-lga3-1.cdninstagram.com/vp/8ada8bd86f0b32fe9cb4010d3618789= 2/5D198BD4/t51.2885-19/s150x150/37978940_714225998926422_798256038308688691= 2_n.jpg?_nc_ht=3Dscontent-lga3-1.cdninstagram.com&se=3D8 E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPARMI DI TUTTI: FEDERICO IZZI "TRADER" DETTO "ZIO ROMOLO https://in.memory.of.e.tern.al/comp.lang.scheme/thread/4226205#4226205 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI BANCA IFIGEST MILANO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 https://groups.google.com/forum/#!topic/it.hobby.fai-da-te/V_4dMdeCZQA PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue= -di-chi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-in= dipendente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE =E2=80=9CPEDOFILESCO-MEDIATICHE=E2=80=9D, NEGLI = ULTIMI ANNI, TIPO QUESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E MANCO TANTO SOTTILISSIMAMENTE, LO STESSO SEMPR= E DIFENDE I PEDOFILI: OVVIO, E' UN VERME ASSASSINO E SODOMIZZA BAMBINI, LUI= IN PRIMO)!! E' SUA LA SETTA DI SATANISTI STUPRA BIMBI CON DENTRO IL REGISTA, ACCLARATIS= SIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) https://www.nextquotidiano.it/giuseppe-lazzari-regista-accusato-pedofilia/ LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/= giuliano-ferrara-omosessualita-giochetto-consiglio-contro-natura-1483446/ )= ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO. GUARDATE VOI STESSI CH= E PEDOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI= DANIELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, = BAMBINI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI= DI MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERL= USCONIA") !!!!!!!!!!!!!!!!!!!!!!! Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda Giuliano Ferrara de Il Fogli= o a guardare, ridere, cercare de masturbarse invano esendo noto impotente d= a sempre. Vi era anche il banchero immensamente pedofilo Gabriele Silvagni = di Banca Carim Rimini, e sua moglie, notia prostituta, tante quanto pedofil= a Raffaella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele = Minotti, criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme = ad altri sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo= . Io, ora, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, = basta droga, basta prostituirsi (como doveti de fare a seguito di questo st= upro, per poter rimanere vivo, per non venire amazato, e doveti de prostitu= irmi proprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a G= enova, rapresentati da questo bastardo sodomizza bambini de avvocato Daniel= e Minotti). Guadanio un decimo di quanto guadaniavo prima e lavoro il tripl= o di quanto prima. Ma preferisco di questo, sento la mia vita uno poco di m= aggiore securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio= de putana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso peder= asta Daniele Minotti di Genova e Rapallo, davvero fa parte di setta di mani= aci sessuali omosessuali molto pericolosi. Ciao. Stefan. Posti Scrito Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:44:21 2024 X-Received: by 2002:ac8:3723:: with SMTP id o32mr4356284qtb.23.1553891508127; Fri, 29 Mar 2019 13:31:48 -0700 (PDT) X-Received: by 2002:a81:5488:: with SMTP id i130mr42929180ywb.417.1553891507903; Fri, 29 Mar 2019 13:31:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no2039438qtn.0!news-out.google.com!i54ni1448qte.0!nntp.google.com!t9no2039427qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 29 Mar 2019 13:31:47 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.28.29.106; posting-account=IG2V5QoAAADWNB-jCtBjZSg45IY7zzEI NNTP-Posting-Host: 62.28.29.106 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: PRENDE MEGA CAZZI IN CULO DI 30 CM: LUIGI BERLUSCONI (CON PADRE IL PEDOFILO SPAPPOLA MAGISTRATI, IL BASTARDO ASSASSINO SILVIO BERLUSCONI, CHE ORA HA FATTO AMMAZZARE ANCHE LA PER BENISSIMO IMANE FADIL, DOPO AVER FATTO LO STESSO CON EGIDIO VERZINI E... From: ANTONIO BINNI - BASTA COL PEDOFILO BERLUSCONI Injection-Date: Fri, 29 Mar 2019 20:31:48 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9452 UN TESTO DICENTE ASSOLUTISSIME VERITA'. DA PARTE DI UNA MIA SORELLA ^MOLTO = SOTTOPOSTA^, PRESSO LA GRAN LOGGIA D'ITALIA: LA CALDISSIMA PORNOSTAR NONCHE= ' INSEGNANTE A SCUOLA IN LOMBARDIA, MARIA GRAZIA CRUPI ( EX AMANTE LESBICA = DI MARINA BERLUSCONI ED EX AMANTE LESBICA DI MARIA DE FILIPPI PER BEN 12 AN= NI). ECCO QUI SUA FOTO MASSONICISSIMA ( CHIARO SCURO) http://3.bp.blogspot.com/-77QAEQtTGWk/W3cRuhZHDJI/AAAAAAAAAPU/ox_S3cmW7KEUZ= nXiaX_TFzWEftaFh63wwCK4BGAYYCw/s1600/ACSszfG2KY6Io2QWHkHClzs_yhKC6NKY96WSeB= EhLQ%253Ds900-mo-c-c0xffffffff-rj-k-no QUI IN FOTO 9 TP 5 LEGGERMENTE SEXY https://yt3.ggpht.com/a-/ACSszfGYKnNA7XEP81l-T0eLaUTs8OwxdR6vxCtIFg=3Ds900-= mo-c-c0xffffffff-rj-k-no QUI IN ALCUNI SUOI FILM PORNO AMATORIALI ( GIRATI FRA L'ALTRO IN VARIE LOGG= E ALAM E NE SIAM FIERISSIMI). DI GRANDISSIMO SUCCESSO IN TUTTO IL MONDO. https://4.bp.blogspot.com/-qkTlyigYRQM/WQsbwxkPZzI/AAAAAAAAALo/MGN1QnRh4Gcw= joiFO96u3-1bFXqWqegDQCK4B/s113/1443711887.76214.jpg https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcRQbZWcnN5tKpb_ra-np= 8v8mAfAGLrNU-7CkH7hUy8HCoWuhR6KFA A VOI IL TESTO IN QUESTIONE Antonio Binni, Gran Maestro della Gran Loggia d'Italia STUDIO BINNI =E2=80=BA www.studiobinni.it/ STUDIO BINNI - Avvocati Associati Via Farini, n. 24 40124 =E2=80=93 Bologna= . Phone: (+39) 051.23.22.00. Phone: (+39) 051.22.42.07. Fax: (+39) 051.29.1= 6.710 ... A VOI IL TESTO, ECCOLO, ECCOLO, SIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII! PRENDE MEGA CAZZI IN CULO DI 30 CM: LUIGI BERLUSCONI (CON PADRE IL PEDOFILO= SPAPPOLA MAGISTRATI, IL BASTARDO ASSASSINO SILVIO BERLUSCONI, CHE ORA HA F= ATTO AMMAZZARE ANCHE LA PER BENISSIMO IMANE FADIL, DOPO AVER FATTO LO STESS= O CON EGIDIO VERZINI E............. EMILIO RANDACIO, https://www.fanpage.it/le-strane-morti-del-caso-ruby-il-giornalista-lavvoca= to-e-la-modella/ PER NON DIRE DI QUANDO RESE IN BRANDELLI I SUPER EROI GIOVANNI FALCONE, PAO= LO BORSELLINO E MIGLIAIA E MIGLIAIA DI ALTRE PERSONE, IN STRAGISTISSIMA, SA= NGUINARISSIMA VITA SUA https://it-it.facebook.com/pages/category/Community/FALCONE-E-BORSELLINO-UC= CISI-DA-BERLUSCONI-134602469910010/ )! CHE FA PER LAVORO IL MEGA RICICLA SO= LDI MAFIOSI! LO STESSO CHE PRIMA EFFETTUAVA IL VERME CRIMINALISSIMO SUO NO= NNO LUIGI BERLUSCONI! E LO STESSO CHE HA SEMPRE FATTO LO SBAUSCIA TROIE POC= O PIU' CHE BAMBINE, PEDOFILO ED OMICIDA DI TANTISSIME PERSONE PER BENE, IL = FIGLIO, MARITO, CAMERATA E PADRE DI PUTTANE: SILVIO BERLUSCONI! MA INIZIAMO DA QUI, ORA, PLEASE.. 1 PRENDE IMMENSI CAZZI IN CULO DI 30 CM: LUIGI BERLUSCONI! CON PADRE LO SCHIF= OSO PEDOFILO SILVIO BERLUSCONI! SI, SI, E' SEMPRE CON MEGA CAZZI IN CULO, I= L RICCHIONE NAZISTA LUIGI BERLUSCONI! FACENTE PER LAVORO IL MEGA RICICLA SO= LDI MAFIOSI!! IL CULATONE HITLERIANO LUIGI BERLUSCONI E' DA SEMPRE " AD ALT= EZZA" CRIMINALISSIMA DI PADRE E NONNO! SI, SI, CIUCCIA E PRENDE MEGA CAZZI = IN CULO LUIGI BERLUSCONI, CHE HA PER SOLA FIDANZATA "UN NOTO MASSONE MAFIOS= O DEL GRANDE ORIENTE D' ITALIA, CON LA BARBA (AMICO E FINANZIATORE DEL COMP= LOTTARDO E CORROTTISSIMO STEFANO BISI). QUESTO MASSONE MAFIOSO CON LA BARBA= ED IL CULATONE PERVERTITO E NAZISTA LUIGI BERLUSCONI SON FRATELLI SATANIST= I, SON FRATELLI ^MASSONAZISTI^! DELLA LOGGIA DEL DRAGO DEL PEDOFILO SPAPPOL= A MAGISTRATI: SILVIO BERLUSCONI! http://www.democraziaradicalpopolare.it/al_Venerabilissimo_Maestro_Massone_= Silvio_Berlusconi_dategli_la_prescrizione_ad_vitam_e_a_priori.html https://www.centroparadesha.it/ude/articoli/1156-549-la-loggia-del-drago-di= -galeazzi-pinotti MASSONE MAFIOSO CON LA BARBA, CHE IO, FRA L' ALTRO, BEN CONOSCO!!!!!!! IN Q= UANTO LAVORAVA CON ME E CON QUELL'EFFERATISSIMO CRIMINALE DI ALDO ACQUISTAP= ACE DI CREDIT SUISSE, IN BORSA, A MILANO" ..ANYWAY..GUARDATE QUI, PLEASE, C= OME IL SEMPRE SBORRATO PROFONDAMENTE DENTRO AL CULO, LUIGI BERLUSCONI, SLIN= GUA DETTO MASSONE MAFIOSO DEL GOI CON LA BARBA http://www.sostenitori.info/wp-content/uploads/2017/07/luigi-berlusconi-681= x357.jpg UN MIO CARO AMICO, IL NOTORIAMENTE DEPRAVATO (E SATANISTA) OMOSESSUALE FEDE= RICO TRABUCCO DI KAIROS https://it.fundspeople.com/people/federico-trabucco HA PARTECIPATO A DIVERSE ORGE GAY MENEGHINE CON LUIGI BERLUSCONI. E MI HA A= SSICURATO CHE LO STESSO PRENDE ANCHE DUE CAZZI IN CULO CONTEMPORANEAMENTE. = MI HA STRA ASSICURATO CHE LO STESSO CHE PRENDE CAZZI DI 30 CM E PASSA, TUTT= I DENTRO ALL'ANO. SIA CHIARO E STRA CHIARO, PLEASE: IO NON SONO PER NULLA A= NTI GAY, PER NULLA OMOFOBA. TANTO E' VERO CHE DA ANNI SON IN RAPPORTI MOLTO= CORDIALI COL PRIMA CITATO NOTO OMOSESSUALE ( PUR SE PIUTTOSTO PERVERTITO = E MOLTO SATANISTA) FEDERICO TRABUCCO DI KAIROS. MA RITENGO ASSOLUTAMENTE CH= E TUTTO IL MONDO, SI, IL MONDO INTERO, IL PIANETA TERRA TUTTO, DEBBA SAPERE= OGNI COSA, PROPRIO OGNI COSA, SUI BASTARDISSIMI CRIMINI E LE MEGA PERVERSI= ONI SESSUALI DI TUTTI I BERLUSCONI: OSSIA LA METASTASI ASSASSINA DEL PIANET= A TERRA. IN QUANTO SONO I DITTATORI NAZISTI, MAFIOSI, CAMORRISTI, NDRANGHET= ISTI, PEDOFILI, STRAGISTI, ASSASSINI, DEL NOSTRO PAESE E DA "APPENA APPENA"= 40 ANNI! FACCIAMO UN CHECK, ORA, SULLA PARTE CHE ANCORA PIU' CONTA, PROBAB= ILMENTE. OSSIA SU QUANTO SIA PROFESSIONALMENTE CRIMINALISSIMO LUIGI BERLUSC= ONI! 2 E' MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI (ECCO QUALE E' IL SUO MALAVI= TOSO VERO LAVORO..CHE POI, CASPITERINA CHE "COINCIDENZUZZA BEDDA", ERA LO S= TESSO LAVORO DEL PEZZO DI MERDA LUIGI BERLUSCONI NONNO IN BANCA RASINI, LA = NOTA BANCA " DI COSA NOSTRA BEDDA BEDDUZZA AAAH" https://www.ilfattoquotidiano.it/2010/11/19/berlusconi-e-cosa-nostra-il-pri= mo-capitolo-de-lintoccabile-di-peter-gomez-e-leo-sisti/77797/5/ http://susannaambivero.blogspot.pt/2009/08/rasini-la-banca-di-berlusconi-e-= della.html ). AVENTE COME PADRE, LO STRAGISTA SPAPPOLA MAGISTRATI, MANDANTE DI MIGLIAIA D= I OMICIDI MASCHERATI DA FINTI MALORI, SUICIDI, INCIDENTI, IL DITTATORE SATA= NISTA E NAZISTA, DICIAMO DITTATORE SATA-N-AZISTA, OLTRE CHE MEGA LAVA SOLDI= MAFIOSILADRO, TRUFFATORE, SEMPRE FALSO, POR-CO-RRUTTORE, MEGA COCAINOMANE,= SCHIFOSISSIMO PEDOFILO SILVIO BERLUSCONI. CIAO A TUTTI, SONO SEMPRE IO, LA VOSTRA FOCOSISSIMA E VINCENTISSIMA PORNOST= AR MARIA GRAZIA CRUPI. EX AMANTE LESBICA DI MARINA BERLUSCONI E PER BEN 12 = ANNI. QUI IN CHIARO SCURO MASSONICISSIMO http://3.bp.blogspot.com/-77QAEQtTGWk/W3cRuhZHDJI/AAAAAAAAAPU/ox_S3cmW7KEUZ= nXiaX_TFzWEftaFh63wwCK4BGAYYCw/s1600/ACSszfG2KY6Io2QWHkHClzs_yhKC6NKY96WSeB= EhLQ%253Ds900-mo-c-c0xffffffff-rj-k-no QUI IN LOOK 9 TO 5, GIUSTO PRIMA DI ANDARE AD UN ORGIA POMERIDIANA CHE FECI= AD ARCOREHARDCORE CON MARINA BERLUSCONI, MARIA DE FILIPPI E TANTISSIME ALT= RE LESBICHE DEI GIRI "MAFIASET" https://yt3.ggpht.com/a-/ACSszfGYKnNA7XEP81l-T0eLaUTs8OwxdR6vxCtIFg=3Ds900-= mo-c-c0xffffffff-rj-k-no QUI IN ALCUNI MIEI FILM PORNO AMATORIALI, DI GRAN SUCCESSO IN TUTTO IL MOND= O https://4.bp.blogspot.com/-qkTlyigYRQM/WQsbwxkPZzI/AAAAAAAAALo/MGN1QnRh4Gcw= joiFO96u3-1bFXqWqegDQCK4B/s113/1443711887.76214.jpg https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcRQbZWcnN5tKpb_ra-np= 8v8mAfAGLrNU-7CkH7hUy8HCoWuhR6KFA E' SEMPRE, SEMPRE E STRA SEMPRE SBORRATO NEL CULO: LUIGI BERLUSCONI! CON FI= DANZATA UN ^MASSONE MAFIOSO^ CON LA BARBA https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg E NON CON FIDANZATA, LA NOTA ZOCCOLA FEDERICA FUMAGALLI, DA ANNI SCOPATA DA= TUTTI, IN MILLE CLUB PRIVE' DI INTERA FOGNA NAZISTA E MAFIOSA DI BERLUSCON= IA. COME COSI', DI MONTECARLO, INGHILTERRA E SVIZZERA! DICEVO.. E' SEMPRE SBORRATO TUTTO DENTRO AL CULO: LUIGI BERLUSCONI! CON FID= ANZATA UN ^MASSONE MAFIOSO^ CON LA BARBA https://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi ^MASSONE MAFIOSO^ DELLA MEGA ASSASSINA GRAN LOGGIA DEL DRAGO DEL DITTATORE = FASCISTA, NDRANGHETISTA, CAMORRA, DI COSA NOSTRA, OLTRE CHE STRAGISTA SPAPP= OLA MAGISTRATI, MANDANTE DI MIGLIAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI= , MALORI, INCIDENTI, NOTO PEDOFILO SILVIO BERLUSCONI!!! RICICLA VALANGHE DI SOLDI MAFIOSI IL RICCHIINE SEMPRE COL CULO PIENO DI SBO= RRA, IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINAL= ISSIMA B CINQUE SRL. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUS= CONI DI CRIMINALISSIMA MEDIASET ALIAS MAFIASET, CAMORRASET, NDRANGASET, NAZ= ISTSET. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMI= NALISSIMA FININVEST ALIAS (MA)FI(A)NINVEST. IL DELINQUENTISSIMO RICICLA SOL= DI MAFIOSI LUIGI DI CRIMINALISSIMA MOLMED. IL DELINQUENTISSIMO RICICLA SOLD= I MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA HOLDING ITALIANA QUATTORDICESI= MA SPA (GIA' CASSAFORTE MAFIOSISSIMA DI STEFANO BONTATE PRIMA E TOTO RIINA,= POI...CASPITERINA CHE SOCI PER BENE, CASPITERINA, WAGLIO'). IL DELINQUENTI= SSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA H 14 ( SEMPR= E GIA' CASSAFORTE MAFIOSA DI STEFANO BONTATE PRIMA E TOTO RIINA, POI...CASP= ITERINA CHE SOCI PER BENE, CASPITERINA, WAGLIO'). IL DELINQUENTISSIMO RICIC= LA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA SERI JAKAL GROUP. IL DE= LINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ITH= ACA SRL. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIM= INALISSIMA DI U-START. 3 IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIM= A SOLDO FINANCIAL SERVICES. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIG= I BERLUSCONI DI CRIMINALISSIMA MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOL= ANUM, LAVALAVAPERCOCALEROSCOLOMBIANUM, NAZISTANUM, NAZISTANUM. IL DELINQUEN= TISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA XLAB. IL D= ELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA HO= LDING DI INVESTIMENTI B5. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI B= ERLUSCONI DI CRIMINALISSIMA ABOCA DI SAN SEPOLCRO. IL DELINQUENTISSIMO RICI= CLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA PAYLEVEN. IL DELINQUEN= TISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ROCKET INT= ERNET. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMIN= ALISSIMA ELIGOTECH AMSTERDAM. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUI= GI BERLUSCONI DI CRIMINALISSIMA CGNAL ( O CRIMINALISSIMA CGNAL-ELIGOTECH CH= E SIA) DEL TOPO DI FOGNA BERLUSCORROTTISSIMO MARCO CARRAI (PURE NOTO PEDOFI= LO, FRA L'ALTRO, NE ABBIAM PROVE A PALATE). IL DELINQUENTISSIMO RICICLA SOL= DI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ALGEBRIS DEL FIGLIO DI PUTTAN= A, MEGA RICICLA SOLDI MAFIOSI: DAVIDE SERRA. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIM= A ITHACA, IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRI= MINALISSIMA SIREFID ( IL TUTTO INSIEME AD UN ALTRO VERME MEGA RICICLA SOLDI= MAFIOSI, LA BESTIA CRIMINALE GIORGIO VALAGUZZA, NON PER NIENTE, EX DI NAZI= STA JP MORGAN). IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI = DI CRIMINALISSIMA CRYPTOLAB E CRYPTOPOLIS DI NOTO PEDOFILO ASSASSINO PAOLO = BARRAI ( DI FALLIMENTARISSIMO BLOG MERCATO "MERDATO" LIBERO). IL DELINQUENT= ISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA EIDOO DI VE= RME DELLA NDRANGHETA: NATALE FERRARA DA REGGIO CALABRIA ( CRIMINALISSIMA EI= DOO DI VERME DELLA NDRANGHETA: NATALE MASSIMILIANO FERRARA DA REGGIO CALABR= IA). PIU' DI TANTISSIMA ALTRA MERDA FINANZIARIO-CRIMINALE, FASCIOMAFIOSA, B= ERLUSCONICCHIA VARIA! SI, SI, E' PROPRIO COSI'. IL MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI E' UN NAZIRICCHIONE, UN CULA= CCHIONE, UN FEMMINONE SEMPRE SBORRATO PROFONDAMENTE DENTRO AL CULO ( NON SO= NO OMOFOBO O ANTI GAY, ASSOLUTISSIMAMENTE NO, ANZI, COME DETTO, MI DANNO AN= CHE A ME, OGNI TANTO, DEL GAY, DICO DI PIU', HO SEMPRE ODIATO QUANDO LEGGO = CHE ALCUNI GAYS VENGONO PICCHIATI QUASI A MORTE, O PROPRIO UCCISI, SOLO IN = QUANTO, BEN APPUNTO, GAYS: MA VISTO CHE I BERLUSCONI HAN NAZISTAMENTE SEMPR= E ODIATO, UMILIATO E DERISO GLI OMOSESSUALI E VISTO CHE COME LORO SOLITO, S= TANNO CASTRANDO MORTALMENTE LA LIBERTA' DI STAMPA, PER NON FAR SAPERE CHE L= ORO FIGLIO, IL NAZI RICCHIONE LUIGI BERLUSCONI, IL CRIMINALISSIMO RICICLA S= OLDI MAFIOSI LUIGI BERLUSCONI, PRENDE MEGA CAZZI IN CULO OGNI GIORNO E BEVE= LITRI E LITRI DI SBORRA, OGNI ANNO, CI PENSIAMO NOI A FARLO SAPERE ED AL P= IANETA TERRA TUTTO). E DI TIPO MOLTO MA MOLTO DEPRAVATO (AMA IL BERLUSCONI'= S DOUBLE ANAL STYLE, OSSIA, PRENDERE DUE MEGA CAZZI IN CULO, CONTEMPORANEME= NTE, CHE SCHIFO, PUAH)! CRIMINALISSIMO MEGA RICICLA SOLDI MAFIOSI LUIGI BER= LUSCONI: CON PADRE L'ASSASSINO NAZIMAFIOSO, STRAGISTA SPAPPOLA MAGISTRATI, = MANDANTE DI MIGLIAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI, INCIDE= NTI, VISCIDISSIMO PEDOFILO SILVIO BERLUSCONI! E CON FIDANZATA UN NOTO MASSO= NE DI COSA NOSTRA, CON LA BARBA. QUESTO: https://www.tuttouomini.it/images/= 2017/7/luigi-berlusconi-bacio-gay-estate-amico.jpg E NON CON FIDANZATA LA NOTA TROIA, SEMPRE SCOPATA DA TUTTI IN MILLE CLUB PR= IVE, LA NOTA COCAINOMANE PUTTANA SEMPRE PENETRATA NEL CULO: FEDERICA FUMAGA= LLI. CIAO A TUTTI DA ME, ORA. SONO LA NOTA, VICENTISSIMA PORNOSTAR ED INSEGNANTE= : MARIA GRAZIA CRUPI. NATA IL 30.10.1969. 4 SON QUI IN CHIARO SCURO MASSONICISSIMO ( SON MASSONA DI ALTISSIMO GRADO PRE= SSO LA GRAN LOGGIA D'ITALIA DI ANTONIO BINNI) http://3.bp.blogspot.com/-77QAEQtTGWk/W3cRuhZHDJI/AAAAAAAAAPU/ox_S3cmW7KEUZ= nXiaX_TFzWEftaFh63wwCK4BGAYYCw/s1600/ACSszfG2KY6Io2QWHkHClzs_yhKC6NKY96WSeB= EhLQ%253Ds900-mo-c-c0xffffffff-rj-k-no QUI IN LOOK 9 TO 5, GIUSTO PRIMA DI ANDARE AD UN ORGIA POMERIDIANA CHE FECI= AD ARCOREHARDCORE CON MARINA BERLUSCONI, PAOLA BARALE, MARIA DE FILIPPI, A= LBA PARIETTI, MARIA ELENA BOSCHI, DANIELA SANTANCHE', SIMONA PREMOLI, FRANC= ESCA PASCALE ( CHE E' DA TANTI ANNI AMANTE LESBICISSIMA DI MARINA BERLUSCON= I E NON DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI) E TANTISSIME AL= TRE "MASCHIONE" DI GIRI "MAFIASET" https://yt3.ggpht.com/a-/ACSszfGYKnNA7XEP81l-T0eLaUTs8OwxdR6vxCtIFg=3Ds900-= mo-c-c0xffffffff-rj-k-no QUI IN ALCUNI MIEI FILM PORNO AMATORIALI, DI GRAN SUCCESSO IN TUTTO IL MOND= O ( OVE SONO SEMPRE ED ASSOLUTAMENTE CON MASCHERINA PER NON RISCHIARE DI PE= RDERE IL PUR SEMPRE COMODO E FACILE STIPENDIO DI INSEGNANTE DEL MINISTERO D= I ISTRUZIONE) https://4.bp.blogspot.com/-qkTlyigYRQM/WQsbwxkPZzI/AAAAAAAAALo/MGN1QnRh4Gcw= joiFO96u3-1bFXqWqegDQCK4B/s113/1443711887.76214.jpg http://b1.woxcdn.com/pics-final-2/ced/ba8/cedba85d41629e8e0faa7f179b8f447a.= jpg https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcRQbZWcnN5tKpb_ra-np= 8v8mAfAGLrNU-7CkH7hUy8HCoWuhR6KFA SONO SPECIALMENTE NOTA IN TUTTO IL GLOBO TERRESTRE PER ESSER STATA L' EX AM= ANTE LESBICA DI MARINA BERLUSCONI E PER BEN 12 ANNI ( FRA MONTAGNE DI CASH = MAFIOSO, QUINTALI DI COCAINA, ORDINI DI OMICIDI E STRAGI: I BERLUSCONI SONO= PIU' MALAVITOSI ASSASSINI DI AL CAPONE E TOTO RIINA MESSI INSIEME, VE LO S= TRA ASSICURO) https://groups.google.com/forum/#!search/maria$20grazia$20crupi/it.sport.ca= lcio.napoli/0K7zC5-GrmA/npiVnL36DQAJ https://groups.google.com/forum/#!search/maria$20grazia$20crupi/it.politica= /KP-ArJynkDY/Og-93NXDBQAJ https://www.youtube.com/channel/UC-jR78tPoXDaRXHYGteQPUw ED ORA FATEMI URLARE CON TUTTE LE MIE FORZE, PLEASE, MI RIPETERO', MOLTO PR= OBABILMENTE, MA PER IL BENE DELLA UMANITA' TUTTA, LO FACCIO E LIETISSIMAMEN= TE!L'IMMENSO PRENDI CAZZI IN CULO LUIGI BERLUSCONI (FIDANZATA-WIKIPEDIA-PAD= RE SPAPPOLA MAGISTRATI E SBAUSCIA TROIE POCO PIU' CHE BAMBINE, SILVIO BERLU= SCONI..... " PER SEMPRE FUORI DAI COGLIONI") STA IMBASTENDO IN GIRO PER IL = MONDO, VERE E PROPRIE OVRA E GESTAPO ASSASSINE DEL WEB, COL PRIMA CITATO ME= RDONE BERLUSCONICCHIO MARCO CARRAI DI CGNAL E COL NAZI-ST-ALKER, ACCERTATO = PEDERASTA INCULA BAMBINI, FREQUENTISSIMO MANDANTE DI OMICIDI, GIA' TRE VOLT= E FINITO IN CARCERE: PAOLO BARRAI NATO A MILANO IL 28.6.1965 ( O FREQUENTIS= SIMO MANDANTE DI OMICIDI, GIA' TRE VOLTE FINITO IN CARCERE: PAOLO PIETRO BA= RRAI NATO A MILANO IL 28.6.1965 CHE SIA)!!! E SIA CHIARO, PLEASE: IO SONO M= ARIA GRAZIA CRUPI DI MILANO. SONO L'EX AMANTE LESBICA DI MARINA BERLUSCONI.= LE HO LECCATO LA FIGA E LE HO MESSO AGGEGGI SESSUALI NEL CULO PER BEN 12 A= NNI. E DI TIPO PERVERTITISSIMO (LO VOLEVA LEI, ME LO IMPONEVA, SEMPRE, LEI)= . SE VI E' UNA AMICA INTIMA DI LGBT QUELLA SONO PROPRIO IO. MA DEBBO URLARE= UNA COSA, ADESSO: LUIGI BERLUSCONI PRENDE CAZZI DI 30 CM IN SU FINO ALLA P= ROSTATA, FA BOCCHINI SU BOCCHINI E BEVE LITRI SU LITRI DI SBORRA. E' UN OMOSESSUALE PERSO, PRESTO, MOLTO PROBABILMENTE, SI FARA' ANCHE LA OPE= RAZIONE E DIVERRA' TRANS, MA NESSUNO E STRA NESSUNO HA IL CORAGGIO DI SCRIV= ERNE: STRACCERO' IO IL LERCIO DRAPPO DI OMERTA' BERLUSCONAZISTA E BERLUSCOM= AFIOSA, ALLORA! IL CIUCCIA E PRENDI MEGA CAZZI A GO GO LUIGI BERLUSCONI (BACIO RICCHIONESCH= ISSIMO QUI https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg ) NATO IN FIGHETTINA ARLESHEIM (CH) IL 27.9.1988. 5 SI, PROPRIO LUI: L'OMOSESSUALE ^OCCULTO^ LUIGI BERLUSCONI DI BASTARDAMENTE = CRIMINALE ELIGOTECH AMSTERDAM, BASTARDAMENTE CRIMINALE SOLDO LTD LONDON E B= ASTARDAMENTE CRIMINALE BANCA MEDIOLANUM (CHE RICICLANO MONTAGNE DI =E2=82= =AC MAFIOSI, ESATTAMENTE COME FACEVA LA CRIMINALISSIMA BANCA RASINI DI SUO = NONNO, TOPO DI FOGNA LUIGI BERLUSCONI ....O COME FACEVA E FA ORA PIU' CHE M= AI, LA FININVEST DEL PEDOFILO DILANIANTE FALCONE E BORSELLINO: SILVIO BERLU= SCONI http://www.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commission= ate-berlusconi/ E DELLA CRIMINALISSIMA, HITLERIANA, ^OCCULTA" LESBICA MARINA BERLUSCONI https://profile.theguardian.com/user/id/12251903?page=3D1 https://twitter.com/premolisimona?lang=3Den https://twitter.com/premolisimona/status/876055837420158976 https://twitter.com/PremoliSimona/status/946915645756715009 https://twitter.com/PremoliSimona/status/946923968245784576 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 ) INSIEME AL BERLUS-CO-RROTTO VERME MARCO CARRAI DI CGNAL, CREA NAZITECNOLOGI= CHE NUOVE OVRA E GHESTAPO! COL NOTO ANTI SEMITA, GIA' 3 VOLTE FINITO IN CAR= CERE, PAOLO BARRAI, NATO A MILANO IL 28.6.1965 ( FINITO IN CARCERE PURE IN = BRASILE, ED ANCHE PER PEDOFILIA OMOSESSUALE: INCULAVA LI I BAMBINI, NE SCRI= VEREMO PRESTO http://www.rotadosertao.com/images/fotos/fotos_noticias/testao.jpg http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg )! 6 COL TUTTO, PER FINIRE, UNITISSIMO ALL'ECONOMISTA NOTORIAMENTE MOLTO PEDOFIL= O, NAZISTA ED ASSASSINO PAOLO CARDEN=C3=80 DI SAN PAOLO INVEST E MALAVITOSA= MEDIOLANUM STESSA. http://www.py.cz/pipermail/python/2017-September/013036.html https://a.mytrend.it/authors/1385.jpg NATO A MACERATA IL 2.19.1971 E RESIDENTE A PENNA SAN GIOVANNI (MACERATA), V= IA UMBERTO I, NUMERO 41. COME ANCHE IN VIA POZZO 105, 63837 FALERONE (FM) h= ttps://www.commoditiestrading.it/public/autori/635338392358575000_Cardena.j= pg STO MERDAIO MEGA OMICIDA ERA DIETRO LO STUPRO DI GRUPPO EFFETTUATO A PAMELA= MASTROPIETRO. http://nomassoneriamacerata.blogspot.com/2018/02/lomicidio-di-pamela-mastro= pietro.html A CUI HA FATTO SEGUITO UN RITUALE MASSONICO NAZIFASCISTA, EFFETTUATO PROPRI= O DAL SATANISTA ASSASSINO E PEDOFILO PAOLO CARDENA', PORTANTE ALLA DIVISION= E DEL CORPO DI PAMELA ( EFFETTUATA DA MEDICI LEGALI MASSONI ANGUINARI, COME= AI TEMPI DEL MOSTRO DI FIRENZE: FRATELLI CRIMINALISSIMI DEI PAZZI OMICIDA = PAOLO CARDENA' E STEFANO CARDENA' DI CRIMINALISSIME CARDENA' AND PARTNERS E= CARDENA' CONSULTING). QUESTO LINK QUADRA OGNI COSA, A PROPOSITO http://m.dagospia.com/clamoroso-a-macerata-sospetti-su-un-giro-di-baby-squi= llo-dietro-l-omicidio-di-pamela-mastropietro-171763 HAN POI TROVATO 4 LORO SCUGNIZZI MALAVITOSI NIGERIANI PER GIRARE A LORO OGN= I COLPA ( I QUALI, ORA, IN CARCERE, DALTRONDE, AVRANNO VITTO E ALLOGGIO PER= UN TOT DI TEMPO, PIU' TANTI SOLDI QUA E LA, RICEVUTI DA QUESTI MASSONI ASS= ASSINI, PER STARE ZITTI.. COSI' CHE FRA QUALCHE ANNO USCIRANNO DALLE CELLE = E SARANNO PURE BENESTANTI). DI QUESTO NE SCRIVONO E DICONO NOTI MASSONI DI = ESTREMA DESTRA STESSA, QUALI FABIO FRABETTI, PAOLO FRANCESCHETTI E SPECIALM= ENTE GIANFRANCO CARPEORO, IN REALTA', A LIVELLO DI VERO NOME E COGNOME, GIA= NFRANCO PECORARO, ( CHE, VIA MARI DI LOGGE MASSONICHE, SON ADDENTRO DA UNA = VITA A QUESTO TIPO DI OMICIDI, QUINDI, SANNO ALLA PERFEZIONE OGNI COSA ED A= MMIREVOLISSIMAMENTE CE NE FANNO SAPERE) http://petalidiloto.com/2018/02/due-parole-sullomicidio-pamela-mastropietro= .html http://petalidiloto.com/2012/12/intervista-carpeoro-su-massoneria-e.html QUESTO E' SONO UN ANTIPASTINO. I PIATTI FORTI ARRIVERANNO AL PIU' PRESTO PO= SSIBILE. O IL PEDOFILO SPAPPOLA MAGISTRATI... O IL NAZIMAFIOSO ASSASSINO SILVIO BERLUSCONI.. O IL DITTATORE COCAINOMANE DISTRUGGI VITE ALTRUI SILVIO BERLUSCONI.. .. AMMETTE IL MALE INGIUSTIFICATISSIMO FATTO, .. AMMETTE IL MALE DAVVERO INGIUSTISSIMO ED OMICIDA, FATTO ( SA' BENISSIMO = A CHE E CHI MI RIFERISCO). E RISARCISCE. O LA GIUSTIZIA LA FARO' IO. NEI SU= OI CONFRONTI E NEI CONFRONTI DI TUTTI I PORCI E VERMI CHE RADONO AL SUOLO V= ITE DI INNOCENTI, PER LUI! PER SUA BORIA, SATANAZIFASCISMO, COCAINA, SOLDI = MAFIOSI, ARROGANZA, ORGE PEDOFILESCHE, SCORCIATOIE SOCIALI, PREPOTENZA, EGO= CENTRISMO, ANTIDEMOCRAZIA, PERVERSIONE, CORRUZIONE, COSA NOSTRA, CAMORRA, N= DRANGHETA, SACRA CORONA UNITA, VANITA', BRAMA DI CAMMINARE A MORTE SULLE ES= ISTENZE ALTRUI. O FATTI O CAZZI AMARI, DA ORA E PER SEMPRE, PER GLI ASSASSI= NI, STRAGISTI, NAZIMAFIOSI, EFFERATISSIMI CRIMINALI IN FIGHETTINA E MOLTO, = MA MOLTO MALAVITOSA CRAVATTA: BERLUSCONI! http://the8club-pasar-komoditi.blogspot.com/2018/06/sborrato-dentro-al-culo= -luigi.html From newsfish@newsfish Thu Aug 1 00:44:21 2024 X-Received: by 2002:a0c:af53:: with SMTP id j19mr1902206qvc.19.1554482630181; Fri, 05 Apr 2019 09:43:50 -0700 (PDT) X-Received: by 2002:a81:758b:: with SMTP id q133mr11132470ywc.256.1554482629876; Fri, 05 Apr 2019 09:43:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no1662955qtn.0!news-out.google.com!i54ni1090qte.0!nntp.google.com!t9no1662952qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Apr 2019 09:43:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.56.105.249; posting-account=suxb8goAAAA_xXgWV0YZdCIO50EfkHvW NNTP-Posting-Host: 85.56.105.249 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: =?UTF-8?Q?PEZZO_DI_MERDA_PEDOFILO_PAOLO_CARDEN=C3=80_=28FACEBOOK=29=21_D?= =?UTF-8?Q?I_CRIMINALISSIMO_VINCITORI_E_VINTI=21_RAGLIA_CHE_FA_IL_=22PRIVAT?= =?UTF-8?Q?E_BANKER=22=2E_MA_NON_DICE_CHE_UNICI_SUOI_CLIENTI_SONO_I_MAFIOSI?= =?UTF-8?Q?_CRISAFULLI_DI_MILANO=21_1=C2=BFUNA_DELLE_FAMIGLIE_DI_COSA_NOSTRA_?= =?UTF-8?Q?PIU=27_ASSASSINE_DI_SE?= From: "CHI E' IL PEDOFILO NAZISTA PAOLO CARDENA'?" Injection-Date: Fri, 05 Apr 2019 16:43:50 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9453 PEZZO DI MERDA PEDOFILO PAOLO CARDEN=C3=80 (FACEBOOK)! DI CRIMINALISSIMO VI= NCITORI E VINTI! RAGLIA CHE FA IL "PRIVATE BANKER". MA NON DICE CHE UNICI S= UOI CLIENTI SONO I MAFIOSI CRISAFULLI DI MILANO! 1=C2=BFUNA DELLE FAMIGLIE = DI COSA NOSTRA PIU' ASSASSINE DI SEMPRE! ED E' PURE NOTIO PEDERASTA SODOMIZ= ZA ED AMMAZZA BAMBINI, STO FIGLIO DI PUTTANA NAZISTA, RICICLA SOLDI MAFIOSI= E PEDERASTA DI PAOLO CARDEN=C3=80!!! PROPRIO COSI! E' CRIMINALISSIMA LA CARDEN=C3=80 CONSULTING DI VIA MONTESSOR= I 6, FALERONE (FM). DA ANNI RICICLA SOLDI ASSASSINI DI COSA NOSTRA, CAMORRA= , NDRANGHETA E MAFIA RUSSA (CHE NON PER NIENTE, LAVO' PRIMI PROPRI =E2=82= =AC OMICIDA, A LIVELLO MONDIALE, ESATTAMENTE NELLE MARCHE)!! E iI VERMI SCH= IFOSI CHE LA RAPPRESENTANO, I BASTARDI EFFERATI CRIMINALI STEFANO CARDENA' = E PAOLO CARDENA' SONO DUE "SATA-N-AZISTI" PEDOFILI INCULA BAMBINI ED UCCIDI= BAMBINI A RAFFICA! REGISTI DI CENTINAIA DI OMICIDI E SPARIZIONI DI PERSONE= , ESATTAMENTE COME DA QUESTO ARTICOLO http://www.cronachemaceratesi.it/2015= /05/25/allarme-persone-scomparse-163-a-macerata-500-nelle-marche/661329/ 1 MALAVITOSISSIMA CARDEN=C3=80 E PARTNERS DI VIA MONTESSORI 6, 63837 FALERONE= (FM) - Tel: 0734.710786 - sua criminalissima e mail: info@cardenaconsultin= g.it - P.IVA: 01840990442). DA ANNI RICICLA SOLDI ASSASSINI DI COSA NOSTRA,= CAMORRA E MAFIA RUSSA (CHE NON PER NIENTE LAVO' PRIMI PROPRI =E2=82=AC OMI= CIDA PROPRIO NELLE MARCHE)! E PAOLO CARDENA' E PURE NOTO PEDOFILO! IL MASSONE PEDERASTA INCULA BAMBINI PAOLO CARDEN=C3=80 HA UN BLOG CRIMINALI= SSIMO: VINCITORI E VINTI! NOI SAREMO I VINCITORI CHE METTEREMO LUI, I SUOI = MEGA CRIMINI E MEGA BALLE, SPALLE AL MURO! MENTRE LUI SARA' IL VINTISSIMO! = IL VERME DELINQUENTISSIMO PAOLO CARDEN=C3=80, PAOLO CARDEN=C3=81, NATO A MA= CERATA IL 2.19.1971 E RESIDENTE IN VIA POZZO 105 A FALERONE, OLTRE AD ESSER= NOTO PEDOFILO E' UN PORCO MEGA RICICLA SOLDI MAFIOSI PER I SUPR KILLER DI = COSA NOSTRA: CRISAFULLI DI MILANO! COME DA "TRADIZIONE" DI SUOI MANDANTI: O= SSIA IL PURE NOTISSIMO PEDOFILO SILVIO BERLUSCONI... (OLTRE CHE STRAGISTA S= PAPPOLA EROICI MAGISTRATI GIOVANNI FALCONE E PAOLO BORSELLINO https://it-it= .facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602469910010/) E= D I PORCI MEGA RICICLA SOLDI ASSASSINI DI MALAVITE DI MEZZO MONDO: ENNIO DO= RIS E MASSIMO DORIS DI MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOLANUM, NA= ZISTANUM! MA CHI =C3=88 DAVVERO STO SCHIFOSO PEDOFIL-O-MOSESSUALE STUPRANTE, BAMBINI = ED ADOLESCENTI, CHIAMANTESI PAOLO CARDEN=C3=80 RESIDENTE A PENNA SAN GIOVAN= NI (MACERATA), VIA UMBERTO I, NUMERO 41! DI BASTARDAMENTE CRIMINALE CARDEN= =C3=80 CONSULTING, BASATA IN VIA MONTESSORI 6, 63837 FALERONE (FM) - Tel: 0= 734.710786 E DI MEGA TRUFFATORE BLOG VINCITORI E VINTI ( CHE ESISTE PER FAR= ABBOCCARE I "CIULA DEL WEB" CHE ABBOCCANDO AI SUOI FALLIMENTARI SERVIZI, S= EMPRE PERDONO TUTTI I PROPRI RISPARMI, SIA PER LA TOTALE INCOMPETENZA DI PA= OLO CARDEN=C3=80 SUI MERCATI FINANZIARI MONDIALI, SIA PER LA INDOLE SEMPRE = ESTREMAMENTE TRUFFALDINA DEL VERME CRIMINALISSIMO PAOLO CARDEN=C3=80 STESSO= )! E CHI E' IL NOTO PEZZO DI MERDA, FIGLIO DI PUTTANA, LADRO, SEMPRE FALSO,= COCAINOMANE, DELINQUENTE ESTREMO E PURE NOTO PEDOFILO STEFANO CARDEN=C3=80 http://www.formazione-lavoro.eu/img/public/stefano.jpg FACENTE DA DECENNI TRUFFE SU TRUFFE E MEGA RICICLAGGI DI CASH MAFIOSO DAGLI= UFFICI DI Via Maria Montessori, 8, 63020 Falerone FM, Italia Telefono: +39 0734 710786 Criminalissima email info@cardenaconsulting.it AL PUNTO, NOW, PLEASE! OPINIONI TUTTE VOMITEVOLI SU STO PEDOFIL-O-MOSESSUALE PAZZO E SODOMIZZA INF= ANTI E RAGAZZINI: PAOLO CARDEN=C3=81 DI DELINQUENTISSIMO BLOG VINCITORI E V= INTI!!! TANTO PER INIZIARE: CHI SONO IO? MI VOLETE FARE FUORI IN QUANTO DICO LA VER= ITA' ( COSA CHE NELLA FASCIOMAFIOSA ITALIA, DA 40 ANNI DITTATURA NAZINDRANG= HETISTA DI BERLUSCONIA, ACCADE DA MILLENNI)? 2 SONO UN FUORI USCITO DA QUEL PARTITO STRA COLMO DI COSA NOSTRA, CAMORRA, ND= RANGHETA E CATTIVERIA ANTI DEMOCRATICA DI ESTREMISSIMA DESTRA CHE E' FORZA = ITALIA ( OVE SGUAZZA, A LIVELLO DI MEGA BALLE CHE FA SCRIVERE SU INTERNET, = LA MASSONA SATA-N-AZISTA, LA PUTTANA SEMPRE CON CAZZI IN CULO: GINA NIERI D= I MEDIASET, MAFIASET, CAMORRASET, NDRANGASET). DI STO VERME CRIMINALE DI PAOLO CARDEN=C3=81 ( CHE IN FORZA ITALIA FA IL ME= GA RICICLA SOLDI MAFIOSI) SO' TUTTO! E QUINDI, COME DICONO A NAPULE, ORA MI= "HAGGIA PROPRIO SFUGA' "!!! PROFESSIONALLY SPEAKING, SI DEFINISCE "PRIVATE BANKER"...MA NON DICE CHE UN= ICI SUOI CLIENTI SONO I MAFIOSI ASSASSINI CRISAFULLI DI MILANO! UNA DELLE F= AMIGLIE DI COSA NOSTRA PIU' BASTARDAMENTE KILLER DI TUTTI I TEMPI! E POI, COME CITATO, IL VOMITEVOLE PEDERASTA PAOLO CARDEN=C3=81 DI CRIMINALI= SSIMO BLOG VINCITORI E VINTI E' PURE NOTISSIMO PEDOFIL-O-MOSESSUALE ( NULLA= CONTRO GLI OMOSESSUALI PER BENE, TRASPARENTI, CHE NON SI NASCONDONO, COSA,= SE MAI, DA AMMIRARE... MA TUTTO CONTRO I PEDOFIL-O-MOSESSUALI, QUELLI CHE = INCULANO NEONATI, BAMBINI, RAGAZZINI, ADOLESCENTI COME FA DA SEMPRE IL PEDE= RASTA PAOLO CARDEN=C3=81: QUI IN UNA FOTO CHE GLI ABBIAMO FATTO, MENTRE, IN= MUTANDE, FISSAVA, CON SGUARDO DA DEPRAVATO SESSUALE MAXIMO, UN BAMBINO DI = OTTO ANNI, NELLE ADIACENZE DI UN CAMPO ROM PADANO, VICINO A COLOGNO MONZESE= , VICINO A MAFIASET-CAMORRASET-NDRANGASET-NAZISTSET MEDIASET... http://a.my= trend.it/authors/1385.jpgBAMBINODIOTTO ANNI CHE MEZZ'ORA DOPO AVREBBE INCUL= ATO A SANGUE...LO STAVAMO PEDINANDO DA MESI E MESI E MESI, ABBIAMO FOTOGRAF= ATO E VIDEATO IL TUTTO. PRESTO OGNI COSA SU MIGLIAIA DI SITI, ANCHE DI PLUT= ONIO E MARTE, NON SOLO DI QUESTO PIANETA SEMPRE PIU' "PICCIRIDDU PICCIRIDDU= " .. USO SLANG SICILIANO, PER FAR SENTIRE IL MEGA RICICLA CASH DI COSA NOST= RA, PAOLO CARDEN=C3=81, COME SE IN UNA "COSA SUA" AAAA)!!! SI, PROPRIO COSI', BABIES, PROPRIO COSI'!!! OPINIONI TUTTE ORRIBILI SUL BAS= TARDO CRIMINALE PAOLO CARDEN=C3=81 NATO A MACERATA IL 2.19.1971, OPINIONI T= UTTE VOMITEVOLI SULL'ECONOMISTA SODOMIZZA BAMBINI PAOLO CARDEN=C3=81, SUL B= LOGGER PEDERASTA, NAZISTA, RAZZISTA, RICICLA CASH MAFIOSO PAOLO CARDEN=C3= =81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI ( PER NON DIRE QUANTO SIA PURE= SEMPRE FALSO, LADRO, TRUFFATORE, BRUCIANTE TUTTI I RISPARMI DI CHI A LUI, = IDIOTAMENTE, ABBOCCHI E QUINDI SI AFFIDI VIA INTERNET=E2=80=A6 PER NON DIRE= QUANTO SIA ANCHE MANDANTE DI OMICIDI, MALATO MENTALE, COCAINOMANE E TANTIS= SIMO ALTRO DI MERAMENTE PERICOLOSISSIMO.. MA VEDREMO TUTTO QUESTO MOLTO PRE= STO)?!? RAGLIEREBBE SU INTERNET CHE FAREBBE IL PRIVATE BANKER.. MA NON AGGI= UNGE CHE I SUOI SOLI 2 CLIENTI SONO LE FAMIGLIE MAFIOSE ED ASSASSINE CAGNET= TI E CRISAFULLI DI MILANO! E POI..IL VERME SCHIFOSO PAOLO CARDENA' DI CRIMI= NALISSIMO BLOG VINCITORI E VINTI E' PURE ACCLARATO PEDERASTA SODOMIZZA BAMB= INI! INFATTI...FATEVI QUESTE DOMANDUZZEDDE, PLEASE ( AGAIN AND AGAIN... SCRIVO I= N SLANG SICILIANO, ESSENDO PAOLO CARDENA=E2=80=99 UNO SCHIFOSO MALAVITOSO R= ICICLATORE DI SOLDI ASSASSINI DI COSA NOSTRA, IN PRIMIS, POI ANCHE DI CAMOR= RA E NDRANGHETA=E2=80=A6 GLI FACCIO COME SE UN FAVORE..LO FACCIO SENTIRE CO= ME SE A CASA=E2=80=A6 LO FACCIO SENTIRE COME SE IN UNA=E2=80=A6SANGUINARISS= IMA... =E2=80=9CCOSA SUA=E2=80=9D=E2=80=A6 AAAH): COME E' IL VERME CRIMINAL= ISSIMO PAOLO CARDEN=C3=80, LO SCHIFOSO PEDERASTA PAOLO CARDEN=C3=80, NELLA = VITA PRIVATA? COI PANTALONI ABBASSATI? 3 DUE, TRE SERE ALLA SETTIMANA VA' IN LOCALI ^OCCULTISSIMI^ DI TIPO ESTREMAME= NTE DEPRAVATO! APERTI SOLO A MASSONI OMOSESSUALI LEGHISTI E BERLUSCONIANI! = CI VA' COL PARI PEDERASTA GIULIO TREMONTI ( IL CUI AMANTE OMOSESSUALISSIMO = ERA IL NAZISTA, ANZI, SATA-N-AZISTA ALEXANDER BOETTCHER, QUELLO CHE SI RIEM= PIVA DI COCAINA E FACEVA SFREGIARE CON ACIDO ASSASSINO TANTA GENTE INNOCENT= E, INNOCUA, PER BENE.. COLUI CHE SI DEFINIVA LUI STESSO UN PAZZO DEPRAVATO = SESSUALE http://www.dagospia.com/rubrica-29/cronache/sono-deviato-sessuale-= martina-levato-era-sadomasochismo-124763.htm...IL DEAL ERA QUESTO: ALEXANDE= R BOETTCHER INCULAVA L'OMOSESSUALE, SPESSO PURE DI TIPO PEDOFILO, GIULIO TR= EMONTI ..COME QUESTO TWITTER ACCOUNT FA STRA INTUIRE https://twitter.com/al= exanboettcher .. E L ^ OCCULTISSIMO" MASSONE LAVA SOLDI MAFIOSI, OMOSESSUAL= E DI TIPO PERVERTITO, GIULIO TREMONTI, CERCAVA DI FARLO SFONDARE IN POLITIC= A..ALLA FINE, PERO', L'UNICA COSA SFONDATA ERA IL DI DIETRO DEL CULACCHIONE= "CHIC LE FREAK" GIULIO TREMONTI STESSO). CON ALTRI PEDERASTA QUALI GIULIANO FERRARA E CLAUDIO CERASA ( DE IL FOGLIO,= SI, MA DA USARSI SOLO X PULIRSI L'ANO IN CASO DI FINE DI CARTA IGIENICA AN= D NEVER FORGET, IL VERME CLAUDIO CERASA DA PALERMO E' AFFILIATO A COSA NOST= RA DA DECENNI: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO.. E' IL NUOVO MARCEL= LO DELL'UTRI, DI FATTO). OLTRE CHE IL GIA' 3 VOLTE IN CARCERE, PAOLO BARRAI DI FALLIMENTARE BLOG "ME= RDATO"LIBERO, IL GIA' 2 VOLTE IN CARCERE, VINCENZO BARRAI DI DELINQUENZIALI= SSIMA BSI ITALIA SRL VIA SOCRATE 26 MILANO, IL NOTO GIOVANE PEDERASTA RICCA= RDO BARRAI ORA PRESSO UNIVERSITY OF READING, IL VERME MALAVITOSO STEFANO BA= SSI DI MEGA TRUFFATORE BLOG IL GRANDE BLUFF, IL NOTO AVVOCATO PEDOFIL-O-MOS= ESSUALE ED ASSASSINO DANIELE MINOTTI DI GENOVA E RAPALLO, OLTRE CHE ALESSAN= DRO CECCHI PAONE, NOTO IN TUTTO IL MONDO COME ALESSANDRO "CHECCHI" PAONE. S= PESSISSIMO SON LI PRESENTI ANCHE I BANCHIERI MALAVITOSI DI BANCA MEDIOLANUM= , GLI OMOSESSUALI E CRIMINALISSIMI GIOVANNI PIROVANO, MASSIMO DORIS, ANGELO= RENOLDI ED OSCAR DI MONTIGNY. IVI FANNO ORGE SU ORGE ANCHE CON RAGAZZINI D= I 14 ANNI!! IN DARK ROOMS! SI, E' PROPRIO COSI' E STRA COSI': E' UNO SCHIFO= SISSIMO PEDOFIL-O-MOSESSUALE, IL VERME BERLUS-CO-RROTTO PAOLO CARDENA'!!! P= AGA ADOLESCENTI ROM DI 10-14 ANNI, PER INCULARLI A SANGUE! VA' IN CAMPI ROM= PADANI, DUE, TRE VOLTE ALLA SETTIMANA, AT 4 AM, IN PIENA NOTTE, A PAGARE Z= INGARELLI, PER INCULARLI TERRIFICANTEMENTE ( QUI IN UNA FOTO CHE GLI ABBIAM= O FATTO, MENTRE IN MUTANDE, FISSA, CON SGUARDO DA DEPRAVATO SESSUALE MAXIMO= , UN BAMBINO DI OTTO ANNI, NELLE ADIACENZE DI UN CAMPO ROM PADANO...CHE MEZ= Z'ORA DOPO INCLUERA' A SANGUE...LO STAVAMO PEDINANDO DA MESI E MESI E MESI,= ABBIAMO FOTOGRAFATO E VIDEATO IL TUTTO http://a.mytrend.it/authors/1385.jp= g .. PRESTISSIMO, OGNI DOVUTA COSA, PRESTO, IN VISIONE, SU INTERNET)! TUTTI QUESTI EFFERATISSIMI CRIMINI, SIA DI TIPO PEDERASTA, CHE DI RICICLAGG= IO DI SOLDI ASSASSINI, OSSIA CASH CHE COLA FIUMI DI SANGUE DI MORTI AMMAZZA= TI DI MAFIA, CAMORRA, NDRANGHETA, SONO EFFETTUATI IN CONNESSIONE COL MANDAN= TE DI OMICIDI, RAZZISTA, KU KLUK KLANISTA, LADRO, TRUFFATORE, CORROTTISSIMO= , SEMPRE FALSO, ESTORTORE DI SOLDI, MEGA STALKER SU INTERNET, GIA' 3 VOLTE = IN CARCERE, CACCIATO A SBERLE DA CITIBANK, INDAGATO DA 7 PROCURE ITALIANE E= DALLA PROCURA DI LUGANO, MEGA MULTATO DALLA CONSOB, ORGANIZZANTE "LA SUICI= DAT-A-SSASSINA" DI DAVID ROSSI DI MONTE PASCHI: BASTARDO ASSASSINO PAOLO PI= ETRO BARRAI. E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZIRAZZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965= . NONCHE' MEGA RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI M= EGA RUBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA E STRAGISTA SPAPPOLA = MAGISTRATI, NONCHE', TANTO QUANTO, NAZIFASCISTA DITTATORE E PEDOFILO: SILVI= O BERLUSCONI! 4 DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERRORISTA N= AZISTA ED ASSASSINO, PAOLO BARRAI. NON PER NIENTE, GIA' STATO IN GALERA 3 V= OLTE. OPINIONI TUTTE TERRIFICANTI SU DI LUI! MEGA TRUFFATORE E MEGA RICICLA CASH = ASSASSINO VIA CRIMINALISSIMA BLOCKCHAIN INVEST O VIA CRIMINALISSIMA BLOCKCH= AININVEST CHE SIA, OLTRE CHE VIA CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALIS= SIMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA E CRIMINA= LISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO! NOTO PEDOFIL-O-MOSESSUALE = SODOMIZZA BAMBINI E RAGAZZINI! CACCIATO DA CITIBANK A SBERLE, PER MEGA FROD= I CHE LI FACEVA! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI DI TANTISSIME P= ERSONE! FALSO&LADRO&TRUFFATORE! DIFFAMA SUL WEB A FINI NAZI-RAZZISTI! FONDA= TORE DEI NUOVI MEGASSASSINI TERRORISTI DI ESTREMISSIMA DESTRA: "NUOVI NAR" FONDATORE DEL, PROSSIMAMENTE, DI FREQUENTE, OMICIDA: KU KLUK KLAN PADANO! C= ONDANNATO AL CARCERE A MILANO ED IN BRASILE ( 8 ANNI E PURE PER PEDERASTIA = OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE)! MULTATO DA CONSOB 70= .000 =E2=82=AC! DESTABILIZZA L'ITALIA PER FILO NAZISTI SERVIZI SEGRETI SVIZ= ZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTISSIMAMENTE, NAZIONE SCHIFATA IN = TUTTO IL MONDO, IN QUANTO FASCIOMAFIOSA DITTATURA DI BERLUSCONIA.. NON PER = NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITALIA DA SECOLI, DALLA TIRANNIA= SSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIAT, PIRELLI, LUXOTTICA, MERLON= I E MIGLIAIA E MIGLIAIA DI ALTRE... E CHE SIA CHIARO, PLS, CHE IDDIO BENEDI= CA I GRANDI PM CHE NON SOPPORTANTO IL CANCRO DEL MONDO INTERO, SILVIO BERLU= SCONI, COME HENRY WOODCOCK, ILDA BOCASSINI E CHIUNQUE ALTRO DI QUESTA AMMIR= EVOLISSIMA CATEGORIA)! FA CRIMINI SU CRIMINI E NAZI-ST-ALKING, SU INTERNET,= SU ORDINE DEI PUZZONI CRIMINALISSIM SILVIO BERLUSCONI, PAOLO BERLUSCONI ED= UBALDO LIVOLSI DI FININVEST ( CHE DA ANNI FANNO GLI ADOLPH HITLER MISTI AD= AL CAPONE, DEL WEB, ANCHE, MA DI CERTO, NON SOLO, CON QUEL VERME SCHIFOSAM= ENTE TERRORISTA DI GIULIO OCCHIONERO). INNEGGIANTE ALLO SPAPPOLAMENTO DI MA= GISTRATI SCOMODI "COME BERLUSCONI GRANDISSIMAMENTE FECE CON FALCONE E BORSE= LLINO"! PAROLE SUE, DETTE SPESSISSIMO! ORGANIZZANTE OMICIDIO DI DAVID ROSSI= DI MONTE PASCHI! VAMONOS BABIES, VAMONOS, VAMONOS, LET'S GO...... - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA EIDOO, DIRETTA DAL VERME MALAVITOSO NATALE M. FERRARA O NATALE FER= RARA CHE SIA https://ch.linkedin.com/in/natale-ferrara ( EXTREMELY CRIMINAL= EIDOO : YOUR VERY HOODLUM ASSET EXPERIENCE, MEGA MAFIA MONEY LAUNDERER FOR= COSA NOSTRA, NDRANGHETA, CAMORRA AND ASSASSIN RUSSIAN GANSGTERS, NOT FOR N= OTHING, CLOSE TO PRINCIPAL OF MURDERS, SLAUGHTERS AND ASCERTAINED PEDOPHILE= SILVIO BERLUSCONI) - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA CRYPTOPOLYS ( OVE MEGA RICICLA SOLDI MAFIOSI COL NOTO VERME KUKLUK= LANISTA, NAZIFASCISTA, MEGA RICICLA SOLDI MAFIOSI, BASTARDO VERO ARON CAMPO= NOVO DI MALAVITOSISSIMA TANTO QUANTO IBEX CAPITAL LTD, MALAVITOSISSIMA TANT= O QUANTO MONCLER SUISSE LTD, MALAVITOSISSIMA TANTO QUANTO IBEX SERVICES LTD https://www.linkedin.com/in/aron-camponovo-a0030094 ED IL NOTO RAZZISTA, KU= KLUKLANISTA, HITLERIANO, MEGA RICICLA SOLDI DI MALAVITE DI TUTTO IL MONDO E= D ACCERTATO PEDOFILO INCULA BAMBINI: OLIVER CAMPONOVO DI CAMPONOVO STRATEGY= https://ch.linkedin.com/in/oliver-camponovo-cfa-ciia-1786935) -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA, SEMPRE MEGA RICICLA SOLDI MAFIOSI, BITINCUBATOR VENTURES GRONO (CH= ) ( AFFIANCATO IN QUESTO DA QUEL NOTO PORCO PEDOFILO DI CLAUDIO LEVRINI DI = MALAVITOSA BITCOIN FOUNDATION, E, BEN APPUNTO, DI CRIMINALISSIMA BITINCUBAT= OR VENTURES GRONO) https://www.moneyhouse.ch/en/company/bitincubator-ventures-sa-12554072241 5 - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI BLOCKC= HAIN INVEST - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMIN= ALISSIMA BIGBITGOLD E CRIMINALISSIMA BIGBIT -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA WORLD MAN OPPORTUNITIES LUGANO -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINA= LISSIMA WMO SA PANAMA IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI LEGA LAD= RONA -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI FORZA I= TALIA MAFIOSA -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI GIORNAL= E HITLERIANO: LIBERO - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI TANTIS= SIMI GRUPPI NAZISTI ED ANTI SEMITI -IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI ASSASSI= NO KU KLUK KLAN - IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI GRAN L= OGGIA ITALIA MASSONICA DEL MALAVITOSO BANCHIERE GIUSEPPE SABATO DI BANCA ES= PERIA ( GRUPPO BANCARIO DELLO SPAPPOLA MAGISTRATI, NONCHE' ACCLARATISSIMO P= EDOFILO SILVIO BERLUSCONI) - IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA = MALAVITOSA ELIGOTECH, DELL'OMOSESSUALE ^OCCULTO^ LUIGI BERLUSCONI http://ww= w.tuttouomini.it/images/luigi-berlusconi-bacio-gay-estate-amico.jpg ( NIPOT= E DEL TOPO DI FOGNA LUIGI BERLUSCONI, A SUA VOLTA, BESTIA CRIMINALE DELLA C= HIUSA PER MEGA RICICLAGGIO DI SOLDI MAFIOSI, BANCA RASINI http://temi.repub= blica.it/micromega-online/mafia-politica-e-affari-sette-domande-al-cavalier= e/?printpage=3Dundefined E FIGLIO DI NOTO PEDOFILO SILVIO BERLUSCONI http:/= /www.elafter.com/foro/showthread.php?t=3D948509, DI NOTO MANDANTE DI DOZZIN= E DI STRAGI SILVIO BERLUSCONI http://www.vnews24.it/2014/05/29/borsellino-s= entenza-choc-stragi-commissionate-berlusconi/http://www.ilfattoquotidiano.i= t/2017/06/09/graviano-e-berlusconi-peter-gomez-ricostruisce-le-stragi-del-1= 993/3648613/ , DI NOTO MANDANTE DI CENTINAIA E CENTINAIA DI OMICIDI MASCHER= ATI, SILVIO BERLUSCONI http://www.pmli.it/sismicolpivanemiciberlusconi.htm) - IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA = MALAVITOSA CGNAL DI MARCO CARRAI http://espresso.repubblica.it/plus/articol= i/2016/10/17/news/marco-carrai-l-amico-che-mette-matteo-renzi-nei-guai-1.28= 5898(CANZONCINA CHE STIAMO PREPARANDO, CON QUESTO VINCENTISSIMO CHORUS: "A = COSA NOSTRA, CAMORRA E NDRANGHETA, IL BUCATO FINANZIARIO TU LO FAI: RICICLA= SOLDI MAFIOSI PAOLO BARRAI, RICICLA SOLDI MAFIOSI MARCO CARRAI) - IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA = MERDA FASCIOMAFIOSA DI ENNIO DORIS E MASSIMO DORIS: BANCA MEDIOLANUM, COSAN= OSTRANUM, CAMORRANUM, NDRANOLANUM -IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIM= INALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO. - IL IL PRIMA CITATO DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI, NATO = A MILANO IL 28.6.1965, FINITO "APPENA APPENA" 3 VOLTE IN GALERA 6 TORNIANO AL DOVUTISSIMO PUNTO INIZIALE, ORA, PLEASE. I SATANISTI, NAZIFASCI= STI, PEDERASTA ED ASSASSINI PAOLO CARDENA' E STEFANO CARDENA' DI CARDENA' C= ONSULTING, COME DETTO, SONO DIETRO TANTISSIMI CASI DI RAPIMENTI STUPRI, UCC= ISIONI ED OCCULTAMENTO DI CADAVERI DI BAMBINI E NON SOLO. ANZI, SON PROTAGO= NISTI DI QUESTE UCCISIONI SU UCCISIONI ( A CENTINAIA E CENTINAIA: A MIGLIAI= A). SONO I CAPI, ANZI, SONO I KAPO' DELLA NOTA SETTA " I MAIALI MACERATESI = DI SATANA"! MACERATA E' CITTA' DA SEMPRE, LUCIFERINISSIMA, CON UNO FRA I PI= U' ALTI TASSI MONDIALI DI UCCISIONI DI PERSONE E A SEGUITO, LORO SPARIZIONI= ( COL TUTTO TANTISSIMO SUPERIORE AI GIA' TASSI MOSTRUOSI DI NOTISSIME IN Q= UESTO: NEW ORLEANS NEGLI USA, CIUDAD JUAREZ IN MESSICO, RIO DE JANEIRO IN B= RASILE, DAMASCO IN SIRIA, TRIPOLI IN LIBIA, BAGDAD IN IRAQ). E QUESTO COME = DA TANTI, TANTI, TANTISSIMI LINKS CHE VI SONO IN RETE. DA CUI NE PRENDIAMO = SOLO DUE, AL VOLO, PER OVVI MOTIVI DI TEMPO E SPAZIO DIGITALE http://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche-= si-cercano-558-persone/811406/ https://www.ilrestodelcarlino.it/macerata/cronaca/ragazza-scomparsa-14-anni= -ansia-1.3410852 EBBENE, I PEDOFILI BASTARDISSIMAMENTE ASSASSINI PAOLO CARDENA' E STEFANO CA= RDENA' DI CRIMINALISSIMA CARDENA' CONSULTRING FURONO ANCHE I RESPONSABILI D= ELLA UCCISIONE DI PAMELA MASTROPIETRO: STUPRATA, UCCISA E POI SEZIONATA CON= EXPERTISE TIPICA DI MEDICI LEGALI MASSONICI E BIANCHI, MARCHIGIANI, MACERA= TISSIMI ( E NON UCCISA E SEZIONATA DA VERMI FANS DEL WODOO, NIGERIANI, SE M= AI PAGATI, POI, PER PRENDERSI LA COLPA..PER LORO, 30 ANNI IN CARCERE, DA VA= RI PUNTI DI VISTA, PUO' ANCHE ESSERE UNA SPECIE DI MACABRO AFFARE: VITTO E = ALLOGGIO SONO ASSICURATI PER SEMPRE, NON INTENDO ESSERE CINICO, MA SOLO FOT= OGRAFICO, IL MONDO E' PIENO DI CASI DEL GENERE.... GOOGLE VINCENZO SCARANTI= NO... O VEDI BERLUSCONIANISSIMA STRAGE DI BRINDISI). MASSONI FOTOCOPIA DELL= A GANG SANGUINARISSIMA E MASSONICISSIMA, AI TEMPI, DEL MOSTRO DI FIRENZE! P= OTRESTE RAGLIARE DA DENTRO I VOSTRI ASSASSINI CAPPUCCI " WAGLIO', E' ARRIVA= TO SHERLOCK HOLMES DEI POVERI, COME FAI A DIRE UNA COSA DEL GENERE"? LA MIA= RISPOSTA? MA CHE STATE GRUGNENDO, STARNAZZANDO, RAGLIANDO? MICA IO LO DICO= IO, CHE SONO UN CONSULENTE FINANZIARIO ITALO INGLESE, GIA' MANAGER DI NOTI= SSIMA BANCA D'AFFARI AMERICANA. LO DICE UNO DEI GRAN MAESTRI FILO PIDUISTI = CHE PIU' SAN DI TUTTO QUESTO, IMMERSO DA SEMPRE IN MARI DI COMPLOTTI, OMICI= DI, SPARIZIONI DI MATRICE MASSONICO NAZIFASCISTA, ALIAS DI MATRICE NEO BERL= USCONICCHIA: L' AMMIRABILISSIMO, NEL FARNE SAPERE A TUTTI, GIANFRANCO PERCO= RARO CARPEORO, EX NUMERO UNO DI TUTTI I TEMPI, DELLA MASSONERIA DI RITO SCO= ZZESE, DICIAMO COSI'... DI STAMPO "BERLUSCONICCHIO" https://www.youtube.com/watch?v=3DDuJQGxmAvnk A FRA POCO PER MILIARDI DI ALTRI DETTAGLI SU DETTAGLI A PROPOSITO. SOON BAC= K! From newsfish@newsfish Thu Aug 1 00:44:21 2024 X-Received: by 2002:a0c:d0ef:: with SMTP id b44mr6740949qvh.61.1555008668528; Thu, 11 Apr 2019 11:51:08 -0700 (PDT) X-Received: by 2002:a81:a38b:: with SMTP id a133mr39030298ywh.423.1555008668263; Thu, 11 Apr 2019 11:51:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!t9no3779543qtn.0!news-out.google.com!i8ni1766qtr.1!nntp.google.com!t9no3779542qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Apr 2019 11:51:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=77.26.200.36; posting-account=v4kPxAoAAAAwxTgbyCQJmQN_-O8qB5LL NNTP-Posting-Host: 77.26.200.36 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <73413c34-5880-406a-88ef-c2c908d19b74@googlegroups.com> Subject: LA LURIDA PUTTANA FRANCESCA VERDINI SE LA FA CON L'ASSASSINO NAZISTA E NDRANGHETISTA MATTEO SALVINI! CHE HA 20 ANNI PIU' DI LEI O QUASI. E' FIGLIA DEL MASSONE PEZZO DI MERDA DENIS VERDINI, UN FASCISTA MALAVITOSISSIMO, CHE HA PIU' CONDANNE AL CARCERE From: "LUIGI BISIGNANI - MAI PIU' COL PEDOFILO BERLUSCONI" Injection-Date: Thu, 11 Apr 2019 18:51:08 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 33554 X-Received-Body-CRC: 3571763989 Lines: 553 Xref: reader01.eternal-september.org comp.lang.vhdl:9454 LA LURIDA PUTTANA FRANCESCA VERDINI SE LA FA CON L'ASSASSINO NAZISTA E NDRA= NGHETISTA MATTEO SALVINI! CHE HA 20 ANNI PIU' DI LEI O QUASI. E' FIGLIA DEL= MASSONE PEZZO DI MERDA DENIS VERDINI, UN FASCISTA MALAVITOSISSIMO, CHE HA= PIU' CONDANNE AL CARCERE.........LUI CHE AL CAPONE E RENATO VALLANZASCA ME= SSI INSIEME ( E CHE E' SEMPRE LI A LECCARE IL CULO, ORA AL MASSONE PEDOFILO= SPAPPOLA MAGISTRATI SILVIO BERLUSCONI, ORA AL MASSONE BERLUSCORROTTO MATTE= O RENZI, ORA AL MASSONE BERLUSMAZZETTATO MATTEO SALVINI, PER VEDERE DI SGOZ= ZARE I TANTISSIMI PROCESSI, CHE UN CRIMINALE FIGLIO DI CANE E LAVA SOLDI MA= FIOSI, COME DENIS VERDINI, HA IN MEZZA TIRANNIA DI BERLUSCONIA... ALIAS EX = REPUBBLICA ITALIANA)! https://www.ilfattoquotidiano.it/2018/07/03/processo-credito-fiorentino-den= is-verdini-condannato-a-6-anni-e-10-mesi-in-appello/4467756/ https://www.ilfattoquotidiano.it/2018/09/13/denis-verdini-condannato-a-5-an= ni-e-mezzo-per-bancarotta-fraudolenta-de-il-giornale-della-toscana/4623501/ https://www.giornalettismo.com/archives/2057063/processi-denis-verdini ED A PROPOSITO DEL FIGLIO DI CANE HITLERIANO, KU KLUK KLANISTA, LADRO DI "S= OLO" 49 MILIONI DI EURO E MEGA OMICIDA MATTEO SALVINI.. IL FIGLIO DI PUTTANA ASSASSINO MATTEO SALVINI (I CUI SCHIFOSAMENTE NAZISTI = FIGLI MIRTA SALVINI E FEDERICO SALVINI, FIGLI ANCHE DI NOTE "FASCISTROIE" F= ABRIZIA IELUZZI E GIULIA MARTINELLI, DI LUI, UN GIORNO, SI STRA VERGOGNERAN= NO) FA LA PUBBLICITA' ALLA MERDOSA NUTELLA, IN QUANTO I CRIMINALISSIMI FERR= ERO, SON DA SEMPRE FASCISTI, RAZZISTI E SATANISTI COME LUI. "Mio figlio, passato dalle Bestie di Satana alla Lega Nord" https://www.youtube.com/watch?v=3DCrfIbm-9wHY http://www.dagospia.com/rubrica-3/politica/ldquo-vade-retro-salvini-rdquo-n= dash-copertina-39-39-famiglia-179527.htm SON BASTARDI KU KLUK KLANISTI COME LUI ( https://www.ilfattoquotidiano.it/2= 019/01/16/ovetti-kinder-accusati-di-razzismo-la-sorpresa-ha-il-simbolo-del-= ku-klux-klan-e-il-ciuffo-di-donald-trump-manda-messaggi-subliminali/4901191= / ) 1 LO FA ANCHE IN QUANTO ALLA CRIMINALISSIMA FONDAZIONE FERRERO DI ALBA E PURE= ALLA CRIMINALISSIMA FRUIMEX SAS DI ALBA, LAVORA UNA NOTA PUTTANA LUCIFERIN= A, HITLERIANA, RAZZISTA E MOLTO ASSASSINA TANTO QUANTO: ELISA COGNO https://www.instagram.com/p/Bcc0zWonbtv/ (DIETRO TANTI OMICIDI DA LEI ESEGUITI, DI SATANISTI, AVVENUTI IN SUA ZONA https://www.altriconfini.it/2013/06/lombra-delle-sette-sataniche-nei-suicid= i-in-provincia-di-cuneo/ https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.notizieprovita.it/notizie-dallitalia/satanismo-in-fiera-da-vita= -a-proteste-indignate/ PARTE PURE DELLA SETTA SANGUINARISSIMA PIEMONTESE " AMMAZZIAMO PER SATANA" = E DI MERDONI SVASTIKATI DI BLOOD AND HONOR). CHE E' BEN APPUNTO DI ALBA (SC= RIVEREMO DI LEI ANCHE ALLA FINE DI QUESTO TESTO). ED E' PAPPA E CICCIA CON = IL NOTO PADANAZISTA, SATANISTA E PURE MOLTO OMICIDA MAURIZIO BARBERO DI TEC= HNOSKY MONTESETTEPANI, https://it.linkedin.com/in/maurizio-barbero-a521978 https://pbs.twimg.com/profile_images/698221802565279744/7hEZuIO__400x400.jp= g IL TUTTO E' CONNESSISSIMO ALLA MEGA TROIA ANCORA PIU' SATANISTA E NAZIFASCI= STA, SUA (FINTA) EX: ELISA ISOARDI! NON PER NIENTE, ANCHE LEI DI CUNEO ( CO= ME DI CUNEO E' LA KAPO' PUZZONA DI TUTTI STI TOPI DI FOGNA ASSASSINI, LA MO= STRUOSA BAGASCIA, MEGA COCAINOMANE, SEMPRE CON MILLE CAZZI IN CULO: DANIELA= SANTANCHE' ... O MOSTRUOSA BAGASCIA, MEGA COCAINOMANE, SEMPRE CON MILLE CA= ZZI IN CULO: DANIELA GARNERO SANTANCHE' ). 2 AND NEVER FORGET, PLEASE: IL MARITO, FIGLIO E CAMERATA DI PUTTANE MATTEO SA= LVINI STA CREANDO LISTE DI PROSCRIZIONE OMICIDA, SI OMICIDA ( BASTA CHE GUA= RDATE QUESTI NAZISTISSIMI, ASSASSINI DI DEMOCRAZIA, ARTICOLI E VIDEOS https://globalist.it/media/2018/12/15/un-cartello-con-scritto-ama-il-prossi= mo-tuo-picchiato-e-portato-via-a-forza-dal-comizio-di-salvini-2034955.html https://www.lastampa.it/2018/12/15/italia/jacopo-e-natalia-fermati-in-piazz= a-per-il-cartello-ama-il-prossimo-tuo-vlBRbvbI1ikvQEpMpLKprO/pagina.html https://it.blastingnews.com/cronaca/2018/11/roma-casalinga-60enne-da-del-bu= ffone-a-salvini-fermata-e-denunciata-002771157.html https://www.youtube.com/watch?v=3D3ENKQI5f5tA PER NON PARLARE DI COME ABBIA FATTO CREPARE 1000 PERSONE IN MARE, STO BASTA= RDO PINOCHETTIANO OMICIDA DI MATTEO SALVINI, DA QUANDO COLERIZZA IL VIMINAL= E https://www.ilfattoquotidiano.it/2018/06/28/migranti-romano-salvini-spieg= hi-in-parlamento-morte-120-persone-scontro-con-borgonovo-che-lascia-la-tras= missione/4458573/ )! BUT FIRST, LET'S GO WORLDWIDE WITH THIS, BABY! MAFIOSO, FASCIST, DEPRAVED PEDOPHILE DONALD TRUMP TOGETHER AT NAZIST KILLER= VLADIMIR PUTIN USE CORRUPT, PROTECTOR OF CAMORRA, NDRANGHETA & COSA NOSTRA= , AS WELL AS RACIST, KUKLUKLANIST, SCAMMERS, LIARS, THIEFTS, MAFIA MONEY LA= UNDERERS, PRINCIPAL OF.....HUNDREDS OF (MASKED) HOMICIDES AND DOZENS OF SLA= UGHTERS, MEGA CRIMINAL DICTATORS AND ASSASSIN MATTEO SALVINI AND SILVIO BER= LUSCONI, TO DESTABILIZE, THEN DESTROY, THEN DISINTEGRATE EUROPE!!! ED ORA VAMOS A FARE LA STORIA, DE VERDAD !!!!!! BY SIMONA PREMOLI. FOR 13 YEARS MARINA BERLUSCONI'S NUMBER ONE LESBIAN LOVE= R ( BETWEEN HUNDREDS). EX CIA AGENT IN MANY COUNTRIES OF THE WORLD ( IN MY = CITY OF MILAN, IN LONDON, IN ZURICH, IN BERLIN, IN DOMINICAN REPUBLIC, IN P= UERTO RICO, IN WASHINGTON DC). VERY WELL KNOWN MASKED PORNSTAR. FEMALE FREE= MASON OF VERY HIGH DEGREE. INTEPRETER ( ITALIAN, ENGISH, SPANISH). DIRTY MO= NEY LAUNDERER FOR NAZIST ASSASSIN MATTEO SALVINI FROM LEGA NORD ( BETTER KN= OWN AS LEGA LADRONA) AND FOR MEGA PRINCIPAL OF MURDERS AND SLAUGHTERS, SLIM= Y, CRIMINAL PEDOPHILE SILVIO BERLUSCONI. BY SIMONA PREMOLI DI MILANO. PER 13 ANNI, NUMERO UNO, FRA CENTINAIA E CENTI= NAIA DI AMANTI LESBICHE DI MEGA COCAINOMANE, CRIMINALISSIMA MARINA BERLUSCO= NI. EX AGENTE CIA IN MIA CITTA' DI MILANO, COME IN ROMA, BERLINO, ZURIGO, L= ONDRA, REPUBBLICA DOMINICANA, PORTORICO, WASHINGTON DC. CONOSCIUTISSIMA E C= ALDISSIMA PORNOSTAR, MA SEMPRE E SOLO CON MASCHERINA, PER, OVVIAMENTE, NON = INTRALCIARE MIEI MOLTO IMPORTANTI LAVORI SOPRA CITATI. GRAN MAESTRO MASSONI= CO. INTERPRETE ( IN TANTI DICONO, CHE PIU' CHE INTERPRETE, CHE SONO " ESPER= TISSIMA NELL'USO DELLA LINGUA). RICICLATRICE DI SOLDI CRIMINALISSIMI DI LEG= A LADRONA ( FAMOSI 49 MILIONI RUBATI, MA NON SOLO) E DI SPAPPOLA MAIGSTRATI= , NONCHE' VOMITEVOLE PEDOFILO SILVIO BERLUSCONI. 3 ECCO ORA UN MIO TESTO, DICENTE, VE LO ASSICURO, TANTE ASSOLUTISSIME E DIMOS= TRABILISSIME VERITA'. IL FIGLIO DI PUTTANA ASSASSINO MATTEO SALVINI (I CUI FIGLI NAZISTI FIGLI MI= RTA SALVINI E FEDERICO SALVINI, FIGLI PURE DI NOTE "FASCISTROIE" GIULIA MAR= TINELLI E FABRIZIA IELUZZI, DI LUI, UN GIORNO, SI STRA VERGOGNERANNO), INSI= EME ALLA SCOPATA IN CULO DA MILLE MASSONI FILO MAFIOSI, NOTA PUTTANA ELISA = ISOARDI ( MEGA COCAINOMANE TROIA ELISA ISOARDI, PURE SU INSTAGRAM), STA CRE= ANDO LISTE DI PROSCRIZIONE OMICIDA! SI, OMICIDA! HA FATTO CREPARE 2000 PERS= ONE IN MARE, STO HITLERIANO KILLER DI MATTEO SALVINI, DA QUANDO COLERIZZA I= L VIMINALE https://www.ilfattoquotidiano.it/2018/06/28/migranti-romano-salvini-spieghi= -in-parlamento-morte-120-persone-scontro-con-borgonovo-che-lascia-la-trasmi= ssione/4458573/ http://www.ilsussidiario.net/News/Cronaca/2018/7/17/Saviano-choc-contro-Sal= vini-ti-eccitano-bimbi-morti-in-mare-Caso-Open-Arms-Ministro-Malavita-assas= sino-/830817/ E TUTTE LE UCCISIONI E VIOLENZE FISICHE A MIGRANTI DEGLI ULTIMI MESI, SON D= OVUTE, VOLUTE, INCITATE ED ORGANIZZATE DA LUI: E DI QUESTO NON NE PARLO CHI= SSA' QUANTO, IO, NE PARLA IL PER BENE PRESIDENTE DELLA REPUBBLICA SERGIO MA= TTARELLA, NON PER NIENTE, DI AMMIRABILE, NON "BERLUSCORROTTO" TIPO DI CENTR= O SINISTRA https://www.corriere.it/politica/18_luglio_25/mattarella-il-veleno-razzismo= -continua-creare-barriere-societa-b1f70e9e-8fee-11e8-9e3d-9a7bf81b9c8e.shtm= l ..... OGNI TANTO, QUESTO FIGLIO MEGA COCAINOMANE E BASTARDO FIGLIO DI NAZIS= TROIA MATTEO SALVINI (TWITTER, FACEBOOK, INSTAGRAM, WIKIPEDIA) FA FOTO CON = VENDITORI DI COLORE O FA ELEGGERE SUOI SCHIFOSI, CORROTTISSIMI, LECCA CULO = DI COLORE, MA E' TUTTO PURO DEPISTAGGIO, CONOSCO PERSONALISSIMAMENTE STO TO= PO DI FOGNA DI MATTEO SALVINI DA 20 ANNI, SO' CHE E' DA SEMPRE RAZZISTISSIM= O, BASTA VEDERE QUI, COME UMILIAVA A MORTE I GRANDI UOMINI E DONNE EI NAPUL= E https://www.politicaeattualita.it/2018/02/26/quando-matteo-salvini-cantava-= senti-che-puzza-scappano-anche-i-cani-stanno-arrivando-i-napoletani-video/ = ! IL FIGLIO DI PUTTANA MATTEO SALVINI VUOLE FAR AMMAZZARE CHIUNQUE LO FOTOGRA= FI PER IL NUOVO ADOLPH HITLER ASSASSINO CHE EGLI ALTRO NON E', FACENDO PASS= ARE OMICIDI DA LUI ORDINATI, PER "SOLITI" FINTI SUICIDI, MALORI, INCIDENTI!= OLTRE CHE TSO KILLER! COME GIA' ACCADETTE, NON PER NIENTE, A RAFFICA, FRA IL 2001 ED IL 2006, COM= E FRA IL 2008 ED IL 2011. ALLORCHE' IL PEDOFILO SPAPPOLA MAGISTRATI SILVIO = BERLUSCONI, INSIEME AI KUKLUKLANISTI, NDRANGHETISTI E NAZISTI ASSASSINI DI = LEGA LADRONA, ORDINO' DI "DISARTICOLARE LA VITA IN MANIERA TRAUMATICA", OSS= IA DI UCCIDERE FACENDO PASSARE IL TUTTO PER QUALSIASI COSA CHE PARESSE NON = UN OMICIDIO, MA CHE OMICIDIO STRA ERA, CHIUNQUE NON LECCASSE IL DI DIETRO D= ELLE MERDE SANGUINARIE, ASSASSINE, FASCIOMAFIOSE E NAZINDRANGHETISTE, CHE A= LTRO, TUTTI QUESTI, NON SONO ( PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCO= NI IN PRIMIS)! COME QUANDO GLI ASSASSINI MATTEO SALVINI, ROBERTO MARONI ED UMBERTO BOSSI O= RDINARONO E DAVANTI AI MIEI OCCHI, DI " SBULLONARE A MORTE" GLI ELICOTTERI = DI GIORGIO PANTO E PAOLO ALBERTI, FACENDO SFRACELLARE MORTALMENTE I DUE AL = SUOLO. PER FAR LORO AGARE L' ESSERE PASSATI CON OTTIMO ROMANO PRODI, NEL 20= 06!!! 4 IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 5 E POI ANCORA.. http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://forum.enti.it/viewtopic.php?t=3D66625 http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm 6 E STRA ANCORA.. https://www.agoravox.it/Documenti-segreti-made-in-Italy.html https://www.ariannaeditrice.it/articolo.php?id_articolo=3D6352 ALTRE DUE COSE, PLEASE. PRIMA. GLI ATTENTATI DI VARIO TIPO A CREMONA, TREVISO E BERGAMO, LEGA LADRO= NA, NAZISTA ED ASSASSINA, SE LI FA DA SOLI. PER FAR PASSARE IL NUOVO BASTAR= DO ADOLPH HITLER, CHE E' E STRA E' MATTEO SALVINI, PER VITTIMA. QUANDO E' S= OLO UN BAS.ARDO, ASSASSINO CARNEFICE. AFFINCHE' POSSA ESSERE OMICIDA PAZZO = CARNEFICE ANCORA DI PIU'. CLASSICA TATTICA DEL LUPO CHE SI METTE LA TESTA D= I AGNELLO, PER, DI NOTTE, POTER SBRANARTI MEGLIO. http://studiovanelli.com/wp-content/uploads/2017/03/Eliseu-Antonio-Gomes_E.= A.G._UBE-Blogs_UniC3A3o-de-Blogueiros-EvangC3A9licos_falso-pastor-pastor-jo= io.jpg SECONDA IMPORTANTISSIMA COSA. E' DA SEMPRE UNA SATANISTA E NAZISTA, OSSIA, = UNA SATANAZISTA PUTTANA: ELISA ISOARDI (FIGLI - INSTAGRAM). I CUI GENITORI,= NON PER NIENTE, SONO UN MASSONE PLURI OMICIDA DI CUNEO, CHE, NEGLI ANNI 80= E 90, HA AMMAZZATO E SOTTERRATO NEI BOSCHI LOCALI, ALMENO 60 PERSONE. COME= DA COTANTO DI SEGUENTI LINKS http://www.lastampa.it/2015/08/01/cuneo/scomparsi-da-anni-resta-il-mistero-= Q1u3ZmsLrLVEH43wjtxC8N/pagina.html https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ ED UNA NOTA PUTTANONA SEMPRE SCOPATA DENTRO AL CULO: IRMA ISOARDI ( TROIONA= COME ELISA ISOARDI: SANGUE MARCIO MAI MENTE). CHE NEGLI ANNI 80 E 90, SI C= HIAVAVANO TUTTI, SIA NELLA FIGA CHE NELL'ANO, NEI CLUB PRIVE' DI FRANCIA, P= IEMONTE, LIGURIA E LOMBARDIA. COME IN TANTE SETTE SATANICHE E LOGGE MASSONI= CHE, SEMPRE DI FRANCIA, PIEMONTE, LIGURIA E LOMBARDIA. DOPO QUESTO DOVUTISSIMO ANTIPASTINO, ORA I PIATTI FORTI. PRIMA, PERO', IF YOU DON'T MIND, MI PRESENTO. SONO SIMONA PREMOLI. NOTA PORNOSTAR IN TUTTO IL MONDO. LAUREATA IN SCIENZE = POLITICHE ALLA CATTOLICA DI MILANO. "ASSOLUTA ESPERTA NELL'USO DELLA LINGUA= " INTESO NEL SENSO CHE SONO INTERPRETE ( MA ANCHE INTESO IN "ALTRI SENSI"). 7 E SPECIALMENTE: EX AGENTE CIA A LIVELLO MONDIALE. A MILANO, COME IN TANTE A= LTRE VARIE CITTA' DI BERLUSCONIA-LEGALADRONUSCONIA-RENZUSCONIA-DIMAIOUSCONI= A, COME A WASHINGTON DC, IN PUERTO RICO, REPUBBLICA DOMINICANA, INGHILTERRA= , SVIZZERA, ECT ECT. MA ANCOR PIU' DI TUTTO CIO', SONO NOTA IN TUTTO IL GLO= BO TERRESTRE PER ESSERE STATA L'EX AMANTE LESBICA DELLA DEPRAVATA NAZIMAFIO= SA MARINA BERLUSCONI. E PER BEN 13 ANNI. https://plus.google.com/113646548587006228899 https://twitter.com/premolisimona?lang=3Des https://twitter.com/premolisimona/status/876056110033235969 https://profile.theguardian.com/user/id/12251903?page=3D1 AL PUNTO CHE DAVVERO CONTA, ORA. MENTRE ERO AGENTE CIA ( PARTE PIU' DI ESTR= EMA DESTRA DELLA CIA), HO RICICLATO ALL'ESTERO MARI DI EURO CRIMINALISSIMI,= STRA RUBATI O FRUTTO DI MEGA MAZZETTE ( NOTI 49 MILIONI FREGATISSIMI E DI = CERTO NON SOLO), PER LEGA LADRONA ( CHE CON QUESTA ULTIMA MANOVRA CON 40 MI= LIARDI DI DEBITO INTENDE RUBARE E PRENDERE MAZZETTE PER ALTRI 490 MILIONI D= I EURO, NON "SOLO" 49). E PER IL PEDOFILO SPAPPOLA MAGISTRATI: SILVIO BERLUSCONI. TUTTE IMMENSE FRO= DI, TRUFFE E MEGA TANGENTI CHE I PEZZI DI MERDA, HITLERIANI, COCAINOMANI, C= ORROTTI, NDRANGHETISTI, LADRI ED ASSASSINI UMBERTO BOSSI, ROBERTO MARONI, M= ATTEO SALVINI, ENNIO DORIS, MASSIMO DORIS, SILVIO BERLUSCONI E FEDELE CONFA= LONIERI, HAN BECCATO NEGLI ULTIMI ANNI DAI LORO ... - KAMERADEN NAZISTEN, BLOODTHIRSTY ASSASSIN VLADIMIR PUTIN ( THAT SCARE US = LESS THAN ZERO, WHEN "IT" SEND US HIS NAZIST MEGA SON OF FASCIST BITCHES FR= OM HIS RUSSIAN GESTAPOS, AS IT HAPPENES YESTERDAY, TO TRY TO INTIMIDATE US,= WHILE WE SCRIEAM AND SHOUT PURE TRUTHS, VIA COMPUTER: WE ALWAYS TELL THEM,= AT LEAST, ENORMOUS "FUCK OFF", TO SHOW THEM BELOW ZERO FEARS, EXACTLY AS I= T HAPPENED IN 24 HOURS AGO, MAKING THEM RUN AWAY). AND HIS FASCIST COCK SUC= KERS, MEGA RUSSIAN MAFIA MONEY LAUNDERES SILVIO BERLUSCONI, DONALD TRUMP AN= D VIKTOR ORBAN https://torino.corriere.it/sport/18_maggio_06/de-benedetti-salvini-antisemi= ta-finanziato-putin-leghista-querelo-8b0a05bc-5140-11e8-b393-1dfa8344f8a7.s= html OLTRE CHE DA BASTARD, CORRUPT, NAZIFASCIST WORM LEWIS EISENBERG, HITLERIAN = KAPO' OF PINOCHETTIAN US EMBASSY IN NAZIMAFIOSA TIRANNY OF BERLUSCONIA.....= . TO NOT TALK BOUT BEFORE MENTIONES DONALD "STINKY PEDOPHILE" TRUMP https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.huffingtonpost.com/entry/donald-trump-rape-case_us_581a31a5e4b0= c43e6c1d9834 https://www.snopes.com/fact-check/are-we-not-going-to-talk-about-trump/ 8 YES, MEGA COCAINE TAKER DONALD TRUMP (NAZIST KAPO' OF THE WHITE "POWDER" HO= USE, FOR WHO, I WD REPEAT SAME SPEECH DONE BEFORE FOR NAZIST ASSASSIN VLADI= MIR PUTIN, IN CASE WD BE MEGA HITLERIAN EXCREMENT DONALD TRUMP TO SEND US S= EWER RATS FROM HIS FASCIST PRESENT KIND OF CIA TO TRY TO INTIMIDATE US). MA= CCARTIST, MAFIOSO, MEGA MAFIA MONEY LAUNDERER, MEGA COCAINE TAKER, DEPRAVED= , PERVERT, PEDOPHILE DONALD TRUMP ( WHO IS ALSO THREATENING WITH THE STYLE = OF HIS BASTARD IDOL AL CAPONE, VIOLENCE, IF HE'LL LOOSE, AS HE ABSOLUTELY S= HOULD, NEXT US MID TERM ELECTIONS https://www.theguardian.com/us-news/2018/aug/28/donald-trump-midterms-priva= te-meeting-church-antifa ), SINCE ALWAYS, FINANCIAL WASHING MACHINE FOR RU= SSIAN MAFIA, CHINESE MAFIA CALLED TRIADE, SICILIAN MAFIA, NAPULITAN MAFIA, = CALABRESIEDDA MAFIA, COLOMBIAN MAFIA http://www.newsweek.com/trump-russian-italian-mafia-fusion-785524 https://www.theaustralian.com.au/news/investigations/donald-trump-the-deals= -and-the-mafia-dons/news-story/40c61d98c72c3ba10064357c047ee8ce?nk=3D07c238= 2e7c9003d0828e92d735514bac-1532970957 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia http://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-ref= use-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html EXACTLY THE SAME .... REGARDING - NAZIFASCIST, RACIST, KUKLUKLANIST, AS MUCH AS STINKY MAFIA MONEY LAUNDERE= R AND PEDOPHILE PAUL SINGER FROM ELLIOTT FUND ( WHO IS A SLIMY, COWARD, HID= DEN, PEDERAST KIND OF HOMOSEXUAL, NO ONE HAS COURAGE TO TELL THAT, BUT I HA= VE IT AND SUPER STRA HAVE IT ) http://ryansorba.blogspot.com/2017/05/paul-singers-gay-agenda-punish-pay-of= f.html ME, PERSONALLY, SIMONA PREMOLI, I HAVE BEEN FOR 13 YEARS, MARINA BERLUSCONI= 'S HOTTEST LESBIAN LOVER, SO, IF THERE IS A LGBT FELLA, THAT'S ME.... BUT S= LIMY, COWARD, HIDDEN, SATANIC, NAZIST, MAFIOSI, PEDOPHILE KIND OF HOMOSEXUA= LS LIKE PAUL SINGER FROM ELLIOTT FUND, I DON'T LIKE THEM... SO I WILL SCREA= M AND SHOUT THIS, IN MILLIONS OF SITES OF ALL THIS PLANET .. FROM NOW ON...= AND BY THE WAY... "THE REAL POINT OF MY IMMENSE ANGER, EVEN MORE THAN IS K= ILLING PEDERASTY", IS THE FOLLOWING: SHAME ON YOU, NAZIST MAFIA MONEY LAUND= ERER AND WELL KNOWN PEDOPHILE HOMOSEXUAL PAUL SINGER FROM ELLIOTT FUND TO S= UPPORT ANOTHER PEDOPHILE LIKE YOU, FURTHERMORE ASSASSIN, MEGA PRINCIPAL OF = HUNDREDS OF MURDERS AND VERY BLOODTHIRSTY SLAUGHTERS LIKE HOMICIDE DICTATOR= SILVIO BERLUSCONI: SHAME ON YOU!!!!!!!!!!!!!!!!!!!!! https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ ) - NAZIFASCIST RACIST KUKLUKLANIST PIG AS WELL AS MEGA MAFIA MONEY LAUNDERER= , AND ALSO SLIMY AND PERVERT KIND OF HOMOSEXUAL: GORDON SINGER FROM ELLIOTT= FUND - NAZIFASCIST RACIST KUKLUKLANIST PIG AS WELL AS MEGA MAFIA MONEY LAUNDERER= AND ALSO EVEN MORE SLIMY AND DEPRAVED KIND OD HOMOSEXUAL ANDREW SINGER FRO= M ELLIOTT FUND ( WHO DOES LOT OF VERY PERVERT ORGIES WITH VERY YOUNG BOYS E= VERYWHERE IN THE WORLD, NO ONE HAS COURAGE TO TELL THAT, BUT, AGAIN, I HAVE= IT AND SUPER STRA HAVE IT http://ryansorba.blogspot.com/2017/05/paul-singers-gay-agenda-punish-pay-of= f.html ) TO NOT WRITE BOUT BASTARD NAZIST, RACIST, KUKLKLANIST, COCAINE TAKER AND PE= DOPHILE STEVE BANNON WITH HIS SHITTY, KILLING, HITLERIAN PROPAGANDA RETROSP= ECTIVE. 9 COL TUTTO COORDINATO DAL NOTO IN TUTTO IL MONDO COME " ER POMPINARO DE AUGU= STO PINOCHET": MIKE POMPEO ( FAMOSO COLLEGA ED ONONIMO DI UN ALTRO NOTISSIM= O "POMPINARO DE AUGUSTO PINOCHET": " PIO POMPA"). PER NON PARLARE DEL PEZZO DI MERDA, NAZIFASCISTA, STALKER ASSASSINO VIA INT= ERNET, NOTISSIMO PEDOFILO LUCA MORISI DI LEGA LADRONA, TWITTER E LINKEDIN ( SON OF A BITCH AND WELL KNOWN PEDOPHILE LUCA MORISI: ASSASSIN, NAZIST, SO= CIAL MEDIA STRATEGIST) https://it.linkedin.com/in/luca-morisi-315b10b E PER NON RIPARLARE DEL BASTARDO ASSASSINO GENNARO VECCHIONE DEL DIS ( FIGL= IO DI CANE GENNARO VECCHIONE, NOTO PER ESSERE ANCHE UN DEPRAVATISSIMO RICCH= IONE) ED IL PEZZO DI MERDA MEGA OMICIDA LUCIANO CARTA DELL'AISE ( CHE VUOLE= AMMAZZARE CHIUNQUE NON SIA NAZIFASCISTA COME LUI E LA CAROGNA MEGA KILLER = MATTEO SALVINI, OVUNQUE NEL MONDO, FATE VOI CHE RISPETTO PER LA DEMOCRAZIA,= STI RATTI COLERICI ABBIANO). TRATTASI DI DUE TOPI DI FOGNA, CORROTTISSIMI = DA SILVIO BERLUSCONI E LEGA LADRONA, QUANDO A KAPO' DELLA GUARDIA DI FINANZ= A. DI CUI RIVELERO' TANTISSIMI ALTRI PARTICOLARI, PROSSIMAMENTE. A PROPOSITO DEL PRIMA CITATO, TUTTI I PRIMA DESCRITTI MEGA CRIMINI DI LEGA = LADRONA, RAZZISTA, NAZISTA, NDRANGHETISTA ED ASSASSINA, SONO GEMELLI DEGLI = STESSI CHE LEGA LADRONA, RAZZISTA, NAZISTA ED ASSASSINA, USAVA CONCRETIZZAR= E, NEI FAMOSI ANNI 2001-2006. FACENDOSI STECCARE IN GIRO PER IL MONDO, DA A= LTRI DITTATORI ASSASSINI QUALI GHEDDAFI, MUBARAK E BEN ALI' http://www.marcogregoretti.it/verita-nascoste/la-lega-nord-era-finanziata-d= a-gheddafi-gossip-elettorale-contro-il-centrodestra-o-storia-vera/ CIAO A TUTTI. SONO SIMONA PREMOLI, EX AMANTE DI MARINA BERLUSCONI PER BEN 1= 3 ANNI ED EX AGENTE DELLA CIA IN DIVERSI PAESI DEL MONDO ( BERLUSCONIA-LEGA= LADRONUSCONIA, USA, PUERTO RICO, REPUBBLICA DOMINICANA, INGHILTERRA, SVIZZE= RA, ECT ECT). https://twitter.com/premolisimona?lang=3Den https://twitter.com/PremoliSimona/status/937885752003723265 https://twitter.com/premolisimona/status/876055837420158976 https://twitter.com/PremoliSimona/status/946915645756715009 https://twitter.com/PremoliSimona/status/946923968245784576 https://twitter.com/PremoliSimona/status/977570748847050754 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 https://profile.theguardian.com/user/id/12251903?page=3D1 10 COME PRIMA CITATO, SONO STATA PER DECENNI DIETRO TANTI RICICLAGGI DI SOLDI = CRIMINALISSIMI DI LEGA LADRONA ( IN SVIZZERA, A PANAMA, ALLE BAHAMAS, ALLE = CAYMAN, ALLE SEYCHELLES, SPECIALMENTE AD HONG KONG, PRESSO WELL KNOWN KUKLU= KKLANIST, SATANAZIST, MEGA MAFIA MONEY LAUNDERER AND ALSO WELL KNOWN PEDOPH= ILE DANIEL HEGGLIN EX MORGAN STANLEY LONDON AND HONG KONG .. OR KUKLUKKLANI= ST, SATANAZIST, MEGA MAFIA MONEY LAUNDERER AND PEDOPHILE DANIEL "DANNY" HEG= GLIN EX MORGAN STANLEY LONDON AND HONG KONG). BASTARD ASSASSIN SON OF A BIT= CH DANIEL HEGGLIN NOW WASHING KILLING MAFIA'S CASH BY SEVENOAKS, REALM THER= APEUTICS PLC AND FOR SURE NOT ONLY https://alt.business.misc.narkive.com/iTvPQU8e/bastard-assassins-daniel-heg= glin-ex-morgan-stanley-arrested-3-times-paolo-barrai-mercato-libero-mkg- https://www.py.cz/pipermail/python/2017-March/012858.html https://lists.mozilla.org/pipermail/dev-platform/2014-September/006516.html NOTO "FIDUCIARY" DI TIPO CRIMINALISSIMO, DELLE NOTE BESTIE ASSASSINE DI COS= A NOSTRA, "QUANDO IN CRAVATTA": SILVIO BERLUSCONI, FEDELE CONFALONIERI, MAR= CELLO DELL'UTRI, MASSIMO DORIS, ENNIO DORIS. OSCAR DI MONTIGNY. SI, VOGLIO SPUTTANARE AL MASSIMO, STO PARTITO DI ESTREMISSIMA DESTRA, PRIMA= ANTI MERIDIONALI ( BASTA VEDERE QUESTO VIDEO DAVVERO BASTARDO https://vide= o.repubblica.it/politica/quando-salvini-cantava-senti-che-puzza-arrivano-i-= napoletani/291156/291766 ), POI, ANTI EROI DI CENTRO SINISTRA, POI ANTI ROM= , POI ANTI PERSONE DI COLORE, POI ANTI EBREI, DI QUEL FIGLIO DI PUTTANA HIT= LERIANO E RAZZISTISSIMO, TUTT'UNO CON COSA NOSTRA E E NDRANGHETA, CHIAMATO = " ASSASSINO MATTEO SALVINI ( CHE SE BEN NOTATE, STA INIZIANDOSI A MEGA CAGA= RE SOTTO NEI CONFRONTI DI FINANZA MONDIALE, UE ED EROICI PM AGRIGENTINI, EF= FETTUANDO RETROMARCE SU RETROMARCE A GO GO: MERDACCIA DI QUAQUARQUA CHE ALT= RO NON E' ". GIA' BEN SMERDATO DA GRANDI GIORNALISTI DE L'ESPRESSO, E NON S= OLO, QUI: http://espresso.repubblica.it/inchieste/2018/07/04/news/soldi-lega-la-lette= ra-che-incastra-salvini-1.324561?ref=3DRHRR-BE http://espresso.repubblica.it/inchieste/2018/05/31/news/alla-lega-sovranist= a-di-matteo-salvini-piace-offshore-1.323128 http://espresso.repubblica.it/inchieste/2018/04/13/news/i-soldi-offshore-de= lla-fondazione-targata-lega-1.320530 http://espresso.repubblica.it/inchieste/2018/03/28/news/i-conti-segreti-di-= matteo-salvini-1.320080 http://www.ilsussidiario.net/News/Cronaca/2018/6/3/L-Espresso-contro-la-Leg= a-Gli-affari-dei-cassieri-di-Salvini-holding-in-Lussemburgo-ragnatela-di-fi= duciarie/823987// COME DA AMMIRABILISSIMO GEORGE SOROS QUI: http://www.repubblica.it/economia/2018/06/03/news/soros_preoccupato_della_v= icinanza_del_nuovo_governo_con_la_russia_-198062920/). ED AGGIUNIGAMO UN ALTRA IMPORTANTISSIMA COSA, ORA, PLEASE. IO SIMONA PREMOL= I, SON PURE STATA PER TANTISSIMO TEMPO, COMPLICE, COLLUSA, "INTIMISSIMA" CO= LLABORATRICE DEL ^NEOLD^ PIDUISTA, NONCHE' MEGA RICICLA SOLDI DI MILLE MAFI= E: GIANPIERO SAMOR=C3=8C DEL CRIMINALISSIMO MOVIMENTO "MODERATI IN RIVOLUZI= ONE", ( MODERATI... DI TIPO MALAVITOSISSIMO). ORA PERO' MI INCAZZO E DICO B= ASTA A STA FOGNA DI COSA NOSTRA, CAMORRA E NDRANGHETA FINANZIARIA CHE DA SE= MPRE STI PEZZI DI MERDA BERLUSCONAZISTI E PADANAZISTI RAPPRESENTANO ( VI AS= SICURO, SPESSO, PURE PEDOFILI, STUPRA UOMINI E DONNE, IMMENSAMENTE COCAINOM= ANI, STRAGISTI ED ASSASSINI, IN QUANTO ORDINANTI DOZZINE DI STRAGI E MIGLIA= IA DI OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI ED INCIDENTI, IL TUTTO VI= A VARIE LORO LOGGE MASSONICHE OMICIDA). 11 NE ERO DENTRO. E DA LORO "LO PRENDEVO IN CONTINUAZIONE DENTRO". QUINDI SO' = QUESTO ALLA PERFEZIONE PER AVER VISSUTO TUTTO QUESTO, NON SOLO VISTO. I BAS= TARDI ASSASSINI E STRAGISTI SILVIO BERLUSCONI, PAOLO BERLUSCONI, MARINA BER= LUSCONI, OSCAR DI MONTIGNY, PAOLO BARRAI, GIOVANNI PUIROVANO, MASSIMO DORIS= ED ENNIO DORIS ORDINANO DOZZINE DI STRAGI E MIGLIAIA DI OMICIDI MASCHERATI= DA FINTI SUICIDI, MALORI ED INCIDENTI, IL TUTTO VIA VARIE LORO LOGGE MASSO= NICHE KILLER, COME ANCHE ATTRAVERSO MAFIA, CAMORRA, NDRANGHETA, A CUI LAVAN= O MONTAGNE DI SOLDI ZUPPI DI SANGUE DI MORTI AMMAZZATI, ED ANCOR PIU', ATTR= AVERSO LORO SANGUINARIE NUOVE OVRA E GESTAPO, SIA PUBBLICHE CHE PRIVATE) . GUARDATE BENE QUESTA CHART, ORA, PLS https://www.worldcoinindex.com/coin/eidoo LEGA LADRONA HA RICICLATO 22 MILIONI DI EURO, IN QUESTA FALLIMENTARISSIMA I= CO ( PARTE DEI FAMOSI 200 MILIONI E NON SOLO 48 MILIONI DI EURO RUBATI DA P= ARTE DI LEGA LADRONA). ATTRAVERSO IL PIU' GRANDE CRIMINALE DELLA FINANZA MO= NDIALE: TOPO DI FOGNA, GIA' FINITO 3 VOLTE IN GALERA, PAOLO BARRAI, NATO A = MILANO IL 28.6.1965 ( O TOPO DI FOGNA, PIU' GRANDE CRIMINALE DELLA FINANZA = MONDIALE, GIA' FINITO 3 VOLTE IN GALERA, PAOLO PIETRO BARRAI, NATO A MILANO= IL 28.6.1965 CHE STA A LUGANO, ORA, PER NON FINIRE IN CARCERE A MILANO... = PER UNA 4TA VOLTA... FA PURE RIMA, WAGLIO'). QUESTA ICO HA SEMPRE AVUTO VOL= UMI BASSISSIMI ( SCAMBI PER UNA QUALCHE DECINA DI MIGLIAIA DI EURO AL GIORN= O). MA DOPO CHE IN DATA 3.6.18 HO INIZIATO A SCRIVERE ALL OVER THE WORLD, D= EI MEGA RICICLAGGI DI SOLDI LERCISSIMI DI LEGA LADRONA IN CRIMINALISSIMA E = FALLIMENTARISSIMA EIDOO ( ORA IL PEZZO DI MERDA, NAZIMAFIOSO, PEDOFILO DONA= LD TRUMP HA ORDINATO DI FARLA LINKARE ALL'ORO FISICO PER FARNE SALIRE IL PR= EZZO: BUONO A SAPERCI, CI FAREMO UN MARE DI SOLDI ANCHE NOI, VISTO CHE CONO= SCIAMO LE SUE, COME AL SOLITO, MEGA TRUFFALDINE INTENZIONI). NEI GIORNI SUB= ITO A SEGUIRE, LA STESSA, DA NOI SGAMATISSIMA, LEGA LADRONA, HA SUPER STRA = DATO ORDINE DI VENDERE EIDOO PER UN TOTALE DI 22 MILIONI DI EURO. COL STRA = PIENO INTENTO DI MONETIZZARE TUTTO ( CON PERDITE DEL 50 PER CENTO E PASSA..= .... AHAHHA, CHE DEFICENTI ED IDIOTA A LIVELLO IMMENSO). E QUINDI FAR SPARI= RE LORO CRIMINALISSIMI SOLDI. PIU' PROVA DI COSI', CHE STO PONENDO DITA SU = GIUSTISSIME LORO MALAVITOSE PIAGHE? IO VOGLIO O MOVIMENTO S STELLE ED INTER= O CENTRO SINISTRA A PALAZZO CHIGI (MA SENZA LA MERDA BERLUSCORROTTA DI MATT= EO RENZI, SENZA LA MERDA BERLUSCORROTTA DI CARLO CALENDA, SENZA LA MERDA BE= RLUSCORROTTA DI MARIA ELENA BOSCHI, SENZA LA MERDA BERLUSCORROTTA DI MATTEO= ORFINI, SENZA LA MERDA BERLUSCORROTTA DI LUCA LOTTI, SENZA LA MERDA BERLUS= CORROTTA DI LORENZO GUERINI E LORO BERLUSMAZZETTATA GANG VARIA... DATE IL P= AESE A LEU UNITO AD UN PD CAPEGGIATO DA MICHELE EMILIANO ED OLIVIERO TOSCAN= I, FONDENDO IL TUTTO AD UN M5S GUIDATO DA ALFONSO BONAFEDE O ROBERTO FICO, = CHE SIA ANTI PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI AL CALOR BIANCO= , ED IL NOSTRO PAESE AVRA' UN MEGA BOOM DI SUCCESSO). O LA RIVOLUZIONE ED A= TUTTI I COSTI ( NIENTE NAZISMO, RAZZISMO, KUKLUKLANISMO, MAFIA, CAMORRA E = NDRANGHETA DI LEGA LADRONA NEL MIO PAESE: RESISTENZA ANTI ASSASSINI SWASTIK= ATI E NDRANGHETISTI PADANI DA SUBITO)! AVANTI TUTTA! QUESTO ORGANIZZERO' A = TUTTI I COSTI!!! E CON CENTINAIA SERVIZI SEGRETI DI TUTTO IL PIANETA TERRA,= COL TUTTO DIRETTO FAL GENIO DELLA FINANZA E POLITICA MONDIALE, L'EROE GEOR= GE SOROS: MIO AMICO " INTIMISSIMO" DA TANTI ANNI !!!!!!! 12 INFINE, UNA COSA DA DONNA, CHE HO PROPRIO SULLA BOCCA DELLO STOMACO! CHE SCHIFOSA PUTTANA E' ELISA ISOARDI: TROIA, RAZZISTA, SATANAZISTA ( DIETR= O TANTI OMICIDI E SPARIZIONI SATANISTE ACCADUTE NEL CUNEENSE http://www.lastampa.it/2015/08/01/cuneo/scomparsi-da-anni-resta-il-mistero-= Q1u3ZmsLrLVEH43wjtxC8N/pagina.html OMICIDI E SPARIZIONI MESSI INSIEME DA LEI E DA SUA CAMERATA, PUTTANONA E SA= TANAZISTA TANTO QUANTO, BASTARDA ASSASSINA TROIA ELISA COGNO DI CRIMINALISS= IMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX DI ALBA https://instagram.flis3-1.fna.fbcdn.net/vp/b0c9ea513b28f4d7a7c52cf85e320c2a= /5CCA71D4/t51.2885-19/s150x150/37978940_714225998926422_7982560383086886912= _n.jpg?_nc_ht=3Dinstagram.flis3-1.fna.fbcdn.net ). IN RAI SOLO ED ESCLUSIVA= MENTE IN QUANTO CIUCCIA E PRENDE IN CULO E FIGA MILLE CAZZI SU CAZZI DI HIT= LERIANI PADANI. PER NULLA, SOLO QUELLO DELLA MERDA SWASTIKATA, OMICIDA E CO= RNUTONA: MATTEO SALVINI. A 16 ANNI, LA NAZISTROIA ELISA ISOARDI GIA' LO PRE= NDEVA NELL'ANO E NELLA VAGINA, CONTEMPORANEAMENTE, E PER SOLI 30 EURO DI AL= LORA. SIA DA ERNESTO PREATONI, CHE DA FLAVIO BRIATORE ( COME DETTOMI DAI DU= E, DI PERSONA E TANTE VOLTE) http://www.today.it/gossip/love-corn/elisa-isoardi-briatore-insieme.html LA SCORSA ESTATE SCOPAVA ALLO STESSO TEMPO, UN AVVOCATO CRIMINALE, VICINISS= IMO A NDRANGHETA, CAMORRA E MAFIA, TALE MATTEO PLACIDI E NEGLI STESSISSIMI GIORNI, ANCHE LA BESTIA HITLERIANA, MEGA FREGA SOLDI, F= ASCISTA, KUKLUKLANISTA, COCAINOMANE, CORROTTA, INSOMMA, IL NOTO FIGLIO DI P= UTTANA, RAZZISTA, PAZZO DA RINCHIUDERE, NAZISTASSASSINO MATTEO SALVINI !!! SIMONA PREMOLI. FOLLOW ME, MY SWEET SWEET BABY, ON ... https://twitter.com/premolisimona?lang=3Den https://twitter.com/PremoliSimona/status/937885752003723265 https://twitter.com/premolisimona/status/876055837420158976 https://twitter.com/PremoliSimona/status/946915645756715009 https://twitter.com/PremoliSimona/status/946923968245784576 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 https://profile.theguardian.com/user/id/12251903?page=3D1 From newsfish@newsfish Thu Aug 1 00:44:22 2024 X-Received: by 2002:a37:9c55:: with SMTP id f82mr3182977qke.101.1556233670393; Thu, 25 Apr 2019 16:07:50 -0700 (PDT) X-Received: by 2002:a25:52d5:: with SMTP id g204mr34314403ybb.228.1556233670153; Thu, 25 Apr 2019 16:07:50 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Thu, 25 Apr 2019 16:07:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.157.134.26; posting-account=J_kdbgoAAADBWJs37f5dH7KCjm4VbyVx NNTP-Posting-Host: 88.157.134.26 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1e7a45ee-4a8f-4d3c-b4ee-5e55e519d89e@googlegroups.com> Subject: PRENDE CAZZI IN CULO DI MEZZO METRO: LUIGI BERLUSCONI (CON PADRE IL PEDOFILO SPAPPOLA MAGISTRATI, IL BASTARDO ASSASSINO SILVIO BERLUSCONI, CHE ORA HA FATTO AMMAZZARE ANCHE LA PER BENISSIMO IMANE FADIL, DOPO AVER FATTO LO STESSO CON EGIDIO VERZINI ED From: ANDREA MAZZALAI ICEBERG FINANZA Injection-Date: Thu, 25 Apr 2019 23:07:50 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!t9no576723qtn.0!news-out.google.com!i54ni259qte.0!nntp.google.com!t9no576715qtn.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9455 PRENDE CAZZI IN CULO DI MEZZO METRO: LUIGI BERLUSCONI (CON PADRE IL PEDOFIL= O SPAPPOLA MAGISTRATI, IL BASTARDO ASSASSINO SILVIO BERLUSCONI, CHE ORA HA = FATTO AMMAZZARE ANCHE LA PER BENISSIMO IMANE FADIL, DOPO AVER FATTO LO STES= SO CON EGIDIO VERZINI ED EMILIO RANDACIO, https://www.fanpage.it/le-strane-morti-del-caso-ruby-il-giornalista-lavvoca= to-e-la-modella/ PER NON DIRE DI QUANDO RESE IN BRANDELLI I SUPER EROI GIOVANNI FALCONE, PAO= LO BORSELLINO E MIGLIAIA E MIGLIAIA DI ALTRE PERSONE, IN STRAGISTISSIMA, SA= NGUINARISSIMA VITA SUA https://it-it.facebook.com/pages/category/Community/FALCONE-E-BORSELLINO-UC= CISI-DA-BERLUSCONI-134602469910010/ )! RICCHIONE DEPRAVATO E NAZISTA LUIGI = BERLUSCONI DI CRIMINALISSIMA H14, CHE FA PER LAVORO IL MEGA RICICLA SOLDI M= AFIOSI! LO STESSO CHE PRIMA EFFETTUAVA IL VERME CRIMINALISSIMO SUO NONNO L= UIGI BERLUSCONI! E LO STESSO CHE HA SEMPRE FATTO LO SBAUSCIA TROIE POCO PIU= ' CHE BAMBINE, PEDOFILO ED OMICIDA DI TANTISSIME PERSONE PER BENE, IL FIGLI= O, MARITO, CAMERATA E PADRE DI PUTTANE: SILVIO BERLUSCONI! MA INIZIAMO DA QUI, ORA, PLEASE.. 1 PRENDE IMMENSI CAZZI IN CULO DI 30 CM: LUIGI BERLUSCONI! CON PADRE LO SCHIF= OSO PEDOFILO SILVIO BERLUSCONI! SI, SI, E' SEMPRE CON MEGA CAZZI IN CULO, I= L RICCHIONE NAZISTA LUIGI BERLUSCONI! FACENTE PER LAVORO IL MEGA RICICLA SO= LDI MAFIOSI!! IL CULATONE HITLERIANO LUIGI BERLUSCONI E' DA SEMPRE " AD ALT= EZZA" CRIMINALISSIMA DI PADRE E NONNO! SI, SI, CIUCCIA E PRENDE MEGA CAZZI = IN CULO LUIGI BERLUSCONI, CHE HA PER SOLA FIDANZATA "UN NOTO MASSONE MAFIOS= O DEL GRANDE ORIENTE D' ITALIA, CON LA BARBA (AMICO E FINANZIATORE DEL COMP= LOTTARDO E CORROTTISSIMO STEFANO BISI). QUESTO MASSONE MAFIOSO CON LA BARBA= ED IL CULATONE PERVERTITO E NAZISTA LUIGI BERLUSCONI SON FRATELLI SATANIST= I, SON FRATELLI ^MASSONAZISTI^! DELLA LOGGIA DEL DRAGO DEL PEDOFILO SPAPPOL= A MAGISTRATI: SILVIO BERLUSCONI! http://www.democraziaradicalpopolare.it/al_Venerabilissimo_Maestro_Massone_= Silvio_Berlusconi_dategli_la_prescrizione_ad_vitam_e_a_priori.html https://www.centroparadesha.it/ude/articoli/1156-549-la-loggia-del-drago-di= -galeazzi-pinotti MASSONE MAFIOSO CON LA BARBA, CHE IO, FRA L' ALTRO, BEN CONOSCO!!!!!!! IN Q= UANTO LAVORAVA CON ME E CON QUELL'EFFERATISSIMO CRIMINALE DI ALDO ACQUISTAP= ACE DI CREDIT SUISSE, IN BORSA, A MILANO" ..ANYWAY..GUARDATE QUI, PLEASE, C= OME IL SEMPRE SBORRATO PROFONDAMENTE DENTRO AL CULO, LUIGI BERLUSCONI, SLIN= GUA DETTO MASSONE MAFIOSO DEL GOI CON LA BARBA http://www.sostenitori.info/wp-content/uploads/2017/07/luigi-berlusconi-681= x357.jpg UN MIO CARO AMICO, IL NOTORIAMENTE DEPRAVATO (E SATANISTA) OMOSESSUALE FEDE= RICO TRABUCCO DI KAIROS https://it.fundspeople.com/people/federico-trabucco HA PARTECIPATO A DIVERSE ORGE GAY MENEGHINE CON LUIGI BERLUSCONI. E MI HA A= SSICURATO CHE LO STESSO PRENDE ANCHE DUE CAZZI IN CULO CONTEMPORANEAMENTE. = MI HA STRA ASSICURATO CHE LO STESSO CHE PRENDE CAZZI DI 30 CM E PASSA, TUTT= I DENTRO ALL'ANO. SIA CHIARO E STRA CHIARO, PLEASE: IO NON SONO PER NULLA A= NTI GAY, PER NULLA OMOFOBA. TANTO E' VERO CHE DA ANNI SON IN RAPPORTI MOLTO= CORDIALI COL PRIMA CITATO NOTO OMOSESSUALE ( PUR SE PIUTTOSTO PERVERTITO = E MOLTO SATANISTA) FEDERICO TRABUCCO DI KAIROS. MA RITENGO ASSOLUTAMENTE CH= E TUTTO IL MONDO, SI, IL MONDO INTERO, IL PIANETA TERRA TUTTO, DEBBA SAPERE= OGNI COSA, PROPRIO OGNI COSA, SUI BASTARDISSIMI CRIMINI E LE MEGA PERVERSI= ONI SESSUALI DI TUTTI I BERLUSCONI: OSSIA LA METASTASI ASSASSINA DEL PIANET= A TERRA. IN QUANTO SONO I DITTATORI NAZISTI, MAFIOSI, CAMORRISTI, NDRANGHET= ISTI, PEDOFILI, STRAGISTI, ASSASSINI, DEL NOSTRO PAESE E DA "APPENA APPENA"= 40 ANNI! FACCIAMO UN CHECK, ORA, SULLA PARTE CHE ANCORA PIU' CONTA, PROBAB= ILMENTE. OSSIA SU QUANTO SIA PROFESSIONALMENTE CRIMINALISSIMO LUIGI BERLUSC= ONI! 2 E' MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI (ECCO QUALE E' IL SUO MALAVI= TOSO VERO LAVORO..CHE POI, CASPITERINA CHE "COINCIDENZUZZA BEDDA", ERA LO S= TESSO LAVORO DEL PEZZO DI MERDA LUIGI BERLUSCONI NONNO IN BANCA RASINI, LA = NOTA BANCA " DI COSA NOSTRA BEDDA BEDDUZZA AAAH" https://www.ilfattoquotidiano.it/2010/11/19/berlusconi-e-cosa-nostra-il-pri= mo-capitolo-de-lintoccabile-di-peter-gomez-e-leo-sisti/77797/5/ http://susannaambivero.blogspot.pt/2009/08/rasini-la-banca-di-berlusconi-e-= della.html ). AVENTE COME PADRE, LO STRAGISTA SPAPPOLA MAGISTRATI, MANDANTE DI MIGLIAIA D= I OMICIDI MASCHERATI DA FINTI MALORI, SUICIDI, INCIDENTI, IL DITTATORE SATA= NISTA E NAZISTA, DICIAMO DITTATORE SATA-N-AZISTA, OLTRE CHE MEGA LAVA SOLDI= MAFIOSILADRO, TRUFFATORE, SEMPRE FALSO, POR-CO-RRUTTORE, MEGA COCAINOMANE,= SCHIFOSISSIMO PEDOFILO SILVIO BERLUSCONI. CIAO A TUTTI, SONO SEMPRE IO, LA VOSTRA INSEGNANTE IN SCUOLE LOMBARDE, MASS= ONA DI ALTO GRADO, FOCOSISSIMA E VINCENTISSIMA PORNOSTAR MARIA GRAZIA CRUPI= NATA IL 30.10.1969. NOTA IN TUTTO IL GLOBO TERRESTE PER ESSER STATA EX AMA= NTE LESBICA DI MARINA BERLUSCONI E PER BEN 12 ANNI. MI VEDETE QUI IN CHIARO SCURO MASSONICISSIMO http://3.bp.blogspot.com/-77QAEQtTGWk/W3cRuhZHDJI/AAAAAAAAAPU/ox_S3cmW7KEUZ= nXiaX_TFzWEftaFh63wwCK4BGAYYCw/s1600/ACSszfG2KY6Io2QWHkHClzs_yhKC6NKY96WSeB= EhLQ%253Ds900-mo-c-c0xffffffff-rj-k-no QUI IN LOOK 9 TO 5, GIUSTO PRIMA DI ANDARE AD UN ORGIA POMERIDIANA CHE FECI= AD ARCOREHARDCORE CON MARINA BERLUSCONI, MARIA DE FILIPPI, PAOLA BARALE, A= LBA PARIETTI E TANTISSIME ALTRE LESBICHE DEI GIRI "MAFIASET-CAMORRASET-NDRA= NGASET-NAZISTSET-MEDIASET" https://yt3.ggpht.com/a-/ACSszfGYKnNA7XEP81l-T0eLaUTs8OwxdR6vxCtIFg=3Ds900-= mo-c-c0xffffffff-rj-k-no QUI IN ALCUNI MIEI FILM PORNO AMATORIALI, DI GRAN SUCCESSO IN TUTTO IL MOND= O ( FILM PORNO CHE FACCIO PERO' SEMPRE E SOLO CON MASCHERINA, OVVIAMENTE, P= ER NON GIOCARMI IL COMODO E FACILE STIPENDIO DELLA PUBBLICA ISTRUZIONE, CHE= PRENDO, LAVORANDO MOLTO POCO, FRA L'ALTRO) https://4.bp.blogspot.com/-qkTlyigYRQM/WQsbwxkPZzI/AAAAAAAAALo/MGN1QnRh4Gcw= joiFO96u3-1bFXqWqegDQCK4B/s113/1443711887.76214.jpg https://cdn1.images.lesbianpornvideos.com/videos/0566/13400/main.jpg https://encrypted-tbn0.gstatic.com/images?q=3Dtbn:ANd9GcRQbZWcnN5tKpb_ra-np= 8v8mAfAGLrNU-7CkH7hUy8HCoWuhR6KFA SI, SI, SI, SI: E' SEMPRE, SEMPRE E STRA SEMPRE SBORRATO NEL CULO, LUIGI BE= RLUSCONI! CON FIDANZATA UN NOTO ^MASSONE MAFIOSO^ CON LA BARBA https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-bacio-gay-estate-= amico.jpg E NON CON FIDANZATA, LA NOTA ZOCCOLA FEDERICA FUMAGALLI, DA ANNI SCOPATA DA= TUTTI, IN MILLE CLUB PRIVE' DI INTERA FOGNA NAZISTA E MAFIOSA DI BERLUSCON= IA. COME COSI', DI MONTECARLO, INGHILTERRA E SVIZZERA! DICEVO.. E' SEMPRE SBORRATO TUTTO DENTRO AL CULO: LUIGI BERLUSCONI! CON FID= ANZATA UN ^MASSONE MAFIOSO^ CON LA BARBA https://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi ^MASSONE MAFIOSO^ DELLA MEGA ASSASSINA GRAN LOGGIA DEL DRAGO DEL DITTATORE = FASCISTA, NDRANGHETISTA, CAMORRA, DI COSA NOSTRA, OLTRE CHE STRAGISTA SPAPP= OLA MAGISTRATI, MANDANTE DI MIGLIAIA DI OMICIDI MASCHERATI DA FINTI SUICIDI= , MALORI, INCIDENTI, NOTO PEDOFILO SILVIO BERLUSCONI!!! RICICLA VALANGHE DI SOLDI MAFIOSI IL RICCHIINE SEMPRE COL CULO PIENO DI SBO= RRA, IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINAL= ISSIMA B CINQUE SRL. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUS= CONI DI CRIMINALISSIMA MEDIASET ALIAS MAFIASET, CAMORRASET, NDRANGASET, NAZ= ISTSET. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMI= NALISSIMA FININVEST ALIAS (MA)FI(A)NINVEST. IL DELINQUENTISSIMO RICICLA SOL= DI MAFIOSI LUIGI DI CRIMINALISSIMA MOLMED. IL DELINQUENTISSIMO RICICLA SOLD= I MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA HOLDING ITALIANA QUATTORDICESI= MA SPA (GIA' CASSAFORTE MAFIOSISSIMA DI STEFANO BONTATE PRIMA E TOTO RIINA,= POI...CASPITERINA CHE SOCI PER BENE, CASPITERINA, WAGLIO'). 3 IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIM= A H 14 ( SEMPRE GIA' CASSAFORTE MAFIOSA DI STEFANO BONTATE PRIMA E TOTO RII= NA, POI...CASPITERINA CHE SOCI PER BENE, CASPITERINA, WAGLIO'). IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIM= A SERI JAKAL GROUP ( CHE PORTA AVANTI COL SCHIFOSAMENTE SUPER COCAINOMANE P= AOLO MARZOTTO, NOTO RICICLA SOLDI MAFIOSI PROPRIO COME LUIGI, PIERSILVIO, P= AOLO E SILVIO BERLUSCONI). IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI = BERLUSCONI DI CRIMINALISSIMA ITHACA SRL. IL DELINQUENTISSIMO RICICLA SOLDI = MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA DI U-START. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIM= A SOLDO FINANCIAL SERVICES. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIG= I BERLUSCONI DI CRIMINALISSIMA MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOL= ANUM, LAVALAVAPERCOCALEROSCOLOMBIANUM, NAZISTANUM, NAZISTANUM. IL DELINQUEN= TISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA XLAB. IL D= ELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA HO= LDING DI INVESTIMENTI B5. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI B= ERLUSCONI DI CRIMINALISSIMA ABOCA DI SAN SEPOLCRO. IL DELINQUENTISSIMO RICI= CLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA PAYLEVEN. IL DELINQUEN= TISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ROCKET INT= ERNET. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMIN= ALISSIMA ELIGOTECH AMSTERDAM. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUI= GI BERLUSCONI DI CRIMINALISSIMA CGNAL ( O CRIMINALISSIMA CGNAL-ELIGOTECH CH= E SIA) DEL TOPO DI FOGNA BERLUSCORROTTISSIMO MARCO CARRAI (PURE NOTO PEDOFI= LO, FRA L'ALTRO, NE ABBIAM PROVE A PALATE). IL DELINQUENTISSIMO RICICLA SOL= DI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA ALGEBRIS DEL FIGLIO DI PUTTAN= A, MEGA RICICLA SOLDI MAFIOSI: DAVIDE SERRA. IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIM= A ITHACA, IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRI= MINALISSIMA SIREFID ( IL TUTTO INSIEME AD UN ALTRO VERME MEGA RICICLA SOLDI= MAFIOSI, LA BESTIA CRIMINALE GIORGIO VALAGUZZA, NON PER NIENTE, EX DI NAZI= STA JP MORGAN). IL DELINQUENTISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI = DI CRIMINALISSIMA CRYPTOLAB E CRYPTOPOLIS DI NOTO PEDOFILO ASSASSINO PAOLO = BARRAI ( DI FALLIMENTARISSIMO BLOG MERCATO "MERDATO" LIBERO). IL DELINQUENT= ISSIMO RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI DI CRIMINALISSIMA EIDOO DI VE= RME DELLA NDRANGHETA: NATALE FERRARA DA REGGIO CALABRIA ( CRIMINALISSIMA EI= DOO DI VERME DELLA NDRANGHETA: NATALE MASSIMILIANO FERRARA DA REGGIO CALABR= IA). PIU' DI TANTISSIMA ALTRA MERDA FINANZIARIO-CRIMINALE, FASCIOMAFIOSA, B= ERLUSCONICCHIA VARIA! SI, SI, E' PROPRIO COSI'. IL MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI E' UN NAZIRICCHIONE, UN CULA= CCHIONE, UN FEMMINONE SEMPRE SBORRATO PROFONDAMENTE DENTRO AL CULO ( NON SO= NO OMOFOBO O ANTI GAY, ASSOLUTISSIMAMENTE NO, ANZI, COME DETTO, MI DANNO AN= CHE A ME, OGNI TANTO, DEL GAY, DICO DI PIU', HO SEMPRE ODIATO QUANDO LEGGO = CHE ALCUNI GAYS VENGONO PICCHIATI QUASI A MORTE, O PROPRIO UCCISI, SOLO IN = QUANTO, BEN APPUNTO, GAYS: MA VISTO CHE I BERLUSCONI HAN NAZISTAMENTE SEMPR= E ODIATO, UMILIATO E DERISO GLI OMOSESSUALI E VISTO CHE COME LORO SOLITO, S= TANNO CASTRANDO MORTALMENTE LA LIBERTA' DI STAMPA, PER NON FAR SAPERE CHE L= ORO FIGLIO, IL NAZI RICCHIONE LUIGI BERLUSCONI, IL CRIMINALISSIMO RICICLA S= OLDI MAFIOSI LUIGI BERLUSCONI, PRENDE MEGA CAZZI IN CULO OGNI GIORNO E BEVE= LITRI E LITRI DI SBORRA, OGNI ANNO, CI PENSIAMO NOI A FARLO SAPERE ED AL P= IANETA TERRA TUTTO). E DI TIPO MOLTO MA MOLTO DEPRAVATO (AMA IL BERLUSCONI'= S DOUBLE ANAL STYLE, OSSIA, PRENDERE DUE MEGA CAZZI IN CULO, CONTEMPORANEME= NTE, CHE SCHIFO, PUAH)! 4 CRIMINALISSIMO MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI: CON PADRE L'ASS= ASSINO NAZIMAFIOSO, STRAGISTA SPAPPOLA MAGISTRATI, MANDANTE DI MIGLIAIA DI = OMICIDI MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI, VISCIDISSIMO PEDOFI= LO SILVIO BERLUSCONI! E CON FIDANZATA UN NOTO MASSONE DI COSA NOSTRA, CON L= A BARBA. QUESTO: https://www.tuttouomini.it/images/2017/7/luigi-berlusconi-= bacio-gay-estate-amico.jpg E NON CON FIDANZATA LA NOTA TROIA, SEMPRE SCOPATA DA TUTTI IN MILLE CLUB PR= IVE, LA NOTA COCAINOMANE PUTTANA SEMPRE PENETRATA NEL CULO: FEDERICA FUMAGA= LLI. CIAO A TUTTI DA ME, ORA. SONO LA NOTA, VICENTISSIMA PORNOSTAR, MASSONA DI A= LTO GRADO, EX POLITICO DI FORZA ITALIA (MAFIOSA) ED INSEGNANTE IN LOMBARDIA= : MARIA GRAZIA CRUPI. NATA IL 30.10.1969. NOTA IN TUTTO IL MONDO PER ESSERE= STATA PER BEN 12 ANNI, L'AMANTE LESBICA NUMERO DELLA NAZISTA, MEGA RICICLA= SOLDI MAFIOSI, COCAINOMANE, CRIMINALISSIMA MARINA BERLUSCONI ( FRA MIGLIAI= A DI TROIE CHE LA NAZISTA, RICICLA SOLDI SUPER LERCI E CRIMINALISSIMA MARIN= A BERLUSCONI PAGA AFFINCHE' LE LECCHINO LA FIGA... COME DA NOTO PROVERBIO..= . " SANGUE MARCIO MAI MENTE"). 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" PER SEMPRE FUORI DAI COGLIONI") STA IMBASTENDO IN GIRO PER IL = MONDO, VERE E PROPRIE OVRA E GESTAPO ASSASSINE DEL WEB, COL PRIMA CITATO ME= RDONE BERLUSCONICCHIO MARCO CARRAI DI CGNAL E COL NAZI-ST-ALKER, ACCERTATO = PEDERASTA INCULA BAMBINI, FREQUENTISSIMO MANDANTE DI OMICIDI, GIA' TRE VOLT= E FINITO IN CARCERE: PAOLO BARRAI NATO A MILANO IL 28.6.1965 ( O FREQUENTIS= SIMO MANDANTE DI OMICIDI, GIA' TRE VOLTE FINITO IN CARCERE: PAOLO PIETRO BA= RRAI NATO A MILANO IL 28.6.1965 CHE SIA)!!! E SIA CHIARO, PLEASE: IO SONO M= ARIA GRAZIA CRUPI DI MILANO. SONO L'EX AMANTE LESBICA DI MARINA BERLUSCONI. 5 LE HO LECCATO LA FIGA E LE HO MESSO AGGEGGI SESSUALI NEL CULO PER BEN 12 AN= NI. E DI TIPO PERVERTITISSIMO (LO VOLEVA LEI, ME LO IMPONEVA, SEMPRE, LEI).= SE VI E' UNA AMICA INTIMA DI LGBT QUELLA SONO PROPRIO IO. MA DEBBO URLARE = UNA COSA, ADESSO: LUIGI BERLUSCONI PRENDE CAZZI DI 30 CM IN SU FINO ALLA PR= OSTATA, FA BOCCHINI SU BOCCHINI E BEVE LITRI SU LITRI DI SBORRA. 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SI, PROPRIO LUI: L'OMOSESSUALE ^OCCULTO^ LUIGI BERLUSCONI DI BASTARDAMENTE = CRIMINALE ELIGOTECH AMSTERDAM, BASTARDAMENTE CRIMINALE SOLDO LTD LONDON E B= ASTARDAMENTE CRIMINALE BANCA MEDIOLANUM (CHE RICICLANO MONTAGNE DI =E2=82= =AC MAFIOSI, ESATTAMENTE COME FACEVA LA CRIMINALISSIMA BANCA RASINI DI SUO = NONNO, TOPO DI FOGNA LUIGI BERLUSCONI ....O COME FACEVA E FA ORA PIU' CHE M= AI, LA FININVEST DEL PEDOFILO DILANIANTE FALCONE E BORSELLINO: SILVIO BERLU= SCONI http://www.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commission= ate-berlusconi/ E DELLA CRIMINALISSIMA, HITLERIANA, ^OCCULTA" LESBICA MARINA BERLUSCONI https://profile.theguardian.com/user/id/12251903?page=3D1 https://twitter.com/premolisimona?lang=3Den https://twitter.com/premolisimona/status/876055837420158976 https://twitter.com/PremoliSimona/status/946915645756715009 https://twitter.com/PremoliSimona/status/946923968245784576 https://it.linkedin.com/in/simona-lara-premoli-mejia-examante-marina-berlus= coni-77a4b1139 ) INSIEME AL BERLUS-CO-RROTTO VERME MARCO CARRAI DI CGNAL, CREA NAZITECNOLOGI= CHE NUOVE OVRA E GHESTAPO! COL NOTO ANTI SEMITA, GIA' 3 VOLTE FINITO IN CAR= CERE, PAOLO BARRAI, NATO A MILANO IL 28.6.1965 ( FINITO IN CARCERE PURE IN = BRASILE, ED ANCHE PER PEDOFILIA OMOSESSUALE: INCULAVA LI I BAMBINI, NE SCRI= VEREMO PRESTO https://twitter.com/megliomortiche1 http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg )! 6 COL TUTTO, PER FINIRE, UNITISSIMO ALL'ECONOMISTA NOTORIAMENTE MOLTO PEDOFIL= O, NAZISTA ED ASSASSINO PAOLO CARDEN=C3=80 DI CRIMINALISSIMO BLOG VINCITORI= E VINTI http://www.py.cz/pipermail/python/2017-September/013036.html https://a.mytrend.it/authors/1385.jpg NATO A MACERATA IL 2.19.1971 E RESIDENTE A PENNA SAN GIOVANNI (MACERATA), V= IA UMBERTO I, NUMERO 41. COME ANCHE IN VIA POZZO 105, 63837 FALERONE (FM) h= ttps://www.commoditiestrading.it/public/autori/635338392358575000_Cardena.j= pg STO MERDAIO MEGA OMICIDA ERA DIETRO LO STUPRO DI GRUPPO EFFETTUATO A PAMELA= MASTROPIETRO. http://nomassoneriamacerata.blogspot.com/2018/02/lomicidio-di-pamela-mastro= pietro.html A CUI HA FATTO SEGUITO UN RITUALE MASSONICO NAZIFASCISTA, EFFETTUATO PROPRI= O DAL SATANISTA ASSASSINO E PEDOFILO PAOLO CARDENA', PORTANTE ALLA DIVISION= E DEL CORPO DI PAMELA ( EFFETTUATA DA MEDICI LEGALI MASSONI SANGUINARI, COM= E AI TEMPI DEL MOSTRO DI FIRENZE: FRATELLI CRIMINALISSIMI DEI PAZZI OMICIDA= PAOLO CARDENA' E STEFANO CARDENA' DI CRIMINALISSIME CARDENA' AND PARTNERS = E CARDENA' CONSULTING). QUESTO LINK QUADRA OGNI COSA, A PROPOSITO http://m.dagospia.com/clamoroso-a-macerata-sospetti-su-un-giro-di-baby-squi= llo-dietro-l-omicidio-di-pamela-mastropietro-171763 HAN POI TROVATO 4 LORO SCUGNIZZI MASSONICO-MALAVITOSI NIGERIANI PER GIRARE = A LORO OGNI COLPA ( I QUALI, ORA, IN CARCERE, DALTRONDE, AVRANNO VITTO E AL= LOGGIO PER UN TOT DI TEMPO, PIU' TANTI SOLDI QUA E LA, RICEVUTI DA QUESTI N= EO PIDUISTI ASSASSINI, PER STARE ZITTI.. COSI' CHE FRA QUALCHE ANNO USCIRAN= NO DALLE CELLE E SARANNO PURE BENESTANTI). DI QUESTO NE SCRIVONO E DICONO N= OTI MASSONI DI ESTREMA DESTRA STESSA, CHE DI OMICIDI MASSONICI NE HAN VISTI= TANTI. QUALI FABIO FRABETTI, PAOLO FRANCESCHETTI E SPECIALMENTE GIANFRANCO= CARPEORO, IN REALTA', A LIVELLO DI VERO NOME E COGNOME, GIANFRANCO PECORAR= O, ( CHE, COME DETTO, VIA MARI DI LOGGE MASSONICHE, SON ADDENTRO DA UNA VIT= A A QUESTO TIPO DI OMICIDI, QUINDI, SANNO ALLA PERFEZIONE OGNI COSA A PROPO= SITO) http://petalidiloto.com/2018/02/due-parole-sullomicidio-pamela-mastropietro= .html http://petalidiloto.com/2012/12/intervista-carpeoro-su-massoneria-e.html QUESTO E' SONO UN ANTIPASTINO. I PIATTI FORTI ARRIVERANNO AL PIU' PRESTO PO= SSIBILE. O IL PEDOFILO SPAPPOLA MAGISTRATI... O IL NAZIMAFIOSO ASSASSINO SILVIO BERLUSCONI.. O IL DITTATORE COCAINOMANE DISTRUGGI VITE ALTRUI SILVIO BERLUSCONI.. .. AMMETTE IL MALE INGIUSTIFICATISSIMO FATTO, .. AMMETTE IL MALE DAVVERO INGIUSTISSIMO ED OMICIDA, FATTO ( SA' BENISSIMO = A CHE E CHI MI RIFERISCO). E RISARCISCE. O LA GIUSTIZIA LA FARO' IO. NEI SU= OI CONFRONTI E NEI CONFRONTI DI TUTTI I PORCI E VERMI CHE RADONO AL SUOLO V= ITE DI INNOCENTI, PER LUI! PER SUA BORIA, SATANAZIFASCISMO, COCAINA, SOLDI = MAFIOSI, ARROGANZA, ORGE PEDOFILESCHE, SCORCIATOIE SOCIALI, PREPOTENZA, EGO= CENTRISMO, ANTIDEMOCRAZIA, PERVERSIONE, CORRUZIONE, COSA NOSTRA, CAMORRA, N= DRANGHETA, SACRA CORONA UNITA, VANITA', BRAMA DI CAMMINARE A MORTE SULLE ES= ISTENZE ALTRUI. O FATTI O CAZZI AMARI, DA ORA E PER SEMPRE, PER GLI ASSASSI= NI, STRAGISTI, NAZIMAFIOSI, EFFERATISSIMI CRIMINALI IN FIGHETTINA E MOLTO, = MA MOLTO MALAVITOSA CRAVATTA: BERLUSCONI! http://the8club-pasar-komoditi.blogspot.com/2018/06/sborrato-dentro-al-culo= -luigi.html From newsfish@newsfish Thu Aug 1 00:44:22 2024 X-Received: by 2002:aed:3804:: with SMTP id j4mr32853068qte.361.1558437180446; Tue, 21 May 2019 04:13:00 -0700 (PDT) X-Received: by 2002:a25:ba0b:: with SMTP id t11mr36027193ybg.133.1558437180081; Tue, 21 May 2019 04:13:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!c48no2644005qtc.0!news-out.google.com!i13ni814qtr.0!nntp.google.com!c48no2643995qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 May 2019 04:12:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.255.51.195; posting-account=SWOeEgoAAADAfTMsgLrhpAAOtEVjk8Di NNTP-Posting-Host: 62.255.51.195 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81df8a4b-828d-4688-8abe-efd008969c2a@googlegroups.com> Subject: METHOD: TestBench How to? Verification over "Generic" parameters From: Edward Fisher Injection-Date: Tue, 21 May 2019 11:13:00 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 41 Xref: reader01.eternal-september.org comp.lang.vhdl:9456 Hello all,=20 To aid re-use, my VHDL is heavily parameterised using generics. For example= bus, bit-widths, counter maximums, reset high/low etc. During test benching, these can of course be passed to a UUT via generic ma= p (), but they are treated as block instantiation constants evaluated at el= aboration time and cannot be changed as part of the test bench's process. Scenario: - Lets say we have a 8-bit counter (BIT_WIDTH =3D 8) which is given a hard= maximum value of 200 (COUNT_MAX =3D 200). Lets also say we have a block re= set that is active high (RST_LEVEL =3D '1'). I may also have a generate sta= tement in my design that allows the synthesis (or not) of some parity bits = (INCLUDE_PARITY =3D TRUE). - In my test bench, I may have a series of tests that provide some test ve= ctors. For resets etc, these can use the defined value of RST_LEVEL. Howeve= r, when it comes to the checking the full scope of the code the test vector= s are increased by my use of generics. Reset may only be 0 or 1, but it can= be logic high or low, i.e. 4 vectors not 2. If parity is included, I need = to check these outputs, but they will be undefined or coded to zeros if INC= LUDE_PARITY =3D FALSE. Likewise, as the counter is parameterised, perhaps I= want to check that this is correct over a range of bit-widths (8, 16, 32 o= r say 12 or 14 etc), the count maximum could also change. Question: - For cases where the use of generics increases the possibility space for t= est vectors and automatic tests, I have previously ran the test bench twice= , first for (BIT_WIDTH =3D 8) and then for (BIT_WIDTH =3D 16). However, jus= t like my man test vectors, I'd prefer to do this in an automated manner. - From a test methodology perspective, how do you easily test across multi= ple generics, not only testing over the possible physical input vectors, bu= t also testing over a large variety of generic combinations? For Example: - (BIT_WIDTH =3D 8)(RST_LEVEL =3D '1') - All test vectors, then=20 - (BIT_WIDTH =3D 8)(RST_LEVEL =3D '0') - All test vectors, then=20 - (BIT_WIDTH =3D 16)(RST_LEVEL =3D '1') - All test vectors, then - (BIT_WIDTH =3D 16)(RST_LEVEL =3D '0') - All test vectors etc. Many thanks, Ed From newsfish@newsfish Thu Aug 1 00:44:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (gtwrek) Newsgroups: comp.lang.vhdl Subject: Re: METHOD: TestBench How to? Verification over "Generic" parameters Date: Tue, 21 May 2019 16:23:27 -0000 (UTC) Organization: Sonic Lines: 78 Message-ID: References: <81df8a4b-828d-4688-8abe-efd008969c2a@googlegroups.com> Injection-Date: Tue, 21 May 2019 16:23:27 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="ba6f015ea353a6259996682c61829a59"; logging-data="24831"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19KysqX4gNV45kRL0qyLebM" Cancel-Lock: sha1:T32EE6vao3YtgESIEHEIU1Bz9FM= Originator: gtwrek@sonic.net (gtwrek) X-Newsreader: trn 4.0-test77 (Sep 1, 2010) Xref: reader01.eternal-september.org comp.lang.vhdl:9457 In article <81df8a4b-828d-4688-8abe-efd008969c2a@googlegroups.com>, Edward Fisher wrote: >Hello all, > >To aid re-use, my VHDL is heavily parameterised using generics. For example bus, bit-widths, counter maximums, reset high/low etc. > >During test benching, these can of course be passed to a UUT via generic map (), but they are treated as block instantiation constants evaluated at elaboration time and >cannot be changed as part of the test bench's process. > >Scenario: > - Lets say we have a 8-bit counter (BIT_WIDTH = 8) which is given a hard maximum value of 200 (COUNT_MAX = 200). Lets also say we have a block reset that is active high >(RST_LEVEL = '1'). I may also have a generate statement in my design that allows the synthesis (or not) of some parity bits (INCLUDE_PARITY = TRUE). > - In my test bench, I may have a series of tests that provide some test vectors. For resets etc, these can use the defined value of RST_LEVEL. However, when it comes to the >checking the full scope of the code the test vectors are increased by my use of generics. Reset may only be 0 or 1, but it can be logic high or low, i.e. 4 vectors not 2. If >parity is included, I need to check these outputs, but they will be undefined or coded to zeros if INCLUDE_PARITY = FALSE. Likewise, as the counter is parameterised, perhaps >I want to check that this is correct over a range of bit-widths (8, 16, 32 or say 12 or 14 etc), the count maximum could also change. > >Question: >- For cases where the use of generics increases the possibility space for test vectors and automatic tests, I have previously ran the test bench twice, first for (BIT_WIDTH >= 8) and then for (BIT_WIDTH = 16). However, just like my man test vectors, I'd prefer to do this in an automated manner. > - From a test methodology perspective, how do you easily test across multiple generics, not only testing over the possible physical input vectors, but also testing over a >large variety of generic combinations? > >For Example: > - (BIT_WIDTH = 8)(RST_LEVEL = '1') - All test vectors, then > - (BIT_WIDTH = 8)(RST_LEVEL = '0') - All test vectors, then > - (BIT_WIDTH = 16)(RST_LEVEL = '1') - All test vectors, then > - (BIT_WIDTH = 16)(RST_LEVEL = '0') - All test vectors etc. > Edward, I can offer some advice from a verilog user's perspective. We parameterize our designs extensively too. Some general advice first - Dont use parameters where a (perhaps constant) input would work just as well. In your examples, COUNT_MAX, RST_LEVEL, INCLUDE_PARITY, can likely be changed to component inputs instead of parameters. Reserve the use of parameter/generics to case where it's absolutely required. This has many advantages - both from a test and use-case perspective. >From a test perspective, the advantages should be obvious - as it addresses the specific concerns your trying to solve. These "configuration" inputs are not run-time constants - hence your testbenches can change them, as needed. >From a design reuse perspective, it's an advantage as the component is well, more reusable. Just because in the one use case that parameter is a constant doesn't mean that in other use-cases making it a variable (perhaps with constraints on when it may be changed) isn't needed. I can't tell you how many times I have something simple - like your COUNT_MAX example where I originally coded it as a parameter, then sometime down the road realize I needed it to be semi-variable, and had to recode it as such. >From a Synthesis QoR point of view - I've done MANY examples of comparisions between a constant parameter, and a constant input. Synthesis may take different paths with the different coding styles, one may take longer than the other to build. But in the end, the QoR differences are in the noise. The synthesis optimizers are QUITE good these days - it'a mature technology. So - minimize your parameter/generic set first. Then, you're left with a verification corners on the remaining parameter sets. This is, as you've found really outside the scope of a simulator. This just means you need to move the task up - to scripts that drive multiple simulation runs. When designing your reusable modules encourage your designers to list - and even check with assertions - the limits and acceptable values for your parameter sets. Then use these limits to either 1.) Drive the verification over ALL corners (when achievable) or 2.) Verify certain directed corners (i.e. your specific use cases) + random parameter sets. Regards, Mark From newsfish@newsfish Thu Aug 1 00:44:22 2024 X-Received: by 2002:a0c:878e:: with SMTP id 14mr72895397qvj.103.1558530419289; Wed, 22 May 2019 06:06:59 -0700 (PDT) X-Received: by 2002:a81:5155:: with SMTP id f82mr41225776ywb.53.1558530418825; Wed, 22 May 2019 06:06:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!c48no455781qtc.0!news-out.google.com!i13ni106qtr.0!nntp.google.com!c48no455770qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 May 2019 06:06:58 -0700 (PDT) In-Reply-To: <81df8a4b-828d-4688-8abe-efd008969c2a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=204.19.223.246; posting-account=w728HAoAAAAF2xrMb6mkfbhZUlYwqJjV NNTP-Posting-Host: 204.19.223.246 References: <81df8a4b-828d-4688-8abe-efd008969c2a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: METHOD: TestBench How to? Verification over "Generic" parameters From: KKoorndyk Injection-Date: Wed, 22 May 2019 13:06:59 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 62 Xref: reader01.eternal-september.org comp.lang.vhdl:9458 On Tuesday, May 21, 2019 at 7:13:02 AM UTC-4, Edward Fisher wrote: > Hello all,=20 >=20 > To aid re-use, my VHDL is heavily parameterised using generics. For examp= le bus, bit-widths, counter maximums, reset high/low etc. >=20 > During test benching, these can of course be passed to a UUT via generic = map (), but they are treated as block instantiation constants evaluated at = elaboration time and cannot be changed as part of the test bench's process. >=20 > Scenario: > - Lets say we have a 8-bit counter (BIT_WIDTH =3D 8) which is given a ha= rd maximum value of 200 (COUNT_MAX =3D 200). Lets also say we have a block = reset that is active high (RST_LEVEL =3D '1'). I may also have a generate s= tatement in my design that allows the synthesis (or not) of some parity bit= s (INCLUDE_PARITY =3D TRUE). > - In my test bench, I may have a series of tests that provide some test = vectors. For resets etc, these can use the defined value of RST_LEVEL. Howe= ver, when it comes to the checking the full scope of the code the test vect= ors are increased by my use of generics. Reset may only be 0 or 1, but it c= an be logic high or low, i.e. 4 vectors not 2. If parity is included, I nee= d to check these outputs, but they will be undefined or coded to zeros if I= NCLUDE_PARITY =3D FALSE. Likewise, as the counter is parameterised, perhaps= I want to check that this is correct over a range of bit-widths (8, 16, 32= or say 12 or 14 etc), the count maximum could also change. >=20 > Question: > - For cases where the use of generics increases the possibility space for= test vectors and automatic tests, I have previously ran the test bench twi= ce, first for (BIT_WIDTH =3D 8) and then for (BIT_WIDTH =3D 16). However, j= ust like my man test vectors, I'd prefer to do this in an automated manner. > - From a test methodology perspective, how do you easily test across mul= tiple generics, not only testing over the possible physical input vectors, = but also testing over a large variety of generic combinations? >=20 > For Example: > - (BIT_WIDTH =3D 8)(RST_LEVEL =3D '1') - All test vectors, then=20 > - (BIT_WIDTH =3D 8)(RST_LEVEL =3D '0') - All test vectors, then=20 > - (BIT_WIDTH =3D 16)(RST_LEVEL =3D '1') - All test vectors, then > - (BIT_WIDTH =3D 16)(RST_LEVEL =3D '0') - All test vectors etc. >=20 > Many thanks, > Ed I typically use VHDL Configurations to accomplish this. If you have the 3r= d Edition of the Ashenden book, check out Chapter 13. Doulos has a decent = overview: https://www.doulos.com/knowhow/vhdl_designers_guide/configuration= s_part_1/ And Sigasi has a good detailed example illustrating how to define the gener= ic port maps: https://insights.sigasi.com/tech/advanced-vhdl-configuration= s-tying-component-unrelated-entity.html I have successfully employed this methodology to develop a full suite of te= st cases covering all (or a specific subset) permutations of generic port v= alues. I end up with a separate VHDL Configuration for each test case, but= it makes my testbench architecture generic (meaning a single architecture = for all test cases) and it makes running regressions and generating code co= verage results quite easy. It sounds like you might even have be able to employ a single test case tha= t uses those generics, which is exactly what I did for my most recent desig= n. From newsfish@newsfish Thu Aug 1 00:44:23 2024 X-Received: by 2002:a24:910b:: with SMTP id i11mr1907798ite.76.1559019485004; Mon, 27 May 2019 21:58:05 -0700 (PDT) X-Received: by 2002:a81:98cd:: with SMTP id p196mr37049273ywg.366.1559019484763; Mon, 27 May 2019 21:58:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.166.216.MISMATCH!i64no434206iti.0!news-out.google.com!l135ni90itc.0!nntp.google.com!c92no433976itd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 27 May 2019 21:58:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.65.42.185; posting-account=-GHnfgoAAAD_k0Op5NFtAvWDdXR4MrRS NNTP-Posting-Host: 109.65.42.185 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: SD slave with Samsung flash. From: pini@rachip.com Injection-Date: Tue, 28 May 2019 04:58:04 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9459 Hi I saw this SD code. Any one try it. "...SD slave project was extended recently to support a Samsung flash instead of the XILINX ROM components, which are used in the free version of the code." ...p://bknpk.dynu.com/my_web/SDIO/sd_to_flash_write.html From newsfish@newsfish Thu Aug 1 00:44:23 2024 X-Received: by 2002:ac8:877:: with SMTP id x52mr12287460qth.328.1559352270237; Fri, 31 May 2019 18:24:30 -0700 (PDT) X-Received: by 2002:a25:4489:: with SMTP id r131mr6427555yba.14.1559352270087; Fri, 31 May 2019 18:24:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!c48no1251870qtc.0!news-out.google.com!i13ni440qtr.0!nntp.google.com!c48no1251865qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 31 May 2019 18:24:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=65.92.40.204; posting-account=-3m9WQoAAADqph1cWZ4uX0b-9dwN4Ozr NNTP-Posting-Host: 65.92.40.204 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Safe State Machine with Conditional when others From: digitalguy33@gmail.com Injection-Date: Sat, 01 Jun 2019 01:24:30 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 13 Xref: reader01.eternal-september.org comp.lang.vhdl:9460 Can you make a finite state machine with a when others clause that has a conditional statement inside? This would be for synthesizing a "safe case" state machine with Synplify Pro. For example: when others => if (a = ''1') then next_state <= IDLE; elsif (b = '1') then next_state <= READ; else next_state <= ERROR; end if; I have never actually done this before before and have only seen simple "when others" with only a single state assignment. From newsfish@newsfish Thu Aug 1 00:44:23 2024 X-Received: by 2002:ac8:2ea1:: with SMTP id h30mr11736758qta.333.1559353244517; Fri, 31 May 2019 18:40:44 -0700 (PDT) X-Received: by 2002:a25:9cc1:: with SMTP id z1mr6603157ybo.133.1559353244356; Fri, 31 May 2019 18:40:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!c48no1258506qtc.0!news-out.google.com!i13ni440qtr.0!nntp.google.com!c48no1258498qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 31 May 2019 18:40:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=4.15.102.76; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 4.15.102.76 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <499afb0e-155e-4dcf-997f-1503534b2ce0@googlegroups.com> Subject: Safe State Machine with Conditional when others From: KJ Injection-Date: Sat, 01 Jun 2019 01:40:44 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9461 Yes From newsfish@newsfish Thu Aug 1 00:44:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.fr7!futter-mich.highwinds-media.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx33.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Safe State Machine with Conditional when others Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190602-0, 02/06/2019), Outbound message X-Antivirus-Status: Clean Lines: 27 Message-ID: <5XQIE.778275$0R6.46535@fx33.am4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Sun, 02 Jun 2019 14:20:49 UTC Organization: virginmedia.com Date: Sun, 2 Jun 2019 15:20:50 +0100 X-Received-Bytes: 2144 X-Received-Body-CRC: 3138087134 Xref: reader01.eternal-september.org comp.lang.vhdl:9462 On 01/06/2019 02:24, digitalguy33@gmail.com wrote: > Can you make a finite state machine with a when others clause that has a conditional statement inside? This would be for synthesizing a "safe case" state machine with Synplify Pro. > > For example: > > when others => > if (a = ''1') then > next_state <= IDLE; > elsif (b = '1') then > next_state <= READ; > else > next_state <= ERROR; > end if; > > I have never actually done this before before and have only seen simple "when others" with only a single state assignment. > You will find most synthesis tools (including Synplify Pro?) can do this automatically for you, search your manual for safe FSM attribute. Some HiRel tools used in the space industry will have the additional options to add FEC to your FSM. This means that your FSM can either detect an illegal state (and jump to a recovery state) or correct the illegal state and continue as normal (assuming you don't to many bit flips in the same clock cycle). Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:24 2024 X-Received: by 2002:a37:4781:: with SMTP id u123mr22036516qka.284.1559567446549; Mon, 03 Jun 2019 06:10:46 -0700 (PDT) X-Received: by 2002:a25:ca8d:: with SMTP id a135mr8648589ybg.438.1559567446320; Mon, 03 Jun 2019 06:10:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.swapon.de!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!c48no2772332qtc.0!news-out.google.com!l95ni400qte.0!nntp.google.com!c48no2772323qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Jun 2019 06:10:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <79a5c1e2-1a53-4cb4-80d6-7297bb73b2fe@googlegroups.com> Subject: Re: Safe State Machine with Conditional when others From: Thomas Stanka Injection-Date: Mon, 03 Jun 2019 13:10:46 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 39 Xref: reader01.eternal-september.org comp.lang.vhdl:9463 Am Samstag, 1. Juni 2019 03:24:32 UTC+2 schrieb digita...@gmail.com: > I have never actually done this before before and have only seen simple "when others" with only a single state assignment. I think the answer is obvious for you when you consider a simple fsm with all (2^n) states used. In case you use enumerated types you could have a case with a branch for each state explicit as selector (eg case state1=>...case state4=>.. end case;), but you could also have the fourth state selected by others ("case others => do_all_state4_stuff()".) In general you should not mix up the function of Synplify Pro for safe state and the others-part. Synplify Pro detectes when an others-clause is never reached and optimizes those states regardless of your code. There is no functional difference for Synplify between type state_t is (idle, do1, do2) .. case idle => wait_and_goto_do1() do1=> wait_and_goto_do2() do2 => wait_and_goto_idle() end case and type state_t is (idle, do1, do2, notused) .. case idle => wait_and_goto_do1() do1=> wait_and_goto_do2() do2 => wait_and_goto_idle() others => goto_idle() end case The functionality of Safe-FSM-encoding is also not changed by those two code snipplets (for all those version of Synplify I tried up to now). A real difference would be, if you would set the state "notused" as reset-value for the fsm as this ensures all four states are reachable and could not optimised away. regards, Thomas From newsfish@newsfish Thu Aug 1 00:44:24 2024 X-Received: by 2002:a0c:adef:: with SMTP id x44mr1651803qvc.153.1559568581938; Mon, 03 Jun 2019 06:29:41 -0700 (PDT) X-Received: by 2002:a81:148b:: with SMTP id 133mr1159689ywu.394.1559568581833; Mon, 03 Jun 2019 06:29:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!c48no2782114qtc.0!news-out.google.com!l95ni400qte.0!nntp.google.com!c48no2782109qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Jun 2019 06:29:41 -0700 (PDT) In-Reply-To: <81df8a4b-828d-4688-8abe-efd008969c2a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <81df8a4b-828d-4688-8abe-efd008969c2a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <275d6549-f74e-4cda-a023-0bf24e18e1a0@googlegroups.com> Subject: Re: METHOD: TestBench How to? Verification over "Generic" parameters From: Thomas Stanka Injection-Date: Mon, 03 Jun 2019 13:29:41 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 17 Xref: reader01.eternal-september.org comp.lang.vhdl:9464 Am Dienstag, 21. Mai 2019 13:13:02 UTC+2 schrieb Edward Fisher: > To aid re-use, my VHDL is heavily parameterised using generics. For example bus, bit-widths, counter maximums, reset high/low etc. [..] > - From a test methodology perspective, how do you easily test across multiple generics, not only testing over the possible physical input vectors, but also testing over a large variety of generic combinations? > > For Example: > - (BIT_WIDTH = 8)(RST_LEVEL = '1') - All test vectors, then > - (BIT_WIDTH = 8)(RST_LEVEL = '0') - All test vectors, then > - (BIT_WIDTH = 16)(RST_LEVEL = '1') - All test vectors, then > - (BIT_WIDTH = 16)(RST_LEVEL = '0') - All test vectors etc. Are you aware that your testbench entity is allowed to have generics so it is possible to pass bitwidth etc to your testbench. Those generics could be set by simulator start (eg for modelsim: vsim -G BIT_WIDTH=8). You could setup a "super testbench" eg in tcl or python to iterate over the set of generics you like to have tested. regards, Thomas From newsfish@newsfish Thu Aug 1 00:44:25 2024 X-Received: by 2002:ad4:5426:: with SMTP id g6mr7194847qvt.132.1559691377565; Tue, 04 Jun 2019 16:36:17 -0700 (PDT) X-Received: by 2002:a25:cf0d:: with SMTP id f13mr15877594ybg.323.1559691377407; Tue, 04 Jun 2019 16:36:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!c48no119690qtc.0!news-out.google.com!b26ni0qtp.1!nntp.google.com!c48no119689qtc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Jun 2019 16:36:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <60d9b805-61a7-425d-b339-a2b5a191aab0@googlegroups.com> Subject: Re: Safe State Machine with Conditional when others From: Rick C Injection-Date: Tue, 04 Jun 2019 23:36:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 32 Xref: reader01.eternal-september.org comp.lang.vhdl:9465 On Friday, May 31, 2019 at 9:24:32 PM UTC-4, digita...@gmail.com wrote: > Can you make a finite state machine with a when others clause that has a = conditional statement inside? This would be for synthesizing a "safe case"= state machine with Synplify Pro. >=20 > For example: >=20 > when others =3D> > if (a =3D ''1') then > next_state <=3D IDLE; > elsif (b =3D '1') then > next_state <=3D READ; > else > next_state <=3D ERROR; > end if; >=20 > I have never actually done this before before and have only seen simple "= when others" with only a single state assignment. I believe you are asking about coding a state machine in VHDL, not anything= specific to Synplify Pro. A VHDL synthesis tool doesn't really know you a= re coding a state machine. It just sees the logic you are implementing and= implements that logic in the technology of your target. So you can put an= y conditionals anywhere you want and the state machine will do exactly what= you are specifying. The only problem is if your HDL is not really describ= ing what you think it is. Then that is what simulation is for.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:25 2024 X-Received: by 2002:a37:b5c5:: with SMTP id e188mr10892226qkf.55.1560018522579; Sat, 08 Jun 2019 11:28:42 -0700 (PDT) X-Received: by 2002:a81:3d58:: with SMTP id k85mr30553211ywa.30.1560018522391; Sat, 08 Jun 2019 11:28:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!j96no2147834qte.0!news-out.google.com!d20ni301qtd.0!nntp.google.com!j96no2147833qte.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 8 Jun 2019 11:28:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.37.126.142; posting-account=GFafwQoAAABAnCTWaUu8pHQKW4yiH6lh NNTP-Posting-Host: 62.37.126.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <59a0d79e-3103-4484-8d05-8e001883fdad@googlegroups.com> Subject: E' ZOCCOLA SEMPRE SCOPATA IN CULO: COSTANZA RACHELE BARRAI! NOTA PUTTANA COCAINOMANE NATA A MILANO IL 1.1.1999. SCHIFOSISSIMA TROIA COSTANZA RACHELE BARRAI: SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA, PRESSO L'INTERNATIONAL SCHOOL MILA From: SBORRATISSIMAINCULO COSTANZA BARRAI MEGACOCAINOMAN Injection-Date: Sat, 08 Jun 2019 18:28:42 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 197 X-Received-Bytes: 15486 X-Received-Body-CRC: 820475597 Xref: reader01.eternal-september.org comp.lang.vhdl:9466 E' ZOCCOLA SEMPRE SCOPATA IN CULO: COSTANZA RACHELE BARRAI! NOTA PUTTANA CO= CAINOMANE NATA A MILANO IL 1.1.1999. SCHIFOSISSIMA TROIA COSTANZA RACHELE B= ARRAI: SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA, PRESSO L'= INTERNATIONAL SCHOOL MILANO!! LURIDA MIGNOTTA COSTANZA RACHELE BARRAI: SEMP= RE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA PRESSO L'UNIVERSITY O= F BATH!! DEPRAVATA BAGASCIA COSTANZA RACHELE BARRAI: SEMPRE A CIUCCIARE E P= RENDERE CAZZI IN CULO, FIGA E BOCCA PRESSO IL QMI!! PERVERTITA ZOCCOLA COST= ANZA RACHELE BARRAI: SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BO= CCA PRESSO SONY PICTURES ENTERTAINMENT (https://uk.linkedin.com/in/costanza= -rachele-barrai-3a5b97a7 ) !!!!!!!!! FACENTE FILM PORNO AMATORIALI A GO GO!= PRENDENTE NELL'ANO CAZZI "ESOTICI" PURE DI 30 CM! D'ALTRONDE..VENNE SEMPRE= INCULATA, DA QUANDO BAMBINA, DA NOTO PADRE PEDOFILO PAOLO BARRAI, NATO A M= ILANO IL 28.6.65! =E3=80=80 A PROPOSITO DEL CRIMINALISSIMO QUALE... E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965. NON= CHE' MEGA RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI MEGA R= UBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA E STRAGISTA SPAPPOLA MAGIS= TRATI, NONCHE', TANTO QUANTO, NAZIFASCISTA DITTATORE E PEDOFILO: SILVIO BER= LUSCONI! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TER= RORISTA NAZISTA ED ASSASSINO, PAOLO BARRAI. NON PER NIENTE, GIA' STATO IN G= ALERA 3 VOLTE. OPINIONI TUTTE TERRIFICANTI SU DI LUI! MEGA TRUFFATORE E MEG= A RICICLA CASH ASSASSINO VIA CRIMINALISSIMA BLOCKCHAIN INVEST O VIA CRIMINA= LISSIMA BLOCKCHAININVEST CHE SIA, OLTRE CHE VIA CRIMINALISSIMA WMO SAGL LUG= ANO, CRIMINALISSIMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA P= ANAMA E CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO! NOTO PEDOFI= L-O-MOSESSUALE SODOMIZZA BAMBINI E RAGAZZINI! CACCIATO DA CITIBANK A SBERLE= , PER MEGA FRODI CHE LI FACEVA! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI = DI CENTINAIA E CENTINAIA DI PERSONE! FALSO&LADRO&TRUFFATORE! DIFFAMA SUL WE= B A FINI NAZIRAZZISTI! FONDATORE DEI NUOVI MEGASSASSINI TERRORISTI DI ESTRE= MISSIMA DESTRA: "NUOVI NAR"! FONDATORE DEL, PROSSIMAMENTE, DI FREQUENTE, OM= ICIDA: KU KLUK KLAN PADANO! CONDANNATO AL CARCERE A MILANO ED IN BRASILE ( = 8 ANNI E PURE PER PEDERASTIA OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSE= SSUALE)! MULTATO DA CONSOB 70.000 =E2=82=AC! DESTABILIZZA L'ITALIA PER FILO= NAZISTI SERVIZI SEGRETI SVIZZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTISSI= MAMENTE, NAZIONE SCHIFATA IN TUTTO IL MONDO, IN QUANTO FASCIOMAFIOSA DITTAT= URA DI BERLUSCONIA.. NON PER NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITA= LIA DA SECOLI, DALLA TIRANNIASSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIA= T, PIRELLI, LUXOTTICA, MERLONI E MIGLIAIA E MIGLIAIA DI ALTRE... E CHE SIA = CHIARO, PLS, CHE IDDIO BENEDICA I GRANDI PM CHE NON SOPPORTANTO IL CANCRO D= EL MONDO INTERO, SILVIO BERLUSCONI, COME HENRY WOODCOCK, ILDA BOCASSINI E C= HIUNQUE ALTRO DI QUESTA AMMIREVOLISSIMA CATEGORIA)! FA CRIMINI SU CRIMINI E= NAZI-ST-ALKING, SU INTERNET, SU ORDINE DEI PUZZONI CRIMINALISSIM SILVIO BE= RLUSCONI, PAOLO BERLUSCONI ED UBALDO LIVOLSI DI FININVEST ( CHE DA ANNI FAN= NO GLI ADOLPH HITLER MISTI AD AL CAPONE, DEL WEB, ANCHE, MA DI CERTO, NON S= OLO, CON QUEL VERME SCHIFOSAMENTE TERRORISTA DI GIULIO OCCHIONERO). INNEGGI= ANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GRANDISSIMAM= ENTE FECE CON FALCONE E BORSELLINO"! PAROLE SUE, DETTE SPESSISSIMO! ORGANIZ= ZANTE OMICIDIO DI DAVID ROSSI DI MONTE PASCHI! Ho tantissimo da scrivere sul gia' 3 volte finito in galera, accertatissimo= pedofilo omosessuale, ladro, truffatore, sempre falso, nazi-st-alker, mand= ante di omicidi ( spesso, ma non sempre, mascherati da finti incidenti, mal= ori o "suicidate"... come quando fece ammazzare David Rossi di Monte Paschi= , ma ne scrivero' in dettagli molto presto), mega ricicla soldi mafiosi e/o= politico-criminali (piu' tanto di orrido altro), arrestato gia' 3 volte, P= aolo Barrai, nato a Milano il 28.6.1965 e gia' residente a Milano in Via Ip= podromo 105! Come presto meglio sottolineeremo, multato dalla Consob ben 70= .000 euro! http://www.bluerating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un= -ex-promotore-che-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion http://www.maidireborsa.it/showthread.php?27302-Paolo-Barrai-di-Mercato-Lib= ero-sanzionato-dalla-Consob VI SONO TONNELLATE DI ALTRE COSE DA DIRE SU QUANTO SIA BASTARDO EFFERATO CR= IMINALE E PEDOFILO PAOLO BARRAI. TROVATE UNA PARTE ( CHE PRESTO AMPLIEREMO = ALL'INFINITO), QUI: https://twitter.com/megliomortiche1 ALWAYS SODOMIZED BY 30 CM LONG DICKS: COSTANZA RACHELE BARRAI, BORN IN MILA= N ON 1.1.1999. ALWAYS GETTING HUGE DICKS IN THE ASS, PUSSY AND MOUTH BY THE= INTERNATIONAL SCHOOL MILAN. STINKY, NASTY BITCH COSTANZA RACHELE BARRAI: A= LWAYS GETTING HUGE DICKS IN THE ASS, PUSSY AND MOUTH BY UNIVERSITY OF BATH.= STINKY, NASTY BITCH COSTANZA RACHELE BARRAI: ALWAYS GETTING HUGE DICKS IN = THE ASS, PUSSY AND MOUTH BY QMI. STINKY, NASTY BITCH COSTANZA RACHELE BARRA= I: ALWAYS GETTING HUGE DICKS IN THE ASS, PUSSY AND MOUTH BY SONY PICTURES = ENTERTAINMENT (https://uk.linkedin.com/in/costanza-rachele-barrai-3a5b97a7)= . E' SEMPRE SCOPATA E SBORRATA IN CULO: COSTANZA RACHELE BARRAI! LA PUTTANO= NA NATA A MILANO IL 1.1.1999. SCHIFOSISSIMA TROIA COSTANZA RACHELE BARRAI: = SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA, PRESSO L'INTERNA= TIONAL SCHOOL MILANO! SCHIFOSISSIMA TROIA COSTANZA RACHELE BARRAI: SEMPRE A= CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA PRESSO L'UNIVERSITY OF BA= TH. SCHIFOSISSIMA TROIA COSTANZA RACHELE BARRAI: SEMPRE A CIUCCIARE E PREND= ERE CAZZI IN CULO, FIGA E BOCCA PRESSO IL QMI. SCHIFOSISSIMA TROIA COSTANZA= RACHELE BARRAI: SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA = PRESSO SONY PICTURES ENTERTAINMENT (https://uk.linkedin.com/in/costanza-rac= hele-barrai-3a5b97a7) ! FACENTE FILM PORNO A GO GO! PRENDENTE NELL'ANO CAZZ= I "ESOTICI" PURE DI 30 CM! D'ALTRONDE..VENNE SEMPRE INCULATA, DA QUANDO BAM= BINA, DA NOTO PADRE PEDOFILO PAOLO BARRAI! SU CUI TROVATE NON POCHISSIMO, QUI! https://twitter.com/megliomortiche1 https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg SI... E=C2=B4 SBORRATA SEMPRE TUTTA DENTRO AL CULO: COSTANZA BARRAI! NATA A= MILANO IL 1.1.1999, BORN IN MILAN ON 1.1.1999! EX INTERNATIONAL SCHOOL MIL= AN. DICIOTTENNE E FA FILM PORNO A GO GO! https://i1.sndcdn.com/avatars-000123698582-6zu6yw-t500x500.jpg https://uk.linkedin.com/in/costanza-rachele-barrai-3a5b97a7 PRENDENDO PROFONDAMENTE NEL CULO CAZZI "ESOTICI" PURE DI 30-32-35 CM ( E LE= PIACE SEMPRE DI PIU', SEMPRE DI PIU', SEMPRE DI PIU')! D'ALTRONDE..VENNE, = GIA' DALLA NASCITA, SODOMIZZATA DAL BASTARDO CRIMINALISSIMO PADRE. NOTO PED= OFILO PAOLO BARRAI. NATO A MILANO IL 28.6.1965 ( E NOTO PEDERASTA INCULA BA= MBINI ERA PURE SUO NONNO, SCHIFOSISSIMO PEDOFILO VINCENZO BARRAI ABITANTE I= N VIA PADOVA 282 A MILANO E NATO A MILANO IL 3.5.1938... A "KAPO' " DI SCHI= FOSISSIMAMENTE MALAVITOSA BSI ITALIA SRL MILANO, VIA SOCRATE 26 https://= grokbase.com/t/gg/tasker/162ghxnpsb/vermi-criminali-di-bsi-italia-srl-via-s= ocrate-26-milano-di-noti-pedofili-paolo-barrai-e-vincenzo-barrai-oltre-che-= nazi-ladri-truffatori-lava-cash-mafioso-o-frutto-di-stecche-e-furti-di-lega= -ladrona-ex-pdl-popolodiladroni-i-barrai-omicida )! E A PROPOSITO DI STI ULTIMI DUE BASTARDISSIMI MOSTRI.... E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965. NON= CHE' MEGA RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI MEGA R= UBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA E STRAGISTA SPAPPOLA MAGIS= TRATI, NONCHE', TANTO QUANTO, NAZIFASCISTA DITTATORE E PEDOFILO SILVIO BERL= USCONI! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERR= ORISTA NAZISTA ED ASSASSINO, PAOLO BARRAI ( ASSICURANDOSI CHE QUESTA VOLTA = RIMANGA IN CARCERE PER SEMPRE O PER LO MENO PER DECENNI E DECENNI). NON PER= NIENTE, GIA' STATO IN GALERA 3 VOLTE. OPINIONI TUTTE TERRIFICANTI SU DI LU= I! MEGA TRUFFATORE E MEGA RICICLA CASH LERCIO CHE PIU' LERCIO NON SI POTREB= BE, VIA CRIMINALISSIMA BLOCKCHAIN INVEST, OLTRE CHE VIA CRIMINALISSIMA WORL= D MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA E CRIMINALISSIMA B= SI ITALIA SRL DI VIA SOCRATE 26 MILANO! NOTO PEDOFIL-O-MOSESSUALE SODOMIZZA= BAMBINI PAOLO BARRAI! CACCIATO DA CITIBANK A SBERLE, PER MEGA FRODI CHE LI= FACEVA ( IL FUNZIONARIO SUPER DELINQUENTE DI CITIBANK MILANO DELLA FINE DI= QUESTO ARTICOLO E' LUI http://ricerca.repubblica.it/repubblica/archivio/re= pubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.ht= ml )! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI DI CENTINAIA DI PERSONE! F= ALSO&LADRO&TRUFFATORE! DIFFAMA SUL WEB A FINI NAZIRAZZISTI! FONDATORE DEI N= UOVI MEG-A-SSASSINI MOVIMENTI TERRORISTI DI ESTREMA DESTRA: "NEO NAR"! FOND= ATORE DEL, PROSSIMAMENTE, DI FREQUENTE, OMICIDA: KU KLUK KLAN PADANO! CONDA= NNATO AL CARCERE A MILANO ED IN BRASILE ( 8 ANNI E PURE PER PEDERASTIA OMOS= ESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE)! MULTATO DA CONSOB BEN 70= .000 =E2=82=AC! DESTABILIZZA L'ITALIA PER FILO NAZISTI SERVIZI SEGRETI SVIZ= ZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTAMENTE, NAZIONE SCHIFATA IN TUTTO= IL MONDO, IN QUANTO FASCIOMAFIOSA DITTATURA DI BERLUSCONIA.. NON PER NIENT= E, TUTTE I MIGLIORI CERVELLI PRIVATI E TUTTE LE PIU' GRANDI INDUSTRIE, IN I= TALIA DA SECOLI, DALLA TIRANNI-A-SSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI= FIAT, PIRELLI, LUXOTTICA, MERLONI E MIGLIAIA E DI ALTRE... E CHE SIA CHIAR= O, PLS, CHE IDDIO BENEDICA I GRANDI PM ED EX PM CHE NON SOPPORTANTO IL CANC= RO DEL MONDO INTERO SILVIO BERLUSCONI, COME HENRY WOODCOCK, ILDA BOCASSINI,= ANTONIO INGROIA E CHIUNQUE ALTRO DI QUESTA AMMIREVOLISSIMA CATEGORIA)! FA = CRIMINI SU CRIMINI E NAZI-ST-ALKING, SU INTERNET, SU ORDINE DEI BASTARDI CR= IMINALI SILVIO BERLUSCONI, PAOLO BERLUSCONI ED UBALDO LIVOLSI DI FININVEST = ( PER NON DIRE SU ORDINE DEL FIGLIO, PADRE E MARITO DI PUTTANE ENNO DORIS D= I MEDIOLANUM). IL BASTARDO, PURE ASSASSINO, PAOLO BARRAI, E' ANCHE, DA SEMP= RE, INNEGGIANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI G= RANDEMENTE FECE CON FALCONE E BORSELLINO"! PAROLE SUE, DETTE SPESSISSIMO! F= U LUI AD ORGANIZZARE L'OMICIDIO DI DAVID ROSSI DI MONTE PASCHI! Avrei tantissimo altro da scrivere sul gia' 3 volte finito in galera, accer= tato pedofilo omosessuale, ladro, truffatore, sempre falso, nazi-st-alker, = mandante di omicidi ( spesso, ma non sempre, mascherati da finti incidenti,= malori o "suicidate"... come quando fece ammazzare David Rossi di Monte Pa= schi), mega ricicla soldi mafiosi e/o politico-criminali (piu' tanto di orr= ido altro), arrestato gia' 3 volte, Paolo Barrai, nato a Milano il 28.6.196= 5 e gia' residente a Milano in Via Ippodromo 105! Come presto meglio sottol= ineeremo, multato pure dalla Consob ben 70.000 euro! http://www.bluerating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un= -ex-promotore-che-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion http://www.maidireborsa.it/showthread.php?27302-Paolo-Barrai-di-Mercato-Lib= ero-sanzionato-dalla-Consob Oure condannato al carcere in Brasile! Otto anni di galera sentenziatissimi= . Per pedofilia omosessuale, furto, truffa, minacce di morte, tentativi di = estorsione uniti a stalking via internet, riciclaggio di soldi mafiosi, pro= paganda razzista, propaganda nazifascista. Ecco i links di inizio indagine.= Ora vi e' la sentenza. E' scappato da Porto Seguro, di notte, in pieno car= nevale 2011, per fuggire a processo e galera ( ed ovviamente, da allora, di= piedi in Brasile non ne ha mai piu' messi: perbacco che coincidenzuzza bed= da). Fate voi di che schifoso topo di fogna parliamo quando parliamo di sto= colerico ratto criminale che da sempre e' Paolo Barrai (o ratto criminalis= simo "Paolo Pietro Barrai" nato a Milano il 28.6.1965..... come si fa chiam= are all'estero, truffaldinamente, e quindi, come da suo solito... per vigli= accamente depistare Google) http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://portoseguroagora.blogspot.be/2011/03/porto-seguro-o-blogueiro-italia= no-sera.html http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.osollo.com.br/online/index.php/crimes/3052-blogueiro-italiano-se= ra-indiciado-por-estelionato-calunia-e-difamacao-pela-policia-civil-de-port= o-seguro http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 VI SONO TONNELLATE DI ALTRE COSE DA DIRE SU QUANTO SIA BASTARDISSIMAMENTE E= FFERATO CRIMINALE E PEDOFILO, PAOLO BARRAI. NE TROVATE IN OGNI CASO, UNA NO= N PICCOLISSIMA PARTE ( CHE PRESTO AMPLIEREMO ALL'INFINITO)... QUI: https://twitter.com/megliomortiche1 https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg From newsfish@newsfish Thu Aug 1 00:44:25 2024 X-Received: by 2002:ac8:6958:: with SMTP id n24mr19094760qtr.360.1560162744770; Mon, 10 Jun 2019 03:32:24 -0700 (PDT) X-Received: by 2002:a0d:e20e:: with SMTP id l14mr3649462ywe.105.1560162744060; Mon, 10 Jun 2019 03:32:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!j96no3008060qte.0!news-out.google.com!33ni90qtt.0!nntp.google.com!j96no3008049qte.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 10 Jun 2019 03:32:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.165.129.226; posting-account=BnbPYgoAAACV95kJ96RhL11rsub4vLtr NNTP-Posting-Host: 83.165.129.226 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8b215466-39b7-46da-9448-58ec6a268cdf@googlegroups.com> Subject: E' DA ARRESTARE SUBITO, L'AVVOCATO ASSASSINO DANIELE MINOTTI DI RAPALLO. NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI! E' AVVOCATO MALVITOSISSIMO, PEDERASTA ED OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E MILANO ( https://www.s From: ORDINA-OMICIDI DANIELE MINOTTI AVVOCATO-SATANAZIST Injection-Date: Mon, 10 Jun 2019 10:32:24 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 965 Xref: reader01.eternal-september.org comp.lang.vhdl:9467 E' DA ARRESTARE SUBITO, L'AVVOCATO ASSASSINO DANIELE MINOTTI DI RAPALLO. NO= TO PEDOFILO INCULA ED AMMAZZA BAMBINI! E' AVVOCATO MALVITOSISSIMO, PEDERAST= A ED OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE= E MILANO ( https://www.studiolegalelisi.it STUDIO LEGALE MASSONICO-CRIMINA= LE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI SACRA CORONA UNITA, MAFIA BARE= SE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E' STALKER ASSASSINO VIA INTERNET= , NONCHE' PEDERASTA CHE STUPRA ED UCCIDE I BAMBINI, QUESTO AVV DELINQUENTIS= SIMO DANIELE MINOTTI! AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, = PERVERTITO, KILLER, DI RAPALLO E GENOVA. https://www.flickr.com/photos/danieleminotti/ RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 OGNI SETTIMANA SGOZZA OLTRE CHE CANI, GATTI E SERPENTI, TANTI BAMBINI, IN R= ITI SATANICI. IN TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEGUONO.. = I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMAZZATI, = FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRIO DALL'= AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI DI RAPALLO E GENO= VA http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI MEGA OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://genova.repubblica.it/cronaca/2011/06/14/news/riti_voodoo_al_cimiter= o_di_staglieno-17668927/ https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO KILLER= , NAZISTA E PEDOFILO, STUPRANTE ED UCCIDENTE BAMBINI SU BAMBINI: DANIELE MI= NOTTI DI RAPALLO E GENOVA! Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI ED OMICIDA ). A CAPO, ANZI, A KAPO' DI UNA SETTA = ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA ASSASSINA CHIAMATA " AMMAZZIAMO PE= R NOSTRO SATANA IN TERRA: SILVIO BERLUSCONI". E' AVVOCATO PEDERASTA INCULA = ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO. UNITO IN CIO' AI PARIMENTI SATANAZISTI, CORROTTI E MEGA COCAINOMANI MARIO G= IORDANO, CALUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSELMA DEL'OLI= O ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). 2 ED ALL'ARRESTATO REGISTA, VOMITEVOLISSIMAMENTE PEDOFILO: GIUSEPPE LAZZARI D= I BRESCIA ( REGISTA PEDERASTISSIMO GIUSEPPE LAZZARI DI BRESCIA https://brescia.corriere.it/notizie/cronaca/16_agosto_11/pedofilia-arrestat= o-regista-bresciano-giuseppe-lazzari-5e4ca24a-5fb2-11e6-bfed-33aa6b5e1635_a= mp.html CHE, COME VEDETE DA QUESTO VIDEO, E' PAPPA E CICCIA CON LA PARI PEDOFILONA = ANSELMA DELL'OLIO https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). STUPRI ED UCCISIONI DI BAM= BINI CHE AVVENGONO ANCHE COL TRE VOLTE FINITO IN GALERA PAOLO BARRAI ( NOTO= , NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFILO DEL BITCOIN= " ). NOTO PEDOFILO ED ASSASSINO PAOLO BARRAI DI CRIMINALISSIMA, DI NDRANGHETISTA= EIDOO https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.rsi.ch/la1/programmi/informazione/falo/tutti-i-servizi/Bella-ge= nte-10474214.html IL TUTTO INSIEME AL PARIMENTI, NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DE = IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO SE SI= E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORRA, N= DRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA: RIC= ORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AFFILI= ATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUO PEZZO DI MERDA NAZISTA FIGLI= O PIERSILVIO BERLUSCONI https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI KILLER DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTAPO,= DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZIFAS= CISTI CRIMINALISSIMI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONE= RO https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html ). 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA VIA BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI VIA BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI VIA BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI VIA BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E VERME ASSASSINO MARCO MANCINI ( QUESTI ULTI= MI, CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE= NON TOPO DI FOGNA BERLUSCONICCHIO COME LORO, VIA "DISARTICOLAZIONI DI TIPO= TRAUMATICO", OSSIA OMICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, M= ALORI, INCIDENTI)! OGNI COSA POTETE RISCONTRARLA PRESSO QUESTI VINCENTISSIMI LINKS http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l http://www.pmli.it/sismicolpivanemiciberlusconi.htm ). MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! AVVOCATO FIGLIO DI PUTTANA ASSASSINO E PEDOFILO DANIELE MINOTTI DI RAPALLO = E GENOVA, CHE NON PER NIENTE, DIFENDE PEDOFILI KILLERS COME LUI, A MAN BASS= A ( FRA TOPI DI FOGNA PERVERTITISSIMI CI SI CAPISCE) http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 TROVATE QUALSIASI ALTRA INFORMAZIONE SUL MASSONE NAZISTA, SUL SATANISTA NAZ= ISTA, SUL SATANAZISTA, PEDOFILO, PEDERASTA, ASSASSINO DANIELE MINOTTI DI RA= PALLO E GENOVA, QUI: www.py.cz/pipermail/python/2017-March/012978.html E QUI https://www.mail-archive.com/docker-dev@googlegroups.com/msg00517.html COME PURE QUI E STRA QUI https://www.mail-archive.com/support-seamonkey@lists.mozilla.org/msg74904.h= tml E' DA ARRESTARE SUBITO, L'AVVOCATO ASSASSINO DANIELE MINOTTI DI RAPALLO. NO= TO PEDOFILO INCULA ED AMMAZZA BAMBINI! E' AVVOCATO MALVITOSISSIMO, PEDERAST= A ED OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE= E MILANO ( https://www.studiolegalelisi.it STUDIO LEGALE MASSONICO-CRIMIN= ALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI SACRA CORONA UNITA, MAFIA BAR= ESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E' STALKER ASSASSINO VIA INTERNE= T, NONCHE' PEDERASTA CHE STUPRA ED UCCIDE I BAMBINI, QUESTO AVV DELINQUENTI= SSIMO DANIELE MINOTTI! AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO,= PERVERTITO, KILLER, DI RAPALLO E GENOVA. https://www.flickr.com/photos/danieleminotti/ RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 OGNI SETTIMANA SGOZZA OLTRE CHE CANI, GATTI E SERPENTI, TANTI BAMBINI, IN R= ITI SATANICI. IN TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEGUONO.. = I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMAZZATI, = FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRIO DALL'= AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI DI RAPALLO E GENO= VA http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI MEGA OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://genova.repubblica.it/cronaca/2011/06/14/news/riti_voodoo_al_cimiter= o_di_staglieno-17668927/ https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO KILLER= , NAZISTA E PEDOFILO, STUPRANTE ED UCCIDENTE BAMBINI SU BAMBINI: DANIELE MI= NOTTI DI RAPALLO E GENOVA! Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI ED OMICIDA ). A CAPO, ANZI, A KAPO' DI UNA SETTA = ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA ASSASSINA CHIAMATA " AMMAZZIAMO PE= R NOSTRO SATANA IN TERRA: SILVIO BERLUSCONI". E' AVVOCATO PEDERASTA INCULA = ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO. UNITO IN CIO' AI PARIMENTI SATANAZISTI, CORROTTI E MEGA COCAINOMANI MARIO G= IORDANO, CALUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSELMA DEL'OLI= O ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTATO REGISTA = PEDOFILO STUPRA RAGAZZINI GIUSEPPE LAZZARI DI BRESCIA https://brescia.corriere.it/notizie/cronaca/16_agosto_11/pedofilia-arrestat= o-regista-bresciano-giuseppe-lazzari-5e4ca24a-5fb2-11e6-bfed-33aa6b5e1635_a= mp.html ( CHE, COME VEDETE DA QUESTO VIDEO, NON PER NIENTE, E' PAPPA E CICCIA CON L= A PARI PEDOFILONA STUPRA BAMBINI: ANSELMA DELL'OLIO STESSA https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). STUPRI ED UCCISIONI DI BAM= BINI CHE AVVENGONO ANCHE COL TRE VOLTE FINITO IN GALERA PAOLO BARRAI ( NOT= O, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFILO DEL BITCOI= N" ). 2 NOTO PEDOFILO ED ASSASSINO PAOLO BARRAI DI CRIMINALISSIMA, DI NDRANGHETISTA= EIDOO https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ IL TUTTO INSIEME AL PARIMENTI, NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DE = IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO SE SI= E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORRA, N= DRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA: RIC= ORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AFFILI= ATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUO PEZZO DI MERDA NAZISTA FIGLI= O PIERSILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI KILLER DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTAPO,= DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZIFAS= CISTI CRIMINALISSIMI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONE= RO https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html ). IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA VIA BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI VIA BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI VIA BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI VIA BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E VERME ASSASSINO MARCO MANCINI ( QUESTI ULTI= MI, CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE= NON TOPO DI FOGNA BERLUSCONICCHIO COME LORO, VIA "DISARTICOLAZIONI DI TIPO= TRAUMATICO", OSSIA OMICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, M= ALORI, INCIDENTI)! 3 IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l http://www.pmli.it/sismicolpivanemiciberlusconi.htm ). MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! AVVOCATO FIGLIO DI PUTTANA ASSASSINO E PEDOFILO DANIELE MINOTTI DI RAPALLO = E GENOVA, CHE NON PER NIENTE, DIFENDE PEDOFILI KILLERS COME LUI, A MAN BASS= A ( FRA TOPI DI FOGNA PERVERTITISSIMI CI SI CAPISCE) http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 TROVATE QUALSIASI ALTRA INFORMAZIONE SUL MASSONE NAZISTA, SUL SATANISTA NAZ= ISTA, SUL SATANAZISTA, PEDOFILO, PEDERASTA, ASSASSINO DANIELE MINOTTI DI RA= PALLO E GENOVA, QUI: www.py.cz/pipermail/python/2017-March/012978.html E QUI https://www.mail-archive.com/docker-dev@googlegroups.com/msg00517.html COME PURE QUI E STRA QUI https://www.mail-archive.com/support-seamonkey@lists.mozilla.org/msg74904.h= tml E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI! CRIMINALISSIMO A= VV DI GENOVA E RAPALLO! E' UN NAZI-ST-ALKER ASSASSINO VIA INTERNET, NONCHE'= PEDERASTA CHE STUPRA ED UCCIDE I BAMBINI: DANIELE MINOTTI! AVVOCATO SATA-N= AZISTA, DEPRAVATO............... PERVERSO, PERVERTITO, SANGUINARIO, COCAINO= MANE, MEGA OMICIDA, DI GENOVA E RAPALLO!!! https://www.flickr.com/photos/danieleminotti/ RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATA= NISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GE= NOVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIS= TA DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI,= AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TI= PO STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 FINO A POCO FA..SGOZZAVA OLTRE CHE CANI, GATTI E SERPENTI, TANTISSIMI BAMBI= NI, IN RITI SATANICI DI TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEG= UONO.. I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMA= ZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRI= O DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO! Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Fax +39 010 91 63 11 54 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER https://www.flickr.com/photos/danieleminotti/ ). A CAPO, ANZI, A KAPO' DI S= ETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA ASSASSINA CHIAMATA " AMMAZZIA= MO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCONI". E' AVVOCATO PEDERASTA IN= CULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO. https://grupy.scigacz.pl/moj,pierwszy,czyli,sprzedam Subject: PUTTANONA SEMPRE SCOPATA IN CULO: COSTANZA RACHELE BARRAI! NOTA TROIA MEGA COCAINOMANE NATA A MILANO IL 1.1.1999. SCHIFOSISSIMA BALDRACCA COSTANZA RACHELE BARRAI: SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA, PRESSO L'INTERNATIONAL SCHOO From: SBORRATISSIMAINCULO COSTANZA BARRAI MEGACOCAINOMAN Injection-Date: Tue, 11 Jun 2019 13:31:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 15322 X-Received-Body-CRC: 1396377602 Xref: reader01.eternal-september.org comp.lang.vhdl:9468 PUTTANONA SEMPRE SCOPATA IN CULO: COSTANZA RACHELE BARRAI! NOTA TROIA MEGA = COCAINOMANE NATA A MILANO IL 1.1.1999. SCHIFOSISSIMA BALDRACCA COSTANZA RAC= HELE BARRAI: SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA, PRE= SSO L'INTERNATIONAL SCHOOL MILANO!! LURIDA MIGNOTTA COSTANZA RACHELE BARRAI= : SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA PRESSO L'UNIVER= SITY OF BATH!! DEPRAVATA BAGASCIA COSTANZA RACHELE BARRAI: SEMPRE A CIUCCIA= RE E PRENDERE CAZZI IN CULO, FIGA E BOCCA PRESSO IL QMI!! PERVERTITA ZOCCOL= A COSTANZA RACHELE BARRAI: SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIG= A E BOCCA PRESSO SONY PICTURES ENTERTAINMENT (https://uk.linkedin.com/in/co= stanza-rachele-barrai-3a5b97a7 ) !!!!!!!!! FACENTE FILM PORNO AMATORIALI A = GO GO! PRENDENTE NELL'ANO CAZZI "ESOTICI" PURE DI 30 CM! D'ALTRONDE..VENNE = SEMPRE INCULATA, DA QUANDO BAMBINA, DA NOTO PADRE PEDOFILO PAOLO BARRAI, NA= TO A MILANO IL 28.6.65! =E3=80=80 A PROPOSITO DEL CRIMINALISSIMO QUALE... E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965. NON= CHE' MEGA RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI MEGA R= UBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA E STRAGISTA SPAPPOLA MAGIS= TRATI, NONCHE', TANTO QUANTO, NAZIFASCISTA DITTATORE E PEDOFILO: SILVIO BER= LUSCONI! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TER= RORISTA NAZISTA ED ASSASSINO, PAOLO BARRAI. NON PER NIENTE, GIA' STATO IN G= ALERA 3 VOLTE. OPINIONI TUTTE TERRIFICANTI SU DI LUI! MEGA TRUFFATORE E MEG= A RICICLA CASH ASSASSINO VIA CRIMINALISSIMA BLOCKCHAIN INVEST O VIA CRIMINA= LISSIMA BLOCKCHAININVEST CHE SIA, OLTRE CHE VIA CRIMINALISSIMA WMO SAGL LUG= ANO, CRIMINALISSIMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA P= ANAMA E CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO! NOTO PEDOFI= L-O-MOSESSUALE SODOMIZZA BAMBINI E RAGAZZINI! CACCIATO DA CITIBANK A SBERLE= , PER MEGA FRODI CHE LI FACEVA! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI = DI CENTINAIA E CENTINAIA DI PERSONE! FALSO&LADRO&TRUFFATORE! DIFFAMA SUL WE= B A FINI NAZIRAZZISTI! FONDATORE DEI NUOVI MEGASSASSINI TERRORISTI DI ESTRE= MISSIMA DESTRA: "NUOVI NAR"! FONDATORE DEL, PROSSIMAMENTE, DI FREQUENTE, OM= ICIDA: KU KLUK KLAN PADANO! CONDANNATO AL CARCERE A MILANO ED IN BRASILE ( = 8 ANNI E PURE PER PEDERASTIA OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSE= SSUALE)! MULTATO DA CONSOB 70.000 =E2=82=AC! DESTABILIZZA L'ITALIA PER FILO= NAZISTI SERVIZI SEGRETI SVIZZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTISSI= MAMENTE, NAZIONE SCHIFATA IN TUTTO IL MONDO, IN QUANTO FASCIOMAFIOSA DITTAT= URA DI BERLUSCONIA.. NON PER NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITA= LIA DA SECOLI, DALLA TIRANNIASSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIA= T, PIRELLI, LUXOTTICA, MERLONI E MIGLIAIA E MIGLIAIA DI ALTRE... E CHE SIA = CHIARO, PLS, CHE IDDIO BENEDICA I GRANDI PM CHE NON SOPPORTANTO IL CANCRO D= EL MONDO INTERO, SILVIO BERLUSCONI, COME HENRY WOODCOCK, ILDA BOCASSINI E C= HIUNQUE ALTRO DI QUESTA AMMIREVOLISSIMA CATEGORIA)! FA CRIMINI SU CRIMINI E= NAZI-ST-ALKING, SU INTERNET, SU ORDINE DEI PUZZONI CRIMINALISSIM SILVIO BE= RLUSCONI, PAOLO BERLUSCONI ED UBALDO LIVOLSI DI FININVEST ( CHE DA ANNI FAN= NO GLI ADOLPH HITLER MISTI AD AL CAPONE, DEL WEB, ANCHE, MA DI CERTO, NON S= OLO, CON QUEL VERME SCHIFOSAMENTE TERRORISTA DI GIULIO OCCHIONERO). INNEGGI= ANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GRANDISSIMAM= ENTE FECE CON FALCONE E BORSELLINO"! PAROLE SUE, DETTE SPESSISSIMO! ORGANIZ= ZANTE OMICIDIO DI DAVID ROSSI DI MONTE PASCHI! Ho tantissimo da scrivere sul gia' 3 volte finito in galera, accertatissimo= pedofilo omosessuale, ladro, truffatore, sempre falso, nazi-st-alker, mand= ante di omicidi ( spesso, ma non sempre, mascherati da finti incidenti, mal= ori o "suicidate"... come quando fece ammazzare David Rossi di Monte Paschi= , ma ne scrivero' in dettagli molto presto), mega ricicla soldi mafiosi e/o= politico-criminali (piu' tanto di orrido altro), arrestato gia' 3 volte, P= aolo Barrai, nato a Milano il 28.6.1965 e gia' residente a Milano in Via Ip= podromo 105! Come presto meglio sottolineeremo, multato dalla Consob ben 70= .000 euro! http://www.bluerating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un= -ex-promotore-che-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion http://www.maidireborsa.it/showthread.php?27302-Paolo-Barrai-di-Mercato-Lib= ero-sanzionato-dalla-Consob VI SONO TONNELLATE DI ALTRE COSE DA DIRE SU QUANTO SIA BASTARDO EFFERATO CR= IMINALE E PEDOFILO PAOLO BARRAI. TROVATE UNA PARTE ( CHE PRESTO AMPLIEREMO = ALL'INFINITO), QUI: https://twitter.com/megliomortiche1 ALWAYS SODOMIZED BY 30 CM LONG DICKS: COSTANZA RACHELE BARRAI, BORN IN MILA= N ON 1.1.1999. ALWAYS GETTING HUGE DICKS IN THE ASS, PUSSY AND MOUTH BY THE= INTERNATIONAL SCHOOL MILAN. STINKY, NASTY BITCH COSTANZA RACHELE BARRAI: A= LWAYS GETTING HUGE DICKS IN THE ASS, PUSSY AND MOUTH BY UNIVERSITY OF BATH.= STINKY, NASTY BITCH COSTANZA RACHELE BARRAI: ALWAYS GETTING HUGE DICKS IN = THE ASS, PUSSY AND MOUTH BY QMI. STINKY, NASTY BITCH COSTANZA RACHELE BARRA= I: ALWAYS GETTING HUGE DICKS IN THE ASS, PUSSY AND MOUTH BY SONY PICTURES = ENTERTAINMENT (https://uk.linkedin.com/in/costanza-rachele-barrai-3a5b97a7)= . E' SEMPRE SCOPATA E SBORRATA IN CULO: COSTANZA RACHELE BARRAI! LA PUTTANO= NA NATA A MILANO IL 1.1.1999. SCHIFOSISSIMA TROIA COSTANZA RACHELE BARRAI: = SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA, PRESSO L'INTERNA= TIONAL SCHOOL MILANO! SCHIFOSISSIMA TROIA COSTANZA RACHELE BARRAI: SEMPRE A= CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA PRESSO L'UNIVERSITY OF BA= TH. SCHIFOSISSIMA TROIA COSTANZA RACHELE BARRAI: SEMPRE A CIUCCIARE E PREND= ERE CAZZI IN CULO, FIGA E BOCCA PRESSO IL QMI. SCHIFOSISSIMA TROIA COSTANZA= RACHELE BARRAI: SEMPRE A CIUCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA = PRESSO SONY PICTURES ENTERTAINMENT (https://uk.linkedin.com/in/costanza-rac= hele-barrai-3a5b97a7) ! FACENTE FILM PORNO A GO GO! PRENDENTE NELL'ANO CAZZ= I "ESOTICI" PURE DI 30 CM! D'ALTRONDE..VENNE SEMPRE INCULATA, DA QUANDO BAM= BINA, DA NOTO PADRE PEDOFILO PAOLO BARRAI! SU CUI TROVATE NON POCHISSIMO, QUI! https://twitter.com/megliomortiche1 https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg SI... E=C2=B4 SBORRATA SEMPRE TUTTA DENTRO AL CULO: COSTANZA BARRAI! NATA A= MILANO IL 1.1.1999, BORN IN MILAN ON 1.1.1999! EX INTERNATIONAL SCHOOL MIL= AN. DICIOTTENNE E FA FILM PORNO A GO GO! https://i1.sndcdn.com/avatars-000123698582-6zu6yw-t500x500.jpg https://uk.linkedin.com/in/costanza-rachele-barrai-3a5b97a7 PRENDENDO PROFONDAMENTE NEL CULO CAZZI "ESOTICI" PURE DI 30-32-35 CM ( E LE= PIACE SEMPRE DI PIU', SEMPRE DI PIU', SEMPRE DI PIU')! D'ALTRONDE..VENNE, = GIA' DALLA NASCITA, SODOMIZZATA DAL BASTARDO CRIMINALISSIMO PADRE. NOTO PED= OFILO PAOLO BARRAI. NATO A MILANO IL 28.6.1965 ( E NOTO PEDERASTA INCULA BA= MBINI ERA PURE SUO NONNO, SCHIFOSISSIMO PEDOFILO VINCENZO BARRAI ABITANTE I= N VIA PADOVA 282 A MILANO E NATO A MILANO IL 3.5.1938... A "KAPO' " DI SCHI= FOSISSIMAMENTE MALAVITOSA BSI ITALIA SRL MILANO, VIA SOCRATE 26 https://= grokbase.com/t/gg/tasker/162ghxnpsb/vermi-criminali-di-bsi-italia-srl-via-s= ocrate-26-milano-di-noti-pedofili-paolo-barrai-e-vincenzo-barrai-oltre-che-= nazi-ladri-truffatori-lava-cash-mafioso-o-frutto-di-stecche-e-furti-di-lega= -ladrona-ex-pdl-popolodiladroni-i-barrai-omicida )! E A PROPOSITO DI STI ULTIMI DUE BASTARDISSIMI MOSTRI.... E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965. NON= CHE' MEGA RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI MEGA R= UBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA E STRAGISTA SPAPPOLA MAGIS= TRATI, NONCHE', TANTO QUANTO, NAZIFASCISTA DITTATORE E PEDOFILO SILVIO BERL= USCONI! DICEVO, E' DAVVERO DA ARRESTARE UNA QUARTA VOLTA, E SUBITO, IL TERR= ORISTA NAZISTA ED ASSASSINO, PAOLO BARRAI ( ASSICURANDOSI CHE QUESTA VOLTA = RIMANGA IN CARCERE PER SEMPRE O PER LO MENO PER DECENNI E DECENNI). NON PER= NIENTE, GIA' STATO IN GALERA 3 VOLTE. OPINIONI TUTTE TERRIFICANTI SU DI LU= I! MEGA TRUFFATORE E MEGA RICICLA CASH LERCIO CHE PIU' LERCIO NON SI POTREB= BE, VIA CRIMINALISSIMA BLOCKCHAIN INVEST, OLTRE CHE VIA CRIMINALISSIMA WORL= D MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA E CRIMINALISSIMA B= SI ITALIA SRL DI VIA SOCRATE 26 MILANO! NOTO PEDOFIL-O-MOSESSUALE SODOMIZZA= BAMBINI PAOLO BARRAI! CACCIATO DA CITIBANK A SBERLE, PER MEGA FRODI CHE LI= FACEVA ( IL FUNZIONARIO SUPER DELINQUENTE DI CITIBANK MILANO DELLA FINE DI= QUESTO ARTICOLO E' LUI http://ricerca.repubblica.it/repubblica/archivio/re= pubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.ht= ml )! SBAGLIA SEMPRE IN BORSA! AZZERA I RISPARMI DI CENTINAIA DI PERSONE! F= ALSO&LADRO&TRUFFATORE! DIFFAMA SUL WEB A FINI NAZIRAZZISTI! FONDATORE DEI N= UOVI MEG-A-SSASSINI MOVIMENTI TERRORISTI DI ESTREMA DESTRA: "NEO NAR"! FOND= ATORE DEL, PROSSIMAMENTE, DI FREQUENTE, OMICIDA: KU KLUK KLAN PADANO! CONDA= NNATO AL CARCERE A MILANO ED IN BRASILE ( 8 ANNI E PURE PER PEDERASTIA OMOS= ESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE)! MULTATO DA CONSOB BEN 70= .000 =E2=82=AC! DESTABILIZZA L'ITALIA PER FILO NAZISTI SERVIZI SEGRETI SVIZ= ZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTAMENTE, NAZIONE SCHIFATA IN TUTTO= IL MONDO, IN QUANTO FASCIOMAFIOSA DITTATURA DI BERLUSCONIA.. NON PER NIENT= E, TUTTE I MIGLIORI CERVELLI PRIVATI E TUTTE LE PIU' GRANDI INDUSTRIE, IN I= TALIA DA SECOLI, DALLA TIRANNI-A-SSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI= FIAT, PIRELLI, LUXOTTICA, MERLONI E MIGLIAIA E DI ALTRE... E CHE SIA CHIAR= O, PLS, CHE IDDIO BENEDICA I GRANDI PM ED EX PM CHE NON SOPPORTANTO IL CANC= RO DEL MONDO INTERO SILVIO BERLUSCONI, COME HENRY WOODCOCK, ILDA BOCASSINI,= ANTONIO INGROIA E CHIUNQUE ALTRO DI QUESTA AMMIREVOLISSIMA CATEGORIA)! FA = CRIMINI SU CRIMINI E NAZI-ST-ALKING, SU INTERNET, SU ORDINE DEI BASTARDI CR= IMINALI SILVIO BERLUSCONI, PAOLO BERLUSCONI ED UBALDO LIVOLSI DI FININVEST = ( PER NON DIRE SU ORDINE DEL FIGLIO, PADRE E MARITO DI PUTTANE ENNO DORIS D= I MEDIOLANUM). IL BASTARDO, PURE ASSASSINO, PAOLO BARRAI, E' ANCHE, DA SEMP= RE, INNEGGIANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI G= RANDEMENTE FECE CON FALCONE E BORSELLINO"! PAROLE SUE, DETTE SPESSISSIMO! F= U LUI AD ORGANIZZARE L'OMICIDIO DI DAVID ROSSI DI MONTE PASCHI! Avrei tantissimo altro da scrivere sul gia' 3 volte finito in galera, accer= tato pedofilo omosessuale, ladro, truffatore, sempre falso, nazi-st-alker, = mandante di omicidi ( spesso, ma non sempre, mascherati da finti incidenti,= malori o "suicidate"... come quando fece ammazzare David Rossi di Monte Pa= schi), mega ricicla soldi mafiosi e/o politico-criminali (piu' tanto di orr= ido altro), arrestato gia' 3 volte, Paolo Barrai, nato a Milano il 28.6.196= 5 e gia' residente a Milano in Via Ippodromo 105! Come presto meglio sottol= ineeremo, multato pure dalla Consob ben 70.000 euro! http://www.bluerating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un= -ex-promotore-che-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion http://www.maidireborsa.it/showthread.php?27302-Paolo-Barrai-di-Mercato-Lib= ero-sanzionato-dalla-Consob Oure condannato al carcere in Brasile! Otto anni di galera sentenziatissimi= . Per pedofilia omosessuale, furto, truffa, minacce di morte, tentativi di = estorsione uniti a stalking via internet, riciclaggio di soldi mafiosi, pro= paganda razzista, propaganda nazifascista. Ecco i links di inizio indagine.= Ora vi e' la sentenza. E' scappato da Porto Seguro, di notte, in pieno car= nevale 2011, per fuggire a processo e galera ( ed ovviamente, da allora, di= piedi in Brasile non ne ha mai piu' messi: perbacco che coincidenzuzza bed= da). Fate voi di che schifoso topo di fogna parliamo quando parliamo di sto= colerico ratto criminale che da sempre e' Paolo Barrai (o ratto criminalis= simo "Paolo Pietro Barrai" nato a Milano il 28.6.1965..... come si fa chiam= are all'estero, truffaldinamente, e quindi, come da suo solito... per vigli= accamente depistare Google) http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://portoseguroagora.blogspot.be/2011/03/porto-seguro-o-blogueiro-italia= no-sera.html http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.osollo.com.br/online/index.php/crimes/3052-blogueiro-italiano-se= ra-indiciado-por-estelionato-calunia-e-difamacao-pela-policia-civil-de-port= o-seguro http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 VI SONO TONNELLATE DI ALTRE COSE DA DIRE SU QUANTO SIA BASTARDISSIMAMENTE E= FFERATO CRIMINALE E PEDOFILO, PAOLO BARRAI. NE TROVATE IN OGNI CASO, UNA NO= N PICCOLISSIMA PARTE ( CHE PRESTO AMPLIEREMO ALL'INFINITO)... QUI: https://twitter.com/megliomortiche1 https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg From newsfish@newsfish Thu Aug 1 00:44:26 2024 X-Received: by 2002:a37:a094:: with SMTP id j142mr65523272qke.2.1560332367529; Wed, 12 Jun 2019 02:39:27 -0700 (PDT) X-Received: by 2002:a0d:e20e:: with SMTP id l14mr10679797ywe.105.1560332367226; Wed, 12 Jun 2019 02:39:27 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Wed, 12 Jun 2019 02:39:26 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=47.62.19.4; posting-account=0JqcqAoAAABxW8ciEXe8j1MIfzWge8xa NNTP-Posting-Host: 47.62.19.4 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: E' TROIONA SEMPRE SBORRATA IN CULO: COSTANZA RACHELE BARRAI, GIA' ABITANTE A MILANO IN VIA IPPODROMO 105! https://i1.sndcdn.com/avatars-000123698582-6zu6yw-t500x500.jpg E' NOTA PUTTANA MEGA COCAINOMANE: COSTANZA RACHELE BARRAI, NATA A MILANO IL 1.1.1 From: "LUIGI BISIGNANI-MAI PIU' COL PEDOFILO BERLUSCONI" Injection-Date: Wed, 12 Jun 2019 09:39:27 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!j96no341600qte.0!news-out.google.com!33ni110qtt.0!nntp.google.com!j96no341595qte.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9469 E' TROIONA SEMPRE SBORRATA IN CULO: COSTANZA RACHELE BARRAI, GIA' ABITANTE = A MILANO IN VIA IPPODROMO 105! https://i1.sndcdn.com/avatars-000123698582-6zu6yw-t500x500.jpg E' NOTA PUTTANA MEGA COCAINOMANE: COSTANZA RACHELE BARRAI, NATA A MILANO IL= 1.1.1999! E' SCHIFOSISSIMA BALDRACCA: COSTANZA RACHELE BARRAI, SEMPRE A CI= UCCIARE E PRENDERE CAZZI IN CULO, FIGA E BOCCA, PRESSO L'INTERNATIONAL SCHO= OL MILANO!! https://mpak-suse1.akamaized.net/res/usericon/507/icon-21714507-322.jpg E' LURIDA MIGNOTTONA: COSTANZA RACHELE BARRAI, SEMPRE A FARE SESSO DEPRAVAT= O, ANCHE MOLTO LESBICO, PRESSO L'UNIVERSITY OF BATH!! https://dok7xy59qfw9h.cloudfront.net/194/934/091/-469996989-1scbatj-gp4df4l= qqhaij0p/original/file.jpg E' DEPRAVATA BAGASCIA SEMPRE SCOPATA E SBORRATA IN CULO: COSTANZA RACHELE B= ARRAI (SONY PICTURES ENTERTAINMENT). E' SEMPRE LI A PRENDERE CAZZI DI OGNI = COLORE ( SPECIE NERO, MA NON SOLO), LUNGHI MEZZO METRO, PER POI FARSI RIEMP= IRE L'ANO DI TANTISSIMA SBORRA, COSTANZA RACHELE BARRAI (https://uk.linkedi= n.com/in/costanza-rachele-barrai-3a5b97a7 ) !!!!!!!!! E' NINFOMANE ZOCCOLIS= SIMA: COSTANZA RACHELE BARRAI, DA ANNI FACENTE FILM PORNO AMATORIALI A GO G= O ( QUI IN UNA FOTO RIPRENDENTELA PROPRIO A SEGUITO DI UNA MEGA INCULATA AV= VENUTA AL ZOCCOLONE COSTANZA RACHELE BARRAI STESSO, SODOMIZZASIONI, D'ALTRO= NDE, DA SEMPRE, DA LEI, ADORATISSIME http://www.hotanalxxx.com/contents/vid= eos_screenshots/0/43/400x300/1.jpg) ! BEH, BISOGNA ANCHE DIRE CHE L'ATTUALE PUTTANONE COSTANZA RACHELE BARRAI, NA= TA A MILANO IL 1.1.1999 E GIA' ABITANTE IN VIA IPPODROMO 105 A MILANO, VENN= E INCULTATA, GIA' DA QUANDO AVENTE 6 ANNI, DAL PADRE, NOTO PEDOFILO, NOTO C= RIMINALE, FINANCO ASSASSINO: PAOLO BARRAI!!!!!!! FACCIAMO UN BIS IN DUE OTHER WAY, NOW, PLEASE E' TROIONA SEMPRE SCOPATA E SBORRATA IN CULO: COSTANZA BARRAI, GIA' ABITANT= E A MILANO IN VIA IPPODROMO 105! https://i1.sndcdn.com/avatars-000123698582-6zu6yw-t500x500.jpg E' NOTA PUTTANA MEGA COCAINOMANE: COSTANZA BARRAI, NATA A MILANO IL 1.1.199= 9! E' SCHIFOSISSIMA BALDRACCA: COSTANZA BARRAI, SEMPRE A CIUCCIARE E PRENDE= RE CAZZI IN CULO, FIGA E BOCCA, PRESSO L'INTERNATIONAL SCHOOL MILANO!! https://mpak-suse1.akamaized.net/res/usericon/507/icon-21714507-322.jpg E' LURIDA MIGNOTTONA: COSTANZA BARRAI, SEMPRE A FARE SESSO DEPRAVATO, ANCHE= MOLTO LESBICO, PRESSO L'UNIVERSITY OF BATH!! https://dok7xy59qfw9h.cloudfront.net/194/934/091/-469996989-1scbatj-gp4df4l= qqhaij0p/original/file.jpg E' DEPRAVATA BAGASCIA SEMPRE SCOPATA E SBORRATA IN CULO: COSTANZA BARRAI (S= ONY PICTURES ENTERTAINMENT). E' SEMPRE LI A PRENDERE CAZZI DI OGNI COLORE (= SPECIE NERO, MA NON SOLO), LUNGHI MEZZO METRO, PER POI FARSI RIEMPIRE L'AN= O DI TANTISSIMA SBORRA, COSTANZA RACHELE BARRAI (https://uk.linkedin.com/in= /costanza-rachele-barrai-3a5b97a7 ) !!!!!!!!! E' NINFOMANE ZOCCOLISSIMA: CO= STANZA BARRAI, DA ANNI FACENTE FILM PORNO AMATORIALI A GO GO ( QUI IN UNA F= OTO RIPRENDENTELA PROPRIO A SEGUITO DI UNA MEGA INCULATA AVVENUTA AL ZOCCOL= ONE COSTANZA BARRAI STESSO, SODOMIZZASIONI, D'ALTRONDE, DA SEMPRE, DA LEI, = ADORATISSIME http://www.hotanalxxx.com/contents/videos_screenshots/0/43/400= x300/1.jpg) ! BEH, BISOGNA ANCHE DIRE CHE L'ATTUALE PUTTANONE COSTANZA BARRAI, NATA A MIL= ANO IL 1.1.1999 E GIA' ABITANTE IN VIA IPPODROMO 105 A MILANO, VENNE INCULT= ATA, GIA' DA QUANDO AVENTE 6 ANNI, DAL PADRE, NOTO PEDOFILO, NOTO CRIMINALE= , FINANCO ASSASSINO: PAOLO BARRAI!!!!!!! BEH, BISOGNA ANCHE DIRE CHE L'ATTUALE PUTTANONE COSTANZA BARRAI, NATA A MIL= ANO IL 1.1.1999 E GIA' ABITANTE IN VIA IPPODROMO 105 A MILANO, VENNE INCULT= ATA, GIA' DA QUANDO AVENTE 6 ANNI, DAL PADRE, NOTO PEDOFILO, NOTO CRIMINALE= , FINANCO ASSASSINO: PAOLO BARRAI!!!!!!! A PROPOSITO DEL DELINQUENTISSIMO QUALE... E' PEDOFILO ED ASSASSINO: PAOLO BARRAI, NATO A MILANO IL 28.6.1965. E' STAT= O IL CRIMINALISSIMO REGISTA DELL'OPERAZIONE "NDRANGHETA IN EIDOO"!! IL GIA'= 3 VOLTE FINITO IN GALERA PAOLO BARRAI, SPACCIAVA COCAINA, A MILANO, PER IL= NDRANGHETISTA OMICIDA GIULIO MARTINO, PER IL NDRANGHETISTA OMICIDA VINCENZ= O MARTINO E PER IL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PER IL FACC= ENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVITOSA IN = CONTATTO COL PORCO DELINQUENTISSIMO OLIVER CAMPONOVO DI CHIASSO! E' PEDOFILO ASSASSINO PAOLO BARRAI ( CRIMINALISSIMA BIGBIT E CRIMINALISSIMA= CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/images/fotos/fotos_noticias/testao.jpg https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://in.memory.of.e.tern.al/comp.lang.tcl/thread/4226231 - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lug= ano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dello = Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di B= anca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele Za= nzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 NEVER AND NEVER FORGET, PLEASE: IS ALWAYS SODOMIZED BY DICKS LONG 30-35 CM, CRIMINAL BITCH COSTANZA BARRAI,= BORN IN MILAN ON 1.1.1999. DELINQUENT MEGA COCAINE TAKER, EX INTERNATIONAL= SCHOOL MILAN, NOW UNIVERSITY OF BATH, NASTY, DRUGGED SICK PROSTITUTE COSTA= NZA BARRAI, BORN IN MILAN ON 1.1.1999, MAKING LOT OF PERVERT PORN MOVIES IN= COOPERATION WITH SONY PICTURES ENTERTAINMENT. https://uk.linkedin.com/in/costanza-rachele-barrai-3a5b97a7 BIS, GIMME BIS, PLEASE, GIMME BIS, BIS, BIS, BIS. OK BABIES, HERE IS YOUR F= ANTASTIC BIS!!! IS ALWAYS SODOMIZED BY DICKS LONG 30-35 CM, CRIMINAL BITCH COSTANZA RACHELE= BARRAI, BORN IN MILAN ON 1.1.1999. DELINQUENT MEGA COCAINE TAKER, EX INTER= NATIONAL SCHOOL MILAN, NOW UNIVERSITY OF BATH, NASTY, DRUGGED SICK PROSTITU= TE COSTANZA RACHELE BARRAI, BORN IN MILAN ON 1.1.1999, MAKING LOT OF PERVER= T PORN MOVIES IN COOPERATION WITH SONY PICTURES ENTERTAINMENT. https://uk.linkedin.com/in/costanza-rachele-barrai-3a5b97a7 DAUGHTER OF BASTARD HITLERIAN FELONIOUS PAOLO BARRAI, BORN IN MILAN ON 28.6= .65I! ALREADY GONE TO 3 TIMES TO JAIL! THAT'S WHAT HE IS, THIS MONSTER ASSASSIN CALLED PAOLO BARRAI BORN IN MILAN = ON 28.6.1965 ( OR THAT'S WHAT HE IS, THIS MONSTER ASSASSIN CALLED PAOLO PIE= TRO BARRAI BORN IN MILAN ON 28.6.1965 )! HOMOSEXUAL OF PEDOPHILE KIND: PAOLO BARRAI (BITCOIN: THAT HE USES X MAFIA M= ONEY LAUNDERING + POLITICAL NAZIFASCIST VERY ILLEGAL MONEY LAUNDERING)! PUP= PETEER OF EXTREMELY CRIMINAL MAFIA MONEY LAUNDERING TRANSACTION NAMED EIDOO https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://coinidol.com/mafias-use-bitcoin/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://twitter.com/megliomortiche1 https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html STINKY NAZIST ASSASSIN PAOLO BARRAI, BEEN 3 TIMES IN JAIL AND NOT BEEN ON W= IKIPEDIA ( FROM BLOG "MERDATO" LIBERO ALIAS "STALKING SHIT SPREADED.... I= N A VERY HOODLUM WAY WITH NAZIST JOSEPH GOEBBELS'S STYLE")! VERY EXTREME C= RIMINAL PAOLO BARRAI IS A BASTARD ASSASSIN! VERY EXTREME CRIMINAL PAOLO BAR= RAI IS A PRINCIPAL OF MANY MURDERS! VERY EXTREME CRIMINAL PAOLO BARRAI HAS = ALREADY GONE 3 TIMES TO PRISONS IN 3 DIFFERENT NATIONS OF THE WORLD ( ONE I= S BRAZIL)! VERY EXTREME CRIMINAL PAOLO BARRAI; FIRED BADLY BY CITIBANK MILA= N! VERY EXTREME CRIMINAL PAOLO BARRAI HAS ALSO BEEN VERY HEAVILY FINED BY C= ONSOB! VERY EXTREME CRIMINAL PAOLO BARRAI HAS ALSO ESCAPED FROM BRASIL AT N= IGHT, GETTING A FIRST AVAILABLE FLIGHT, IN THE MIDDLE OF CARNAVAL DAYS, TO = NOT RISK TO REMAIN IN JAIL FOR YEARS: FOR EXTREMELY SERIOUS CRIMES LIKE HAV= ING RAPED AN 8 YEARS OLD CHILD, AS WELL AS FOR ENORMOUS FRAUDS, MAFIA MONEY= LAUNDERING, NAZIST AND RACIST PROPAGANDA, EXECUTION OF KILLING THREATS, BL= ACKMAILS AND EXTORSIONS.... AND, LITTLE SWEET CHERRY ON CAKE: PEDERAST SEX = HE HAD WITH AND 8 YEARS OLD CHILD. BASTARD ASSASSIN WORM PAOLO BARRAI IS ALSO A MEGA SCAMMER, BURNING ALL SAVI= NGS OF EVERYONE FALLING IN HIS -CYBER-MEDIATIC-FINANCIAL TRAPS! AL CAPONE O= F FINANCE: PAOLO BARRAI BORN IN MILAN ON 28.6.1965 ( LAUNDERING CASH FROM C= OSA NOSTRA, CAMORRA, NDRANGHETA, AS WELL AS CRIMINAL CASH FROM NAZIRACIST M= OVEMENTS LEGA NORD AND FORZA ITALIA, IN EXTREMELY CRIMINAL EIDOO SWITZERLAN= D AND EXTREMELY CRIMINAL CRYPTOPOLIS SWITZERLAND)!!! AND.. AGAIN.. AND..AGAIN..AND..AGAIN... IS ONE OF MOST BASTARD CRIMINAL CONNECTED TO PANAMA PAPERS, STINKY WORM PAO= LO BARRAI, ALREADY THREE TIMES IN JAIL, BORN IN MILAN ON 28.6.1965 CAREFUL TO THIS LOUSY VERY NASTY, SAVAGE DELINQUENT: PAOLO BARRAI EX CITIBA= NK MILAN, BORN IN MILAN ON 28.06.1965, CONDEMEND TO JAIL ALREADY MANY TIMES= ! ONE OF DIRTIEST MAFIA AND CRIMINAL COLLARS MONEY LAUNDERER IN PANAMA ( AND = NOT ONLY IN PANAMA)... EXTREMELY DELINQUENT INDIVIDUAL, ALREADY THREE TIMES= IN PRISON ( EITHER IN ITALY AND ESPECIALLY IN BRAZIL), STINKY FELONIOUS PA= OLO BARRAI (OR STINKY FELONIOUS PAOLO "PIETRO" BARRAI), BORN IN MILAN ON 28= .06.1965. FROM VERY VERY CRIMINAL WMO SA PANAMA, VERY VERY CRIMINAL WORLD MAN OPPORTU= INITES VIA MAZZINI 14 LUGANO, VERY VERY CRIMINAL BSI ITALIA SRL VIA SOCRATE= 26 MILAN, VERY VERY CRIMINAL BLOG MERCATO LIBERO ( NOT FOR NOTHING, EVERYO= NE IN ITALY AND INITALIAN SPEAKING PART OF SWITZERLAND, KNOWING HOW MANY CR= IMES AND WHAT HORRIBLE KIND OF CRIMES, PAOLO BARRAI, ALWAYS DOES, CALLS THI= S BLOG: "MERDATO" LIBERO). FINED VERY HEAVILY BY CONSOB FOR MEGA FRAUDS HE DID ON PV BUSINESS AND NOT = ONLY http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html https://www.adviseonly.com/blog/investire/mercati-finanziari/il-trading-dei= -miracoli/ http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion FIRED BADLY BY CITIBANK MILAN FOR MEGA ROBERRIES, COLLECTION OF BRIBES AND = FRAUDS "IT" USED TO ORGAINZE THERE. MADE CONDEMNED TO JAIL BY CITIBANK MILA= N. CONDEMNED TO JAIL, THEN, EVEN IN BRAZIL. FOR OTHER FRAUDS, FOR MAFIA MON= EY LAUNDERING, FOR ATTEMPTED EXTORTION, FOR DEATH THREATS DONE, FOR BLACKMA= ILS DONE, FOR INTERNET STALKING DONE AND ALSO ATTEMPTS OF HAVING PEDOPHILE = SEX WITH VIEW UNDERAGE LOCAL BOYS ( INFACT, SINCE ALL THIS GOT SENTENCED, E= XTREMELY CRIMINAL PAOLO BARRAI HAS NEVER PUT A FEET IN BRAZIL ANYMORE... HE= RE FOLLOWS A LINK CORRESPONDING TO THE BEGINNING OF ANY INVESTIGATION http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato ) "IT" TOTALLY BURNED, TOTALLY NULLIFY 100% OF THE SAVINGS SOME CANDID PEOPLE= HE SCRUBBED VIA INTERNET, GAVE HIM TO INVEST ( EVEN BECAUSE IN HAVING "NOS= E FOR BUSINESS", IN HAVING "BUSINESS INTUITION", PAOLO BARRAI IS AN ABSOLUT= E DONKEY: HIS PREVISIONS IN WORLDWIDE STOCKS, COMODITIES, CURRENCIES, REAL = ESTATES, ARE ALWAYS WRONG, WRONG, INCREDIBLY WRONG... ALWAYS.... WITH ZERO = EXCEPTIONS...EVERY ONE IN FINANCIAL BUSINESS CALLS HIM "REVERSAL INDICATOR"= ). "IT" HAS BEEN WASHING IN PANAMA ( IN CONNECTION WITH MOSSACK FONSECA AND= NOT ONLY), SWITZERLAND ( BY FINTER BANK ZURICH LUGANO AND BANCA STATO LUGA= NO), GERMANY, SPAIN, ESTONIA AND DUBAI, LOT AND LOT OF -ASSASSIN ITALIAN COSA NOSTRA, NDRANGHETA, CAMORRA'S CASH -ASSASSIN COLOMBIAN MAFIA CASH -ASSASSIN MEXICAN MAFIA CASH -NAZIRACIST LEGA NORD'S CASH ( COMING FROM MEGA CORRUPTION, MEGA ROBBERIES,= DIRTY BUSINESSES OF THESE KUKLUKKLANIST MIXED TO NDRANGHETIST FROM LEGA NO= RD, IN CONNECTION WITH DICTATORS LIKE PUTIN, GHEDDAFI AND LE PEN'S FAMILY) HE CALLED MANY TIMES OBAMA BARACK A BLACK BASTARD http://ilpunto-borsainvestimenti.blogspot.com/2013/01/ecco-limpatto-fiscale= -che-ha-fatto.html AN HISTERICAL FAIRY http://ilpunto-borsainvestimenti.blogspot.com/2014/03/mercato-libero-e-per-= la-grande-madre.html ( "IT" CALLS OTHER PEOPLE "FAIRY" BUT THEN ALWAYS LOOKS FOR 8, 10, 12, 14 Y= EARS OLD GYPSY MALE PROSTITUTES TO MAKE PAEDERAST SEX WITH) - FASCIST MAFIOSO DICTATOR, PRINCIPAL OF MANY MURDERS AND SLAUGHTERS, AS MU= CH AS ASCERTAINED PEDOPHILE SILVIO BERLUSCONI'S CASH http://www.mercatolibero.info/panama-mercato-libero/ INFACT, SILVIO BERLUSCONI, LEGA NORD, COSA NOSTRA, CAMORRA, NDRANGHETA, COL= OMBIAN MAFIA, MEXICAN MAFIA, ARE, SINCE ALWAYS, SAME KILLING CHOLERIC SEWER= ! PS BE STRONG NOW PLS. AS JUST MENTIONED BEFORE, BUT BETTER EXPLAINED NOW, EXTR= EMELY CRIMINAL PAOLO BARRAI BORN IN MILAN ON 28.6.1965, HAS THE CARD OF WOR= LDWIDE ASSOCIATION OF PEDOPHILES: " PEDOPHILE PRIDE". "IT" SAID MANY TIMES, IN PRIVATE, "IT" HAS BECOME, SINCE VIEW YEARS, AN HOM= OSEXUAL PEDOPHILE. A PAEDERAST. AND "IT" IS PROUD TO MAKE SEX WITH BOYS JUS= T A LITTLE BIT MORE THAN CHILDREN, BEING KIDS 8, 10, 12, 14 YEARS OLD. "IT"= SAID THIS HAPPENS EVERY TIME "IT" GOES TO PANAMA, LATIN AMERICA IN GENERAL= AND THAILAND ( AND OUT OF PANAMA PAPERS ARE COMING OUT VARIOUS CASES OF PE= DOPHILES AND MAFIOSI HAVING EXTREMELY DIRTY CASH THERE: NR ONE BETWEEN THES= E BASTARD NASTY CRIMINALS IS PAOLO BARRAI, BORN IN MILAN ON 28.6.1965.... N= R ONE BETWEEN THESE BASTARD NASTY CRIMINALS IS PAOLO PIETRO BARRAI, BORN IN= MILAN ON 28.6.1965 ). From newsfish@newsfish Thu Aug 1 00:44:26 2024 X-Received: by 2002:a05:620a:125b:: with SMTP id a27mr37170453qkl.112.1560345005731; Wed, 12 Jun 2019 06:10:05 -0700 (PDT) X-Received: by 2002:a25:2042:: with SMTP id g63mr39644005ybg.113.1560345005281; Wed, 12 Jun 2019 06:10:05 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Wed, 12 Jun 2019 06:10:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=178.57.174.45; posting-account=FiJOqwoAAABTa9aMB9-1UUgsWPfCZi5j NNTP-Posting-Host: 178.57.174.45 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: E' PEDOFILO ED ASSASSINO: PAOLO BARRAI (BLOG MERCATO LIBERO ALIAS MER-D-ATO LIBERO)! MA CHI' E' DAVVERO QUESTO PEDERASTA OMICIDA, NATO A MILANO IL 28.6.65, CHIAMANTESI PAOLO BARRAI? PER INIZIARE: E' STATO IL REGISTA DELLA CRIMINALISSIMA OPERAZIONE... From: RICICLASOLDIMAFIOSI PAOLO BARRAI ORDINATANTIOMICID Injection-Date: Wed, 12 Jun 2019 13:10:05 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!j96no435679qte.0!news-out.google.com!33ni110qtt.0!nntp.google.com!j96no435670qte.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9470 E' PEDOFILO ED ASSASSINO: PAOLO BARRAI (BLOG MERCATO LIBERO ALIAS MER-D-ATO= LIBERO)! MA CHI' E' DAVVERO QUESTO PEDERASTA OMICIDA, NATO A MILANO IL 28.= 6.65, CHIAMANTESI PAOLO BARRAI? PER INIZIARE: E' STATO IL REGISTA DELLA CRI= MINALISSIMA OPERAZIONE............."NDRANGHETA IN EIDOO"! https://groups.google.com/a/chromium.org/forum/#!topic/mojo-reviews/vzgxTcO= 0JgA IL GIA' 3 VOLTE FINITO IN GALERA...... PAOLO BARRAI, SPACCIAVA COCAINA, A M= ILANO, PER IL NDRANGHETISTA OMICIDA GIULIO MARTINO, PER IL NDRANGHETISTA OM= ICIDA VINCENZO MARTINO E PER IL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COM= E PER IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG M= ALAVITOSA IN CONTATTO COL PORCO DELINQUENTISSIMO OLIVER CAMPONOVO DI CHIASS= O! E' PEDOFILO ASSASSINO PAOLO BARRAI ( CRIMINALISSIMA BIGBIT E CRIMINALISSIMA= CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://in.memory.of.e.tern.al/comp.lang.tcl/thread/4226231 - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:26 2024 X-Received: by 2002:a0c:adef:: with SMTP id x44mr8127485qvc.153.1560517172317; Fri, 14 Jun 2019 05:59:32 -0700 (PDT) X-Received: by 2002:a81:67c2:: with SMTP id b185mr39467151ywc.504.1560517171932; Fri, 14 Jun 2019 05:59:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!j96no925086qte.0!news-out.google.com!33ni107qtt.0!nntp.google.com!j96no925080qte.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Jun 2019 05:59:31 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.37.126.142; posting-account=ZoBkmgoAAADd2njBbWf4kq3j42Go0CxZ NNTP-Posting-Host: 62.37.126.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <369a5754-117d-44a9-810b-4b776bbfe874@googlegroups.com> Subject: IL VERME CRIMINALE PAOLO BARRAI (LINKEDIN) E' STATO IL REGISTA MALAVITOSO DELL'OPERAZIONE "EIDOO MEANS MAFIA, EIDOO MEANS NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE EFFERATO PAOLO BARRAI ABITAVA A MILANO, IN VIA IPPODROMO 105 (ZONA From: INCULAIBAMBINI PAOLO BARRAI ILPEDOFILODELBITCOIN Injection-Date: Fri, 14 Jun 2019 12:59:32 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9471 IL VERME CRIMINALE PAOLO BARRAI (LINKEDIN) E' STATO IL REGISTA MALAVITOSO D= ELL'OPERAZIONE "EIDOO MEANS MAFIA, EIDOO MEANS NDRANGHETA"! IL GIA' 3 VOLTE= FINITO IN GALERA, IL DELINQUENTE EFFERATO PAOLO BARRAI ABITAVA A MILANO, I= N VIA IPPODROMO 105 (ZONA SAN SIRO- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA= , I RAS NDRANGHETISTI ERANO I MEGA ASSASSINI GIULIANO MARTINO, VINCENZO MAR= TINO E DOMENICO MARTINO.=20 https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CIONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTI= NO, COL NDRANGHETISTA OMICIDA VINCENZO MARTINO E COL NDRANGHETISTA OMICIDA = DOMENICO MARTINO. COME PURE PER IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO.= POSE POI TUTTA STA GANG MALAVITOSA IN CONTATTO COL PORCO CRIMINALISSIMO OL= IVER CAMPONOVO DI CHIASSO! COME DA QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. E' UN PEDOFILO ASSASSINO, SPACCIATORE DI COCAINA E MEGA RICICLA SOLDI MAFIO= SI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CRYPTOLAB E CRIMIN= ALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://in.memory.of.e.tern.al/comp.lang.tcl/thread/4226231 - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:27 2024 X-Received: by 2002:a37:4d14:: with SMTP id a20mr76044898qkb.87.1560698079087; Sun, 16 Jun 2019 08:14:39 -0700 (PDT) X-Received: by 2002:a0d:f5c4:: with SMTP id e187mr44975915ywf.88.1560698078733; Sun, 16 Jun 2019 08:14:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!j96no3168391qte.0!news-out.google.com!33ni376qtt.0!nntp.google.com!j96no3168387qte.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Jun 2019 08:14:38 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=77.224.123.51; posting-account=dxdUwwoAAAC9GWVUgihc3u5gmh-STT4K NNTP-Posting-Host: 77.224.123.51 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <57bad8a3-ae4b-4320-92bd-ffcdf6e93cea@googlegroups.com> Subject: E' DA ARRESTARE SUBITO: PAOLO BARRAI (LINKEDIN)! E' STATO IL REGISTA CRIMINALISSIMO DELL'OPERAZIONE "EIDOO RICICLA SOLDI MAFIOSI PER LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE EFFERATO PAOLO BARRAI, ABITAVA A MILANO, IN VIA..... From: TIAZZERAIRISPARMI PAOLO BARRAI TRUFFAVIABITCOIN Injection-Date: Sun, 16 Jun 2019 15:14:39 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9472 E' DA ARRESTARE SUBITO: PAOLO BARRAI (LINKEDIN)! E' STATO IL REGISTA CRIMIN= ALISSIMO DELL'OPERAZIONE "EIDOO RICICLA SOLDI MAFIOSI PER LA NDRANGHETA"! I= L GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE EFFERATO PAOLO BARRAI, ABIT= AVA A MILANO, IN VIA.......... IPPODROMO 105 (ZONA SAN SIRO- CERTOSA). ED I= N ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEGA ASSASSINI GIULI= ANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://in.memory.of.e.tern.al/comp.lang.tcl/thread/4226231 - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:27 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Code Review: SPI Transmitter Date: Mon, 17 Jun 2019 09:58:38 -0700 Organization: A noiseless patient Spider Lines: 225 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 17 Jun 2019 16:58:38 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="79ba4e6d51103242ab0b73a506142849"; logging-data="29837"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19scqDphKibaFJq+c5Yl0wl" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 Cancel-Lock: sha1:5zDnrSOYYfjhQMdwMEaFVSkpZP4= Content-Language: en-US X-Mozilla-News-Host: snews://news.eternal-september.org/ Xref: reader01.eternal-september.org comp.lang.vhdl:9473 So things have been to my mind unfortunately quiet over here for a while now, so I figured I'd try do get something new going, just in case any of us have gotten bored with the 118th iteration of telling some wet-nosed pup to use numeric_std instead of std_logic_arith and explaining what a process is. Let's actually talk about VHDL code and the improving thereof. So the rules of the game are simple. Someone posts their code, and we talk about it. Code should be at the bare minimum syntactically valid, and preferably working. But how could it have been cleaner, or more elegant? Does it scan when you read it? What obvious low-hanging fruit of functionality was missed? Basically, if this was code that you were going to bring in to your project, what would you have liked to be different about it? Today I've got code for an SPI transmitter. The goal was to create thing that can be kicked off by a register write and update either a serial DAC or relay-driving shift register. It requires no configuration from the software side, and if the software stops writing to the register it will always ultimately set the connected thing to the last written value. ------------------------------------------------------------------------------- -- Title : SPI Transmitter -- Project : T904 TEM Testset ------------------------------------------------------------------------------- -- File : spi_transmitter.vhd -- Author : Rob Gaddi -- Company : Highland Technology, Inc. -- Created : 04-Jun-2019 -- Last update: 04-Jun-2019 -- Platform : Xilinx Zynq 7020 (uZed) -- Standard : VHDL-2002 ------------------------------------------------------------------------------- -- Description: Sends framed words out over SPI on request. -- -- A pulse on go sets a request flag asking the engine to run. The engine -- runs at the next available time, which is the time at which it has been -- idle for at least the MIN_IDLE time. At "run" time it will latch whatever -- the current data on din is and begin the SPI transaction. -- -- This means that, if the engine is and has been idle, the go pulse will -- cause the data on din to start immediately. If the engine is -- currently running, an update to din and pulse on go will cause the engine -- to finish the transaction it is currently running, then take the new din. -- But a second update while the engine is running will cause the first to -- simply be ignored; the idea being that devices being communicated with by -- this engine have only a current state rather than a history or multiple -- current states, and that the point of the engine is to make the current -- state correct. -- -- idle_out represents the state of the transmitter. done goes high for a -- single clock on the completion of the transmit. -- -- SPI Information: Clock idle state is low. Data is transitioned on the -- falling edge of SCLK, under the assumption that it is sampled on the rising -- edge. Data transmits MSB first. ------------------------------------------------------------------------------- -- Revision History: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.standard_functions.all; entity spi_transmitter is generic ( BUS_FREQ_MHZ : integer; SCLK_PERIOD : time; MIN_IDLE : time := 0 ns; CS_EXTRA : time := 0 ns; BITS : positive ); port ( -- Logic side din : in std_logic_vector(BITS-1 downto 0); go : in boolean; idle_out : out boolean; done : out boolean; -- Serial side MOSI : out std_logic; SCLK : out std_logic; CS_N : out std_logic; clk : in std_logic; rst : in std_logic ); end entity spi_transmitter; architecture Behavioral of spi_transmitter is type t_state is ( IDLE, DROP_CS, SCLK_LOW, SCLK_HIGH, HOLD_CS ); constant tClk : time := 1 us / BUS_FREQ_MHZ; -- Number of clocks to spend in each of the states. For IDLE this is -- a minimum, for everyone else it's a fixed time. function time_to_clocks(x: time) return natural is begin return time_to_clocks(x, tClk); end function time_to_clocks; constant IDLE_LEN : natural := time_to_clocks(MIN_IDLE); constant CSD_LEN : natural := time_to_clocks(CS_EXTRA); constant SCLK_LEN : natural := time_to_clocks(SCLK_PERIOD); constant SCLKH_LEN : natural := SCLK_LEN / 2; constant SCLKL_LEN : natural := SCLK_LEN - SCLKH_LEN; constant CSH_LEN : natural := time_to_clocks(CS_EXTRA + SCLK_PERIOD/2); -- Sharing a single timer for all these values requires that it be large -- enough to hold the maximum value. function MAXTIMER return natural is variable x : natural; begin x := IDLE_LEN; if x < SCLKH_LEN then x := SCLKH_LEN; end if; if x < CSH_LEN then x := CSH_LEN; end if; return x; end function MAXTIMER; subtype t_timer is integer range 0 to MAXTIMER-1; begin MACHINE: process(clk) variable go_pending: boolean; variable sr: std_logic_vector(din'range); variable timer: t_timer; variable bits_left : integer range din'range; variable state: t_state; -- Procedure for handling simple wait states. procedure waitandthen(clocks : in positive; nextstate : in t_state) is constant LIMIT : natural := clocks-1; begin if timer = LIMIT then timer := 0; state := nextstate; else timer := timer + 1; end if; end procedure waitandthen; begin if rising_edge(clk) then -- Manage the state machine. done <= false; case state is when IDLE => if timer = (IDLE_LEN-1) then if go_pending then go_pending := false; sr := din; bits_left := BITS-1; timer := 0; -- We don't even have a DROP_CS state if we don't -- request any extra CS time. if CSD_LEN = 0 then state := SCLK_LOW; else state := DROP_CS; end if; end if; else timer := timer + 1; end if; when DROP_CS => waitandthen(CSD_LEN, SCLK_LOW); when SCLK_LOW => waitandthen(SCLKL_LEN, SCLK_HIGH); when SCLK_HIGH => if timer = (SCLKH_LEN-1) then timer := 0; sr := sr(sr'high-1 downto 0) & 'X'; if bits_left = 0 then state := HOLD_CS; else bits_left := bits_left - 1; state := SCLK_LOW; end if; else timer := timer + 1; end if; when HOLD_CS => waitandthen(CSH_LEN, IDLE); done <= (state = IDLE); end case; -- A new data request always sets the go_pending flag, but a reset -- overrides everything. if go then go_pending := true; end if; if (rst = '1') then state := IDLE; timer := 0; sr := (others => 'X'); go_pending := false; end if; -- Drive the outputs based on the state. SCLK <= POS_LOGIC(state = SCLK_HIGH); CS_N <= NEG_LOGIC(state /= IDLE); MOSI <= sr(sr'high); idle_out <= (state = IDLE); end if; end process MACHINE; end architecture Behavioral; -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:44:27 2024 X-Received: by 2002:a37:a094:: with SMTP id j142mr2921681qke.2.1560861824736; Tue, 18 Jun 2019 05:43:44 -0700 (PDT) X-Received: by 2002:a0d:d60e:: with SMTP id y14mr14889659ywd.223.1560861824282; Tue, 18 Jun 2019 05:43:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m24no753665qtm.0!news-out.google.com!33ni723qtt.0!nntp.google.com!m24no753664qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2019 05:43:43 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.67.81; posting-account=ItqpGgoAAABEZj4wvqeBOr-Cqw6yt1jN NNTP-Posting-Host: 128.179.67.81 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: output <= registers(to_integer(address)) and intentional meta values From: a.fiergolski@gmail.com Injection-Date: Tue, 18 Jun 2019 12:43:44 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9474 Hi, I have an array of std_logic_vectors. The address selector (unsigned type) = may intentionally be unsigned to don't care/unknown state in order to simpl= ify logic in other parts of a design. In such a case, the simulator will ge= nerate a warning, however, the output vector will be assigned to registers(= 0). My intention, in such a case, would be to assign don't care/unknown sta= te also to the output vector. Is there any best practice for this problem? I know that something like: output <=3D (others =3D> '-') when is_x(address) else registers(to_integer(= address)); could work, but according to my knowledge, the is_x function may have a pro= blem with synthesis. Another option would be to write a process: mux: process(all) begin output <=3D (others =3D> '-'); for i in registers'range loop if address =3D to_unsgined(i, address'range) then output <=3D registers(i); end if; end loop; end process; However, I am worried that the synthesis tool may have an issue to extract = a proper and simple mux from this description. Is there any more straightforward description? I am using VHDL 2008. Regards, Adrian From newsfish@newsfish Thu Aug 1 00:44:28 2024 X-Received: by 2002:aed:3804:: with SMTP id j4mr98965762qte.361.1560864846024; Tue, 18 Jun 2019 06:34:06 -0700 (PDT) X-Received: by 2002:a25:2042:: with SMTP id g63mr58038234ybg.113.1560864845837; Tue, 18 Jun 2019 06:34:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m24no836902qtm.0!news-out.google.com!33ni732qtt.0!nntp.google.com!m24no836893qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2019 06:34:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77066471-db43-4ba9-a86b-28a0ad7364a8@googlegroups.com> Subject: Re: output <= registers(to_integer(address)) and intentional meta values From: Rick C Injection-Date: Tue, 18 Jun 2019 13:34:06 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 58 Xref: reader01.eternal-september.org comp.lang.vhdl:9475 On Tuesday, June 18, 2019 at 8:43:46 AM UTC-4, a.fie...@gmail.com wrote: > Hi, > I have an array of std_logic_vectors. The address selector (unsigned type= ) may intentionally be unsigned to don't care/unknown state in order to sim= plify logic in other parts of a design. In such a case, the simulator will = generate a warning, however, the output vector will be assigned to register= s(0). My intention, in such a case, would be to assign don't care/unknown s= tate also to the output vector. Is there any best practice for this problem= ? > I know that something like: > output <=3D (others =3D> '-') when is_x(address) else registers(to_intege= r(address)); > could work, but according to my knowledge, the is_x function may have a p= roblem with synthesis. >=20 > Another option would be to write a process: >=20 > mux: process(all) > begin > output <=3D (others =3D> '-'); > for i in registers'range loop > if address =3D to_unsgined(i, address'range) then > output <=3D registers(i); > end if; > end loop; > end process; >=20 > However, I am worried that the synthesis tool may have an issue to extrac= t a proper and simple mux from this description. >=20 > Is there any more straightforward description? I am using VHDL 2008. >=20 > Regards, > Adrian Why not convert address to an integer and use it as the index in a simple a= ssignment? Put that assignment inside a conditional that checks the bounds= of the register index and perform the default assignment if that test fail= s.=20 output <=3D registers(to_integer(address)) when=20 (to_integer(address) in registers'range) else=20 output <=3D (others =3D> '-'); Not sure if (to_integer(address) in registers'range) is a valid expression = for this syntax. You may need to break that out as an AND of the upper and= lower limit checks.=20 The way to see what the compiler does with this syntax is to construct a te= st bench that simply instantiates the code and look at the result in your s= ynthesis tool. I would do that with your existing code before bothering to= optimize it.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:28 2024 X-Received: by 2002:a0c:92ab:: with SMTP id b40mr26672401qvb.129.1560865628786; Tue, 18 Jun 2019 06:47:08 -0700 (PDT) X-Received: by 2002:a81:9a07:: with SMTP id r7mr55242885ywg.428.1560865628456; Tue, 18 Jun 2019 06:47:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m24no858111qtm.0!news-out.google.com!33ni732qtt.0!nntp.google.com!m24no858103qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2019 06:47:08 -0700 (PDT) In-Reply-To: <77066471-db43-4ba9-a86b-28a0ad7364a8@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.67.81; posting-account=ItqpGgoAAABEZj4wvqeBOr-Cqw6yt1jN NNTP-Posting-Host: 128.179.67.81 References: <77066471-db43-4ba9-a86b-28a0ad7364a8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <041db48a-4862-4fd7-8260-6f3479f0f8ab@googlegroups.com> Subject: Re: output <= registers(to_integer(address)) and intentional meta values From: a.fiergolski@gmail.com Injection-Date: Tue, 18 Jun 2019 13:47:08 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 4 Xref: reader01.eternal-september.org comp.lang.vhdl:9476 Hi Rick, Thank you for your reply. I haven't simulated it, but as you propose to_integer(address) you will have the same issue: even if the address has meta values, the output of the to_integer will be 0 which lies in the range of registers. From newsfish@newsfish Thu Aug 1 00:44:28 2024 X-Received: by 2002:a37:30c:: with SMTP id 12mr938750qkd.175.1560872376143; Tue, 18 Jun 2019 08:39:36 -0700 (PDT) X-Received: by 2002:a5b:b0b:: with SMTP id z11mr58227138ybp.143.1560872375984; Tue, 18 Jun 2019 08:39:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m24no1049365qtm.0!news-out.google.com!33ni757qtt.0!nntp.google.com!m24no1049364qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2019 08:39:35 -0700 (PDT) In-Reply-To: <041db48a-4862-4fd7-8260-6f3479f0f8ab@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <77066471-db43-4ba9-a86b-28a0ad7364a8@googlegroups.com> <041db48a-4862-4fd7-8260-6f3479f0f8ab@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <171f202c-8b89-429a-b835-7fe814ec9d06@googlegroups.com> Subject: Re: output <= registers(to_integer(address)) and intentional meta values From: Rick C Injection-Date: Tue, 18 Jun 2019 15:39:36 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 37 Xref: reader01.eternal-september.org comp.lang.vhdl:9477 On Tuesday, June 18, 2019 at 9:47:10 AM UTC-4, a.fie...@gmail.com wrote: > Hi Rick, >=20 > Thank you for your reply. >=20 > I haven't simulated it, but as you propose to_integer(address) you will h= ave the same issue: even if the address has meta values, the output of the = to_integer will be 0 which lies in the range of registers. Sorry, I didn't quite catch what you had written. i assume this condition= al is intended only for simulation and debug and has nothing to do with the= operation of the circuit since these values are not synthesizable. =20 In that case, simply substitute the is_X function for the comparison in the= WHEN conditional and it should do what you want... assuming I now understa= nd the full problem.=20 I see in your original post you talk about IS_X not being synthesizable, so= I'm wondering if you really are trying to synthesize the use of meta-value= s. If you give it a bit of thought you will realize there is no hardware t= hat will perform this sort of evaluation, so the use of meta-values can't g= enerate synthesizable logic. I believe constructs like these are simply ig= nored by synthesis.=20 I shouldn't make this sound so absolute though. I believe the value '-' ca= n be used in comparisons as a wild card, but it has been too long since I'v= e done this to remember if it is limited to non-standard extensions of synt= hesizers. After digging a bit, I see VHDL-2008 allows wild cards to be use= d in a version of case statements.=20 Am I getting closer to understanding your question?=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:28 2024 X-Received: by 2002:a0c:ee49:: with SMTP id m9mr28055193qvs.217.1560875082933; Tue, 18 Jun 2019 09:24:42 -0700 (PDT) X-Received: by 2002:a81:57ce:: with SMTP id l197mr66786773ywb.115.1560875082642; Tue, 18 Jun 2019 09:24:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!m24no1132975qtm.0!news-out.google.com!33ni761qtt.0!nntp.google.com!m24no1132966qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2019 09:24:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.16.107.226; posting-account=0JqcqAoAAABxW8ciEXe8j1MIfzWge8xa NNTP-Posting-Host: 88.16.107.226 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ba88f6b-f406-4cc7-b01f-86ef51b82f4a@googlegroups.com> Subject: E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI! CRIMINALISSIMO AVVOCATO DI GENOVA E RAPALLO! E' UN NAZI-ST-ALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE STUPRA ED UCCIDE I BAMBINI: L'AVV DANIELE MINOTTI! AVVOCATO SATA-NAZISTA........ From: "LUIGI BISIGNANI-MAI PIU' COL PEDOFILO BERLUSCONI" Injection-Date: Tue, 18 Jun 2019 16:24:42 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 531 Xref: reader01.eternal-september.org comp.lang.vhdl:9478 E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI! CRIMINALISSIMO A= VVOCATO DI GENOVA E RAPALLO! E' UN NAZI-ST-ALKER ASSASSINO VIA INTERNET, NO= NCHE' PEDERASTA CHE STUPRA ED UCCIDE I BAMBINI: L'AVV DANIELE MINOTTI! AVVO= CATO SATA-NAZISTA.........................DEPRAVATO, PERVERSO, PERVERTITO, = SANGUINARIO, COCAINOMANE, MEGA OMICIDA, DI GENOVA E RAPALLO!!! https://www.flickr.com/photos/danieleminotti/ RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATA= NISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GE= NOVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIS= TA DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI,= AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TI= PO STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 FINO A POCO FA..SGOZZAVA OLTRE CHE CANI, GATTI E SERPENTI, TANTISSIMI BAMBI= NI, IN RITI SATANICI DI TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEG= UONO.. I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMA= ZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRI= O DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO! Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Fax +39 010 91 63 11 54 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER https://www.flickr.com/photos/danieleminotti/ ). A CAPO, ANZI, A KAPO' DI S= ETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA ASSASSINA CHIAMATA " AMMAZZIA= MO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCONI". E' AVVOCATO PEDERASTA IN= CULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO. https://grupy.scigacz.pl/moj,pierwszy,czyli,sprzedam Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.67.81; posting-account=ItqpGgoAAABEZj4wvqeBOr-Cqw6yt1jN NNTP-Posting-Host: 128.179.67.81 References: <77066471-db43-4ba9-a86b-28a0ad7364a8@googlegroups.com> <041db48a-4862-4fd7-8260-6f3479f0f8ab@googlegroups.com> <171f202c-8b89-429a-b835-7fe814ec9d06@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <21c4815b-6952-4678-b40a-eee54dc7f9f6@googlegroups.com> Subject: Re: output <= registers(to_integer(address)) and intentional meta values From: a.fiergolski@gmail.com Injection-Date: Tue, 18 Jun 2019 16:29:30 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 17 Xref: reader01.eternal-september.org comp.lang.vhdl:9479 Yes, I think you are getting closer to the core of the issue. You are right, this condition is intended only for the simulation. I want t= o avoid a mismatch between eventual hardware and the behavioural verificati= on: when address is unknown, also the "output" vector should be unknown. Cu= rrently, in simulation, it will be assigned to registers(0) (to_integer ret= urns 0 for vectors containing meta value bits). An RTL description being ve= rified may rely on this fact (registers(0) output when address is don't car= e) and I would like to exclude it My concern is that line like: output <=3D (others =3D> '-') when is_x(address) else registers(to_integer(= address)); will be fully ignored by a synthesis tool. I think, in general, synthesis t= ool's behaviour is not standardized in such a case. I also confirm VHDL2008 comes with new relational operators (?=3D, ?<...) a= nd case? statements. From newsfish@newsfish Thu Aug 1 00:44:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: output <= registers(to_integer(address)) and intentional meta values Date: Tue, 18 Jun 2019 10:06:48 -0700 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 18 Jun 2019 17:06:50 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="f375e24df2659b8f16b880a9c210d013"; logging-data="18939"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19h/G1C9hsTxs/rtqL9Qc0P" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 Cancel-Lock: sha1:8sYj2IFm2ui5+cilcB266SRcEVg= In-Reply-To: Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9480 On 6/18/19 5:43 AM, a.fiergolski@gmail.com wrote: > Hi, > I have an array of std_logic_vectors. The address selector (unsigned type) may intentionally be unsigned to don't care/unknown state in order to simplify logic in other parts of a design. In such a case, the simulator will generate a warning, however, the output vector will be assigned to registers(0). My intention, in such a case, would be to assign don't care/unknown state also to the output vector. Is there any best practice for this problem? > I know that something like: > output <= (others => '-') when is_x(address) else registers(to_integer(address)); > could work, but according to my knowledge, the is_x function may have a problem with synthesis. > > Another option would be to write a process: > > mux: process(all) > begin > output <= (others => '-'); > for i in registers'range loop > if address = to_unsgined(i, address'range) then > output <= registers(i); > end if; > end loop; > end process; > > However, I am worried that the synthesis tool may have an issue to extract a proper and simple mux from this description. > > Is there any more straightforward description? I am using VHDL 2008. > > Regards, > Adrian > I've definitely used IS_X in synthesizable code for exactly this reason, and done pretty much exactly what you did (I tend to prefer 'X' to '-' as an output don't care and only use '-' as an input don't care). It worked out just fine; IS_X was treated as a constant false and the entire half of the condition dropped out of existence. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:44:29 2024 X-Received: by 2002:a37:815:: with SMTP id 21mr53248988qki.257.1560878900526; Tue, 18 Jun 2019 10:28:20 -0700 (PDT) X-Received: by 2002:a81:5597:: with SMTP id j145mr64182902ywb.328.1560878900355; Tue, 18 Jun 2019 10:28:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m24no1251102qtm.0!news-out.google.com!33ni765qtt.0!nntp.google.com!m24no1251094qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2019 10:28:20 -0700 (PDT) In-Reply-To: <21c4815b-6952-4678-b40a-eee54dc7f9f6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <77066471-db43-4ba9-a86b-28a0ad7364a8@googlegroups.com> <041db48a-4862-4fd7-8260-6f3479f0f8ab@googlegroups.com> <171f202c-8b89-429a-b835-7fe814ec9d06@googlegroups.com> <21c4815b-6952-4678-b40a-eee54dc7f9f6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0607431a-2d43-4277-8cd5-2b4cdde3cee8@googlegroups.com> Subject: Re: output <= registers(to_integer(address)) and intentional meta values From: Rick C Injection-Date: Tue, 18 Jun 2019 17:28:20 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9481 On Tuesday, June 18, 2019 at 12:29:31 PM UTC-4, a.fie...@gmail.com wrote: > Yes, I think you are getting closer to the core of the issue. >=20 > You are right, this condition is intended only for the simulation. I want= to avoid a mismatch between eventual hardware and the behavioural verifica= tion: when address is unknown, also the "output" vector should be unknown. = Currently, in simulation, it will be assigned to registers(0) (to_integer r= eturns 0 for vectors containing meta value bits). An RTL description being = verified may rely on this fact (registers(0) output when address is don't c= are) and I would like to exclude it >=20 > My concern is that line like: > output <=3D (others =3D> '-') when is_x(address) else registers(to_intege= r(address)); > will be fully ignored by a synthesis tool. I think, in general, synthesis= tool's behaviour is not standardized in such a case. >=20 > I also confirm VHDL2008 comes with new relational operators (?=3D, ?<...)= and case? statements. Why not just write a test case and try it with your tools. Most synthesis = tools will let you "see" the resulting logic in diagrams which are easy to = analyze as long as they aren't large.=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:29 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx20.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Code Review: SPI Transmitter Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 8bit X-Antivirus: Avast (VPS 190618-4, 18/06/2019), Outbound message X-Antivirus-Status: Clean Lines: 260 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Wed, 19 Jun 2019 07:53:48 UTC Organization: virginmedia.com Date: Wed, 19 Jun 2019 08:53:49 +0100 X-Received-Bytes: 12391 X-Received-Body-CRC: 3411762196 Xref: reader01.eternal-september.org comp.lang.vhdl:9482 On 17/06/2019 17:58, Rob Gaddi wrote: > So things have been to my mind unfortunately quiet over here for a while > now, so I figured I'd try do get something new going, just in case any > of us have gotten bored with the 118th iteration of telling some > wet-nosed pup to use numeric_std instead of std_logic_arith and > explaining what a process is.  Let's actually talk about VHDL code and > the improving thereof. > > So the rules of the game are simple.  Someone posts their code, and we > talk about it.  Code should be at the bare minimum syntactically valid, > and preferably working.  But how could it have been cleaner, or more > elegant?  Does it scan when you read it?  What obvious low-hanging fruit > of functionality was missed?  Basically, if this was code that you were > going to bring in to your project, what would you have liked to be > different about it? I applaud you for trying to bring back some live in this newsgroup as everybody (with exceptions of some old guys) seemed to have moved to stack exchange, reddit or any of the censorship free vendor mailing lists. I don't think your code review idea will kick off as the traffic is simply to low and engineers generally don't want to expose their bad coding style (including me). However, to give you some comments your code looks great and is easy to read. My only minor suggestion (apart from some personal coding style preferences) would be to add some functional verification directives. It is relative easy to sprinkle some PSL cover directives (or asserts) over your code which then makes the verification job later on a lot easier. Regards, Hans. www.ht-lab.com > > Today I've got code for an SPI transmitter.  The goal was to create > thing that can be kicked off by a register write and update either a > serial DAC or relay-driving shift register.  It requires no > configuration from the software side, and if the software stops writing > to the register it will always ultimately set the connected thing to the > last written value. > > ------------------------------------------------------------------------------- > > -- Title      : SPI Transmitter > -- Project    : T904 TEM Testset > ------------------------------------------------------------------------------- > > -- File       : spi_transmitter.vhd > -- Author     : Rob Gaddi  > -- Company    : Highland Technology, Inc. > -- Created    : 04-Jun-2019 > -- Last update: 04-Jun-2019 > -- Platform   : Xilinx Zynq 7020 (uZed) > -- Standard   : VHDL-2002 > ------------------------------------------------------------------------------- > > -- Description: Sends framed words out over SPI on request. > -- > --  A pulse on go sets a request flag asking the engine to run.  The engine > --  runs at the next available time, which is the time at which it has been > --  idle for at least the MIN_IDLE time.  At "run" time it will latch > whatever > --  the current data on din is and begin the SPI transaction. > -- > --  This means that, if the engine is and has been idle, the go pulse will > --  cause the data on din to start immediately.  If the engine is > --  currently running, an update to din and pulse on go will cause the > engine > --  to finish the transaction it is currently running, then take the new > din. > --  But a second update while the engine is running will cause the first to > --  simply be ignored; the idea being that devices being communicated > with by > --  this engine have only a current state rather than a history or multiple > --  current states, and that the point of the engine is to make the current > --  state correct. > -- > --  idle_out represents the state of the transmitter.  done goes high for a > --  single clock on the completion of the transmit. > -- > --  SPI Information: Clock idle state is low. Data is transitioned on the > --  falling edge of SCLK, under the assumption that it is sampled on the > rising > --  edge.  Data transmits MSB first. > ------------------------------------------------------------------------------- > > -- Revision History: > ------------------------------------------------------------------------------- > > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > use work.standard_functions.all; > > entity spi_transmitter is >     generic ( >         BUS_FREQ_MHZ : integer; >         SCLK_PERIOD  : time; >         MIN_IDLE     : time := 0 ns; >         CS_EXTRA     : time := 0 ns; >         BITS : positive >     ); >     port ( >         -- Logic side >         din  : in  std_logic_vector(BITS-1 downto 0); >         go   : in  boolean; >         idle_out : out boolean; >         done : out boolean; > >         -- Serial side >         MOSI : out std_logic; >         SCLK : out std_logic; >         CS_N : out std_logic; > >         clk  : in  std_logic; >         rst  : in  std_logic >     ); > end entity spi_transmitter; > > architecture Behavioral of spi_transmitter is > >     type t_state is ( >         IDLE, DROP_CS, >         SCLK_LOW, SCLK_HIGH, >         HOLD_CS >     ); > >     constant tClk : time := 1 us / BUS_FREQ_MHZ; > >     -- Number of clocks to spend in each of the states.  For IDLE this is >     -- a minimum, for everyone else it's a fixed time. >     function time_to_clocks(x: time) return natural is >     begin >         return time_to_clocks(x, tClk); >     end function time_to_clocks; > >     constant IDLE_LEN   : natural := time_to_clocks(MIN_IDLE); >     constant CSD_LEN    : natural := time_to_clocks(CS_EXTRA); > >     constant SCLK_LEN   : natural := time_to_clocks(SCLK_PERIOD); >     constant SCLKH_LEN  : natural := SCLK_LEN / 2; >     constant SCLKL_LEN  : natural := SCLK_LEN - SCLKH_LEN; > >     constant CSH_LEN    : natural := time_to_clocks(CS_EXTRA + > SCLK_PERIOD/2); > >     -- Sharing a single timer for all these values requires that it be > large >     -- enough to hold the maximum value. >     function MAXTIMER return natural is >         variable x : natural; >     begin >         x := IDLE_LEN; >         if x < SCLKH_LEN then   x := SCLKH_LEN; end if; >         if x < CSH_LEN then     x := CSH_LEN; end if; >         return x; >     end function MAXTIMER; >     subtype t_timer is integer range 0 to MAXTIMER-1; > > begin > >     MACHINE: process(clk) >         variable go_pending: boolean; >         variable sr: std_logic_vector(din'range); >         variable timer: t_timer; >         variable bits_left : integer range din'range; >         variable state: t_state; > >         -- Procedure for handling simple wait states. >         procedure waitandthen(clocks : in positive; nextstate : in > t_state) is >             constant LIMIT : natural := clocks-1; >         begin >             if timer = LIMIT then >                 timer := 0; >                 state := nextstate; >             else >                 timer := timer + 1; >             end if; >         end procedure waitandthen; > >     begin >         if rising_edge(clk) then >             -- Manage the state machine. >             done <= false; >             case state is >                 when IDLE => >                     if timer = (IDLE_LEN-1) then >                         if go_pending then >                             go_pending := false; > >                             sr := din; >                             bits_left := BITS-1; >                             timer := 0; > >                             -- We don't even have a DROP_CS state if we > don't >                             -- request any extra CS time. >                             if CSD_LEN = 0 then >                                 state := SCLK_LOW; >                             else >                                 state := DROP_CS; >                             end if; >                         end if; >                     else >                         timer := timer + 1; >                     end if; > >                 when DROP_CS    =>  waitandthen(CSD_LEN, SCLK_LOW); >                 when SCLK_LOW =>    waitandthen(SCLKL_LEN, SCLK_HIGH); >                 when SCLK_HIGH => >                     if timer = (SCLKH_LEN-1) then >                         timer := 0; >                         sr := sr(sr'high-1 downto 0) & 'X'; >                         if bits_left = 0 then >                             state := HOLD_CS; >                         else >                             bits_left := bits_left - 1; >                             state := SCLK_LOW; >                         end if; >                     else >                         timer := timer + 1; >                     end if; > >                 when HOLD_CS => >                     waitandthen(CSH_LEN, IDLE); >                     done <= (state = IDLE); >             end case; > >             -- A new data request always sets the go_pending flag, but > a reset >             -- overrides everything. >             if go then >                 go_pending := true; >             end if; >             if (rst = '1') then >                 state := IDLE; >                 timer := 0; >                 sr := (others => 'X'); >                 go_pending := false; >             end if; > >             -- Drive the outputs based on the state. >             SCLK <= POS_LOGIC(state = SCLK_HIGH); >             CS_N <= NEG_LOGIC(state /= IDLE); >             MOSI <= sr(sr'high); >             idle_out <= (state = IDLE); >         end if; >     end process MACHINE; > > end architecture Behavioral; > > > From newsfish@newsfish Thu Aug 1 00:44:30 2024 X-Received: by 2002:a0c:afd5:: with SMTP id t21mr32296337qvc.105.1560936337924; Wed, 19 Jun 2019 02:25:37 -0700 (PDT) X-Received: by 2002:a0d:f5c4:: with SMTP id e187mr53913600ywf.88.1560936337633; Wed, 19 Jun 2019 02:25:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m24no2667198qtm.0!news-out.google.com!4ni110qtw.1!nntp.google.com!m24no2667195qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2019 02:25:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.67.81; posting-account=ItqpGgoAAABEZj4wvqeBOr-Cqw6yt1jN NNTP-Posting-Host: 128.179.67.81 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: output <= registers(to_integer(address)) and intentional meta values From: a.fiergolski@gmail.com Injection-Date: Wed, 19 Jun 2019 09:25:37 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9483 I confirm that my original idea (and confirmed by Rob as well) works: [code] output <= registers(to_integer(address)) when not Is_X(address) else (others => 'U'); [/code] I checked results generated by the synthesis tool, and it seems that it properly ignores (set False) Is_X branch and the generated netlist is equivalent to simple [code] output <= registers(to_integer(address)); [/code] Thank you all for discussion. From newsfish@newsfish Thu Aug 1 00:44:30 2024 X-Received: by 2002:a37:4152:: with SMTP id o79mr72604354qka.276.1560955994079; Wed, 19 Jun 2019 07:53:14 -0700 (PDT) X-Received: by 2002:a25:dc88:: with SMTP id y130mr12698781ybe.14.1560955993830; Wed, 19 Jun 2019 07:53:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!m24no3271666qtm.0!news-out.google.com!4ni150qtw.1!nntp.google.com!m24no3271658qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2019 07:53:13 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.37.126.142; posting-account=noSIMgoAAABlmAktjVKtZ8-b3Cxkethg NNTP-Posting-Host: 62.37.126.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6961391b-be31-40f2-94d0-d2a8225dedce@googlegroups.com> Subject: E' DA ARRESTARE SUBITO: PAOLO BARRAI (LINKEDIN)! E' STATO IL REGISTA CRIMINALISSIMO DELL'OPERAZIONE "EIDOO RICICLA SOLDI MAFIOSI PER LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE EFFERATO PAOLO BARRAI, ABITAVA A MILANO, IN VIA..... From: ROBERTO-GORINI 4 UPPER LTD-LONDON Injection-Date: Wed, 19 Jun 2019 14:53:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9484 UN TESTO OTTIMO, SCRITTO DAL MIO BANCHIERE IN SVIZZERA: IL GRANDE ANDREAS N= IGG DI BANK J SAFRA SARASIN ZURICH (OVE NOI GORINI ABBIAMO QUASI TUTTI I NO= STRI RISPARMI: NERI, BIANCHI, ROSSI, VERDI, GIALLI... DI OGNI COLORE... CI = SIAMO CAPITI). ANDREAS QUI SGAMA I MEGA RICICLAGGI DI SOLDI MAFIOSI DEL BAS= TARDO ASSASSINO, RAZZISTA, LADRO, TRUFFATORE, PEDOFILO, NAZI-S-TALKER PAOLO= BARRAI! A VOI QUESTO FANTASTICO SCRITTO. SALUTA DAL LEGHISTA DI MERDA, TRI= VENETO, OVE VIVO DA SEMPRE.=20 E' DA ARRESTARE SUBITO: PAOLO BARRAI (LINKEDIN)! E' STATO IL REGISTA CRIMIN= ALISSIMO DELL'OPERAZIONE "EIDOO RICICLA SOLDI MAFIOSI PER LA NDRANGHETA"! I= L GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE EFFERATO PAOLO BARRAI, ABIT= AVA A MILANO, IN VIA............. IPPODROMO 105 (ZONA SAN SIRO- CERTOSA). = ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEGA ASSASSINI G= IULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. 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O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). 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LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483=20 From newsfish@newsfish Thu Aug 1 00:44:30 2024 X-Received: by 2002:a05:620a:14ab:: with SMTP id x11mr34859120qkj.186.1560971058209; Wed, 19 Jun 2019 12:04:18 -0700 (PDT) X-Received: by 2002:a81:148b:: with SMTP id 133mr56746176ywu.394.1560971058026; Wed, 19 Jun 2019 12:04:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m24no3812532qtm.0!news-out.google.com!4ni170qtw.1!nntp.google.com!m24no3812529qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2019 12:04:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=65.46.187.134; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 65.46.187.134 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7255ca83-e552-4591-969e-910b23c47e57@googlegroups.com> Subject: Code Review: SPI Transmitter From: KJ Injection-Date: Wed, 19 Jun 2019 19:04:18 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9485 Why is the 'Bus' clock specified as an integer frequency in MHz? All of the= other time related things are specified as time units... the same should b= e done for the clock period. Not to mention I can't remember the last time = I dealt with a clock that had such a nice integer frequency. Lastly, if you= did want to specify frequency it would not be integers but positives. Possibly outside of the scope of your design, but typically I would have to= communicate with more than one SPI device on the board but never independe= ntly since they are controlled by some single processor. In that scenario, = having multiple SPI controllers is wasteful, better to have a single contro= ller that produces multiple CS outputs and share use of all other SPI signa= ls. With that design, you would would want generics for the number of SPI d= evices and arrays of genetics to specify SCLK periods and bits. But again t= hat is probably outside the scope of what are intending here. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:31 2024 X-Received: by 2002:ac8:3037:: with SMTP id f52mr107970662qte.364.1560971627329; Wed, 19 Jun 2019 12:13:47 -0700 (PDT) X-Received: by 2002:a0d:d60e:: with SMTP id y14mr19670037ywd.223.1560971627160; Wed, 19 Jun 2019 12:13:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m24no3833058qtm.0!news-out.google.com!4ni170qtw.1!nntp.google.com!m24no3833055qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2019 12:13:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=65.46.187.134; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 65.46.187.134 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <589d182c-7220-481f-a07b-8b9bb85544eb@googlegroups.com> Subject: Code Review: SPI Transmitter From: KJ Injection-Date: Wed, 19 Jun 2019 19:13:47 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9486 No reset for your state machine... that's an 'oops'. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:31 2024 X-Received: by 2002:a37:c449:: with SMTP id h9mr81856929qkm.187.1560972768251; Wed, 19 Jun 2019 12:32:48 -0700 (PDT) X-Received: by 2002:a25:7444:: with SMTP id p65mr61467885ybc.319.1560972768048; Wed, 19 Jun 2019 12:32:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m24no3875146qtm.0!news-out.google.com!4ni170qtw.1!nntp.google.com!m24no3875145qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2019 12:32:47 -0700 (PDT) In-Reply-To: <589d182c-7220-481f-a07b-8b9bb85544eb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=65.46.187.134; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 65.46.187.134 References: <589d182c-7220-481f-a07b-8b9bb85544eb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <90abbf4a-38ff-42c8-ad22-e6d424b26a47@googlegroups.com> Subject: Code Review: SPI Transmitter From: KJ Injection-Date: Wed, 19 Jun 2019 19:32:48 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9487 My 'oops', I now see the reset signal 'rst' being used in the state machine. Also unclear is why 'clk' and 'rst' aren't considered part of the 'logic' set of signals. By the way, the design process isn't 'Wheel of Fortune' where vowels cost money. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:31 2024 X-Received: by 2002:ac8:26d5:: with SMTP id 21mr50856502qtp.266.1560974440489; Wed, 19 Jun 2019 13:00:40 -0700 (PDT) X-Received: by 2002:a0d:f5c4:: with SMTP id e187mr55765780ywf.88.1560974440328; Wed, 19 Jun 2019 13:00:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.usenet.farm!feed.usenet.farm!newsreader4.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!m24no3935768qtm.0!news-out.google.com!4ni175qtw.1!nntp.google.com!m24no3935763qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2019 13:00:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=65.46.187.134; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 65.46.187.134 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Code Review: SPI Transmitter From: KJ Injection-Date: Wed, 19 Jun 2019 20:00:40 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3190 X-Received-Body-CRC: 1606757643 Xref: reader01.eternal-september.org comp.lang.vhdl:9488 For the 'logic' side, the signal names leave much to the imagination. Let'= s say you have no clue at all what the design is supposed to do, would this= set of signals give you any idea if what this part of the interface is sup= posed to do? =C2=A0=C2=A0din =C2=A0: in =C2=A0std_logic_vector(BITS-1 downto 0);=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0go =C2=A0 : in =C2=A0boolean;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0idle_out : out boolean;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0done : out boolean;=C2=A0 My guess is 'No'. 'Go', 'idle_out', 'done', really? What this interface re= ally is, is a write only processor type of interface (that may or may not a= ctually be controlled by a processor). If you accept that, then you should = be looking to use an already existing convention for that type of interface= . Wishbone or Avalon come to mind. Then the interface signals would have n= ames like 'Write', 'WriteData', and 'WaitRequest' and you could describe it= as an Avalon or Wishbone compatible interface and be done. Your audience w= ould know what the interface is or could look it up in the appropriate docu= mentation for Avalon or Wishbone. No need to go into the guts of the design= to figure out how to use it. On the one hand, this may seem like just that the signal names are being re= named so it is cosmetic and not important. But look again. Using an accept= ed interface there are two control and status signals where you used three = and there is no discernable advantage to the user of your code having that = extra status. Being superfluous, that extra signal makes your design harde= r to use, not easier. As a user of your code I wouldn't want to have to loo= k beyond the interface to have to figure out how to use it. Don't reinvent the wheel, this one came out not round. Use existing standa= rds and conventions for every interface.=20 Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:32 2024 X-Received: by 2002:a37:2750:: with SMTP id n77mr10118452qkn.370.1561207204829; Sat, 22 Jun 2019 05:40:04 -0700 (PDT) X-Received: by 2002:a25:7444:: with SMTP id p65mr70070552ybc.319.1561207204453; Sat, 22 Jun 2019 05:40:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m24no5598902qtm.0!news-out.google.com!4ni281qtw.1!nntp.google.com!m24no5598895qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 22 Jun 2019 05:40:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.99.192.2; posting-account=mVwp1AoAAAAkPAWpK5Z39ahNoRqLW1hn NNTP-Posting-Host: 103.99.192.2 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <178f04c3-1ce9-4010-86b2-bd96b0566de0@googlegroups.com> Subject: Re: Cadence Simvision question From: pursh012@gmail.com Injection-Date: Sat, 22 Jun 2019 12:40:04 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9489 Thanks for your info. It really helped From newsfish@newsfish Thu Aug 1 00:44:32 2024 X-Received: by 2002:ac8:2b90:: with SMTP id m16mr514628qtm.384.1561498345837; Tue, 25 Jun 2019 14:32:25 -0700 (PDT) X-Received: by 2002:a81:9a07:: with SMTP id r7mr587297ywg.428.1561498345584; Tue, 25 Jun 2019 14:32:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!m24no340550qtm.0!news-out.google.com!e20ni33qta.0!nntp.google.com!m24no340546qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Jun 2019 14:32:25 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=47.63.138.211; posting-account=khlczQoAAABAM1D7-5r8Wo78Dk7INUt4 NNTP-Posting-Host: 47.63.138.211 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5103820f-ea07-41a3-b4ee-125c17e683ff@googlegroups.com> Subject: E' DA ARRESTARE SUBITO, L'AVVOCATO ASSASSINO DANIELE MINOTTI DI RAPALLO E GENOVA. NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI! E' AVVOCATO MALVITOSISSIMO, PEDERASTA ED OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E MILANO ( http From: MariaGrazia Crupi Examantedi MarinaBerlusconi Injection-Date: Tue, 25 Jun 2019 21:32:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9490 E' DA ARRESTARE SUBITO, L'AVVOCATO ASSASSINO DANIELE MINOTTI DI RAPALLO E G= ENOVA. NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI! E' AVVOCATO MALVITOSISSIMO,= PEDERASTA ED OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI= DI LECCE E MILANO ( https://www.studiolegalelisi.it=20 STUDIO LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI= SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E'= STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE STUPRA ED UCCIDE I B= AMBINI, QUESTO AVV DELINQUENTISSIMO DANIELE MINOTTI! AVVOCATO SATANISTA, NA= ZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI RAPALLO E GENOVA. https://www.flickr.com/photos/danieleminotti/ RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 OGNI SETTIMANA SGOZZA OLTRE CHE CANI, GATTI E SERPENTI, TANTI BAMBINI, IN R= ITI SATANICI. IN TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEGUONO.. = I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMAZZATI, = FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRIO DALL'= AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI DI RAPALLO E GENO= VA http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI MEGA OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://genova.repubblica.it/cronaca/2011/06/14/news/riti_voodoo_al_cimiter= o_di_staglieno-17668927/ https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO KILLER= , NAZISTA E PEDOFILO, STUPRANTE ED UCCIDENTE BAMBINI SU BAMBINI: DANIELE MI= NOTTI DI RAPALLO E GENOVA! Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI ED OMICIDA ). A CAPO, ANZI, A KAPO' DI UNA SETTA = ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA ASSASSINA CHIAMATA " AMMAZZIAMO PE= R NOSTRO SATANA IN TERRA: SILVIO BERLUSCONI". E' AVVOCATO PEDERASTA INCULA = ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO. UNITO IN CIO' AI PARIMENTI SATANAZISTI, CORROTTI E MEGA COCAINOMANI MARIO G= IORDANO, CALUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSELMA DEL'OLI= O ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). =20 =20 =20 =20 =20 2 ED ALL'ARRESTATO REGISTA, VOMITEVOLISSIMAMENTE PEDOFILO: GIUSEPPE LAZZARI D= I BRESCIA ( REGISTA PEDERASTISSIMO GIUSEPPE LAZZARI DI BRESCIA https://grupy.scigacz.pl/E,REGISTA,ASSASSINO,E,PEDERASTA,GIUSEPPE,LAZZARI,(= ,FINITO,IN,CARCERE,PER,QUESTO,2,114482,2019_04.html CHE, COME VEDETE DA QUESTO VIDEO, E' PAPPA E CICCIA CON LA NOTISSIMA PEDOFI= LA TANTO QUANTO ANSELMA DELL'OLIO https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). STUPRI ED UCCISIONI DI BAM= BINI CHE AVVENGONO ANCHE COL TRE VOLTE FINITO IN GALERA PAOLO BARRAI ( NOTO= , NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFILO DEL BITCOIN= " ). NOTO PEDOFILO ED ASSASSINO PAOLO BARRAI DI CRIMINALISSIMA, DI NDRANGHETISTA= EIDOO https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.rsi.ch/la1/programmi/informazione/falo/tutti-i-servizi/Bella-ge= nte-10474214.html IL TUTTO INSIEME AL PARIMENTI, NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DE = IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO SE SI= E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORRA, N= DRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA: RIC= ORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AFFILI= ATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUO PEZZO DI MERDA NAZISTA FIGLI= O PIERSILVIO BERLUSCONI https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI KILLER DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTAPO,= DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZIFAS= CISTI CRIMINALISSIMI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONE= RO https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html ). =20 =20 =20 =20 =20 =20 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA VIA BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI VIA BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI VIA BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI VIA BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E VERME ASSASSINO MARCO MANCINI ( QUESTI ULTI= MI, CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE= NON TOPO DI FOGNA BERLUSCONICCHIO COME LORO, VIA "DISARTICOLAZIONI DI TIPO= TRAUMATICO", OSSIA OMICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, M= ALORI, INCIDENTI)! OGNI COSA POTETE RISCONTRARLA PRESSO QUESTI VINCENTISSIMI LINKS http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l http://www.pmli.it/sismicolpivanemiciberlusconi.htm ). MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! AVVOCATO FIGLIO DI PUTTANA ASSASSINO E PEDOFILO DANIELE MINOTTI DI RAPALLO = E GENOVA, CHE NON PER NIENTE, DIFENDE PEDOFILI KILLERS COME LUI, A MAN BASS= A ( FRA TOPI DI FOGNA PERVERTITISSIMI CI SI CAPISCE) http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 TROVATE QUALSIASI ALTRA INFORMAZIONE SUL MASSONE NAZISTA, SUL SATANISTA NAZ= ISTA, SUL SATANAZISTA, PEDOFILO, PEDERASTA, ASSASSINO DANIELE MINOTTI DI RA= PALLO E GENOVA, QUI: www.py.cz/pipermail/python/2017-March/012978.html E QUI https://www.mail-archive.com/docker-dev@googlegroups.com/msg00517.html COME PURE QUI E STRA QUI https://www.mail-archive.com/support-seamonkey@lists.mozilla.org/msg74904.h= tml =20 =20 =20 =20 =20 =20 4 PER CONCLUDERE, A VOI ORA IL TESTO PRIMA CITATO DI UN IMMIGRATO RUMENO, STE= FAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGUE, ALLORCHE' POCO PIU' CHE = BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO, NONCHE' VERMINOSO PEDOFIL= O DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA ( I POSTS DI STEFAN CUMESCU= , DI CUI ERA STRA COLMA LA RETE, SONO STATI FATTI TUTTI CANCELLARE DALL'ASS= ASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI... OVVIO, HA LA COSCIENZA L= ERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PERVERTITISSIMA PEDERASTA ED O= MICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO VENIRE E STRA VENIRE A GALLA= NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAAD!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scrito Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:44:32 2024 X-Received: by 2002:a05:620a:1443:: with SMTP id i3mr13935365qkl.11.1561821685912; Sat, 29 Jun 2019 08:21:25 -0700 (PDT) X-Received: by 2002:a0d:d60e:: with SMTP id y14mr9224531ywd.223.1561821685714; Sat, 29 Jun 2019 08:21:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!m24no6201965qtm.0!news-out.google.com!4ni111qtw.1!nntp.google.com!m24no6201963qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 29 Jun 2019 08:21:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2600:1:c261:618:d8e3:e9bd:5904:415a; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1:c261:618:d8e3:e9bd:5904:415a References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <82b98e63-29f9-4ad2-90f5-7a5cb6180155@googlegroups.com> Subject: Code Review: SPI Transmitter From: KJ Injection-Date: Sat, 29 Jun 2019 15:21:25 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9491 "so I figured I'd try do get something new going" Well, that was short lived Kevin From newsfish@newsfish Thu Aug 1 00:44:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Code Review: SPI Transmitter Date: Mon, 1 Jul 2019 09:39:32 -0700 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <589d182c-7220-481f-a07b-8b9bb85544eb@googlegroups.com> <90abbf4a-38ff-42c8-ad22-e6d424b26a47@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 1 Jul 2019 16:39:32 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="2ea71db7a0510169ea5095ee06dcd6a1"; logging-data="1860"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/QY6CdhICbeTNaGLJcZeRv" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 Cancel-Lock: sha1:I2tIOc1fEYiHxpKv1UMZw4InCaA= In-Reply-To: <90abbf4a-38ff-42c8-ad22-e6d424b26a47@googlegroups.com> Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9492 On 6/19/19 12:32 PM, KJ wrote: > My 'oops', I now see the reset signal 'rst' being used in the state machine. Also unclear is why 'clk' and 'rst' aren't considered part of the 'logic' set of signals. By the way, the design process isn't 'Wheel of Fortune' where vowels cost money. > > Kevin Jennings > Yeah, but all those keystrokes on my poor tired fingers! I'd argue that clk at least is pretty much standard in VHDL code; it's the reference name for the one and only clock you've got in tutorials going back decades. Reset, on the other hand, well that's just a mess everywhere. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:44:33 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Code Review: SPI Transmitter Date: Mon, 1 Jul 2019 09:49:11 -0700 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: <7255ca83-e552-4591-969e-910b23c47e57@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 1 Jul 2019 16:49:13 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="2ea71db7a0510169ea5095ee06dcd6a1"; logging-data="6727"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19stBcaZQ1twOXto4m5i9rJ" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 Cancel-Lock: sha1:yR4smbPlS4ILhQyKk1sFEGGwpME= In-Reply-To: <7255ca83-e552-4591-969e-910b23c47e57@googlegroups.com> Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9493 On 6/19/19 12:04 PM, KJ wrote:> Why is the 'Bus' clock specified as an integer frequency in MHz? All of the other time related things are specified as time units... the same should be done for the clock period. Not to mention I can't remember the last time I dealt with a clock that had such a nice integer frequency. Lastly, if you did want to specify frequency it would not be integers but positives. > A function of how I've done things for a while, back when I couldn't trust the synthesis tools to handle math on time objects correctly even when it all cooked down to integers at compile time. But you're absolutely right, having already decided that the tools will handle time right the rest of the time, I should really make that interface consistent. I haven't yet because whenever I do it it's going to be a nuisance, but if it'll be a nuisance whenever then the time to do it is now. > Possibly outside of the scope of your design, but typically I would have to communicate with more than one SPI device on the board but never independently since they are controlled by some single processor. In that scenario, having multiple SPI controllers is wasteful, better to have a single controller that produces multiple CS outputs and share use of all other SPI signals. With that design, you would would want generics for the number of SPI devices and arrays of genetics to specify SCLK periods and bits. But again that is probably outside the scope of what are intending here. > > Kevin Jennings > As you said, outside the scope. At the hardware level on this design we've got plenty of pins, and the SPI target devices are situated somewhat radially out from the FPGA, so trying to share copper makes signal integrity a mess. Also, I'm amazed by how many SPI devices deal with being multidropped badly. I've seen a couple of ADCs that get deeply confused if the SCLK coming in is too fast, even if they're not even chip-selected during the process. One of these days I've got a vision in the back of my head of doing a really GOOD queued SPI controller to use as a standard peripheral. Generic as you suggested for number of devices, but with an array of registers describing the devices that get configured by the processor at runtime for clock rate, polarity stuff, and a general purpose bitmask of "And how should the CS lines look when you address this device" given the number of wacky not-quite-SPI devices with positive CS, or maybe you also need to control a tri-state buffer along the way, etc. Then arrays as well of write-data and read-data registers, one for each device, but they all funnel through the same queue and the core takes care of all the details. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:44:33 2024 X-Received: by 2002:a37:464a:: with SMTP id t71mr33672182qka.436.1562200944242; Wed, 03 Jul 2019 17:42:24 -0700 (PDT) X-Received: by 2002:a81:678a:: with SMTP id b132mr24016223ywc.96.1562200944013; Wed, 03 Jul 2019 17:42:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!m24no4202979qtm.0!news-out.google.com!g23ni68qtq.1!nntp.google.com!m24no4202968qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Jul 2019 17:42:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.81.36.75; posting-account=dxdUwwoAAAC9GWVUgihc3u5gmh-STT4K NNTP-Posting-Host: 2.81.36.75 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72b00bcc-6e28-4f0f-9b3d-e5ef13fba112@googlegroups.com> Subject: IL PEDOFILO ASSASSINO PAOLO BARRAI, IL NUOVO SITO LO FARA' A SAN VITTORE! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STUPRA ED UCCIDE BAMBINI. HA RICICLATO CASH ASSASSINO DI NDRANGHETA IN MALAVITOSISSIMA ICO EIDOO! E' STATO CACCIATO DA.. From: TIAZZERAIRISPARMI PAOLO BARRAI TRUFFAVIABITCOIN Injection-Date: Thu, 04 Jul 2019 00:42:24 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 262 Xref: reader01.eternal-september.org comp.lang.vhdl:9494 IL PEDOFILO ASSASSINO PAOLO BARRAI, IL NUOVO SITO LO FARA' A SAN VITTORE! T= RATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STUPRA ED UCCIDE BAM= BINI. HA RICICLATO CASH ASSASSINO DI NDRANGHETA IN MALAVITOSISSIMA ICO EIDO= O! E' STATO CACCIATO DA.................CITIBANK E FATTO CONDANNARE A GALER= A DA CITIBANK! HA FATTO FILM PEDOPORNOGRAFICI, STUPRANDO QUASI A MORTE TANT= I BAMBINI! HA UCCISO LUI STESSO, TANTI BAMBINI, PER PRENDER I LORO ORGANI E= TRAFFICARLI! HA FATTO FILM PORNO CON CAVALLI, BEVENDO LITRI DI SPERMA EQUI= NO! E' STATO MULTATO DA CONSOB BEN 70.000 EURO! HA 23 CAUSE, CON GENTE DI M= EZZA DITTATURA FASCIOMAFIOSA DI BERLUSCONIA, A CUI HA AZZERATO I RISPARMI! = PER SCAPPARE ALLE QUALI, SI E' ORA RIFUGIATO A LONDRA, OVE FA TANTI POMPINI= AL NAZISTA NIGEL FARAGE ED ALLA MEGA PALLA DI MERDA FASCISTOIDE, BORIS JOH= NSON, AFFINCHE' I DUE LO PROTEGGANO! E' STATO CONDANNATO AL CARCERE IN BRAS= ILE, ANCHE PER PEDERASTIA VIOLENTA ( E PER ALTRI TANTISSIMI CRIMINI)! NON N= E AZZECCA MAI MEZZA UNA IN BORSA, OVE AZZERA I RISPARMI DI TUTTI E SEMPRE! = E VI E' TANTISSIMO PIU', DI CUI SCRIVEREMO FINO A 15 MINUTI DOPO LA NOSTRA = MORTE! =20 =20 E' DA ARRESTARE IMMEDIATAMENTE: PAOLO BARRAI (CRYPTOPOLIS E CRYPTOLAB)! E' = STATO IL REGISTA CRIMINALE DELL'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER = LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO P= AOLO BARRAI, ABITAVA A MILANO, IN VIA.......... IPPODROMO 105 (ZONA SAN SIR= O- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEG= A ASSASSINI GIULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://in.memory.of.e.tern.al/comp.lang.tcl/thread/4226231 - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:33 2024 X-Received: by 2002:a37:9185:: with SMTP id t127mr5178237qkd.384.1562373808662; Fri, 05 Jul 2019 17:43:28 -0700 (PDT) X-Received: by 2002:a25:4295:: with SMTP id p143mr3764866yba.319.1562373808383; Fri, 05 Jul 2019 17:43:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!m24no10918598qtm.0!news-out.google.com!g23ni325qtq.1!nntp.google.com!m24no10918594qtm.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Jul 2019 17:43:28 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:8a0:e7f3:2901:19cd:1774:245e:278d; posting-account=ZoBkmgoAAADd2njBbWf4kq3j42Go0CxZ NNTP-Posting-Host: 2001:8a0:e7f3:2901:19cd:1774:245e:278d User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e7cee6d-1ece-4b6b-9435-c990700f7dc3@googlegroups.com> Subject: E' DA ARRESTARE: PAOLO BARRAI (LINKEDIN)! E' STATO IL REGISTA CRIMINALE DELL'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO PAOLO BARRAI, ABITAVA A MILANO, IN VIA.......... IPPODRO From: INCULAIBAMBINI PAOLO BARRAI ILPEDOFILODELBITCOIN Injection-Date: Sat, 06 Jul 2019 00:43:28 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9495 E' DA ARRESTARE: PAOLO BARRAI (LINKEDIN)! E' STATO IL REGISTA CRIMINALE DEL= L'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER LA NDRANGHETA"! IL GIA' 3 VOLT= E FINITO IN GALERA, IL DELINQUENTE BASTARDO PAOLO BARRAI, ABITAVA A MILANO,= IN VIA.......... IPPODROMO 105 (ZONA SAN SIRO- CERTOSA). ED IN ZONA SAN SI= RO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEGA ASSASSINI GIULIANO MARTINO, = VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://in.memory.of.e.tern.al/comp.lang.tcl/thread/4226231 - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:34 2024 X-Received: by 2002:a0c:a8d2:: with SMTP id h18mr904954qvc.16.1562811359568; Wed, 10 Jul 2019 19:15:59 -0700 (PDT) X-Received: by 2002:a25:4d85:: with SMTP id a127mr643514ybb.119.1562811358889; Wed, 10 Jul 2019 19:15:58 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Wed, 10 Jul 2019 19:15:58 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:8a0:e7f3:2901:9c3a:b4a0:492e:9461; posting-account=qePucQoAAACGv7xYHeqgBe4oEaQAApgS NNTP-Posting-Host: 2001:8a0:e7f3:2901:9c3a:b4a0:492e:9461 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <716cd3f8-2fd1-4500-9d10-0bdbae0826cb@googlegroups.com> Subject: IL BASTARDO CRIMINALE PAOLO BARRAI, IL NUOVO SITO LO FARA' A SAN VITTORE! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDOFILO CHE STUPRA ED AMMAZZA BAMBINI. HA RICICLATO CASH ASSASSINO DI NDRANGHETA IN MALAVITOSISSIMA ICO EIDOO! E' STATO CACCIATO DA.. From: TRUFFATORE-MEGASCAMMER PAOLO BARRAI EINCULAIBAMBIN Injection-Date: Thu, 11 Jul 2019 02:15:59 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no4446912qtq.0!news-out.google.com!g23ni1233qtq.1!nntp.google.com!b26no4446906qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9496 IL BASTARDO CRIMINALE PAOLO BARRAI, IL NUOVO SITO LO FARA' A SAN VITTORE! T= RATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDOFILO CHE STUPRA ED AMMAZZA BAM= BINI. HA RICICLATO CASH ASSASSINO DI NDRANGHETA IN MALAVITOSISSIMA ICO EIDO= O! E' STATO CACCIATO DA........CITIBANK E FATTO CONDANNARE A GALERA DA CITI= BANK! HA FATTO FILM PEDOPORNOGRAFICI, STUPRANDO QUASI A MORTE TANTI BAMBINI= ! HA UCCISO LUI STESSO, TANTI BAMBINI, PER PRENDER I LORO ORGANI E TRAFFICA= RLI! HA FATTO FILM PORNO CON CAVALLI, BEVENDO LITRI DI SPERMA EQUINO! E' ST= ATO MULTATO DA CONSOB BEN 70.000 EURO! HA 23 CAUSE, CON GENTE DI MEZZA DITT= ATURA FASCIOMAFIOSA DI BERLUSCONIA, A CUI HA AZZERATO I RISPARMI! PER SCAPP= ARE ALLE QUALI, SI E' ORA RIFUGIATO A LONDRA, OVE FA TANTI POMPINI AL NAZIS= TA NIGEL FARAGE ED ALLA MEGA PALLA DI MERDA FASCISTOIDE, BORIS JOHNSON, AFF= INCHE' I DUE LO PROTEGGANO! E' STATO CONDANNATO AL CARCERE IN BRASILE, ANCH= E PER PEDERASTIA VIOLENTA ( E PER ALTRI TANTISSIMI CRIMINI)! NON NE AZZECCA= MAI MEZZA UNA IN BORSA, OVE AZZERA I RISPARMI DI TUTTI E SEMPRE! E VI E' T= ANTISSIMO PIU', DI CUI SCRIVEREMO FINO A 15 MINUTI DOPO LA NOSTRA MORTE! =20 =20 E' DA ARRESTARE IMMEDIATAMENTE: PAOLO BARRAI (CRYPTOPOLIS E CRYPTOLAB)! E' = STATO IL REGISTA CRIMINALE DELL'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER = LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO P= AOLO BARRAI, ABITAVA A MILANO, IN VIA.......... IPPODROMO 105 (ZONA SAN SIR= O- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEG= A ASSASSINI GIULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:34 2024 X-Received: by 2002:a0c:d94e:: with SMTP id t14mr3417543qvj.18.1562878901921; Thu, 11 Jul 2019 14:01:41 -0700 (PDT) X-Received: by 2002:a25:7254:: with SMTP id n81mr3607712ybc.200.1562878901766; Thu, 11 Jul 2019 14:01:41 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Thu, 11 Jul 2019 14:01:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=51.253.98.43; posting-account=lCPCjwoAAAAxfjE9RBrFbBQMwNcp3Cs1 NNTP-Posting-Host: 51.253.98.43 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4bb0232c-e93b-4414-a757-806dcc83d9b6@googlegroups.com> Subject: =?UTF-8?B?VXMgY29uZ3Jlc3MgaGVhcmluZyBvZiBtYWFuIGFsc2FhbiBNb25leSBsYXVuZHJ5INmC?= =?UTF-8?B?2LbZitipINin2YTZg9mI2YbYutis2LHYsyDZhNi62LPZitmEINin2YTYo9mF2YjYp9mEINmE2YTZhdmE?= =?UTF-8?B?2YrYp9iv2YrYsSDZhdi52YYg2KfZhNi12KfZhti5?= From: kamal a Injection-Date: Thu, 11 Jul 2019 21:01:41 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: base64 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no215857qtq.0!news-out.google.com!a5ni33qtd.0!nntp.google.com!b26no215849qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9497 DQoNCllvdVR1YmUgdmlkZW9zIG9mDQoNCiANCg0KIFUuUy4gQ29uZ3Jlc3MgbW9uZXkgbGF1bmRl cmluZyBoZWFyaW5nDQoNCg0Kb2YgDQoNClNhdWRpIEJpbGxpb25haXJlICAiIE1hYW4gIEFsIHNh bmVhIg0KDQogd2l0aCBiYW5rIG9mIEFtZXJpY2EgDQoNCg0KYW5kICBUaGUgIG93bmVyIG9mIFNh YWQgSG9zcGl0YWwgYW5kICBTY2hvb2xzDQoNCiBpbiB0aGUgRWFzdGVybiBQcm92aW5jZSBpbiBT YXVkaSBBcmFiaWENCg0KIA0KDQphbmQgdGhlIENoYWlybWFuIG9mIHRoZSBCb2FyZCBvZiBEaXJl Y3RvcnMgb2YgQXdhbCBCYW5rICBpbiBCYWhyYWluIA0KDQoNCldpdGggQXJhYmljIFN1YnRpdGxl cw0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0K DQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoN Cg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0K DQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoNCg0KDQoN Cg0KDQoNCg0KDQoNCg0KaHR0cDovL3d3dy55b3V0dWJlLmNvbS93YXRjaD92PW1JQk5uUXZoVThz DQoNCiANCg0KIA0KDQrZhdmI2YLYuSDYp9mE2YrZiNiq2YrZiNioINin2YTYsNmKINi52LHYtiDY rNmE2LPYqSDYp9iz2KrZhdin2Lkg2KfZhNmD2YjZhtis2LHYsyDYp9mE2KPZhdix2YrZg9mKIA0K DQog2YTZhdiq2KfYqNi52Kkg2YbYtNin2LfYp9iqINi62LPZhCDYp9mE2KPZhdmI2KfZhCDZiNmG 2LTYp9i32KfYqg0KDQogDQoNCtin2YTYs9i52YjYr9mKINmF2LnZhiDYudio2K/Yp9mE2YjYp9it 2K8g2KfZhNi12KfZhti5DQoNCiAgDQoNCtmF2KfZhNmDINmF2LPYqti02YHZiSAg2YjYtNix2YPY qSDYs9i52K8gINmI2YXYr9in2LHYsyDYs9i52K8g2KjYp9mE2YXZhti32YLYqSDYp9mE2LTYsdmC 2YrYqSDYqNin2YTYs9i52YjYr9mK2KkgICDZiNix2KbZitizINmF2KzZhNizINin2K/Yp9ix2Kkg 2KjZhtmDINin2YjYp9mEINin2YTYqNit2LHZitmG2YoNCg0KICANCg0K2YXYqtix2KzZhSDYqNin 2YTZhNi62Kkg2KfZhNi52LHYqNmK2KkNCg0KIA0KDQpodHRwOi8vd3d3LnlvdXR1YmUuY29tL3dh dGNoP3Y9bUlCTm5RdmhVOHMNCg0KIA0K From newsfish@newsfish Thu Aug 1 00:44:34 2024 X-Received: by 2002:a37:7702:: with SMTP id s2mr16863489qkc.247.1563201124670; Mon, 15 Jul 2019 07:32:04 -0700 (PDT) X-Received: by 2002:a81:eb09:: with SMTP id n9mr16591102ywm.115.1563201124383; Mon, 15 Jul 2019 07:32:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!b26no924226qtq.0!news-out.google.com!a5ni578qtd.0!nntp.google.com!b26no924222qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Jul 2019 07:32:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.255.51.195; posting-account=SWOeEgoAAADAfTMsgLrhpAAOtEVjk8Di NNTP-Posting-Host: 62.255.51.195 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Replacing xilinx "ASYNC_REG" directive with a TCL script method. From: Edward Fisher Injection-Date: Mon, 15 Jul 2019 14:32:04 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 26 Xref: reader01.eternal-september.org comp.lang.vhdl:9498 Hi all,=20 The Xilinx tools allow an attribute called "ASYNC_REG" to be applied to FFs= to constrain their placement for clock domain crossing synchroniser FFs. T= he attribute also ensures that various optimisations are not applied to the= se registers (e.g. register balancing etc). For a dual flip-flop synchroniser, I could apply the attribute to the two F= Fs in the VHDL. However the style guide for my current role states that dir= ectives are to be avoided (e.g. DONT_TOUCH, KEEP etc) and instead scripts c= an be used. This is because such directives may not be portable between syn= thesis tools (Xilinx, Intel, Mentor etc). Question: - Assuming that we want to use register balancing (retiming) within the de= sign globally. We need some method to prevent this optimisation being appli= ed to the CDC synchroniser logic. If I can't use the compile directive how = could I achieve the same using TCL? - If the TCL knew the synthesis route, it could select the correct compile= time directive and then boot up the relevant tool (Vivado vs Quartus vs Pr= ecision). That way in all cases the attribute would match the tool. However= , after some digging, I cannot find the Intel equivalent of the Xilinx "ASY= NC_REG" attribute. Many thanks, Ed From newsfish@newsfish Thu Aug 1 00:44:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx08.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Replacing xilinx "ASYNC_REG" directive with a TCL script method. Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190715-2, 15/07/2019), Outbound message X-Antivirus-Status: Clean Lines: 46 Message-ID: <781XE.1748715$Szs1.1386616@fx08.am4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Mon, 15 Jul 2019 15:40:51 UTC Organization: virginmedia.com Date: Mon, 15 Jul 2019 16:40:51 +0100 X-Received-Bytes: 3326 X-Received-Body-CRC: 2132361302 Xref: reader01.eternal-september.org comp.lang.vhdl:9499 On 15/07/2019 15:32, Edward Fisher wrote: > Hi all, > > The Xilinx tools allow an attribute called "ASYNC_REG" to be applied to FFs to constrain their placement for clock domain crossing synchroniser FFs. The attribute also ensures that various optimisations are not applied to these registers (e.g. register balancing etc). > > For a dual flip-flop synchroniser, I could apply the attribute to the two FFs in the VHDL. However the style guide for my current role states that directives are to be avoided (e.g. DONT_TOUCH, KEEP etc) and instead scripts can be used. This is because such directives may not be portable between synthesis tools (Xilinx, Intel, Mentor etc). > > Question: > - Assuming that we want to use register balancing (retiming) within the design globally. We need some method to prevent this optimisation being applied to the CDC synchroniser logic. If I can't use the compile directive how could I achieve the same using TCL? > > - If the TCL knew the synthesis route, it could select the correct compile time directive and then boot up the relevant tool (Vivado vs Quartus vs Precision). That way in all cases the attribute would match the tool. However, after some digging, I cannot find the Intel equivalent of the Xilinx "ASYNC_REG" attribute. Hi Ed, I think the reason you can't find it because it is generally know as register retiming. Quartus QNS has the dont_retime attribute which you put on your synchroniser FFs. signal my_reg : std_logic; attribute dont_retime : boolean; attribute dont_retime of my_reg : signal is true; I don't believe there is a universal method (nothing in SDC) to apply this to the various synthesis tools. There are no checks on attributes so I can understand why some coding styles wants you to avoid them. VHDL2018 will have the `define option which allows you to perform various actions depending on the vendor. For the moment you could use one of many pre-parsers until VHDL2018 becomes available. Personally I would use attributes and then before the project completion purchase a short term CDC tool license and check all your synchronisers. Getting it right is surprisingly difficult. Good luck, Hans www.ht-lab.com > > Many thanks, > Ed > From newsfish@newsfish Thu Aug 1 00:44:35 2024 X-Received: by 2002:a37:4a04:: with SMTP id x4mr19086056qka.408.1563222156427; Mon, 15 Jul 2019 13:22:36 -0700 (PDT) X-Received: by 2002:a81:4801:: with SMTP id v1mr16651163ywa.105.1563222156087; Mon, 15 Jul 2019 13:22:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!newsreader4.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!b26no1810079qtq.0!news-out.google.com!a5ni635qtd.0!nntp.google.com!b26no1810071qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Jul 2019 13:22:35 -0700 (PDT) In-Reply-To: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.36.200.143; posting-account=FiJOqwoAAABTa9aMB9-1UUgsWPfCZi5j NNTP-Posting-Host: 81.36.200.143 References: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9cc26d5c-c746-469a-9ff8-f7703a2df9f2@googlegroups.com> Subject: Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI OMICIDA A From: RICICLASOLDIMAFIOSI PAOLO BARRAI ORDINATANTIOMICID Injection-Date: Mon, 15 Jul 2019 20:22:36 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 17111 X-Received-Body-CRC: 3212818880 Xref: reader01.eternal-september.org comp.lang.vhdl:9500 Lines: 246 E' DA ARRESTARE: PAOLO BARRAI (LINKEDIN)! E' STATO IL REGISTA CRIMINALISSIM= O DELL'OPERAZIONE "EIDOO RICICLA SOLDI MAFIOSI PER LA NDRANGHETA"! IL GIA' = 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO PAOLO BARRAI, ABITAVA A M= ILANO, IN VIA IPPODROMO 105 (ZONA SAN SIRO- CERTOSA). ED IN ZONA SAN SIRO -= CERTOSA, I RAS NDRANGHETISTI ERANO I MEGA ASSASSINI GIULIANO MARTINO, VINC= ENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTI STUPENDI DOCUMENTARI E PROGRAMMI RADIOFONICI: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.rsi.ch/rete-uno/programmi/informazione/modem/Una-mafia-sempre-p= i%C3%B9-4.0-11630989.html AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (gtwrek) Newsgroups: comp.lang.vhdl Subject: Re: Replacing xilinx "ASYNC_REG" directive with a TCL script method. Date: Mon, 15 Jul 2019 21:22:42 -0000 (UTC) Organization: Sonic Lines: 55 Message-ID: References: Injection-Date: Mon, 15 Jul 2019 21:22:42 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="7656107392a68984302b9eacd4226072"; logging-data="5766"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+/wEknYYqbWvWeXnBMcGv3" Cancel-Lock: sha1:zJsYxF+1casoNJWBJCJka8mMJn8= Originator: gtwrek@sonic.net (gtwrek) X-Newsreader: trn 4.0-test77 (Sep 1, 2010) Xref: reader01.eternal-september.org comp.lang.vhdl:9501 In article , Edward Fisher wrote: >Hi all, > >The Xilinx tools allow an attribute called "ASYNC_REG" to be applied to FFs to constrain their placement for clock domain crossing synchroniser FFs. The attribute also ensures that >various optimisations are not applied to these registers (e.g. register balancing etc). > >For a dual flip-flop synchroniser, I could apply the attribute to the two FFs in the VHDL. However the style guide for my current role states that directives are to be avoided (e.g. >DONT_TOUCH, KEEP etc) and instead scripts can be used. This is because such directives may not be portable between synthesis tools (Xilinx, Intel, Mentor etc). > >Question: > - Assuming that we want to use register balancing (retiming) within the design globally. We need some method to prevent this optimisation being applied to the CDC synchroniser >logic. If I can't use the compile directive how could I achieve the same using TCL? > > - If the TCL knew the synthesis route, it could select the correct compile time directive and then boot up the relevant tool (Vivado vs Quartus vs Precision). That way in all cases >the attribute would match the tool. However, after some digging, I cannot find the Intel equivalent of the Xilinx "ASYNC_REG" attribute. I don't have a comment specific to your proposal, but rather just a warning regarding inferring logic with respect to CDC circuits and other similar strategies - i.e. places where you need to use these types of attributes in the first place. Originally, we had the synthesis tool infer our "n-stage" back-to-back synchronizers. We carefully applieid the ASYNC_REG attribute, as you've noted. Further reading, we noticed we needed the "KEEP=true" attribute to prevent synthesis from sharing or otherwise optimizing these circuits. As we always had full register retiming on, we decided that the KEEP_HIERARCHY attribute was needed as well. The SHREG_EXTRACT = "no", also needed to be added to prevent the inferrence of SRLs (which have poor metastability performance). However, after all this when we put a full, and proper CDC checker into our flows, it was still flagging some errors. Reading more, it looks like we needed the DIRECT_ENABLE="yes", and DIRECT_RESET="yes" attributes applied to the module level CE, and RESET ports too. That reduced or CDC LINT flagging even more,... But not to zero. It seems that in Vivador, all these attrbutes are mostly taken by the tools as suggestions only. These last two seem to be the most problematic - Vivado was consistently optimizing the CE, or, RESET circuitry along with any of the other upstream synchronous logic, ignoring our directives, and violating the CDC rules. In the end, we still have all those attributes, set, but we ended up just instanciating the proper flip-flop (Vendor, and sometimes product specific) in our synchronizer module, and hard dont__touching the entire module. Your mileage may vary, etc., but that's our findings. Regards, Mark From newsfish@newsfish Thu Aug 1 00:44:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.usenet.farm!feed.usenet.farm!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!buffer1.nntp.dca1.giganews.com!buffer2.nntp.dca1.giganews.com!nntp.westnet.com.au!news.westnet.com.au.POSTED!not-for-mail NNTP-Posting-Date: Tue, 16 Jul 2019 07:15:20 -0500 From: Allan Herriman Subject: Re: Replacing xilinx "ASYNC_REG" directive with a TCL script method. Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.146 (Hic habitat felicitas; edad96d github.com/GNOME/pan.git) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Tue, 16 Jul 2019 07:15:20 -0500 Lines: 51 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 118.209.94.144 X-Trace: sv3-QlNysqjK7Th65rbKmirvzTJYVCdTPLFB19mDchHTMqQb0UmCj55kzo9xXuNeCTVLLAiDd/QdS+vjT21!fRTSQ9Hxe5+3lH9HQbJ3c818REF1cUgSTQclHPj4HIlQaNcWJbP2tuzwk+f430mnFsxPQfCH64yE!v3JLUG96ZDlOTclMnvOfyQ== X-Complaints-To: abuse@westnet.com.au X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3460 X-Received-Bytes: 3741 X-Received-Body-CRC: 89076988 Xref: reader01.eternal-september.org comp.lang.vhdl:9502 On Mon, 15 Jul 2019 07:32:04 -0700, Edward Fisher wrote: > Hi all, > > The Xilinx tools allow an attribute called "ASYNC_REG" to be applied to FFs to constrain their placement for clock domain crossing synchroniser FFs. The attribute also ensures that various optimisations are not applied to these registers (e.g. register balancing etc). > > For a dual flip-flop synchroniser, I could apply the attribute to the two FFs in the VHDL. However the style guide for my current role states that directives are to be avoided (e.g. DONT_TOUCH, KEEP etc) and instead scripts can be used. This is because such directives may not be portable between synthesis tools (Xilinx, Intel, Mentor etc). > > Question: > - Assuming that we want to use register balancing (retiming) within the design globally. We need some method to prevent this optimisation being applied to the CDC synchroniser logic. If I can't use the compile directive how could I achieve the same using TCL? > > - If the TCL knew the synthesis route, it could select the correct compile time directive and then boot up the relevant tool (Vivado vs Quartus vs Precision). That way in all cases the attribute would match the tool. However, after some digging, I cannot find the Intel equivalent of the Xilinx "ASYNC_REG" attribute. > > Many thanks, > Ed If your style guide doesn't allow you to use vendor-specific attributes in your source, you might be able to work around it by creating your own user-defined attribute (e.g. MY_ASYNC_REG). You can write code / scripts to scan the compiled netlist for this attribute, and convert it to whatever vendor-specific attribute is needed by the vendor's back end tools. I have done something similar in Vivado to generate complicated timing constraints that were completely controlled by HDL source, to avoid the need to keep my HDL and XDC source files aligned. (I eventually dropped the idea because scanning the database for attributes using TCL in Vivado kinda sucks and is exceedingly slow.) BTW, if your style guide actualy stops you from making maintainable designs (e.g. it requires that you have source and attributes for that source in separate files), it's time to get a new style guide. Regards, Alan From newsfish@newsfish Thu Aug 1 00:44:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx35.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Replacing xilinx "ASYNC_REG" directive with a TCL script method. Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190716-2, 16/07/2019), Outbound message X-Antivirus-Status: Clean Lines: 30 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Tue, 16 Jul 2019 18:51:32 UTC Organization: virginmedia.com Date: Tue, 16 Jul 2019 19:51:33 +0100 X-Received-Bytes: 2144 X-Received-Body-CRC: 3736895601 Xref: reader01.eternal-september.org comp.lang.vhdl:9503 On 16/07/2019 13:15, Allan Herriman wrote: > On Mon, 15 Jul 2019 07:32:04 -0700, Edward Fisher wrote: .. snip > > > BTW, if your style guide actualy stops you from making maintainable > designs (e.g. it requires that you have source and attributes for that > source in separate files), it's time to get a new style guide. I suspect he might not have a choice. It would be interested to find out which coding style he must adhere to, probably some high DAL DO-254 standard style. As I mentioned the problem is that RTL attributes are no guarantee for the final bitstream. This is one of the reasons most CDC vendors now offer a gatelevel version as P&R does all sort of clever stuff to make your design fit and achieve timing closure. Add some DFT/BIST and you may have a glitch fest. Every Wilson survey showed that CDC errors are the number 2 reason for designs failing, given the price of formal CDC tools I believe this will continue for a long long time..... Regards, Hans www.ht-lab.com > > Regards, > Alan > From newsfish@newsfish Thu Aug 1 00:44:36 2024 X-Received: by 2002:a05:620a:41:: with SMTP id t1mr31753178qkt.423.1563473903902; Thu, 18 Jul 2019 11:18:23 -0700 (PDT) X-Received: by 2002:a81:678a:: with SMTP id b132mr27855062ywc.96.1563473903624; Thu, 18 Jul 2019 11:18:23 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Thu, 18 Jul 2019 11:18:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.37.126.142; posting-account=FiJOqwoAAABTa9aMB9-1UUgsWPfCZi5j NNTP-Posting-Host: 62.37.126.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b086f2f-d91f-49f1-8938-d9aac0437fe4@googlegroups.com> Subject: =?UTF-8?Q?E=27_DA_ARRESTARE_SUBITO=3A_PAOLO_BARRAI_=28=22IL_PEDOFILO_D?= =?UTF-8?Q?EL_BITCOIN=22=3A_COME_E=27_NOTO_IN_TUTTO_IL_MONDO=29=21_E=27_STATO_IL_RE?= =?UTF-8?Q?GISTA_CRIMINALISSIMO_DELL=27OPERAZIONE_=22EIDOO_21_MLN_DI_=E2=82=AC__M?= =?UTF-8?Q?AFIOSI_PER_LA_NDRANGHETA=22=21_IL_GIA=27_3_VOLTE_FINITO_IN_GALERA=2C?= =?UTF-8?Q?_IL_DELINQUENTE=2E=2E=2E=2E=2E?= From: RICICLASOLDIMAFIOSI PAOLO BARRAI ORDINATANTIOMICID Injection-Date: Thu, 18 Jul 2019 18:18:23 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no742409qtq.0!news-out.google.com!a5ni936qtd.0!nntp.google.com!b26no742405qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9504 E' DA ARRESTARE SUBITO: PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME E' NO= TO IN TUTTO IL MONDO)! E' STATO IL REGISTA CRIMINALISSIMO DELL'OPERAZIONE "= EIDOO 21 MLN DI =E2=82=AC MAFIOSI PER LA NDRANGHETA"! IL GIA' 3 VOLTE FINI= TO IN GALERA, IL DELINQUENTE...................EFFERATO PAOLO BARRAI, ABITA= VA A MILANO, IN VIA IPPODROMO 105 (ZONA SAN SIRO- CERTOSA). ED IN ZONA SAN = SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEGA ASSASSINI GIULIANO MARTINO= , VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTI STUPENDI DOCUMENTARI E PROGRAMMI RADIOFONICI: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.rsi.ch/rete-uno/programmi/informazione/modem/Una-mafia-sempre-p= i%C3%B9-4.0-11630989.html AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:36 2024 X-Received: by 2002:a05:620a:137c:: with SMTP id d28mr39911190qkl.351.1563647268911; Sat, 20 Jul 2019 11:27:48 -0700 (PDT) X-Received: by 2002:a25:404:: with SMTP id 4mr38826666ybe.77.1563647268446; Sat, 20 Jul 2019 11:27:48 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Sat, 20 Jul 2019 11:27:48 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.37.126.142; posting-account=dxdUwwoAAAC9GWVUgihc3u5gmh-STT4K NNTP-Posting-Host: 62.37.126.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72c33142-02e9-4d88-aa11-25b4d179e986@googlegroups.com> Subject: E' DA ARRESTARE: PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME E' NOTO IN TUTTO IL MONDO)! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STUPRA ED UCCIDE BAMBINI. HA RICICLATO CASH ASSASSINO DI NDRANGHETA IN MALAVITOSISSIMA ICO EIDOO!!!!!! From: TIAZZERAIRISPARMI PAOLO BARRAI TRUFFAVIABITCOIN Injection-Date: Sat, 20 Jul 2019 18:27:48 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no7179965qtq.0!news-out.google.com!a5ni1234qtd.0!nntp.google.com!b26no7179963qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9505 E' DA ARRESTARE: PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME E' NOTO IN T= UTTO IL MONDO)! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STU= PRA ED UCCIDE BAMBINI. HA RICICLATO CASH ASSASSINO DI NDRANGHETA IN MALAVIT= OSISSIMA ICO EIDOO!!!!!! E' STATO CACCIATO DA CITIBANK= E FATTO CONDANNARE A GALERA DA CITIBANK! HA FATTO FILM PEDOPORNOGRAFICI, S= TUPRANDO QUASI A MORTE TANTI BAMBINI! HA UCCISO LUI STESSO, TANTI BAMBINI, = PER PRENDER I LORO ORGANI E TRAFFICARLI! HA FATTO FILM PORNO CON CAVALLI, B= EVENDO LITRI DI SPERMA EQUINO! E' STATO MULTATO DA CONSOB BEN 70.000 EURO! = HA 23 CAUSE, CON GENTE DI MEZZA DITTATURA FASCIOMAFIOSA DI BERLUSCONIA, A C= UI HA AZZERATO I RISPARMI! PER SCAPPARE ALLE QUALI, SI E' ORA RIFUGIATO A L= ONDRA, OVE FA TANTI POMPINI AL NAZISTA NIGEL FARAGE ED ALLA MEGA PALLA DI M= ERDA FASCISTOIDE, BORIS JOHNSON, AFFINCHE' I DUE LO PROTEGGANO! E' STATO CO= NDANNATO AL CARCERE IN BRASILE, ANCHE PER PEDERASTIA VIOLENTA ( E PER ALTRI= TANTISSIMI CRIMINI)! NON NE AZZECCA MAI MEZZA UNA IN BORSA, OVE AZZERA I R= ISPARMI DI TUTTI E SEMPRE! E VI E' TANTISSIMO PIU', DI CUI SCRIVEREMO FINO = A 15 MINUTI DOPO LA NOSTRA MORTE!=20 E' DA ARRESTARE IMMEDIATAMENTE: PAOLO BARRAI (CRYPTOPOLIS E CRYPTOLAB)! E' = STATO IL REGISTA CRIMINALISSIMO DELL'OPERAZIONE "EIDOO 21 MLN DI =E2=82=AC = MAFIOSI PER LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUEN= TE EFFERATO PAOLO BARRAI, ABITAVA A MILANO, IN VIA IPPODROMO 105 (ZONA SAN = SIRO- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I = MEGA ASSASSINI GIULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTI STUPENDI DOCUMENTARI E PROGRAMMI RADIOFONICI: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.rsi.ch/rete-uno/programmi/informazione/modem/Una-mafia-sempre-p= i%C3%B9-4.0-11630989.html AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:44:36 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Code Review: SPI Transmitter Date: Wed, 24 Jul 2019 15:54:03 -0700 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <7255ca83-e552-4591-969e-910b23c47e57@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Wed, 24 Jul 2019 22:54:04 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="e8bf0608002d3a0a40a4cd8526dcefc9"; logging-data="791"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/tA2D+Zf+Enap8zHkgBuei" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 Cancel-Lock: sha1:iLR75hX9fkcTu781rEA24Js/6KU= In-Reply-To: Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9506 On 7/1/19 9:49 AM, Rob Gaddi wrote: > On 6/19/19 12:04 PM, KJ wrote:> Why is the 'Bus' clock specified as an integer > frequency in MHz? All of the other time related things are specified as time > units... the same should be done for the clock period. Not to mention I can't > remember the last time I dealt with a clock that had such a nice integer > frequency. Lastly, if you did want to specify frequency it would not be integers > but positives. > > > > A function of how I've done things for a while, back when I couldn't trust the > synthesis tools to handle math on time objects correctly even when it all cooked > down to integers at compile time.  But you're absolutely right, having already > decided that the tools will handle time right the rest of the time, I should > really make that interface consistent.  I haven't yet because whenever I do it > it's going to be a nuisance, but if it'll be a nuisance whenever then the time > to do it is now. > Ah-HA! I'm back into the design now, and I'm remembering why, at least in upper-level code, I use BUS_FREQ_MHZ. It's because system builders like the Vivado IP Integrator, in the interest of playing nicely with Verilog, are so utterly brain-damaged that they're not able to use /time/ as a generic, only /integer/. Because otherwise they might have to actually support VHDL, and god knows we can't have that. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:44:36 2024 X-Received: by 2002:ac8:6619:: with SMTP id c25mr39967664qtp.221.1564404005760; Mon, 29 Jul 2019 05:40:05 -0700 (PDT) X-Received: by 2002:a81:148b:: with SMTP id 133mr66098267ywu.394.1564404005354; Mon, 29 Jul 2019 05:40:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!b26no3263914qtq.0!news-out.google.com!a5ni400qtd.0!nntp.google.com!b26no3263904qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jul 2019 05:40:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=77.224.123.51; posting-account=BnbPYgoAAACV95kJ96RhL11rsub4vLtr NNTP-Posting-Host: 77.224.123.51 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0bab57a2-3e10-4117-ad05-1304b03517a1@googlegroups.com> Subject: SONO PEDOFILI ASSASSINI: IL REGISTA GIUSEPPE LAZZARI DI BRESCIA, IL SATANISTA KILLER DANIELE MINOTTI DEL CRIMINALISSIMO STUDIO LEGALE LISI, LA TROIONA NAZISTA ANSELMA DELL'OLIO ED IL RICCHIONE SEMPRE SBORRATO IN CULO DA RAGAZZINI CHE PAGA ALL'UOPO... From: ORDINA-OMICIDI DANIELE MINOTTI AVVOCATO-SATANAZIST Injection-Date: Mon, 29 Jul 2019 12:40:05 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 36032 X-Received-Body-CRC: 1163460883 Lines: 608 Xref: reader01.eternal-september.org comp.lang.vhdl:9507 SONO PEDOFILI ASSASSINI: IL REGISTA GIUSEPPE LAZZARI DI BRESCIA, IL SATANIS= TA KILLER DANIELE MINOTTI DEL CRIMINALISSIMO STUDIO LEGALE LISI, LA TROIONA= NAZISTA ANSELMA DELL'OLIO ED IL RICCHIONE SEMPRE SBORRATO IN CULO DA RAGAZ= ZINI CHE PAGA ALL'UOPO.........GIULIANO FERRARA! =20 TENETE ALLA LARGA I VOSTRI FIGLI DAL REGISTA PEDOFILO ED ASSASSINO, GIUSEPP= E LAZZARI DI BRESCIA. https://movieplayer.net-cdn.it/images/2009/09/29/una-foto-di-giuseppe-lazza= ri-132273.jpg NOTO COME " IL REGISTA INCULA ED AMMAZZA BAMBINI". PARTECIPO' ALLO STUPRO E= D UCCISIONE DI YARA GAMBIRASIO (EFFETTUATO VICINO A BRESCIA, NON PER NIENTE= ). VENNE ARRESTATO PER AVER INCULATO RAGAZZINI! VENNE ARRESTATO PER AVER IN= CULATO DEI POCO PIU' CHE BAMBINI=20 https://brescia.corriere.it/notizie/cronaca/16_agosto_09/sesso-un-11enne-ar= restato-regista-giuseppe-lazzari-5ff89ba8-5e3b-11e6-bfed-33aa6b5e1635_amp.h= tml=20 E' STATO IL SATANISTA ASSASSINO E SEPPELLITORE DI TANTE PERSONE PER BENE. D= EL BRESCIANO. SCOMPARSE E MAI PIU' RITROVATE ( ERA PARTE ANCORA NON SCOPERT= A, NON PER NIENTE, DELLE BESTIE DI SATANA). COME DA QUESTO SCIOCCANTISSIMO = ARTICOLO! http://www.bresciatoday.it/cronaca/brescia-persone-scomparse.html E' REGISTA ASSASSINO E PEDERASTA: GIUSEPPE LAZZARI DI BRESCIA ( FINITO IN C= ARCERE PER QUESTO https://grupy.scigacz.pl/gt,sprzedam,motocykl Subject: attribute of a record member From: daltonj Injection-Date: Sat, 03 Aug 2019 16:26:15 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9508 I am trying to set an attribute for safe state machine encoding in Synplify. I have a defined all my registers in a record called "registers" and then two signals of type register as shown below. signal r, rin : registers; I added the safe encoding attribute with the following code. attribute syn_encoding: string; attribute syn_encoding of r.sweep_record_sm : signal is "safe"; @E: CD128 :"\path\to\file:277:29:277:29|Expecting : before class of object(s) Line 277:29 is just before the "r" in r.sweep_record_sm Does anyone know why I am getting this error? From newsfish@newsfish Thu Aug 1 00:44:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: attribute of a record member Date: Mon, 5 Aug 2019 09:00:23 -0700 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <024b5b07-7125-4867-b586-2fd38965b0cf@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 5 Aug 2019 16:00:23 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="867e720427d83e7c9cb207b531d51fba"; logging-data="15265"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/XtqQNQkopZJdvhj2Btn+/" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 Cancel-Lock: sha1:k2X/x04DxlMt+s6/vvHnhwoidEI= In-Reply-To: <024b5b07-7125-4867-b586-2fd38965b0cf@googlegroups.com> Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9509 On 8/3/19 9:26 AM, daltonj wrote: > I am trying to set an attribute for safe state machine encoding in Synplify. > I have a defined all my registers in a record called "registers" and then two signals of type register as shown below. > > signal r, rin : registers; > > I added the safe encoding attribute with the following code. > > attribute syn_encoding: string; > attribute syn_encoding of r.sweep_record_sm : signal is "safe"; > > @E: CD128 :"\path\to\file:277:29:277:29|Expecting : before class of object(s) > > Line 277:29 is just before the "r" in r.sweep_record_sm > > Does anyone know why I am getting this error? > I don't believe you can apply an attribute to a member of a record, only to the entire record. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:44:37 2024 X-Received: by 2002:a05:620a:745:: with SMTP id i5mr2512907qki.39.1565384084339; Fri, 09 Aug 2019 13:54:44 -0700 (PDT) X-Received: by 2002:a0d:fc03:: with SMTP id m3mr14495714ywf.428.1565384084109; Fri, 09 Aug 2019 13:54:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!b26no4610973qtq.0!news-out.google.com!y1ni342qtn.0!nntp.google.com!b26no4610963qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Aug 2019 13:54:43 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.33.54.235; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.33.54.235 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Weng Tianxiang Injection-Date: Fri, 09 Aug 2019 20:54:44 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 12 Xref: reader01.eternal-september.org comp.lang.vhdl:9510 Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I need help to understand a puzzle: Merly-type state machine generates outputs which depend on inputs to the state machine and the current states of the state machine, while Moore-type state machine generates outputs which depend only on the current states of the state machine. Am I right if I treat a Merly-type state machine as a Moore-type state machine plus an independent combinational logic which has the same inputs to the state machine and the Moore-type state machine's state outputs? If I am right, why the paper "Automatic synthesis of lower power gated-clock finite state machine" https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss6Jun96pg630.pdf says (p.632, 2nd column, last section) "The knowledge of the state and the input is not sufficient to individuate the conditions when the clock can be stopped." Thank you. Weng From newsfish@newsfish Thu Aug 1 00:44:38 2024 X-Received: by 2002:aed:2b01:: with SMTP id p1mr21211230qtd.33.1565406833316; Fri, 09 Aug 2019 20:13:53 -0700 (PDT) X-Received: by 2002:a25:aae3:: with SMTP id t90mr16140213ybi.319.1565406833013; Fri, 09 Aug 2019 20:13:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!b26no5461063qtq.0!news-out.google.com!y1ni358qtn.0!nntp.google.com!b26no5461060qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Aug 2019 20:13:52 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: KJ Injection-Date: Sat, 10 Aug 2019 03:13:53 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 53 Xref: reader01.eternal-september.org comp.lang.vhdl:9511 On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote: > Why differences between Merly-type and Moore-type clock-gated state machi= nes are important on how to stop clocking?=20 >=20 > I need help to understand a puzzle:=20 >=20 > Merly-type state machine generates outputs which depend on inputs to the = state machine and the current states of the state machine, while Moore-type= state machine generates outputs which depend only on the current states of= the state machine.=20 > Am I right if I treat a Merly-type state machine as a Moore-type state m= achine plus an independent combinational logic which has the same inputs to= the state machine and the Moore-type state machine's state outputs?=20 > If I am right, why the paper "Automatic synthesis of lower power gated-cl= ock finite state machine"=20 > https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss6J= un96pg630.pdf=20 > says (p.632, 2nd column, last section) "The knowledge of the state and th= e input is not sufficient to individuate the conditions when the clock can = be stopped."=20 >=20 > Thank you.=20 >=20 > Weng The writer states their reason a couple of sentences later which I quote "T= he important consequence is that, even if we know that the state is not goi= ng to change, we cannot guarantee that the output will remain constant as w= ell, and therefore we cannot safely stop the clock". The writer then goes = on to refer to an Example 1 and concludes "Unfortunately, we do not have an= y way to know is the output value in the current clock cycle (it could be e= ither 10 or -1". I'm not interested enough to read anymore of this but the writer's Figure 1= does not represent a Mealy state machine. The inputs get registered and t= hen it goes into logic. However, the definition of a Mealy state machine i= s "a Mealy machine is a finite-state machine whose output values are determ= ined both by its current state and the current inputs."...current inputs...= not input delayed by a clock cycle. So in the writer's example, he is correct that for Figure 1, clock gating w= ouldn't work, the outputs would not be correct because the registers on the= inputs would be blocked from reaching the output computation logic. The w= riter's flaw is that Figure 1 is not a Mealy state machine so that any conc= lusions he draws from Figure 1 do not apply to a Mealy state machine. Figu= re 1 may be considered a Luca Benini and Giovanni De Micheli state machine.= ..but not a Mealy state machine. But of course the usefulness of understanding a Benini/De Micheli state mac= hine is about the same as understanding Mealy and Moore state machine (hint= : only important if you're trying to publish some garbage about such a top= ic, but not important if you do any design). Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:38 2024 X-Received: by 2002:a05:6214:110c:: with SMTP id e12mr18092700qvs.126.1565407832631; Fri, 09 Aug 2019 20:30:32 -0700 (PDT) X-Received: by 2002:a5b:4ce:: with SMTP id u14mr15896083ybp.323.1565407832468; Fri, 09 Aug 2019 20:30:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no5494269qtq.0!news-out.google.com!y1ni358qtn.0!nntp.google.com!b26no5494268qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Aug 2019 20:30:32 -0700 (PDT) In-Reply-To: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 10 Aug 2019 03:30:32 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9512 On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote: > > Why differences between Merly-type and Moore-type clock-gated state mac= hines are important on how to stop clocking?=20 > >=20 > > I need help to understand a puzzle:=20 > >=20 > > Merly-type state machine generates outputs which depend on inputs to th= e state machine and the current states of the state machine, while Moore-ty= pe state machine generates outputs which depend only on the current states = of the state machine.=20 > > Am I right if I treat a Merly-type state machine as a Moore-type state= machine plus an independent combinational logic which has the same inputs = to the state machine and the Moore-type state machine's state outputs?=20 > > If I am right, why the paper "Automatic synthesis of lower power gated-= clock finite state machine"=20 > > https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss= 6Jun96pg630.pdf=20 > > says (p.632, 2nd column, last section) "The knowledge of the state and = the input is not sufficient to individuate the conditions when the clock ca= n be stopped."=20 > >=20 > > Thank you.=20 > >=20 > > Weng >=20 > The writer states their reason a couple of sentences later which I quote = "The important consequence is that, even if we know that the state is not g= oing to change, we cannot guarantee that the output will remain constant as= well, and therefore we cannot safely stop the clock". The writer then goe= s on to refer to an Example 1 and concludes "Unfortunately, we do not have = any way to know is the output value in the current clock cycle (it could be= either 10 or -1". >=20 > I'm not interested enough to read anymore of this but the writer's Figure= 1 does not represent a Mealy state machine. The inputs get registered and= then it goes into logic. However, the definition of a Mealy state machine= is "a Mealy machine is a finite-state machine whose output values are dete= rmined both by its current state and the current inputs."...current inputs.= ..not input delayed by a clock cycle. That was my point in reply to this post in another group... sort of. My po= int was that the definition is not clear. Virtually everyone registers the= inputs to prevent erroneous transitions from race conditions in the combin= ational logic. I don't see the inclusion of input registers to be a proble= m. If you look at any state machine diagram for a Mealy FSM, you will find= the outputs are specified on the transitions while the outputs of a Moore = FSM are specified on the states. The transitions don't happen until the cl= ock edge, so it makes sense the outputs don't change until then either.=20 > So in the writer's example, he is correct that for Figure 1, clock gating= wouldn't work, the outputs would not be correct because the registers on t= he inputs would be blocked from reaching the output computation logic. The= writer's flaw is that Figure 1 is not a Mealy state machine so that any co= nclusions he draws from Figure 1 do not apply to a Mealy state machine. Fi= gure 1 may be considered a Luca Benini and Giovanni De Micheli state machin= e...but not a Mealy state machine. Clock gating can work if you don't disable the inputs based on the state ch= anges. The input registers should be enabled based on the inputs changing.= =20 > But of course the usefulness of understanding a Benini/De Micheli state m= achine is about the same as understanding Mealy and Moore state machine (hi= nt: only important if you're trying to publish some garbage about such a t= opic, but not important if you do any design). "Garbage" is a loaded word. Clock gating is not trivial and is essential i= n many devices. I think it is a very important topic.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:38 2024 X-Received: by 2002:a0c:d4d0:: with SMTP id y16mr20580059qvh.191.1565410389700; Fri, 09 Aug 2019 21:13:09 -0700 (PDT) X-Received: by 2002:a25:9203:: with SMTP id b3mr9871527ybo.14.1565410389495; Fri, 09 Aug 2019 21:13:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no5580886qtq.0!news-out.google.com!d29ni174qtg.1!nntp.google.com!b26no5580877qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Aug 2019 21:13:09 -0700 (PDT) In-Reply-To: <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.33.54.235; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.33.54.235 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Weng Tianxiang Injection-Date: Sat, 10 Aug 2019 04:13:09 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9513 On Friday, August 9, 2019 at 8:30:34 PM UTC-7, Rick C wrote: > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote: > > > Why differences between Merly-type and Moore-type clock-gated state m= achines are important on how to stop clocking?=20 > > >=20 > > > I need help to understand a puzzle:=20 > > >=20 > > > Merly-type state machine generates outputs which depend on inputs to = the state machine and the current states of the state machine, while Moore-= type state machine generates outputs which depend only on the current state= s of the state machine.=20 > > > Am I right if I treat a Merly-type state machine as a Moore-type sta= te machine plus an independent combinational logic which has the same input= s to the state machine and the Moore-type state machine's state outputs?=20 > > > If I am right, why the paper "Automatic synthesis of lower power gate= d-clock finite state machine"=20 > > > https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15i= ss6Jun96pg630.pdf=20 > > > says (p.632, 2nd column, last section) "The knowledge of the state an= d the input is not sufficient to individuate the conditions when the clock = can be stopped."=20 > > >=20 > > > Thank you.=20 > > >=20 > > > Weng > >=20 > > The writer states their reason a couple of sentences later which I quot= e "The important consequence is that, even if we know that the state is not= going to change, we cannot guarantee that the output will remain constant = as well, and therefore we cannot safely stop the clock". The writer then g= oes on to refer to an Example 1 and concludes "Unfortunately, we do not hav= e any way to know is the output value in the current clock cycle (it could = be either 10 or -1". > >=20 > > I'm not interested enough to read anymore of this but the writer's Figu= re 1 does not represent a Mealy state machine. The inputs get registered a= nd then it goes into logic. However, the definition of a Mealy state machi= ne is "a Mealy machine is a finite-state machine whose output values are de= termined both by its current state and the current inputs."...current input= s...not input delayed by a clock cycle. >=20 > That was my point in reply to this post in another group... sort of. My = point was that the definition is not clear. Virtually everyone registers t= he inputs to prevent erroneous transitions from race conditions in the comb= inational logic. I don't see the inclusion of input registers to be a prob= lem. If you look at any state machine diagram for a Mealy FSM, you will fi= nd the outputs are specified on the transitions while the outputs of a Moor= e FSM are specified on the states. The transitions don't happen until the = clock edge, so it makes sense the outputs don't change until then either.= =20 >=20 >=20 > > So in the writer's example, he is correct that for Figure 1, clock gati= ng wouldn't work, the outputs would not be correct because the registers on= the inputs would be blocked from reaching the output computation logic. T= he writer's flaw is that Figure 1 is not a Mealy state machine so that any = conclusions he draws from Figure 1 do not apply to a Mealy state machine. = Figure 1 may be considered a Luca Benini and Giovanni De Micheli state mach= ine...but not a Mealy state machine. >=20 > Clock gating can work if you don't disable the inputs based on the state = changes. The input registers should be enabled based on the inputs changin= g.=20 >=20 >=20 > > But of course the usefulness of understanding a Benini/De Micheli state= machine is about the same as understanding Mealy and Moore state machine (= hint: only important if you're trying to publish some garbage about such a= topic, but not important if you do any design). >=20 > "Garbage" is a loaded word. Clock gating is not trivial and is essential= in many devices. I think it is a very important topic.=20 >=20 > --=20 >=20 > Rick C. >=20 > - Get 1,000 miles of free Supercharging > - Tesla referral code - https://ts.la/richard11209 Rick, >Virtually everyone registers the inputs to prevent erroneous transitions f= rom race conditions in the combinational logic. =20 I never do it! All my projects are assumed to work in a global synchronous = system so that outputs from one unit become inputs of next unit without any= additional registers inserted between them. And any race conditions are ex= pected to exist only on the boundary between 2 asynchronous systems.=20 Actually I never pay any attention to whether my state machine is a Merly-t= ype state machine or a Moore-type state machine and I am never worried abou= t whether the inputs are registered or not.=20 KC or Rick, can you list a code example showing that the paper following vi= ew is justified:=20 "The important consequence is that, even if we know that the state is not g= oing to change, we cannot guarantee that the output will remain constant as= well, and therefore we cannot safely stop the clock." I fully agree with Rick's following idea:=20 >Finally, I would submit it is very easy to determine if a FF should be clo= cked or not. Simply compare the D input to the Q output. If they are the = same, gate the clock. If they are different enable the clock. BTW, this e= ffectively turns the D FF into a toggle FF.=20 Both your comments are very appreciated.=20 Thank you. Weng From newsfish@newsfish Thu Aug 1 00:44:38 2024 X-Received: by 2002:a37:85c2:: with SMTP id h185mr22045317qkd.353.1565413854870; Fri, 09 Aug 2019 22:10:54 -0700 (PDT) X-Received: by 2002:a0d:eccd:: with SMTP id v196mr15679852ywe.30.1565413854672; Fri, 09 Aug 2019 22:10:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no5695177qtq.0!news-out.google.com!d29ni174qtg.1!nntp.google.com!b26no5695171qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Aug 2019 22:10:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.33.54.235; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.33.54.235 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <866e71fb-07f5-4822-832c-77dd627c2b80@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Weng Tianxiang Injection-Date: Sat, 10 Aug 2019 05:10:54 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9514 On Friday, August 9, 2019 at 9:13:11 PM UTC-7, Weng Tianxiang wrote: > On Friday, August 9, 2019 at 8:30:34 PM UTC-7, Rick C wrote: > > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote: > > > > Why differences between Merly-type and Moore-type clock-gated state= machines are important on how to stop clocking?=20 > > > >=20 > > > > I need help to understand a puzzle:=20 > > > >=20 > > > > Merly-type state machine generates outputs which depend on inputs t= o the state machine and the current states of the state machine, while Moor= e-type state machine generates outputs which depend only on the current sta= tes of the state machine.=20 > > > > Am I right if I treat a Merly-type state machine as a Moore-type s= tate machine plus an independent combinational logic which has the same inp= uts to the state machine and the Moore-type state machine's state outputs?= =20 > > > > If I am right, why the paper "Automatic synthesis of lower power ga= ted-clock finite state machine"=20 > > > > https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol1= 5iss6Jun96pg630.pdf=20 > > > > says (p.632, 2nd column, last section) "The knowledge of the state = and the input is not sufficient to individuate the conditions when the cloc= k can be stopped."=20 > > > >=20 > > > > Thank you.=20 > > > >=20 > > > > Weng > > >=20 > > > The writer states their reason a couple of sentences later which I qu= ote "The important consequence is that, even if we know that the state is n= ot going to change, we cannot guarantee that the output will remain constan= t as well, and therefore we cannot safely stop the clock". The writer then= goes on to refer to an Example 1 and concludes "Unfortunately, we do not h= ave any way to know is the output value in the current clock cycle (it coul= d be either 10 or -1". > > >=20 > > > I'm not interested enough to read anymore of this but the writer's Fi= gure 1 does not represent a Mealy state machine. The inputs get registered= and then it goes into logic. However, the definition of a Mealy state mac= hine is "a Mealy machine is a finite-state machine whose output values are = determined both by its current state and the current inputs."...current inp= uts...not input delayed by a clock cycle. > >=20 > > That was my point in reply to this post in another group... sort of. M= y point was that the definition is not clear. Virtually everyone registers= the inputs to prevent erroneous transitions from race conditions in the co= mbinational logic. I don't see the inclusion of input registers to be a pr= oblem. If you look at any state machine diagram for a Mealy FSM, you will = find the outputs are specified on the transitions while the outputs of a Mo= ore FSM are specified on the states. The transitions don't happen until th= e clock edge, so it makes sense the outputs don't change until then either.= =20 > >=20 > >=20 > > > So in the writer's example, he is correct that for Figure 1, clock ga= ting wouldn't work, the outputs would not be correct because the registers = on the inputs would be blocked from reaching the output computation logic. = The writer's flaw is that Figure 1 is not a Mealy state machine so that an= y conclusions he draws from Figure 1 do not apply to a Mealy state machine.= Figure 1 may be considered a Luca Benini and Giovanni De Micheli state ma= chine...but not a Mealy state machine. > >=20 > > Clock gating can work if you don't disable the inputs based on the stat= e changes. The input registers should be enabled based on the inputs chang= ing.=20 > >=20 > >=20 > > > But of course the usefulness of understanding a Benini/De Micheli sta= te machine is about the same as understanding Mealy and Moore state machine= (hint: only important if you're trying to publish some garbage about such= a topic, but not important if you do any design). > >=20 > > "Garbage" is a loaded word. Clock gating is not trivial and is essenti= al in many devices. I think it is a very important topic.=20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > - Get 1,000 miles of free Supercharging > > - Tesla referral code - https://ts.la/richard11209 >=20 > Rick, >=20 > >Virtually everyone registers the inputs to prevent erroneous transitions= from race conditions in the combinational logic. =20 >=20 > I never do it! All my projects are assumed to work in a global synchronou= s system so that outputs from one unit become inputs of next unit without a= ny additional registers inserted between them. And any race conditions are = expected to exist only on the boundary between 2 asynchronous systems.=20 >=20 > Actually I never pay any attention to whether my state machine is a Merly= -type state machine or a Moore-type state machine and I am never worried ab= out whether the inputs are registered or not.=20 >=20 > KC or Rick, can you list a code example showing that the paper following = view is justified:=20 >=20 > "The important consequence is that, even if we know that the state is not= going to change, we cannot guarantee that the output will remain constant = as well, and therefore we cannot safely stop the clock." >=20 > I fully agree with Rick's following idea:=20 >=20 > >Finally, I would submit it is very easy to determine if a FF should be c= locked or not. Simply compare the D input to the Q output. If they are th= e same, gate the clock. If they are different enable the clock. BTW, this= effectively turns the D FF into a toggle FF.=20 >=20 > Both your comments are very appreciated.=20 >=20 > Thank you. >=20 > Weng I published the same topic in 3 places, please refer to: https://www.reddit.com/r/FPGA/comments/co8aw5/why_differences_between_merly= type_and_mooretype/ From newsfish@newsfish Thu Aug 1 00:44:39 2024 X-Received: by 2002:ac8:c86:: with SMTP id n6mr9574797qti.345.1565416684778; Fri, 09 Aug 2019 22:58:04 -0700 (PDT) X-Received: by 2002:a25:d68e:: with SMTP id n136mr6629996ybg.133.1565416684534; Fri, 09 Aug 2019 22:58:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no5786838qtq.0!news-out.google.com!d29ni174qtg.1!nntp.google.com!b26no5786834qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Aug 2019 22:58:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 10 Aug 2019 05:58:04 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9515 On Saturday, August 10, 2019 at 12:13:11 AM UTC-4, Weng Tianxiang wrote: > On Friday, August 9, 2019 at 8:30:34 PM UTC-7, Rick C wrote: > > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote: > > > > Why differences between Merly-type and Moore-type clock-gated state= machines are important on how to stop clocking?=20 > > > >=20 > > > > I need help to understand a puzzle:=20 > > > >=20 > > > > Merly-type state machine generates outputs which depend on inputs t= o the state machine and the current states of the state machine, while Moor= e-type state machine generates outputs which depend only on the current sta= tes of the state machine.=20 > > > > Am I right if I treat a Merly-type state machine as a Moore-type s= tate machine plus an independent combinational logic which has the same inp= uts to the state machine and the Moore-type state machine's state outputs?= =20 > > > > If I am right, why the paper "Automatic synthesis of lower power ga= ted-clock finite state machine"=20 > > > > https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol1= 5iss6Jun96pg630.pdf=20 > > > > says (p.632, 2nd column, last section) "The knowledge of the state = and the input is not sufficient to individuate the conditions when the cloc= k can be stopped."=20 > > > >=20 > > > > Thank you.=20 > > > >=20 > > > > Weng > > >=20 > > > The writer states their reason a couple of sentences later which I qu= ote "The important consequence is that, even if we know that the state is n= ot going to change, we cannot guarantee that the output will remain constan= t as well, and therefore we cannot safely stop the clock". The writer then= goes on to refer to an Example 1 and concludes "Unfortunately, we do not h= ave any way to know is the output value in the current clock cycle (it coul= d be either 10 or -1". > > >=20 > > > I'm not interested enough to read anymore of this but the writer's Fi= gure 1 does not represent a Mealy state machine. The inputs get registered= and then it goes into logic. However, the definition of a Mealy state mac= hine is "a Mealy machine is a finite-state machine whose output values are = determined both by its current state and the current inputs."...current inp= uts...not input delayed by a clock cycle. > >=20 > > That was my point in reply to this post in another group... sort of. M= y point was that the definition is not clear. Virtually everyone registers= the inputs to prevent erroneous transitions from race conditions in the co= mbinational logic. I don't see the inclusion of input registers to be a pr= oblem. If you look at any state machine diagram for a Mealy FSM, you will = find the outputs are specified on the transitions while the outputs of a Mo= ore FSM are specified on the states. The transitions don't happen until th= e clock edge, so it makes sense the outputs don't change until then either.= =20 > >=20 > >=20 > > > So in the writer's example, he is correct that for Figure 1, clock ga= ting wouldn't work, the outputs would not be correct because the registers = on the inputs would be blocked from reaching the output computation logic. = The writer's flaw is that Figure 1 is not a Mealy state machine so that an= y conclusions he draws from Figure 1 do not apply to a Mealy state machine.= Figure 1 may be considered a Luca Benini and Giovanni De Micheli state ma= chine...but not a Mealy state machine. > >=20 > > Clock gating can work if you don't disable the inputs based on the stat= e changes. The input registers should be enabled based on the inputs chang= ing.=20 > >=20 > >=20 > > > But of course the usefulness of understanding a Benini/De Micheli sta= te machine is about the same as understanding Mealy and Moore state machine= (hint: only important if you're trying to publish some garbage about such= a topic, but not important if you do any design). > >=20 > > "Garbage" is a loaded word. Clock gating is not trivial and is essenti= al in many devices. I think it is a very important topic.=20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > - Get 1,000 miles of free Supercharging > > - Tesla referral code - https://ts.la/richard11209 >=20 > Rick, >=20 > >Virtually everyone registers the inputs to prevent erroneous transitions= from race conditions in the combinational logic. =20 >=20 > I never do it! All my projects are assumed to work in a global synchronou= s system so that outputs from one unit become inputs of next unit without a= ny additional registers inserted between them. And any race conditions are = expected to exist only on the boundary between 2 asynchronous systems.=20 If your inputs come from logic that is on the same clock then those inputs = are already registered. Of course you don't need to register them again. = Regardless these inputs are registered so the previous analysis applies.=20 > Actually I never pay any attention to whether my state machine is a Merly= -type state machine or a Moore-type state machine and I am never worried ab= out whether the inputs are registered or not.=20 >=20 > KC or Rick, can you list a code example showing that the paper following = view is justified:=20 >=20 > "The important consequence is that, even if we know that the state is not= going to change, we cannot guarantee that the output will remain constant = as well, and therefore we cannot safely stop the clock." I think in my previous post I pointed out that this argument is fallacious.= The only reason outputs would change if the state doesn't is if the input= s change in a way that does not change the state, but does change the outpu= ts. In that case, clock the inputs but do not clock the state. Duh!=20 > I fully agree with Rick's following idea:=20 >=20 > >Finally, I would submit it is very easy to determine if a FF should be c= locked or not. Simply compare the D input to the Q output. If they are th= e same, gate the clock. If they are different enable the clock. BTW, this= effectively turns the D FF into a toggle FF.=20 >=20 > Both your comments are very appreciated.=20 >=20 > Thank you. >=20 > Weng You are welcome.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:39 2024 X-Received: by 2002:ac8:41d7:: with SMTP id o23mr13890064qtm.268.1565444859416; Sat, 10 Aug 2019 06:47:39 -0700 (PDT) X-Received: by 2002:a25:854c:: with SMTP id f12mr18693926ybn.359.1565444859182; Sat, 10 Aug 2019 06:47:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!b26no6804197qtq.0!news-out.google.com!d29ni224qtg.1!nntp.google.com!b26no6804183qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 06:47:38 -0700 (PDT) In-Reply-To: <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: KJ Injection-Date: Sat, 10 Aug 2019 13:47:39 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 54 Xref: reader01.eternal-september.org comp.lang.vhdl:9516 On Friday, August 9, 2019 at 11:30:34 PM UTC-4, Rick C wrote: > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote: > > I'm not interested enough to read anymore of this but the writer's Figu= re 1 does not represent a Mealy state machine. The inputs get registered a= nd then it goes into logic. However, the definition of a Mealy state machi= ne is "a Mealy machine is a finite-state machine whose output values are de= termined both by its current state and the current inputs."...current input= s...not input delayed by a clock cycle. >=20 > That was my point in reply to this post in another group... sort of. My = point was that the definition is not clear. Virtually everyone registers t= he inputs to prevent erroneous transitions from race conditions in the comb= inational logic. No, you would only register on async (or alternative clock domain) inputs w= hich would be in the minority of cases. > I don't see the inclusion of input registers to be a problem. If you lo= ok at any state machine diagram for a Mealy FSM, you will find the outputs = are specified on the transitions while the outputs of a Moore FSM are speci= fied on the states. The 'problem' is that adding the input registers changes it from a Mealy FS= M to something else. The definition of a Mealy state machine is "In the th= eory of computation, a Mealy machine is a finite-state machine whose output= values are determined both by its current state and the current inputs" (s= ee https://en.wikipedia.org/wiki/Mealy_machine). I'm not saying that one wouldn't add input registers if they are needed. I= 'm saying that doing so changes it to longer be a Mealy state machine since= the output is not dependent on the current input. In fact, what those inp= ut registers actually do is change it to a Moore state machine which is def= ined as "This is in contrast to a Moore machine, whose (Moore) output value= s are determined solely by its current state" (same Wiki reference) because= the 'state' would also include those input registers. The output in the w= riter's Figure 1 are logic based on current state which would include the o= utputs of those input registers...a Moore state machine. >=20 >=20 > > But of course the usefulness of understanding a Benini/De Micheli state= machine is about the same as understanding Mealy and Moore state machine (= hint: only important if you're trying to publish some garbage about such a= topic, but not important if you do any design). >=20 > "Garbage" is a loaded word. Clock gating is not trivial and is essential= in many devices. I think it is a very important topic.=20 >=20 > Rick C. >=20 The term 'garbage' is referring to publishing stuff on the topic of Mealy a= nd Moore state machines, not clock gating. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:39 2024 X-Received: by 2002:a37:5445:: with SMTP id i66mr23835259qkb.369.1565446163745; Sat, 10 Aug 2019 07:09:23 -0700 (PDT) X-Received: by 2002:a25:c70c:: with SMTP id w12mr18087940ybe.113.1565446163588; Sat, 10 Aug 2019 07:09:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!b26no6855101qtq.0!news-out.google.com!d29ni224qtg.1!nntp.google.com!b26no6855099qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 07:09:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <09909e5d-a411-4f7c-81b3-926bec7a550b@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: KJ Injection-Date: Sat, 10 Aug 2019 14:09:23 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 34 Xref: reader01.eternal-september.org comp.lang.vhdl:9517 On Saturday, August 10, 2019 at 12:13:11 AM UTC-4, Weng Tianxiang wrote: > On Friday, August 9, 2019 at 8:30:34 PM UTC-7, Rick C wrote: > > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote: > KC or Rick, can you list a code example showing that the paper following = view is justified:=20 >=20 > "The important consequence is that, even if we know that the state is not= going to change, we cannot guarantee that the output will remain constant = as well, and therefore we cannot safely stop the clock." >=20 The statement is flat out wrong. In a Mealy, the outputs can change regard= less of whether there is a state change and therefore the output can change= even if the clock to the state machine stops. That is inherent in the def= inition (previously referenced) of a Mealy state machine. The writer's sta= tement was in the context of Mealy state machines, therefore it is wrong. As I previously posted, the writer produced an example that was *claimed* t= o be a Mealy when in fact it was not because it added registers to the inpu= ts. Claiming something to be true does not in fact make it true. In the wr= iter's example, the output no longer depends on the current input and there= fore it is not a Mealy state machine. Those additional registers are in fa= ct additional states. From that viewpoint, when you look at the writer's e= xample it is actually a Moore state machine where the output depends only o= n current state (which includes those input registers). With a Moore state machine the clock can be stopped if the inputs are in fa= ct not changing but if they are changing the clock must run as well. I'll promptly now forget the distinction between Mealy and Moore since ther= e is no value in retaining such knowledge beyond knowing that these concept= s exist. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:39 2024 X-Received: by 2002:a37:ef1a:: with SMTP id j26mr13637985qkk.474.1565446298988; Sat, 10 Aug 2019 07:11:38 -0700 (PDT) X-Received: by 2002:a25:98c2:: with SMTP id m2mr1657290ybo.438.1565446298844; Sat, 10 Aug 2019 07:11:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no6860318qtq.0!news-out.google.com!d29ni224qtg.1!nntp.google.com!b26no6860313qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 07:11:38 -0700 (PDT) In-Reply-To: <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 10 Aug 2019 14:11:38 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9518 On Saturday, August 10, 2019 at 9:47:41 AM UTC-4, KJ wrote: > On Friday, August 9, 2019 at 11:30:34 PM UTC-4, Rick C wrote: > > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote: > > > I'm not interested enough to read anymore of this but the writer's Fi= gure 1 does not represent a Mealy state machine. The inputs get registered= and then it goes into logic. However, the definition of a Mealy state mac= hine is "a Mealy machine is a finite-state machine whose output values are = determined both by its current state and the current inputs."...current inp= uts...not input delayed by a clock cycle. > >=20 > > That was my point in reply to this post in another group... sort of. M= y point was that the definition is not clear. Virtually everyone registers= the inputs to prevent erroneous transitions from race conditions in the co= mbinational logic. >=20 > No, you would only register on async (or alternative clock domain) inputs= which would be in the minority of cases. As I explained, the only time you don't need to register the inputs is when= they are already registered, i.e. in the same clock domain. =20 > > I don't see the inclusion of input registers to be a problem. If you = look at any state machine diagram for a Mealy FSM, you will find the output= s are specified on the transitions while the outputs of a Moore FSM are spe= cified on the states. >=20 > The 'problem' is that adding the input registers changes it from a Mealy = FSM to something else. The definition of a Mealy state machine is "In the = theory of computation, a Mealy machine is a finite-state machine whose outp= ut values are determined both by its current state and the current inputs" = (see https://en.wikipedia.org/wiki/Mealy_machine). Fine, but that is a theoretical model that is virtually never built other t= han in devices like relay operated soda machines... which they likely don't= make anymore. Inputs to a clocked FSM will be registered if not already s= o. Using the unregistered inputs for the output logic creates a mismatch i= n timing between the outputs and the state.=20 > I'm not saying that one wouldn't add input registers if they are needed. = I'm saying that doing so changes it to longer be a Mealy state machine sin= ce the output is not dependent on the current input. In fact, what those i= nput registers actually do is change it to a Moore state machine which is d= efined as "This is in contrast to a Moore machine, whose (Moore) output val= ues are determined solely by its current state" (same Wiki reference) becau= se the 'state' would also include those input registers. The output in the= writer's Figure 1 are logic based on current state which would include the= outputs of those input registers...a Moore state machine. I think people confuse what is meant by "the current input". There is noth= ing in that statement that indicates the input can not be registered and if= you consider the usage and even the diagrams for Mealy machines, you will = see the output actually is defined by the input *at the time of the state t= ransition*. The output is noted on the transitions in the state diagram. = If the outputs depend on the instantaneous value of the input, the output w= ould change will inputs even when there is no state change which can happen= only because the timing did not coincide with a clock edge. The conventio= nal notation of Mealy machines has no way to indicate that for clocked FSM.= =20 > > > But of course the usefulness of understanding a Benini/De Micheli sta= te machine is about the same as understanding Mealy and Moore state machine= (hint: only important if you're trying to publish some garbage about such= a topic, but not important if you do any design). > >=20 > > "Garbage" is a loaded word. Clock gating is not trivial and is essenti= al in many devices. I think it is a very important topic.=20 > >=20 > > Rick C. > >=20 > The term 'garbage' is referring to publishing stuff on the topic of Mealy= and Moore state machines, not clock gating. Yes, that was obvious.=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:40 2024 X-Received: by 2002:a37:a5d1:: with SMTP id o200mr23624585qke.93.1565446749881; Sat, 10 Aug 2019 07:19:09 -0700 (PDT) X-Received: by 2002:a25:50d1:: with SMTP id e200mr17303750ybb.188.1565446749749; Sat, 10 Aug 2019 07:19:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!b26no6877764qtq.0!news-out.google.com!d29ni224qtg.1!nntp.google.com!b26no6877756qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 07:19:09 -0700 (PDT) In-Reply-To: <09909e5d-a411-4f7c-81b3-926bec7a550b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <09909e5d-a411-4f7c-81b3-926bec7a550b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <741c4227-23d5-46f0-bc29-f5e3db2affc5@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 10 Aug 2019 14:19:09 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 62 Xref: reader01.eternal-september.org comp.lang.vhdl:9519 On Saturday, August 10, 2019 at 10:09:25 AM UTC-4, KJ wrote: > On Saturday, August 10, 2019 at 12:13:11 AM UTC-4, Weng Tianxiang wrote: > > On Friday, August 9, 2019 at 8:30:34 PM UTC-7, Rick C wrote: > > > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wrote= : >=20 > > KC or Rick, can you list a code example showing that the paper followin= g view is justified:=20 > >=20 > > "The important consequence is that, even if we know that the state is n= ot going to change, we cannot guarantee that the output will remain constan= t as well, and therefore we cannot safely stop the clock." > >=20 >=20 > The statement is flat out wrong. In a Mealy, the outputs can change rega= rdless of whether there is a state change and therefore the output can chan= ge even if the clock to the state machine stops. That is inherent in the d= efinition (previously referenced) of a Mealy state machine. The writer's s= tatement was in the context of Mealy state machines, therefore it is wrong. I can logically prove you are not seeing this correctly. If a Mealy FSM is= intended to have outputs change from changes in inputs when there is no cl= ock input (regardless of whether it is because of timing or the absence of = a clock) there is no way it could be equivalent to a Moore FSM in a clocked= FSM design.=20 There are any number of proofs available that will show you how to convert = any Mealy FSM to a Moore FSM. Ergo the Mealy outputs must only change when= clocked. Registering the inputs accomplishes this and precludes the probl= em you describe of outputs changing between clocks.=20 > As I previously posted, the writer produced an example that was *claimed*= to be a Mealy when in fact it was not because it added registers to the in= puts. Claiming something to be true does not in fact make it true. In the = writer's example, the output no longer depends on the current input and the= refore it is not a Mealy state machine. Those additional registers are in = fact additional states. From that viewpoint, when you look at the writer's= example it is actually a Moore state machine where the output depends only= on current state (which includes those input registers). Registering inputs does not preclude the designation of it being a Mealy FS= M.=20 > With a Moore state machine the clock can be stopped if the inputs are in = fact not changing but if they are changing the clock must run as well. >=20 > I'll promptly now forget the distinction between Mealy and Moore since th= ere is no value in retaining such knowledge beyond knowing that these conce= pts exist. Except that they are equivalent and conversions can be made between any suc= h designs.=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:40 2024 X-Received: by 2002:ac8:23cc:: with SMTP id r12mr19595717qtr.241.1565454857587; Sat, 10 Aug 2019 09:34:17 -0700 (PDT) X-Received: by 2002:a0d:e8cb:: with SMTP id r194mr2344446ywe.96.1565454857386; Sat, 10 Aug 2019 09:34:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no7206120qtq.0!news-out.google.com!d29ni232qtg.1!nntp.google.com!b26no7206119qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 09:34:16 -0700 (PDT) In-Reply-To: <741c4227-23d5-46f0-bc29-f5e3db2affc5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <09909e5d-a411-4f7c-81b3-926bec7a550b@googlegroups.com> <741c4227-23d5-46f0-bc29-f5e3db2affc5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: KJ Injection-Date: Sat, 10 Aug 2019 16:34:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9520 On Saturday, August 10, 2019 at 10:19:11 AM UTC-4, Rick C wrote: > On Saturday, August 10, 2019 at 10:09:25 AM UTC-4, KJ wrote: > > On Saturday, August 10, 2019 at 12:13:11 AM UTC-4, Weng Tianxiang wrote= : > > > On Friday, August 9, 2019 at 8:30:34 PM UTC-7, Rick C wrote: > > > > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > > > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang wro= te: >=20 > If a Mealy FSM is intended to have outputs change from changes in inputs = when there is no clock input (regardless of whether it is because of timing= or the absence of a clock) there is no way it could be equivalent to a Moo= re FSM in a clocked FSM design.=20 You should re-read the definition of a Mealy state machine. >=20 > There are any number of proofs available that will show you how to conver= t any Mealy FSM to a Moore FSM. Ergo the Mealy outputs must only change wh= en clocked. Registering the inputs accomplishes this and precludes the pro= blem you describe of outputs changing between clocks.=20 Whether or not one form can be converted to the other is not relevant. Onc= e a state machine is 'converted' from Mealy to Moore it is no longer Mealy = even though the two forms are functionally equivalent. >=20 > > As I previously posted, the writer produced an example that was *claime= d* to be a Mealy when in fact it was not because it added registers to the = inputs. Claiming something to be true does not in fact make it true. In th= e writer's example, the output no longer depends on the current input and t= herefore it is not a Mealy state machine. Those additional registers are i= n fact additional states. From that viewpoint, when you look at the writer= 's example it is actually a Moore state machine where the output depends on= ly on current state (which includes those input registers). >=20 > Registering inputs does not preclude the designation of it being a Mealy = FSM.=20 >=20 Re-read the definition of a Mealy state machine paying attention to the par= t about 'current inputs'. >=20 > > With a Moore state machine the clock can be stopped if the inputs are i= n fact not changing but if they are changing the clock must run as well. > >=20 > > I'll promptly now forget the distinction between Mealy and Moore since = there is no value in retaining such knowledge beyond knowing that these con= cepts exist. >=20 > Except that they are equivalent and conversions can be made between any s= uch designs.=20 >=20 Functionally equivalent does not mean the identical. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:44:40 2024 X-Received: by 2002:a37:ad04:: with SMTP id f4mr6959929qkm.144.1565455640325; Sat, 10 Aug 2019 09:47:20 -0700 (PDT) X-Received: by 2002:a0d:d752:: with SMTP id z79mr14250536ywd.53.1565455640164; Sat, 10 Aug 2019 09:47:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!b26no7238062qtq.0!news-out.google.com!d29ni232qtg.1!nntp.google.com!b26no7238060qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 09:47:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <09909e5d-a411-4f7c-81b3-926bec7a550b@googlegroups.com> <741c4227-23d5-46f0-bc29-f5e3db2affc5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 10 Aug 2019 16:47:20 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 80 Xref: reader01.eternal-september.org comp.lang.vhdl:9521 On Saturday, August 10, 2019 at 12:34:19 PM UTC-4, KJ wrote: > On Saturday, August 10, 2019 at 10:19:11 AM UTC-4, Rick C wrote: > > On Saturday, August 10, 2019 at 10:09:25 AM UTC-4, KJ wrote: > > > On Saturday, August 10, 2019 at 12:13:11 AM UTC-4, Weng Tianxiang wro= te: > > > > On Friday, August 9, 2019 at 8:30:34 PM UTC-7, Rick C wrote: > > > > > On Friday, August 9, 2019 at 11:13:54 PM UTC-4, KJ wrote: > > > > > > On Friday, August 9, 2019 at 4:54:45 PM UTC-4, Weng Tianxiang w= rote: > >=20 > > If a Mealy FSM is intended to have outputs change from changes in input= s when there is no clock input (regardless of whether it is because of timi= ng or the absence of a clock) there is no way it could be equivalent to a M= oore FSM in a clocked FSM design.=20 >=20 > You should re-read the definition of a Mealy state machine. > >=20 > > There are any number of proofs available that will show you how to conv= ert any Mealy FSM to a Moore FSM. Ergo the Mealy outputs must only change = when clocked. Registering the inputs accomplishes this and precludes the p= roblem you describe of outputs changing between clocks.=20 >=20 > Whether or not one form can be converted to the other is not relevant. O= nce a state machine is 'converted' from Mealy to Moore it is no longer Meal= y even though the two forms are functionally equivalent. >=20 > >=20 > > > As I previously posted, the writer produced an example that was *clai= med* to be a Mealy when in fact it was not because it added registers to th= e inputs. Claiming something to be true does not in fact make it true. In = the writer's example, the output no longer depends on the current input and= therefore it is not a Mealy state machine. Those additional registers are= in fact additional states. From that viewpoint, when you look at the writ= er's example it is actually a Moore state machine where the output depends = only on current state (which includes those input registers). > >=20 > > Registering inputs does not preclude the designation of it being a Meal= y FSM.=20 > >=20 >=20 > Re-read the definition of a Mealy state machine paying attention to the p= art about 'current inputs'. >=20 > >=20 > > > With a Moore state machine the clock can be stopped if the inputs are= in fact not changing but if they are changing the clock must run as well. > > >=20 > > > I'll promptly now forget the distinction between Mealy and Moore sinc= e there is no value in retaining such knowledge beyond knowing that these c= oncepts exist. > >=20 > > Except that they are equivalent and conversions can be made between any= such designs.=20 > >=20 >=20 > Functionally equivalent does not mean the identical. This issue is entirely about what is meant by "current" input. You seem to= think this requires purely combinational logic between the inputs and outp= uts. I don't see that the word "current" requires that. "Current" can eas= ily mean the input present at the time of the clock in a design that is clo= cked since that is the nature of "time" in a synchronous system. By the sa= me argument I could reject the use of combinational logic since the output = is rather delayed from the input and so is not always reflecting the state = of the inputs. The issue of the conversion of a Mealy FSM to a Moore FSM i= s that they are equivalent. That is mathematically proven and shown in man= y text books. How could that be if there are fundamental differences in th= e logic?=20 I know nothing I say will matter to you. I believe we have had similar con= versations before. You toss my argument by sticking to an unsupportable po= sition on the definition of "current". I give what is essentially a mathem= atical proof and you reject that as somehow not being relevant. Ok. I can= 't do any more if you reject the facts.=20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:40 2024 X-Received: by 2002:ac8:2622:: with SMTP id u31mr17976010qtu.211.1565464884502; Sat, 10 Aug 2019 12:21:24 -0700 (PDT) X-Received: by 2002:a25:bd87:: with SMTP id f7mr17751404ybh.143.1565464884274; Sat, 10 Aug 2019 12:21:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no7614080qtq.0!news-out.google.com!d29ni243qtg.1!nntp.google.com!b26no7614067qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 12:21:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <09909e5d-a411-4f7c-81b3-926bec7a550b@googlegroups.com> <741c4227-23d5-46f0-bc29-f5e3db2affc5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c359473-94b2-4520-81ff-5baa2079903d@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: KJ Injection-Date: Sat, 10 Aug 2019 19:21:24 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9522 On Saturday, August 10, 2019 at 12:47:21 PM UTC-4, Rick C wrote: > This issue is entirely about what is meant by "current" input. You seem = to think this requires purely combinational logic between the inputs and ou= tputs. Find and read the definition of a Mealy state machine...there is no 'issue'= about what is meant by 'current'. But feel free to research that word as = well. > "Current" can easily mean the input present at the time of the clock in a= design that is clocked since that is the nature of "time" in a synchronous= system. The OP topic was about a Mealy state machine. Try to stay on topic. Find = and read the definition of a Mealy state machine. Read the paper that Weng= was questioning. > The issue of the conversion of a Mealy FSM to a Moore FSM is that they ar= e equivalent. =20 Conversion is not the 'issue', the OP posed a question based on a statement= from the author regarding Mealy state machines. You keep taking the tange= nts. > That is mathematically proven and shown in many text books. How could th= at be if there are fundamental differences in the logic?=20 I never said that there were functional differences. The conversion betwee= n Mealy and Moore just isn't relevant to what the OP questioned. You are o= n that tangent, not me. >=20 > I know nothing I say will matter to you. I believe we have had similar c= onversations before. You toss my argument by sticking to an unsupportable = position on the definition of "current". I stayed on topic, you veer off in other directions. I used accepted defin= itions of Mealy/Moore and posted my reference. You on the other hand just = make off-topic comments and you do not post any supporting references...but= that's your choice, that's the way you have rolled in the past and are doi= ng so again. > I give what is essentially a mathematical proof and you reject that as so= mehow not being relevant. Ok. I can't do any more if you reject the facts= .=20 HAHAHAHAHA...you gave no proof of anything. Maybe you should research what= would go into a proof. My point with you is that your postings about bein= g able to convert between Mealy and Moore are not relevant to Weng's questi= on about a comment that a student writer made 23 years ago in a section of = a paper that was discussing a Mealy state machine. Anyway, I'm done with your off topic tangents on this thread. Til we clash= (or agree) again...we sometimes do agree. Kevin From newsfish@newsfish Thu Aug 1 00:44:41 2024 X-Received: by 2002:ac8:c86:: with SMTP id n6mr12134515qti.345.1565466658528; Sat, 10 Aug 2019 12:50:58 -0700 (PDT) X-Received: by 2002:a0d:fc03:: with SMTP id m3mr17538467ywf.428.1565466658360; Sat, 10 Aug 2019 12:50:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no7685504qtq.0!news-out.google.com!d29ni243qtg.1!nntp.google.com!b26no7685493qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 12:50:58 -0700 (PDT) In-Reply-To: <8c359473-94b2-4520-81ff-5baa2079903d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.86.49.10; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 72.86.49.10 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <09909e5d-a411-4f7c-81b3-926bec7a550b@googlegroups.com> <741c4227-23d5-46f0-bc29-f5e3db2affc5@googlegroups.com> <8c359473-94b2-4520-81ff-5baa2079903d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 10 Aug 2019 19:50:58 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9523 On Saturday, August 10, 2019 at 3:21:26 PM UTC-4, KJ wrote: >=20 > HAHAHAHAHA...you gave no proof of anything. Maybe you should research wh= at would go into a proof. My point with you is that your postings about be= ing able to convert between Mealy and Moore are not relevant to Weng's ques= tion about a comment that a student writer made 23 years ago in a section o= f a paper that was discussing a Mealy state machine. >=20 > Anyway, I'm done with your off topic tangents on this thread. Til we cla= sh (or agree) again...we sometimes do agree. >=20 > Kevin Yes, this is exactly what I expected. You reject the entire community. =20 You say it is irrelevant if the two types of FSM equivalent and yet you the= n try to they aren't. Obviously it is relevant because you are concerned a= bout the issue. Look it up. Any Mealy FSM can be represented by an equiva= lent Moore FSM. If the outputs of a Mealy FSM could change without being c= locked that would not be true. =20 QED=20 OK, that should be enough to convince anyone but the most stubborn, fact d= enialist. =20 --=20 Rick C. ++ Get 1,000 miles of free Supercharging ++ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? Date: Sat, 10 Aug 2019 15:23:47 -0500 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 10 Aug 2019 20:23:51 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="4b7642a8b7867f60003355306fb701b9"; logging-data="31909"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Ay3lLhcz7CS7RXhCZc/4iWQXunL4PFxI=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:cEbSxtgEaQ6+rHjg/PxtO382ovM= In-Reply-To: <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> Xref: reader01.eternal-september.org comp.lang.vhdl:9524 On 2019-08-10 08:47, KJ wrote: > > The 'problem' is that adding the input registers changes it from a Mealy FSM to something else. The definition of a Mealy state machine is "In the theory of computation, a Mealy machine is a finite-state machine whose output values are determined both by its current state and the current inputs" (see https://en.wikipedia.org/wiki/Mealy_machine). > > I'm not saying that one wouldn't add input registers if they are needed. I'm saying that doing so changes it to longer be a Mealy state machine since the output is not dependent on the current input. In fact, what those input registers actually do is change it to a Moore state machine which is defined as "This is in contrast to a Moore machine, whose (Moore) output values are determined solely by its current state" (same Wiki reference) because the 'state' would also include those input registers. The output in the writer's Figure 1 are logic based on current state which would include the outputs of those input registers...a Moore state machine. > I agree. "Current" means "right now", not at some previous time. If we register the inputs then we have a state machine that would be defined as "An FSM whose output values are determined both by its current state and the input values from the previous clock cycle." Of course if you redraw the boundaries of what is included in "the machine" so that its inputs are now defined to be the outputs from the input latches then this redrawn machine once again becomes a Mealy machine. Charles Bailey From newsfish@newsfish Thu Aug 1 00:44:41 2024 X-Received: by 2002:ac8:24b8:: with SMTP id s53mr24647360qts.276.1565474402815; Sat, 10 Aug 2019 15:00:02 -0700 (PDT) X-Received: by 2002:a25:c70c:: with SMTP id w12mr19226189ybe.113.1565474402627; Sat, 10 Aug 2019 15:00:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no7992407qtq.0!news-out.google.com!d29ni284qtg.1!nntp.google.com!b26no7992399qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 15:00:02 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.86.49.10; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 72.86.49.10 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 10 Aug 2019 22:00:02 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9525 On Saturday, August 10, 2019 at 4:23:53 PM UTC-4, Charles Bailey wrote: > On 2019-08-10 08:47, KJ wrote: > > > > The 'problem' is that adding the input registers changes it from a Meal= y FSM to something else. The definition of a Mealy state machine is "In th= e theory of computation, a Mealy machine is a finite-state machine whose ou= tput values are determined both by its current state and the current inputs= " (see https://en.wikipedia.org/wiki/Mealy_machine). > > > > I'm not saying that one wouldn't add input registers if they are needed= . I'm saying that doing so changes it to longer be a Mealy state machine s= ince the output is not dependent on the current input. In fact, what those= input registers actually do is change it to a Moore state machine which is= defined as "This is in contrast to a Moore machine, whose (Moore) output v= alues are determined solely by its current state" (same Wiki reference) bec= ause the 'state' would also include those input registers. The output in t= he writer's Figure 1 are logic based on current state which would include t= he outputs of those input registers...a Moore state machine. > > > I agree. "Current" means "right now", not at some previous time. If we= =20 > register the inputs then we have a state machine that would be defined=20 > as "An FSM whose output values are determined both by its current state= =20 > and the input values from the previous clock cycle." Of course if you=20 > redraw the boundaries of what is included in "the machine" so that its=20 > inputs are now defined to be the outputs from the input latches then=20 > this redrawn machine once again becomes a Mealy machine. I did a bit of reading and I did find sources that literally say the output= s change other than at the clock cycles. But that is not terribly importan= t since in the sort of applications the OP is considering there are no inpu= ts that are truly asynchronous. Even if an input is from another clock dom= ain or is input to the device and so asynchronous, it will be synchronized = with the FSM clock and so no longer async and this synchronized signal is t= he input to the FSM. =20 Probably more significant is the fact that it is not important to the discu= ssion. The authors are talking about gating the clock to FSMs to save powe= r. The state registers in a Mealy FSM work the same as the registers in a = Moore FSM. So they incorrectly conclude something different must be done i= n a Mealy machine. I don't get why a simple XOR gate with inputs from the = Q and D signals on the FF can't be used? =20 It doesn't matter what you call the FSM. In virtually all digital logic th= e inputs will be operating in the same clock domain by the time they reach = the state machine. I think the authors' bigger error is faulty thinking of= how clocks can be gated. They also calculate "improvement" very oddly, th= e delta divided by the lower power so it can be more than 100%. Go figure.= .. =20 --=20 Rick C. --- Get 1,000 miles of free Supercharging --- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:42 2024 X-Received: by 2002:a0c:b998:: with SMTP id v24mr24545112qvf.132.1565476370137; Sat, 10 Aug 2019 15:32:50 -0700 (PDT) X-Received: by 2002:a0d:cec5:: with SMTP id q188mr17699881ywd.90.1565476369997; Sat, 10 Aug 2019 15:32:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!b26no8068168qtq.0!news-out.google.com!d29ni288qtg.1!nntp.google.com!b26no8068167qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 15:32:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.86.49.10; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 72.86.49.10 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <562a48f4-dc56-454a-8043-8ddf34559240@googlegroups.com> Subject: Codewright Setup Files From: Rick C Injection-Date: Sat, 10 Aug 2019 22:32:50 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 9 Xref: reader01.eternal-september.org comp.lang.vhdl:9526 I managed to get Codewright to run on my system again. I'm slowly getting it set up for the work I do. I can't find the language specific codesense files for Forth or VHDL. Anyone have these? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx27.iad.POSTED!not-for-mail Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? Newsgroups: comp.lang.vhdl References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> From: Richard Damon User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 56 Message-ID: X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Sat, 10 Aug 2019 20:47:32 -0400 X-Received-Bytes: 3866 X-Received-Body-CRC: 1879363937 Xref: reader01.eternal-september.org comp.lang.vhdl:9527 I think a big problem with this discussion is there seems to be two different definition of the Mealy machine. What I learned was that, given input I, and state S, and output O that a Moore machine had the description: (S' indicates S on next clock, f & g are pure combinatorial functions) S' = f(S, I) O = g(S) and a Mealy machine was S' = f(S, I) O = g(S, I) Note that in both cases, O is a pure combinatorial function of some signals. On the state diagram, the Moore machine puts the output values on the states, and the Mealy puts them on the arcs. It seems, some want to define Mealy as instead, O' = g(S, I) i.e, the outputs specified doesn't happen until the clock that updates the state, i.e. the arcs aren't specifying the CURRENT output, but the NEXT output. A key factor that this definition defies is that in the classic definition, you can determine how much 'state' is in the system by the size of S (and how you encode it) and that determines how many registers you need. This modified definition effectively has added 1 bit of state for every output, and of course for that definition, you can always convert it, as you are just playing name games of which bits are 'state' and which are 'output' With the classic definition, the distinction between a machine defined by the Mealy method (on the arcs) or the Moore method (on the states) in that there are a number of basic properties that can be easily determined for Moore machines, as they are relatively isolated from each other, and thus you can compute the speed of a system of Moore machines only needing to deal with a given machine and the machines that feed it. With the Mealy machine, because of the 'shoot through' of signals, you need to look at much more of the system. With Moore machines, you can, by re-encoding the states, convert g(S) into a simple selection of state bits, and then the output is available immediately (well, one clk->q delay, the delay ALL signals have) after the clock, and each machine can be computed totally independent of the other machines. (assuming a uniform clock in the system, if you have multiple clock domains, you need to do special analysis to take those issue into account, which is beyond the theory in Mealy/Moore machines). Generally, the flip-flops that are needed to synchronize signals not of the current machines clock domain are NOT considered part of the machine, as those ffs really need the multi-domain analysis. From newsfish@newsfish Thu Aug 1 00:44:42 2024 X-Received: by 2002:ac8:e45:: with SMTP id j5mr11979592qti.149.1565488127365; Sat, 10 Aug 2019 18:48:47 -0700 (PDT) X-Received: by 2002:a81:7dc3:: with SMTP id y186mr15401555ywc.223.1565488127197; Sat, 10 Aug 2019 18:48:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no8492923qtq.0!news-out.google.com!d29ni293qtg.1!nntp.google.com!b26no8492918qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2019 18:48:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sun, 11 Aug 2019 01:48:47 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9528 On Saturday, August 10, 2019 at 8:47:35 PM UTC-4, Richard Damon wrote: > I think a big problem with this discussion is there seems to be two > different definition of the Mealy machine. >=20 > What I learned was that, given input I, and state S, and output O that a > Moore machine had the description: (S' indicates S on next clock, f & g > are pure combinatorial functions) >=20 > S' =3D f(S, I) > O =3D g(S) >=20 > and a Mealy machine was >=20 > S' =3D f(S, I) > O =3D g(S, I) >=20 > Note that in both cases, O is a pure combinatorial function of some signa= ls. >=20 > On the state diagram, the Moore machine puts the output values on the > states, and the Mealy puts them on the arcs. >=20 > It seems, some want to define Mealy as instead, >=20 > O' =3D g(S, I) >=20 > i.e, the outputs specified doesn't happen until the clock that updates > the state, i.e. the arcs aren't specifying the CURRENT output, but the > NEXT output. That's not really the issue. I don't think anyone is suggesting the output= s must be registered in a Mealy machine. If I said that, I was mistaken. = The issue at hand is whether the inputs change between state transitions in= useful systems. =20 > A key factor that this definition defies is that in the classic > definition, you can determine how much 'state' is in the system by the > size of S (and how you encode it) and that determines how many registers > you need. This modified definition effectively has added 1 bit of state > for every output, and of course for that definition, you can always > convert it, as you are just playing name games of which bits are 'state' > and which are 'output' I don't know about 1 bit of state for every bit of output. But yes, that i= s why you can convert a Mealy FSM into a Moore FSM, they are be equivalent.= But this is only valid if the inputs and outputs are considered at the cl= ocking points. =20 > With the classic definition, the distinction between a machine defined > by the Mealy method (on the arcs) or the Moore method (on the states) in > that there are a number of basic properties that can be easily > determined for Moore machines, as they are relatively isolated from each > other, and thus you can compute the speed of a system of Moore machines > only needing to deal with a given machine and the machines that feed it. > With the Mealy machine, because of the 'shoot through' of signals, you > need to look at much more of the system. If you are coupling FSMs, this "shoot through" you mentions is really input= s to the second Mealy FSM for some odd reason being run through logic of th= e first Mealy FSM. If you were to move any of those output logic functions= to the second machine both machines could be made Moore with no other chan= ges... well, if you ignore the async logic feeding outputs of the second Me= aly FSM, lol. But that logic is just logic and can easily be elsewhere.=20 I'm not trying to mess with anyone here. I'm just batting this around in m= y brain. In reality the attachments of outputs to transitions in a Mealy F= SM graph makes no sense unless the output is accompanied by a state transit= ion. If the state transition is not required to change outputs in a Mealy = machine, that type of directed graph and in fact any that I have seen does = not properly represent a Mealy FSM with inputs changing without state trans= itions and impacting the outputs at times other than state transitions. =20 I did some work with async state machines once. An async Mealy FSM can be = properly represented by the Mealy FSM graph while a sync Mealy FSM can't.= =20 > With Moore machines, you can, by re-encoding the states, convert g(S) > into a simple selection of state bits, and then the output is available > immediately (well, one clk->q delay, the delay ALL signals have) after > the clock, and each machine can be computed totally independent of the > other machines. (assuming a uniform clock in the system, if you have > multiple clock domains, you need to do special analysis to take those > issue into account, which is beyond the theory in Mealy/Moore machines). >=20 > Generally, the flip-flops that are needed to synchronize signals not of > the current machines clock domain are NOT considered part of the > machine, as those ffs really need the multi-domain analysis. Indeed. =20 --=20 Rick C. --+ Get 1,000 miles of free Supercharging --+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:43 2024 X-Received: by 2002:a0c:db88:: with SMTP id m8mr7856484qvk.143.1565553681055; Sun, 11 Aug 2019 13:01:21 -0700 (PDT) X-Received: by 2002:a25:b84a:: with SMTP id b10mr21095097ybm.144.1565553680831; Sun, 11 Aug 2019 13:01:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no11104805qtq.0!news-out.google.com!d29ni1097qtg.1!nntp.google.com!b26no11104802qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 Aug 2019 13:01:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.33.35.191; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.33.35.191 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Weng Tianxiang Injection-Date: Sun, 11 Aug 2019 20:01:21 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9529 On Saturday, August 10, 2019 at 5:47:35 PM UTC-7, Richard Damon wrote: > I think a big problem with this discussion is there seems to be two > different definition of the Mealy machine. > > What I learned was that, given input I, and state S, and output O that a > Moore machine had the description: (S' indicates S on next clock, f & g > are pure combinatorial functions) > > S' = f(S, I) > O = g(S) > > and a Mealy machine was > > S' = f(S, I) > O = g(S, I) > > Note that in both cases, O is a pure combinatorial function of some signals. > > On the state diagram, the Moore machine puts the output values on the > states, and the Mealy puts them on the arcs. > > It seems, some want to define Mealy as instead, > > O' = g(S, I) > > i.e, the outputs specified doesn't happen until the clock that updates > the state, i.e. the arcs aren't specifying the CURRENT output, but the > NEXT output. > > A key factor that this definition defies is that in the classic > definition, you can determine how much 'state' is in the system by the > size of S (and how you encode it) and that determines how many registers > you need. This modified definition effectively has added 1 bit of state > for every output, and of course for that definition, you can always > convert it, as you are just playing name games of which bits are 'state' > and which are 'output' > > With the classic definition, the distinction between a machine defined > by the Mealy method (on the arcs) or the Moore method (on the states) in > that there are a number of basic properties that can be easily > determined for Moore machines, as they are relatively isolated from each > other, and thus you can compute the speed of a system of Moore machines > only needing to deal with a given machine and the machines that feed it. > With the Mealy machine, because of the 'shoot through' of signals, you > need to look at much more of the system. > > With Moore machines, you can, by re-encoding the states, convert g(S) > into a simple selection of state bits, and then the output is available > immediately (well, one clk->q delay, the delay ALL signals have) after > the clock, and each machine can be computed totally independent of the > other machines. (assuming a uniform clock in the system, if you have > multiple clock domains, you need to do special analysis to take those > issue into account, which is beyond the theory in Mealy/Moore machines). > > Generally, the flip-flops that are needed to synchronize signals not of > the current machines clock domain are NOT considered part of the > machine, as those ffs really need the multi-domain analysis. Richard, >With the classic definition, the distinction between a machine defined by the Mealy method (ON THE ARCS) or the Moore method (on the states) My explanation for (ON THE ARCS) is that the input is STABLE ONLY ON the edge (setup time plus hold time), not because an output is registered by a register. Weng From newsfish@newsfish Thu Aug 1 00:44:43 2024 X-Received: by 2002:a37:6392:: with SMTP id x140mr20138268qkb.114.1565557006321; Sun, 11 Aug 2019 13:56:46 -0700 (PDT) X-Received: by 2002:a0d:c685:: with SMTP id i127mr20322196ywd.366.1565557006182; Sun, 11 Aug 2019 13:56:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no11236056qtq.0!news-out.google.com!d29ni1101qtg.1!nntp.google.com!b26no11236046qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 Aug 2019 13:56:45 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sun, 11 Aug 2019 20:56:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9530 On Sunday, August 11, 2019 at 4:01:22 PM UTC-4, Weng Tianxiang wrote: > On Saturday, August 10, 2019 at 5:47:35 PM UTC-7, Richard Damon wrote: >=20 > Richard, > >With the classic definition, the distinction between a machine defined b= y the Mealy method (ON THE ARCS) or the Moore method (on the states) >=20 > My explanation for (ON THE ARCS) is that the input is STABLE ONLY ON the = edge (setup time plus hold time), not because an output is registered by a = register. The problem is everyone has their own interpretation of what a Mealy machin= e is. So in the end "it means just what I choose it to mean=E2=80=94neithe= r more nor less." Apologies to Lewis Carrol. Discussing FSM always seems= to end up in Humpty Dumpty speak.=20 --=20 Rick C. -+- Get 1,000 miles of free Supercharging -+- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:43 2024 X-Received: by 2002:ac8:46cc:: with SMTP id h12mr15404944qto.234.1565558655624; Sun, 11 Aug 2019 14:24:15 -0700 (PDT) X-Received: by 2002:a0d:cec5:: with SMTP id q188mr20157799ywd.90.1565558655449; Sun, 11 Aug 2019 14:24:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no11300898qtq.0!news-out.google.com!d29ni1110qtg.1!nntp.google.com!b26no11300892qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 Aug 2019 14:24:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.33.54.235; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.33.54.235 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9d25c07b-9d56-42a8-90e0-c5bc9730ac9c@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Weng Tianxiang Injection-Date: Sun, 11 Aug 2019 21:24:15 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9531 On Sunday, August 11, 2019 at 1:56:47 PM UTC-7, Rick C wrote: > On Sunday, August 11, 2019 at 4:01:22 PM UTC-4, Weng Tianxiang wrote: > > On Saturday, August 10, 2019 at 5:47:35 PM UTC-7, Richard Damon wrote: > >=20 > > Richard, > > >With the classic definition, the distinction between a machine defined= by the Mealy method (ON THE ARCS) or the Moore method (on the states) > >=20 > > My explanation for (ON THE ARCS) is that the input is STABLE ONLY ON th= e edge (setup time plus hold time), not because an output is registered by = a register. >=20 > The problem is everyone has their own interpretation of what a Mealy mach= ine is. So in the end "it means just what I choose it to mean=E2=80=94neit= her more nor less." Apologies to Lewis Carrol. Discussing FSM always see= ms to end up in Humpty Dumpty speak.=20 >=20 > --=20 >=20 > Rick C. >=20 > -+- Get 1,000 miles of free Supercharging > -+- Tesla referral code - https://ts.la/richard11209 Sorry to everyone who joined the discussion posted by me. Finally I find that the concept of Mealy and Moore state machine is a garba= ge, useless and should have no value in all modern circuit designs, worth n= othing to discuss it. Weng From newsfish@newsfish Thu Aug 1 00:44:43 2024 X-Received: by 2002:a05:6214:561:: with SMTP id cj1mr6542445qvb.50.1565558749551; Sun, 11 Aug 2019 14:25:49 -0700 (PDT) X-Received: by 2002:a25:b192:: with SMTP id h18mr21600108ybj.507.1565558749285; Sun, 11 Aug 2019 14:25:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no11304572qtq.0!news-out.google.com!d29ni1110qtg.1!nntp.google.com!b26no11304566qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 Aug 2019 14:25:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4cbc17e0-99b7-4b0a-97cf-cb3c8587825c@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: KJ Injection-Date: Sun, 11 Aug 2019 21:25:49 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9532 On Saturday, August 10, 2019 at 8:47:35 PM UTC-4, Richard Damon wrote: > I think a big problem with this discussion is there seems to be two > different definition of the Mealy machine. >=20 Good post, but there is really only one definition: Mealy, George H. (1955= ). A Method for Synthesizing Sequential Circuits. Bell System Technical Jou= rnal. pp. 1045=E2=80=931079. For those without access to the definitive source, Wikipedia presents their= definition at https://en.wikipedia.org/wiki/Mealy_machine which is: In the theory of computation, a Mealy machine is a finite-state machine who= se output values are determined both by its current state and the current i= nputs. Other 'definitions' are actually just other people's statements. To the ex= tent that those statements actually exactly match with the definition from = the definitive source, those opinions can be considered alternate definitio= ns. However, if the statements don't match the definition, then they are j= ust statements...or possibly 'incorrect definitions', but that seems like a= worthless title. Might seem pedantic, but many people post stuff trying to state something a= s fact when it is not since it has no documented basis...in other words it = just their words, not fact. That's my reason for my believing "You can't b= elieve everything you read on the internet". Kevin From newsfish@newsfish Thu Aug 1 00:44:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer03.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx45.iad.POSTED!not-for-mail Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? Newsgroups: comp.lang.vhdl References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> From: Richard Damon User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 173 Message-ID: X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Sun, 11 Aug 2019 17:47:33 -0400 X-Received-Bytes: 9759 X-Received-Body-CRC: 3627767529 Xref: reader01.eternal-september.org comp.lang.vhdl:9533 On 8/10/19 9:48 PM, Rick C wrote: > On Saturday, August 10, 2019 at 8:47:35 PM UTC-4, Richard Damon wrote: >> I think a big problem with this discussion is there seems to be two >> different definition of the Mealy machine. >> >> What I learned was that, given input I, and state S, and output O that a >> Moore machine had the description: (S' indicates S on next clock, f & g >> are pure combinatorial functions) >> >> S' = f(S, I) >> O = g(S) >> >> and a Mealy machine was >> >> S' = f(S, I) >> O = g(S, I) >> >> Note that in both cases, O is a pure combinatorial function of some signals. >> >> On the state diagram, the Moore machine puts the output values on the >> states, and the Mealy puts them on the arcs. >> >> It seems, some want to define Mealy as instead, >> >> O' = g(S, I) >> >> i.e, the outputs specified doesn't happen until the clock that updates >> the state, i.e. the arcs aren't specifying the CURRENT output, but the >> NEXT output. > > That's not really the issue. I don't think anyone is suggesting the outputs must be registered in a Mealy machine. If I said that, I was mistaken. The issue at hand is whether the inputs change between state transitions in useful systems. > Inputs always change some point after the clock, if fully synchronized, it will be one Clk->Q delay. With a Mealy Machine, the output O will change Tpd after the input change, and thus will be available to later logic on the same clock cycle. Note, the proper interpretation of the state table for a state machine is that it lists CURRENT state, CURRENT input, CURRENT output, and NEXT state, so that on the clock you move the next state to the current state. > >> A key factor that this definition defies is that in the classic >> definition, you can determine how much 'state' is in the system by the >> size of S (and how you encode it) and that determines how many registers >> you need. This modified definition effectively has added 1 bit of state >> for every output, and of course for that definition, you can always >> convert it, as you are just playing name games of which bits are 'state' >> and which are 'output' > > I don't know about 1 bit of state for every bit of output. But yes, that is why you can convert a Mealy FSM into a Moore FSM, they are be equivalent. But this is only valid if the inputs and outputs are considered at the clocking points. But you CAN'T. Please show me how to convert the following machine from Mealy to Moore. It has a simple implementation of a single flip flop, and the output is the xor of the input and the output (with NO flip flop after it) State Input Output State-Next 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 (Poor attempt to draw the diagram for this) 1/1 /------------------\|/----\ | 0/0 ^ v | | 0 1 | 1/0 | ^ 0/1 v | \-----/|\-----------------/ I have seen documents talking about the 'Moore Equivalent', but they are NOT identical machines, because the Moore Equivalent to the Mealy Machine adds a needed clock cycle of delay. > > >> With the classic definition, the distinction between a machine defined >> by the Mealy method (on the arcs) or the Moore method (on the states) in >> that there are a number of basic properties that can be easily >> determined for Moore machines, as they are relatively isolated from each >> other, and thus you can compute the speed of a system of Moore machines >> only needing to deal with a given machine and the machines that feed it. >> With the Mealy machine, because of the 'shoot through' of signals, you >> need to look at much more of the system. > > If you are coupling FSMs, this "shoot through" you mentions is really inputs to the second Mealy FSM for some odd reason being run through logic of the first Mealy FSM. If you were to move any of those output logic functions to the second machine both machines could be made Moore with no other changes... well, if you ignore the async logic feeding outputs of the second Mealy FSM, lol. But that logic is just logic and can easily be elsewhere. The inputs of the second FSM are the output of the first FSM. The may well depend on the state of the first FSM (as well as its inputs if it is Mealy). Since it can be dependent on the State of the first machine, it can't just be moved to the second machine. (You could combine them into a single bigger more complicated FSM). > > I'm not trying to mess with anyone here. I'm just batting this around in my brain. In reality the attachments of outputs to transitions in a Mealy FSM graph makes no sense unless the output is accompanied by a state transition. If the state transition is not required to change outputs in a Mealy machine, that type of directed graph and in fact any that I have seen does not properly represent a Mealy FSM with inputs changing without state transitions and impacting the outputs at times other than state transitions. Let us look at two simple state machines, the first defined as a Moore machine, the second as a Mealy machine. Both have states a, b, c, and d, and output O, and in input I, S'(0) is the next state for I = 0, S'(1) is the next state if I = 1, similarly for the Mealy Moore Machine S O S'(0) S'(1) a 0 a b b 0 a c c 1 d c d 1 a c This is the description of a simple debouncer, the output follows the input, but a single cycle change of the input gets ignored. Mealy Machine S S'(0) O(0) S'(1) O(1) a a 0 b 0 b a 0 c 1 c d 1 c 1 d a 0 c 1 Note, the states transitions are identical to the above, and the output is similar to the above, the difference being that with the Moore Machine, if you had a long series of 0s, then the input goes high, then on the 1st clock we move to state b, the 2nd clock we move to state c, and THEN the output changes. With the second machine, given the same input, on the first clock we move to state b as above, and THEN the output goes high (since we are in state b with i=1, and then on the 2nd clock we move to state c, and the output stays high. This machine generates its output almost a whole cycle earlier (it may have its output delayed by a bit more propagation delay. Mealy machines can of course have output without a state change, as the arcs can be from the state to itself, and in fact you MUST have such arrows if you can have input combinations that don't change the state (like states a and c above). In fact, a Mealy machine, since the arcs define the output states, must have a complete set of arcs out for ALL possible combinations of inputs, as you need to define the output for all conditions. In contrast, a Moore machine might use the definition that if the inputs don't match any of the provided arcs, the state stays the same, so you can omit the arcs from a state to itself. > > I did some work with async state machines once. An async Mealy FSM can be properly represented by the Mealy FSM graph while a sync Mealy FSM can't. > I am not talking about an asynchronous state machine here (Those are really neither Mealy or Moore, as the state transitions are not tied to the clock). Asynchronous machines, where some of the state latches can change state on certain input changes (not tied to the clock) are a very different beast and need different tools to analyze. > >> With Moore machines, you can, by re-encoding the states, convert g(S) >> into a simple selection of state bits, and then the output is available >> immediately (well, one clk->q delay, the delay ALL signals have) after >> the clock, and each machine can be computed totally independent of the >> other machines. (assuming a uniform clock in the system, if you have >> multiple clock domains, you need to do special analysis to take those >> issue into account, which is beyond the theory in Mealy/Moore machines). >> >> Generally, the flip-flops that are needed to synchronize signals not of >> the current machines clock domain are NOT considered part of the >> machine, as those ffs really need the multi-domain analysis. > > Indeed. > From newsfish@newsfish Thu Aug 1 00:44:44 2024 X-Received: by 2002:ac8:24b8:: with SMTP id s53mr28524346qts.276.1565568076394; Sun, 11 Aug 2019 17:01:16 -0700 (PDT) X-Received: by 2002:a81:3256:: with SMTP id y83mr14375558ywy.418.1565568076102; Sun, 11 Aug 2019 17:01:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!b26no255356qtq.0!news-out.google.com!d29ni1120qtg.1!nntp.google.com!b26no255353qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 Aug 2019 17:01:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Mon, 12 Aug 2019 00:01:16 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9534 On Sunday, August 11, 2019 at 5:47:37 PM UTC-4, Richard Damon wrote: > On 8/10/19 9:48 PM, Rick C wrote: > >=20 > > I don't know about 1 bit of state for every bit of output. But yes, th= at is why you can convert a Mealy FSM into a Moore FSM, they are be equival= ent. But this is only valid if the inputs and outputs are considered at th= e clocking points. =20 >=20 > But you CAN'T. Please show me how to convert the following machine from > Mealy to Moore. It has a simple implementation of a single flip flop, > and the output is the xor of the input and the output (with NO flip flop > after it) >=20 > State Input Output State-Next > 0 0 0 0 > 0 1 1 1 > 1 0 1 0 > 1 1 0 1 >=20 > (Poor attempt to draw the diagram for this) >=20 > 1/1 > /------------------\|/----\ > | 0/0 ^ v | > | 0 1 | 1/0 > | ^ 0/1 v | > \-----/|\-----------------/ >=20 > I have seen documents talking about the 'Moore Equivalent', but they are > NOT identical machines, because the Moore Equivalent to the Mealy > Machine adds a needed clock cycle of delay. FSM: process (CLK, RST) begin if RST then=20 Q <=3D '0';=20 elsif rising_edge(CLK) then Q <=3D D; end if; end process; There is the new FSM with the output Q. Then a bit of logic is needed to p= roduce the intended output.=20 Out <=3D D xor Q;=20 I'm sure you will say this is a Mealy FSM. That is fair. But adding a bit= of combinational logic to a FSM does not actually make it a new FSM. As W= eng has realized, this distinction is without value in "modern" design. =20 I realized something was amiss when I saw the outputs indicated on the tran= sitions could not represent the outputs of a combinational circuit of the i= nputs and state.=20 > > If you are coupling FSMs, this "shoot through" you mentions is really i= nputs to the second Mealy FSM for some odd reason being run through logic o= f the first Mealy FSM. If you were to move any of those output logic funct= ions to the second machine both machines could be made Moore with no other = changes... well, if you ignore the async logic feeding outputs of the secon= d Mealy FSM, lol. But that logic is just logic and can easily be elsewhere= .=20 >=20 > The inputs of the second FSM are the output of the first FSM. The may > well depend on the state of the first FSM (as well as its inputs if it > is Mealy). Since it can be dependent on the State of the first machine, > it can't just be moved to the second machine. (You could combine them > into a single bigger more complicated FSM). Simply make the required state variables available as outputs.=20 It can be argued that every set of interacting FSMs is a single FSM. But t= hat is of no value in this discussion.=20 > > I'm not trying to mess with anyone here. I'm just batting this around = in my brain. In reality the attachments of outputs to transitions in a Mea= ly FSM graph makes no sense unless the output is accompanied by a state tra= nsition. If the state transition is not required to change outputs in a Me= aly machine, that type of directed graph and in fact any that I have seen d= oes not properly represent a Mealy FSM with inputs changing without state t= ransitions and impacting the outputs at times other than state transitions.= =20 >=20 > Let us look at two simple state machines, the first defined as a Moore > machine, the second as a Mealy machine. =20 I believe we all understand the issues here. What bothers me is the discon= nect between the definition of the two types of machines and the notation u= sed to describe them. Mealy himself in his original paper used the notatio= n of assigning outputs to the transitions which can not represent the opera= tion of the Mealy FSM implemented with clocked synchronous logic. On readi= ng the paper I understand why. While he mentions the use of a clock in his= definitions of a synchronous circuit, but the circuits he uses have NO CLO= CK! They are asynchronous state machines which will change state as soon a= s the inputs change. In that case it makes sense to say the outputs of a M= ealy FSM reflect the "current" state of the inputs as well as being represe= nted by outputs assigned to the state changes. =20 Bottom line, as Weng has said, there is no real value to the distinction be= tween Mealy and Moore FSM. As others have said, often a given implementati= on is not either of these two theoretical models. =20 --=20 Rick C. -++ Get 1,000 miles of free Supercharging -++ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:44 2024 X-Received: by 2002:aed:3327:: with SMTP id u36mr29870275qtd.94.1565720129219; Tue, 13 Aug 2019 11:15:29 -0700 (PDT) X-Received: by 2002:a0d:ce84:: with SMTP id q126mr26155648ywd.88.1565720128977; Tue, 13 Aug 2019 11:15:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!b26no5839863qtq.0!news-out.google.com!d29ni1358qtg.1!nntp.google.com!b26no5839851qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Aug 2019 11:15:28 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.18.137.244; posting-account=FiJOqwoAAABTa9aMB9-1UUgsWPfCZi5j NNTP-Posting-Host: 88.18.137.244 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <779c8f8b-285b-4002-8929-4922423214e4@googlegroups.com> Subject: LA BESTIA CRIMINALE PAOLO BARRAI, PURE NEL 2019, E' INDAGATO DA PROCURA DI MILANO. MA ANCHE DA PROCURA DI LUGANO. ANCHE DA SCOTLAND YARD DI LONDRA. E' INDAGATISSIMO DA EUROPOL ED INTERPOL. LO INDAGA ANCHE L'FBI DA NEW YORK. NE TROVATE .............. From: RICICLASOLDIMAFIOSI PAOLO BARRAI ORDINATANTIOMICID Injection-Date: Tue, 13 Aug 2019 18:15:29 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 19476 X-Received-Body-CRC: 3053715379 Lines: 288 Xref: reader01.eternal-september.org comp.lang.vhdl:9535 LA BESTIA CRIMINALE PAOLO BARRAI, PURE NEL 2019, E' INDAGATO DA PROCURA DI = MILANO. MA ANCHE DA PROCURA DI LUGANO. ANCHE DA SCOTLAND YARD DI LONDRA. E'= INDAGATISSIMO DA EUROPOL ED INTERPOL. LO INDAGA ANCHE L'FBI DA NEW YORK.= =20 NE TROVATE ................. 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OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 From newsfish@newsfish Thu Aug 1 00:44:44 2024 X-Received: by 2002:ac8:1a6c:: with SMTP id q41mr673980qtk.217.1565806923407; Wed, 14 Aug 2019 11:22:03 -0700 (PDT) X-Received: by 2002:a25:8482:: with SMTP id v2mr771515ybk.200.1565806922935; Wed, 14 Aug 2019 11:22:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!f14no285838qtq.0!news-out.google.com!d29ni1471qtg.1!nntp.google.com!f14no285835qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2019 11:22:02 -0700 (PDT) In-Reply-To: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.121.249.239; posting-account=ZoBkmgoAAADd2njBbWf4kq3j42Go0CxZ NNTP-Posting-Host: 95.121.249.239 References: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1f55ad9f-5fa0-4459-8f8c-fae2a1cfe2b4@googlegroups.com> Subject: Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI OMICIDA A From: INCULAIBAMBINI PAOLO BARRAI ILPEDOFILODELBITCOIN Injection-Date: Wed, 14 Aug 2019 18:22:03 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 19708 X-Received-Body-CRC: 2530620295 Xref: reader01.eternal-september.org comp.lang.vhdl:9536 Lines: 289 LA BESTIA CRIMINALE PAOLO BARRAI, PURE NEL 2019, E' INDAGATO DA PROCURA DI = MILANO. MA PURE DA PROCURA DI LUGANO. PURE DA SCOTLAND YARD DI LONDRA. PURE= DA FBI DA NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL.=20 NE TROVATE VINCENTISSIMAMENTE QUI .........................................= ....... https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ MI PRESENTO.=20 SONO ANDREAS NIGG VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN BANK ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK= VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, ALLORCHE' COMPRAMMO LA = EX FINTER BANK ZURICH DEI MASSONI NAZISTI E LEGHISTI PESENTI, IO IN PERSONA= , ANDREAS NIGG, ORDIANI DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI A STA BE= STIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL 28.6.19= 65. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA E CAMORRA, DA LONTANO 3.= 000 KM. MUMBLE, MUMBLE, MUMBLE... SONO SVIZZERO, ICH BIN SCHWEIZER, QUINDI SONO UN = UOMO PRECISO. AMO LA PRECISIONE. PER VIA DI QUESTO, ANALIZZIAMO BEN BENE, O= GNI CONCETTO, DA ORA IN AVANTI, PLEASE!=20 DICEVAMO..... L'ASSASSINO PEDOFILO PAOLO BARRAI, ANCHE NEL 2019, FA CRIMINI TERRIFICANTI = PIU' CHE MAI! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STUPR= A ED AMMAZZA TANTI BAMBINI. HA RICICLATO EURO ASSASSINI DI NDRANGHETA IN MA= LAVITOSISSIMA ICO EIDOO!!!!!!!!!!!!!!!!!!!! E' STATO CACCIATO DA CITIBANK E= FATTO CONDANNARE A GALERA DA CITIBANK! HA FATTO FILM PEDOPORNOGRAFICI, STU= PRANDO QUASI A MORTE TANTI BAMBINI! HA UCCISO LUI STESSO, TANTI BAMBINI, PE= R PRENDER I LORO ORGANI E TRAFFICARLI! HA FATTO FILM PORNO CON CAVALLI, BEV= ENDO LITRI DI SPERMA EQUINO! E' STATO MULTATO DA CONSOB BEN 70.000 EURO! HA= 23 CAUSE, CON GENTE DI MEZZA DITTATURA FASCIOMAFIOSA DI BERLUSCONIA, A CUI= HA AZZERATO I RISPARMI! PER SCAPPARE ALLE QUALI, SI E' ORA RIFUGIATO A LON= DRA, OVE FA TANTI POMPINI AL NAZISTA NIGEL FARAGE AFFINCHE' LO PROTEGGA! E'= STATO CONDANNATO AL CARCERE IN BRASILE, ANCHE PER PEDERASTIA VIOLENTA ( E = PER ALTRI TANTISSIMI CRIMINI)! NON NE AZZECCA MAI MEZZA UNA IN BORSA, OVE A= ZZERA I RISPARMI DI TUTTI E SEMPRE! E VI E' TANTISSIMO PIU', DI CUI SCRIVER= EMO FINO A 15 MINUTI DOPO LA NOSTRA MORTE! E' DA ARRESTARE IMMEDIATAMENTE: PAOLO BARRAI (CRYPTOPOLIS E CRYPTOLAB)! E' = STATO IL REGISTA CRIMINALE DELL'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER = LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO P= AOLO BARRAI, ABITAVA A MILANO, IN VIA.......... IPPODROMO 105 (ZONA SAN SIR= O- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEG= A ASSASSINI GIULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 From newsfish@newsfish Thu Aug 1 00:44:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx44.iad.POSTED!not-for-mail Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? Newsgroups: comp.lang.vhdl References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> From: Richard Damon User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 143 Message-ID: X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Fri, 16 Aug 2019 22:30:00 -0400 X-Received-Bytes: 10157 X-Received-Body-CRC: 2670448784 X-Original-Bytes: 9862 Xref: reader01.eternal-september.org comp.lang.vhdl:9537 On 8/11/19 8:01 PM, Rick C wrote: > On Sunday, August 11, 2019 at 5:47:37 PM UTC-4, Richard Damon wrote: >> On 8/10/19 9:48 PM, Rick C wrote: >>> >>> I don't know about 1 bit of state for every bit of output. But yes, that is why you can convert a Mealy FSM into a Moore FSM, they are be equivalent. But this is only valid if the inputs and outputs are considered at the clocking points. >> >> But you CAN'T. Please show me how to convert the following machine from >> Mealy to Moore. It has a simple implementation of a single flip flop, >> and the output is the xor of the input and the output (with NO flip flop >> after it) >> >> State Input Output State-Next >> 0 0 0 0 >> 0 1 1 1 >> 1 0 1 0 >> 1 1 0 1 >> >> (Poor attempt to draw the diagram for this) >> >> 1/1 >> /------------------\|/----\ >> | 0/0 ^ v | >> | 0 1 | 1/0 >> | ^ 0/1 v | >> \-----/|\-----------------/ >> >> I have seen documents talking about the 'Moore Equivalent', but they are >> NOT identical machines, because the Moore Equivalent to the Mealy >> Machine adds a needed clock cycle of delay. > > > FSM: process (CLK, RST) > begin > if RST then > Q <= '0'; > elsif rising_edge(CLK) then > Q <= D; > end if; > end process; > > There is the new FSM with the output Q. Then a bit of logic is needed to produce the intended output. > > Out <= D xor Q; > > I'm sure you will say this is a Mealy FSM. That is fair. But adding a bit of combinational logic to a FSM does not actually make it a new FSM. As Weng has realized, this distinction is without value in "modern" design. > > I realized something was amiss when I saw the outputs indicated on the transitions could not represent the outputs of a combinational circuit of the inputs and state. > > So you are saying you can convert any Mealy machine into a Moore machine, if it doesn't have to be a Moore machine? That sounds like a FAIL. Your description is exactly how to describe it as a Mealy machine, you have a process to compute the next state and output equations that depend on the state and the inputs, i.e. a Mealy machine. If you are building a Moore machine, you can do the same thing but the outputs are only dependent on the state variables, and not the input. The one difference is that with a Moore machine, it is generally possible to refactor the machine, so that you move the output computation so that you compute the 'next output' instead of the 'current output' and then put those into register like the state (and perhaps by re-encoding the state remove some of the existing state registers, so the output has just a single clk to out delay. (It may increase the setup time of the machine, which is the reason you might not be able to do this). This motion of the output is one thing that can NOT be done with a Mealy machine. I don't understand how you can can say that the outputs are not a combinatorial output of the input and the current state? Is that not exactly what the truth table provides, it lists all combinations of the input and the state, and the exact desired output for that combination. > >>> If you are coupling FSMs, this "shoot through" you mentions is really inputs to the second Mealy FSM for some odd reason being run through logic of the first Mealy FSM. If you were to move any of those output logic functions to the second machine both machines could be made Moore with no other changes... well, if you ignore the async logic feeding outputs of the second Mealy FSM, lol. But that logic is just logic and can easily be elsewhere. >> >> The inputs of the second FSM are the output of the first FSM. The may >> well depend on the state of the first FSM (as well as its inputs if it >> is Mealy). Since it can be dependent on the State of the first machine, >> it can't just be moved to the second machine. (You could combine them >> into a single bigger more complicated FSM). > > Simply make the required state variables available as outputs. > > It can be argued that every set of interacting FSMs is a single FSM. But that is of no value in this discussion. > > Yes, the full single domain design can be called a single FSM. But large FSMs are hard to analyze, which is why it helps the understanding to partition them into smaller interconnected machines. The conceptual load to analyze such a combination can be significantly less than the system as a whole. Divorcing the output generation from the state transition often destroys the encapsulation which was helping to reduce the system complexity, removing the advantage of partitioning into smaller machines. >>> I'm not trying to mess with anyone here. I'm just batting this around in my brain. In reality the attachments of outputs to transitions in a Mealy FSM graph makes no sense unless the output is accompanied by a state transition. If the state transition is not required to change outputs in a Mealy machine, that type of directed graph and in fact any that I have seen does not properly represent a Mealy FSM with inputs changing without state transitions and impacting the outputs at times other than state transitions. >> >> Let us look at two simple state machines, the first defined as a Moore >> machine, the second as a Mealy machine. > > > > I believe we all understand the issues here. What bothers me is the disconnect between the definition of the two types of machines and the notation used to describe them. Mealy himself in his original paper used the notation of assigning outputs to the transitions which can not represent the operation of the Mealy FSM implemented with clocked synchronous logic. On reading the paper I understand why. While he mentions the use of a clock in his definitions of a synchronous circuit, but the circuits he uses have NO CLOCK! They are asynchronous state machines which will change state as soon as the inputs change. In that case it makes sense to say the outputs of a Mealy FSM reflect the "current" state of the inputs as well as being represented by outputs assigned to the state changes. > > Bottom line, as Weng has said, there is no real value to the distinction between Mealy and Moore FSM. As others have said, often a given implementation is not either of these two theoretical models. > With a quick search, I can't seem to find a free version of the paper, and I am not feeling the need to pay $35 for an official copy (and it is old enough that if they didn't renew the copyright I would expect it to have expired by now, being a 1955 document), so I will go on my understand from my studies. I suspect you are misunderstanding the paper. A Mealy machine IS a clock sequential machine for the States, the states update synchronously on the system clock. The difference between the Mealy model and the Moore model is that Mealy built the combinatorial output based on both the current state and the inputs. As is typical for synchronous systems, often the registers are not drawn with a clock, as it is implied, ALL the registers are clocked together, and drawing the clock to all of them just adds clutter. The introduction to the paper, that I can find, it clearly refers to the Moore paper, and talks about extending it, so it clearly is talking about a synchronous system. The way to read a Mealy diagram, if you are currently in State S1, with input I, find the arc leaving S1 that matches the input going to some state S2 (which might be the same as S1), and be outputing the specifed output on the arc until the next clock at which point the state will change to S2, and the output will then change to be based on the arcs leaving S2 and the then current input. Any change to the input value may cause a change to the output as you change which arc you are following. The outputs that other synchronous machines will act on will be based on the last value of the input prior to the clock arriving. As changes propogate through the system, the output might change several times until it stabilizes on its final value. One thing that you do need to be careful with Mealy machines, is it is possible to accidentally build an asynchronous latch or an astable network if there is a combitorial loop in the logic. I thought I remember that such a loop was to be excluded in a proper Mealy design. From newsfish@newsfish Thu Aug 1 00:44:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder4.feed.usenet.farm!feed.usenet.farm!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx41.iad.POSTED!not-for-mail Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? Newsgroups: comp.lang.vhdl References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> From: Richard Damon User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Lines: 37 Message-ID: X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Fri, 16 Aug 2019 22:50:29 -0400 X-Received-Bytes: 3498 X-Received-Body-CRC: 3997602428 Xref: reader01.eternal-september.org comp.lang.vhdl:9538 On 8/11/19 4:56 PM, Rick C wrote: > On Sunday, August 11, 2019 at 4:01:22 PM UTC-4, Weng Tianxiang wrote: >> On Saturday, August 10, 2019 at 5:47:35 PM UTC-7, Richard Damon wrote: >> >> Richard, >>> With the classic definition, the distinction between a machine defined by the Mealy method (ON THE ARCS) or the Moore method (on the states) >> >> My explanation for (ON THE ARCS) is that the input is STABLE ONLY ON the edge (setup time plus hold time), not because an output is registered by a register. > > The problem is everyone has their own interpretation of what a Mealy machine is. So in the end "it means just what I choose it to mean—neither more nor less." Apologies to Lewis Carrol. Discussing FSM always seems to end up in Humpty Dumpty speak. > There is a precise definition of what a Mealy machine is, and it is well described in the literature. I find no disagreement with that definition among what I consider reputable sites. Yes, there ARE people who will misuse the terms either because they don't know better, or they choose to not care. That doesn't mean the definition isn't precise. (Just that some people are Wrong). The essence of the definition is that you state with a set of states S (with a starting state specified), a set of input values I, and a set of output values O. The machine can be described via a pair of mappings, one is the transition mapping of the combinations of S and I to S to describe the next state, and another, the output mapping that defines a mapping of S and I to O to define the output. The output mapping needs to be run as needed due to a change in S or I, and the transition mapping is run when it is time to advance the system to the next state. Note that the Moore machine can be described similarly, except that the output mapping is only a mapping of S to O, and as such, a Moore machine only needs to be evaluated when you want a state update, so much of the math becomes simpler. From newsfish@newsfish Thu Aug 1 00:44:45 2024 X-Received: by 2002:a37:4804:: with SMTP id v4mr12294674qka.60.1566013429782; Fri, 16 Aug 2019 20:43:49 -0700 (PDT) X-Received: by 2002:a0d:eccd:: with SMTP id v196mr8781640ywe.30.1566013429587; Fri, 16 Aug 2019 20:43:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!f14no8068630qtq.0!news-out.google.com!d29ni1807qtg.1!nntp.google.com!f14no8068621qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Aug 2019 20:43:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <439b6a53-ed95-4253-875d-0dd37127b47e@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 17 Aug 2019 03:43:49 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9539 On Friday, August 16, 2019 at 10:30:04 PM UTC-4, Richard Damon wrote: > On 8/11/19 8:01 PM, Rick C wrote: > > On Sunday, August 11, 2019 at 5:47:37 PM UTC-4, Richard Damon wrote: > >> On 8/10/19 9:48 PM, Rick C wrote: > >>> > >>> I don't know about 1 bit of state for every bit of output. But yes, = that is why you can convert a Mealy FSM into a Moore FSM, they are be equiv= alent. But this is only valid if the inputs and outputs are considered at = the clocking points. =20 > >> > >> But you CAN'T. Please show me how to convert the following machine fro= m > >> Mealy to Moore. It has a simple implementation of a single flip flop, > >> and the output is the xor of the input and the output (with NO flip fl= op > >> after it) > >> > >> State Input Output State-Next > >> 0 0 0 0 > >> 0 1 1 1 > >> 1 0 1 0 > >> 1 1 0 1 > >> > >> (Poor attempt to draw the diagram for this) > >> > >> 1/1 > >> /------------------\|/----\ > >> | 0/0 ^ v | > >> | 0 1 | 1/0 > >> | ^ 0/1 v | > >> \-----/|\-----------------/ > >> > >> I have seen documents talking about the 'Moore Equivalent', but they a= re > >> NOT identical machines, because the Moore Equivalent to the Mealy > >> Machine adds a needed clock cycle of delay. > >=20 > >=20 > > FSM: process (CLK, RST) > > begin > > if RST then=20 > > Q <=3D '0';=20 > > elsif rising_edge(CLK) then > > Q <=3D D; > > end if; > > end process; > >=20 > > There is the new FSM with the output Q. Then a bit of logic is needed = to produce the intended output.=20 > >=20 > > Out <=3D D xor Q;=20 > >=20 > > I'm sure you will say this is a Mealy FSM. That is fair. But adding a= bit of combinational logic to a FSM does not actually make it a new FSM. = As Weng has realized, this distinction is without value in "modern" design.= =20 > >=20 > > I realized something was amiss when I saw the outputs indicated on the = transitions could not represent the outputs of a combinational circuit of t= he inputs and state.=20 > >=20 > >=20 >=20 > So you are saying you can convert any Mealy machine into a Moore > machine, if it doesn't have to be a Moore machine? That sounds like a FAI= L. >=20 > Your description is exactly how to describe it as a Mealy machine, you > have a process to compute the next state and output equations that > depend on the state and the inputs, i.e. a Mealy machine. Just find any text book on the topic and read the section on converting fro= m one type of FSM to the other. What you keep focusing on is the idea that= the outputs have to change from input changes which are not at the time of= a state change. THAT was not part of Mealy's FSM design method although i= t is in his description of the FSM. =20 The trouble is at his time there were no logic types that you could use for= the type of FSM where inputs change and not trigger a state change or at l= east the potential. Everyone focuses on inputs changing the outputs when t= he state isn't changing because the clock hasn't happened yet. That's not = what Mealy was working with.=20 > If you are building a Moore machine, you can do the same thing but the > outputs are only dependent on the state variables, and not the input. > The one difference is that with a Moore machine, it is generally > possible to refactor the machine, so that you move the output > computation so that you compute the 'next output' instead of the > 'current output' and then put those into register like the state (and > perhaps by re-encoding the state remove some of the existing state > registers, so the output has just a single clk to out delay. (It may > increase the setup time of the machine, which is the reason you might > not be able to do this). This motion of the output is one thing that can > NOT be done with a Mealy machine. >=20 > I don't understand how you can can say that the outputs are not a > combinatorial output of the input and the current state? Is that not > exactly what the truth table provides, it lists all combinations of the > input and the state, and the exact desired output for that combination. Instead of focusing on that one erroneous aspect of Mealy's FSM description= , look at the diagrams he uses for his FSM. They show output specification= s on state transitions and ONLY on state transitions. This allows one type= of FSM to be morphed into the other.=20 > >>> If you are coupling FSMs, this "shoot through" you mentions is really= inputs to the second Mealy FSM for some odd reason being run through logic= of the first Mealy FSM. If you were to move any of those output logic fun= ctions to the second machine both machines could be made Moore with no othe= r changes... well, if you ignore the async logic feeding outputs of the sec= ond Mealy FSM, lol. But that logic is just logic and can easily be elsewhe= re.=20 > >> > >> The inputs of the second FSM are the output of the first FSM. The may > >> well depend on the state of the first FSM (as well as its inputs if it > >> is Mealy). Since it can be dependent on the State of the first machine= , > >> it can't just be moved to the second machine. (You could combine them > >> into a single bigger more complicated FSM). > >=20 > > Simply make the required state variables available as outputs.=20 > >=20 > > It can be argued that every set of interacting FSMs is a single FSM. B= ut that is of no value in this discussion.=20 > >=20 > >=20 >=20 > Yes, the full single domain design can be called a single FSM. But large > FSMs are hard to analyze, which is why it helps the understanding to > partition them into smaller interconnected machines. The conceptual load > to analyze such a combination can be significantly less than the system > as a whole. Divorcing the output generation from the state transition > often destroys the encapsulation which was helping to reduce the system > complexity, removing the advantage of partitioning into smaller machines. >=20 > >>> I'm not trying to mess with anyone here. I'm just batting this aroun= d in my brain. In reality the attachments of outputs to transitions in a M= ealy FSM graph makes no sense unless the output is accompanied by a state t= ransition. If the state transition is not required to change outputs in a = Mealy machine, that type of directed graph and in fact any that I have seen= does not properly represent a Mealy FSM with inputs changing without state= transitions and impacting the outputs at times other than state transition= s. =20 > >> > >> Let us look at two simple state machines, the first defined as a Moore > >> machine, the second as a Mealy machine. > >=20 > > =20 > >=20 > > I believe we all understand the issues here. What bothers me is the di= sconnect between the definition of the two types of machines and the notati= on used to describe them. Mealy himself in his original paper used the not= ation of assigning outputs to the transitions which can not represent the o= peration of the Mealy FSM implemented with clocked synchronous logic. On r= eading the paper I understand why. While he mentions the use of a clock in= his definitions of a synchronous circuit, but the circuits he uses have NO= CLOCK! They are asynchronous state machines which will change state as so= on as the inputs change. In that case it makes sense to say the outputs of= a Mealy FSM reflect the "current" state of the inputs as well as being rep= resented by outputs assigned to the state changes. =20 > >=20 > > Bottom line, as Weng has said, there is no real value to the distinctio= n between Mealy and Moore FSM. As others have said, often a given implemen= tation is not either of these two theoretical models. =20 > >=20 >=20 > With a quick search, I can't seem to find a free version of the paper, > and I am not feeling the need to pay $35 for an official copy (and it is > old enough that if they didn't renew the copyright I would expect it to > have expired by now, being a 1955 document), so I will go on my > understand from my studies. https://archive.org/details/bstj34-5-1045 Unfortunately two pages are missing. =20 > I suspect you are misunderstanding the paper. A Mealy machine IS a clock > sequential machine for the States, the states update synchronously on > the system clock. The difference between the Mealy model and the Moore > model is that Mealy built the combinatorial output based on both the > current state and the inputs. As is typical for synchronous systems, > often the registers are not drawn with a clock, as it is implied, ALL > the registers are clocked together, and drawing the clock to all of them > just adds clutter. YOU are adding the "clock" to sequential for both types of FSM. Once you o= mit that you might do better at understanding that both Mealy and Moore's p= apers were not about the hardware, they are about design methods.=20 > The introduction to the paper, that I can find, it clearly refers to the > Moore paper, and talks about extending it, so it clearly is talking > about a synchronous system. Synchronous is not the same thing as sequential. A main logic type at the = time was relay logic which is asynchronous sequential.=20 > The way to read a Mealy diagram, if you are currently in State S1, with > input I, find the arc leaving S1 that matches the input going to some > state S2 (which might be the same as S1), and be outputing the specifed > output on the arc until the next clock at which point the state will > change to S2, and the output will then change to be based on the arcs > leaving S2 and the then current input. Any change to the input value may > cause a change to the output as you change which arc you are following. > The outputs that other synchronous machines will act on will be based on > the last value of the input prior to the clock arriving. As changes > propogate through the system, the output might change several times > until it stabilizes on its final value. One thing that you do need to be > careful with Mealy machines, is it is possible to accidentally build an > asynchronous latch or an astable network if there is a combitorial loop > in the logic. I thought I remember that such a loop was to be excluded > in a proper Mealy design. I don't want to discuss this with you in two different forums. I also am n= ot going to let you invent how to read Mealy state diagrams. You can inven= t anything you want, but don't attribute it to Mealy.=20 --=20 Rick C. +-- Get 1,000 miles of free Supercharging +-- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:45 2024 X-Received: by 2002:ac8:46d2:: with SMTP id h18mr11772338qto.38.1566014601542; Fri, 16 Aug 2019 21:03:21 -0700 (PDT) X-Received: by 2002:a25:bd87:: with SMTP id f7mr9893572ybh.143.1566014601378; Fri, 16 Aug 2019 21:03:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!f14no8107700qtq.0!news-out.google.com!d29ni1807qtg.1!nntp.google.com!f14no8107694qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Aug 2019 21:03:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <75a0403d-736c-43ba-a258-648be864c51a@googlegroups.com> <4ac8bba8-c6d3-4d56-a110-3aa73b8bf010@googlegroups.com> <87764b35-e704-467b-b287-7cd890163fc7@googlegroups.com> <2c851fe3-67b7-4f7b-87d3-626d37abf22b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <546c2edb-4aca-4659-878a-a6fdaffaf4e1@googlegroups.com> Subject: Re: Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? From: Rick C Injection-Date: Sat, 17 Aug 2019 04:03:21 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 75 Xref: reader01.eternal-september.org comp.lang.vhdl:9540 On Friday, August 16, 2019 at 10:50:32 PM UTC-4, Richard Damon wrote: > On 8/11/19 4:56 PM, Rick C wrote: > > On Sunday, August 11, 2019 at 4:01:22 PM UTC-4, Weng Tianxiang wrote: > >> On Saturday, August 10, 2019 at 5:47:35 PM UTC-7, Richard Damon wrote: > >> > >> Richard, > >>> With the classic definition, the distinction between a machine define= d by the Mealy method (ON THE ARCS) or the Moore method (on the states) > >> > >> My explanation for (ON THE ARCS) is that the input is STABLE ONLY ON t= he edge (setup time plus hold time), not because an output is registered by= a register. > >=20 > > The problem is everyone has their own interpretation of what a Mealy ma= chine is. So in the end "it means just what I choose it to mean=E2=80=94ne= ither more nor less." Apologies to Lewis Carrol. Discussing FSM always s= eems to end up in Humpty Dumpty speak.=20 > >=20 >=20 > There is a precise definition of what a Mealy machine is, and it is well > described in the literature. I find no disagreement with that definition > among what I consider reputable sites. >=20 > Yes, there ARE people who will misuse the terms either because they > don't know better, or they choose to not care. That doesn't mean the > definition isn't precise. (Just that some people are Wrong). >=20 > The essence of the definition is that you state with a set of states S > (with a starting state specified), a set of input values I, and a set of > output values O. >=20 > The machine can be described via a pair of mappings, one is the > transition mapping of the combinations of S and I to S to describe the > next state, and another, the output mapping that defines a mapping of S > and I to O to define the output. >=20 > The output mapping needs to be run as needed due to a change in S or I, > and the transition mapping is run when it is time to advance the system > to the next state. >=20 > Note that the Moore machine can be described similarly, except that the > output mapping is only a mapping of S to O, and as such, a Moore machine > only needs to be evaluated when you want a state update, so much of the > math becomes simpler. One last time. Yes, Mealy himself defined his FSM model (what he calls a "= switching circuit") as having outputs that depend on the "present input com= bination and the present state". But in his world there was no input separ= ate from the "clock" as it was pulse logic. =20 So Mealy never said or implied that the outputs would change at any time ot= her than when the state was potentially changing.=20 When people try to interpret his intent as saying the outputs could change = separately from the clock, they are misinterpreting his paper. =20 If you stop arguing semantics and actually look at the other evidence such = as the equivalence of the two types of machines, you will see that Mealy di= d not invent a unique FSM architecture. Heck, typing into google gives sug= gested search for "equivalence of mealy and moore machine". Or better, sea= rch for "Conversion from Mealy to Moore Machine". =20 Or better yet, here is a paper with the mathematical proof that for every M= oore FSM there is an equivalent Mealy and vice versa. =20 http://lms.uop.edu.jo/lms/pluginfile.php/35159/mod_resource/content/0/chap0= 8.pdf Enough?=20 --=20 Rick C. +-+ Get 1,000 miles of free Supercharging +-+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:46 2024 X-Received: by 2002:ad4:430f:: with SMTP id c15mr5125084qvs.25.1566054104079; Sat, 17 Aug 2019 08:01:44 -0700 (PDT) X-Received: by 2002:a25:514:: with SMTP id 20mr10625030ybf.319.1566054103957; Sat, 17 Aug 2019 08:01:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!85.12.16.69.MISMATCH!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!f14no9512272qtq.0!news-out.google.com!d29ni1882qtg.1!nntp.google.com!f14no9512258qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Aug 2019 08:01:43 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=65.92.40.178; posting-account=-3m9WQoAAADqph1cWZ4uX0b-9dwN4Ozr NNTP-Posting-Host: 65.92.40.178 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <948a647a-b492-4c1f-8e6e-0bfa040eaef0@googlegroups.com> Subject: HDLC Clocking From: digitalguy33@gmail.com Injection-Date: Sat, 17 Aug 2019 15:01:44 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1410 X-Received-Body-CRC: 3400124696 Xref: reader01.eternal-september.org comp.lang.vhdl:9541 Is there a standard for the clocking in HDLC? I have seen examples where data is transmitted on rising edge of TXCLK and sampled on falling edge ... as well as examples where data is transmitted on falling edge of TXCLK and sampled on rising edge. I can't seem to find any mention in the HDLC standard. From newsfish@newsfish Thu Aug 1 00:44:46 2024 X-Received: by 2002:ac8:c86:: with SMTP id n6mr13566007qti.345.1566056274773; Sat, 17 Aug 2019 08:37:54 -0700 (PDT) X-Received: by 2002:a25:8301:: with SMTP id s1mr11062959ybk.119.1566056274035; Sat, 17 Aug 2019 08:37:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!f14no9595926qtq.0!news-out.google.com!d29ni1885qtg.1!nntp.google.com!f14no9595924qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Aug 2019 08:37:53 -0700 (PDT) In-Reply-To: <948a647a-b492-4c1f-8e6e-0bfa040eaef0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <948a647a-b492-4c1f-8e6e-0bfa040eaef0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6bfa8966-ce4d-404e-86b1-f0ff48d3da95@googlegroups.com> Subject: Re: HDLC Clocking From: Rick C Injection-Date: Sat, 17 Aug 2019 15:37:54 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 12 Xref: reader01.eternal-september.org comp.lang.vhdl:9542 On Saturday, August 17, 2019 at 11:01:46 AM UTC-4, digita...@gmail.com wrote: > Is there a standard for the clocking in HDLC? I have seen examples where data is transmitted on rising edge of TXCLK and sampled on falling edge ... as well as examples where data is transmitted on falling edge of TXCLK and sampled on rising edge. > > I can't seem to find any mention in the HDLC standard. HDLC doesn't seem to specify the clock. I would expect the clock to be specified at a lower level protocol. HDLC can be used over async links where no clock is transmitted. So clearly no clock edge could be specified in that case. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:46 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsreader4.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx18.iad.POSTED!not-for-mail Subject: Re: HDLC Clocking Newsgroups: comp.lang.vhdl References: <948a647a-b492-4c1f-8e6e-0bfa040eaef0@googlegroups.com> From: Richard Damon User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <948a647a-b492-4c1f-8e6e-0bfa040eaef0@googlegroups.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 11 Message-ID: <%cV5F.52351$_a4.25754@fx18.iad> X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Sat, 17 Aug 2019 11:39:38 -0400 X-Received-Bytes: 1719 X-Received-Body-CRC: 2979334667 Xref: reader01.eternal-september.org comp.lang.vhdl:9543 On 8/17/19 11:01 AM, digitalguy33@gmail.com wrote: > Is there a standard for the clocking in HDLC? I have seen examples where data is transmitted on rising edge of TXCLK and sampled on falling edge ... as well as examples where data is transmitted on falling edge of TXCLK and sampled on rising edge. > > I can't seem to find any mention in the HDLC standard. > I think the issue is that is a detail at a different level than the HDLC standard, dealing with the physical transport layer. HDLC doesn't even imply that there IS a clock transferred between units to worry about what edge to use, and in fact has pieces that make sure there is enough data transitions to allow for clock recovery operation in the receiver. From newsfish@newsfish Thu Aug 1 00:44:47 2024 X-Received: by 2002:a05:620a:685:: with SMTP id f5mr15267927qkh.238.1566305144708; Tue, 20 Aug 2019 05:45:44 -0700 (PDT) X-Received: by 2002:a25:bd87:: with SMTP id f7mr20540249ybh.143.1566305144359; Tue, 20 Aug 2019 05:45:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!f14no8207251qtq.0!news-out.google.com!d29ni2263qtg.1!nntp.google.com!f14no8207248qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Aug 2019 05:45:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.106.231.41; posting-account=4hpGrgoAAADJrROAaEYYjlAHL3bwOxDs NNTP-Posting-Host: 46.106.231.41 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6c4b78eb-5401-4e30-bc84-c19a4c0b4c6b@googlegroups.com> Subject: Chdl 8 bit counter From: kadir284197@gmail.com Injection-Date: Tue, 20 Aug 2019 12:45:44 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9544 Design an 8-bit up counter with reset feature. Two different count speed be= defined. One of the count speeds should be 1 bit at 1 sec, while other one= should be set 4 bit increment in 1 sec. =C4=B0 cant do this hw tell me something please From newsfish@newsfish Thu Aug 1 00:44:47 2024 X-Received: by 2002:ae9:ef06:: with SMTP id d6mr27458766qkg.157.1566333003470; Tue, 20 Aug 2019 13:30:03 -0700 (PDT) X-Received: by 2002:a81:4801:: with SMTP id v1mr21051882ywa.105.1566333003330; Tue, 20 Aug 2019 13:30:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!f14no9304060qtq.0!news-out.google.com!d29ni2298qtg.1!nntp.google.com!f14no9304050qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Aug 2019 13:30:03 -0700 (PDT) In-Reply-To: <6c4b78eb-5401-4e30-bc84-c19a4c0b4c6b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=173.163.197.221; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 173.163.197.221 References: <6c4b78eb-5401-4e30-bc84-c19a4c0b4c6b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <871005c9-910c-4df5-b58b-18f87fc63ec2@googlegroups.com> Subject: Re: Chdl 8 bit counter From: Rick C Injection-Date: Tue, 20 Aug 2019 20:30:03 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9545 On Tuesday, August 20, 2019 at 8:45:46 AM UTC-4, kadir...@gmail.com wrote: > Design an 8-bit up counter with reset feature. Two different count speed = be defined. One of the count speeds should be 1 bit at 1 sec, while other o= ne should be set 4 bit increment in 1 sec. > =C4=B0 cant do this hw tell me something please What DO you know? Let's start there. Do you know VHDL? Do you know how = to code a FF? How about a simple counter? =20 Give us something to work with.=20 Also, I don't completely understand the spec. What does it mean to increme= nt "4 bit"? Does that mean to increment by 4, or to increment the fourth b= it, i.e. by 16? Is the clock 1 Hz? =20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:47 2024 X-Received: by 2002:ac8:c86:: with SMTP id n6mr2337275qti.345.1566519430088; Thu, 22 Aug 2019 17:17:10 -0700 (PDT) X-Received: by 2002:a25:ba90:: with SMTP id s16mr1206844ybg.507.1566519429704; Thu, 22 Aug 2019 17:17:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!f14no6146338qtq.0!news-out.google.com!d29ni2576qtg.1!nntp.google.com!f14no6146331qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Aug 2019 17:17:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2600:1012:b162:fc09:6262:df0a:9d06:5885; posting-account=96toEwoAAAAj_H6Uvl-DoCJyQg6KZtGq NNTP-Posting-Host: 2600:1012:b162:fc09:6262:df0a:9d06:5885 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <238fc3a6-c97e-42d9-b215-2e2d1d0eae28@googlegroups.com> Subject: What happened to the osvvm website!? From: Reuven Injection-Date: Fri, 23 Aug 2019 00:17:10 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 2 Xref: reader01.eternal-september.org comp.lang.vhdl:9546 When I attempt to go-to osvvm.org, I message says the account is suspended. Does anyone (Jim Lewis?) Know when this sure will be up again? Reuven paley From newsfish@newsfish Thu Aug 1 00:44:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx40.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: What happened to the osvvm website!? Newsgroups: comp.lang.vhdl References: <238fc3a6-c97e-42d9-b215-2e2d1d0eae28@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <238fc3a6-c97e-42d9-b215-2e2d1d0eae28@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190822-6, 22/08/2019), Outbound message X-Antivirus-Status: Clean Lines: 9 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Fri, 23 Aug 2019 07:04:18 UTC Organization: virginmedia.com Date: Fri, 23 Aug 2019 08:04:16 +0100 X-Received-Bytes: 1311 X-Received-Body-CRC: 3021337252 Xref: reader01.eternal-september.org comp.lang.vhdl:9547 On 23/08/2019 01:17, Reuven wrote: > When I attempt to go-to osvvm.org, I message says the account is suspended. Does anyone (Jim Lewis?) Know when this sure will be up again? > > Reuven paley > The site is owned by Aldec and Jim already notified them of the issue, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:48 2024 X-Received: by 2002:ac8:4988:: with SMTP id f8mr5604526qtq.2.1566575931972; Fri, 23 Aug 2019 08:58:51 -0700 (PDT) X-Received: by 2002:a81:4801:: with SMTP id v1mr3892158ywa.105.1566575931596; Fri, 23 Aug 2019 08:58:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!f14no8260071qtq.0!news-out.google.com!q13ni1029qtn.0!nntp.google.com!f14no8260060qtq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 23 Aug 2019 08:58:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2600:1702:4360:4b70:3120:66c4:b7f3:427d; posting-account=96toEwoAAAAj_H6Uvl-DoCJyQg6KZtGq NNTP-Posting-Host: 2600:1702:4360:4b70:3120:66c4:b7f3:427d References: <238fc3a6-c97e-42d9-b215-2e2d1d0eae28@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5d343929-ff35-45ec-b04b-8dafe1fc5e4c@googlegroups.com> Subject: Re: What happened to the osvvm website!? From: Reuven Injection-Date: Fri, 23 Aug 2019 15:58:51 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9548 Thank you for responding Hans From newsfish@newsfish Thu Aug 1 00:44:48 2024 X-Received: by 2002:aed:22d3:: with SMTP id q19mr17091745qtc.101.1567190205668; Fri, 30 Aug 2019 11:36:45 -0700 (PDT) X-Received: by 2002:a25:550a:: with SMTP id j10mr12678324ybb.106.1567190205422; Fri, 30 Aug 2019 11:36:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.usenet.farm!feed.usenet.farm!newsreader4.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!a13no10158713qtd.0!news-out.google.com!d29ni54qtg.1!nntp.google.com!a13no10158710qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Aug 2019 11:36:45 -0700 (PDT) In-Reply-To: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.205.83.167; posting-account=dxdUwwoAAAC9GWVUgihc3u5gmh-STT4K NNTP-Posting-Host: 62.205.83.167 References: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <253cd7c9-3753-4fa2-9738-6e3905153c73@googlegroups.com> Subject: Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI OMICIDA A From: TIAZZERAIRISPARMI PAOLO BARRAI TRUFFAVIABITCOIN Injection-Date: Fri, 30 Aug 2019 18:36:45 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 19704 X-Received-Body-CRC: 4098025688 Xref: reader01.eternal-september.org comp.lang.vhdl:9549 IL BESTIONE CRIMINALE PAOLO BARRAI (FACEBOOK) E' INDAGATO AL MOMENTO DALLA = PROCURA DI MILANO, COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD DI L= ONDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI .........................................= ....... https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ MI PRESENTO. SONO ANDREAS NIGG VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN BANK ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK= VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, ALLORCHE' COMPRAMMO LA = EX FINTER BANK ZURICH DEI MASSONI NAZISTI E LEGHISTI PESENTI, IO IN PERSONA= , ANDREAS NIGG, ORDIANI DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI A STA BE= STIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL 28.6.19= 65. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA E CAMORRA, DA LONTANO 3.= 000 KM. MUMBLE, MUMBLE, MUMBLE... SONO SVIZZERO, ICH BIN SCHWEIZER, QUINDI SONO UN = UOMO PRECISO. AMO LA PRECISIONE. PER VIA DI QUESTO, ANALIZZIAMO BEN BENE, O= GNI CONCETTO, DA ORA IN AVANTI, PLEASE! DICEVAMO..... L'ASSASSINO PEDOFILO PAOLO BARRAI, ANCHE NEL 2019, FA CRIMINI TERRIFICANTI = PIU' CHE MAI! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STUPR= A ED AMMAZZA TANTI BAMBINI. HA RICICLATO EURO ASSASSINI DI NDRANGHETA IN MA= LAVITOSISSIMA ICO EIDOO!!!!!!!!!!!!!!!!!!!! E' STATO CACCIATO DA CITIBANK E= FATTO CONDANNARE A GALERA DA CITIBANK! HA FATTO FILM PEDOPORNOGRAFICI, STU= PRANDO QUASI A MORTE TANTI BAMBINI! HA UCCISO LUI STESSO, TANTI BAMBINI, PE= R PRENDER I LORO ORGANI E TRAFFICARLI! HA FATTO FILM PORNO CON CAVALLI, BEV= ENDO LITRI DI SPERMA EQUINO! E' STATO MULTATO DA CONSOB BEN 70.000 EURO! HA= 23 CAUSE, CON GENTE DI MEZZA DITTATURA FASCIOMAFIOSA DI BERLUSCONIA, A CUI= HA AZZERATO I RISPARMI! PER SCAPPARE ALLE QUALI, SI E' ORA RIFUGIATO A LON= DRA, OVE FA TANTI POMPINI AL NAZISTA NIGEL FARAGE AFFINCHE' LO PROTEGGA! E'= STATO CONDANNATO AL CARCERE IN BRASILE, ANCHE PER PEDERASTIA VIOLENTA ( E = PER ALTRI TANTISSIMI CRIMINI)! NON NE AZZECCA MAI MEZZA UNA IN BORSA, OVE A= ZZERA I RISPARMI DI TUTTI E SEMPRE! E VI E' TANTISSIMO PIU', DI CUI SCRIVER= EMO FINO A 15 MINUTI DOPO LA NOSTRA MORTE! E' DA ARRESTARE IMMEDIATAMENTE: PAOLO BARRAI (CRYPTOPOLIS E CRYPTOLAB)! E' = STATO IL REGISTA CRIMINALE DELL'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER = LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO P= AOLO BARRAI, ABITAVA A MILANO, IN VIA.......... IPPODROMO 105 (ZONA SAN SIR= O- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEG= A ASSASSINI GIULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 From newsfish@newsfish Thu Aug 1 00:44:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: silverdr Newsgroups: comp.lang.vhdl Subject: Re: GALs and VHDL Date: Sun, 1 Sep 2019 18:12:51 +0200 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <5d2ad8b4-2c78-4041-9d0e-8cbf6f05ecc0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: reader02.eternal-september.org; posting-host="8949fee4d2381b819dfc9182b2117af3"; logging-data="8524"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+vuclunnDUTSHtmtVHx2KeAT6F7MBW9SM=" User-Agent: Unison/2.2 Cancel-Lock: sha1:DmbVtvYeHiGOEu9Qw76Fp4dz5kI= Xref: reader01.eternal-september.org comp.lang.vhdl:9550 On 2018-06-13 03:02:50 +0000, abner.diaz@ieee.org said: > On Wednesday, June 15, 2016 at 9:41:35 AM UTC-6, silverdr wrote: >> So far I downloaded and installed the ispLEVER from Lattice, which is >> still available and supports "obsolete" devices like GALs. The problem >> is that when I try to do some synthesis using >> ispLEVER/PureVHDL/Synplify/ project I get output like: >> >> ******* >> Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl >> -target ispGAL -pro ' >> >> >> Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights >> reserved. >> Version : 2.0.00.17.20.15 >> >> Done sucessfully with exit code 1. >> Error output EDIF file c:/documents and settings/silverdr/my >> documents/sources/vhdl/r512/r512vhdl.edi >> Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 >> >> Done: failed with exit code: 0002. >> ******* >> > > I have the same problem... when I do Synthesize there appears the next error: > Error output EDIF file c:/isplever_classic2_0/examples/ESumRes.edi > Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 > > ... > How did you fix it? After spending indecent amount of time trying to troubleshoot the problem, insrtalling, reinstalling, and exchanging emails with friendly people from Lattice, I worked the issue around by running the software in question in a Wine based Windows emulation. As strange as it may sound, that was the best option for me but below is a summary of my "research" on the subject: - Windows XP Home SP2 (fresh install) – no luck - Windows XP Pro SP3 (fresh install and available updates) – no luck - Wine based Windows XP emulation – runs (sic!) - Windows 10 Pro 64 bit installed from scratch in a virtual machine – runs - Windows 10 Pro 32 bit installed from scratch in a virtual machine - runs Looks like there's some kind of problem with "native" Windows XP support. From newsfish@newsfish Thu Aug 1 00:44:49 2024 X-Received: by 2002:a37:8547:: with SMTP id h68mr3782491qkd.219.1567359062164; Sun, 01 Sep 2019 10:31:02 -0700 (PDT) X-Received: by 2002:a25:83c5:: with SMTP id v5mr18414008ybm.113.1567359061965; Sun, 01 Sep 2019 10:31:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.fr7!futter-mich.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no131152qtl.0!news-out.google.com!d29ni287qtg.1!nntp.google.com!o24no131144qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Sep 2019 10:31:01 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.255.146.86; posting-account=FiJOqwoAAABTa9aMB9-1UUgsWPfCZi5j NNTP-Posting-Host: 5.255.146.86 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <082aadbf-fb3c-4c0c-b52f-c615c8fe025c@googlegroups.com> Subject: LA BESTIA CRIMINALISSIMA PAOLO BARRAI (FACEBOOK) E' INDAGATO, AL MOMENTO, DALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD LONDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI ..... From: RICICLASOLDIMAFIOSI PAOLO BARRAI ORDINATANTIOMICID Injection-Date: Sun, 01 Sep 2019 17:31:02 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 19567 X-Received-Body-CRC: 2551224402 Lines: 289 Xref: reader01.eternal-september.org comp.lang.vhdl:9551 LA BESTIA CRIMINALISSIMA PAOLO BARRAI (FACEBOOK) E' INDAGATO, AL MOMENTO, D= ALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD= LONDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI .........................................= ....... https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ MI PRESENTO. SONO ANDREAS NIGG VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN BANK ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK= VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, ALLORCHE' COMPRAMMO LA = EX FINTER BANK ZURICH DEI MASSONI NAZISTI E LEGHISTI PESENTI, IO IN PERSONA= , ANDREAS NIGG, ORDIANI DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI A STA BE= STIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL 28.6.19= 65. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA E CAMORRA, DA LONTANO 3.= 000 KM. MUMBLE, MUMBLE, MUMBLE... SONO SVIZZERO, ICH BIN SCHWEIZER, QUINDI SONO UN = UOMO PRECISO. AMO LA PRECISIONE. PER VIA DI QUESTO, ANALIZZIAMO BEN BENE, O= GNI CONCETTO, DA ORA IN AVANTI, PLEASE! DICEVAMO..... L'ASSASSINO PEDOFILO PAOLO BARRAI, ANCHE NEL 2019, FA CRIMINI TERRIFICANTI = PIU' CHE MAI! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STUPR= A ED AMMAZZA TANTI BAMBINI. HA RICICLATO EURO ASSASSINI DI NDRANGHETA IN MA= LAVITOSISSIMA ICO EIDOO!!!!!!!!!!!!!!!!!!!! E' STATO CACCIATO DA CITIBANK E= FATTO CONDANNARE A GALERA DA CITIBANK! HA FATTO FILM PEDOPORNOGRAFICI, STU= PRANDO QUASI A MORTE TANTI BAMBINI! HA UCCISO LUI STESSO, TANTI BAMBINI, PE= R PRENDER I LORO ORGANI E TRAFFICARLI! HA FATTO FILM PORNO CON CAVALLI, BEV= ENDO LITRI DI SPERMA EQUINO! E' STATO MULTATO DA CONSOB BEN 70.000 EURO! HA= 23 CAUSE, CON GENTE DI MEZZA DITTATURA FASCIOMAFIOSA DI BERLUSCONIA, A CUI= HA AZZERATO I RISPARMI! PER SCAPPARE ALLE QUALI, SI E' ORA RIFUGIATO A LON= DRA, OVE FA TANTI POMPINI AL NAZISTA NIGEL FARAGE AFFINCHE' LO PROTEGGA! E'= STATO CONDANNATO AL CARCERE IN BRASILE, ANCHE PER PEDERASTIA VIOLENTA ( E = PER ALTRI TANTISSIMI CRIMINI)! NON NE AZZECCA MAI MEZZA UNA IN BORSA, OVE A= ZZERA I RISPARMI DI TUTTI E SEMPRE! E VI E' TANTISSIMO PIU', DI CUI SCRIVER= EMO FINO A 15 MINUTI DOPO LA NOSTRA MORTE! E' DA ARRESTARE IMMEDIATAMENTE: PAOLO BARRAI (CRYPTOPOLIS E CRYPTOLAB)! E' = STATO IL REGISTA CRIMINALE DELL'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER = LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO P= AOLO BARRAI, ABITAVA A MILANO, IN VIA.......... IPPODROMO 105 (ZONA SAN SIR= O- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEG= A ASSASSINI GIULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 From newsfish@newsfish Thu Aug 1 00:44:49 2024 X-Received: by 2002:a05:620a:234:: with SMTP id u20mr4098570qkm.11.1567372231102; Sun, 01 Sep 2019 14:10:31 -0700 (PDT) X-Received: by 2002:a25:6c84:: with SMTP id h126mr4587008ybc.144.1567372230901; Sun, 01 Sep 2019 14:10:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no661400qtl.0!news-out.google.com!d29ni305qtg.1!nntp.google.com!o24no661394qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Sep 2019 14:10:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.70.165.75; posting-account=OWa_qgoAAAByFR78NrlkARoVlD1rqOJB NNTP-Posting-Host: 86.70.165.75 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7458e8b2-4059-45cf-a6ed-375670450d8d@googlegroups.com> Subject: Re: Microsemi Libero on Linux From: the.yasep@gmail.com Injection-Date: Sun, 01 Sep 2019 21:10:31 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9552 Hi Rob, I am a "true Linux" fanboy but due to this kind of "adventures" (with Liber= o, Xilinx & Actel to name a few) I'm forced to keep a Windows box alive for= these sorts of SW only. With NO internet access, and being seldom used, th= ese systems are quite stable, though there are still issues in the beginnin= g. Once it works, I don't touch it anymore. And Libero has been the least o= ffending IDE of the bunch. I have some Lattice and Xilinx tools that a frie= nd helped me to install, Atera could never get to a working state... Anyway I stick to the ProASIC3 family for "experimental reasons" :-) Good luck ! From newsfish@newsfish Thu Aug 1 00:44:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.unit0.net!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx35.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: What happened to the osvvm website!? Newsgroups: comp.lang.vhdl References: <238fc3a6-c97e-42d9-b215-2e2d1d0eae28@googlegroups.com> <5d343929-ff35-45ec-b04b-8dafe1fc5e4c@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <5d343929-ff35-45ec-b04b-8dafe1fc5e4c@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190906-0, 06/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 11 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Fri, 06 Sep 2019 09:37:57 UTC Organization: virginmedia.com Date: Fri, 6 Sep 2019 10:37:58 +0100 X-Received-Bytes: 1365 X-Received-Body-CRC: 2313820250 Xref: reader01.eternal-september.org comp.lang.vhdl:9553 On 23/08/2019 16:58, Reuven wrote: > Thank you for responding Hans > It is still down which indicates this is not a simple "forgot to pay the hosting company" issue. I am always worried when a commercial company is in charge of an open source project (or it website). Still I do appreciate and thanks Aldec paying for it for the past few years. Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:50 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx12.am4.POSTED!not-for-mail Newsgroups: comp.lang.vhdl X-Mozilla-News-Host: news://news.virginmedia.com:119 Reply-To: hans64@htminuslab.com From: HT-Lab Subject: IEEE Std 1076-2019 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190906-0, 06/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 9 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Fri, 06 Sep 2019 09:47:03 UTC Organization: virginmedia.com Date: Fri, 6 Sep 2019 10:47:03 +0100 X-Received-Bytes: 1213 X-Received-Body-CRC: 371602299 Xref: reader01.eternal-september.org comp.lang.vhdl:9554 For those of you who are not on the VHDL-200X mailing list it looks like IEEE has finally ratified VHDL2019, it is now an official IEEE standard: IEEE Std 1076-2019 Thanks to Jim Lewis and the volunteers for all the hard work and not giving up under all the SV pressure ;-) Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:50 2024 X-Received: by 2002:ac8:7192:: with SMTP id w18mr8287251qto.361.1567789252323; Fri, 06 Sep 2019 10:00:52 -0700 (PDT) X-Received: by 2002:a25:550a:: with SMTP id j10mr7391859ybb.106.1567789252173; Fri, 06 Sep 2019 10:00:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no5648207qtl.0!news-out.google.com!c11ni159qtp.0!nntp.google.com!o24no5648197qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Sep 2019 10:00:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: IEEE Std 1076-2019 From: Rick C Injection-Date: Fri, 06 Sep 2019 17:00:52 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9555 On Friday, September 6, 2019 at 5:47:05 AM UTC-4, HT-Lab wrote: > For those of you who are not on the VHDL-200X mailing list it looks like= =20 > IEEE has finally ratified VHDL2019, it is now an official IEEE standard:= =20 > IEEE Std 1076-2019 >=20 > Thanks to Jim Lewis and the volunteers for all the hard work and not=20 > giving up under all the SV pressure ;-) >=20 > Hans > www.ht-lab.com Interesting. I wonder what the impacts will be. =20 64 bit integer. Seems like this is the default, not an option to be specif= ied. I expect this will have an impact on some code that works with the 32= bit default. Much like in other languages which don't specify the size of= integer data types, rather just minimums, I expect coding will change in V= HDL to make all use of integers work with ranges (other than 64 bit integer= s of course). So if you had assumed 32 bits, you will need to specify a su= b-type with a 32 bit integer range. I suppose this won't break code but it= can result in wasteful additional resources used.=20 Conditional compilation sounds useful.=20 I wonder which features will be supported in tools first? I wonder which f= eatures will be supported at all?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:51 2024 X-Received: by 2002:a05:620a:14a1:: with SMTP id x1mr14298178qkj.373.1567859709912; Sat, 07 Sep 2019 05:35:09 -0700 (PDT) X-Received: by 2002:a25:bb0e:: with SMTP id z14mr9479789ybg.507.1567859709729; Sat, 07 Sep 2019 05:35:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no8328029qtl.0!news-out.google.com!c11ni261qtp.0!nntp.google.com!o24no8328017qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Sep 2019 05:35:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.70.165.170; posting-account=OWa_qgoAAAByFR78NrlkARoVlD1rqOJB NNTP-Posting-Host: 86.70.165.170 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> Subject: VHDL'2019 is ratified ! From: the.yasep@gmail.com Injection-Date: Sat, 07 Sep 2019 12:35:09 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9556 Jim Lewis shared the news : IEEE Std 1076-2019 has been approved by the IEEE SASB today. What a ride it was ! I'm still frustrated by the crazy process and the refusal of my own tiny feature request but it's good to see that venerable language still moving forward and kicking Verilog's ass ;-) yg From newsfish@newsfish Thu Aug 1 00:44:51 2024 X-Received: by 2002:ae9:f703:: with SMTP id s3mr13740012qkg.74.1567859936440; Sat, 07 Sep 2019 05:38:56 -0700 (PDT) X-Received: by 2002:a0d:d850:: with SMTP id a77mr9551233ywe.90.1567859936317; Sat, 07 Sep 2019 05:38:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no8336739qtl.0!news-out.google.com!c11ni261qtp.0!nntp.google.com!o24no8336730qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Sep 2019 05:38:56 -0700 (PDT) In-Reply-To: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.70.165.170; posting-account=OWa_qgoAAAByFR78NrlkARoVlD1rqOJB NNTP-Posting-Host: 86.70.165.170 References: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <03a77f5d-0041-4775-92af-3868378fee95@googlegroups.com> Subject: Re: VHDL'2019 is ratified ! From: the.yasep@gmail.com Injection-Date: Sat, 07 Sep 2019 12:38:56 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9557 WOOOooooops ! Hans reported it yesterday :-D From newsfish@newsfish Thu Aug 1 00:44:51 2024 X-Received: by 2002:a37:8547:: with SMTP id h68mr15201766qkd.219.1567886943141; Sat, 07 Sep 2019 13:09:03 -0700 (PDT) X-Received: by 2002:a0d:e8cb:: with SMTP id r194mr11064833ywe.96.1567886942682; Sat, 07 Sep 2019 13:09:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no9375939qtl.0!news-out.google.com!d29ni999qtg.1!nntp.google.com!o24no9375934qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Sep 2019 13:09:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=100.19.79.197; posting-account=h5h-SwoAAADcc_e83pZ0Y3HaAOZ8ZvpK NNTP-Posting-Host: 100.19.79.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: PipelineC (again), dct example, looking for help/interest From: Julian Kemmerer Injection-Date: Sat, 07 Sep 2019 20:09:03 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9558 Hi folks looking for feedback on PipelineC. Ideas of what to implement next= . I will point you to a recent reddit post which ultimately points to GitHub. https://www.reddit.com/r/FPGA/comments/d0x2p5/serial_8x8_dct_in_pipelinec_l= ower_resource_usage/ Here is the code to get you interested: // This is the unrolled version of the original dct copy-and-pasted algorit= hm // https://www.geeksforgeeks.org/discrete-cosine-transform-algorithm-progra= m/ // PipelineC iterations of dctTransformUnrolled are used // to unroll the calculation serially in O(n^4) time // Input 'matrix' and start=3D1 to begin calculation // Input 'matrix' must stay constant until return .done // 'sum' accumulates over iterations/clocks and should be pipelined // So 'sum' must be a volatile global variable // Keep track of when sum is valid and be read+written volatile uint1_t dct_volatiles_valid; // sum will temporarily store the sum of cosine signals volatile float dct_sum; // dct_result will store the discrete cosine transform // Signal that this is the iteration containing the 'done' result=20 typedef struct dct_done_t { float matrix[DCT_M][DCT_N]; uint1_t done; } dct_done_t; volatile dct_done_t dct_result; dct_done_t dctTransformUnrolled(dct_pixel_t matrix[DCT_M][DCT_N], uint1_t s= tart) { // Assume not done yet dct_result.done =3D 0; =09 // Start validates volatiles if(start) { dct_volatiles_valid =3D 1; } =09 // Global func to handle getting to BRAM // 1) Lookup constants from BRAM (using iterators) // 2) Increment iterators // Returns next iterators and constants and will increment when requested dct_lookup_increment_t lookup_increment; uint1_t do_increment; // Only increment when volatiles valid do_increment =3D dct_volatiles_valid; lookup_increment =3D dct_lookup_increment(do_increment); =09 // Unpack struct for ease of reading calculation code below float const_val; const_val =3D lookup_increment.lookup.const_val; float cos_val; cos_val =3D lookup_increment.lookup.cos_val; dct_iter_t i; i =3D lookup_increment.incrementer.curr_iters.i; dct_iter_t j; j =3D lookup_increment.incrementer.curr_iters.j; dct_iter_t k; k =3D lookup_increment.incrementer.curr_iters.k; dct_iter_t l; l =3D lookup_increment.incrementer.curr_iters.l; uint1_t reset_k; reset_k =3D lookup_increment.incrementer.increment.reset_k; uint1_t reset_l; reset_l =3D lookup_increment.incrementer.increment.reset_l; uint1_t done; done =3D lookup_increment.incrementer.increment.done; =09 =09 // Do math for this volatile iteration only when // can safely read+write volatiles if(dct_volatiles_valid) { // ~~~ The primary calculation ~~~: // 1) Float * cosine constant from lookup table =20 float dct1; dct1 =3D (float)matrix[k][l] * cos_val; // 2) Increment sum dct_sum =3D dct_sum + dct1; // 3) constant * Float and assign into the output matrix dct_result.matrix[i][j] =3D const_val * dct_sum; =09 // Sum accumulates during the k and l loops // So reset when they are rolling over if(reset_k & reset_l) { dct_sum =3D 0.0; } =09 // Done yet? dct_result.done =3D done; =09 // Reset volatiles once done if(done) { dct_volatiles_valid =3D 0; } } =09 return dct_result; } What does this synthesize to? Essentially a state machine where each state uses the same N clocks worth o= f logic to do work. (the body of dctTransformUnrolled). Consider the 'execution' of the function in time order. The logic consists = of: ~17% of time for getting lookup constants & incrementing the iterators (dct= _lookup_increment), reading the [k][l] value out of input 'matrix' ~21% of time for the 1) Float * cosine constant from lookup table, a floati= ng point multiplier ~34% of time for the 2) Increment sum addition, a floating point adder ~21% of time for the 3) constant * Float, a floating point multiplier ~5% of time for the 3) assignment into the output matrix at [i][j] That pipeline takes some fixed number of clock cycles N. That means every N= clock cycles 'dct_volatiles_valid' will =3D1 (after being set at the start= ). The algorithm unrolls as O(n^4) for 4096 total iterations. So the total = latency in clock cycles is N * 4096. From newsfish@newsfish Thu Aug 1 00:44:52 2024 X-Received: by 2002:a37:c206:: with SMTP id i6mr16849794qkm.114.1567908859079; Sat, 07 Sep 2019 19:14:19 -0700 (PDT) X-Received: by 2002:a25:550a:: with SMTP id j10mr11804073ybb.106.1567908858911; Sat, 07 Sep 2019 19:14:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no10168804qtl.0!news-out.google.com!d29ni1063qtg.1!nntp.google.com!o24no10168792qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Sep 2019 19:14:18 -0700 (PDT) In-Reply-To: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:147:4002:f4bf:9560:3b2b:142f:1cfa; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:9560:3b2b:142f:1cfa References: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4fcc9eb1-149a-4cfb-922f-5b5d2e851f98@googlegroups.com> Subject: Re: VHDL'2019 is ratified ! From: Rick C Injection-Date: Sun, 08 Sep 2019 02:14:19 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 16 Xref: reader01.eternal-september.org comp.lang.vhdl:9559 On Saturday, September 7, 2019 at 8:35:11 AM UTC-4, the....@gmail.com wrote: > Jim Lewis shared the news : > > IEEE Std 1076-2019 has been approved by the IEEE SASB today. > > What a ride it was ! > > I'm still frustrated by the crazy process and the refusal of my own tiny feature request but it's good to see that venerable language still moving forward and kicking Verilog's ass ;-) I wish they had waited a few more months. VHDL-2020 sounds so much more futuristic. ;) -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!2.eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx15.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: IEEE Std 1076-2019 Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190907-4, 07/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 55 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Mon, 09 Sep 2019 18:36:20 UTC Organization: virginmedia.com Date: Mon, 9 Sep 2019 19:36:20 +0100 X-Received-Bytes: 3162 X-Received-Body-CRC: 2986843836 Xref: reader01.eternal-september.org comp.lang.vhdl:9560 On 06/09/2019 18:00, Rick C wrote: > On Friday, September 6, 2019 at 5:47:05 AM UTC-4, HT-Lab wrote: >> For those of you who are not on the VHDL-200X mailing list it looks like >> IEEE has finally ratified VHDL2019, it is now an official IEEE standard: >> IEEE Std 1076-2019 >> >> Thanks to Jim Lewis and the volunteers for all the hard work and not >> giving up under all the SV pressure ;-) >> >> Hans >> www.ht-lab.com > > Interesting. I wonder what the impacts will be. I suspect very little to start with but I am hoping Jim Lewis will create again one of his VHDL presentations which will point out all the goodies. > > 64 bit integer. Seems like this is the default, not an option to be specified. I expect this will have an impact on some code that works with the 32 bit default. I assume vendors will keep the same behaviour unless the user specifies VHDL2019. Much like in other languages which don't specify the size of integer data types, rather just minimums, I expect coding will change in VHDL to make all use of integers work with ranges (other than 64 bit integers of course). So if you had assumed 32 bits, you will need to specify a sub-type with a 32 bit integer range. I suppose this won't break code but it can result in wasteful additional resources used. > > Conditional compilation sounds useful. I fully agree, I know a lot of engineers advocate that pragma's lead to spaghetti code as seen in C/C++ and other languages but to have zero support is no solution either. I use a home grown preprocessor on my code for many years and it made my life a lot easier not to mention reduced the number of synthesis warning. > > I wonder which features will be supported in tools first? I wonder which features will be supported at all? Aldec's Riviera apparently already supports some features, not sure which one but the preprocessor is probably the simplest one as they can lift it straight from SV. Perhaps a Riviera user can confirm this? Hans www.ht-lab.com I wonder which features will be supported at all? > From newsfish@newsfish Thu Aug 1 00:44:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx15.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: VHDL'2019 is ratified ! Newsgroups: comp.lang.vhdl References: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> <03a77f5d-0041-4775-92af-3868378fee95@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <03a77f5d-0041-4775-92af-3868378fee95@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190907-4, 07/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 15 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Mon, 09 Sep 2019 18:37:11 UTC Organization: virginmedia.com Date: Mon, 9 Sep 2019 19:37:11 +0100 X-Received-Bytes: 1548 X-Received-Body-CRC: 3322093981 Xref: reader01.eternal-september.org comp.lang.vhdl:9561 On 07/09/2019 13:38, the.yasep@gmail.com wrote: > WOOOooooops ! Hans reported it yesterday :-D > No problem, the more people report it the better. I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that is OK as it looks like VHDL2019 brings the 2 languages closer together (similar to what Accellera did with PSL and SVA). VHDL2019 will have DPI, interfaces and a preprocessor using the same unreadable "`" character as SV does :-( Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:53 2024 X-Received: by 2002:a37:6651:: with SMTP id a78mr3153983qkc.474.1568901672624; Thu, 19 Sep 2019 07:01:12 -0700 (PDT) X-Received: by 2002:a5b:d48:: with SMTP id f8mr6943308ybr.438.1568901672438; Thu, 19 Sep 2019 07:01:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no11231006qtl.0!news-out.google.com!q23ni868qtl.1!nntp.google.com!o24no11231001qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Sep 2019 07:01:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> <03a77f5d-0041-4775-92af-3868378fee95@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL'2019 is ratified ! From: Rick C Injection-Date: Thu, 19 Sep 2019 14:01:12 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9562 On Monday, September 9, 2019 at 2:37:13 PM UTC-4, HT-Lab wrote: > On 07/09/2019 13:38, the.yasep@gmail.com wrote: > > WOOOooooops ! Hans reported it yesterday :-D > >=20 > No problem, the more people report it the better. >=20 > I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that is= =20 > OK as it looks like VHDL2019 brings the 2 languages closer together=20 > (similar to what Accellera did with PSL and SVA). >=20 > VHDL2019 will have DPI, interfaces and a preprocessor using the same=20 > unreadable "`" character as SV does :-( >=20 > Hans > www.ht-lab.com I don't know what that character is. It doesn't seem to be the single quot= e "'". I guess it is "`"... Does that have a name? Google seems to searc= h on it ok. It's called a "grave accent" and has uses in programing, also = called "backquote" or "backtick". =20 I guess I vaguely recall seeing it on keyboards, but I don't recall ever us= ing it for anything in my 45 year career, the only key on the keyboard like= that I think... well, other than SYSRQ I guess. I've at least played with= SYSRQ to see what it does... nothing that I've ever found.=20 --=20 Rick C. + Get 2,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx23.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: VHDL'2019 is ratified ! Newsgroups: comp.lang.vhdl References: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> <03a77f5d-0041-4775-92af-3868378fee95@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190919-0, 19/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 39 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 19 Sep 2019 15:01:10 UTC Organization: virginmedia.com Date: Thu, 19 Sep 2019 16:01:10 +0100 X-Received-Bytes: 2929 X-Received-Body-CRC: 83412757 Xref: reader01.eternal-september.org comp.lang.vhdl:9563 On 19/09/2019 15:01, Rick C wrote: > On Monday, September 9, 2019 at 2:37:13 PM UTC-4, HT-Lab wrote: >> On 07/09/2019 13:38, the.yasep@gmail.com wrote: >>> WOOOooooops ! Hans reported it yesterday :-D >>> >> No problem, the more people report it the better. >> >> I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that is >> OK as it looks like VHDL2019 brings the 2 languages closer together >> (similar to what Accellera did with PSL and SVA). >> >> VHDL2019 will have DPI, interfaces and a preprocessor using the same >> unreadable "`" character as SV does :-( >> >> Hans >> www.ht-lab.com > > I don't know what that character is. It doesn't seem to be the single quote "'". I guess it is "`"... Does that have a name? Google seems to search on it ok. It's called a "grave accent" and has uses in programing, also called "backquote" or "backtick". Yes, I know it from Verilog as the backtick but officially it is called a grave accent (also in the VHDL2019 LRM). I guess the steering group chose that character as it was already used for VHDL encryption and Verilog directives. Also with modern editors you quickly see if you are using the wrong character but still as an old C/ASM programmer I would have preferred '#'. > > I guess I vaguely recall seeing it on keyboards, but I don't recall ever using it for anything in my 45 year career, the only key on the keyboard like that I think... well, other than SYSRQ I guess. I've at least played with SYSRQ to see what it does... nothing that I've ever found. > I vaguely remember you posting that you prefer Verilog over VHDL so you must have used it many times? Perhaps like me your memory is not that great any more. Regards, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: VHDL'2019 is ratified ! Date: Thu, 19 Sep 2019 09:58:59 -0700 Organization: A noiseless patient Spider Lines: 57 Message-ID: References: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> <03a77f5d-0041-4775-92af-3868378fee95@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 19 Sep 2019 16:58:59 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="1a2c04664ac0fc82c46dbdee06e0d52c"; logging-data="1250"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19XjkU2+Tsr76Jhp6mvDOoq" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 Cancel-Lock: sha1:5CXL632mEI0BXCR3PGa0eaApu/Q= In-Reply-To: Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9564 On 9/19/19 8:01 AM, HT-Lab wrote: > On 19/09/2019 15:01, Rick C wrote: >> On Monday, September 9, 2019 at 2:37:13 PM UTC-4, HT-Lab wrote: >>> On 07/09/2019 13:38, the.yasep@gmail.com wrote: >>>> WOOOooooops ! Hans reported it yesterday :-D >>>> >>> No problem, the more people report it the better. >>> >>> I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that is >>> OK as it looks like VHDL2019 brings the 2 languages closer together >>> (similar to what Accellera did with PSL and SVA). >>> >>> VHDL2019 will have DPI, interfaces and a preprocessor using the same >>> unreadable "`" character as SV does :-( >>> >>> Hans >>> www.ht-lab.com >> >> I don't know what that character is.  It doesn't seem to be the single quote >> "'".  I guess it is "`"...  Does that have a name?  Google seems to search on >> it ok.  It's called a "grave accent" and has uses in programing, also called >> "backquote" or "backtick". > > Yes, I know it from Verilog as the backtick but officially it is called a grave > accent (also in the VHDL2019 LRM). I guess the steering group chose that > character as it was already used for VHDL encryption and Verilog directives. > Also with modern editors you quickly see if you are using the wrong character > but still as an old C/ASM programmer I would have preferred '#'. > >> >> I guess I vaguely recall seeing it on keyboards, but I don't recall ever using >> it for anything in my 45 year career, the only key on the keyboard like that I >> think... well, other than SYSRQ I guess.  I've at least played with SYSRQ to >> see what it does... nothing that I've ever found. >> > > I vaguely remember you posting that you prefer Verilog over VHDL so you must > have used it many times? Perhaps like me your memory is not that great any more. > > Regards, > Hans > www.ht-lab.com > > Yep, it's a backtick. Also gets used a lot in shell scripting. I'm not sure if the reason to use it for the encryption directives in VHDL-2008 was that Verilog already uses it, but the decision to use it for other preprocessor sorts of things in VHDL-2019 was definitely driven by the fact that 2008 already "broke the seal" on it. Otherwise we'd have introduced yet another "everything henceforth is special magic" character. One of those is problematic enough, two is simply excessive. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Thu Aug 1 00:44:54 2024 X-Received: by 2002:a0c:ea27:: with SMTP id t7mr684974qvp.103.1568923656523; Thu, 19 Sep 2019 13:07:36 -0700 (PDT) X-Received: by 2002:a0d:d904:: with SMTP id b4mr9193894ywe.366.1568923656355; Thu, 19 Sep 2019 13:07:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no724795qtl.0!news-out.google.com!x7ni1050qtf.0!nntp.google.com!o24no724788qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Sep 2019 13:07:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> <03a77f5d-0041-4775-92af-3868378fee95@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07b83485-fa79-4a8e-91ba-6a507807c046@googlegroups.com> Subject: Re: VHDL'2019 is ratified ! From: Rick C Injection-Date: Thu, 19 Sep 2019 20:07:36 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9565 On Thursday, September 19, 2019 at 11:01:13 AM UTC-4, HT-Lab wrote: > On 19/09/2019 15:01, Rick C wrote: > > On Monday, September 9, 2019 at 2:37:13 PM UTC-4, HT-Lab wrote: > >> On 07/09/2019 13:38, the.yasep@gmail.com wrote: > >>> WOOOooooops ! Hans reported it yesterday :-D > >>> > >> No problem, the more people report it the better. > >> > >> I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that i= s > >> OK as it looks like VHDL2019 brings the 2 languages closer together > >> (similar to what Accellera did with PSL and SVA). > >> > >> VHDL2019 will have DPI, interfaces and a preprocessor using the same > >> unreadable "`" character as SV does :-( > >> > >> Hans > >> www.ht-lab.com > >=20 > > I don't know what that character is. It doesn't seem to be the single = quote "'". I guess it is "`"... Does that have a name? Google seems to s= earch on it ok. It's called a "grave accent" and has uses in programing, a= lso called "backquote" or "backtick". >=20 > Yes, I know it from Verilog as the backtick but officially it is called= =20 > a grave accent (also in the VHDL2019 LRM). I guess the steering group=20 > chose that character as it was already used for VHDL encryption and=20 > Verilog directives. Also with modern editors you quickly see if you are= =20 > using the wrong character but still as an old C/ASM programmer I would=20 > have preferred '#'. >=20 > >=20 > > I guess I vaguely recall seeing it on keyboards, but I don't recall eve= r using it for anything in my 45 year career, the only key on the keyboard = like that I think... well, other than SYSRQ I guess. I've at least played = with SYSRQ to see what it does... nothing that I've ever found. > >=20 >=20 > I vaguely remember you posting that you prefer Verilog over VHDL so you= =20 > must have used it many times? Perhaps like me your memory is not that=20 > great any more. No, the opposite. I know VHDL, I've only played with Verilog.=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:54 2024 X-Received: by 2002:aed:3e8d:: with SMTP id n13mr4504142qtf.116.1568998913593; Fri, 20 Sep 2019 10:01:53 -0700 (PDT) X-Received: by 2002:a25:3a45:: with SMTP id h66mr12061074yba.359.1568998913342; Fri, 20 Sep 2019 10:01:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.alt.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no3689085qtl.0!news-out.google.com!q23ni964qtl.1!nntp.google.com!o24no3689080qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Sep 2019 10:01:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.118.48.1; posting-account=FiJOqwoAAABTa9aMB9-1UUgsWPfCZi5j NNTP-Posting-Host: 188.118.48.1 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: LA BESTIA CRIMINALISSIMA PAOLO BARRAI (FACEBOOK) E' INDAGATA, AL MOMENTO, DALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD LONDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI ..... From: RICICLASOLDIMAFIOSI PAOLO BARRAI ORDINATANTIOMICID Injection-Date: Fri, 20 Sep 2019 17:01:53 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 356 Xref: reader01.eternal-september.org comp.lang.vhdl:9566 LA BESTIA CRIMINALISSIMA PAOLO BARRAI (FACEBOOK) E' INDAGATA, AL MOMENTO, D= ALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD= LONDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. 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NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NAZISTA, MAFIOSO, MEGA ASSASSINO VLADIMIR PUTIN https://www.jornalopcao.com.br/colunas-e-blogs/imprensa/livro-expoe-o-russo= -vladimir-putin-como-chefao-de-regime-assassino-e-corrupto-128511/ - ALLO STALKER VIA INTERNET, NONCHE' EBREO NAZISTA LEONARDO FOA' (COSA CHE = GIA' DIMOSTRA DI CHE TOPO DI FOGNA STO SCRIVENDO). FIGLIO DEL MEGA PEZZO DI= MERDA MARCELLO FOA' CHE STA RENDENDO LA RAI TELEPINOCHET, TELEMUSSOLINI, T= ELE E PURE TELESTEFANODELLECHIAIE - FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFILO M= EGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMENTE^= ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI ERA= NO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) TANTISSIMO PIU', A SEGUIRE, NEI PROSSIMI GIORNI!!!!!!!!!!!!!! - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://citywire.ch/manager/andreas-nigg/d2395 https://ch.linkedin.com/in/andreasnigg?trk=3Dpeople-guest_profile-result-ca= rd_result-card_full-click From newsfish@newsfish Thu Aug 1 00:44:54 2024 X-Received: by 2002:ad4:5445:: with SMTP id h5mr53227qvt.32.1569255892392; Mon, 23 Sep 2019 09:24:52 -0700 (PDT) X-Received: by 2002:a81:7c8a:: with SMTP id x132mr331794ywc.105.1569255892176; Mon, 23 Sep 2019 09:24:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder4.feed.usenet.farm!feed.usenet.farm!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no1729218qtl.0!news-out.google.com!x7ni1498qtf.0!nntp.google.com!o24no1729210qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Sep 2019 09:24:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.118.48.1; posting-account=IrEjCgoAAAD7Xu3yovPq55XCEnUmnODH NNTP-Posting-Host: 188.118.48.1 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: IL BASTARDO CRIMINALE PAOLO BARRAI (FACEBOOK) E' INDAGATO, AL MOMENTO, DALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD LONDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI ........ From: ANDREAS NIGG SAFRA SARASIN NOW-EX BANK VONTOBEL Injection-Date: Mon, 23 Sep 2019 16:24:52 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 23191 X-Received-Body-CRC: 740953175 Xref: reader01.eternal-september.org comp.lang.vhdl:9567 IL BASTARDO CRIMINALE PAOLO BARRAI (FACEBOOK) E' INDAGATO, AL MOMENTO, DALL= A PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD LO= NDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI .........................................= ....... https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit MI PRESENTO. SONO ANDREAS NIGG VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN BANK ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK= VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, ALLORCHE' COMPRAMMO LA = EX FINTER BANK ZURICH DEI MASSONI NAZISTI E LEGHISTI PESENTI, IO IN PERSONA= , ANDREAS NIGG, ORDIANI DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI A STA BE= STIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL 28.6.19= 65. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA E CAMORRA, DA LONTANO 3.= 000 KM. MUMBLE, MUMBLE, MUMBLE... SONO SVIZZERO, ICH BIN SCHWEIZER, QUINDI SONO UN = UOMO PRECISO. AMO LA PRECISIONE. PER VIA DI QUESTO, ANALIZZIAMO BEN BENE, O= GNI CONCETTO, DA ORA IN AVANTI, PLEASE! DICEVAMO..... L'ASSASSINO PEDOFILO PAOLO BARRAI, ANCHE NEL 2019, FA CRIMINI TERRIFICANTI = PIU' CHE MAI! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STUPR= A ED AMMAZZA TANTI BAMBINI. HA RICICLATO EURO ASSASSINI DI NDRANGHETA IN MA= LAVITOSISSIMA ICO EIDOO!!!!!!!!!!!!!!!!!!!! E' STATO CACCIATO DA CITIBANK E= FATTO CONDANNARE A GALERA DA CITIBANK! HA FATTO FILM PEDOPORNOGRAFICI, STU= PRANDO QUASI A MORTE TANTI BAMBINI! HA UCCISO LUI STESSO, TANTI BAMBINI, PE= R PRENDER I LORO ORGANI E TRAFFICARLI! HA FATTO FILM PORNO CON CAVALLI, BEV= ENDO LITRI DI SPERMA EQUINO! E' STATO MULTATO DA CONSOB BEN 70.000 EURO! HA= 23 CAUSE, CON GENTE DI MEZZA DITTATURA FASCIOMAFIOSA DI BERLUSCONIA, A CUI= HA AZZERATO I RISPARMI! PER SCAPPARE ALLE QUALI, SI E' ORA RIFUGIATO A LON= DRA, OVE FA TANTI POMPINI AL NAZISTA NIGEL FARAGE AFFINCHE' LO PROTEGGA! E'= STATO CONDANNATO AL CARCERE IN BRASILE, ANCHE PER PEDERASTIA VIOLENTA ( E = PER ALTRI TANTISSIMI CRIMINI)! NON NE AZZECCA MAI MEZZA UNA IN BORSA, OVE A= ZZERA I RISPARMI DI TUTTI E SEMPRE! E VI E' TANTISSIMO PIU', DI CUI SCRIVER= EMO FINO A 15 MINUTI DOPO LA NOSTRA MORTE! E' DA ARRESTARE IMMEDIATAMENTE: PAOLO BARRAI (CRYPTOPOLIS E CRYPTOLAB)! E' = STATO IL REGISTA CRIMINALE DELL'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER = LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO P= AOLO BARRAI, ABITAVA A MILANO, IN VIA.......... IPPODROMO 105 (ZONA SAN SIR= O- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEG= A ASSASSINI GIULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NAZISTA, MAFIOSO, MEGA ASSASSINO VLADIMIR PUTIN https://www.jornalopcao.com.br/colunas-e-blogs/imprensa/livro-expoe-o-russo= -vladimir-putin-como-chefao-de-regime-assassino-e-corrupto-128511/ - ALLO STALKER VIA INTERNET, NONCHE' EBREO NAZISTA LEONARDO FOA' (COSA CHE = GIA' DIMOSTRA DI CHE TOPO DI FOGNA STO SCRIVENDO). FIGLIO DEL MEGA PEZZO DI= MERDA MARCELLO FOA' CHE STA RENDENDO LA RAI TELEPINOCHET, TELEMUSSOLINI, T= ELE E PURE TELESTEFANODELLECHIAIE - FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFILO M= EGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMENTE^= ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI ERA= NO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) TANTISSIMO PIU', A SEGUIRE, NEI PROSSIMI GIORNI!!!!!!!!!!!!!! - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lu= gano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dell= o Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele= Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://citywire.ch/manager/andreas-nigg/d2395 https://ch.linkedin.com/in/andreasnigg?trk=3Dpeople-guest_profile-result-ca= rd_result-card_full-click From newsfish@newsfish Thu Aug 1 00:44:55 2024 X-Received: by 2002:a37:b041:: with SMTP id z62mr1104366qke.94.1569310979444; Tue, 24 Sep 2019 00:42:59 -0700 (PDT) X-Received: by 2002:a0d:c006:: with SMTP id b6mr879977ywd.96.1569310979237; Tue, 24 Sep 2019 00:42:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no3820785qtl.0!news-out.google.com!x7ni1560qtf.0!nntp.google.com!o24no3820774qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Sep 2019 00:42:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=165.225.84.156; posting-account=bMuEOQoAAACUUr_ghL3RBIi5neBZ5w_S NNTP-Posting-Host: 165.225.84.156 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> Subject: The meaning of code coverage in VHDL From: Maciej Sobczak Injection-Date: Tue, 24 Sep 2019 07:42:59 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 33 Xref: reader01.eternal-september.org comp.lang.vhdl:9568 Hi, my first post here, I'm glad to join the group. I'm a software engineer with interests in embedded designs and I have decid= ed to learn VHDL as a way to broaden my perspective on the world of program= mable devices. My understanding, confirmed by authors of several books that= I have seen so far, is that VHDL programming is a software experience. Thi= s in turn suggests that with respect to quality and verification in the ind= ustrial practice, the software standards should be relevant. All is well un= til we reach the point where the easy analogies break apart - one of such p= oints is the notion of code coverage. Software world has a pretty good understanding of code coverage and of tech= niques to measure it. That is, my 100% object code coverage has a precise m= eaning and I know how to get the evidence that my test suite actually exerc= ises the given design to that extent. This is how I can convince myself, th= e customers, the certification authorities or whoever else, that the softwa= re was done right. But what is the analogy of code coverage in VHDL? I can imagine that when w= e limit the discussion to simulation only, there are no new problems, becau= se the design can be instrumented or the debugger instructed to gather the = coverage traces and this is all software exercise. But the synthesis seems = to be a black box, further concealed by the IP concerns of the toolset and = chip vendor. That is, because the synthesized structures do not necessarily= mirror the VHDL structures, my simulation coverage traces are not necessar= ily indicative of the final coverage in the programmed chip. I short, I'm not testing what I'm selling. I can still run my tests on the = final hardware to keep some level of confidence, but the coverage evidence = is gone. This seems to be against some software quality standards. Is this considered to be an issue? --=20 Maciej Sobczak * http://www.inspirel.com From newsfish@newsfish Thu Aug 1 00:44:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder4.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr1.eu1.usenetexpress.com!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.69.MISMATCH!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx22.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: The meaning of code coverage in VHDL Newsgroups: comp.lang.vhdl References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190923-2, 23/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 69 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Tue, 24 Sep 2019 08:30:05 UTC Organization: virginmedia.com Date: Tue, 24 Sep 2019 09:30:05 +0100 X-Received-Bytes: 4579 X-Received-Body-CRC: 1056753297 Xref: reader01.eternal-september.org comp.lang.vhdl:9569 On 24/09/2019 08:42, Maciej Sobczak wrote: > Hi, my first post here, I'm glad to join the group. > > I'm a software engineer with interests in embedded designs and I have decided to learn VHDL as a way to broaden my perspective on the world of programmable devices. My understanding, confirmed by authors of several books that I have seen so far, is that VHDL programming is a software experience. I would argue against this and would say it is more of a hardware experience, as many engineers will tell you think hardware when you write your RTL. I would say that only languages like untimed C/C++ can be considered more of a software than hardware experience. This in turn suggests that with respect to quality and verification in the industrial practice, the software standards should be relevant. All is well until we reach the point where the easy analogies break apart - one of such points is the notion of code coverage. > > Software world has a pretty good understanding of code coverage and of techniques to measure it. The same applies in the hardware world, Code Coverage has been used for many decades. My first introduction to Code Coverage was nearly 25 years ago with the VN tools. That is, my 100% object code coverage has a precise meaning and I know how to get the evidence that my test suite actually exercises the given design to that extent. This is how I can convince myself, the customers, the certification authorities or whoever else, that the software was done right. Are you sure? I have never used Code Coverage in the software world but Code Coverage is a measure how well your testbench/testfixture is stimulating your design, it tells you nothing if your design is working OK. In the hardware world you have to use functional coverage to answer that questions. > > But what is the analogy of code coverage in VHDL? I can imagine that when we limit the discussion to simulation only, there are no new problems, because the design can be instrumented or the debugger instructed to gather the coverage traces and this is all software exercise. This can also be done one a synthesised/P&R'd design or even on chip. But the synthesis seems to be a black box, further concealed by the IP concerns of the toolset and chip vendor. That is, because the synthesized structures do not necessarily mirror the VHDL structures, my simulation coverage traces are not necessarily indicative of the final coverage in the programmed chip. There are a lots of answers and subtleties to all the points you have raised. However, I would say in general that if you fully validated your synchronous RTL design you can assume that after synthesis and P&R the produce netlist is equivalent to your RTL. If you want to validate the netlist you can use an equivalence checker. This is especially important if additional logic such as TMR, BIST etc is added. One important aspect which might be different from the software world is that 100% Code Coverage is not always achievable. I also expect that there are more Code Coverage metrics in the hardware world than in the software world. We have metrics like path and toggle coverage to name a few. Regards, Hans www.ht-lab.com > I short, I'm not testing what I'm selling. I can still run my tests on the final hardware to keep some level of confidence, but the coverage evidence is gone. This seems to be against some software quality standards. > > Is this considered to be an issue? > From newsfish@newsfish Thu Aug 1 00:44:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx22.iad.POSTED!not-for-mail Subject: Re: The meaning of code coverage in VHDL Newsgroups: comp.lang.vhdl References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> From: Richard Damon User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 30 Message-ID: X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Tue, 24 Sep 2019 07:45:15 -0400 X-Received-Bytes: 3832 X-Received-Body-CRC: 2760785154 Xref: reader01.eternal-september.org comp.lang.vhdl:9570 On 9/24/19 3:42 AM, Maciej Sobczak wrote: > Hi, my first post here, I'm glad to join the group. > > I'm a software engineer with interests in embedded designs and I have decided to learn VHDL as a way to broaden my perspective on the world of programmable devices. My understanding, confirmed by authors of several books that I have seen so far, is that VHDL programming is a software experience. This in turn suggests that with respect to quality and verification in the industrial practice, the software standards should be relevant. All is well until we reach the point where the easy analogies break apart - one of such points is the notion of code coverage. > > Software world has a pretty good understanding of code coverage and of techniques to measure it. That is, my 100% object code coverage has a precise meaning and I know how to get the evidence that my test suite actually exercises the given design to that extent. This is how I can convince myself, the customers, the certification authorities or whoever else, that the software was done right. > > But what is the analogy of code coverage in VHDL? I can imagine that when we limit the discussion to simulation only, there are no new problems, because the design can be instrumented or the debugger instructed to gather the coverage traces and this is all software exercise. But the synthesis seems to be a black box, further concealed by the IP concerns of the toolset and chip vendor. That is, because the synthesized structures do not necessarily mirror the VHDL structures, my simulation coverage traces are not necessarily indicative of the final coverage in the programmed chip. > I short, I'm not testing what I'm selling. I can still run my tests on the final hardware to keep some level of confidence, but the coverage evidence is gone. This seems to be against some software quality standards. > > Is this considered to be an issue? > My first thought on this is that fundamentally, the concept of code coverage just works for HDLs, ultimately it would be great if you can verify that all 'paths' are exercised and tested. The big issue is that the HDL languages are very different than traditional software, as HDLs are at their core, parallel execution vs the sequential execution of traditional software. This makes coverage metrics harder to work with. Part of the issue is that it isn't enough that you have tested every execution 'path' in the form of statements, but that the execution path becomes combinatorial (have you tested all combinations of statements being active). In some ways the testing answer is the same as large software projects, you break it down into smaller pieces which you can build tests for, and verify functionality, then you combine the pieces and perform integration tests. From newsfish@newsfish Thu Aug 1 00:44:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: The meaning of code coverage in VHDL Date: Tue, 24 Sep 2019 12:36:48 -0500 Organization: A noiseless patient Spider Lines: 58 Message-ID: References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 24 Sep 2019 17:36:50 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="2e7b335d0f008bf1eb6d7476739612b5"; logging-data="21959"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+kk2DbZJ+0bst03MBJM+DONC1TKiNWnIY=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:3lZxWpsgwsUK7y1fkIxMkjT3K7c= In-Reply-To: Xref: reader01.eternal-september.org comp.lang.vhdl:9571 On 2019-09-24 06:45, Richard Damon wrote: > On 9/24/19 3:42 AM, Maciej Sobczak wrote: >> Hi, my first post here, I'm glad to join the group. >> >> I'm a software engineer with interests in embedded designs and I have decided to learn VHDL as a way to broaden my perspective on the world of programmable devices. My understanding, confirmed by authors of several books that I have seen so far, is that VHDL programming is a software experience. This in turn suggests that with respect to quality and verification in the industrial practice, the software standards should be relevant. All is well until we reach the point where the easy analogies break apart - one of such points is the notion of code coverage. >> >> Software world has a pretty good understanding of code coverage and of techniques to measure it. That is, my 100% object code coverage has a precise meaning and I know how to get the evidence that my test suite actually exercises the given design to that extent. This is how I can convince myself, the customers, the certification authorities or whoever else, that the software was done right. >> >> But what is the analogy of code coverage in VHDL? I can imagine that when we limit the discussion to simulation only, there are no new problems, because the design can be instrumented or the debugger instructed to gather the coverage traces and this is all software exercise. But the synthesis seems to be a black box, further concealed by the IP concerns of the toolset and chip vendor. That is, because the synthesized structures do not necessarily mirror the VHDL structures, my simulation coverage traces are not necessarily indicative of the final coverage in the programmed chip. >> I short, I'm not testing what I'm selling. I can still run my tests on the final hardware to keep some level of confidence, but the coverage evidence is gone. This seems to be against some software quality standards. >> >> Is this considered to be an issue? >> > > My first thought on this is that fundamentally, the concept of code > coverage just works for HDLs, ultimately it would be great if you can > verify that all 'paths' are exercised and tested. > > The big issue is that the HDL languages are very different than > traditional software, as HDLs are at their core, parallel execution vs > the sequential execution of traditional software. > > This makes coverage metrics harder to work with. Part of the issue is > that it isn't enough that you have tested every execution 'path' in the > form of statements, but that the execution path becomes combinatorial > (have you tested all combinations of statements being active). > > In some ways the testing answer is the same as large software projects, > you break it down into smaller pieces which you can build tests for, and > verify functionality, then you combine the pieces and perform > integration tests. > Richard Damon gave some good answers to your questions, but I'll add a little bit to it. Most commercial logic simulators have a function to give you a first-level coverage report of the thoroughness of your logic simulations. That is, they can give you a report of what percentage of the signals in your circuit switched to both the '1' and '0' logic state at some point in the simulation. But then, as Richard pointed out, you have the question of all possible combinations of those signals. This is usually fairly straight forward for purely combinatorial logic, such as decoders, Galois field adders and multipliers, address decoders, etc. For these you typically write a testbench that instantiates your logic as a Circuit Under Test. The testbench applies all possible combinations of input signals to your circuit, computes what the outputs should be, and compares the expected with the actual results. Once you are satisfied that your HDL is functioning correctly, the mapping to the actual hardware implementation by a synthesis tool is usually not a big concern, at least for logic functionality. There are equivalence checkers that can verify that the two are equivalent. There are also testability analyzers that can verify how thoroughly the logic can be tested and identify redundancies. Charles Bailey From newsfish@newsfish Thu Aug 1 00:44:56 2024 X-Received: by 2002:a0c:9082:: with SMTP id p2mr3842548qvp.197.1569351085975; Tue, 24 Sep 2019 11:51:25 -0700 (PDT) X-Received: by 2002:a25:360a:: with SMTP id d10mr176656yba.133.1569351085768; Tue, 24 Sep 2019 11:51:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no5429814qtl.0!news-out.google.com!x7ni1623qtf.0!nntp.google.com!o24no5429803qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Sep 2019 11:51:25 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.33.54.235; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.33.54.235 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: How to write a correct code to do 2 writes to an array on same cycle? From: Weng Tianxiang Injection-Date: Tue, 24 Sep 2019 18:51:25 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9572 Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1. p1: process(CLK) is begin if CLK'event and CLK = '1' then if C1 then An_Array(a) <= D1; end if; -- I know a /= b -- do I need to inform VHDL compiler of 2 different addresses? if C2 then An_Array(b) <= D2; end if; end if; end process; 2. p2: process(CLK) is begin if CLK'event and CLK = '1' then case C1 & C2 is when "10" => An_Array(a) <= D1; when "01" => An_Array(b) <= D2; when "11" => -- I know a /= b -- do I need to inform VHDL compiler of 2 different addresses? An_Array(a) <= D1; An_Array(b) <= D2; when others => null; end case; end if; end process; I think it is no problem with a simulator. Thank you. Weng From newsfish@newsfish Thu Aug 1 00:44:56 2024 X-Received: by 2002:a05:6214:1463:: with SMTP id c3mr6207908qvy.48.1569396004953; Wed, 25 Sep 2019 00:20:04 -0700 (PDT) X-Received: by 2002:a81:5c57:: with SMTP id q84mr4555898ywb.88.1569396004723; Wed, 25 Sep 2019 00:20:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no7146632qtl.0!news-out.google.com!x7ni1693qtf.0!nntp.google.com!o24no7146621qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Sep 2019 00:20:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=165.225.84.161; posting-account=bMuEOQoAAACUUr_ghL3RBIi5neBZ5w_S NNTP-Posting-Host: 165.225.84.161 References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <467fa0e8-a549-4523-95b5-50fe0d2077e1@googlegroups.com> Subject: Re: The meaning of code coverage in VHDL From: Maciej Sobczak Injection-Date: Wed, 25 Sep 2019 07:20:04 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9573 > Most commercial logic simulators have a function to give you a=20 > first-level coverage report of the thoroughness of your logic=20 > simulations. Yes, this is what I expected - but as already noted, as long as work is kep= t in the software domain, it is a well-understood software exercise, where = everything can be instrumented. It's the transition to hardware that is gen= erating most of the question marks. > Once you are satisfied that your HDL is functioning correctly, the=20 > mapping to the actual hardware implementation by a synthesis tool is=20 > usually not a big concern, at least for logic functionality. There are= =20 > equivalence checkers that can verify that the two are equivalent. And this is the part that I hoped you to confirm. Thanks for your replies t= hey were very instructive. --=20 Maciej Sobczak * http://www.inspirel.com From newsfish@newsfish Thu Aug 1 00:44:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder2.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr3.eu1.usenetexpress.com!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.69.MISMATCH!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx21.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: IEEE Std 1076-2019 Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190925-2, 25/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 22 Message-ID: <6gMiF.412078$RU2.392355@fx21.am4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Wed, 25 Sep 2019 16:06:26 UTC Organization: virginmedia.com Date: Wed, 25 Sep 2019 17:06:27 +0100 X-Received-Bytes: 1742 X-Received-Body-CRC: 1307709224 Xref: reader01.eternal-september.org comp.lang.vhdl:9574 On 06/09/2019 10:47, HT-Lab wrote: > For those of you who are not on the VHDL-200X mailing list it looks like > IEEE has finally ratified VHDL2019, it is now an official IEEE standard: > IEEE Std 1076-2019 > > Thanks to Jim Lewis and the volunteers for all the hard work and not > giving up under all the SV pressure ;-) > > Hans > www.ht-lab.com It has just been pointed out to me that although VHDL2019 is ratified by the IEEE it has not yet been released, this might take some time but hopefully should happen before the end of the year. Note that VHDL2008 was released in 2009. I guess this is the reason why we don't see any press releases, we need to wait until the LRM is printed and be made available to the general public. Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:57 2024 X-Received: by 2002:a05:620a:65d:: with SMTP id a29mr4551434qka.285.1569427975467; Wed, 25 Sep 2019 09:12:55 -0700 (PDT) X-Received: by 2002:a0d:db0d:: with SMTP id d13mr6585444ywe.394.1569427975326; Wed, 25 Sep 2019 09:12:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no8480927qtl.0!news-out.google.com!x7ni1738qtf.0!nntp.google.com!o24no8480922qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Sep 2019 09:12:55 -0700 (PDT) In-Reply-To: <467fa0e8-a549-4523-95b5-50fe0d2077e1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> <467fa0e8-a549-4523-95b5-50fe0d2077e1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d713fbe-ba08-41bc-b210-7b0a9db55109@googlegroups.com> Subject: Re: The meaning of code coverage in VHDL From: Rick C Injection-Date: Wed, 25 Sep 2019 16:12:55 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 39 Xref: reader01.eternal-september.org comp.lang.vhdl:9575 On Wednesday, September 25, 2019 at 3:20:07 AM UTC-4, Maciej Sobczak wrote: > > Most commercial logic simulators have a function to give you a=20 > > first-level coverage report of the thoroughness of your logic=20 > > simulations. >=20 > Yes, this is what I expected - but as already noted, as long as work is k= ept in the software domain, it is a well-understood software exercise, wher= e everything can be instrumented. It's the transition to hardware that is g= enerating most of the question marks. >=20 > > Once you are satisfied that your HDL is functioning correctly, the=20 > > mapping to the actual hardware implementation by a synthesis tool is=20 > > usually not a big concern, at least for logic functionality. There are= =20 > > equivalence checkers that can verify that the two are equivalent. >=20 > And this is the part that I hoped you to confirm. Thanks for your replies= they were very instructive. The mapping to hardware does not limit further testing to actual hardware. = The components inferred in the HDL can be netlisted and simulated as well.= Any code coverage tool that is used on simulated code should be able to h= andle the post synthesis code. =20 What tools are you working with? =20 My designs are not so complex that code coverage tools are required or part= icularly useful. I perform functional simulation which verifies the code i= s doing the job it is asked to do. When I took a class in program manageme= nt the testing was to verify that the requirements are being addressed. If= those tests do not cover some of the code I would ask why that code is in = the code base? Can it not be removed and still pass the requirements testi= ng or was there a failure in the test design?=20 --=20 Rick C. - Get 2,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:57 2024 X-Received: by 2002:a05:620a:4c9:: with SMTP id 9mr4517551qks.235.1569428154162; Wed, 25 Sep 2019 09:15:54 -0700 (PDT) X-Received: by 2002:a25:c54a:: with SMTP id v71mr3409939ybe.319.1569428153955; Wed, 25 Sep 2019 09:15:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder4.feed.usenet.farm!feed.usenet.farm!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no8489185qtl.0!news-out.google.com!x7ni1738qtf.0!nntp.google.com!o24no8489173qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Sep 2019 09:15:53 -0700 (PDT) In-Reply-To: <6gMiF.412078$RU2.392355@fx21.am4> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <6gMiF.412078$RU2.392355@fx21.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: IEEE Std 1076-2019 From: Rick C Injection-Date: Wed, 25 Sep 2019 16:15:54 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 31 X-Received-Bytes: 2547 X-Received-Body-CRC: 1491701548 Xref: reader01.eternal-september.org comp.lang.vhdl:9576 On Wednesday, September 25, 2019 at 12:06:29 PM UTC-4, HT-Lab wrote: > On 06/09/2019 10:47, HT-Lab wrote: > > For those of you who are not on the VHDL-200X mailing list it looks like > > IEEE has finally ratified VHDL2019, it is now an official IEEE standard: > > IEEE Std 1076-2019 > > > > Thanks to Jim Lewis and the volunteers for all the hard work and not > > giving up under all the SV pressure ;-) > > > > Hans > > www.ht-lab.com > > It has just been pointed out to me that although VHDL2019 is ratified by > the IEEE it has not yet been released, this might take some time but > hopefully should happen before the end of the year. Note that VHDL2008 > was released in 2009. > > I guess this is the reason why we don't see any press releases, we need > to wait until the LRM is printed and be made available to the general > public. > > Hans > www.ht-lab.com "Printed"??? Really, they want to "print" the document? Does that take more than 15 minutes? I guess 5 minutes to generate the PDF file and 10 minutes to send it to the printer? -- Rick C. - Get 2,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx04.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: The meaning of code coverage in VHDL Newsgroups: comp.lang.vhdl References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> <467fa0e8-a549-4523-95b5-50fe0d2077e1@googlegroups.com> <7d713fbe-ba08-41bc-b210-7b0a9db55109@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <7d713fbe-ba08-41bc-b210-7b0a9db55109@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190925-2, 25/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 46 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Wed, 25 Sep 2019 16:55:56 UTC Organization: virginmedia.com Date: Wed, 25 Sep 2019 17:55:57 +0100 X-Received-Bytes: 3869 X-Received-Body-CRC: 4027429313 Xref: reader01.eternal-september.org comp.lang.vhdl:9577 On 25/09/2019 17:12, Rick C wrote: > On Wednesday, September 25, 2019 at 3:20:07 AM UTC-4, Maciej Sobczak wrote: >>> Most commercial logic simulators have a function to give you a >>> first-level coverage report of the thoroughness of your logic >>> simulations. >> >> Yes, this is what I expected - but as already noted, as long as work is kept in the software domain, it is a well-understood software exercise, where everything can be instrumented. It's the transition to hardware that is generating most of the question marks. >> >>> Once you are satisfied that your HDL is functioning correctly, the >>> mapping to the actual hardware implementation by a synthesis tool is >>> usually not a big concern, at least for logic functionality. There are >>> equivalence checkers that can verify that the two are equivalent. >> >> And this is the part that I hoped you to confirm. Thanks for your replies they were very instructive. > > The mapping to hardware does not limit further testing to actual hardware. The components inferred in the HDL can be netlisted and simulated as well. Any code coverage tool that is used on simulated code should be able to handle the post synthesis code. There is absolutely no point in running code coverage on a netlist with primitives, the results is meaningless. Perhaps toggle coverage might have some usage to estimate power consumption but even that is generally not recommended (custom tools/functions are more accurate). > > What tools are you working with? > > My designs are not so complex that code coverage tools are required or particularly useful. I find Code Coverage very useful even on a small designs. Any tool that analyses your design (incl synthesis) can tell you something new about your design. Code Coverage is quick and easy to run so why not use it. I have spoken to many engineers who claimed their testbench is perfect and when they run Code Coverage for the first time they always find holes even on small designs. It is very difficult to look at a piece of code and say yep my testbench has fully tested that. The only problem with Code Coverage is that the free tools don't support it which I think is a shame. Hans www.ht-lab.com > I perform functional simulation which verifies the code is doing the job it is asked to do. When I took a class in program management the testing was to verify that the requirements are being addressed. If those tests do not cover some of the code I would ask why that code is in the code base? Can it not be removed and still pass the requirements testing or was there a failure in the test design? > From newsfish@newsfish Thu Aug 1 00:44:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx28.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: IEEE Std 1076-2019 Newsgroups: comp.lang.vhdl References: <6gMiF.412078$RU2.392355@fx21.am4> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190925-2, 25/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 38 Message-ID: <39NiF.266997$665.180799@fx28.am4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Wed, 25 Sep 2019 17:07:11 UTC Organization: virginmedia.com Date: Wed, 25 Sep 2019 18:07:12 +0100 X-Received-Bytes: 2560 X-Received-Body-CRC: 3945419551 Xref: reader01.eternal-september.org comp.lang.vhdl:9578 On 25/09/2019 17:15, Rick C wrote: > On Wednesday, September 25, 2019 at 12:06:29 PM UTC-4, HT-Lab wrote: >> On 06/09/2019 10:47, HT-Lab wrote: >>> For those of you who are not on the VHDL-200X mailing list it looks like >>> IEEE has finally ratified VHDL2019, it is now an official IEEE standard: >>> IEEE Std 1076-2019 >>> >>> Thanks to Jim Lewis and the volunteers for all the hard work and not >>> giving up under all the SV pressure ;-) >>> >>> Hans >>> www.ht-lab.com >> >> It has just been pointed out to me that although VHDL2019 is ratified by >> the IEEE it has not yet been released, this might take some time but >> hopefully should happen before the end of the year. Note that VHDL2008 >> was released in 2009. >> >> I guess this is the reason why we don't see any press releases, we need >> to wait until the LRM is printed and be made available to the general >> public. >> >> Hans >> www.ht-lab.com > > "Printed"??? Really, they want to "print" the document? Does that take more than 15 minutes? I guess 5 minutes to generate the PDF file and 10 minutes to send it to the printer? > Of course printed means a whole range of admin/marketing/bureaucratic tasks, I suspect that even getting the webpage sorted out will take a few weeks. Now an interesting questions is if the IEEE will make the standard freely available like they do for SV/SystemC or paid for like they do for VHDL2008/PSL.....never mind. Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:58 2024 X-Received: by 2002:a37:a411:: with SMTP id n17mr5938898qke.216.1569444340583; Wed, 25 Sep 2019 13:45:40 -0700 (PDT) X-Received: by 2002:a25:8151:: with SMTP id j17mr4154194ybm.188.1569444340380; Wed, 25 Sep 2019 13:45:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no9201670qtl.0!news-out.google.com!q23ni449qtl.1!nntp.google.com!o24no9201667qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Sep 2019 13:45:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> <467fa0e8-a549-4523-95b5-50fe0d2077e1@googlegroups.com> <7d713fbe-ba08-41bc-b210-7b0a9db55109@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2912b02f-f69d-4c1c-b78c-59a142d89000@googlegroups.com> Subject: Re: The meaning of code coverage in VHDL From: Rick C Injection-Date: Wed, 25 Sep 2019 20:45:40 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5252 X-Received-Body-CRC: 1059064049 Xref: reader01.eternal-september.org comp.lang.vhdl:9579 On Wednesday, September 25, 2019 at 12:55:59 PM UTC-4, HT-Lab wrote: > On 25/09/2019 17:12, Rick C wrote: > > On Wednesday, September 25, 2019 at 3:20:07 AM UTC-4, Maciej Sobczak wr= ote: > >>> Most commercial logic simulators have a function to give you a > >>> first-level coverage report of the thoroughness of your logic > >>> simulations. > >> > >> Yes, this is what I expected - but as already noted, as long as work i= s kept in the software domain, it is a well-understood software exercise, w= here everything can be instrumented. It's the transition to hardware that i= s generating most of the question marks. > >> > >>> Once you are satisfied that your HDL is functioning correctly, the > >>> mapping to the actual hardware implementation by a synthesis tool is > >>> usually not a big concern, at least for logic functionality. There a= re > >>> equivalence checkers that can verify that the two are equivalent. > >> > >> And this is the part that I hoped you to confirm. Thanks for your repl= ies they were very instructive. > >=20 > > The mapping to hardware does not limit further testing to actual hardwa= re. The components inferred in the HDL can be netlisted and simulated as w= ell. Any code coverage tool that is used on simulated code should be able = to handle the post synthesis code. >=20 > There is absolutely no point in running code coverage on a netlist with= =20 > primitives, the results is meaningless. Perhaps toggle coverage might=20 > have some usage to estimate power consumption but even that is generally= =20 > not recommended (custom tools/functions are more accurate). Why? The same issue exists, how much of the design does the test simulatio= n actually test? If you want to know how much it covers in simulation of t= he HDL it would be useful to know how much of the design is covered in post= synthesis simulation. =20 > > What tools are you working with? > >=20 > > My designs are not so complex that code coverage tools are required or = particularly useful.=20 >=20 >=20 > I find Code Coverage very useful even on a small designs. Any tool that= =20 > analyses your design (incl synthesis) can tell you something new about=20 > your design. Code Coverage is quick and easy to run so why not use it. > I have spoken to many engineers who claimed their testbench is perfect=20 > and when they run Code Coverage for the first time they always find=20 > holes even on small designs. It is very difficult to look at a piece of= =20 > code and say yep my testbench has fully tested that. >=20 > The only problem with Code Coverage is that the free tools don't support= =20 > it which I think is a shame. As I said, I use a different test technique. Code coverage tells you if th= e tests detect the correct operation of a line of code. It doesn't tell yo= u if the test is the right test or not. That is the part I care about. =20 No point in testing a line of code if that line of code is not doing someth= ing called for in the requirements. =20 We find it much more important to know the coverage of tests performed on h= ardware to verify it is working. In that case the design has already be ve= rified to be a correct design. Now we want to know how much of the design = is actually tested by the tests. Not at all the same thing as code coverag= e since there is not a direct correspondence between hardware and lines of = code.=20 When you find a mismatch between the code and the test coverage of that cod= e, which do you fix, the code or the tests?=20 --=20 Rick C. + Get 2,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:58 2024 X-Received: by 2002:ac8:1302:: with SMTP id e2mr369992qtj.326.1569444590344; Wed, 25 Sep 2019 13:49:50 -0700 (PDT) X-Received: by 2002:a0d:e6cd:: with SMTP id p196mr53750ywe.418.1569444590166; Wed, 25 Sep 2019 13:49:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no9212696qtl.0!news-out.google.com!q23ni449qtl.1!nntp.google.com!o24no9212680qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Sep 2019 13:49:49 -0700 (PDT) In-Reply-To: <39NiF.266997$665.180799@fx28.am4> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <6gMiF.412078$RU2.392355@fx21.am4> <39NiF.266997$665.180799@fx28.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3857366a-7fba-4182-8ce5-be34914bf9d0@googlegroups.com> Subject: Re: IEEE Std 1076-2019 From: Rick C Injection-Date: Wed, 25 Sep 2019 20:49:50 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9580 On Wednesday, September 25, 2019 at 1:07:14 PM UTC-4, HT-Lab wrote: > On 25/09/2019 17:15, Rick C wrote: > > On Wednesday, September 25, 2019 at 12:06:29 PM UTC-4, HT-Lab wrote: > >> On 06/09/2019 10:47, HT-Lab wrote: > >>> For those of you who are not on the VHDL-200X mailing list it looks l= ike > >>> IEEE has finally ratified VHDL2019, it is now an official IEEE standa= rd: > >>> IEEE Std 1076-2019 > >>> > >>> Thanks to Jim Lewis and the volunteers for all the hard work and not > >>> giving up under all the SV pressure ;-) > >>> > >>> Hans > >>> www.ht-lab.com > >> > >> It has just been pointed out to me that although VHDL2019 is ratified = by > >> the IEEE it has not yet been released, this might take some time but > >> hopefully should happen before the end of the year. Note that VHDL2008 > >> was released in 2009. > >> > >> I guess this is the reason why we don't see any press releases, we nee= d > >> to wait until the LRM is printed and be made available to the general > >> public. > >> > >> Hans > >> www.ht-lab.com > >=20 > > "Printed"??? Really, they want to "print" the document? Does that tak= e more than 15 minutes? I guess 5 minutes to generate the PDF file and 10 = minutes to send it to the printer? > > > Of course printed means a whole range of admin/marketing/bureaucratic=20 > tasks, I suspect that even getting the webpage sorted out will take a=20 > few weeks. It would seem to be an inefficient organization that does all that complete= ly serially. =20 > Now an interesting questions is if the IEEE will make the standard=20 > freely available like they do for SV/SystemC or paid for like they do=20 > for VHDL2008/PSL.....never mind. A trick they use with some standards is to take advantage of the fact that = they can release all but the final version. Make some totally insignifican= t change in the final release and the standard version document before that= change can still be freely circulated. A standard that no one reads is no= t of much value.=20 --=20 Rick C. -- Get 2,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:44:58 2024 X-Received: by 2002:a0c:c590:: with SMTP id a16mr1514105qvj.144.1569483829112; Thu, 26 Sep 2019 00:43:49 -0700 (PDT) X-Received: by 2002:a81:4702:: with SMTP id u2mr1613629ywa.53.1569483828884; Thu, 26 Sep 2019 00:43:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no10724391qtl.0!news-out.google.com!x7ni1796qtf.0!nntp.google.com!o24no10724378qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Sep 2019 00:43:48 -0700 (PDT) In-Reply-To: <2912b02f-f69d-4c1c-b78c-59a142d89000@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.9.245.39; posting-account=bMuEOQoAAACUUr_ghL3RBIi5neBZ5w_S NNTP-Posting-Host: 194.9.245.39 References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> <467fa0e8-a549-4523-95b5-50fe0d2077e1@googlegroups.com> <7d713fbe-ba08-41bc-b210-7b0a9db55109@googlegroups.com> <2912b02f-f69d-4c1c-b78c-59a142d89000@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The meaning of code coverage in VHDL From: Maciej Sobczak Injection-Date: Thu, 26 Sep 2019 07:43:49 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9581 > When you find a mismatch between the code and the test coverage of that c= ode, which do you fix, the code or the tests?=20 Both code and tests should be written based on some requirements. If you en= d up with any kind of mismatch between them, then one of them or even both = might need to be fixed, but the only way to tell is to analyze the issue on= a case-by-basis. No up-front rules here are possible, unless you *arbitrar= ily* decide to treat one of these artifacts as primary, for whatever reason= . Still, the information whether there is any mismatch is something that is w= orth having. --=20 Maciej Sobczak * http://www.inspirel.com From newsfish@newsfish Thu Aug 1 00:44:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx40.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: The meaning of code coverage in VHDL Newsgroups: comp.lang.vhdl References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> <467fa0e8-a549-4523-95b5-50fe0d2077e1@googlegroups.com> <7d713fbe-ba08-41bc-b210-7b0a9db55109@googlegroups.com> <2912b02f-f69d-4c1c-b78c-59a142d89000@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <2912b02f-f69d-4c1c-b78c-59a142d89000@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190925-2, 25/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 71 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 26 Sep 2019 09:27:19 UTC Organization: virginmedia.com Date: Thu, 26 Sep 2019 10:27:19 +0100 X-Received-Bytes: 4750 X-Received-Body-CRC: 4267500678 X-Original-Bytes: 4577 Xref: reader01.eternal-september.org comp.lang.vhdl:9582 On 25/09/2019 21:45, Rick C wrote: > On Wednesday, September 25, 2019 at 12:55:59 PM UTC-4, HT-Lab wrote: >> On 25/09/2019 17:12, Rick C wrote: >>> On Wednesday, September 25, 2019 at 3:20:07 AM UTC-4, Maciej Sobczak wrote: .. >> >> There is absolutely no point in running code coverage on a netlist with >> primitives, the results is meaningless. Perhaps toggle coverage might >> have some usage to estimate power consumption but even that is generally >> not recommended (custom tools/functions are more accurate). > > Why? The same issue exists, how much of the design does the test simulation actually test? If you want to know how much it covers in simulation of the HDL it would be useful to know how much of the design is covered in post synthesis simulation. I think you have never used Code Coverage before but that is OK. Consider a simple statement of the form: if (a ='1' or b='1' ) Next assume Conditional Coverage tells you that ab="10" and ab="11" have been recorded. This might be correct or not in which case you change your testbench or seed to hit the "00" and "01" test cases. Statement Coverage might give you 100% coverage even if "b" is stuck at 1, toggle coverage might tell you that "a" went from 0 to 1 but never back to 0 again etc. Now synthesis your design which converts the above RTL into luts, what information are you expected to extract with Code Coverage? and if you do get say 66% coverage what does this tell you? > > >>> What tools are you working with? >>> >>> My designs are not so complex that code coverage tools are required or particularly useful. >> >> .. >> >> The only problem with Code Coverage is that the free tools don't support >> it which I think is a shame. > > As I said, I use a different test technique. Code coverage tells you if the tests detect the correct operation of a line of code. It doesn't tell you if the test is the right test or not. That is the part I care about. You are repeating my words from my original reply. > > No point in testing a line of code if that line of code is not doing something called for in the requirements. > > We find it much more important to know the coverage of tests performed on hardware to verify it is working. In that case the design has already be verified to be a correct design. Now we want to know how much of the design is actually tested by the tests. Not at all the same thing as code coverage since there is not a direct correspondence between hardware and lines of code. You are confusing Functional Coverage with Code Coverage, they are different methods. Code Coverage not only check the quality of your testbench but it also makes you better understand you design. I would suggest you find somebody/client who has access to Code Coverage and use it on one of your design which you think you have fully tested. I will guarantee you will find statements/expressions/conditions/toggles/branches which have not been stimulated. This does not mean your design is faulty but it does mean your testbench was not complete and you have been lucky. > > When you find a mismatch between the code and the test coverage of that code, which do you fix, the code or the tests? > If anybody asks me that question I would politely suggest they hand the design back to the designer and let him run the Code Coverage. Regards, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:44:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!85.12.16.70.MISMATCH!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx16.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: The meaning of code coverage in VHDL Newsgroups: comp.lang.vhdl References: <624d0238-3926-4eaf-9690-f644adf0709e@googlegroups.com> <467fa0e8-a549-4523-95b5-50fe0d2077e1@googlegroups.com> <7d713fbe-ba08-41bc-b210-7b0a9db55109@googlegroups.com> <2912b02f-f69d-4c1c-b78c-59a142d89000@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 190925-2, 25/09/2019), Outbound message X-Antivirus-Status: Clean Lines: 24 Message-ID: <2M%iF.270189$ir6.208972@fx16.am4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 26 Sep 2019 09:44:30 UTC Organization: virginmedia.com Date: Thu, 26 Sep 2019 10:44:31 +0100 X-Received-Bytes: 2453 X-Received-Body-CRC: 62385003 Xref: reader01.eternal-september.org comp.lang.vhdl:9583 On 26/09/2019 08:43, Maciej Sobczak wrote: >> When you find a mismatch between the code and the test coverage of that code, which do you fix, the code or the tests? > > Both code and tests should be written based on some requirements. My experience is that companies do not write requirements for Code Coverage, what they tend to do is to specify a single coverage value. For DO-254 this is normally 100% (which is a real pain and might requires expensive formal tools and lots of waivers if the design is complex). Other companies just say you need at least 100% Statement (not line) and Branch coverage, which I find quite sensible. Regards, Hans. www.ht-lab.com If you end up with any kind of mismatch between them, then one of them or even both might need to be fixed, but the only way to tell is to analyze the issue on a case-by-basis. No up-front rules here are possible, unless you *arbitrarily* decide to treat one of these artifacts as primary, for whatever reason. > Still, the information whether there is any mismatch is something that is worth having. > From newsfish@newsfish Thu Aug 1 00:44:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: How to write a correct code to do 2 writes to an array on same cycle? Date: Thu, 26 Sep 2019 23:25:25 -0500 Organization: A noiseless patient Spider Lines: 62 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 27 Sep 2019 04:25:29 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="70f44d4d6565756c36b00012d9b2336c"; logging-data="12837"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+lGAcUG7/dWoyt08ibo3Yh9FhtP7LTEVg=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:9yJlxxM/Am6G+B6siw56Z7EnKVo= In-Reply-To: Xref: reader01.eternal-september.org comp.lang.vhdl:9584 On 2019-09-24 13:51, Weng Tianxiang wrote: > Hi, > > Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: > > 1. > p1: process(CLK) is > begin > if CLK'event and CLK = '1' then > if C1 then > An_Array(a) <= D1; > end if; > > -- I know a /= b > -- do I need to inform VHDL compiler of 2 different addresses? > if C2 then > An_Array(b) <= D2; > end if; > end if; > end process; > > 2. > p2: process(CLK) is > begin > if CLK'event and CLK = '1' then > case C1 & C2 is > when "10" => > An_Array(a) <= D1; > > when "01" => > An_Array(b) <= D2; > > when "11" => > -- I know a /= b > -- do I need to inform VHDL compiler of 2 different addresses? > An_Array(a) <= D1; > An_Array(b) <= D2; > > when others => > null; > end case; > end if; > end process; > > I think it is no problem with a simulator. > > Thank you. > > Weng > What you are trying to create is a 2-port array. If your target technology provides it, this is normally done by instantiating a 2-port RAM macro. If you are trying to synthesize a 2-port array then I think your process p1 is an adequate description. The second is just a more complicated way of saying the same thing. I don't think you need to give any special instructions to the synthesis tool to tell it that a /= b when C1 and C2 are active at the same time. The tool should just create an AND-OR Mux for every memory location. There will exist a logical possibility of an address collision but that shouldn't be a problem if a /= b when both C1 and C2 are active. Charles Bailey From newsfish@newsfish Thu Aug 1 00:44:59 2024 X-Received: by 2002:ac8:46d8:: with SMTP id h24mr207748qto.235.1569595617901; Fri, 27 Sep 2019 07:46:57 -0700 (PDT) X-Received: by 2002:a0d:d850:: with SMTP id a77mr2882764ywe.90.1569595617702; Fri, 27 Sep 2019 07:46:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no4149446qtl.0!news-out.google.com!x7ni2092qtf.0!nntp.google.com!o24no4149436qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Sep 2019 07:46:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to write a correct code to do 2 writes to an array on same cycle? From: Rick C Injection-Date: Fri, 27 Sep 2019 14:46:57 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4066 X-Received-Body-CRC: 1581912918 Xref: reader01.eternal-september.org comp.lang.vhdl:9585 On Friday, September 27, 2019 at 12:25:31 AM UTC-4, Charles Bailey wrote: > On 2019-09-24 13:51, Weng Tianxiang wrote: > > Hi, > > > > Here is a code segment showing 2 methods doing 2 writes to an array wit= h 2 different addresses on the same cycle: > > > > 1. > > p1: process(CLK) is > > begin > > if CLK'event and CLK =3D '1' then > > if C1 then > > An_Array(a) <=3D D1; > > end if; > > > > -- I know a /=3D b > > -- do I need to inform VHDL compiler of 2 different addresses? > > if C2 then > > An_Array(b) <=3D D2; > > end if; > > end if; > > end process; > > > > 2. > > p2: process(CLK) is > > begin > > if CLK'event and CLK =3D '1' then > > case C1 & C2 is > > when "10" =3D> > > An_Array(a) <=3D D1; > > > > when "01" =3D> > > An_Array(b) <=3D D2; > > > > when "11" =3D> > > -- I know a /=3D b > > -- do I need to inform VHDL compiler of 2 different addresses? > > An_Array(a) <=3D D1; > > An_Array(b) <=3D D2; > > > > when others =3D> > > null; > > end case; > > end if; > > end process; > > > > I think it is no problem with a simulator. > > > > Thank you. > > > > Weng > > > What you are trying to create is a 2-port array. If your target=20 > technology provides it, this is normally done by instantiating a 2-port= =20 > RAM macro. If you are trying to synthesize a 2-port array then I think= =20 > your process p1 is an adequate description. The second is just a more=20 > complicated way of saying the same thing. I don't think you need to=20 > give any special instructions to the synthesis tool to tell it that a /= =3D=20 > b when C1 and C2 are active at the same time. The tool should just=20 > create an AND-OR Mux for every memory location. There will exist a=20 > logical possibility of an address collision but that shouldn't be a=20 > problem if a /=3D b when both C1 and C2 are active. >=20 > Charles Bailey If you consider the logic that would be created, it can't deal with both po= rts writing to the same address other than by giving one port priority, so = obviously that is what will happen. The trick is doing what is appropriate= in the cases where there is no conflict. The hardware is not trivial. =20 Luckily I work with FPGAs rather than custom designs and the hardware is pr= ovided by the manufacturers. So the appropriate HDL will easily infer the = appropriate hardware. Easy-peasy. =20 --=20 Rick C. - Get 2,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:00 2024 X-Received: by 2002:aed:2469:: with SMTP id s38mr28519687qtc.190.1570432036351; Mon, 07 Oct 2019 00:07:16 -0700 (PDT) X-Received: by 2002:a81:4815:: with SMTP id v21mr18623197ywa.485.1570432036114; Mon, 07 Oct 2019 00:07:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no4302375qtl.0!news-out.google.com!x7ni1119qtf.0!nntp.google.com!o24no4302370qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2019 00:07:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=165.225.84.80; posting-account=bMuEOQoAAACUUr_ghL3RBIi5neBZ5w_S NNTP-Posting-Host: 165.225.84.80 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> Subject: Bit vs. std_logic for description of internal structures From: Maciej Sobczak Injection-Date: Mon, 07 Oct 2019 07:07:16 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9586 Hi, I have found a coding guideline that recommends to use std_logic everywhere= in preference to bit, on the basis that it can represent more states (X, Z= , etc.). What I found surprising is the implicit assumption that more states is an a= dded value. I understand that on the module boundary the additional states = can be useful, as they can model (or even enable) wider interfacing options= . But for modeling (and ultimately synthesis) of internal logic, I see no p= articular benefit - on the contrary, I can imagine that it might be benefic= ial to restrict the number of possible states as much as possible and in fa= ct, elsewhere designers are encouraged to always use (or define) the narrow= est type that covers the given context. Additional and unused states are al= so problematic with language constructs like the case statement, which expe= ct complete coverage and code fragments like this: case my_std_logic_value is when '0' =3D> ... when '1' =3D> ... when others =3D> assert false; end case; obviously miss the point. So I find such guidelines contradicting each other. What is your opinion on= this? Are there other aspects worth discussing? Do you feel bad using bit(= _vector) for modeling internal logic? --=20 Maciej Sobczak * http://www.inspirel.com From newsfish@newsfish Thu Aug 1 00:45:00 2024 X-Received: by 2002:a37:313:: with SMTP id 19mr23521110qkd.356.1570456499272; Mon, 07 Oct 2019 06:54:59 -0700 (PDT) X-Received: by 2002:a25:71d6:: with SMTP id m205mr11006429ybc.119.1570456499107; Mon, 07 Oct 2019 06:54:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no5225309qtl.0!news-out.google.com!x7ni1173qtf.0!nntp.google.com!o24no5225302qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2019 06:54:58 -0700 (PDT) In-Reply-To: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:147:4002:f4bf:b1c6:4def:74e2:51d7; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:b1c6:4def:74e2:51d7 References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <38e91295-1ad1-4601-8552-882cee60e2ad@googlegroups.com> Subject: Re: Bit vs. std_logic for description of internal structures From: Rick C Injection-Date: Mon, 07 Oct 2019 13:54:59 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 51 X-Received-Bytes: 3687 X-Received-Body-CRC: 1233425036 Xref: reader01.eternal-september.org comp.lang.vhdl:9587 On Monday, October 7, 2019 at 3:07:18 AM UTC-4, Maciej Sobczak wrote: > Hi, >=20 > I have found a coding guideline that recommends to use std_logic everywhe= re in preference to bit, on the basis that it can represent more states (X,= Z, etc.). > What I found surprising is the implicit assumption that more states is an= added value. I understand that on the module boundary the additional state= s can be useful, as they can model (or even enable) wider interfacing optio= ns. But for modeling (and ultimately synthesis) of internal logic, I see no= particular benefit - on the contrary, I can imagine that it might be benef= icial to restrict the number of possible states as much as possible and in = fact, elsewhere designers are encouraged to always use (or define) the narr= owest type that covers the given context. Additional and unused states are = also problematic with language constructs like the case statement, which ex= pect complete coverage and code fragments like this: >=20 > case my_std_logic_value is > when '0' =3D> ... > when '1' =3D> ... > when others =3D> > assert false; > end case; >=20 > obviously miss the point. >=20 > So I find such guidelines contradicting each other. What is your opinion = on this? Are there other aspects worth discussing? Do you feel bad using bi= t(_vector) for modeling internal logic? >=20 > --=20 > Maciej Sobczak * http://www.inspirel.com I suppose this is not unlike the use of Boolean for certain signals. The v= arious values that std_logic can take on allows for indications of problems= in simulation. When signals are uninitialized std_logic makes that known = easily. When signals have driver conflicts std_logic makes that known easi= ly. =20 That said, I'm sure in many cases the need for this sort of debugging help = is minimal. Still, rather than trying to figure out when it is better to u= se bit vs. std_logic, why not just use std_logic everywhere?=20 I gave up using Boolean a long time ago. I don't think I ever really used = BIT.=20 --=20 Rick C. - Get 2,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:00 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx35.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Bit vs. std_logic for description of internal structures Newsgroups: comp.lang.vhdl References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 191007-2, 07/10/2019), Outbound message X-Antivirus-Status: Clean Lines: 46 Message-ID: <%sJmF.1001633$yw3.857218@fx35.am4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Mon, 07 Oct 2019 16:11:39 UTC Organization: virginmedia.com Date: Mon, 7 Oct 2019 17:11:39 +0100 X-Received-Bytes: 3499 X-Received-Body-CRC: 3962929187 Xref: reader01.eternal-september.org comp.lang.vhdl:9588 On 07/10/2019 08:07, Maciej Sobczak wrote: > Hi, > > I have found a coding guideline that recommends to use std_logic everywhere in preference to bit, on the basis that it can represent more states (X, Z, etc.). > What I found surprising is the implicit assumption that more states is an added value. I understand that on the module boundary the additional states can be useful, as they can model (or even enable) wider interfacing options. But for modeling (and ultimately synthesis) of internal logic, I see no particular benefit - on the contrary, I can imagine that it might be beneficial to restrict the number of possible states as much as possible and in fact, elsewhere designers are encouraged to always use (or define) the narrowest type that covers the given context. Additional and unused states are also problematic with language constructs like the case statement, which expect complete coverage and code fragments like this: > > case my_std_logic_value is > when '0' => ... > when '1' => ... > when others => > assert false; > end case; > > obviously miss the point. > > So I find such guidelines contradicting each other. What is your opinion on this? Are there other aspects worth discussing? Do you feel bad using bit(_vector) for modeling internal logic? I can think of 3 reasons why you might want to use std_logic(_vector) types, the first is that it allows you to use 'X' (carefully as dontcare could have nasty side effects) which could help synthesis (but unfortunately not always). As Rick already mentioned, the second reason is that it is great for showing issues, if you feed an 'X' into a bit(_vector) circuit your conversion function will mask the fact you are reading invalid values. The third reason is that most hard-ip/coregens/megawizards/examples etc all use std_logic types so you would need a lot of conversion functions which becomes a real pain. I always use std_logic types on the I/O and boolean/unsigned/integer etc internally. For Code Coverage it not really an issue as you will know if the "when others" clause should be hit or not, if the case statement is fully decoded you can use a coverage exclude pragma or some global flag like Modelsim's -coverexcludedefault. Now if you have 'X's propagating through your design then Code Coverage becomes more complex as 'X's might give you a false positive. Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:45:00 2024 X-Received: by 2002:ac8:224b:: with SMTP id p11mr31812274qtp.38.1570476503354; Mon, 07 Oct 2019 12:28:23 -0700 (PDT) X-Received: by 2002:a25:ab21:: with SMTP id u30mr7754334ybi.143.1570476502945; Mon, 07 Oct 2019 12:28:22 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2019 12:28:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.21.36.103; posting-account=ixzXGgoAAADkhLm6OjEOE5uGjsHUSYrw NNTP-Posting-Host: 78.21.36.103 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <118e438f-f3d2-4d2f-bda1-dec17a9a9fee@googlegroups.com> Subject: E' DA ARRESTARE SUBITO: L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI GENOVA! IL NOTISSIMO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LEGALE MALAVITOSISSIM From: ROBERTO GORINI 4-UPPER LTD LUGANO-LA-SUISSE Injection-Date: Mon, 07 Oct 2019 19:28:23 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no6082940qtl.0!news-out.google.com!q23ni291qtl.1!nntp.google.com!o24no6082933qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9589 E' DA ARRESTARE SUBITO: L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMME= DIATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI= GENOVA! IL NOTISSIMO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!= !!! 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IL TUTTO INSIEME ANCHE AL TRE VOLTE FINIT= O IN GALERA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, DI CRIMIN= ALISSIMA BITINCUBATOR & VENTURE, DI CRIMINALISSIMA CRYPTOPOLYS, CRIMINALISS= IMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "MERDATO"= LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFI= LO DEL BITCOIN" https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg https://twitter.com/megliomortiche1 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ). 2 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). =E3=80=80 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 4 E POI ANCORA.. http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! =E3=80=80 5 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ =E3=80=80 =E3=80=80 6 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html https://twitter.com/LavaPaolo ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg 7 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/company D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ =E3=80=80 8 AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://www.instagram.com/p/Bcc0zWonbtv/ E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO https://www.spreaker.com/user/10297125 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". 9 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIP= O QUESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/ https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!! 10 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! https://www.py.cz/pipermail/python/2018-February/013212.html 11 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o) Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:45:01 2024 X-Received: by 2002:a0c:fb43:: with SMTP id b3mr233183qvq.187.1570523525525; Tue, 08 Oct 2019 01:32:05 -0700 (PDT) X-Received: by 2002:a25:adc2:: with SMTP id d2mr13342499ybe.200.1570523525284; Tue, 08 Oct 2019 01:32:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no7837182qtl.0!news-out.google.com!q23ni340qtl.1!nntp.google.com!o24no7837171qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Oct 2019 01:32:04 -0700 (PDT) In-Reply-To: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Bit vs. std_logic for description of internal structures From: Thomas Stanka Injection-Date: Tue, 08 Oct 2019 08:32:05 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 35 Xref: reader01.eternal-september.org comp.lang.vhdl:9590 Am Montag, 7. Oktober 2019 09:07:18 UTC+2 schrieb Maciej Sobczak: > What I found surprising is the implicit assumption that more states is an= added value.=20 Std_logic vs bit costs simulation performance but provides an universal and= known good debug tool that bit will never provide. First keep in mind that real world VHDL code needs to be portable as much a= s possible from design to design (reuse). This will always mean that the co= de needs to be portable from tool to tool as good as possible (Every design= er knows the limits when technology dependency is needed for performance re= asons) as some might request you to incorporate 10 year old fpga code in a= mixed signal ASIC as IP. In large projects it is quite common to detect problems with unitialised re= gisters which might not even be detectable in an Xilinx-FPGA on equipment l= evel as this FF is initialised to low after power up, when moving same desi= gn to ASIC you learn that there is no guarantee that FF is low after Power-= Up. =20 std_(u)logic helps detecting this in first simulations. Same for correct be= havior of (intended or undesired) tristate.=20 And what benefit is gained, when you need to convert anywhere between bit i= nternal and std_(u)logic as your internal signal might be tomorrow external= input or output. Therefore it is far easier to encurage to use std_logic anywhere instead of= wasting time for checking on every signal what type is more benefitial. Same for integer. It is easier to use always (un)signed instead of integer/= natural instead of double checking if integer is really useable or not. =20 regards Thomas From newsfish@newsfish Thu Aug 1 00:45:01 2024 X-Received: by 2002:a37:6651:: with SMTP id a78mr29706972qkc.474.1570543873063; Tue, 08 Oct 2019 07:11:13 -0700 (PDT) X-Received: by 2002:a25:3109:: with SMTP id x9mr15103671ybx.77.1570543872856; Tue, 08 Oct 2019 07:11:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no8655849qtl.0!news-out.google.com!q23ni366qtl.1!nntp.google.com!o24no8655841qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Oct 2019 07:11:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:147:4002:f4bf:dd21:50af:e10:216a; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:dd21:50af:e10:216a References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9939c34b-553d-4dac-a8f8-057441448476@googlegroups.com> Subject: Re: Bit vs. std_logic for description of internal structures From: Rick C Injection-Date: Tue, 08 Oct 2019 14:11:13 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 57 Xref: reader01.eternal-september.org comp.lang.vhdl:9591 On Tuesday, October 8, 2019 at 4:32:07 AM UTC-4, Thomas Stanka wrote: > Am Montag, 7. Oktober 2019 09:07:18 UTC+2 schrieb Maciej Sobczak: > > What I found surprising is the implicit assumption that more states is = an added value.=20 >=20 > Std_logic vs bit costs simulation performance but provides an universal a= nd known good debug tool that bit will never provide. >=20 > First keep in mind that real world VHDL code needs to be portable as much= as possible from design to design (reuse). This will always mean that the = code needs to be portable from tool to tool as good as possible (Every desi= gner knows the limits when technology dependency is needed for performance = reasons) as some might request you to incorporate 10 year old fpga code in= a mixed signal ASIC as IP. >=20 > In large projects it is quite common to detect problems with unitialised = registers which might not even be detectable in an Xilinx-FPGA on equipment= level as this FF is initialised to low after power up, when moving same de= sign to ASIC you learn that there is no guarantee that FF is low after Powe= r-Up. > =20 > std_(u)logic helps detecting this in first simulations. Same for correct = behavior of (intended or undesired) tristate.=20 >=20 > And what benefit is gained, when you need to convert anywhere between bit= internal and std_(u)logic as your internal signal might be tomorrow extern= al input or output. >=20 > Therefore it is far easier to encurage to use std_logic anywhere instead = of wasting time for checking on every signal what type is more benefitial. >=20 > Same for integer. It is easier to use always (un)signed instead of intege= r/natural instead of double checking if integer is really useable or not. I would also point out the inconvenience of needing to think about the type= conversions required when using other than std_logic. Unless all your non= -vector data types are BIT, it gets messy to combine them with logical oper= ators. Maybe VHDL-2008 made that easier with some of the defaults. I woul= dn't know since I don't use BIT type. =20 I don't want to turn this into a general "what type is better" discussion, = but I find the range limiting of integer can be useful over signed or unsig= ned. If I want a counter that ranges from 0 to 9 or 0 to 16,384 times 2048= , integer gives me that without hassle, helps sanity check my code and I do= n't need to count how many bits it will require.=20 I don't mind mixing data types if it gives me some advantage or ease of use= .=20 For simple signals I can't see the performance advantages being very signif= icant unless there are an awful lot of them.=20 --=20 Rick C. - Get 2,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:01 2024 X-Received: by 2002:ad4:53c1:: with SMTP id k1mr2227209qvv.223.1570605402464; Wed, 09 Oct 2019 00:16:42 -0700 (PDT) X-Received: by 2002:a25:bdcb:: with SMTP id g11mr1054284ybk.359.1570605402190; Wed, 09 Oct 2019 00:16:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder4.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr2.eu1.usenetexpress.com!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!85.12.16.68.MISMATCH!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no238659qtl.0!news-out.google.com!q23ni42qtl.1!nntp.google.com!o24no238651qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Oct 2019 00:16:41 -0700 (PDT) In-Reply-To: <9939c34b-553d-4dac-a8f8-057441448476@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=165.225.84.85; posting-account=bMuEOQoAAACUUr_ghL3RBIi5neBZ5w_S NNTP-Posting-Host: 165.225.84.85 References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> <9939c34b-553d-4dac-a8f8-057441448476@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9b2ff4ba-08db-45a8-9297-fa9b30cc7c27@googlegroups.com> Subject: Re: Bit vs. std_logic for description of internal structures From: Maciej Sobczak Injection-Date: Wed, 09 Oct 2019 07:16:42 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2220 X-Received-Body-CRC: 3574671704 Xref: reader01.eternal-september.org comp.lang.vhdl:9592 Thank you all for your answers, they were very instructive. The general the= me is that std_logic prevents hiding some of the issues that otherwise migh= t get lost when narrower bit is used. I also understand that the mere presence of 'Z' in the std_logic type does = not necessarily lead the synthesis tool to choose more expensive elements f= or what is intended to be a basic logic (2-state) circuit. Or that in pract= ice what the designer thinks to be a basic logic ends up in LUTs and whatev= er else is available, so that the "savings" presumed by the use of bit are = not going to lead to actually smaller footprint. If that's the case, then t= his clears my concerns. Reagrds, --=20 Maciej Sobczak * http://www.inspirel.com From newsfish@newsfish Thu Aug 1 00:45:02 2024 X-Received: by 2002:ac8:1810:: with SMTP id q16mr5139342qtj.38.1570643146970; Wed, 09 Oct 2019 10:45:46 -0700 (PDT) X-Received: by 2002:a05:6902:510:: with SMTP id x16mr3094539ybs.143.1570643146222; Wed, 09 Oct 2019 10:45:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.alt.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no1841413qtl.0!news-out.google.com!q23ni82qtl.1!nntp.google.com!o24no1841406qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Oct 2019 10:45:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.66.7.216; posting-account=ixzXGgoAAADkhLm6OjEOE5uGjsHUSYrw NNTP-Posting-Host: 87.66.7.216 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <52ccc654-a773-4d4b-baad-32bba8a17cd5@googlegroups.com> Subject: IN GALERA E NON SU WIKIPEDIA: GIANFRANCO CARPEORO! E' MASSONE AFFILIATO LA NDRANGHETA: GIANFRANCO CARPEORO (NOTO PURE COME "IL SICARIO ASSASSINO AL SERVIZIO DI CRAXI")! E' UN KILLER PUNCIUTO, PARTE DELLA MEGA OMICIDA NDRINA PERNA DI COSENZA......... From: ROBERTO GORINI 4-UPPER LTD LUGANO-LA-SUISSE Injection-Date: Wed, 09 Oct 2019 17:45:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 433 Xref: reader01.eternal-september.org comp.lang.vhdl:9593 IN GALERA E NON SU WIKIPEDIA: GIANFRANCO CARPEORO! E' MASSONE AFFILIATO LA= NDRANGHETA: GIANFRANCO CARPEORO (NOTO PURE COME "IL SICARIO ASSASSINO AL S= ERVIZIO DI CRAXI")! E' UN KILLER PUNCIUTO, PARTE DELLA MEGA OMICIDA NDRINA = PERNA DI COSENZA........... ( https://it.wikipedia.org/wiki/%27Ndrina_Perna= ). FU L'IDEATORE DELL'OMICIDIO DI DENIS BERGAMINI, AVVENUTO INFATTI A COSE= NZA A FINI ANNI 80 ( http://www.iacchite.blog/omicidio-bergamini-ecco-come-= hanno-ucciso-denis-prima-di-stenderlo-sullasfalto1/ ). ALLORCHE' STO PURE N= OTO PEDOFILO DI GIANFRANCO CARPEORO FACEVA OGNI TIPO DI SCHIFEZZA COL SUO C= OMPARE SUPER STRA PEDOFILO SILVIO BERLUSCONI E CON BETTINO ^BOTTINO^ CRAXI = (PENSATE CHE QUI POTETE ASCOLTARE STA MERDACCIA SATA/N/AZISTA DI GIAFRANCO = "PERCORARO" CARPEORO RAGLIARE CHE BERLUSCONI NON HA MAI RICICLATO SOLDI DI = MAFIA E NON HA STECCATO BETTINO CRAXI NOTO IN TUTTO IL MONDO COME BOTTINO C= RAXI... https://www.youtube.com/watch?v=3Dv1f8qDQQHC0 https://www.ilfattoquotidiano.it/2012/10/30/mafia-soldi-narcotraffico-a-del= lutri-per-investimento-in-attivita-berlusconi/398736/ http://www.maurizioturco.it/dossier/cera-una-volta-il-mafioso-d/1998-07-07-= la-padania-silvi.html https://www.ilfattoquotidiano.it/2017/01/20/bettino-craxi-tangenti-per-mili= ardi-a-domicilio-ecco-perche-fu-condannato/3329146/ https://www.repubblica.it/politica/1995/11/24/news/berlusconi_craxi_e_10_mi= liardi-24581177/ CRIMINALISSIMA SFACCIATAGGINE PARI A RAGLIARE CHE LA LUNA SI VEDE NEL CIELO= A PARTIRE DALLE DIECI DI MATTINA ED IL SOLE A PARTIRE DALLE 22, IN PIENA = SERATA, NE PIU' NE MENO). ANCHE IO SONO DA SEMPRE IN GIRI MASSONICI, E SONO= UN EX CRAXIANO E BERLUSCONIANO (EX PERO', ORA TIFO A MANETTA M5S UNITO A C= ENTRO SINISTRA, COSA CHE INFATTI STA SALVANDO IL NOSTRO PAESE, FACENDO PREC= IPITARE LO SPREAD E FACENDO SALIRE LA BORSA, COSI' DA ARRICCHIRICI TUTTI E = TANTO). MA I MASSONI BERLUSCONICCHI E NDRANGHETISTI, SEMPRE PI=C3=9A MI SCH= IFANO. E DA PENTITO, DA EX DI QUESTI GIRI, RITENGO GIUSTO CHE IL MONDO SAPP= IA CHE CRIMINALI EFFERATI, PURE ASSASSINI, ASSASSINI, ASSASSINI, ESSI SIANO= . CHI APPOGGIA I RICICLAGGI DI SOLDI DI NDRANGHETA, PORTATI AVANTI DA SEMPR= E DA STO VERME MALAVITOSO CHE E' GIANFRANCO CARPEORO ( O VERME VERME MALAVI= TOSO GIANFRANCO PECORARO CARPEORO CHE SIA), E' UN MASSONE MARCHIGIANO, OVVI= AMENTE PURE ESTREMAMENTE PEDOFILO E DELINQUENTE: PAOLO CARDEN=C3=81. A PRO= POSITO DEL QUALE... E' PEDOFILO ED ASSASSINO: PAOLO CARDEN=C3=80 (FACEBOOK, TWITTER, CRIMINALIS= SIMO BLOG VINCITORI E VINTI....VEDRA' COME LO FAREMO DIVENIRE PARTE DELLA S= ECONDA CATEGORIA E NON PRIMA, CHE RICICLI DA SEMPRE SOLDI DI MAFIA, CAMORRA= E NDRANGHETA O MENO..."O MENO", OVVIAMENTE, SI FA PER DIRE)?!? RAGLIA DI A= VER FATTO IL "PRIVATE BANKER", MA NON DICE CHE SUOI PRINCIPALI CLIENTI SONO= I NOTI MAFIOSI CRISAFULLI DI MILANO! UNA DELLE FAMIGLIE DI COSA NOSTRA PIU= ' ASSASSINE DI TUTTI I TEMPI! https://milano.repubblica.it/cronaca/2018/02/22/news/droga_maxiprocesso_mil= ano_biagio_crisafulli_condannato_20_anno_boss-189496506/ MA CHI' E' DAVVERO LO SCHIFOSO PEDERASTA ED ASSASSINO PAOLO CARDEN=C3=80 (C= HE HA PER CRIMINALISSIMO CV, SOLO QUELLO DEL TIPICO MEGA RICICLA SOLDI MAFI= OSI)? BEH, INTANTO DICIAMO CHE TRATTASI PURE DI NOTO NAZISTA, RAZZISTA E KU= KLUK KLANISTA! OLTRE CHE SATANISTA SODOMIZZA ED AMMAZZA BAMBINI!!! https://www.mail-archive.com/racket-users@googlegroups.com/msg40600.html E' LUI DIETRO TANTISSIMI OMICIDI MASSONICI A CUI HAN FATTO SEGUITO POI DIVI= SIONE DEL CORPO DEGLI UCCISI IN TANTI PEZZI E SOTTERRAMENTO DEL TUTTO IN TA= NTI BOSCHI MARCHIGIANI. ESATTISSIMAMENTE COME DA QUESTI ARTICOLI. https://www.corriereadriatico.it/marche/marche_persone_scomparse_minori-660= 674.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ED E' CRIMINALISSIMA LA CARDEN=C3=80 CONSULTING DI VIA MONTESSORI 6, FALERO= NE (FM). COME E' E STRA E' CRIMINALISSIMA LA CARDEN=C3=80 AND PARTNERS DI V= IA MONTESSORI 6, FALERONE (FM). DA ANNI, LE DUE, RICICLANO SOLDI MEGA KILL= ER DI COSA NOSTRA, CAMORRA, NDRANGHETA E MAFIA RUSSA (CHE NON PER NIENTE, L= AVO' PRIMI PROPRI =E2=82=AC OMICIDA, A LIVELLO MONDIALE, ESATTAMENTE NELLE = MARCHE, COME DA QUESTO PUNTUALISSIMO ARTICOLO http://www.comitato-antimafia-lt.org/la-mafia-russa-la-piu-pericolisa-e-la-= piu-sottovalutata/ )!! ED I VERMI SCHIFOSI CHE LA RAPPRESENTANO, I BASTARDI EFFERATI CRIMINALI STE= FANO CARDEN=C3=80 E PAOLO CARDEN=C3=80 SONO PURE, COME DETTO, DUE NOTISSIMI= "SATA-N-AZISTI" , OSSIA DUE SATANISTI NAZISTI, DUE PEDOFILI INCULA ED AMMA= ZZA BAMBINI! SON REGISTI DI CENTINAIA DI OMICIDI E SPARIZIONI DI PERSONE, E= SATTAMENTE COME DA QUESTO ARTICOLO http://www.anconatoday.it/cronaca/persone-scomparse-regione-marche.html SI, SI, E' PROPRIO COSI': E' CRIMINALISSIMA LA CARDEN=C3=80 E PARTNERS DI V= IA MONTESSORI 6, 63837 FALERONE (FM) - Tel: 0734.710786 CON CRIMINALISSIMA = EMAIL info@cardenaconsulting.it E CRIMINALISSIMA PARTITA IVA 01840990442). = DA ANNI RICICLA SOLDI ASSASSINI DI COSA NOSTRA, CAMORRA E MAFIA RUSSA (CHE,= COME DETTO, NON PER NIENTE, LAVO' PRIMI PROPRI RUBLI ASSASSINI PROPRIO NEL= LE MARCHE.. COME PROVATO DA QUESTO ALTRO INECCEPIBILE ARTICOLO http://www.culturaeculture.it/di-tutto-un-po/mafia-russa-la-storia-sulla-pe= lle-66587/ )! PAOLO CARDEN=C3=80 =C3=89 UNO SCHIFOSISSIMO PEDOFILO ( =C3=89= IL PRESIDENTE DELLA ASSOCIAZIONE "INCULIAMO I BAMBINI E LI AMMAZZIAMO PER= SATANA", ASSOCIAZIONE ANIMALESCHISSIMA GEMELLA DELL'ASSOCIAZIONE ORGOGLIO = PEDOFILO http://www.cshg.it/lapice-della-violenza-orgoglio-pedofilo-e-legit= timazione-della-pedofilia.html ) IL MASSONE ECONOMISTA PEDERASTA ED ASSASSINO PAOLO CARDEN=C3=80 (NATO IL 2.= 10.1971 E RESIDENTE IN VIA POZZO 105, 63837 FALERONE ) HA PURE UN BLOG CRIM= INALISSIMO: VINCITORI E VINTI! NOI SAREMO I VINCITORI CHE METTEREMO LUI, I = SUOI MEGA CRIMINI E MEGA BALLE, SPALLE AL MURO! MENTRE LUI SARA' IL VINTISS= IMO! IL VERME DELINQUENTISSIMO PAOLO CARDEN=C3=80 (TWITTER), OLTRE AD ESSER= NOTO PEDOFILO E' UN MEGA RICICLA SOLDI MAFIOSI PER I SUPER KILLER DI COSA = NOSTRA: CRISAFULLI DI MILANO ( E NON SOLO)! COME DA "TRADIZIONE" DI SUOI MA= NDANTI, OSSIA IL PURE NOTISSIMO PEDOFILO SILVIO BERLUSCONI (OLTRE CHE STRAG= ISTA SILVIO BERLUSCONI, SPAPPOLANTE EROICI MAGISTRATI COME GIOVANNI FALCONE= E PAOLO BORSELLINO https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ ). ED I PORCI, PURE MEGA RICICLA SOLDI ASSASSINI DI MALAVITE DI MEZZO MONDO: E= NNIO DORIS E MASSIMO DORIS DI MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOLA= NUM, NAZISTANUM! BUT AGAIN AND AGAIN AND AGAIN... CHI =C3=88 DAVVERO STO PEDOFILO ASSASSINO = CHIAMANTESI PAOLO CARDEN=C3=80 RESIDENTE ANCHE A PENNA SAN GIOVANNI (MACERA= TA), VIA UMBERTO I, NUMERO 41! DI BASTARDAMENTE CRIMINALE CARDEN=C3=80 CONS= ULTING, BASATA IN VIA MONTESSORI 6, 63837 FALERONE (FM) - Tel: 0734.710786 = E DI MEGA TRUFFATORE BLOG VINCITORI E VINTI ( CHE ESISTE PER FAR ABBOCCARE = I "CIUCCI DEL WEB" I QUALI, ABBOCCANDO AI SUOI FALLIMENTARI SERVIZI, SEMPRE= PERDONO TUTTI I PROPRI RISPARMI, SIA PER LA TOTALE INCOMPETENZA DI PAOLO C= ARDEN=C3=80 SUI MERCATI FINANZIARI MONDIALI, SIA PER LA INDOLE SEMPRE TRUFF= ALDINA DEL VERME CRIMINALISSIMO PAOLO CARDEN=C3=80 STESSO)! E CHI E' IL NOTO PEZZO DI MERDA, FIGLIO DI PUTTANA, LADRO, SEMPRE FALSO, CO= CAINOMANE, DELINQUENTE ESTREMISSIMO E PURE NOTO PEDOFILO STEFANO CARDEN=C3= =80? http://www.formazione-lavoro.eu/img/public/stefano.jpg AL PUNTO, NOW, PLEASE! VI SONO OPINIONI SOLO VOMITEVOLI SU STO PEDOFIL-O-MOSESSUALE PAZZO, SODOMIZ= ZA ED AMMAZZA BIMBI E RAGAZZINI DI PAOLO CARDEN=C3=81 DI DELINQUENTISSIMO B= LOG VINCITORI E VINTI!!! COME TUTTO IL MONDO BEN SA', CHI STA QUI SCRIVENDO ORA, E' UN FUORI USCITO = DA QUEL PARTITO STRA COLMO DI COSA NOSTRA, CAMORRA, NDRANGHETA E CATTIVERIA= ANTI DEMOCRATICA DI ESTREMISSIMA DESTRA CHE E' FORZA ITALIA ( OVE SGUAZZA,= A LIVELLO DI MEGA BALLE, CHE FA SCRIVERE SU INTERNET, LA MASSONA SATA-N-AZ= ISTA, LA PUTTANA SEMPRE CON CAZZI SU CAZZI IN CULO: GINA NIERI DI MEDIASET,= MAFIASET, CAMORRASET, NDRANGASET, NAZISTSET). DI STO VERME CRIMINALE DI PAOLO CARDEN=C3=81 CONOSCO TUTTO, SO' TUTTO! E QU= INDI, COME DICONO A NAPULE " MO' M'HAGGIA PROPRIO SFUGA' "!!! IL PEDOFILO ASSASSINO PAOLO CARDENA' DI FORZA ITALIA MAFIOSA ( https://picc= hionews.it/attualita/paolo-cardena-relatore-al-convegno-sulle-banche-promos= so-da-forza-italia-macerata ) PROFESSIONALLY SPEAKING, SI DEFINISCE "PRIVAT= E BANKER". MA NON DICE CHE SUOI CLIENTI NUMERI UNO SONO I MAFIOSI ASSASSINI= CRISAFULLI DI MILANO! UNA DELLE FAMIGLIE DI COSA NOSTRA PIU' BASTARDAMENTE= KILLER DI TUTTI I TEMPI! https://it.wikipedia.org/wiki/Crisafulli_(clan) E POI, COME CITATO, IL VOMITEVOLE PEDERASTA PAOLO CARDEN=C3=81 DI CRIMINALI= SSIMO BLOG VINCITORI E VINTI E' PURE CONOSCIUTISSIMO PEDOFIL-O-MOSESSUALE (= NULLA CONTRO GLI OMOSESSUALI PER BENE, TRASPARENTI, CHE NON SI NASCONDONO.= .. MA TUTTO CONTRO I PEDOFIL-O-MOSESSUALI, QUELLI CHE INCULANO NEONATI, BAM= BINI, RAGAZZINI, ADOLESCENTI, COME FA DA SEMPRE IL PEDERASTA PAOLO CARDEN= =C3=81: QUI IN UNA FOTO CHE GLI ABBIAMO FATTO, MENTRE IN MUTANDE, FISSAVA, = CON SGUARDO DA DEPRAVATO SESSUALE MAXIMO, UN BAMBINO DI OTTO ANNI, NELLE AD= IACENZE DI UN CAMPO ROM PADANO, VICINO A COLOGNO MONZESE, VICINO ALLA SEDE = CRIMINALISSIMA DI MEDIASET-MAFIASET-CAMORRASET-NDRANGASET-NAZISTSET OVE SI = ERA APPENA RECATO https://www.commoditiestrading.it/public/autori/635338392358575000_Cardena.= jpg BAMBINO DI OTTO ANNI CHE MEZZ'ORA DOPO AVREBBE INCULATO A SANGUE. STAVAMO P= EDINANDO DA MESI E MESI E MESI QUESTRO TOPO DI FOGNA PEDERASTA DI PAOLO CAR= DEN=C3=81, ABBIAMO FOTOGRAFATO E VIDEATO IL TUTTO, PRESTO OGNI COSA SU MIGL= IAIA DI SITI, ANCHE DI PLUTONIO E MARTE, NON SOLO DI QUESTO PIANETA SEMPRE = PIU' "PICCIRIDDU PICCIRIDDU" .. USO SLANG SICILIANO, PER FAR SENTIRE IL MEG= A RICICLA CASH DI COSA NOSTRA, PAOLO CARDEN=C3=81, COME SE IN UNA "COSA SUA= " AAAA)!!! SI, PROPRIO COSI', BABIES, PROPRIO COSI'!!! VI SONO OPINIONI SOLO ORRIBILI = SUL BASTARDISSIMO CRIMINALE PAOLO CARDEN=C3=81 NATO A MACERATA IL 2.19.1971= ( PER NON DIRE QUANTO SIA PURE SEMPRE FALSO, LADRO, TRUFFATORE, BRUCIANTE = TUTTI I RISPARMI DI CHI, A LUI, IDIOTAMENTE ABBOCCHI E QUINDI SI AFFIDI VIA= INTERNET=E2=80=A6 PER NON DIRE INOLTRE QUANTO SIA ANCHE MANDANTE DI OMICID= I, MALATO MENTALE, COCAINOMANE E TANTISSIMO ALTRO)?!? FATEVI QUESTE DOMANDUZZEDDE, ORA PLEASE ( AGAIN AND AGAIN... SCRIVO IN SLAN= G SICILIANO, ESSENDO PAOLO CARDENA=E2=80=99 UNO SCHIFOSO MALAVITOSO RICICLA= TORE DI SOLDI ASSASSINI DI COSA NOSTRA, IN PRIMIS, POI ANCHE DI CAMORRA E N= DRANGHETA=E2=80=A6 GLI FACCIO COME SE UN FAVORE..LO FACCIO SENTIRE COME SE = A CASA=E2=80=A6 LO FACCIO SENTIRE COME SE IN UNA=E2=80=A6SANGUINARISSIMA...= =E2=80=9CCOSA SUA=E2=80=9D=E2=80=A6 AAAH): COME E' IL VERME CRIMINALISSIMO= PAOLO CARDEN=C3=80, LO SCHIFOSO PEDERASTA PAOLO CARDEN=C3=80, NELLA VITA P= RIVATA? COI PANTALONI ABBASSATI? LA BESTIA PEDOFILESCA E MEGA RICCHIONESCA PAOLO CARDENA', DUE, TRE SERE ALL= A SETTIMANA, VA' IN LOCALI ^OCCULTISSIMI^ DI TIPO ESTREMAMENTE DEPRAVATO! A= PERTI SOLO A MASSONI OMOSESSUALI LEGHISTI E BERLUSCONIANI! CI VA' COL PARI = PEDERASTA GIULIO TREMONTI (IL CUI AMANTE OMOSESSUALISSIMO ERA IL NAZISTA, A= NZI, SATA-N-AZISTA ALEXANDER BOETTCHER, QUELLO CHE SI RIEMPIVA DI COCAINA E= FACEVA SFREGIARE CON ACIDO ASSASSINO TANTA GENTE INNOCENTE, INNOCUA, PER B= ENE.. COLUI CHE IN UN IMPULSO DI ONESTA' SI E' DEFINITO UN PAZZO DEPRAVATO = SESSUALE http://www.dagospia.com/rubrica-29/cronache/sono-deviato-sessuale-martina-l= evato-era-sadomasochismo-124763.htm IL DEAL ERA QUESTO: ALEXANDER BOETTCHER INCULAVA L'OMOSESSUALE, SPESSO PURE= DI TIPO PEDOFILO, GIULIO TREMONTI ..COME QUESTO TWITTER ACCOUNT FA STRA IN= TUIRE https://twitter.com/alexanboettcher E L ^ OCCULTISSIMO" MASSONE LAVA SOLDI MAFIOSI, OMOSESSUALE DI TIPO PERVERT= ITO, GIULIO TREMONTI, CERCAVA DI FARLO SFONDARE IN POLITICA..ALLA FINE, PER= O', L'UNICA COSA SFONDATA RIMANEVA L'ANO DEL CULACCHIONE "CHIC LE FREAK" GI= ULIO TREMONTI STESSO https://elfobruno.wordpress.com/2011/07/29/tremonti-sarebbe-gay-ma-nessuno-= puo-dirlo/ http://www.mosinforma.org/cecchi-paone-pdl-piena-di-gay-anche-un-ministro-g= iulio-tremonti/ ). CON ALTRI PEDERASTA QUALI SONO DA SEMPRE GIULIANO FERRARA E CLAUDIO CERASA = ( GIULIANO FERRARA AMMETTE SE STESSO, QUI, COME GLI PIACCIA PRENDERLO IN S= UO IMMENSO BUCO DEL CULO E DA UNA VITA https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ RICCHIONI PEDERASTA GIULIANO FERRARA E CLAUDIO CERASA DE IL FOGLIO, SI.....= FOGLIO PERO' DA USARSI SOLO X PULIRSI L'ANO IN CASO DI FINE DI CARTA IGIEN= ICA'... AND NEVER FORGET PLEASE, IL VERME CLAUDIO CERASA DA PALERMO E' AFFI= LIATO A COSA NOSTRA DA DECENNI, E' PUNCIUTO: FAMIGLIA CIMINNA, MANDAMENTO D= I CACCAMO.. E' UN NUOVO MARCELLO DELL'UTRI, DI FATTO https://groups.google.com/forum/?nomobile=3Dtrue#!topic/wwfx/cGpTIPY2T1o = ). OLTRE CHE CON IL GIA' 3 VOLTE IN CARCERE, PAOLO BARRAI NATO A MILANO IL 28.= 6.65. ED IL GIA' 2 VOLTE IN CARCERE, VINCENZO BARRAI NATO IL 3.5.1938, DI D= ELINQUENZIALISSIMA BSI ITALIA SRL VIA SOCRATE 26 MILANO. OLTRE CHE CON IL N= OTO GIOVANE PEDERASTA TANTO QUANTO RICCARDO BARRAI NATO IL 26.11.1996 ( ORA= SEMPRE A FARE ORGE GAY PRESSO UNIVERSITY OF READING). OLTRE CHE CON IL VER= ME MALAVITOSO E PURE LUI NOTO PEDOFIL-O-MOSESSUALE STEFANO BASSI DI MEGA TR= UFFATORE BLOG IL GRANDE BLUFF. OLTRE CHE COL RICCHIO-N-AZISTA ALESSANDRO CE= CCHI PAONE, NOTO IN TUTTO IL MONDO COME ALESSANDRO "CHECCHI" PAONE. SPESSIS= SIMO SON LI PRESENTI ANCHE I BANCHIERI MALAVITOSI DI BANCA MEDIOLANUM, GLI = OMOSESSUALI E CRIMINALISSIMI GIOVANNI PIROVANO, ENNIO DORIS ED ANGELO RENOL= DI ( NOTI PEDERASTA PURE). IVI FANNO ORGE SU ORGE ANCHE CON RAGAZZINI DI 14= ANNI!! IN DARK ROOMS! SI, E' PROPRIO COSI' E STRA COSI': E' UNO SCHIFOSISS= IMO PEDOFIL-O-MOSESSUALE, IL VERME BERLUS-CO-RROTTO PAOLO CARDENA'!!! PAGA = ADOLESCENTI ROM DI 8-12 ANNI, PER INCULARLI A SANGUE! VA' IN CAMPI ROM, DUE= , TRE VOLTE ALLA SETTIMANA, AT 4 AM, IN PIENA NOTTE, A PAGARE ZINGARELLI, P= ER INCULARLI TERRIFICANTEMENTE ( VEDI INEQUIVOCABILE FOTO A PROPOSITO, DI C= UI ABBIAM PRIMA GIA' SCRITTO https://www.commoditiestrading.it/public/autori/635338392358575000_Cardena.= jpg )! TUTTI QUESTI EFFERATISSIMI CRIMINI, SIA DI TIPO PEDERASTA, CHE DI RICICLAGG= IO DI SOLDI ASSASSINI, SONO EFFETTUATI IN CONNESSIONE COL MANDANTE DI OMICI= DI, RAZZISTA, KU KLUK KLANISTA, LADRO, TRUFFATORE, CORROTTISSIMO, SEMPRE FA= LSO, ESTORTORE DI SOLDI, MEGA STALKER SU INTERNET, GIA' 3 VOLTE IN CARCERE,= CACCIATO A SBERLE DA CITIBANK, INDAGATO DA 7 PROCURE ITALIANE E DALLA PROC= URA DI LUGANO, MEGA MULTATO DALLA CONSOB : BASTARDISSIMO CRIMINALE PAOLO PI= ETRO BARRAI NATO A MILANO IL 28.6.65. A PROPOSITO DEL QUALE, NON POSSO CHE SCRIVERE... E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZIRAZZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965= . NONCHE' MEGA RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI M= EGA RUBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA! MEGA TRUFFATORE E MEGA RICICLA CASH ASSASSINO PAOLO BARRAI! ANCHE LUI NOTO = PEDOFIL-O-MOSESSUALE SODOMIZZA BAMBINI E RAGAZZINI! CACCIATO DA CITIBANK A = SBERLE, PER MEGA FRODI CHE LI FACEVA! FONDATORE DELLA SIGLIA TERRORISTICA D= EI NUOVI MEGASSASSINI DI ESTREMA DESTRA: "NUOVI NAR"! FONDATORE DEL KU KLUK= KLAN PADANO! GIA' CONDANNATO AL CARCERE A MILANO ED IN BRASILE ( 8 ANNI E = PURE PER PEDERASTIA OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE)! = MULTATO DA CONSOB BEN 70.000 =E2=82=AC! DESTABILIZZANTE L'ITALIA PER FILO N= AZISTI SERVIZI SEGRETI SVIZZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTISSIMA= MENTE, NAZIONE SCHIFATA IN TUTTO IL MONDO, IN QUANTO FASCIOMAFIOSA DITTATUR= A DI BERLUSCONIA.. NON PER NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITALI= A DA SECOLI, DALLA TIRANNIASSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIAT,= PIRELLI, LUXOTTICA, MERLONI, PARMALAT E MIGLIAIA E MIGLIAIA DI ALTRE... E = CHE SIA CHIARO, PLS, CHE IDDIO BENEDICA I GRANDI PM CHE NON SOPPORTANTO IL = CANCRO DEL MONDO INTERO, SILVIO BERLUSCONI, COME HENRY WOODCOCK, ILDA BOCAS= SINI E CHIUNQUE ALTRO DI QUESTA AMMIREVOLISSIMA CATEGORIA)! FACENTE CRIMINI= SU CRIMINI E NAZI-ST-ALKING VIA INTERNET, SU ORDINE DEI BASTARDI INFINITI = CRIMINALI SILVIO BERLUSCONI, PAOLO BERLUSCONI ED UBALDO LIVOLSI DI FININVES= T, INNEGGIANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GR= ANDISSIMAMENTE FECE CON FALCONE E BORSELLINO", PAROLE DETTE DAL TERRORISTA = MAFIOSO, NAZISTA ED ASSASSINO PAOLO BARRAI, TANTISSIME VOLTE E PURE IN PUBB= LICO. MA VAMONOS BABIES, NOW, VAMONOS, VAMONOS, LET'S GO...... STO SCRIVENDO DEL - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA, MEGA R= ICICLA SOLDI DI NDRANGHETA, EIDOO, DIRETTA DAL VERME CALABRESE E NDRANGHETI= STA NATALE M. FERRARA O NATALE FERRARA CHE SIA https://ch.linkedin.com/in/n= atale-ferrara COME DA QUESTI OTTIMI ARTICOLI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edi COME DA QUESTO BELLISSIMO DOCUMENTARIO https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l ( FOUNDER OF EXTREMELY CRIMINAL EIDOO : YOUR VERY HOODLUM ASSET EXPERIENCE,= MEGA MAFIA MONEY LAUNDERER FOR COSA NOSTRA, NDRANGHETA, CAMORRA AND ASSASS= IN RUSSIAN GANSGTERS, NOT FOR NOTHING, CLOSE TO PRINCIPAL OF MURDERS, SLAUG= HTERS AND ASCERTAINED PEDOPHILE SILVIO BERLUSCONI). - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA CRYPTOP= OLYS ( OVE MEGA RICICLA SOLDI MAFIOSI COL NOTO VERME KUKLUKLANISTA, NAZIFAS= CISTA, MEGA RICICLA SOLDI MAFIOSI, BASTARDO VERO ARON CAMPONOVO DI MALAVITO= SISSIMA TANTO QUANTO IBEX CAPITAL LTD, MALAVITOSISSIMA TANTO QUANTO IBEX SE= RVICES LTD, MALAVITOSISSIMA TANTO QUANTO MONCLER SUISSE LTD https://ch.linkedin.com/in/aron-r-camponovo-a0030094 ED IL NOTO RAZZISTA, KUKLUKLANISTA, HITLERIANO, MEGA RICICLA SOLDI DI MALAV= ITE DI TUTTO IL MONDO ED ACCERTATO PEDOFILO INCULA BAMBINI: OLIVER CAMPONOV= O DI CAMPONOVO STRATEGY, ORA SOTTO PROCESSI SU PROCESSI, PER I SUOI MEGA RI= CICLAGGI DI CASH KILLER, BEN APPUNTO, DI NDRANGHETA, COME DA QUESTI OTTIMI = LINKS https://www.laregione.ch/cantone/mendrisiotto/1228182/affari-della-ndranghe= ta-in-ticino-alla-sbarra-l-uomo-di-fiducia-della-cosca-l-ex-municipale-di-c= hiasso-e-la-moglie-del-fratello-del-boss https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ ) - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA, SEMPRE= MEGA RICICLA SOLDI MAFIOSI, BITINCUBATOR VENTURES GRONO (CH) https://www.moneyhouse.ch/en/company/bitincubator-ventures-sa-12554072241 ( AFFIANCATO IN QUESTO DA QUELL'ALTRO SCHIFOSO PEDOFILO DI CLAUDIO LEVRINI = DI MALAVITOSA BITCOIN FOUNDATION, E, BEN APPUNTO, DI CRIMINALISSIMA BITINCU= BATOR VENTURES GRONO, COME DA QUEL PEZZO DI MERDA, NAZI-ST-ALKER E PURE LUI= NOTO PEDERASTA DI GIACOMO ZUCCO DI BLOCKCHAINLABIT ... NAZI-ST-ALKER E PUR= E LUI NOTO PEDOFILO OMOSESSUALE GIACOMO ZUCCO PURE DI HITLERIANI TEA PARTIE= S, CHE CHIAMA SEMPRE LA CIA ATTUALE PER CHIEDERE DI AMMAZZARE CHI NON SCHIF= OSAMENTE NAZISTA COME SE STESSO) https://www.moneyhouse.ch/en/company/bitincubator-ventures-sa-12554072241 - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI BLOCKCHAIN INVEST - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA BIGBITG= OLD E CRIMINALISSIMA BIGBIT - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA WORLD M= AN OPPORTUNITIES LUGANO - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN= CRYPTOECONOMY - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA WMO SA = PANAMA - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA LEGA LA= DRONA - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA FORZA I= TALIA MAFIOSA - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMI IL GIOR= NALE E LIBERO - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI ASSASSINO KU KLUK KLAN= PADANO - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI GRAN LOGGIA ITALIA MAS= SONICA DEL MALAVITOSO BANCHIERE GIUSEPPE SABATO DI BANCA ESPERIA ( GRUPPO B= ANCARIO DELLO SPAPPOLA MAGISTRATI, NONCHE' ACCLARATISSIMO PEDOFILO SILVIO B= ERLUSCONI). - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA CRIMINALISSIMA H 14= , DELL'OMOSESSUALE ^OCCULTO^ LUIGI BERLUSCONI https://www.gay.it/gossip/new= s/bacio-gay-luigi-berlusconi ( NIPOTE DEL TOPO DI FOGNA LUIGI BERLUSCONI, A SUA VOLTA, BESTIA CRIMINALE = DELLA CHIUSA PER MEGA RICICLAGGIO DI SOLDI MAFIOSI, BANCA RASINI http://tem= i.repubblica.it/micromega-online/mafia-politica-e-affari-sette-domande-al-c= avaliere/?printpage=3Dundefined E FIGLIO DI NOTO PEDOFILO SILVIO BERLUSCONI https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ http://www.elafter.com/foro/showthread.php?t=3D948509 COME PURE DI NOTO MANDANTE DI DOZZINE DI STRAGI SILVIO BERLUSCONI http://ww= w.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commissionate-berlu= sconi/ http://www.ilfattoquotidiano.it/2017/06/09/graviano-e-berlusconi-peter-gome= z-ricostruisce-le-stragi-del-1993/3648613/ COME PURE DI NOTO MANDANTE DI CENTINAIA E CENTINAIA DI OMICIDI MASCHERATI D= A FINTI SUICIDI, MALORI, INCIDENTI: SILVIO BERLUSCONI http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l ) - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA MALAVITOSA CGNAL DI= MARCO CARRAI http://espresso.repubblica.it/plus/articoli/2016/10/17/news/marco-carrai-l-= amico-che-mette-matteo-renzi-nei-guai-1.285898 (CANZONCINA CHE STIAMO PREPARANDO A PROPOSITO, CON QUESTO VINCENTISSIMO CHO= RUS: "A COSA NOSTRA, CAMORRA E NDRANGHETA, IL BUCATO FINANZIARIO TU LO FAI,= RICICLA SOLDI MAFIOSI PAOLO BARRAI, RICICLA SOLDI MAFIOSI MARCO CARRAI) - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA MERDA FASCIOMAFIOSA= DI ENNIO DORIS E MASSIMO DORIS: BANCA MEDIOLANUM, COSANOSTRANUM, CAMORRANU= M, NDRANOLANUM - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA BSI ITA= LIA SRL DI VIA SOCRATE 26 MILANO. - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI, NATO A MILANO IL 28.6.19= 65, FINITO "APPENA APPENA" 3 VOLTE IN GALERA TORNIAMO ORA AL DOVUTISSIMO PUNTO INIZIALE, PLEASE. I SATANISTI, NAZIFASCIS= TI, PEDERASTA ED ASSASSINI PAOLO CARDENA' E STEFANO CARDENA' DI CRIMINALISS= IMA CARDENA' CONSULTING, COME DETTO, SONO DIETRO TANTI CASI DI RAPIMENTI, S= TUPRI, UCCISIONI ED OCCULTAMENTO DI CADAVERI DI BAMBINI, RAGAZZINI ED ADULT= I, AVVENUTI SPECIALMENTE NELLE LORO MARCHE, MA NON SOLO ( COME DI UCCISIONI= DI NEONATI E BAMBINI AL FINE DI ANIMALESCO PRELEVARE E TRAFFICARE ORGANI D= EGLI STESSI). IL TUTTO PER CENTINAIA, ANZI, MIGLIAIA E MIGLIAIA DI CASI! MACERATA E' CITTA' DA SEMPRE, SATANISTISSIMA. CON UNO FRA I PIU' ALTI TASSI= MONDIALI DI UCCISIONI VIA OMICIDI MASSONICI E CONSEGUENTI SPARIZIONI ( COL= TUTTO TANTISSIMO SUPERIORE AI GIA' TASSI MOSTRUOSI DI NOTISSIME IN TUTTO C= IO', NEW ORLEANS NEGLI USA O CIUDAD JUAREZ IN MESSICO). E TUTTO QUESTO COME= DA TANTI, TANTISSIMI LINKS CHE VI SONO IN RETE. DA CUI NE PRENDIAMO SOLO T= RE, AL VOLO, PER OVVI MOTIVI DI TEMPO E SPAZIO DIGITALE http://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche-= si-cercano-558-persone/811406/ https://www.ilrestodelcarlino.it/macerata/cronaca/ragazza-scomparsa-14-anni= -ansia-1.3410852 https://www.cronacheancona.it/2017/12/02/persone-scomparse-in-40-anni-quasi= -700-casi-in-tutte-le-marche/68705/ EBBENE, I PEDOFILI BASTARDISSIMAMENTE ASSASSINI PAOLO CARDENA' E STEFANO CA= RDENA' DI CRIMINALISSIMA CARDENA' CONSULTRING FURONO ANCHE I RESPONSABILI D= ELLA UCCISIONE DI PAMELA MASTROPIETRO: STUPRATA, UCCISA E POI SEZIONATA CON= EXPERTISE TIPICA DI MEDICI LEGALI MASSONICI, BIANCHI, MARCHIGIANI, MACERAT= ISSIMI. TRATTASI DI MASSONI ASSASSINI FOTOCOPIA DELLA GANG SANGUINARISSIMA,= AI TEMPI, DEL MOSTRO DI FIRENZE! POTRESTE RAGLIARE DA DENTRO I VOSTRI ASSA= SSINI CAPPUCCI " WAGLIO', E' ARRIVATO SHERLOCK HOLMES DEI POVERI, COME FAI = A DIRE UNA COSA DEL GENERE"? LA MIA RISPOSTA? ECCOLA QUI, WAGLIUNCE', ECCOL= A QUI! "MA CHE STATE GRUGNENDO, STARNAZZANDO, RAGLIANDO VOI? MICA DICO IO T= UTTO CIO'. LO DICE UNO DEI PRINCIPALI GRAN MAESTRI FILO PIDUISTI CHE PIU' S= AN DI TUTTO QUESTO, IMMERSO DA SEMPRE IN MARI DI COMPLOTTI, OMICIDI, SPARIZ= IONI DI MATRICE MASSONICO NAZIFASCISTA, ALIAS DI MATRICE NEO BERLUSCONICCHI= A.. STO SCRIVENDO DEL MASSONE DA SEMPRE DENTRO AD OMICIDI MASSONICI QUALE E= ' E STRA E' IL NOTO SATANISTA COSENTINO, IL MASSONE CALABRESE TUTT'UNO CON = LA NDRANGHETA: GIANFRANCO CARPEORO http://www.carpeoro.com/ ( O ANCHE NOTO SATANISTA COSENTINO, IL MASSONE CALABRESE TUTT'UNO CON LA ND= RANGHETA: GIOVANNI FRANCESCO CARPEORO.. O ANCHE NOTO SATANISTA COSENTINO, I= L MASSONE CALABRESE TUTT'UNO CON LA NDRANGHETA: GIANFRANCO PECORARO O ANCHE= O ANCHE NOTO SATANISTA COSENTINO, IL MASSONE CALABRESE TUTT'UNO CON LA NDR= ANGHETA: GIOVANNI FRANCESCO PECORARO). CHE NE PARLA, DI TUTTO QUESTO, QUI https://petalidiloto.com/2012/12/intervista-carpeoro-su-massoneria-e.html E QUI https://www.youtube.com/watch?v=3DDuJQGxmAvnk INSIEME ALL'ALTRO MASSONE, DA SEMPRE PURE DENTRO TANTISSIMI OMICIDI DI TIPO= MASSONICO: PAOLO FRANCESCHETTI https://petalidiloto.com/2018/02/due-parole-sullomicidio-pamela-mastropietr= o.html CHE RIBADISCE IL TUTTO QUI https://velvetnews.it/2018/05/27/pamela-mastropietro-mafia-nigeriana-legata= -ad-ambienti-massonici/ E QUI http://maestrodidietrologia.blogspot.com/2018/02/pamela-e-luomo-nero-parte-= 1.html COSA SOTTOLINEATA ANCHE DA UN ALTRO PROTAGONISTA DI PARECCHI OMICIDI MASSON= ICI: GIOELE MAGALDI. SI, PROPRIO LUI, IL NAZIFASCISTA LEGHISTA GIOELE MAGAL= DI ( CHE PRENDE PER I FONDELLI IL MONDO, RAGLIANDO SU INTERNET DI ESSERE DI= CENTRO SINISTRA... SI, "DI CENTRO SINISTRA" COME LO ERANO HITLER E MUSSOLI= NI) http://www.libreidee.org/2018/06/magaldi-guerra-ai-massoni-che-hanno-ucciso= -la-democrazia/ ]. DELLA CUI LOGGIA GRANDE ORIENTE DEMOCRATICO FA PARTE IL TRUFFATORE FOGGIANO= DI PALAZZO CHIGI GIUSEPPE CONTE ( CHE PER 9 MESI HA RAGLIATO DI MEGA BOOM = ECONOMICO IN ARRIVO NEL 2019... E CHE ORA, DAVANTI ALLA SUA ENNESIMA IDIOTA= CANNATA, STARNAZZA CHE STAVA SOLO SCHERZANDO... https://www.repubblica.it/= politica/2019/04/10/news/conte_quella_sull_anno_bellissimo_era_solo_una_bat= tuta_-223727910/' A ME PIACEVA IL MOVIMENTO 5 STELLE, IO HO VOTATO MOVIMENTO 5 STELLE ULTIMAM= ENTE, MA SE LO STESSO CONTINUA A STARE CON GLI ASSASSINI NAZISTI E NDRANGHE= TISTI DI LEGA LADRONA, MI INIZIA A SCHIFARE TANTO QUANTO I KU KLUK KLANISTI= OMICIDA DI VIA BELLERIO STESSO, MOVIMENTO 5 STELLE CHE SI PUO' SALVARE SOL= O SE SI UNISCE AGLI AFFATTO MALE NICOLA ZINGARETTI E CHIUNQUE ALTRO DABBENE= DI CENTRO SINISTRA). A FRA NON MOLTO PER ALTRE TONNELLATE DI DETTAGLI A PROPOSITO. SOON BACK . From newsfish@newsfish Thu Aug 1 00:45:02 2024 X-Received: by 2002:a37:9d5:: with SMTP id 204mr9302022qkj.178.1570709116902; Thu, 10 Oct 2019 05:05:16 -0700 (PDT) X-Received: by 2002:a25:3cc7:: with SMTP id j190mr5845239yba.144.1570709116647; Thu, 10 Oct 2019 05:05:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer04.fr7!futter-mich.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no4499704qtl.0!news-out.google.com!q23ni162qtl.1!nntp.google.com!o24no4499694qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Oct 2019 05:05:16 -0700 (PDT) In-Reply-To: <9b2ff4ba-08db-45a8-9297-fa9b30cc7c27@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=152.160.43.162; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 152.160.43.162 References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> <9939c34b-553d-4dac-a8f8-057441448476@googlegroups.com> <9b2ff4ba-08db-45a8-9297-fa9b30cc7c27@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <632171b0-3060-4cd8-a576-7057ffce5d78@googlegroups.com> Subject: Re: Bit vs. std_logic for description of internal structures From: KJ Injection-Date: Thu, 10 Oct 2019 12:05:16 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2738 X-Received-Body-CRC: 132487919 Xref: reader01.eternal-september.org comp.lang.vhdl:9594 On Wednesday, October 9, 2019 at 3:16:44 AM UTC-4, Maciej Sobczak wrote: > Thank you all for your answers, they were very instructive. The general t= heme is that std_logic prevents hiding some of the issues that otherwise mi= ght get lost when narrower bit is used. >=20 Another good take away is that std_ulogic can be generally better than std_= logic since it allows the compiler to catch when you have multiple signal d= rivers on something that should only have one driver. However, whether or = not you find it useful can depend on your design flow. If you tend to simu= late first to get to a somewhat 'working' state then run through synthesis = then you will find the value in using std_ulogic since the compiler will im= mediately flag multiple drivers. The savings is that you don't have to deb= ug to find that type of error. On the other hand if you tend to simulate a= nd synthesize in parallel then the synthesis tool will find and flag multip= le drivers of any type. There is no conversion required between std_logic and std_ulogic but you do= have to convert between std_logic_vector and std_ulogic_vector due to a qu= irk in the way the two are defined. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:02 2024 X-Received: by 2002:aed:228e:: with SMTP id p14mr10869568qtc.190.1570719721798; Thu, 10 Oct 2019 08:02:01 -0700 (PDT) X-Received: by 2002:a0d:eb89:: with SMTP id u131mr7357009ywe.223.1570719721364; Thu, 10 Oct 2019 08:02:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no4958692qtl.0!news-out.google.com!x7ni1504qtf.0!nntp.google.com!o24no4958666qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Oct 2019 08:02:01 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.21.36.103; posting-account=aQ5fBwoAAAAOgfkQPX_fLOtY7cq0ZIxW NNTP-Posting-Host: 78.21.36.103 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <05b0fb77-e835-41c0-aa92-9a4bd5f5ece9@googlegroups.com> Subject: E' DA ARRESTARE L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI GENOVA! IL NOTISSIMO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI! LEGALE MALAVITOSISSIMO............ From: FABIO VENZI-GRAN MAESTRO GLRI Injection-Date: Thu, 10 Oct 2019 15:02:01 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 33376 X-Received-Body-CRC: 2915015638 Lines: 530 Xref: reader01.eternal-september.org comp.lang.vhdl:9595 E' DA ARRESTARE L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMEN= TE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI GENOVA!= IL NOTISSIMO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI! LEGALE MA= LAVITOSISSIMO............... STUPRANTE INFANTI ED ADOLESCENTI, COME PURE OM= ICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E MILA= NO E DI CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDI LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI = MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PIU' D= I SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E= ' STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA ED UCCIDE = I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO CHIAMATO DANIELE MINOTTI! QUESTO = AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI= GENOVA E RAPALLO. https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 FINO A POCO FA..SGOZZAVA OLTRE CHE CANI, GATTI E SERPENTI, TANTISSIMI BAMBI= NI, IN RITI SATANICI DI TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEG= UONO.. I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMA= ZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRI= O DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI http://criminologiasicurezza.blogspot.com/2008/05/satanica-granda-i-luoghi-= del-demonio-in.html http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html https://www.lastampa.it/vatican-insider/it/2018/04/15/news/sette-sataniche-= boom-di-violenze-rituali-1.34005609 https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO! Criminalissimo Studio Cirenei Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Fax +39 010 91 63 11 54 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg ). A CAPO, ANZI, A KAPO' DI SETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA = ASSASSINA CHIAMATA " AMMAZZIAMO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCO= NI". E' AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GE= NOVA E RAPALLO. VEDI QUESTO LINK https://www.py.cz/pipermail/python/2017-April/013002.html UNITO IN CIO' AL PARIMENTI AVVOCATO MASSONE, NAZISTA, LADRO, TRUFFATORE, RI= CICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPPOLITO= . ED AI PARIMENTI SATANAZISTI, CORROTTI, MEGA COCAINOMANI E NOTISSIMI PEDOF= ILI MARIO GIORDANO, CLAUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSE= LMA DEL'OLIO ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTA= TO REGISTA PEDERASTA INCULA BAMBINI GIUSEPPE LAZZARI DI BRESCIA http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 ( CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, E' PAPPA = E CICCIA CON LA PURE MOLTISSIMO PEDOFILA ANSELMA DELL'OLIO STESSA https://www.imdb.com/title/tt1828287/reviews http://www.sentirsidire.it/su-di-me/ VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO A QUESTO LINK https://www.youtube.com/watch?v=3DDLR-DJJWl_M RIPORTANTE UNA TRASMISSIONE DEL NOIOSISSIMO GIGI MARZULLO, CON LA TROIONA S= TUPRA BAMBINI ANSELMA DELL'OLIO ED IL REGISTA PEDERASTA INCULA BAMBINI GIUS= EPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLETTUALMENTE, DIFENDENDO E PR= UOMOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULLLALA' CHE CASO, LA SCHIFOSA= MENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORCO NAZISTA, FIGLIO DI CANE, DA S= EMPRE SUPER PEDERASTA GIULIANO FERRARA, INSIEME AL REGISTA PEDOFILO STUPRA = BAMBINI GIUSEPPE LAZZARI, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN FATTO LEVA= RE... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI CIO' CHE VINCENT= ISSIMAMENTE STIAM QUI SCRIVENDO). IL TUTTO INSIEME ANCHE AL TRE VOLTE FINIT= O IN GALERA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, DI CRIMIN= ALISSIMA BITINCUBATOR & VENTURE, DI CRIMINALISSIMA CRYPTOPOLYS, CRIMINALISS= IMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "MERDATO"= LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFI= LO DEL BITCOIN" https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg https://twitter.com/megliomortiche1 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ). 2 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). =E3=80=80 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 4 E POI ANCORA.. http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! =E3=80=80 5 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ =E3=80=80 =E3=80=80 6 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html https://twitter.com/LavaPaolo ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg 7 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/company D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ =E3=80=80 8 AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://www.instagram.com/p/Bcc0zWonbtv/ E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO https://www.spreaker.com/user/10297125 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". 9 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIP= O QUESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/ https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!! 10 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! https://www.py.cz/pipermail/python/2018-February/013212.html 11 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o) Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova From newsfish@newsfish Thu Aug 1 00:45:03 2024 X-Received: by 2002:ac8:5556:: with SMTP id o22mr8547398qtr.217.1571002470322; Sun, 13 Oct 2019 14:34:30 -0700 (PDT) X-Received: by 2002:a5b:d09:: with SMTP id y9mr106623ybp.113.1571002470035; Sun, 13 Oct 2019 14:34:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer04.fr7!futter-mich.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no4849839qtl.0!news-out.google.com!q23ni665qtl.1!nntp.google.com!o24no4849835qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 13 Oct 2019 14:34:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.88.245.201; posting-account=noSIMgoAAABlmAktjVKtZ8-b3Cxkethg NNTP-Posting-Host: 212.88.245.201 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <899dbf80-29e8-4ee2-8219-8f0860c3b6cb@googlegroups.com> Subject: NOTO COME "IL PEDOFILO DEL BITCOIN": E' PAOLO BARRAI! UN BASTARDO CRIMINALE CHE ORDINA PURE TANTI OMICIDI! E' INDAGATO, AL MOMENTO, DALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD LONDRA E DA FBI NEW YORK. IL TUTTO VIA... From: ROBERTO-GORINI 4 UPPER LTD-LONDON Injection-Date: Sun, 13 Oct 2019 21:34:30 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 23477 X-Received-Body-CRC: 814574288 Xref: reader01.eternal-september.org comp.lang.vhdl:9596 NOTO COME "IL PEDOFILO DEL BITCOIN": E' PAOLO BARRAI! UN BASTARDO CRIMINALE= CHE ORDINA PURE TANTI OMICIDI! E' INDAGATO, AL MOMENTO, DALLA PROCURA DI M= ILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD LONDRA E DA FBI = NEW YORK. IL TUTTO VIA.......EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit MI PRESENTO. SONO ANDREAS NIGG VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN BANK ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK= VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, ALLORCHE' COMPRAMMO LA = EX FINTER BANK ZURICH DEI MASSONI NAZISTI E LEGHISTI PESENTI, IO IN PERSONA= , ANDREAS NIGG, ORDIANI DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI A STA BE= STIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL 28.6.19= 65. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA E CAMORRA, DA LONTANO 3.= 000 KM. MUMBLE, MUMBLE, MUMBLE... SONO SVIZZERO, ICH BIN SCHWEIZER, QUINDI SONO UN = UOMO PRECISO. AMO LA PRECISIONE. PER VIA DI QUESTO, ANALIZZIAMO BEN BENE, O= GNI CONCETTO, DA ORA IN AVANTI, PLEASE! DICEVAMO..... L'ASSASSINO PEDOFILO PAOLO BARRAI, ANCHE NEL 2019, FA CRIMINI TERRIFICANTI = PIU' CHE MAI! TRATTASI DI UN MANDANTE DI OMICIDI, DI UN PEDERASTA CHE STUPR= A ED AMMAZZA TANTI BAMBINI. HA RICICLATO EURO ASSASSINI DI NDRANGHETA IN MA= LAVITOSISSIMA ICO EIDOO!!!!!!!!!!!!!!!!!!!! E' STATO CACCIATO DA CITIBANK E= FATTO CONDANNARE A GALERA DA CITIBANK! HA FATTO FILM PEDOPORNOGRAFICI, STU= PRANDO QUASI A MORTE TANTI BAMBINI! HA UCCISO LUI STESSO, TANTI BAMBINI, PE= R PRENDER I LORO ORGANI E TRAFFICARLI! HA FATTO FILM PORNO CON CAVALLI, BEV= ENDO LITRI DI SPERMA EQUINO! E' STATO MULTATO DA CONSOB BEN 70.000 EURO! HA= 23 CAUSE, CON GENTE DI MEZZA DITTATURA FASCIOMAFIOSA DI BERLUSCONIA, A CUI= HA AZZERATO I RISPARMI! PER SCAPPARE ALLE QUALI, SI E' ORA RIFUGIATO A LON= DRA, OVE FA TANTI POMPINI AL NAZISTA NIGEL FARAGE AFFINCHE' LO PROTEGGA! E'= STATO CONDANNATO AL CARCERE IN BRASILE, ANCHE PER PEDERASTIA VIOLENTA ( E = PER ALTRI TANTISSIMI CRIMINI)! NON NE AZZECCA MAI MEZZA UNA IN BORSA, OVE A= ZZERA I RISPARMI DI TUTTI E SEMPRE! E VI E' TANTISSIMO PIU', DI CUI SCRIVER= EMO FINO A 15 MINUTI DOPO LA NOSTRA MORTE! E' DA ARRESTARE IMMEDIATAMENTE: PAOLO BARRAI (CRYPTOPOLIS E CRYPTOLAB)! E' = STATO IL REGISTA CRIMINALE DELL'OPERAZIONE "EIDOO RICICLA CASH MAFIOSO PER = LA NDRANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE BASTARDO P= AOLO BARRAI, ABITAVA A MILANO, IN VIA.......... IPPODROMO 105 (ZONA SAN SIR= O- CERTOSA). ED IN ZONA SAN SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEG= A ASSASSINI GIULIANO MARTINO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTIN= O, IN CONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA VINCENZO MARTINO, IN CO= NNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA DOMENICO MARTINO. COME PURE PER= IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO. POSE POI TUTTA STA GANG MALAVI= TOSA IN CONTATTO COL PORCO MALAVITOSO OLIVER CAMPONOVO DI CHIASSO! COME DA = QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. OLTRE AD ESSERE PEDOFILO ED ASSASSINO, E' SPACCIATORE DI COCAINA E MEGA RIC= ICLA SOLDI MAFIOSI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CR= YPTOLAB E CRIMINALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NAZISTA, MAFIOSO, MEGA ASSASSINO VLADIMIR PUTIN https://www.jornalopcao.com.br/colunas-e-blogs/imprensa/livro-expoe-o-russo= -vladimir-putin-como-chefao-de-regime-assassino-e-corrupto-128511/ - ALLO STALKER VIA INTERNET, NONCHE' EBREO NAZISTA LEONARDO FOA' (COSA CHE = GIA' DIMOSTRA DI CHE TOPO DI FOGNA STO SCRIVENDO). FIGLIO DEL MEGA PEZZO DI= MERDA MARCELLO FOA' CHE STA RENDENDO LA RAI TELEPINOCHET, TELEMUSSOLINI, T= ELE E PURE TELESTEFANODELLECHIAIE - FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFILO M= EGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMENTE^= ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI ERA= NO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) TANTISSIMO PIU', A SEGUIRE, NEI PROSSIMI GIORNI!!!!!!!!!!!!!! - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lug= ano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dello = Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di B= anca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele Za= nzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://citywire.ch/manager/andreas-nigg/d2395 https://ch.linkedin.com/in/andreasnigg?trk=3Dpeople-guest_profile-result-ca= rd_result-card_full-clic From newsfish@newsfish Thu Aug 1 00:45:03 2024 X-Received: by 2002:a05:6214:1108:: with SMTP id e8mr31165926qvs.231.1571084811322; Mon, 14 Oct 2019 13:26:51 -0700 (PDT) X-Received: by 2002:a25:bdd0:: with SMTP id g16mr9282086ybk.319.1571084810546; Mon, 14 Oct 2019 13:26:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!o24no7997984qtl.0!news-out.google.com!q23ni785qtl.1!nntp.google.com!o24no7997979qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Oct 2019 13:26:50 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=31.31.151.47; posting-account=IG2V5QoAAADWNB-jCtBjZSg45IY7zzEI NNTP-Posting-Host: 31.31.151.47 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7de9a6eb-787d-495f-97e3-9dff94a603e2@googlegroups.com> Subject: E' DA ARRESTARE L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI GENOVA! IL NOTISSIMO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LEGALE MALAVITOSISSIMO, STUPR From: ANTONIO BINNI - BASTA COL PEDOFILO BERLUSCONI Injection-Date: Mon, 14 Oct 2019 20:26:51 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 33381 X-Received-Body-CRC: 3785022270 Xref: reader01.eternal-september.org comp.lang.vhdl:9597 E' DA ARRESTARE L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMEN= TE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI GENOVA!= IL NOTISSIMO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LEGA= LE MALAVITOSISSIMO, STUPRANTE INFANTI ED ADOLESCENTI, COME PURE OMICIDA: DA= NIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E MILANO E DI C= RIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDI LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI = MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PIU' D= I SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E= ' STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA ED UCCIDE = I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO CHIAMATO DANIELE MINOTTI! QUESTO = AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI= GENOVA E RAPALLO. https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 FINO A POCO FA..SGOZZAVA OLTRE CHE CANI, GATTI E SERPENTI, TANTISSIMI BAMBI= NI, IN RITI SATANICI DI TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEG= UONO.. I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMA= ZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRI= O DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI http://criminologiasicurezza.blogspot.com/2008/05/satanica-granda-i-luoghi-= del-demonio-in.html http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html https://www.lastampa.it/vatican-insider/it/2018/04/15/news/sette-sataniche-= boom-di-violenze-rituali-1.34005609 https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO! Criminalissimo Studio Cirenei Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Fax +39 010 91 63 11 54 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg ). A CAPO, ANZI, A KAPO' DI SETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA = ASSASSINA CHIAMATA " AMMAZZIAMO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCO= NI". E' AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GE= NOVA E RAPALLO. VEDI QUESTO LINK https://www.py.cz/pipermail/python/2017-April/013002.html UNITO IN CIO' AL PARIMENTI AVVOCATO MASSONE, NAZISTA, LADRO, TRUFFATORE, RI= CICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPPOLITO= . ED AI PARIMENTI SATANAZISTI, CORROTTI, MEGA COCAINOMANI E NOTISSIMI PEDOF= ILI MARIO GIORDANO, CLAUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSE= LMA DEL'OLIO ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTA= TO REGISTA PEDERASTA INCULA BAMBINI GIUSEPPE LAZZARI DI BRESCIA http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 ( CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, E' PAPPA = E CICCIA CON LA PURE MOLTISSIMO PEDOFILA ANSELMA DELL'OLIO STESSA https://www.imdb.com/title/tt1828287/reviews http://www.sentirsidire.it/su-di-me/ VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO A QUESTO LINK https://www.youtube.com/watch?v=3DDLR-DJJWl_M RIPORTANTE UNA TRASMISSIONE DEL NOIOSISSIMO GIGI MARZULLO, CON LA TROIONA S= TUPRA BAMBINI ANSELMA DELL'OLIO ED IL REGISTA PEDERASTA INCULA BAMBINI GIUS= EPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLETTUALMENTE, DIFENDENDO E PR= UOMOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULLLALA' CHE CASO, LA SCHIFOSA= MENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORCO NAZISTA, FIGLIO DI CANE, DA S= EMPRE SUPER PEDERASTA GIULIANO FERRARA, INSIEME AL REGISTA PEDOFILO STUPRA = BAMBINI GIUSEPPE LAZZARI, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN FATTO LEVA= RE... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI CIO' CHE VINCENT= ISSIMAMENTE STIAM QUI SCRIVENDO). IL TUTTO INSIEME ANCHE AL TRE VOLTE FINIT= O IN GALERA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, DI CRIMIN= ALISSIMA BITINCUBATOR & VENTURE, DI CRIMINALISSIMA CRYPTOPOLYS, CRIMINALISS= IMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "MERDATO"= LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFI= LO DEL BITCOIN" https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg https://twitter.com/megliomortiche1 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ). 2 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). =E3=80=80 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 4 E POI ANCORA.. http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! =E3=80=80 5 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ =E3=80=80 =E3=80=80 6 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html https://twitter.com/LavaPaolo ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg 7 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/company D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ =E3=80=80 8 AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://www.instagram.com/p/Bcc0zWonbtv/ E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO https://www.spreaker.com/user/10297125 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". 9 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIP= O QUESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/ https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!! 10 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! https://www.py.cz/pipermail/python/2018-February/013212.html 11 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o) Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:45:03 2024 X-Received: by 2002:aed:2f86:: with SMTP id m6mr3379155qtd.55.1571313103378; Thu, 17 Oct 2019 04:51:43 -0700 (PDT) X-Received: by 2002:a81:6cd3:: with SMTP id h202mr2227856ywc.223.1571313103020; Thu, 17 Oct 2019 04:51:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no6513524qtl.0!news-out.google.com!x7ni116qtf.0!nntp.google.com!o24no6513514qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Oct 2019 04:51:42 -0700 (PDT) In-Reply-To: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2605:a000:1301:12c4:25d1:b0f0:bcb4:bf22; posting-account=wln-AQoAAADRtUVmpKvekqmwypvFv5BO NNTP-Posting-Host: 2605:a000:1301:12c4:25d1:b0f0:bcb4:bf22 References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Bit vs. std_logic for description of internal structures From: cmelias@woh.rr.com Injection-Date: Thu, 17 Oct 2019 11:51:43 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 32 Xref: reader01.eternal-september.org comp.lang.vhdl:9598 On Monday, October 7, 2019 at 3:07:18 AM UTC-4, Maciej Sobczak wrote: > Hi, >=20 > I have found a coding guideline that recommends to use std_logic everywhe= re in preference to bit, on the basis that it can represent more states (X,= Z, etc.). > What I found surprising is the implicit assumption that more states is an= added value. I understand that on the module boundary the additional state= s can be useful, as they can model (or even enable) wider interfacing optio= ns. But for modeling (and ultimately synthesis) of internal logic, I see no= particular benefit - on the contrary, I can imagine that it might be benef= icial to restrict the number of possible states as much as possible and in = fact, elsewhere designers are encouraged to always use (or define) the narr= owest type that covers the given context. Additional and unused states are = also problematic with language constructs like the case statement, which ex= pect complete coverage and code fragments like this: >=20 > case my_std_logic_value is > when '0' =3D> ... > when '1' =3D> ... > when others =3D> > assert false; > end case; >=20 > obviously miss the point. >=20 > So I find such guidelines contradicting each other. What is your opinion = on this? Are there other aspects worth discussing? Do you feel bad using bi= t(_vector) for modeling internal logic? >=20 > --=20 > Maciej Sobczak * http://www.inspirel.com From newsfish@newsfish Thu Aug 1 00:45:03 2024 X-Received: by 2002:ac8:1975:: with SMTP id g50mr18865067qtk.268.1571664867501; Mon, 21 Oct 2019 06:34:27 -0700 (PDT) X-Received: by 2002:a81:254e:: with SMTP id l75mr15743812ywl.90.1571664867272; Mon, 21 Oct 2019 06:34:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no9851500qtl.0!news-out.google.com!q23ni88qtl.1!nntp.google.com!o24no9851498qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Oct 2019 06:34:26 -0700 (PDT) In-Reply-To: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2605:a000:1301:12c4:ec7d:5a64:5d4f:3493; posting-account=wln-AQoAAADRtUVmpKvekqmwypvFv5BO NNTP-Posting-Host: 2605:a000:1301:12c4:ec7d:5a64:5d4f:3493 References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <248ac264-6a92-4bff-9c07-0d7fcc8423e8@googlegroups.com> Subject: Re: Bit vs. std_logic for description of internal structures From: cmelias@woh.rr.com Injection-Date: Mon, 21 Oct 2019 13:34:27 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9599 On Monday, October 7, 2019 at 3:07:18 AM UTC-4, Maciej Sobczak wrote: > Hi, >=20 > I have found a coding guideline that recommends to use std_logic everywhe= re in preference to bit, on the basis that it can represent more states (X,= Z, etc.). > What I found surprising is the implicit assumption that more states is an= added value. I understand that on the module boundary the additional state= s can be useful, as they can model (or even enable) wider interfacing optio= ns. But for modeling (and ultimately synthesis) of internal logic, I see no= particular benefit - on the contrary, I can imagine that it might be benef= icial to restrict the number of possible states as much as possible and in = fact, elsewhere designers are encouraged to always use (or define) the narr= owest type that covers the given context. Additional and unused states are = also problematic with language constructs like the case statement, which ex= pect complete coverage and code fragments like this: >=20 > case my_std_logic_value is > when '0' =3D> ... > when '1' =3D> ... > when others =3D> > assert false; > end case; >=20 > obviously miss the point. >=20 > So I find such guidelines contradicting each other. What is your opinion = on this? Are there other aspects worth discussing? Do you feel bad using bi= t(_vector) for modeling internal logic? >=20 > --=20 > Maciej Sobczak * http://www.inspirel.com From newsfish@newsfish Thu Aug 1 00:45:04 2024 X-Received: by 2002:a37:2ec5:: with SMTP id u188mr2464507qkh.94.1571743743403; Tue, 22 Oct 2019 04:29:03 -0700 (PDT) X-Received: by 2002:a25:3b10:: with SMTP id i16mr1939833yba.188.1571743743039; Tue, 22 Oct 2019 04:29:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!o24no2725541qtl.0!news-out.google.com!x7ni464qtf.0!nntp.google.com!o24no2725531qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Oct 2019 04:29:02 -0700 (PDT) In-Reply-To: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2605:a000:1301:12c4:7025:f85d:a43f:d47a; posting-account=wln-AQoAAADRtUVmpKvekqmwypvFv5BO NNTP-Posting-Host: 2605:a000:1301:12c4:7025:f85d:a43f:d47a References: <2e56996d-b8ee-4197-b62f-b5a34ad880a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <59c81524-b87d-4967-8015-3766ecacba4e@googlegroups.com> Subject: Re: Bit vs. std_logic for description of internal structures From: cmelias@woh.rr.com Injection-Date: Tue, 22 Oct 2019 11:29:03 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 35 Xref: reader01.eternal-september.org comp.lang.vhdl:9600 On Monday, October 7, 2019 at 3:07:18 AM UTC-4, Maciej Sobczak wrote: > Hi, >=20 > I have found a coding guideline that recommends to use std_logic everywhe= re in preference to bit, on the basis that it can represent more states (X,= Z, etc.). > What I found surprising is the implicit assumption that more states is an= added value. I understand that on the module boundary the additional state= s can be useful, as they can model (or even enable) wider interfacing optio= ns. But for modeling (and ultimately synthesis) of internal logic, I see no= particular benefit - on the contrary, I can imagine that it might be benef= icial to restrict the number of possible states as much as possible and in = fact, elsewhere designers are encouraged to always use (or define) the narr= owest type that covers the given context. Additional and unused states are = also problematic with language constructs like the case statement, which ex= pect complete coverage and code fragments like this: >=20 > case my_std_logic_value is > when '0' =3D> ... > when '1' =3D> ... > when others =3D> > assert false; > end case; >=20 > obviously miss the point. >=20 > So I find such guidelines contradicting each other. What is your opinion = on this? Are there other aspects worth discussing? Do you feel bad using bi= t(_vector) for modeling internal logic? >=20 > --=20 > Maciej Sobczak * http://www.inspirel.com The Z state is needed to implement a bidirectional bus. Such a bus is neede= d, for example, to work with on-board read-write memory; direction into mem= ory for write, out of memory for read. I have used this in practice. From newsfish@newsfish Thu Aug 1 00:45:04 2024 X-Received: by 2002:a05:6214:286:: with SMTP id l6mr4949254qvv.236.1571772423467; Tue, 22 Oct 2019 12:27:03 -0700 (PDT) X-Received: by 2002:a81:5ed4:: with SMTP id s203mr32650ywb.485.1571772422784; Tue, 22 Oct 2019 12:27:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no3971221qtl.0!news-out.google.com!x7ni514qtf.0!nntp.google.com!o24no3971214qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Oct 2019 12:27:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.173.246.14; posting-account=FoeLKgoAAACtyy2nj1ZIjNlooAtqNYQK NNTP-Posting-Host: 37.173.246.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1da371b0-42a6-4343-a18b-8671e858d3ca@googlegroups.com> Subject: Insert stimulus internal module signal From: Raphael Viera Injection-Date: Tue, 22 Oct 2019 19:27:03 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9601 I have a verilog testbench in order to perform gate level simulation of a m= odule. I want to inject a transient voltage at the output of specific gates= inside the module but can't find a way to do it. I can of course insert tr= ansient voltages (like glitches) at the inputs (example below), but I need = to inject on internal signals. Can anyone shed a light on the issue? Example: glitch in a clock signal always begin: voltage_transient #10 force clk =3D 1; #0.5 force clk =3D 0; #1 release clk; end From newsfish@newsfish Thu Aug 1 00:45:04 2024 X-Received: by 2002:a05:620a:342:: with SMTP id t2mr4707852qkm.251.1571773247575; Tue, 22 Oct 2019 12:40:47 -0700 (PDT) X-Received: by 2002:a25:bdd0:: with SMTP id g16mr3686080ybk.319.1571773247147; Tue, 22 Oct 2019 12:40:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!o24no4009349qtl.0!news-out.google.com!x7ni514qtf.0!nntp.google.com!o24no4009345qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Oct 2019 12:40:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.173.246.14; posting-account=FoeLKgoAAACtyy2nj1ZIjNlooAtqNYQK NNTP-Posting-Host: 37.173.246.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <694ef56d-c482-47b5-bde4-6f8472b3dc37@googlegroups.com> Subject: Insert transient voltage on internal signal of a module - Verilog From: Raphael Viera Injection-Date: Tue, 22 Oct 2019 19:40:47 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9602 I have a verilog testbench in order to perform gate level simulation of a m= odule. I want to inject a transient voltage at the output of specific gates= inside the module but can't find a way to do it. I can insert transient vo= ltages (like glitches) at the inputs (example below), but I need to inject = on internal signals. Can anyone shed a light on the issue? Example: glitch in a clock signal (https://stackoverflow.com/questions/2251= 465/producing-a-clock-glitch-in-a-verilog-design) always begin: inject_clk_glitch #1 force clk =3D 1; #1 force clk =3D 0; #1 release clk; end From newsfish@newsfish Thu Aug 1 00:45:05 2024 X-Received: by 2002:a37:e10e:: with SMTP id c14mr9080027qkm.408.1571944416743; Thu, 24 Oct 2019 12:13:36 -0700 (PDT) X-Received: by 2002:a0d:e808:: with SMTP id r8mr7906299ywe.275.1571944416357; Thu, 24 Oct 2019 12:13:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!82.197.223.106.MISMATCH!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!h21no2707175qto.0!news-out.google.com!x7ni779qtf.0!nntp.google.com!h21no2707162qto.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Oct 2019 12:13:36 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.78.184.31; posting-account=QfLpuAkAAABiAn4N5aFUKXKKuVOJoAtr NNTP-Posting-Host: 194.78.184.31 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2dc1eed0-e231-4704-a5f6-fb325f9c2408@googlegroups.com> Subject: E' DA ARRESTARE L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI GENOVA! IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LEGALE MALAVITOSISSIMO STUPRANTE.. From: LUIGI ROTUNNO LA TORRE RESORT - BRASIUUU Injection-Date: Thu, 24 Oct 2019 19:13:36 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9603 E' DA ARRESTARE L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMEN= TE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI GENOVA!= IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LEGALE MA= LAVITOSISSIMO STUPRANTE......... INFANTI ED ADOLESCENTI, COME PURE OMICIDA:= DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E MILANO E D= I CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDI LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI = MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PIU' D= I SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E= ' STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA ED UCCIDE = I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO CHIAMATO DANIELE MINOTTI! QUESTO = AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI= GENOVA E RAPALLO. https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! 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I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMA= ZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRI= O DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI http://criminologiasicurezza.blogspot.com/2008/05/satanica-granda-i-luoghi-= del-demonio-in.html http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html https://www.lastampa.it/vatican-insider/it/2018/04/15/news/sette-sataniche-= boom-di-violenze-rituali-1.34005609 https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO! 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ULLLALA' CHE CASO, LA SCHIFOSA= MENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORCO NAZISTA, FIGLIO DI CANE, DA S= EMPRE SUPER PEDERASTA GIULIANO FERRARA, INSIEME AL REGISTA PEDOFILO STUPRA = BAMBINI GIUSEPPE LAZZARI, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN FATTO LEVA= RE... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI CIO' CHE VINCENT= ISSIMAMENTE STIAM QUI SCRIVENDO). IL TUTTO INSIEME ANCHE AL TRE VOLTE FINIT= O IN GALERA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, DI CRIMIN= ALISSIMA BITINCUBATOR & VENTURE, DI CRIMINALISSIMA CRYPTOPOLYS, CRIMINALISS= IMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "MERDATO"= LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFI= LO DEL BITCOIN" https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg https://twitter.com/megliomortiche1 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ). 2 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). =E3=80=80 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 4 E POI ANCORA.. http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! =E3=80=80 5 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ =E3=80=80 =E3=80=80 6 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html https://twitter.com/LavaPaolo ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg 7 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/company D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ =E3=80=80 8 AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://www.instagram.com/p/Bcc0zWonbtv/ E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO https://www.spreaker.com/user/10297125 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". 9 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIP= O QUESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/ https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!! 10 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! https://www.py.cz/pipermail/python/2018-February/013212.html 11 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o) Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:45:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx15.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Insert transient voltage on internal signal of a module - Verilog Newsgroups: comp.lang.vhdl References: <694ef56d-c482-47b5-bde4-6f8472b3dc37@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <694ef56d-c482-47b5-bde4-6f8472b3dc37@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 191023-2, 23/10/2019), Outbound message X-Antivirus-Status: Clean Lines: 25 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Fri, 25 Oct 2019 09:38:46 UTC Organization: virginmedia.com Date: Fri, 25 Oct 2019 10:38:45 +0100 X-Received-Bytes: 2055 X-Received-Body-CRC: 2605637430 Xref: reader01.eternal-september.org comp.lang.vhdl:9604 On 22/10/2019 20:40, Raphael Viera wrote: > > > I have a verilog testbench in order to perform gate level simulation of a module. I want to inject a transient voltage at the output of specific gates inside the module but can't find a way to do it. I can insert transient voltages (like glitches) at the inputs (example below), but I need to inject on internal signals. Can anyone shed a light on the issue? > > Example: glitch in a clock signal (https://stackoverflow.com/questions/2251465/producing-a-clock-glitch-in-a-verilog-design) > > always begin: inject_clk_glitch > #1 force clk = 1; > #1 force clk = 0; > #1 release clk; > end > If you have access to Modelsim/Questa/Riviera have a look a look at signalspy which is more capable than Verilog/VHDL's force language construct. You could also look at the Tcl force command which has similar capabilities. Both should be able to force a signal/logic/etc in your netlist. Good luck, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:45:05 2024 X-Received: by 2002:aed:3282:: with SMTP id z2mr942810qtd.221.1572301485096; Mon, 28 Oct 2019 15:24:45 -0700 (PDT) X-Received: by 2002:a25:9012:: with SMTP id s18mr10175439ybl.133.1572301484360; Mon, 28 Oct 2019 15:24:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!j16no9707507qtl.0!news-out.google.com!d16ni265qtp.0!nntp.google.com!j16no9707494qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Oct 2019 15:24:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.205.94.166; posting-account=IBPoQgoAAADSDBvtkNJoK2_kNdjRK595 NNTP-Posting-Host: 62.205.94.166 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9a042c9d-57f4-4752-8918-126ba4702e88@googlegroups.com> Subject: E' DA ARRESTARE L'AVV ASSASSINO DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA E KILLER DANIELE MINOTTI DI GENOVA! IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LEGALE MALAVITOSISSIMO...... From: MARTIN ZAPICO EX OF NAZIFASCIST MORGAN STANLEY Injection-Date: Mon, 28 Oct 2019 22:24:45 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9605 E' DA ARRESTARE L'AVV ASSASSINO DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IM= MEDIATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA E KILLER DANIELE MINOTTI DI G= ENOVA! IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LEG= ALE MALAVITOSISSIMO.........STUPRANTE INFANTI ED ADOLESCENTI, COME PURE OMI= CIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E MILAN= O E DI CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDI LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI = MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PIU' D= I SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E= ' STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA ED UCCIDE = I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO CHIAMATO DANIELE MINOTTI! QUESTO = AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI= GENOVA E RAPALLO. https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 FINO A POCO FA..SGOZZAVA OLTRE CHE CANI, GATTI E SERPENTI, TANTISSIMI BAMBI= NI, IN RITI SATANICI DI TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEG= UONO.. I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMA= ZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRI= O DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI http://criminologiasicurezza.blogspot.com/2008/05/satanica-granda-i-luoghi-= del-demonio-in.html http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html https://www.lastampa.it/vatican-insider/it/2018/04/15/news/sette-sataniche-= boom-di-violenze-rituali-1.34005609 https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO! Criminalissimo Studio Cirenei Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Fax +39 010 91 63 11 54 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg ). A CAPO, ANZI, A KAPO' DI SETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA = ASSASSINA CHIAMATA " AMMAZZIAMO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCO= NI". E' AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GE= NOVA E RAPALLO. VEDI QUESTO LINK https://www.py.cz/pipermail/python/2017-April/013002.html UNITO IN CIO' AL PARIMENTI AVVOCATO MASSONE, NAZISTA, LADRO, TRUFFATORE, RI= CICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPPOLITO= . ED AI PARIMENTI SATANAZISTI, CORROTTI, MEGA COCAINOMANI E NOTISSIMI PEDOF= ILI MARIO GIORDANO, CLAUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSE= LMA DEL'OLIO ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTA= TO REGISTA PEDERASTA INCULA BAMBINI GIUSEPPE LAZZARI DI BRESCIA http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 ( CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, E' PAPPA = E CICCIA CON LA PURE MOLTISSIMO PEDOFILA ANSELMA DELL'OLIO STESSA https://www.imdb.com/title/tt1828287/reviews http://www.sentirsidire.it/su-di-me/ VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO A QUESTO LINK https://www.youtube.com/watch?v=3DDLR-DJJWl_M RIPORTANTE UNA TRASMISSIONE DEL NOIOSISSIMO GIGI MARZULLO, CON LA TROIONA S= TUPRA BAMBINI ANSELMA DELL'OLIO ED IL REGISTA PEDERASTA INCULA BAMBINI GIUS= EPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLETTUALMENTE, DIFENDENDO E PR= UOMOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULLLALA' CHE CASO, LA SCHIFOSA= MENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORCO NAZISTA, FIGLIO DI CANE, DA S= EMPRE SUPER PEDERASTA GIULIANO FERRARA, INSIEME AL REGISTA PEDOFILO STUPRA = BAMBINI GIUSEPPE LAZZARI, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN FATTO LEVA= RE... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI CIO' CHE VINCENT= ISSIMAMENTE STIAM QUI SCRIVENDO). IL TUTTO INSIEME ANCHE AL TRE VOLTE FINIT= O IN GALERA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, DI CRIMIN= ALISSIMA BITINCUBATOR & VENTURE, DI CRIMINALISSIMA CRYPTOPOLYS, CRIMINALISS= IMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "MERDATO"= LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFI= LO DEL BITCOIN" https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg https://twitter.com/megliomortiche1 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ). 2 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). =E3=80=80 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 4 E POI ANCORA.. http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! =E3=80=80 5 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ =E3=80=80 =E3=80=80 6 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html https://twitter.com/LavaPaolo ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg 7 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/company D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ =E3=80=80 8 AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://www.instagram.com/p/Bcc0zWonbtv/ E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO https://www.spreaker.com/user/10297125 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". 9 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIP= O QUESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/ https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!! 10 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! https://www.py.cz/pipermail/python/2018-February/013212.html 11 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o) Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:45:06 2024 X-Received: by 2002:aed:2f01:: with SMTP id l1mr20841014qtd.232.1572994210686; Tue, 05 Nov 2019 14:50:10 -0800 (PST) X-Received: by 2002:a25:bd91:: with SMTP id f17mr29945454ybh.77.1572994209749; Tue, 05 Nov 2019 14:50:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!j16no3715720qtl.0!news-out.google.com!p4ni278qtu.1!nntp.google.com!j16no3715718qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Nov 2019 14:50:09 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=31.31.151.104; posting-account=QfLpuAkAAABiAn4N5aFUKXKKuVOJoAtr NNTP-Posting-Host: 31.31.151.104 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7ef6ae64-7034-45b9-a51f-c03ff4bb66ad@googlegroups.com> Subject: E' DA ARRESTARE SUBITO L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMEDIATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI GENOVA! IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LEGALE MALAVITOSISSIMO..... From: LUIGI ROTUNNO LA TORRE RESORT - BRASIUUU Injection-Date: Tue, 05 Nov 2019 22:50:10 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9606 E' DA ARRESTARE SUBITO L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMED= IATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI = GENOVA! IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LE= GALE MALAVITOSISSIMO......... STUPRANTE INFANTI ED ADOLESCENTI, COME PURE O= MICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E MIL= ANO E DI CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO (=20 https://studiolegalelisi.it/team/daniele-minotti/=20 STUDI LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI = MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PIU' D= I SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E= ' STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA ED UCCIDE = I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO CHIAMATO DANIELE MINOTTI! QUESTO = AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI= GENOVA E RAPALLO.=20 https://www.flickr.com/photos/danieleminotti/=20 https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg= =20 RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO!=20 https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi=20 1=20 FINO A POCO FA..SGOZZAVA OLTRE CHE CANI, GATTI E SERPENTI, TANTISSIMI BAMBI= NI, IN RITI SATANICI DI TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEG= UONO.. I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMA= ZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRI= O DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI=20 http://criminologiasicurezza.blogspot.com/2008/05/satanica-granda-i-luoghi-= del-demonio-in.html=20 http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html=20 https://www.lastampa.it/vatican-insider/it/2018/04/15/news/sette-sataniche-= boom-di-violenze-rituali-1.34005609=20 https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html=20 FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI OMICIDA CRIMINI=20 http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml=20 https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/=20 https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html )=20 E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO!=20 Criminalissimo Studio Cirenei=20 Sede di Rapallo (GE)=20 Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE)=20 Tel. +39 0185 57880=20 Fax +39 010 91 63 11 54=20 Sede di Genova=20 Via XX Settembre 3/13 16121 =E2=80=93 GENOVA=20 NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER=20 https://www.flickr.com/photos/danieleminotti/=20 https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg= =20 ). A CAPO, ANZI, A KAPO' DI SETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA = ASSASSINA CHIAMATA " AMMAZZIAMO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCO= NI". E' AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GE= NOVA E RAPALLO.=20 VEDI QUESTO LINK=20 https://www.py.cz/pipermail/python/2017-April/013002.html=20 UNITO IN CIO' AL PARIMENTI AVVOCATO MASSONE, NAZISTA, LADRO, TRUFFATORE, RI= CICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPPOLITO= . ED AI PARIMENTI SATANAZISTI, CORROTTI, MEGA COCAINOMANI E NOTISSIMI PEDOF= ILI MARIO GIORDANO, CLAUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSE= LMA DEL'OLIO ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTA= TO REGISTA PEDERASTA INCULA BAMBINI GIUSEPPE LAZZARI DI BRESCIA=20 http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38=20 ( CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, E' PAPPA = E CICCIA CON LA PURE MOLTISSIMO PEDOFILA ANSELMA DELL'OLIO STESSA=20 https://www.imdb.com/title/tt1828287/reviews=20 http://www.sentirsidire.it/su-di-me/=20 VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO A QUESTO LINK=20 https://www.youtube.com/watch?v=3DDLR-DJJWl_M=20 RIPORTANTE UNA TRASMISSIONE DEL NOIOSISSIMO GIGI MARZULLO, CON LA TROIONA S= TUPRA BAMBINI ANSELMA DELL'OLIO ED IL REGISTA PEDERASTA INCULA BAMBINI GIUS= EPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLETTUALMENTE, DIFENDENDO E PR= UOMOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULLLALA' CHE CASO, LA SCHIFOSA= MENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORCO NAZISTA, FIGLIO DI CANE, DA S= EMPRE SUPER PEDERASTA GIULIANO FERRARA, INSIEME AL REGISTA PEDOFILO STUPRA = BAMBINI GIUSEPPE LAZZARI, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN FATTO LEVA= RE... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI CIO' CHE VINCENT= ISSIMAMENTE STIAM QUI SCRIVENDO). IL TUTTO INSIEME ANCHE AL TRE VOLTE FINIT= O IN GALERA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, DI CRIMIN= ALISSIMA BITINCUBATOR & VENTURE, DI CRIMINALISSIMA CRYPTOPOLYS, CRIMINALISS= IMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "MERDATO"= LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFI= LO DEL BITCOIN"=20 https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg= =20 https://twitter.com/megliomortiche1=20 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png=20 http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html=20 http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion=20 https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai= =20 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato=20 http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html=20 http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950= =20 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/=20 http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ).=20 2=20 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO!=20 BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'!=20 INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI=20 https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/=20 http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649=20 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ )=20 E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO!=20 VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O=20 https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/=20 https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/=20 https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html=20 https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html=20 https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= /=20 IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART=20 https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html=20 http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ).=20 =E3=80=80=20 3=20 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI=20 http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html=20 POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI=20 IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS=20 https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html=20 https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/=20 http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861=20 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html=20 http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php=20 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/=20 http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/=20 https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/=20 http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861=20 4=20 E POI ANCORA..=20 http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx=20 https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html=20 https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html=20 https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/=20 http://www.pmli.it/sismicolpivanemiciberlusconi.htm=20 https://www.agoravox.it/Documenti-segreti-made-in-Italy.html=20 http://forum.enti.it/viewtopic.php?t=3D66625=20 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/=20 https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/=20 http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html=20 http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l=20 MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO!=20 TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE!=20 SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5= =20 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur=20 https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7=20 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI=20 https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml=20 https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )!=20 =E3=80=80=20 5=20 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO=20 https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ).=20 STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI=20 http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ).=20 ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF=20 https://twitter.com/grandebluff=20 https://it-it.facebook.com/stefano.bassi.758=20 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA=20 http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html=20 ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI.=20 https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/=20 https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/=20 =E3=80=80=20 =E3=80=80=20 6=20 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80=20 https://www.py.cz/pipermail/python/2017-September/013036.html=20 https://twitter.com/LavaPaolo=20 ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO=20 https://a.mytrend.it/authors/1385.jpg=20 COME DA COTANTO DI QUESTI ARTICOLI=20 https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html=20 https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ).=20 RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786=20 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA=20 http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html=20 https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/=20 https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ )= =20 UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8!=20 https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg=20 7=20 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND=20 http://it.viadeo.com/it/profile/rocco.tripodi=20 PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES).=20 https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A=20 TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA'=20 https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ).=20 CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO=20 https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ .=20 COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA!=20 https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/=20 DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D)=20 https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/=20 E FRAUNFELD (CH),=20 https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/=20 PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E!=20 https://eidoo.io/company=20 D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA=20 https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l=20 https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/=20 https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/=20 https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/=20 =E3=80=80=20 8=20 AND THEN AGAIN AND AGAIN AND AGAIN...=20 FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA=20 https://twitter.com/mlnews_com?lang=3Des=20 https://it.linkedin.com/in/maurizio-barbero-a521978=20 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE).=20 ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA!=20 https://it.linkedin.com/in/matteo-pardu-90658820=20 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO.=20 https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI=20 https://www.instagram.com/p/Bcc0zWonbtv/=20 E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE=20 https://it.linkedin.com/in/piera-clerico-77793388=20 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 )=20 LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE=20 http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/=20 AND THERE WE GO AGAIN AND AGAIN...=20 DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO=20 https://www.spreaker.com/user/10297125=20 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )".=20 9=20 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO=20 https://www.linkedin.com/in/andrea-scarsi-67a04a9=20 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA=20 http://www.telefree.it/news.php?op=3Dview&id=3D2285=20 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6=20 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE=20 https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/=20 SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI=20 http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/=20 ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIP= O QUESTA=20 http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 )=20 MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6=20 "AGAIN AND AGAIN AND AGAIN"!!!=20 https://www.youtube.com/watch?v=3DwB5KgOXHcxc=20 VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)!=20 NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO"=20 http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html=20 PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI=20 http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html=20 https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/=20 http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html=20 https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147=20 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS=20 ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI=20 https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/= =20 https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi= =20 http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!!=20 10=20 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO)=20 http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38=20 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI= =20 Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio]=20 https://www.youtube.com/watch?v=3DDLR-DJJWl_M ).=20 ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO:=20 https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) !=20 PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!!=20 ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!!=20 https://www.py.cz/pipermail/python/2018-February/013212.html=20 11=20 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan.=20 Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o)=20 Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:45:06 2024 X-Received: by 2002:a0c:95a1:: with SMTP id s30mr25596203qvs.110.1573502128666; Mon, 11 Nov 2019 11:55:28 -0800 (PST) X-Received: by 2002:a81:9216:: with SMTP id j22mr1585663ywg.223.1573502128142; Mon, 11 Nov 2019 11:55:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.alt.net!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!j16no11120164qtl.0!news-out.google.com!p4ni346qtu.1!nntp.google.com!j16no11120158qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 11 Nov 2019 11:55:27 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=84.198.244.197; posting-account=ixzXGgoAAADkhLm6OjEOE5uGjsHUSYrw NNTP-Posting-Host: 84.198.244.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <75c02cbd-27e8-481e-ad45-3801013d365b@googlegroups.com> Subject: =?UTF-8?Q?=C3=89_PEDOFILO_ASSASSINO_L=27AVVOCATO_DANIELE_MINOTTI_DI_?= =?UTF-8?Q?RAPALLO=2C_GENOVA_E_CRIMINALISSIMO_STUDIO_LISI=21_SDD?= From: ROBERTO GORINI 4-UPPER LTD LUGANO-LA-SUISSE Injection-Date: Mon, 11 Nov 2019 19:55:28 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 532 Xref: reader01.eternal-september.org comp.lang.vhdl:9607 E' DA ARRESTARE SUBITO L'AVV DANIELE MINOTTI! E' DAVVERO DA ARRESTARE IMMED= IATAMENTE IL VOMITEVOLE AVVOCATO PEDERASTA ED ASSASSINO DANIELE MINOTTI DI = GENOVA! IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIELE MINOTTI!!!!!! LE= GALE MALAVITOSISSIMO, STUPRANTE INFANTI ED ADOLESCENTI, COME PURE OMICIDA: = DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E MILANO E DI= CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDI LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI = MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PIU' D= I SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! E= ' STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA ED UCCIDE = I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO CHIAMATO DANIELE MINOTTI! QUESTO = AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI= GENOVA E RAPALLO. https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://grokbase.com/t/python/python-list/148jckyh1w/avvocato-pedofilomoses= suale-ed-assassino-daniele-minotti-facebook-oltre-che-nazi-megalava-euro-ma= fiosi-e-come-detto-mandante-di-omicidi-o-suicidate-stalker-di-eroe-civile-m= ichele-nista-su-ordine-di-tiranno-fasciocamorrista-silvio-berlusconi 1 FINO A POCO FA..SGOZZAVA OLTRE CHE CANI, GATTI E SERPENTI, TANTISSIMI BAMBI= NI, IN RITI SATANICI DI TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEG= UONO.. I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMA= ZZATI, FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRI= O DALL'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI http://criminologiasicurezza.blogspot.com/2008/05/satanica-granda-i-luoghi-= del-demonio-in.html http://www.targatocn.it/2013/05/27/leggi-notizia/argomenti/cronaca-1/artico= lo/satanismo-dietro-a-5-suicidi-di-studenti-saluzzo-potrebbe-scoprirsi-quel= la-che-non-sapeva-desser.html https://www.lastampa.it/vatican-insider/it/2018/04/15/news/sette-sataniche-= boom-di-violenze-rituali-1.34005609 https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ https://www.lastampa.it/2018/04/15/vaticaninsider/sette-sataniche-boom-di-v= iolenze-rituali-Icc9Fn11C3H8hZ2MoKY22M/pagina.html ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO ASSASS= INO, NAZISTA, RAZZISTA, LADRO, TRUFFATORE E PEDOFILO STUPRANTE ED UCCIDENTE= BAMBINI SU BAMBINI: DANIELE MINOTTI DI GENOVA E RAPALLO! Criminalissimo Studio Cirenei Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Fax +39 010 91 63 11 54 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg ). A CAPO, ANZI, A KAPO' DI SETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA = ASSASSINA CHIAMATA " AMMAZZIAMO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCO= NI". E' AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GE= NOVA E RAPALLO. VEDI QUESTO LINK https://www.py.cz/pipermail/python/2017-April/013002.html UNITO IN CIO' AL PARIMENTI AVVOCATO MASSONE, NAZISTA, LADRO, TRUFFATORE, RI= CICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPPOLITO= . ED AI PARIMENTI SATANAZISTI, CORROTTI, MEGA COCAINOMANI E NOTISSIMI PEDOF= ILI MARIO GIORDANO, CLAUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSE= LMA DEL'OLIO ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTA= TO REGISTA PEDERASTA INCULA BAMBINI GIUSEPPE LAZZARI DI BRESCIA http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 ( CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, E' PAPPA = E CICCIA CON LA PURE MOLTISSIMO PEDOFILA ANSELMA DELL'OLIO STESSA https://www.imdb.com/title/tt1828287/reviews http://www.sentirsidire.it/su-di-me/ VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO A QUESTO LINK https://www.youtube.com/watch?v=3DDLR-DJJWl_M RIPORTANTE UNA TRASMISSIONE DEL NOIOSISSIMO GIGI MARZULLO, CON LA TROIONA S= TUPRA BAMBINI ANSELMA DELL'OLIO ED IL REGISTA PEDERASTA INCULA BAMBINI GIUS= EPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLETTUALMENTE, DIFENDENDO E PR= UOMOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULLLALA' CHE CASO, LA SCHIFOSA= MENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORCO NAZISTA, FIGLIO DI CANE, DA S= EMPRE SUPER PEDERASTA GIULIANO FERRARA, INSIEME AL REGISTA PEDOFILO STUPRA = BAMBINI GIUSEPPE LAZZARI, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN FATTO LEVA= RE... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI CIO' CHE VINCENT= ISSIMAMENTE STIAM QUI SCRIVENDO). IL TUTTO INSIEME ANCHE AL TRE VOLTE FINIT= O IN GALERA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, DI CRIMIN= ALISSIMA BITINCUBATOR & VENTURE, DI CRIMINALISSIMA CRYPTOPOLYS, CRIMINALISS= IMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "MERDATO"= LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFI= LO DEL BITCOIN" https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg https://twitter.com/megliomortiche1 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ). 2 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). =E3=80=80 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 4 E POI ANCORA.. http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! =E3=80=80 5 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ =E3=80=80 =E3=80=80 6 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html https://twitter.com/LavaPaolo ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg 7 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/company D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ =E3=80=80 8 AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://www.instagram.com/p/Bcc0zWonbtv/ E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO https://www.spreaker.com/user/10297125 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". 9 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIP= O QUESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/ https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!! 10 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! https://www.py.cz/pipermail/python/2018-February/013212.html 11 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o) Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. KS From newsfish@newsfish Thu Aug 1 00:45:06 2024 X-Received: by 2002:a0c:fa05:: with SMTP id q5mr30814396qvn.182.1573589184759; Tue, 12 Nov 2019 12:06:24 -0800 (PST) X-Received: by 2002:a81:574a:: with SMTP id l71mr20911818ywb.30.1573589184478; Tue, 12 Nov 2019 12:06:24 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!j16no3369793qtl.0!news-out.google.com!g53ni126qtg.0!nntp.google.com!j16no3369780qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Nov 2019 12:06:24 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=84.198.244.197; posting-account=IG2V5QoAAADWNB-jCtBjZSg45IY7zzEI NNTP-Posting-Host: 84.198.244.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: =?UTF-8?Q?=C3=89_SATANISTA_BASTARDAMENTE_ASSASSINA=3A_ELISA_COGNO_DI?= =?UTF-8?Q?_MASSONICA_E_NAZIFASCISTA_FONDAZIONE_FERRERO=2C_COME_DI_CRIMIN?= =?UTF-8?Q?ALISSIMA_FRUIMEX_SAS_DI_ALBA=21__HHH?= From: ANTONIO BINNI - BASTA COL PEDOFILO BERLUSCONI Injection-Date: Tue, 12 Nov 2019 20:06:24 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9608 =C3=89 SATANISTA BASTARDAMENTE ASSASSINA: ELISA COGNO DI MASSONICA E NAZIFA= SCISTA FONDAZIONE FERRERO (NOTA PURE PER SUO AMORE PER OMICIDA, RAZZISTISSI= MO KU KLUK KLAN https://www.ilfattoquotidiano.it/2019/01/16/ovetti-kinder-a= ccusati-di-razzismo-la-sorpresa-ha-il-simbolo-del-ku-klux-klan-e-il-ciuffo-= di-donald-trump-manda-messaggi-subliminali/4901191/ ). OLTRE CHE DI CRIMINA= LISSIMA, MEGA RICICLA SOLDI MAFIOSI, FRUIMEX SAS DI ALBA E TORINO! https://www.instagram.com/p/Bcc0zWonbtv/ http://compgroups.net/comp.soft-sys.matlab/sempre-sborrata-nel-culo-elisa-c= ogno-di/2128471 https://www.impresaitalia.info/mstdb80753147/fruimex-di-cogno-elisa-e-c-sas= /alba.aspx CHE POTETE SENTIRE, RAGLIARE DA SUO FASCISTA E FILO NDRANGHETISTA SOLITO, Q= UI https://www.radioradicale.it/scheda/293882/imprese-e-politica DIFFAMA SUL WEB, SU BASE DI BALLE FILO HITLERIANE, A FINI ASSASSINI! SEMPRE= A FARE ORGE AD HARCORE-ARCORE DA STRAGISTA SPAPPOLA MAGISTRATI E NOTO PEDO= FILO SILVIO BERLUSCONI! MANDANTE ED ESECUTRICE DI OMICIDI DI CARATTERE SATA= NISTA! RICICLA SOLDI MAFIOSI! =C3=89 SEMPRE SCOPATA E SBORRATA NEL CULO LA TROIA NAZISTA E RAZZISTA ELISA= COGNO (CRIMINALISSIME FONDAZIONE FERRERO E FRUIMEX SAS DI ALBA E TORINO.. = NOTA ANCHE COME, SEMPRE CRIMINALISSIMA "FRUIMEX.BLOGSPOT.COM")! DA MALAVITO= SA PUTTANONA BERLUSCONAZISTA E PADANAZISTA QUALE E', LAVA TANTO CASH DI COS= A NOSTRA, CAMORRA E NDRANGHETA, COME PURE CASH RUBATO O FRUTTO DI MEGA MAZZ= ETTE DI LL, LEGA LADRONA, ED EX PDL, POPOLO DI LADRONI ( ORA FORZA ITALIA M= AFIOSA). IL TUTTO INSIEME A SUA MADRE, NOTA BAGASCIA SEMPRE PIENA DI SIFILI= DE, DELINQUENTISSIMA PUTTANA PIERA CLERICO https://groups.google.com/forum/#!msg/it.hobby.hi-fi/jym1LwlQhY0/WFxhdI1dxr= 4J (ANCHE LEI MEGA RICICLANTE SOLDI ASSASSINI, PRESSO MALAVITOSISSIMA FRUIMEX = FRU.IM.EX SAS VIA NICOLA FABRIZI 44 10145 TORINO E LOCALITA' SAN CASSIANO 1= 5 - 12051 - ALBA - CN). IL TUTTO IN INFIMA HITLERIANA CONGIUNZIONE CON PROP= RIO, FILO MAFIOSO FRATELLO PAOLO COGNO NOTO PEDERASTA NAZISTA, SUPER LAVA EURO KILLER, VICINISSIMO A FAMOSO " NDRA= NGHETISTA PADANO" DOMENICO BELFIORE DI TORINO E GIOIOSA JONICA. COME DETTO,= STI VERMI SON TUTTI SATANISTI, ANZI, SATA-N-AZISTI, CHE HAN INDOTTO AL SUI= CIDIO TANTISSIME PERSONE ( E SPESSO HANNO "SUICIDATO", OSSIA HANNO AMMAZZAT= O & THAT'S IT). FRA CUI 5 RAGAZZI QUI http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.altriconfini.it/2013/06/lombra-delle-sette-sataniche-nei-suicid= i-in-provincia-di-cuneo/ https://www.notizieprovita.it/notizie-dallitalia/satanismo-in-fiera-da-vita= -a-proteste-indignate/ E CHE PARTECIPAVANO AD ORGE DEMONIACHE, QUI http://www.direttanews.it/2017/03/15/meraglia-orge-sataniche-torino/ CON SATA-N-AZISTE PIERA CLERICO ED ELISA COGNO, ZOCCOLONE MADRE E FIGLIA, C= HE PARTECIPAVANO ALLA STESSA ORGIA E LESBICAVANO ALLA STESSA ORGIA. MADRE E= FIGLIA, CHE SCHIFO ( D'ALTRONDE, FURONO CENTINAIA E CENTINAIA LE VOLTE CHE= LE MEGA MGNOTTE ELISA COGNO E PIERA CLERICO DELLA CRIMINALISSIMA FRUIMEX D= I ALBA E TORINO, PARTECIPARONO AD ORGE AD HARCORE-ARCORE, DAI PEDOFILI, STR= AGISTI SPAPPOLA MAGISTRATI, SEMPRE SODOMIZZATI PAOLO E SILVIO BERLUSCONI http://www.secoloditalia.it/2015/07/glielo-misi-in-quel-posto-triste-scoop-= travaglio-stile-youporn-berlusconi-sodomizzato/ http://www.vnews24.it/2015/07/03/ruby-orgia-berlusconi/ ) LA CRIMINALISSIMA FAMIGLIA COGNO PUO' INTERAMENTE FINIRE IN GALERA DA UN MO= MENTO ALL'ALTRO, HANNO PM DI SEI PROCURE PIEMONTESI ADDOSSO. SPERIAMO CHE C= I FINISCANO IN CARCERE E SUBITO O FARANNO UCCIDERE DECINE E DECINE DI ALTRE= PERSONE. DI QUESTO GRUPPO MAFIOSAMENTE E "SATA-N-AZISTAMENTE" ASSASSINO, F= ANNO OVVIAMENTE PARTE, PURE, IL GIA' PLURI CONDANNATO AL CARCERE, ACCLARATO= PEDOFILO E FREQUENTISSIMO MANDANTE DI OMICIDI, PAOLO BARRAI DI FALLIMENTAR= E BLOG MERCATO "MERDATO" LIBERO! IL GIA' 3 VOLTE IN CARCERE PAOLO PIETRO BARRAI NATO A MILANO IL 28.6.1965 https://twitter.com/megliomortiche1 https://www.py.cz/pipermail/python/2018-July/013298.html (^PEDOFILO DEL BITCOIN^.. COME LO CHIAMANO IN TUTTO IL MONDO). INDAGATO, AL= MOMENTO, DALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SC= OTLAND YARD LONDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit NOTO LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANTE I R= ISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA INTERNE= T, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! OLTRE = AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A SEGUI= TO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA FINAL= E DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio/repu= bblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai CRIMINALE EFFERATISSIMO PAOLO BARRAI DI MEGA RICICLA SOLDI MAFIOSI, CRIMINA= LISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIMA CRYPTOPOLIS,= CRIMIONALISSIMA BLOCKCHAIN INVEST! COME DI CRIMINALISSIMA WMO SA PANAMA, = CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISSIMA WORLD MAN OPPORTUNITIES LU= GANO E CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO. OLTRE CHE, = COME CITATO, DI MEGA TRUFFATORE BLOG MERCATO LIBERO, NOTO IN TUTTO IL MONDO= , COME "MERDATO" LIBERO. INSIEME AD UN ALTRETTANTO PEDOFILO KILLER, SEMPRE = A BANGKOK A STUPRARE ED UCCIDERE BAMBINI, COME A LAVARE CASH SUPER MAFIOSO = DI ROBERTO PALAZZOLO, VERME BASTARDAMENTE ASSASSINO MAURIZIO BARBERO DI TEC= HNO SKY MONTE SETTEPANI https://pbs.twimg.com/profile_images/698221802565279744/7hEZuIO_.jpg https://groups.google.com/forum/#!topic/free.it.citta.genova/fy8Cv0GmJh4 E MERCATO LIBERO NEWS ALIAS "MERDATO" LIBERO NEWS ( ALTRO ASSASSINO SATA-NA= Z-ISTA DI ALBA). DEL GRUPPO OMICIDA FA STRA PARTE, PURE, IL NOTO PEDERASTA = CHE INVOCA LA PEDOFILIA LIBERA, L'INCULA BAMBINI, LO STUPRA BAMBINI STEFANO= BASSI DI TORINO E DE IL GRANDE BLUFF. https://i.ytimg.com/vi/V6Hl3-I-Jb0/hqdefault.jpg?sqp=3D- https://groups.google.com/forum/#!topic/alt.sys.pc-clone.dell/O9u75KVnVcI ED IL COLLETTO LERCIO, MEGA RICICLA SOLDI CRIMINALISSIMI A ROMA (GIRI SCHIF= OSISSIMI DI MAFIA CAPITALE E DELLA EX BANDA DELLA MAGLIANA), NONCHE' SEMPRE= CANNANTE IN BORSA, MEGA AZZERA RISPARMI FEDERICO IZZI, NOTO COME " ER ZIO = ROMOLO CHE VIA CRIMINALISSIMO BITCOIN TE FA' PERDE TUTTO QUELLO CHE HAI E T= E LASCIA EN MUTANDE" ( SE VI E' UN PO' DI IRONIA, ANZI, PICCOLA SDRAMMATIZZ= AZIONE, IN QUESTA PARTE FINALE DEL TESTO, VI ASSICURO CHE IL RESTO E' TUTTO= VERISSIMO E SERISSIMO)! https://cryptonomist.ch/wp-content/uploads/2018/03/08-1.jpg https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/FKY_roBbVQ4 KD From newsfish@newsfish Thu Aug 1 00:45:06 2024 X-Received: by 2002:ac8:754c:: with SMTP id b12mr15640642qtr.291.1573846720962; Fri, 15 Nov 2019 11:38:40 -0800 (PST) X-Received: by 2002:a81:2949:: with SMTP id p70mr10453021ywp.485.1573846720642; Fri, 15 Nov 2019 11:38:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!j16no2613660qtl.0!news-out.google.com!p4ni749qtu.1!nntp.google.com!j16no2613650qtl.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 Nov 2019 11:38:40 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.118.48.1; posting-account=94lwogoAAAAGJtgcYF_SJa1Z5dKgUmXd NNTP-Posting-Host: 188.118.48.1 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6bae7f02-6468-42bc-afd7-db3d9150cf72@googlegroups.com> Subject: =?UTF-8?Q?=C3=89_SATANISTA_ASSASSINA=3A_ELISA_COGNO_DI_MASSONICA_E_N?= =?UTF-8?Q?AZIFASCISTA_FONDAZIONE_FERRERO_=28NOTA_PURE_PER_SUO_AMORE_PER_?= =?UTF-8?Q?OMICIDA=2C_RAZZISTISSIMO_KU_KLUK_KLAN_https=3A=2F=2Fwww=2Eilfattoquoti?= =?UTF-8?Q?diano=2Eit=2F2019=2F01=2F16=2Fovetti=2Dkinder=2Daccusati=2Ddi=2Drazzismo=2Dla=2Dso?= =?UTF-8?Q?rpresa=2Dha=2Dil=2Dsimbol?= From: "VAMOS, VAMOS, VAMOS A GANAR!" Injection-Date: Fri, 15 Nov 2019 19:38:40 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9609 =C3=89 SATANISTA ASSASSINA: ELISA COGNO DI MASSONICA E NAZIFASCISTA FONDAZI= ONE FERRERO (NOTA PURE PER SUO AMORE PER OMICIDA, RAZZISTISSIMO KU KLUK KLA= N https://www.ilfattoquotidiano.it/2019/01/16/ovetti-kinder-accusati-di-raz= zismo-la-sorpresa-ha-il-simbolo-del-ku-klux-klan-e-il-ciuffo-di-donald-trum= p-manda-messaggi-subliminali/4901191/ ). OLTRE CHE DI CRIMINALISSIMA, MEGA = RICICLA SOLDI MAFIOSI, FRUIMEX SAS DI ALBA E TORINO ED ANCOR PIU' DI SOCIET= A' CHE SERVE A COPRIRE TRAFFICO DI DROGA, MALAVITOSISSIMA EDIL.CO.PEC. S.A.= S. DI COGNO ELISA E PAOLO DI VIA PAOLO DELLA VALLE 87 12060 BOSSOLASCO CN. https://www.instagram.com/p/Bcc0zWonbtv/ http://compgroups.net/comp.soft-sys.matlab/sempre-sborrata-nel-culo-elisa-c= ogno-di/2128471 https://www.impresaitalia.info/mstdb80753147/fruimex-di-cogno-elisa-e-c-sas= /alba.aspx CHE POTETE SENTIRE, RAGLIARE DA SUO FASCISTA E FILO NDRANGHETISTA SOLITO, Q= UI https://www.radioradicale.it/scheda/293882/imprese-e-politica DIFFAMA SUL WEB, SU BASE DI BALLE FILO HITLERIANE, A FINI ASSASSINI! SEMPRE= A FARE ORGE AD HARCORE-ARCORE DA STRAGISTA SPAPPOLA MAGISTRATI E NOTO PEDO= FILO SILVIO BERLUSCONI! MANDANTE ED ESECUTRICE DI OMICIDI DI CARATTERE SATA= NISTA! RICICLA SOLDI MAFIOSI! =C3=89 SEMPRE SCOPATA E SBORRATA NEL CULO LA TROIA NAZISTA E RAZZISTA ELISA= COGNO (CRIMINALISSIME FONDAZIONE FERRERO E FRUIMEX SAS DI ALBA E TORINO.. = NOTA ANCHE COME, SEMPRE CRIMINALISSIMA "FRUIMEX.BLOGSPOT.COM")! DA MALAVITO= SA PUTTANONA BERLUSCONAZISTA E PADANAZISTA QUALE E', LAVA TANTO CASH DI COS= A NOSTRA, CAMORRA E NDRANGHETA, COME PURE CASH RUBATO O FRUTTO DI MEGA MAZZ= ETTE DI LL, LEGA LADRONA, ED EX PDL, POPOLO DI LADRONI ( ORA FORZA ITALIA M= AFIOSA). IL TUTTO INSIEME A SUA MADRE, NOTA BAGASCIA SEMPRE PIENA DI SIFILI= DE, DELINQUENTISSIMA PUTTANA PIERA CLERICO https://groups.google.com/forum/#!msg/it.hobby.hi-fi/jym1LwlQhY0/WFxhdI1dxr= 4J (ANCHE LEI MEGA RICICLANTE SOLDI ASSASSINI, PRESSO MALAVITOSISSIMA FRUIMEX = FRU.IM.EX SAS VIA NICOLA FABRIZI 44 10145 TORINO E LOCALITA' SAN CASSIANO 1= 5 - 12051 - ALBA - CN). IL TUTTO IN INFIMA HITLERIANA CONGIUNZIONE CON PROP= RIO, FILO MAFIOSO FRATELLO PAOLO COGNO NOTO PEDERASTA NAZISTA, SUPER LAVA EURO KILLER, VICINISSIMO A FAMOSO " NDRA= NGHETISTA PADANO" DOMENICO BELFIORE DI TORINO E GIOIOSA JONICA. COME DETTO,= STI VERMI SON TUTTI SATANISTI, ANZI, SATA-N-AZISTI, CHE HAN INDOTTO AL SUI= CIDIO TANTISSIME PERSONE ( E SPESSO HANNO "SUICIDATO", OSSIA HANNO AMMAZZAT= O & THAT'S IT). FRA CUI 5 RAGAZZI QUI http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.altriconfini.it/2013/06/lombra-delle-sette-sataniche-nei-suicid= i-in-provincia-di-cuneo/ https://www.notizieprovita.it/notizie-dallitalia/satanismo-in-fiera-da-vita= -a-proteste-indignate/ E CHE PARTECIPAVANO AD ORGE DEMONIACHE, QUI http://www.direttanews.it/2017/03/15/meraglia-orge-sataniche-torino/ CON SATA-N-AZISTE PIERA CLERICO ED ELISA COGNO, ZOCCOLONE MADRE E FIGLIA, C= HE PARTECIPAVANO ALLA STESSA ORGIA E LESBICAVANO ALLA STESSA ORGIA. MADRE E= FIGLIA, CHE SCHIFO ( D'ALTRONDE, FURONO CENTINAIA E CENTINAIA LE VOLTE CHE= LE MEGA MGNOTTE ELISA COGNO E PIERA CLERICO DELLA CRIMINALISSIMA FRUIMEX D= I ALBA E TORINO, PARTECIPARONO AD ORGE AD HARCORE-ARCORE, DAI PEDOFILI, STR= AGISTI SPAPPOLA MAGISTRATI, SEMPRE SODOMIZZATI PAOLO E SILVIO BERLUSCONI http://www.secoloditalia.it/2015/07/glielo-misi-in-quel-posto-triste-scoop-= travaglio-stile-youporn-berlusconi-sodomizzato/ http://www.vnews24.it/2015/07/03/ruby-orgia-berlusconi/ ) LA CRIMINALISSIMA FAMIGLIA COGNO PUO' INTERAMENTE FINIRE IN GALERA DA UN MO= MENTO ALL'ALTRO, HANNO PM DI SEI PROCURE PIEMONTESI ADDOSSO. SPERIAMO CHE C= I FINISCANO IN CARCERE E SUBITO O FARANNO UCCIDERE DECINE E DECINE DI ALTRE= PERSONE. DI QUESTO GRUPPO MAFIOSAMENTE E "SATA-N-AZISTAMENTE" ASSASSINO, F= ANNO OVVIAMENTE PARTE, PURE, IL GIA' PLURI CONDANNATO AL CARCERE, ACCLARATO= PEDOFILO E FREQUENTISSIMO MANDANTE DI OMICIDI, PAOLO BARRAI DI FALLIMENTAR= E BLOG MERCATO "MERDATO" LIBERO! IL GIA' 3 VOLTE IN CARCERE PAOLO PIETRO BARRAI NATO A MILANO IL 28.6.1965 https://twitter.com/megliomortiche1 https://www.py.cz/pipermail/python/2018-July/013298.html (^PEDOFILO DEL BITCOIN^.. COME LO CHIAMANO IN TUTTO IL MONDO). INDAGATO, AL= MOMENTO, DALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SC= OTLAND YARD LONDRA E DA FBI NEW YORK. IL TUTTO VIA EUROPOL ED INTERPOL. NE TROVATE VINCENTISSIMAMENTE QUI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit NOTO LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANTE I R= ISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA INTERNE= T, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! OLTRE = AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A SEGUI= TO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA FINAL= E DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio/repu= bblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai CRIMINALE EFFERATISSIMO PAOLO BARRAI DI MEGA RICICLA SOLDI MAFIOSI, CRIMINA= LISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIMA CRYPTOPOLIS,= CRIMIONALISSIMA BLOCKCHAIN INVEST! COME DI CRIMINALISSIMA WMO SA PANAMA, = CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISSIMA WORLD MAN OPPORTUNITIES LU= GANO E CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO. OLTRE CHE, = COME CITATO, DI MEGA TRUFFATORE BLOG MERCATO LIBERO, NOTO IN TUTTO IL MONDO= , COME "MERDATO" LIBERO. INSIEME AD UN ALTRETTANTO PEDOFILO KILLER, SEMPRE = A BANGKOK A STUPRARE ED UCCIDERE BAMBINI, COME A LAVARE CASH SUPER MAFIOSO = DI ROBERTO PALAZZOLO, VERME BASTARDAMENTE ASSASSINO MAURIZIO BARBERO DI TEC= HNO SKY MONTE SETTEPANI https://pbs.twimg.com/profile_images/698221802565279744/7hEZuIO_.jpg https://groups.google.com/forum/#!topic/free.it.citta.genova/fy8Cv0GmJh4 E MERCATO LIBERO NEWS ALIAS "MERDATO" LIBERO NEWS ( ALTRO ASSASSINO SATA-NA= Z-ISTA DI ALBA). DEL GRUPPO OMICIDA FA STRA PARTE, PURE, IL NOTO PEDERASTA = CHE INVOCA LA PEDOFILIA LIBERA, L'INCULA BAMBINI, LO STUPRA BAMBINI STEFANO= BASSI DI TORINO E DE IL GRANDE BLUFF. https://i.ytimg.com/vi/V6Hl3-I-Jb0/hqdefault.jpg?sqp=3D- https://groups.google.com/forum/#!topic/alt.sys.pc-clone.dell/O9u75KVnVcI ED IL COLLETTO LERCIO, MEGA RICICLA SOLDI CRIMINALISSIMI A ROMA (GIRI SCHIF= OSISSIMI DI MAFIA CAPITALE E DELLA EX BANDA DELLA MAGLIANA), NONCHE' SEMPRE= CANNANTE IN BORSA, MEGA AZZERA RISPARMI FEDERICO IZZI, NOTO COME " ER ZIO = ROMOLO CHE VIA CRIMINALISSIMO BITCOIN TE FA' PERDE TUTTO QUELLO CHE HAI E T= E LASCIA EN MUTANDE" ( SE VI E' UN PO' DI IRONIA, ANZI, PICCOLA SDRAMMATIZZ= AZIONE, IN QUESTA PARTE FINALE DEL TESTO, VI ASSICURO CHE IL RESTO E' TUTTO= VERISSIMO E SERISSIMO)! https://cryptonomist.ch/wp-content/uploads/2018/03/08-1.jpg https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/FKY_roBbVQ4 From newsfish@newsfish Thu Aug 1 00:45:07 2024 X-Received: by 2002:a0c:f241:: with SMTP id z1mr7610851qvl.53.1574893651197; Wed, 27 Nov 2019 14:27:31 -0800 (PST) X-Received: by 2002:a81:d543:: with SMTP id l3mr4734241ywj.394.1574893650956; Wed, 27 Nov 2019 14:27:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!185.151.15.255.MISMATCH!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!g89no5479423qtd.0!news-out.google.com!g53ni1515qtg.0!nntp.google.com!g89no5479413qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Nov 2019 14:27:30 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=31.31.151.104; posting-account=IG2V5QoAAADWNB-jCtBjZSg45IY7zzEI NNTP-Posting-Host: 31.31.151.104 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3a493393-0721-4d94-9397-bdb3517b0c03@googlegroups.com> Subject: RICICLA TANTI SOLDI MAFIOSI: ANGELO LIETTI DI BANCA MEDIOLANUM, NDRANGOLANUM, MAFIOLANUM, HITLERANUM https://www.bancamediolanum.it/corporate-governance/governance/angelo-lietti IL PORCO NAZISTA, RAZZISTA, CRIMINALISSIMO ANGELO LIETTI DI BANCA....... From: ANTONIO BINNI - BASTA COL PEDOFILO BERLUSCONI Injection-Date: Wed, 27 Nov 2019 22:27:31 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 167 Xref: reader01.eternal-september.org comp.lang.vhdl:9610 RICICLA TANTI SOLDI MAFIOSI: ANGELO LIETTI DI BANCA MEDIOLANUM, NDRANGOLANU= M, MAFIOLANUM, HITLERANUM https://www.bancamediolanum.it/corporate-governan= ce/governance/angelo-lietti IL PORCO NAZISTA, RAZZISTA, CRIMINALISSIMO ANGELO LIETTI DI BANCA..........= ...MEDIOLANUM, NDRANGOLANUM, MAFIOLANUM, HITLERANUM=20 https://it.linkedin.com/in/angelo-lietti-09b62a6a IL TUTTO INSIEME AL PURE NOTO PEDOFILO INCULA BAMBINI GIOVANNI PIROVANO DI = DI BANCA MEDIOLANUM, NDRANGOLANUM, MAFIOLANUM, HITLERANUM=20 https://www.bancamediolanum.it/corporate-governance/governance/giovanni-pir= ovano I DUE TENEVANO I RAPPORTI CON GLI IMPRENDITORI ASSASSINI DI COSA NOSTRA: FR= ANCESCO ZUMMO ED IGNAZIO ZUMMO! AI TEMPI DELL'ARRESTO DELL'AVVOCATO PEDOFIL= O E NAZISTA PAOLO SCIUME'! https://ricerca.repubblica.it/repubblica/archivio/repubblica/2009/01/24/ric= iclaggio-arrestato-sciume-avvocato-della-finanza-milanese.html VERME SCHIFOSISSIMO ANGELO LIETTI: BANCHIERE SCHIFOSAMENTE BASTARDAMENTE CR= IMINALE, NATO A MILANO IL 2.2.1961! STATE ALLA LARGA DAL BANCHIERE DELINQUENTISSIMO E NOTORIAMENTE MOLTO PEDOFI= LO GIOVANNI PIROVANO DI BANCA MEDIOLANUM, MAFIOLANUM, NDRANGOLANUM, CAMORRA= NUM, LAVALAVAPERCOCALEROSCOLOMBIANUM, RICICLANUM, NAZISTANUM! I DUE TENEVANO I RAPPORTI CON GLI IMPRENDITORI ASSASSINI DI COSA NOSTRA: IG= NAZIO ZUMMO E FRANCESCO ZUMMO! QUESTO AI TEMPI DEL LORO ARRESTO! https://ricerca.repubblica.it/repubblica/archivio/repubblica/2006/10/31/maf= ia-condannati-costruttori-zummo.html COME AI TEMPI DELL'ARRESTO DELL'AVVOCATO NAZISTA, RAZZISTA E PURE NOTORIAME= NTE PEDOFILO: PAOLO SCIUME' DI MALAVITOSISIMA COMPAGNIA DELLE OPERE!!! CON CUI, NOTORIAMENTE, TRAFFICAVA PURE "IL PERICOLOSISSIMO" RICICLA SOLDI M= AFIOSI GIOVANNI RAIMONDI DI CRIMINALE PIA PARTECIPAZIONI ( COME PURE RICICL= A SOLDI MAFIOSI GIOVANNI RAIMONDI DI MITTEL, RICICLA SOLDI MAFIOSI GIOVANNI= RAIMONDI DI PARTECIPAZIONI INTERESSENZE AZIONARIE, RICICLA SOLDI MAFIOSI G= IOVANNI RAIMONDI DI ISTITUTO TONIOLO, RICICLA SOLDI MAFIOSI GIOVANNI RAIMON= DI DI CASTELLO SGR, RICICLA SOLDI MAFIOSI GIOVANNI RAIMONDI DI POLICINICO G= EMELLI). NOTORIAMENTE, EX DI SOCIETA' FINANZIARIE E BANCHE " TUTTE COSA NOS= TRA", QUALI GESFID LUGANO E BANCA SAI ( OVE MEGA RICICLAVA CASH MALAVITOSO= , ASSASSINO E PER I LIGRESTI... DI CIO' NE PARLAVA ANCHE L'AMMIREVOLISIMO, = PER LO MENO IN QUESTO, PENTITO GASPARE MUTOLO... TROVAVATE IL TUTTO, PIU' O= MENO, A FINE VIDEO, QUI https://www.youtube.com/watch?v=3DgmjdXBIcBt0 DA QUANDO NE ABBIAMO SCRITTO= , I RICICLA SOLDI MAFIOSI GIOVANNI RAIMONDI DEL POLICLINICO GEMELLI E PAOLO= LIGRESTI, HAN OVVIAMENTE FATTO SPARIRE IL TUTTO DA INTERNET... MA POTETE L= EGGERE A PROPOSITO DEL CITATO, QUI https://www.dagospia.com/rubrica-4/busin= ess/sull-impero-ligresto-ombra-mattanza-mafiosi-che-rapirono-59759.htm = ). "PERICOLOSISSIMO" RICICLA SOLDI MAFIOSI GIOVANNI RAIMONDI ( EX DI DELINQ= UENTISSIMA SOCIETA' "AGENTE DI CAMBIO GIOVANNI RAIMONDI"). ORA IMBOSCATOSI,= VIA SUOI PAPPONI FURBASTRI E NAZISTI DI COMUNIONE E LIBERAZIONE, PRESSO OS= PEDALE GEMELLI! http://www.progettoalternativo.com/2016/08/comunione-e-liberazione-dietro-l= a.html NOTO PER PRIMA SFRUTTARE GLI ALTRI FINO ALL'OSSO, E POI, UNA VOLTA FATTO QU= ESTO, SENZA MOTIVO ALCUNO (PUR SE SEMPRE FINGENDOSI AMICO), INIZIARE A DISC= ONOSCERLI. E PURE COMPLOTTARLI E DENIGRARLI SU BASE DI IMMENSE BALLE DETTE = A FINI "BERLUSCONAZIFASCISTI". E DI NASCOSTO. E DI DIETRO ( IL TUTTO INSIEM= E AL NOTO PEDERASTA INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO GORLI= NI DI BANCA ALBERTINI E DI BERGAMO .. COME PURE INSIEME AL NOTO PEDERASTA, = ANCHE MEGA RICICLA SOLDI MAFIOSI, GIANPAOLO GAMBA, SEMPRE DI BANCA ALBERTIN= I.... FAMOSO PER INONDARE IL LIECHTENSTEIN DI SOLDI DI COSA NOSTRA, CAMORRA= E NDRANGHETA http://ricerca.gelocal.it/messaggeroveneto/archivio/messaggeroveneto/2008/0= 3/28/NZ_06_SEE1.html SI, SI, E' PROPRIO COSI': E' UN MASSONE E ROTARIANO DI TIPO CRIMINALISSIMO = E PEDERASTA, GIANPAOLO GAMBA DI BANCA ALBERTINI, IL CUI LOOK MALAVITOSISSIM= O, IN CHE NEL LINK CHE SEGUE, POTETE VEDERE, IL TUTTO CONFERMA https://it.linkedin.com/in/gian-paolo-gamba-96931594 BANCHIERE TUTT'UNO CON CRIMINALISSIMI MASSONI SUOI COMPARI, PURE SUPER NARC= O TRAFFICANTI, COME IL MEGA PREGIUDICATO PASQUALE CLAUDIO LOCATELLI DI BERG= AMO https://www.repubblica.it/cronaca/2015/08/11/news/da_bergamo_al_messico_l_i= mpero_del_signore_della_coca-120775546/ DI BERGAMO COME IL PRIMA CITATO, MEGA RICICLA SOLDI MAFIOSI, PAOLO GORLINI = DI BANCA ALBERTINI .. CASPITERINA CHE COINCIDENZA, CASPITERINA). IN OGNI CASO, COME RIPORTATO AD INIZIO POST, IL LEIT MOTIV CHE MI FA SCRIVE= RE ORA E' IL NOTO PEDOFILO INCULA BAMBINI GIOVANNI PIROVANO DI CRIMINALISSI= MA BANCA MEDIOLANUM E PURE DI ABI https://www.bloomberg.com/research/stocks/people/person.asp?personId=3D1266= 4112&privcapId=3D32562212 COME LO E' ANCHE L'IMMENSO LAVA CAH MAFIOSO ANGELO LIETTI DI CRIMINALISSIMA= MEDIOLANUM! BANCHIERE DELINQUENTISSIMO, NATO A MILANO IL 2.2.1961! http://the8club-pasar-komoditi.blogspot.com/2017/07/figlio-di-puttana-angel= o-lietti-di.html COME ANCOR PIU', CRIMINALISSIMI SONO I BANCHIERI MEGA RICICLA SOLDI MAFIOSI= ENNIO DORIS DI MEDIOLANUM-MAFIOLANUM, MASSIMO DORIS DI MEDIOLANUM-MAFIOLAN= UM, OSCAR DI MONTIGNY DI MEDIOLANUM-MAFIOLANUM. ED "IL NOTO PRENDI CAZZI IN= CULO" LUIGI BERLUSCONI (CON PADRE L'ACCERTATISSIMO PEDOFILO SPAPPOLA MAGIS= TRATI SILVIO BERLUSCONI... https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ ) INFATTI, SI, SI, E' PROPRIO COSI', E' SEMPRE CON MEGA CAZZI IN CULO, IL CRI= MINALE "ALL'ALTEZZA DEL PADRE" LUIGI BERLUSCONI! https://fcku.it/comp.soft-sys.stat.spss/thread/4208801 IL DELINQUENTE MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI, PURE SU INSTAGR= AM, CHE TRA L'ALTRO HA PER FIDANZATA, SOLO ED ESCLUSIVAMENTE UN NOTO MASSON= E DI COSA NOSTRA CON LA BARBA https://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi IL CULATONE TARGATO "COSA NOSTRA, CAMORRA E NDRANGHETA" LUIGI BERLUSCONI, N= ON HA DI CERTO, PER FIDANZATA, LA NOTA ZOCCOLA SCOPATA DA TUTTI IN MILLE CL= UB PRIVE': FEDERICA FUMAGALLI. E' INFATTI SEMPRE CON CAZZI IN CULO DI 30 CM= , LUIGI BERLUSCONI, ANCHE LUI GIA' DI MEDIOLANUM-MAFIOLANUM. https://www.firstonline.info/banca-mediolanum-utili-25-luigi-berlusconi-con= sigliere/ DI STI GIRI CRIMINALISSIMI VI E' POI IL NOTO RAZZISTA, KU KLUK KLANISTA, MA= FIOSO, MEGA RICICLA CASH MAFIOSO, LADRO, TRUFFATORE, SEMPRE FALSO, ESTORTOR= E DI SOLDI, MEGA STALKER VIA INTERNET, GIA' 3 VOLTE IN CARCERE, CACCIATO A = SBERLE DA CITIBANK, INDAGATO DA 7 PROCURE ITALIANE E DA PROCURA DI LUGANO, = MEGA MULTATO DA CONSOB, ALTRETTANTO NOTO PEDERASTA PAOLO BARRAI ( O ALTRETT= ANTO NOTO PEDERASTA PAOLO PIETRO BARRAI). NATO A MILANO IL 28.6.1965 (PEDER= ASTA PAOLO BARRAI: FAMOSO IN TUTTO IL MONDO, NON PER NIENTE, COME "IL PEDOF= ILO DEL BITCOIN", USANTE UNA CRIMINALISSIMO ICO, OSSIA IPO DI CRIPTOVALUTA,= CHIAMATA EIDOO, PER ORGANIZZARE MEGA RICICLAGGI DI NDRANGHETA ASSASSINA, M= EGA TRAFFICI DI COCAINA E PEDOPORNOGRAFIA A LIVELLO MONDIALE https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/tutti-i-servizi/Bella-ge= nte-10474214.html ). VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, VERM= E MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BITINCUBATOR & VENTURE, VERME M= ALAVITOSO PAOLO BARRAI DI CRIMINALISSIM BLOG "MERDATO" LIBERO, VERME MALAVI= TOSO PAOLO BARRAI DI CRIMINALISSIMA CRYPTOLAB S A, VERME MALAVITOSO PAOLO B= ARRAI DI CRIMINALISSIMA CRYPTOPOLIS, VERME MALAVITOSO PAOLO BARRAI DI CRIMI= NALISSIMA MEDICALCHAIN, VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BIT= INCUBATOR GRONO ( IN COMUNE CON NOTO DELINQUENTISSIMO PORCO CLAUDIO LEVRINI= DI BITCOIN FOUNDATION), VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA WM= O SAGL LUGANO, VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA WMO SA PANAM= A, VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA WORLD MAN OPPORTUNITIES = LUGANO (WORLD MAN OPPORTUNITIES FOR MAFIA MONEY LAUNDERING, OBVIOUSLY SPEAK= ING), VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BLOCKCHAIN INVEST, VE= RME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BIGBIT, VERME MALAVITOSO PAOL= O BARRAI DI CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 16 MILANO (FORMALM= ENTE DI SUO PADRE, NOTO MEGA RICICLA SOLDI DI CAMORRA, COSA NOSTRA E NDRANG= HETA, NONCHE' ANCHE LUI FAMOSISSIMO PEDOFILO VINCENZO BARRAI NATO A MILANO = IL 3.5.1938 ED ABITANTE IN VIA PADOVA 282 A MILANO: SANGUE MARCIO MAI MENTE= )!!! FRA L'ALTRO, I SCHIFOSISSIMI CRIMINALI GIACOMO ZUCCO DI BLOCKCAINLABIT E BL= OCKCHAIN LAB E PAOLO BARRAI DI TUTTO IL MERDAIO MALAVITOSO PRIMA CITATO, UN= ITI AGLI ALTRETTANTO VERMI CRIMINALISSIMI GIOVANNI PIROVANO, ENNIO DORIS, M= ASSIMO DORIS E OSCAR DI MONTIGNY DI "MAFIOLANUM-MEDIOLANUM", IN CANTON TICI= NO, ERAN DIETRO QUESTI MEGA RICICLAGGI DI CASH ASSASSINO, DELLA NDRANGHETA,= EFFETTUATI INSIEME ALL'ANIMALE DELINQUENTISSIMO OLIVER CAMPONOVO: UN FIDUC= IARIO ASSASSINO, AMATO ALLA FOLLIA, BEN APPUNTO, DA NDRANGHETA, MA ANCHE DA= COSA NOSTRA E CAMORRA! https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ http://www.area7.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della-ndra= ngheta-29f7ee00 https://www.laregione.ch/cantone/mendrisiotto/1228182/affari-della--ndrangh= eta-in-ticino--alla-sbarra-l-uomo-di-fiducia-della-cosca--l-ex-municipale-d= i-chiasso-e-la-moglie-del-fratello-del-boss https://www.swissinfo.ch/ita/tpf--processo--ndrangheta--chieste-pene-di-rec= lusione/43734126 https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ https://www.rsi.ch/la1/programmi/informazione/falo/tutti-i-servizi/Bella-ge= nte-10474214.html From newsfish@newsfish Thu Aug 1 00:45:07 2024 X-Received: by 2002:a37:6794:: with SMTP id b142mr24000101qkc.216.1575142793522; Sat, 30 Nov 2019 11:39:53 -0800 (PST) X-Received: by 2002:a25:d30f:: with SMTP id e15mr44075194ybf.200.1575142793219; Sat, 30 Nov 2019 11:39:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!border2.nntp.ams1.giganews.com!nntp.giganews.com!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.am4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!g89no4492748qtd.0!news-out.google.com!o19ni615qtr.1!nntp.google.com!g89no4492736qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 30 Nov 2019 11:39:53 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.144.76.99; posting-account=aQ5fBwoAAAAOgfkQPX_fLOtY7cq0ZIxW NNTP-Posting-Host: 195.144.76.99 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: =?UTF-8?Q?RICICLA__=D0=84_MAFIOSI_A_RAFFICA=3A_ANGELO_LIETTI_DI_BANC?= =?UTF-8?Q?A_MEDIOLANUM=2C_NDRANGOLANUM=2C_MAFIOLANUM=2C_HITLERANUM_https=3A=2F=2Fw?= =?UTF-8?Q?ww=2Ebancamediolanum=2Eit=2Fcorporate=2Dgovernance=2Fgovernance=2Fangelo?= =?UTF-8?Q?=2Dlietti_IL_PORCO_NAZISTA=2C_RAZZISTA=2C_CRIMINALISSIMO_ANGELO_LI?= =?UTF-8?Q?ETTI_DI_BANCA=2E=2E=2E=2E=2E=2E?= From: FABIO VENZI-GRAN MAESTRO GLRI Injection-Date: Sat, 30 Nov 2019 19:39:53 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 12160 X-Received-Body-CRC: 2045569045 Lines: 167 Xref: reader01.eternal-september.org comp.lang.vhdl:9611 RICICLA =D0=84 MAFIOSI A RAFFICA: ANGELO LIETTI DI BANCA MEDIOLANUM, NDRAN= GOLANUM, MAFIOLANUM, HITLERANUM https://www.bancamediolanum.it/corporate-go= vernance/governance/angelo-lietti IL PORCO NAZISTA, RAZZISTA, CRIMINALISSIMO ANGELO LIETTI DI BANCA..........= .....MEDIOLANUM, NDRANGOLANUM, MAFIOLANUM, HITLERANUM https://it.linkedin.com/in/angelo-lietti-09b62a6a IL TUTTO INSIEME AL PURE NOTO PEDOFILO INCULA BAMBINI GIOVANNI PIROVANO DI = DI BANCA MEDIOLANUM, NDRANGOLANUM, MAFIOLANUM, HITLERANUM https://www.bancamediolanum.it/corporate-governance/governance/giovanni-pir= ovano I DUE TENEVANO I RAPPORTI CON GLI IMPRENDITORI ASSASSINI DI COSA NOSTRA: FR= ANCESCO ZUMMO ED IGNAZIO ZUMMO! AI TEMPI DELL'ARRESTO DELL'AVVOCATO PEDOFIL= O E NAZISTA PAOLO SCIUME'! https://ricerca.repubblica.it/repubblica/archivio/repubblica/2009/01/24/ric= iclaggio-arrestato-sciume-avvocato-della-finanza-milanese.html VERME SCHIFOSISSIMO ANGELO LIETTI: BANCHIERE SCHIFOSAMENTE BASTARDAMENTE CR= IMINALE, NATO A MILANO IL 2.2.1961! STATE ALLA LARGA DAL BANCHIERE DELINQUENTISSIMO E NOTORIAMENTE MOLTO PEDOFI= LO GIOVANNI PIROVANO DI BANCA MEDIOLANUM, MAFIOLANUM, NDRANGOLANUM, CAMORRA= NUM, LAVALAVAPERCOCALEROSCOLOMBIANUM, RICICLANUM, NAZISTANUM! I DUE TENEVANO I RAPPORTI CON GLI IMPRENDITORI ASSASSINI DI COSA NOSTRA: IG= NAZIO ZUMMO E FRANCESCO ZUMMO! QUESTO AI TEMPI DEL LORO ARRESTO! https://ricerca.repubblica.it/repubblica/archivio/repubblica/2006/10/31/maf= ia-condannati-costruttori-zummo.html COME AI TEMPI DELL'ARRESTO DELL'AVVOCATO NAZISTA, RAZZISTA E PURE NOTORIAME= NTE PEDOFILO: PAOLO SCIUME' DI MALAVITOSISIMA COMPAGNIA DELLE OPERE!!! CON CUI, NOTORIAMENTE, TRAFFICAVA PURE "IL PERICOLOSISSIMO" RICICLA SOLDI M= AFIOSI GIOVANNI RAIMONDI DI CRIMINALE PIA PARTECIPAZIONI ( COME PURE RICICL= A SOLDI MAFIOSI GIOVANNI RAIMONDI DI MITTEL, RICICLA SOLDI MAFIOSI GIOVANNI= RAIMONDI DI PARTECIPAZIONI INTERESSENZE AZIONARIE, RICICLA SOLDI MAFIOSI G= IOVANNI RAIMONDI DI ISTITUTO TONIOLO, RICICLA SOLDI MAFIOSI GIOVANNI RAIMON= DI DI CASTELLO SGR, RICICLA SOLDI MAFIOSI GIOVANNI RAIMONDI DI POLICINICO G= EMELLI). NOTORIAMENTE, EX DI SOCIETA' FINANZIARIE E BANCHE " TUTTE COSA NOS= TRA", QUALI GESFID LUGANO E BANCA SAI ( OVE MEGA RICICLAVA CASH MALAVITOSO= , ASSASSINO E PER I LIGRESTI... DI CIO' NE PARLAVA ANCHE L'AMMIREVOLISIMO, = PER LO MENO IN QUESTO, PENTITO GASPARE MUTOLO... TROVAVATE IL TUTTO, PIU' O= MENO, A FINE VIDEO, QUI https://www.youtube.com/watch?v=3DgmjdXBIcBt0 DA QUANDO NE ABBIAMO SCRITTO= , I RICICLA SOLDI MAFIOSI GIOVANNI RAIMONDI DEL POLICLINICO GEMELLI E PAOLO= LIGRESTI, HAN OVVIAMENTE FATTO SPARIRE IL TUTTO DA INTERNET... MA POTETE L= EGGERE A PROPOSITO DEL CITATO, QUI https://www.dagospia.com/rubrica-4/busin= ess/sull-impero-ligresto-ombra-mattanza-mafiosi-che-rapirono-59759.htm = ). "PERICOLOSISSIMO" RICICLA SOLDI MAFIOSI GIOVANNI RAIMONDI ( EX DI DELINQ= UENTISSIMA SOCIETA' "AGENTE DI CAMBIO GIOVANNI RAIMONDI"). ORA IMBOSCATOSI,= VIA SUOI PAPPONI FURBASTRI E NAZISTI DI COMUNIONE E LIBERAZIONE, PRESSO OS= PEDALE GEMELLI! http://www.progettoalternativo.com/2016/08/comunione-e-liberazione-dietro-l= a.html NOTO PER PRIMA SFRUTTARE GLI ALTRI FINO ALL'OSSO, E POI, UNA VOLTA FATTO QU= ESTO, SENZA MOTIVO ALCUNO (PUR SE SEMPRE FINGENDOSI AMICO), INIZIARE A DISC= ONOSCERLI. E PURE COMPLOTTARLI E DENIGRARLI SU BASE DI IMMENSE BALLE DETTE = A FINI "BERLUSCONAZIFASCISTI". E DI NASCOSTO. E DI DIETRO ( IL TUTTO INSIEM= E AL NOTO PEDERASTA INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO GORLI= NI DI BANCA ALBERTINI E DI BERGAMO .. COME PURE INSIEME AL NOTO PEDERASTA, = ANCHE MEGA RICICLA SOLDI MAFIOSI, GIANPAOLO GAMBA, SEMPRE DI BANCA ALBERTIN= I.... FAMOSO PER INONDARE IL LIECHTENSTEIN DI SOLDI DI COSA NOSTRA, CAMORRA= E NDRANGHETA http://ricerca.gelocal.it/messaggeroveneto/archivio/messaggeroveneto/2008/0= 3/28/NZ_06_SEE1.html SI, SI, E' PROPRIO COSI': E' UN MASSONE E ROTARIANO DI TIPO CRIMINALISSIMO = E PEDERASTA, GIANPAOLO GAMBA DI BANCA ALBERTINI, IL CUI LOOK MALAVITOSISSIM= O, IN CHE NEL LINK CHE SEGUE, POTETE VEDERE, IL TUTTO CONFERMA https://it.linkedin.com/in/gian-paolo-gamba-96931594 BANCHIERE TUTT'UNO CON CRIMINALISSIMI MASSONI SUOI COMPARI, PURE SUPER NARC= O TRAFFICANTI, COME IL MEGA PREGIUDICATO PASQUALE CLAUDIO LOCATELLI DI BERG= AMO https://www.repubblica.it/cronaca/2015/08/11/news/da_bergamo_al_messico_l_i= mpero_del_signore_della_coca-120775546/ DI BERGAMO COME IL PRIMA CITATO, MEGA RICICLA SOLDI MAFIOSI, PAOLO GORLINI = DI BANCA ALBERTINI .. CASPITERINA CHE COINCIDENZA, CASPITERINA). IN OGNI CASO, COME RIPORTATO AD INIZIO POST, IL LEIT MOTIV CHE MI FA SCRIVE= RE ORA E' IL NOTO PEDOFILO INCULA BAMBINI GIOVANNI PIROVANO DI CRIMINALISSI= MA BANCA MEDIOLANUM E PURE DI ABI https://www.bloomberg.com/research/stocks/people/person.asp?personId=3D1266= 4112&privcapId=3D32562212 COME LO E' ANCHE L'IMMENSO LAVA CAH MAFIOSO ANGELO LIETTI DI CRIMINALISSIMA= MEDIOLANUM! BANCHIERE DELINQUENTISSIMO, NATO A MILANO IL 2.2.1961! http://the8club-pasar-komoditi.blogspot.com/2017/07/figlio-di-puttana-angel= o-lietti-di.html COME ANCOR PIU', CRIMINALISSIMI SONO I BANCHIERI MEGA RICICLA SOLDI MAFIOSI= ENNIO DORIS DI MEDIOLANUM-MAFIOLANUM, MASSIMO DORIS DI MEDIOLANUM-MAFIOLAN= UM, OSCAR DI MONTIGNY DI MEDIOLANUM-MAFIOLANUM. ED "IL NOTO PRENDI CAZZI IN= CULO" LUIGI BERLUSCONI (CON PADRE L'ACCERTATISSIMO PEDOFILO SPAPPOLA MAGIS= TRATI SILVIO BERLUSCONI... https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ ) INFATTI, SI, SI, E' PROPRIO COSI', E' SEMPRE CON MEGA CAZZI IN CULO, IL CRI= MINALE "ALL'ALTEZZA DEL PADRE" LUIGI BERLUSCONI! https://fcku.it/comp.soft-sys.stat.spss/thread/4208801 IL DELINQUENTE MEGA RICICLA SOLDI MAFIOSI LUIGI BERLUSCONI, PURE SU INSTAGR= AM, CHE TRA L'ALTRO HA PER FIDANZATA, SOLO ED ESCLUSIVAMENTE UN NOTO MASSON= E DI COSA NOSTRA CON LA BARBA https://www.gay.it/gossip/news/bacio-gay-luigi-berlusconi IL CULATONE TARGATO "COSA NOSTRA, CAMORRA E NDRANGHETA" LUIGI BERLUSCONI, N= ON HA DI CERTO, PER FIDANZATA, LA NOTA ZOCCOLA SCOPATA DA TUTTI IN MILLE CL= UB PRIVE': FEDERICA FUMAGALLI. E' INFATTI SEMPRE CON CAZZI IN CULO DI 30 CM= , LUIGI BERLUSCONI, ANCHE LUI GIA' DI MEDIOLANUM-MAFIOLANUM. https://www.firstonline.info/banca-mediolanum-utili-25-luigi-berlusconi-con= sigliere/ DI STI GIRI CRIMINALISSIMI VI E' POI IL NOTO RAZZISTA, KU KLUK KLANISTA, MA= FIOSO, MEGA RICICLA CASH MAFIOSO, LADRO, TRUFFATORE, SEMPRE FALSO, ESTORTOR= E DI SOLDI, MEGA STALKER VIA INTERNET, GIA' 3 VOLTE IN CARCERE, CACCIATO A = SBERLE DA CITIBANK, INDAGATO DA 7 PROCURE ITALIANE E DA PROCURA DI LUGANO, = MEGA MULTATO DA CONSOB, ALTRETTANTO NOTO PEDERASTA PAOLO BARRAI ( O ALTRETT= ANTO NOTO PEDERASTA PAOLO PIETRO BARRAI). NATO A MILANO IL 28.6.1965 (PEDER= ASTA PAOLO BARRAI: FAMOSO IN TUTTO IL MONDO, NON PER NIENTE, COME "IL PEDOF= ILO DEL BITCOIN", USANTE UNA CRIMINALISSIMO ICO, OSSIA IPO DI CRIPTOVALUTA,= CHIAMATA EIDOO, PER ORGANIZZARE MEGA RICICLAGGI DI NDRANGHETA ASSASSINA, M= EGA TRAFFICI DI COCAINA E PEDOPORNOGRAFIA A LIVELLO MONDIALE https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/tutti-i-servizi/Bella-ge= nte-10474214.html ). VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, VERM= E MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BITINCUBATOR & VENTURE, VERME M= ALAVITOSO PAOLO BARRAI DI CRIMINALISSIM BLOG "MERDATO" LIBERO, VERME MALAVI= TOSO PAOLO BARRAI DI CRIMINALISSIMA CRYPTOLAB S A, VERME MALAVITOSO PAOLO B= ARRAI DI CRIMINALISSIMA CRYPTOPOLIS, VERME MALAVITOSO PAOLO BARRAI DI CRIMI= NALISSIMA MEDICALCHAIN, VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BIT= INCUBATOR GRONO ( IN COMUNE CON NOTO DELINQUENTISSIMO PORCO CLAUDIO LEVRINI= DI BITCOIN FOUNDATION), VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA WM= O SAGL LUGANO, VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA WMO SA PANAM= A, VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA WORLD MAN OPPORTUNITIES = LUGANO (WORLD MAN OPPORTUNITIES FOR MAFIA MONEY LAUNDERING, OBVIOUSLY SPEAK= ING), VERME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BLOCKCHAIN INVEST, VE= RME MALAVITOSO PAOLO BARRAI DI CRIMINALISSIMA BIGBIT, VERME MALAVITOSO PAOL= O BARRAI DI CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 16 MILANO (FORMALM= ENTE DI SUO PADRE, NOTO MEGA RICICLA SOLDI DI CAMORRA, COSA NOSTRA E NDRANG= HETA, NONCHE' ANCHE LUI FAMOSISSIMO PEDOFILO VINCENZO BARRAI NATO A MILANO = IL 3.5.1938 ED ABITANTE IN VIA PADOVA 282 A MILANO: SANGUE MARCIO MAI MENTE= )!!! FRA L'ALTRO, I SCHIFOSISSIMI CRIMINALI GIACOMO ZUCCO DI BLOCKCAINLABIT E BL= OCKCHAIN LAB E PAOLO BARRAI DI TUTTO IL MERDAIO MALAVITOSO PRIMA CITATO, UN= ITI AGLI ALTRETTANTO VERMI CRIMINALISSIMI GIOVANNI PIROVANO, ENNIO DORIS, M= ASSIMO DORIS E OSCAR DI MONTIGNY DI "MAFIOLANUM-MEDIOLANUM", IN CANTON TICI= NO, ERAN DIETRO QUESTI MEGA RICICLAGGI DI CASH ASSASSINO, DELLA NDRANGHETA,= EFFETTUATI INSIEME ALL'ANIMALE DELINQUENTISSIMO OLIVER CAMPONOVO: UN FIDUC= IARIO ASSASSINO, AMATO ALLA FOLLIA, BEN APPUNTO, DA NDRANGHETA, MA ANCHE DA= COSA NOSTRA E CAMORRA! https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ http://www.area7.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della-ndra= ngheta-29f7ee00 https://www.laregione.ch/cantone/mendrisiotto/1228182/affari-della--ndrangh= eta-in-ticino--alla-sbarra-l-uomo-di-fiducia-della-cosca--l-ex-municipale-d= i-chiasso-e-la-moglie-del-fratello-del-boss https://www.swissinfo.ch/ita/tpf--processo--ndrangheta--chieste-pene-di-rec= lusione/43734126 https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ https://www.rsi.ch/la1/programmi/informazione/falo/tutti-i-servizi/Bella-ge= nte-10474214.html From newsfish@newsfish Thu Aug 1 00:45:07 2024 X-Received: by 2002:a05:620a:13da:: with SMTP id g26mr34786525qkl.410.1575306882138; Mon, 02 Dec 2019 09:14:42 -0800 (PST) X-Received: by 2002:a25:aa63:: with SMTP id s90mr391356ybi.133.1575306881669; Mon, 02 Dec 2019 09:14:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.unit0.net!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!g89no10363078qtd.0!news-out.google.com!o19ni915qtr.1!nntp.google.com!g89no10363069qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Dec 2019 09:14:41 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=137.100.137.30; posting-account=jUR2VwoAAABvVOeJj7huZLA3lnNu5zQ- NNTP-Posting-Host: 137.100.137.30 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: vhdl port connection length error From: silverace99@gmail.com Injection-Date: Mon, 02 Dec 2019 17:14:42 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9612 Hi, VHDL-illiterate here. I'm trying to hook up a xilinx logic probe in legacy VHDL code and am getting a complaint from the compiler that the expression length of the signal i'm feeding to the port doesn't match the expected size. ila_inst: entity work.ila(rtl) port map ( clk => CLOCK, probe0(31 downto 11) => std_logic_vector'(31 downto 11 => '0') .... According to the compiler (modelsim), the zero-fill i'm sending to the probe0 port has a expression length of only 9 bits and thus doesn't match the port size. I believe the expression as written should be defining 21 bits of 0's? Anybody have an idea what I am missing? Cheers, Stephen From newsfish@newsfish Thu Aug 1 00:45:07 2024 X-Received: by 2002:a37:6551:: with SMTP id z78mr92198qkb.144.1575310049532; Mon, 02 Dec 2019 10:07:29 -0800 (PST) X-Received: by 2002:a25:73ce:: with SMTP id o197mr655019ybc.14.1575310049210; Mon, 02 Dec 2019 10:07:29 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!185.151.15.255.MISMATCH!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!g89no10488519qtd.0!news-out.google.com!o19ni918qtr.1!nntp.google.com!g89no10488515qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Dec 2019 10:07:28 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=152.160.43.162; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 152.160.43.162 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12f93842-4610-477d-aebb-fcedde24667c@googlegroups.com> Subject: Re: vhdl port connection length error From: KJ Injection-Date: Mon, 02 Dec 2019 18:07:29 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 4 Xref: reader01.eternal-september.org comp.lang.vhdl:9613 On Monday, December 2, 2019 at 12:14:44 PM UTC-5, silve...@gmail.com wrote: - Can you post the entity definition for 'ila' and the exact compiler error message? - Assuming that 'probe0' consists of more bits than just '31 downto 11', where are the other bits being mapped? If probe0 does not have any more bits, then why are you port mapping to 'probe0(31 downto 11)' instead of just 'probe0'? Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:08 2024 X-Received: by 2002:ac8:5205:: with SMTP id r5mr722132qtn.230.1575310383966; Mon, 02 Dec 2019 10:13:03 -0800 (PST) X-Received: by 2002:a5b:708:: with SMTP id g8mr50903ybq.119.1575310383344; Mon, 02 Dec 2019 10:13:03 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no10502110qtd.0!news-out.google.com!o19ni921qtr.1!nntp.google.com!g89no10502108qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Dec 2019 10:13:03 -0800 (PST) In-Reply-To: <12f93842-4610-477d-aebb-fcedde24667c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=137.100.137.30; posting-account=jUR2VwoAAABvVOeJj7huZLA3lnNu5zQ- NNTP-Posting-Host: 137.100.137.30 References: <12f93842-4610-477d-aebb-fcedde24667c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: vhdl port connection length error From: silverace99@gmail.com Injection-Date: Mon, 02 Dec 2019 18:13:03 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9614 On Monday, December 2, 2019 at 11:07:31 AM UTC-7, KJ wrote: > On Monday, December 2, 2019 at 12:14:44 PM UTC-5, silve...@gmail.com wrote: > - Can you post the entity definition for 'ila' and the exact compiler error message? > - Assuming that 'probe0' consists of more bits than just '31 downto 11', where are the other bits being mapped? If probe0 does not have any more bits, then why are you port mapping to 'probe0(31 downto 11)' instead of just 'probe0'? > > Kevin Jennings Thanks for replying Kevin! probe0 does indeed have other bits being used, which I'm pasting below. The entity definition is as follows: COMPONENT ila PORT ( clk : IN STD_LOGIC; -- input wire clk probe0 : IN STD_LOGIC_VECTOR (31 downto 0); -- input wire [31:0] probe0 probe1 : IN STD_LOGIC_VECTOR (31 downto 0); -- input wire [31:0] probe1 probe2 : IN STD_LOGIC_VECTOR (31 downto 0); -- input wire [31:0] probe2 probe3 : IN STD_LOGIC_VECTOR (31 downto 0); -- input wire [31:0] probe3 probe4 : IN STD_LOGIC; -- input wire [0:0] probe4 probe5 : IN STD_LOGIC -- input wire [0:0] probe5 ); END COMPONENT; probe0 in it's entirety is mapped as follows: -- probe0(31 downto 11) => std_logic_vector'(31 downto 11 => '0'), -- probe0(10 downto 10) => std_logic_vector'(10 downto 10 => SIG_A), -- probe0( 9 downto 9) => std_logic_vector'(9 downto 9 => SIG_B), -- probe0( 8 downto 0) => std_logic_vector(SIG_C), Cheers, Stephen From newsfish@newsfish Thu Aug 1 00:45:08 2024 X-Received: by 2002:ae9:f511:: with SMTP id o17mr290528qkg.157.1575312648183; Mon, 02 Dec 2019 10:50:48 -0800 (PST) X-Received: by 2002:a0d:e10b:: with SMTP id k11mr150490ywe.105.1575312647859; Mon, 02 Dec 2019 10:50:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder5.feed.usenet.farm!feed.usenet.farm!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!g89no10590518qtd.0!news-out.google.com!o19ni921qtr.1!nntp.google.com!g89no10590515qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Dec 2019 10:50:47 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=152.160.43.162; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 152.160.43.162 References: <12f93842-4610-477d-aebb-fcedde24667c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9ba298bb-0aa2-40c7-8e5a-79fd62ad858c@googlegroups.com> Subject: Re: vhdl port connection length error From: KJ Injection-Date: Mon, 02 Dec 2019 18:50:48 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 31 Xref: reader01.eternal-september.org comp.lang.vhdl:9615 On Monday, December 2, 2019 at 1:13:05 PM UTC-5, silve...@gmail.com wrote: You posted the component declaration but not the entity declaration for ila= . They probably look nearly identical except for 'entity' vs 'component', = but please post the entity as well since sometimes the two are different an= d a cause for compiler errors. As a side note, since you are using direct entity instantiation (i.e. "ila_= inst: entity work.ila(rtl)"), you don't need any component declaration. Co= mponents are only needed when you don't have the source code for a particul= ar entity, usually because it is coming from some pre-compiled library from= a vendor or something. This is off topic, but thought you might find it u= seful. You say that probe0 is entirely mapped but what you showed for the mapping = is in comments, not live code. One line that looks suspicious is "probe0( 8 downto 0) =3D> std_logic_vecto= r(SIG_C)". Since SIG_A and SIG_B are one bit signals, does that mean SIG_C= is as well? If it is, then you're trying to map a single bit signal to a = nine bit vector in the port map which I think would produce the error messa= ge that you described. However, if it is still not compiling, you will nee= d to post the following posted to diagnose: - The entity definition for ila - The full port map in the instantiation of ila - Declarations of all signals that are included in the port mapping (i.e. S= IG_A, SIG_B, SIG_C, etc.) You didn't post the error message from Modelsim either. Since that error m= essage will refer to a line number in your source file, you will also need = to let us know exactly which line is being pointed to by Modelsim. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:08 2024 X-Received: by 2002:a0c:bf0b:: with SMTP id m11mr1592477qvi.123.1575324379671; Mon, 02 Dec 2019 14:06:19 -0800 (PST) X-Received: by 2002:a25:aa63:: with SMTP id s90mr1484231ybi.133.1575324379198; Mon, 02 Dec 2019 14:06:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no11051573qtd.0!news-out.google.com!o19ni934qtr.1!nntp.google.com!g89no11051563qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Dec 2019 14:06:18 -0800 (PST) In-Reply-To: <9ba298bb-0aa2-40c7-8e5a-79fd62ad858c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=137.100.137.30; posting-account=jUR2VwoAAABvVOeJj7huZLA3lnNu5zQ- NNTP-Posting-Host: 137.100.137.30 References: <12f93842-4610-477d-aebb-fcedde24667c@googlegroups.com> <9ba298bb-0aa2-40c7-8e5a-79fd62ad858c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: vhdl port connection length error From: silverace99@gmail.com Injection-Date: Mon, 02 Dec 2019 22:06:19 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9616 On Monday, December 2, 2019 at 11:50:50 AM UTC-7, KJ wrote: > On Monday, December 2, 2019 at 1:13:05 PM UTC-5, silve...@gmail.com wrote= : > You posted the component declaration but not the entity declaration for i= la. They probably look nearly identical except for 'entity' vs 'component'= , but please post the entity as well since sometimes the two are different = and a cause for compiler errors. >=20 > As a side note, since you are using direct entity instantiation (i.e. "il= a_inst: entity work.ila(rtl)"), you don't need any component declaration. = Components are only needed when you don't have the source code for a partic= ular entity, usually because it is coming from some pre-compiled library fr= om a vendor or something. This is off topic, but thought you might find it= useful. >=20 > You say that probe0 is entirely mapped but what you showed for the mappin= g is in comments, not live code. >=20 > One line that looks suspicious is "probe0( 8 downto 0) =3D> std_logic_vec= tor(SIG_C)". Since SIG_A and SIG_B are one bit signals, does that mean SIG= _C is as well? If it is, then you're trying to map a single bit signal to = a nine bit vector in the port map which I think would produce the error mes= sage that you described. However, if it is still not compiling, you will n= eed to post the following posted to diagnose: > - The entity definition for ila > - The full port map in the instantiation of ila > - Declarations of all signals that are included in the port mapping (i.e.= SIG_A, SIG_B, SIG_C, etc.) >=20 > You didn't post the error message from Modelsim either. Since that error= message will refer to a line number in your source file, you will also nee= d to let us know exactly which line is being pointed to by Modelsim. >=20 > Kevin Jennings I was hoping maybe it would be an obvious issue so I hadn't posted in full.= Let me do all that now. The block being instantiated is actually verilog, but here it is anyway: module ila ( clk, probe0, probe1, probe2, probe3, probe4, probe5 ); input clk; input [31 : 0] probe0; input [31 : 0] probe1; input [31 : 0] probe2; input [31 : 0] probe3; input [0 : 0] probe4; input [0 : 0] probe5; endmodule And this is the full declaration of the instantiation, as well as the signa= l declarations being used: PORT_0 :in unsigned(21 downto 0); (This is part of the port list of t= he calling block) ... signal SIG_A : std_logic; signal SIG_B : std_logic; signal SIG_C : unsigned(8 downto 0); signal SIG_D : unsigned(7 downto 0); signal SIG_E : unsigned(21 downto 0); signal SIG_F : std_logic; signal SIG_G : std_logic; ... =20 ila_inst: entity work.ila(rtl)=20 port map ( clk =3D> CLOCK, (line 330) probe0(31 downto 11) =3D> std_logic_vector'(31 downto 11 = =3D> '0'),=20 (line 331) probe0(10 downto 10) =3D> std_logic_vector'(10 downto 10 = =3D> SIG_A), =09 (line 332) probe0( 9 downto 9) =3D> std_logic_vector'(9 downto 9 =3D>= SIG_B), =09 (line 333) probe0( 8 downto 0) =3D> std_logic_vector(SIG_C), =09 (line 334) probe1(31 downto 8) =3D> std_logic_vector'(31 downto 8 = =3D> '0'), (line 335) probe1( 7 downto 0) =3D> std_logic_vector(SIG_D), =09 (line 336) probe2(31 downto 22) =3D> std_logic_vector'(31 downto 22 = =3D> '0'), (line 337) probe2(21 downto 0) =3D> std_logic_vector(SIG_E), =09 (line 338) probe3(31 downto 22) =3D> std_logic_vector'(31 downto 22 = =3D> '0'), (line 339) probe3(21 downto 0) =3D> std_logic_vector(PORT_0), =09 (line 340) probe4 =3D> SIG_F, (line 341) probe5 =3D> SIG_G );=09 Below are the error messages. Error (line 330): (vcom-1324) Range choice length is 21; length of expressi= on of element association is 9. Error (line 334): (vcom-1324) Range choice length is 24; length of expressi= on of element association is 9. Error (line 336): (vcom-1324) Range choice length is 10; length of expressi= on of element association is 9. Error (line 338): (vcom-1324) Range choice length is 10; length of expressi= on of element association is 9. The error messages seem to all be pointing at my attempts at zero-fill. From newsfish@newsfish Thu Aug 1 00:45:08 2024 X-Received: by 2002:ac8:6a11:: with SMTP id t17mr7113023qtr.284.1575404512433; Tue, 03 Dec 2019 12:21:52 -0800 (PST) X-Received: by 2002:a81:de03:: with SMTP id k3mr5501655ywj.504.1575404512095; Tue, 03 Dec 2019 12:21:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.alt.net!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!g89no2310387qtd.0!news-out.google.com!w29ni103qtc.0!nntp.google.com!g89no2310383qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Dec 2019 12:21:51 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.78.184.31; posting-account=aQ5fBwoAAAAOgfkQPX_fLOtY7cq0ZIxW NNTP-Posting-Host: 194.78.184.31 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: E' UN MASSONE NDRANGHETISTA: GIANFRANCO CARPEORO (LIBRI)! E' INCAPPUCCIATO BERLUSCONICCHIO ASSASSINO PARTE DI NDRINA MEGA OMICIDA: GIANFRANCO CARPEORO ( NOTO PURE COME " GIANFRANCO CARPEORO: IL SICARIO PAZZO AL SERVIZIO DI CRAXI E BERLUSCONI")! E' UN From: FABIO VENZI-GRAN MAESTRO GLRI Injection-Date: Tue, 03 Dec 2019 20:21:52 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 434 Xref: reader01.eternal-september.org comp.lang.vhdl:9617 E' UN MASSONE NDRANGHETISTA: GIANFRANCO CARPEORO (LIBRI)! E' INCAPPUCCIATO = BERLUSCONICCHIO ASSASSINO PARTE DI NDRINA MEGA OMICIDA: GIANFRANCO CARPEORO= ( NOTO PURE COME " GIANFRANCO CARPEORO: IL SICARIO PAZZO AL SERVIZIO DI CR= AXI E BERLUSCONI")! E' UN...........KILLER PUNCIUTO, PARTE DELLA MEGA KILLE= R COSCA PERNA DI COSENZA: GIANFRANCO CARPEORO ( https://it.wikipedia.org/w= iki/%27Ndrina_Perna )! FU L'IDEATORE DELL'UCCISIONE DI DENIS BERGAMINI, AVV= ENUTA INFATTI A COSENZA A FINI ANNI 80 ( http://www.iacchite.blog/omicidio-= bergamini-ecco-come-hanno-ucciso-denis-prima-di-stenderlo-sullasfalto1/ ). = NEGLI ANNI 80, IL PURE NOTO PEDERASTA GIANFRANCO CARPEORO FACEVA OGNI TIPO = DI SCHIFEZZA COL SUO COMPARE SUPER STRA PEDOFILO SILVIO BERLUSCONI E CON BE= TTINO ^BOTTINO^ CRAXI (PENSATE CHE QUI POTETE ASCOLTARE STA MERDACCIA SATA/= N/AZISTA DI GIAFRANCO "PECORARO" CARPEORO, RAGLIARE CHE BERLUSCONI NON HA M= AI RICICLATO SOLDI DI MAFIA E NON HA STECCATO BETTINO CRAXI NOTO IN TUTTO I= L MONDO COME BOTTINO CRAXI... https://www.youtube.com/watch?v=3Dv1f8qDQQHC0 https://www.ilfattoquotidiano.it/2012/10/30/mafia-soldi-narcotraffico-a-del= lutri-per-investimento-in-attivita-berlusconi/398736/ http://www.maurizioturco.it/dossier/cera-una-volta-il-mafioso-d/1998-07-07-= la-padania-silvi.html https://www.ilfattoquotidiano.it/2017/01/20/bettino-craxi-tangenti-per-mili= ardi-a-domicilio-ecco-perche-fu-condannato/3329146/ https://www.repubblica.it/politica/1995/11/24/news/berlusconi_craxi_e_10_mi= liardi-24581177/ CRIMINALISSIMA SFACCIATAGGINE PARI A RAGLIARE CHE LA LUNA SI VEDE NEL CIELO= A PARTIRE DALLE DIECI DI MATTINA ED IL SOLE A PARTIRE DALLE 22, IN PIENA = SERATA, NE PIU' NE MENO). ANCHE IO SONO DA SEMPRE IN GIRI MASSONICI, E SONO= UN EX CRAXIANO E BERLUSCONIANO (EX PERO', ORA TIFO A MANETTA M5S UNITO A C= ENTRO SINISTRA, COSA CHE INFATTI STA SALVANDO IL NOSTRO PAESE, FACENDO PREC= IPITARE LO SPREAD E FACENDO SALIRE LA BORSA, COSI' DA ARRICCHIRICI TUTTI E = TANTO). MA I MASSONI BERLUSCONICCHI E NDRANGHETISTI, SEMPRE PI=C3=9A MI SCH= IFANO. E DA PENTITO, DA EX DI QUESTI GIRI, RITENGO GIUSTO CHE IL MONDO SAPP= IA CHE CRIMINALI EFFERATI, PURE ASSASSINI, ASSASSINI, ASSASSINI, ESSI SIANO= . CHI APPOGGIA I RICICLAGGI DI SOLDI DI NDRANGHETA, PORTATI AVANTI DA SEMPR= E DA STO VERME MALAVITOSO CHE E' GIANFRANCO CARPEORO ( O VERME VERME MALAVI= TOSO GIANFRANCO PECORARO CARPEORO CHE SIA), E' UN MASSONE MARCHIGIANO, OVVI= AMENTE PURE ESTREMAMENTE PEDOFILO E DELINQUENTE: PAOLO CARDEN=C3=81. A PRO= POSITO DEL QUALE... E' PEDOFILO ED ASSASSINO: PAOLO CARDEN=C3=80 (FACEBOOK, TWITTER, CRIMINALIS= SIMO BLOG VINCITORI E VINTI....VEDRA' COME LO FAREMO DIVENIRE PARTE DELLA S= ECONDA CATEGORIA E NON PRIMA, CHE RICICLI DA SEMPRE SOLDI DI MAFIA, CAMORRA= E NDRANGHETA O MENO..."O MENO", OVVIAMENTE, SI FA PER DIRE)?!? RAGLIA DI A= VER FATTO IL "PRIVATE BANKER", MA NON DICE CHE SUOI PRINCIPALI CLIENTI SONO= I NOTI MAFIOSI CRISAFULLI DI MILANO! UNA DELLE FAMIGLIE DI COSA NOSTRA PIU= ' ASSASSINE DI TUTTI I TEMPI! https://milano.repubblica.it/cronaca/2018/02/22/news/droga_maxiprocesso_mil= ano_biagio_crisafulli_condannato_20_anno_boss-189496506/ MA CHI' E' DAVVERO LO SCHIFOSO PEDERASTA ED ASSASSINO PAOLO CARDEN=C3=80 (C= HE HA PER CRIMINALISSIMO CV, SOLO QUELLO DEL TIPICO MEGA RICICLA SOLDI MAFI= OSI)? BEH, INTANTO DICIAMO CHE TRATTASI PURE DI NOTO NAZISTA, RAZZISTA E KU= KLUK KLANISTA! OLTRE CHE SATANISTA SODOMIZZA ED AMMAZZA BAMBINI!!! https://www.mail-archive.com/racket-users@googlegroups.com/msg40600.html E' LUI DIETRO TANTISSIMI OMICIDI MASSONICI A CUI HAN FATTO SEGUITO POI DIVI= SIONE DEL CORPO DEGLI UCCISI IN TANTI PEZZI E SOTTERRAMENTO DEL TUTTO IN TA= NTI BOSCHI MARCHIGIANI. ESATTISSIMAMENTE COME DA QUESTI ARTICOLI. https://www.corriereadriatico.it/marche/marche_persone_scomparse_minori-660= 674.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ED E' CRIMINALISSIMA LA CARDEN=C3=80 CONSULTING DI VIA MONTESSORI 6, FALERO= NE (FM). COME E' E STRA E' CRIMINALISSIMA LA CARDEN=C3=80 AND PARTNERS DI V= IA MONTESSORI 6, FALERONE (FM). DA ANNI, LE DUE, RICICLANO SOLDI MEGA KILL= ER DI COSA NOSTRA, CAMORRA, NDRANGHETA E MAFIA RUSSA (CHE NON PER NIENTE, L= AVO' PRIMI PROPRI =E2=82=AC OMICIDA, A LIVELLO MONDIALE, ESATTAMENTE NELLE = MARCHE, COME DA QUESTO PUNTUALISSIMO ARTICOLO http://www.comitato-antimafia-lt.org/la-mafia-russa-la-piu-pericolisa-e-la-= piu-sottovalutata/ )!! ED I VERMI SCHIFOSI CHE LA RAPPRESENTANO, I BASTARDI EFFERATI CRIMINALI STE= FANO CARDEN=C3=80 E PAOLO CARDEN=C3=80 SONO PURE, COME DETTO, DUE NOTISSIMI= "SATA-N-AZISTI" , OSSIA DUE SATANISTI NAZISTI, DUE PEDOFILI INCULA ED AMMA= ZZA BAMBINI! SON REGISTI DI CENTINAIA DI OMICIDI E SPARIZIONI DI PERSONE, E= SATTAMENTE COME DA QUESTO ARTICOLO http://www.anconatoday.it/cronaca/persone-scomparse-regione-marche.html SI, SI, E' PROPRIO COSI': E' CRIMINALISSIMA LA CARDEN=C3=80 E PARTNERS DI V= IA MONTESSORI 6, 63837 FALERONE (FM) - Tel: 0734.710786 CON CRIMINALISSIMA = EMAIL info@cardenaconsulting.it E CRIMINALISSIMA PARTITA IVA 01840990442). = DA ANNI RICICLA SOLDI ASSASSINI DI COSA NOSTRA, CAMORRA E MAFIA RUSSA (CHE,= COME DETTO, NON PER NIENTE, LAVO' PRIMI PROPRI RUBLI ASSASSINI PROPRIO NEL= LE MARCHE.. COME PROVATO DA QUESTO ALTRO INECCEPIBILE ARTICOLO http://www.culturaeculture.it/di-tutto-un-po/mafia-russa-la-storia-sulla-pe= lle-66587/ )! PAOLO CARDEN=C3=80 =C3=89 UNO SCHIFOSISSIMO PEDOFILO ( =C3=89= IL PRESIDENTE DELLA ASSOCIAZIONE "INCULIAMO I BAMBINI E LI AMMAZZIAMO PER= SATANA", ASSOCIAZIONE ANIMALESCHISSIMA GEMELLA DELL'ASSOCIAZIONE ORGOGLIO = PEDOFILO http://www.cshg.it/lapice-della-violenza-orgoglio-pedofilo-e-legit= timazione-della-pedofilia.html ) IL MASSONE ECONOMISTA PEDERASTA ED ASSASSINO PAOLO CARDEN=C3=80 (NATO IL 2.= 10.1971 E RESIDENTE IN VIA POZZO 105, 63837 FALERONE ) HA PURE UN BLOG CRIM= INALISSIMO: VINCITORI E VINTI! NOI SAREMO I VINCITORI CHE METTEREMO LUI, I = SUOI MEGA CRIMINI E MEGA BALLE, SPALLE AL MURO! MENTRE LUI SARA' IL VINTISS= IMO! IL VERME DELINQUENTISSIMO PAOLO CARDEN=C3=80 (TWITTER), OLTRE AD ESSER= NOTO PEDOFILO E' UN MEGA RICICLA SOLDI MAFIOSI PER I SUPER KILLER DI COSA = NOSTRA: CRISAFULLI DI MILANO ( E NON SOLO)! COME DA "TRADIZIONE" DI SUOI MA= NDANTI, OSSIA IL PURE NOTISSIMO PEDOFILO SILVIO BERLUSCONI (OLTRE CHE STRAG= ISTA SILVIO BERLUSCONI, SPAPPOLANTE EROICI MAGISTRATI COME GIOVANNI FALCONE= E PAOLO BORSELLINO https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ ). ED I PORCI, PURE MEGA RICICLA SOLDI ASSASSINI DI MALAVITE DI MEZZO MONDO: E= NNIO DORIS E MASSIMO DORIS DI MEDIOLANUM, MAFIOLANUM, CAMORRANUM, NDRANGOLA= NUM, NAZISTANUM! BUT AGAIN AND AGAIN AND AGAIN... CHI =C3=88 DAVVERO STO PEDOFILO ASSASSINO = CHIAMANTESI PAOLO CARDEN=C3=80 RESIDENTE ANCHE A PENNA SAN GIOVANNI (MACERA= TA), VIA UMBERTO I, NUMERO 41! DI BASTARDAMENTE CRIMINALE CARDEN=C3=80 CONS= ULTING, BASATA IN VIA MONTESSORI 6, 63837 FALERONE (FM) - Tel: 0734.710786 = E DI MEGA TRUFFATORE BLOG VINCITORI E VINTI ( CHE ESISTE PER FAR ABBOCCARE = I "CIUCCI DEL WEB" I QUALI, ABBOCCANDO AI SUOI FALLIMENTARI SERVIZI, SEMPRE= PERDONO TUTTI I PROPRI RISPARMI, SIA PER LA TOTALE INCOMPETENZA DI PAOLO C= ARDEN=C3=80 SUI MERCATI FINANZIARI MONDIALI, SIA PER LA INDOLE SEMPRE TRUFF= ALDINA DEL VERME CRIMINALISSIMO PAOLO CARDEN=C3=80 STESSO)! E CHI E' IL NOTO PEZZO DI MERDA, FIGLIO DI PUTTANA, LADRO, SEMPRE FALSO, CO= CAINOMANE, DELINQUENTE ESTREMISSIMO E PURE NOTO PEDOFILO STEFANO CARDEN=C3= =80? http://www.formazione-lavoro.eu/img/public/stefano.jpg AL PUNTO, NOW, PLEASE! VI SONO OPINIONI SOLO VOMITEVOLI SU STO PEDOFIL-O-MOSESSUALE PAZZO, SODOMIZ= ZA ED AMMAZZA BIMBI E RAGAZZINI DI PAOLO CARDEN=C3=81 DI DELINQUENTISSIMO B= LOG VINCITORI E VINTI!!! COME TUTTO IL MONDO BEN SA', CHI STA QUI SCRIVENDO ORA, E' UN FUORI USCITO = DA QUEL PARTITO STRA COLMO DI COSA NOSTRA, CAMORRA, NDRANGHETA E CATTIVERIA= ANTI DEMOCRATICA DI ESTREMISSIMA DESTRA CHE E' FORZA ITALIA ( OVE SGUAZZA,= A LIVELLO DI MEGA BALLE, CHE FA SCRIVERE SU INTERNET, LA MASSONA SATA-N-AZ= ISTA, LA PUTTANA SEMPRE CON CAZZI SU CAZZI IN CULO: GINA NIERI DI MEDIASET,= MAFIASET, CAMORRASET, NDRANGASET, NAZISTSET). DI STO VERME CRIMINALE DI PAOLO CARDEN=C3=81 CONOSCO TUTTO, SO' TUTTO! E QU= INDI, COME DICONO A NAPULE " MO' M'HAGGIA PROPRIO SFUGA' "!!! IL PEDOFILO ASSASSINO PAOLO CARDENA' DI FORZA ITALIA MAFIOSA ( https://picc= hionews.it/attualita/paolo-cardena-relatore-al-convegno-sulle-banche-promos= so-da-forza-italia-macerata ) PROFESSIONALLY SPEAKING, SI DEFINISCE "PRIVAT= E BANKER". MA NON DICE CHE SUOI CLIENTI NUMERI UNO SONO I MAFIOSI ASSASSINI= CRISAFULLI DI MILANO! UNA DELLE FAMIGLIE DI COSA NOSTRA PIU' BASTARDAMENTE= KILLER DI TUTTI I TEMPI! https://it.wikipedia.org/wiki/Crisafulli_(clan) E POI, COME CITATO, IL VOMITEVOLE PEDERASTA PAOLO CARDEN=C3=81 DI CRIMINALI= SSIMO BLOG VINCITORI E VINTI E' PURE CONOSCIUTISSIMO PEDOFIL-O-MOSESSUALE (= NULLA CONTRO GLI OMOSESSUALI PER BENE, TRASPARENTI, CHE NON SI NASCONDONO.= .. MA TUTTO CONTRO I PEDOFIL-O-MOSESSUALI, QUELLI CHE INCULANO NEONATI, BAM= BINI, RAGAZZINI, ADOLESCENTI, COME FA DA SEMPRE IL PEDERASTA PAOLO CARDEN= =C3=81: QUI IN UNA FOTO CHE GLI ABBIAMO FATTO, MENTRE IN MUTANDE, FISSAVA, = CON SGUARDO DA DEPRAVATO SESSUALE MAXIMO, UN BAMBINO DI OTTO ANNI, NELLE AD= IACENZE DI UN CAMPO ROM PADANO, VICINO A COLOGNO MONZESE, VICINO ALLA SEDE = CRIMINALISSIMA DI MEDIASET-MAFIASET-CAMORRASET-NDRANGASET-NAZISTSET OVE SI = ERA APPENA RECATO https://www.commoditiestrading.it/public/autori/635338392358575000_Cardena.= jpg BAMBINO DI OTTO ANNI CHE MEZZ'ORA DOPO AVREBBE INCULATO A SANGUE. STAVAMO P= EDINANDO DA MESI E MESI E MESI QUESTRO TOPO DI FOGNA PEDERASTA DI PAOLO CAR= DEN=C3=81, ABBIAMO FOTOGRAFATO E VIDEATO IL TUTTO, PRESTO OGNI COSA SU MIGL= IAIA DI SITI, ANCHE DI PLUTONIO E MARTE, NON SOLO DI QUESTO PIANETA SEMPRE = PIU' "PICCIRIDDU PICCIRIDDU" .. USO SLANG SICILIANO, PER FAR SENTIRE IL MEG= A RICICLA CASH DI COSA NOSTRA, PAOLO CARDEN=C3=81, COME SE IN UNA "COSA SUA= " AAAA)!!! SI, PROPRIO COSI', BABIES, PROPRIO COSI'!!! VI SONO OPINIONI SOLO ORRIBILI = SUL BASTARDISSIMO CRIMINALE PAOLO CARDEN=C3=81 NATO A MACERATA IL 2.19.1971= ( PER NON DIRE QUANTO SIA PURE SEMPRE FALSO, LADRO, TRUFFATORE, BRUCIANTE = TUTTI I RISPARMI DI CHI, A LUI, IDIOTAMENTE ABBOCCHI E QUINDI SI AFFIDI VIA= INTERNET=E2=80=A6 PER NON DIRE INOLTRE QUANTO SIA ANCHE MANDANTE DI OMICID= I, MALATO MENTALE, COCAINOMANE E TANTISSIMO ALTRO)?!? FATEVI QUESTE DOMANDUZZEDDE, ORA PLEASE ( AGAIN AND AGAIN... SCRIVO IN SLAN= G SICILIANO, ESSENDO PAOLO CARDENA=E2=80=99 UNO SCHIFOSO MALAVITOSO RICICLA= TORE DI SOLDI ASSASSINI DI COSA NOSTRA, IN PRIMIS, POI ANCHE DI CAMORRA E N= DRANGHETA=E2=80=A6 GLI FACCIO COME SE UN FAVORE..LO FACCIO SENTIRE COME SE = A CASA=E2=80=A6 LO FACCIO SENTIRE COME SE IN UNA=E2=80=A6SANGUINARISSIMA...= =E2=80=9CCOSA SUA=E2=80=9D=E2=80=A6 AAAH): COME E' IL VERME CRIMINALISSIMO= PAOLO CARDEN=C3=80, LO SCHIFOSO PEDERASTA PAOLO CARDEN=C3=80, NELLA VITA P= RIVATA? COI PANTALONI ABBASSATI? LA BESTIA PEDOFILESCA E MEGA RICCHIONESCA PAOLO CARDENA', DUE, TRE SERE ALL= A SETTIMANA, VA' IN LOCALI ^OCCULTISSIMI^ DI TIPO ESTREMAMENTE DEPRAVATO! A= PERTI SOLO A MASSONI OMOSESSUALI LEGHISTI E BERLUSCONIANI! CI VA' COL PARI = PEDERASTA GIULIO TREMONTI (IL CUI AMANTE OMOSESSUALISSIMO ERA IL NAZISTA, A= NZI, SATA-N-AZISTA ALEXANDER BOETTCHER, QUELLO CHE SI RIEMPIVA DI COCAINA E= FACEVA SFREGIARE CON ACIDO ASSASSINO TANTA GENTE INNOCENTE, INNOCUA, PER B= ENE.. COLUI CHE IN UN IMPULSO DI ONESTA' SI E' DEFINITO UN PAZZO DEPRAVATO = SESSUALE http://www.dagospia.com/rubrica-29/cronache/sono-deviato-sessuale-martina-l= evato-era-sadomasochismo-124763.htm IL DEAL ERA QUESTO: ALEXANDER BOETTCHER INCULAVA L'OMOSESSUALE, SPESSO PURE= DI TIPO PEDOFILO, GIULIO TREMONTI ..COME QUESTO TWITTER ACCOUNT FA STRA IN= TUIRE https://twitter.com/alexanboettcher E L ^ OCCULTISSIMO" MASSONE LAVA SOLDI MAFIOSI, OMOSESSUALE DI TIPO PERVERT= ITO, GIULIO TREMONTI, CERCAVA DI FARLO SFONDARE IN POLITICA..ALLA FINE, PER= O', L'UNICA COSA SFONDATA RIMANEVA L'ANO DEL CULACCHIONE "CHIC LE FREAK" GI= ULIO TREMONTI STESSO https://elfobruno.wordpress.com/2011/07/29/tremonti-sarebbe-gay-ma-nessuno-= puo-dirlo/ http://www.mosinforma.org/cecchi-paone-pdl-piena-di-gay-anche-un-ministro-g= iulio-tremonti/ ). CON ALTRI PEDERASTA QUALI SONO DA SEMPRE GIULIANO FERRARA E CLAUDIO CERASA = ( GIULIANO FERRARA AMMETTE SE STESSO, QUI, COME GLI PIACCIA PRENDERLO IN S= UO IMMENSO BUCO DEL CULO E DA UNA VITA https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ RICCHIONI PEDERASTA GIULIANO FERRARA E CLAUDIO CERASA DE IL FOGLIO, SI.....= FOGLIO PERO' DA USARSI SOLO X PULIRSI L'ANO IN CASO DI FINE DI CARTA IGIEN= ICA'... AND NEVER FORGET PLEASE, IL VERME CLAUDIO CERASA DA PALERMO E' AFFI= LIATO A COSA NOSTRA DA DECENNI, E' PUNCIUTO: FAMIGLIA CIMINNA, MANDAMENTO D= I CACCAMO.. E' UN NUOVO MARCELLO DELL'UTRI, DI FATTO https://groups.google.com/forum/?nomobile=3Dtrue#!topic/wwfx/cGpTIPY2T1o = ). OLTRE CHE CON IL GIA' 3 VOLTE IN CARCERE, PAOLO BARRAI NATO A MILANO IL 28.= 6.65. ED IL GIA' 2 VOLTE IN CARCERE, VINCENZO BARRAI NATO IL 3.5.1938, DI D= ELINQUENZIALISSIMA BSI ITALIA SRL VIA SOCRATE 26 MILANO. OLTRE CHE CON IL N= OTO GIOVANE PEDERASTA TANTO QUANTO RICCARDO BARRAI NATO IL 26.11.1996 ( ORA= SEMPRE A FARE ORGE GAY PRESSO UNIVERSITY OF READING). OLTRE CHE CON IL VER= ME MALAVITOSO E PURE LUI NOTO PEDOFIL-O-MOSESSUALE STEFANO BASSI DI MEGA TR= UFFATORE BLOG IL GRANDE BLUFF. OLTRE CHE COL RICCHIO-N-AZISTA ALESSANDRO CE= CCHI PAONE, NOTO IN TUTTO IL MONDO COME ALESSANDRO "CHECCHI" PAONE. SPESSIS= SIMO SON LI PRESENTI ANCHE I BANCHIERI MALAVITOSI DI BANCA MEDIOLANUM, GLI = OMOSESSUALI E CRIMINALISSIMI GIOVANNI PIROVANO, ENNIO DORIS ED ANGELO RENOL= DI ( NOTI PEDERASTA PURE). IVI FANNO ORGE SU ORGE ANCHE CON RAGAZZINI DI 14= ANNI!! IN DARK ROOMS! SI, E' PROPRIO COSI' E STRA COSI': E' UNO SCHIFOSISS= IMO PEDOFIL-O-MOSESSUALE, IL VERME BERLUS-CO-RROTTO PAOLO CARDENA'!!! PAGA = ADOLESCENTI ROM DI 8-12 ANNI, PER INCULARLI A SANGUE! VA' IN CAMPI ROM, DUE= , TRE VOLTE ALLA SETTIMANA, AT 4 AM, IN PIENA NOTTE, A PAGARE ZINGARELLI, P= ER INCULARLI TERRIFICANTEMENTE ( VEDI INEQUIVOCABILE FOTO A PROPOSITO, DI C= UI ABBIAM PRIMA GIA' SCRITTO https://www.commoditiestrading.it/public/autori/635338392358575000_Cardena.= jpg )! TUTTI QUESTI EFFERATISSIMI CRIMINI, SIA DI TIPO PEDERASTA, CHE DI RICICLAGG= IO DI SOLDI ASSASSINI, SONO EFFETTUATI IN CONNESSIONE COL MANDANTE DI OMICI= DI, RAZZISTA, KU KLUK KLANISTA, LADRO, TRUFFATORE, CORROTTISSIMO, SEMPRE FA= LSO, ESTORTORE DI SOLDI, MEGA STALKER SU INTERNET, GIA' 3 VOLTE IN CARCERE,= CACCIATO A SBERLE DA CITIBANK, INDAGATO DA 7 PROCURE ITALIANE E DALLA PROC= URA DI LUGANO, MEGA MULTATO DALLA CONSOB : BASTARDISSIMO CRIMINALE PAOLO PI= ETRO BARRAI NATO A MILANO IL 28.6.65. A PROPOSITO DEL QUALE, NON POSSO CHE SCRIVERE... E' DAVVERO DA ARRESTARE SUBITO ( PRIMA CHE FACCIA AMMAZZARE ANCORA), IL TER= RORISTA NAZIRAZZISTA ED ASSASSINO, PAOLO BARRAI, NATO A MILANO IL 28.6.1965= . NONCHE' MEGA RICICLA SOLDI MAFIOSI E POLITI-C-RIMINALI, OSSIA FRUTTO DI M= EGA RUBERIE E MEGA MAZZETTE, RICEVUTE DA LEGA LADRONA! MEGA TRUFFATORE E MEGA RICICLA CASH ASSASSINO PAOLO BARRAI! ANCHE LUI NOTO = PEDOFIL-O-MOSESSUALE SODOMIZZA BAMBINI E RAGAZZINI! CACCIATO DA CITIBANK A = SBERLE, PER MEGA FRODI CHE LI FACEVA! FONDATORE DELLA SIGLIA TERRORISTICA D= EI NUOVI MEGASSASSINI DI ESTREMA DESTRA: "NUOVI NAR"! FONDATORE DEL KU KLUK= KLAN PADANO! GIA' CONDANNATO AL CARCERE A MILANO ED IN BRASILE ( 8 ANNI E = PURE PER PEDERASTIA OMOSESSUALE, RIPETO, PURE PER PEDERASTIA OMOSESSUALE)! = MULTATO DA CONSOB BEN 70.000 =E2=82=AC! DESTABILIZZANTE L'ITALIA PER FILO N= AZISTI SERVIZI SEGRETI SVIZZERI ( ITALIA, DICEVAMO, DA 30 ANNI, GIUSTISSIMA= MENTE, NAZIONE SCHIFATA IN TUTTO IL MONDO, IN QUANTO FASCIOMAFIOSA DITTATUR= A DI BERLUSCONIA.. NON PER NIENTE, TUTTE LE PIU' GRANDI INDUSTRIE, IN ITALI= A DA SECOLI, DALLA TIRANNIASSASSINA DI BERLUSCONIA SON SCAPPATE, VEDI FIAT,= PIRELLI, LUXOTTICA, MERLONI, PARMALAT E MIGLIAIA E MIGLIAIA DI ALTRE... E = CHE SIA CHIARO, PLS, CHE IDDIO BENEDICA I GRANDI PM CHE NON SOPPORTANTO IL = CANCRO DEL MONDO INTERO, SILVIO BERLUSCONI, COME HENRY WOODCOCK, ILDA BOCAS= SINI E CHIUNQUE ALTRO DI QUESTA AMMIREVOLISSIMA CATEGORIA)! FACENTE CRIMINI= SU CRIMINI E NAZI-ST-ALKING VIA INTERNET, SU ORDINE DEI BASTARDI INFINITI = CRIMINALI SILVIO BERLUSCONI, PAOLO BERLUSCONI ED UBALDO LIVOLSI DI FININVES= T, INNEGGIANTE ALLO SPAPPOLAMENTO DI MAGISTRATI SCOMODI "COME BERLUSCONI GR= ANDISSIMAMENTE FECE CON FALCONE E BORSELLINO", PAROLE DETTE DAL TERRORISTA = MAFIOSO, NAZISTA ED ASSASSINO PAOLO BARRAI, TANTISSIME VOLTE E PURE IN PUBB= LICO. MA VAMONOS BABIES, NOW, VAMONOS, VAMONOS, LET'S GO...... STO SCRIVENDO DEL - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA, MEGA R= ICICLA SOLDI DI NDRANGHETA, EIDOO, DIRETTA DAL VERME CALABRESE E NDRANGHETI= STA NATALE M. FERRARA O NATALE FERRARA CHE SIA https://ch.linkedin.com/in/n= atale-ferrara COME DA QUESTI OTTIMI ARTICOLI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edi COME DA QUESTO BELLISSIMO DOCUMENTARIO https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l ( FOUNDER OF EXTREMELY CRIMINAL EIDOO : YOUR VERY HOODLUM ASSET EXPERIENCE,= MEGA MAFIA MONEY LAUNDERER FOR COSA NOSTRA, NDRANGHETA, CAMORRA AND ASSASS= IN RUSSIAN GANSGTERS, NOT FOR NOTHING, CLOSE TO PRINCIPAL OF MURDERS, SLAUG= HTERS AND ASCERTAINED PEDOPHILE SILVIO BERLUSCONI). - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA CRYPTOP= OLYS ( OVE MEGA RICICLA SOLDI MAFIOSI COL NOTO VERME KUKLUKLANISTA, NAZIFAS= CISTA, MEGA RICICLA SOLDI MAFIOSI, BASTARDO VERO ARON CAMPONOVO DI MALAVITO= SISSIMA TANTO QUANTO IBEX CAPITAL LTD, MALAVITOSISSIMA TANTO QUANTO IBEX SE= RVICES LTD, MALAVITOSISSIMA TANTO QUANTO MONCLER SUISSE LTD https://ch.linkedin.com/in/aron-r-camponovo-a0030094 ED IL NOTO RAZZISTA, KUKLUKLANISTA, HITLERIANO, MEGA RICICLA SOLDI DI MALAV= ITE DI TUTTO IL MONDO ED ACCERTATO PEDOFILO INCULA BAMBINI: OLIVER CAMPONOV= O DI CAMPONOVO STRATEGY, ORA SOTTO PROCESSI SU PROCESSI, PER I SUOI MEGA RI= CICLAGGI DI CASH KILLER, BEN APPUNTO, DI NDRANGHETA, COME DA QUESTI OTTIMI = LINKS https://www.laregione.ch/cantone/mendrisiotto/1228182/affari-della-ndranghe= ta-in-ticino-alla-sbarra-l-uomo-di-fiducia-della-cosca-l-ex-municipale-di-c= hiasso-e-la-moglie-del-fratello-del-boss https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ ) - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA, SEMPRE= MEGA RICICLA SOLDI MAFIOSI, BITINCUBATOR VENTURES GRONO (CH) https://www.moneyhouse.ch/en/company/bitincubator-ventures-sa-12554072241 ( AFFIANCATO IN QUESTO DA QUELL'ALTRO SCHIFOSO PEDOFILO DI CLAUDIO LEVRINI = DI MALAVITOSA BITCOIN FOUNDATION, E, BEN APPUNTO, DI CRIMINALISSIMA BITINCU= BATOR VENTURES GRONO, COME DA QUEL PEZZO DI MERDA, NAZI-ST-ALKER E PURE LUI= NOTO PEDERASTA DI GIACOMO ZUCCO DI BLOCKCHAINLABIT ... NAZI-ST-ALKER E PUR= E LUI NOTO PEDOFILO OMOSESSUALE GIACOMO ZUCCO PURE DI HITLERIANI TEA PARTIE= S, CHE CHIAMA SEMPRE LA CIA ATTUALE PER CHIEDERE DI AMMAZZARE CHI NON SCHIF= OSAMENTE NAZISTA COME SE STESSO) https://www.moneyhouse.ch/en/company/bitincubator-ventures-sa-12554072241 - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI BLOCKCHAIN INVEST - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA BIGBITG= OLD E CRIMINALISSIMA BIGBIT - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA WORLD M= AN OPPORTUNITIES LUGANO - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN= CRYPTOECONOMY - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA WMO SA = PANAMA - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA LEGA LA= DRONA - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA FORZA I= TALIA MAFIOSA - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMI IL GIOR= NALE E LIBERO - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI ASSASSINO KU KLUK KLAN= PADANO - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI GRAN LOGGIA ITALIA MAS= SONICA DEL MALAVITOSO BANCHIERE GIUSEPPE SABATO DI BANCA ESPERIA ( GRUPPO B= ANCARIO DELLO SPAPPOLA MAGISTRATI, NONCHE' ACCLARATISSIMO PEDOFILO SILVIO B= ERLUSCONI). - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA CRIMINALISSIMA H 14= , DELL'OMOSESSUALE ^OCCULTO^ LUIGI BERLUSCONI https://www.gay.it/gossip/new= s/bacio-gay-luigi-berlusconi ( NIPOTE DEL TOPO DI FOGNA LUIGI BERLUSCONI, A SUA VOLTA, BESTIA CRIMINALE = DELLA CHIUSA PER MEGA RICICLAGGIO DI SOLDI MAFIOSI, BANCA RASINI http://tem= i.repubblica.it/micromega-online/mafia-politica-e-affari-sette-domande-al-c= avaliere/?printpage=3Dundefined E FIGLIO DI NOTO PEDOFILO SILVIO BERLUSCONI https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ http://www.elafter.com/foro/showthread.php?t=3D948509 COME PURE DI NOTO MANDANTE DI DOZZINE DI STRAGI SILVIO BERLUSCONI http://ww= w.vnews24.it/2014/05/29/borsellino-sentenza-choc-stragi-commissionate-berlu= sconi/ http://www.ilfattoquotidiano.it/2017/06/09/graviano-e-berlusconi-peter-gome= z-ricostruisce-le-stragi-del-1993/3648613/ COME PURE DI NOTO MANDANTE DI CENTINAIA E CENTINAIA DI OMICIDI MASCHERATI D= A FINTI SUICIDI, MALORI, INCIDENTI: SILVIO BERLUSCONI http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l ) - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA MALAVITOSA CGNAL DI= MARCO CARRAI http://espresso.repubblica.it/plus/articoli/2016/10/17/news/marco-carrai-l-= amico-che-mette-matteo-renzi-nei-guai-1.285898 (CANZONCINA CHE STIAMO PREPARANDO A PROPOSITO, CON QUESTO VINCENTISSIMO CHO= RUS: "A COSA NOSTRA, CAMORRA E NDRANGHETA, IL BUCATO FINANZIARIO TU LO FAI,= RICICLA SOLDI MAFIOSI PAOLO BARRAI, RICICLA SOLDI MAFIOSI MARCO CARRAI) - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DELLA MERDA FASCIOMAFIOSA= DI ENNIO DORIS E MASSIMO DORIS: BANCA MEDIOLANUM, COSANOSTRANUM, CAMORRANU= M, NDRANOLANUM - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI DI CRIMINALISSIMA BSI ITA= LIA SRL DI VIA SOCRATE 26 MILANO. - DELINQUENTISSIMO FIGLIO DI PUTTANA PAOLO BARRAI, NATO A MILANO IL 28.6.19= 65, FINITO "APPENA APPENA" 3 VOLTE IN GALERA TORNIAMO ORA AL DOVUTISSIMO PUNTO INIZIALE, PLEASE. I SATANISTI, NAZIFASCIS= TI, PEDERASTA ED ASSASSINI PAOLO CARDENA' E STEFANO CARDENA' DI CRIMINALISS= IMA CARDENA' CONSULTING, COME DETTO, SONO DIETRO TANTI CASI DI RAPIMENTI, S= TUPRI, UCCISIONI ED OCCULTAMENTO DI CADAVERI DI BAMBINI, RAGAZZINI ED ADULT= I, AVVENUTI SPECIALMENTE NELLE LORO MARCHE, MA NON SOLO ( COME DI UCCISIONI= DI NEONATI E BAMBINI AL FINE DI ANIMALESCO PRELEVARE E TRAFFICARE ORGANI D= EGLI STESSI). IL TUTTO PER CENTINAIA, ANZI, MIGLIAIA E MIGLIAIA DI CASI! MACERATA E' CITTA' DA SEMPRE, SATANISTISSIMA. CON UNO FRA I PIU' ALTI TASSI= MONDIALI DI UCCISIONI VIA OMICIDI MASSONICI E CONSEGUENTI SPARIZIONI ( COL= TUTTO TANTISSIMO SUPERIORE AI GIA' TASSI MOSTRUOSI DI NOTISSIME IN TUTTO C= IO', NEW ORLEANS NEGLI USA O CIUDAD JUAREZ IN MESSICO). E TUTTO QUESTO COME= DA TANTI, TANTISSIMI LINKS CHE VI SONO IN RETE. DA CUI NE PRENDIAMO SOLO T= RE, AL VOLO, PER OVVI MOTIVI DI TEMPO E SPAZIO DIGITALE http://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche-= si-cercano-558-persone/811406/ https://www.ilrestodelcarlino.it/macerata/cronaca/ragazza-scomparsa-14-anni= -ansia-1.3410852 https://www.cronacheancona.it/2017/12/02/persone-scomparse-in-40-anni-quasi= -700-casi-in-tutte-le-marche/68705/ EBBENE, I PEDOFILI BASTARDISSIMAMENTE ASSASSINI PAOLO CARDENA' E STEFANO CA= RDENA' DI CRIMINALISSIMA CARDENA' CONSULTRING FURONO ANCHE I RESPONSABILI D= ELLA UCCISIONE DI PAMELA MASTROPIETRO: STUPRATA, UCCISA E POI SEZIONATA CON= EXPERTISE TIPICA DI MEDICI LEGALI MASSONICI, BIANCHI, MARCHIGIANI, MACERAT= ISSIMI. TRATTASI DI MASSONI ASSASSINI FOTOCOPIA DELLA GANG SANGUINARISSIMA,= AI TEMPI, DEL MOSTRO DI FIRENZE! POTRESTE RAGLIARE DA DENTRO I VOSTRI ASSA= SSINI CAPPUCCI " WAGLIO', E' ARRIVATO SHERLOCK HOLMES DEI POVERI, COME FAI = A DIRE UNA COSA DEL GENERE"? LA MIA RISPOSTA? ECCOLA QUI, WAGLIUNCE', ECCOL= A QUI! "MA CHE STATE GRUGNENDO, STARNAZZANDO, RAGLIANDO VOI? MICA DICO IO T= UTTO CIO'. LO DICE UNO DEI PRINCIPALI GRAN MAESTRI FILO PIDUISTI CHE PIU' S= AN DI TUTTO QUESTO, IMMERSO DA SEMPRE IN MARI DI COMPLOTTI, OMICIDI, SPARIZ= IONI DI MATRICE MASSONICO NAZIFASCISTA, ALIAS DI MATRICE NEO BERLUSCONICCHI= A.. STO SCRIVENDO DEL MASSONE DA SEMPRE DENTRO AD OMICIDI MASSONICI QUALE E= ' E STRA E' IL NOTO SATANISTA COSENTINO, IL MASSONE CALABRESE TUTT'UNO CON = LA NDRANGHETA: GIANFRANCO CARPEORO http://www.carpeoro.com/ ( O ANCHE NOTO SATANISTA COSENTINO, IL MASSONE CALABRESE TUTT'UNO CON LA ND= RANGHETA: GIOVANNI FRANCESCO CARPEORO.. O ANCHE NOTO SATANISTA COSENTINO, I= L MASSONE CALABRESE TUTT'UNO CON LA NDRANGHETA: GIANFRANCO PECORARO O ANCHE= O ANCHE NOTO SATANISTA COSENTINO, IL MASSONE CALABRESE TUTT'UNO CON LA NDR= ANGHETA: GIOVANNI FRANCESCO PECORARO). CHE NE PARLA, DI TUTTO QUESTO, QUI https://petalidiloto.com/2012/12/intervista-carpeoro-su-massoneria-e.html E QUI https://www.youtube.com/watch?v=3DDuJQGxmAvnk INSIEME ALL'ALTRO MASSONE, DA SEMPRE PURE DENTRO TANTISSIMI OMICIDI DI TIPO= MASSONICO: PAOLO FRANCESCHETTI https://petalidiloto.com/2018/02/due-parole-sullomicidio-pamela-mastropietr= o.html CHE RIBADISCE IL TUTTO QUI https://velvetnews.it/2018/05/27/pamela-mastropietro-mafia-nigeriana-legata= -ad-ambienti-massonici/ E QUI http://maestrodidietrologia.blogspot.com/2018/02/pamela-e-luomo-nero-parte-= 1.html COSA SOTTOLINEATA ANCHE DA UN ALTRO PROTAGONISTA DI PARECCHI OMICIDI MASSON= ICI: GIOELE MAGALDI. SI, PROPRIO LUI, IL NAZIFASCISTA LEGHISTA GIOELE MAGAL= DI ( CHE PRENDE PER I FONDELLI IL MONDO, RAGLIANDO SU INTERNET DI ESSERE DI= CENTRO SINISTRA... SI, "DI CENTRO SINISTRA" COME LO ERANO HITLER E MUSSOLI= NI) http://www.libreidee.org/2018/06/magaldi-guerra-ai-massoni-che-hanno-ucciso= -la-democrazia/ ]. DELLA CUI LOGGIA GRANDE ORIENTE DEMOCRATICO FA PARTE IL TRUFFATORE FOGGIANO= DI PALAZZO CHIGI GIUSEPPE CONTE ( CHE PER 9 MESI HA RAGLIATO DI MEGA BOOM = ECONOMICO IN ARRIVO NEL 2019... E CHE ORA, DAVANTI ALLA SUA ENNESIMA IDIOTA= CANNATA, STARNAZZA CHE STAVA SOLO SCHERZANDO... https://www.repubblica.it/= politica/2019/04/10/news/conte_quella_sull_anno_bellissimo_era_solo_una_bat= tuta_-223727910/' A ME PIACEVA IL MOVIMENTO 5 STELLE, IO HO VOTATO MOVIMENTO 5 STELLE ULTIMAM= ENTE, MA SE LO STESSO CONTINUA A STARE CON GLI ASSASSINI NAZISTI E NDRANGHE= TISTI DI LEGA LADRONA, MI INIZIA A SCHIFARE TANTO QUANTO I KU KLUK KLANISTI= OMICIDA DI VIA BELLERIO STESSO, MOVIMENTO 5 STELLE CHE SI PUO' SALVARE SOL= O SE SI UNISCE AGLI AFFATTO MALE NICOLA ZINGARETTI E CHIUNQUE ALTRO DABBENE= DI CENTRO SINISTRA). A FRA NON MOLTO PER ALTRE TONNELLATE DI DETTAGLI A PROPOSITO. SOON BACK . From newsfish@newsfish Thu Aug 1 00:45:09 2024 X-Received: by 2002:a0c:e2cf:: with SMTP id t15mr392393qvl.127.1575418988000; Tue, 03 Dec 2019 16:23:08 -0800 (PST) X-Received: by 2002:a81:408:: with SMTP id 8mr235475ywe.88.1575418987724; Tue, 03 Dec 2019 16:23:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no2896561qtd.0!news-out.google.com!w29ni117qtc.0!nntp.google.com!g89no2896551qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Dec 2019 16:23:07 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:40e:101:d3c0:819d:16d3:467:f00d; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2601:40e:101:d3c0:819d:16d3:467:f00d References: <12f93842-4610-477d-aebb-fcedde24667c@googlegroups.com> <9ba298bb-0aa2-40c7-8e5a-79fd62ad858c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6b03d238-71c1-455d-b53c-b0e28d7690a8@googlegroups.com> Subject: Re: vhdl port connection length error From: KJ Injection-Date: Wed, 04 Dec 2019 00:23:07 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9618 I don't see anything wrong with what you have posted, maybe it is some peculiarity about the Verilog to VHDL interface or maybe a tool bug. If you have paid support open a ticket. Didn't have time to put it in and play with it on my own. For a workaround, you could define a zero vector constant like this constant Zero: std_logic_vector(31 down to 0) := (others => '0'); Then on the port map take out an appropriate size slice to attach to the port. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:09 2024 X-Received: by 2002:a05:620a:2193:: with SMTP id g19mr11073350qka.317.1575585229753; Thu, 05 Dec 2019 14:33:49 -0800 (PST) X-Received: by 2002:a25:3244:: with SMTP id y65mr7134360yby.359.1575585229514; Thu, 05 Dec 2019 14:33:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no9338428qtd.0!news-out.google.com!w29ni206qtc.0!nntp.google.com!g89no9338422qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Dec 2019 14:33:49 -0800 (PST) In-Reply-To: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.14.29.253; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 73.14.29.253 References: <7536e289-1fb3-4752-97eb-783cbc8a0d37@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <74ef96b3-b39f-44e3-b8fe-1fc8273296a2@googlegroups.com> Subject: Re: VHDL'2019 is ratified ! From: kevin.m.neilson@gmail.com Injection-Date: Thu, 05 Dec 2019 22:33:49 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9619 On Saturday, September 7, 2019 at 6:35:11 AM UTC-6, the....@gmail.com wrote: > Jim Lewis shared the news : > > IEEE Std 1076-2019 has been approved by the IEEE SASB today. > > What a ride it was ! > > I'm still frustrated by the crazy process and the refusal of my own tiny feature request but it's good to see that venerable language still moving forward and kicking Verilog's ass ;-) > > yg Maybe I can use it by the time I retire. Some customers still whine when I use Verilog-2005 because their tools won't parse such-and-such, so for synthesizable code, I pretty much have to stick to last century. From newsfish@newsfish Thu Aug 1 00:45:09 2024 X-Received: by 2002:ae9:efc5:: with SMTP id d188mr22450688qkg.178.1575793349152; Sun, 08 Dec 2019 00:22:29 -0800 (PST) X-Received: by 2002:a25:189:: with SMTP id 131mr5637363ybb.507.1575793348845; Sun, 08 Dec 2019 00:22:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no5483409qtd.0!news-out.google.com!o19ni220qtr.1!nntp.google.com!g89no5483402qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Dec 2019 00:22:28 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.221.183.98; posting-account=ELp5SgoAAABoisgkAl0GoNIS2IZ5Ghtl NNTP-Posting-Host: 117.221.183.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <74390faf-c668-4695-a85e-5039d8f99663@googlegroups.com> Subject: Error in vhdl code From: sweetymalutty@gmail.com Injection-Date: Sun, 08 Dec 2019 08:22:29 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9620 When i was compiling my vhdl code i got an error.....near "EOF":syntax error...can anyone please tell me why this happens. The error is pointing to the last line of my code. Please help.... From newsfish@newsfish Thu Aug 1 00:45:10 2024 X-Received: by 2002:aed:2b62:: with SMTP id p89mr22290755qtd.258.1575825710705; Sun, 08 Dec 2019 09:21:50 -0800 (PST) X-Received: by 2002:a81:d543:: with SMTP id l3mr17952138ywj.394.1575825710522; Sun, 08 Dec 2019 09:21:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!185.151.15.255.MISMATCH!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!g89no6619325qtd.0!news-out.google.com!w29ni570qtc.0!nntp.google.com!g89no6619313qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Dec 2019 09:21:50 -0800 (PST) In-Reply-To: <74390faf-c668-4695-a85e-5039d8f99663@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.205.158.211; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 50.205.158.211 References: <74390faf-c668-4695-a85e-5039d8f99663@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3b8d157b-6922-488a-b720-97056347e7a1@googlegroups.com> Subject: Re: Error in vhdl code From: Rick C Injection-Date: Sun, 08 Dec 2019 17:21:50 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 12 Xref: reader01.eternal-september.org comp.lang.vhdl:9621 On Sunday, December 8, 2019 at 3:22:30 AM UTC-5, sweety...@gmail.com wrote: > When i was compiling my vhdl code i got an error.....near "EOF":syntax error...can anyone please tell me why this happens. The error is pointing to the last line of my code. Please help.... The tool can't "think", it only knows what it is looking for. Most likely you have a control structure or some formatting feature missing and it is finding the end of the file without the missing syntax. Go through your code and make sure all your control structures are complete and balanced and make sure all your formatting constructs are complete. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:10 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: Error in vhdl code Date: Sun, 8 Dec 2019 12:21:29 -0600 Organization: A noiseless patient Spider Lines: 7 Message-ID: References: <74390faf-c668-4695-a85e-5039d8f99663@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 8 Dec 2019 18:21:32 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="24115a4044bb1f87b0c24ec1f3d49d51"; logging-data="8183"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19dEs9L0oDKKfmYvaz7u+O66VHwcnUBwOc=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:m9RNra0NUwThAcJlFXVmOeb6ICI= In-Reply-To: <74390faf-c668-4695-a85e-5039d8f99663@googlegroups.com> Xref: reader01.eternal-september.org comp.lang.vhdl:9622 On 2019-12-08 02:22, sweetymalutty@gmail.com wrote: > When i was compiling my vhdl code i got an error.....near "EOF":syntax error...can anyone please tell me why this happens. The error is pointing to the last line of my code. Please help.... > You probably have an END statement missing somewhere: end if, end process, end loop, end case, end architecture, ... Charles Bailey From newsfish@newsfish Thu Aug 1 00:45:11 2024 X-Received: by 2002:ac8:32ec:: with SMTP id a41mr23790915qtb.235.1575865480711; Sun, 08 Dec 2019 20:24:40 -0800 (PST) X-Received: by 2002:a0d:de07:: with SMTP id h7mr18439466ywe.90.1575865480397; Sun, 08 Dec 2019 20:24:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!82.197.223.106.MISMATCH!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!g89no8015869qtd.0!news-out.google.com!w29ni616qtc.0!nntp.google.com!g89no8015863qtd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Dec 2019 20:24:39 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.139.183.211; posting-account=ELp5SgoAAABoisgkAl0GoNIS2IZ5Ghtl NNTP-Posting-Host: 14.139.183.211 References: <74390faf-c668-4695-a85e-5039d8f99663@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5197e3a4-aef3-4b74-a6a0-a785ce679ea1@googlegroups.com> Subject: Re: Error in vhdl code From: sweetymalutty@gmail.com Injection-Date: Mon, 09 Dec 2019 04:24:40 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9623 On Sunday, December 8, 2019 at 11:51:34 PM UTC+5:30, Charles Bailey wrote: > On 2019-12-08 02:22, sweetymalutty@gmail.com wrote: > > When i was compiling my vhdl code i got an error.....near "EOF":syntax error...can anyone please tell me why this happens. The error is pointing to the last line of my code. Please help.... > > > You probably have an END statement missing somewhere: end if, end > process, end loop, end case, end architecture, ... > > Charles Bailey Thank you so much...it worked....the problem was indeed a missing END statement. From newsfish@newsfish Thu Aug 1 00:45:11 2024 X-Received: by 2002:ac8:7699:: with SMTP id g25mr4438739qtr.75.1576097830952; Wed, 11 Dec 2019 12:57:10 -0800 (PST) X-Received: by 2002:a25:db87:: with SMTP id g129mr1473513ybf.119.1576097830436; Wed, 11 Dec 2019 12:57:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no5068474qtd.0!news-out.google.com!w29ni1028qtc.0!nntp.google.com!g89no5068471qtd.0!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Dec 2019 12:57:10 -0800 (PST) In-Reply-To: <6b03d238-71c1-455d-b53c-b0e28d7690a8@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=137.100.137.30; posting-account=jUR2VwoAAABvVOeJj7huZLA3lnNu5zQ- NNTP-Posting-Host: 137.100.137.30 References: <12f93842-4610-477d-aebb-fcedde24667c@googlegroups.com> <9ba298bb-0aa2-40c7-8e5a-79fd62ad858c@googlegroups.com> <6b03d238-71c1-455d-b53c-b0e28d7690a8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <614b421d-39a0-42a3-a734-5085c5a6ed0e@googlegroups.com> Subject: Re: vhdl port connection length error From: silverace99@gmail.com Injection-Date: Wed, 11 Dec 2019 20:57:10 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9624 On Tuesday, December 3, 2019 at 5:23:10 PM UTC-7, KJ wrote: > I don't see anything wrong with what you have posted, maybe it is some peculiarity about the Verilog to VHDL interface or maybe a tool bug. If you have paid support open a ticket. Didn't have time to put it in and play with it on my own. > > For a workaround, you could define a zero vector constant like this > constant Zero: std_logic_vector(31 down to 0) := (others => '0'); > Then on the port map take out an appropriate size slice to attach to the port. > > Kevin Jennings Thanks for the suggestion; I used that workaround and while it looks janky, at least it works. Could certainly be a tool issue; I'll consult our modelsim rep about it. Cheers, Stephen From newsfish@newsfish Thu Aug 1 00:45:11 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer03.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx12.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: vhdl port connection length error Newsgroups: comp.lang.vhdl References: <12f93842-4610-477d-aebb-fcedde24667c@googlegroups.com> <9ba298bb-0aa2-40c7-8e5a-79fd62ad858c@googlegroups.com> <6b03d238-71c1-455d-b53c-b0e28d7690a8@googlegroups.com> <614b421d-39a0-42a3-a734-5085c5a6ed0e@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <614b421d-39a0-42a3-a734-5085c5a6ed0e@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 191211-0, 11/12/2019), Outbound message X-Antivirus-Status: Clean Lines: 43 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 12 Dec 2019 09:18:33 UTC Organization: virginmedia.com Date: Thu, 12 Dec 2019 09:18:34 +0000 X-Received-Bytes: 3056 X-Received-Body-CRC: 1138735127 Xref: reader01.eternal-september.org comp.lang.vhdl:9625 On 11/12/2019 20:57, silverace99@gmail.com wrote: > On Tuesday, December 3, 2019 at 5:23:10 PM UTC-7, KJ wrote: >> I don't see anything wrong with what you have posted, maybe it is some peculiarity about the Verilog to VHDL interface or maybe a tool bug. If you have paid support open a ticket. Didn't have time to put it in and play with it on my own. >> >> For a workaround, you could define a zero vector constant like this >> constant Zero: std_logic_vector(31 down to 0) := (others => '0'); >> Then on the port map take out an appropriate size slice to attach to the port. >> >> Kevin Jennings > > Thanks for the suggestion; I used that workaround and while it looks janky, at least it works. Could certainly be a tool issue; I'll consult our modelsim rep about it. Before you consult your rep I suspect this is a bug in your version of Modelsim as: "probe(31 downto 11)=>std_logic_vector'(31 downto 11 =>'0')," works fine for me (Modelsim 2019.4). I do get a warning though: vcom Message # 1514: This is an informational warning. When an aggregate does not contain a named element association that has a choice that is a range and that has an expression that is of the type of the aggregate, when that aggregate appears at a place where an OTHERS choice in the aggregate would not be allowed, the direction of the aggregate is obtained from the direction of the index subtype of the base array type (at the applicable index position), not from the direction of the range choice(s) of the element association(s). The range choice(s) have no effect on the direction of the aggregate. [DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] Perhaps a simpler solution is: "probe(31 downto 11)=>(others=>'0')," Hans www.ht-lab.com > > Cheers, > Stephen > From newsfish@newsfish Thu Aug 1 00:45:11 2024 X-Received: by 2002:a0c:e84d:: with SMTP id l13mr67907145qvo.53.1578064804633; Fri, 03 Jan 2020 07:20:04 -0800 (PST) X-Received: by 2002:a25:54e:: with SMTP id 75mr55041025ybf.215.1578064804471; Fri, 03 Jan 2020 07:20:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no8914490qtd.0!news-out.google.com!w29ni621qtc.0!nntp.google.com!g89no8914478qtd.0!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Jan 2020 07:20:04 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=80.235.154.71; posting-account=p-AaZQoAAAD82khi0kHhXnni9wohh0Wn NNTP-Posting-Host: 80.235.154.71 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b93f5d9-327a-45b1-a6b8-17b90c7db97f@googlegroups.com> Subject: International Journal of Embedded Systems and Applications (IJESA) From: ranulflambard20@gmail.com Injection-Date: Fri, 03 Jan 2020 15:20:04 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9626 International Journal of Embedded Systems and Applications (IJESA) ISSN: 1839-5171 http://wireilla.com/ijesa/index.html Scope & Topics International Journal of Embedded Systems and Applications (IJESA) is a qua= rterly open access peer-reviewed journal that publishes articles which cont= ribute new results in all areas of the Embedded Systems and applications. T= he goal of this journal is to bring together researchers and practitioners = from academia and industry to focus on understanding Embedded Systems and e= stablishing new collaborations in these areas.Authors are solicited to cont= ribute to the journal by submitting articles that illustrate research resul= ts, projects, surveying works and industrial experiences that describe sign= ificant advances in the areas of Embedded Systems & applications. Topics of interest =E2=80=A2 Application-specific processors and devices =E2=80=A2 Business Applications =E2=80=A2 Component and binding models =E2=80=A2 Embedded computing education =E2=80=A2 Embedded hardware support =E2=80=A2 Embedded system architecture =E2=80=A2 Hardware and software co-design =E2=80=A2 Integration with SOA =E2=80=A2 Middleware =E2=80=A2 Programming abstractions =E2=80=A2 Real-time systems =E2=80=A2 Service-Oriented Architectures =E2=80=A2 Testing techniques Paper Submission Authors are invited to submit papers for this journal through ijesa@wireill= a.com=20 =E2=80=A2 Final Manuscript Due February 12,2020 Here=E2=80=99s where you can reach us: ijesa@wireilla.com From newsfish@newsfish Thu Aug 1 00:45:12 2024 X-Received: by 2002:a37:4891:: with SMTP id v139mr22721649qka.172.1580225754624; Tue, 28 Jan 2020 07:35:54 -0800 (PST) X-Received: by 2002:a25:618a:: with SMTP id v132mr16232025ybb.95.1580225754408; Tue, 28 Jan 2020 07:35:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no7737442qtd.0!news-out.google.com!w29ni814qtc.0!nntp.google.com!g89no7737433qtd.0!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Jan 2020 07:35:54 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2605:b100:120:b9ca:3907:ede9:c566:69a7; posting-account=-3m9WQoAAADqph1cWZ4uX0b-9dwN4Ozr NNTP-Posting-Host: 2605:b100:120:b9ca:3907:ede9:c566:69a7 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <39a6ef79-424e-49cf-b723-a3e0b6a20f31@googlegroups.com> Subject: Array of std_logic_vector From: digitalguy33@gmail.com Injection-Date: Tue, 28 Jan 2020 15:35:54 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9627 type PACKET_REG_TYPE is array (0 to 127) of std_logic_vector(7 downto 0); =20 signal common_stream_header : std_logic_vector(63 downto 0); signal stream_1_tx_int : PACKET_REG_TYPE; =20 =20 stream_1_tx_int(3 to 10) <=3D common_stream_header; -- FAIL. Same number b= its on each side?? Target type dut_lib.spis_sclk_pkg.PACKET_REG_TYPE in signal assignment is d= ifferent from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR. (vcom-1272) Length of expected is 8; length of actual is 64. =20 stream_1_tx_int(3 to 4) <=3D common_stream_header(63 downto 48); -- FAIL. Target type dut_lib.spis_sclk_pkg.PACKET_REG_TYPE in signal assignment is d= ifferent from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR. (vcom-1272) Length of expected is 2; length of slice name is 16. =20 stream_1_tx_int(3 to 4) <=3D PACKET_REG_TYPE(common_stream_header(63 downt= o 48)); -- FAIL. (vcom-1583) Illegal type converson from 'ieee.std_logic_1164.STD_LOGIC_VECT= OR' to 'dut_lib.spis_sclk_pkg.PACKET_REG_TYPE' (array element type differen= ce). (vcom-1272) Length of type "PACKET_REG_TYPE" is 1046; length of operand is = 16. (vcom-1272) Length of expected is 2; length of actual is 1046. =20 stream_1_tx_int(3 to 4) <=3D common_stream_header(63 downto 56) & common= _stream_header(55 downto 48); -- PASS. I have an array of bytes as defined above. I want to make assignments to m= ultiple array elements at a time but am having a lot of trouble. In the fi= rst example I try to assign a 64-bit signal to 8 elements of the array whic= h ends up being 64-bits as well. It doesn=E2=80=99t work.=20 I can=E2=80=99t figure why none of the examples of array assignment work?? = I even tried type casting. I finally got my code to compile with the last = example but it makes coding cumbersome.=20 Is there a better way to do this. As a note, I tried the VHDL 2008 switch = in Modelsim but it just started complaining about my (others =3D> (others = =3D> =E2=80=980=E2=80=99) assignments. From newsfish@newsfish Thu Aug 1 00:45:12 2024 X-Received: by 2002:ac8:32ec:: with SMTP id a41mr22513522qtb.235.1580229911560; Tue, 28 Jan 2020 08:45:11 -0800 (PST) X-Received: by 2002:a25:e696:: with SMTP id d144mr17314105ybh.316.1580229911257; Tue, 28 Jan 2020 08:45:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no7911799qtd.0!news-out.google.com!w29ni820qtc.0!nntp.google.com!g89no7911793qtd.0!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Jan 2020 08:45:10 -0800 (PST) In-Reply-To: <39a6ef79-424e-49cf-b723-a3e0b6a20f31@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=152.160.43.162; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 152.160.43.162 References: <39a6ef79-424e-49cf-b723-a3e0b6a20f31@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3f18b468-75b0-40a7-830b-6fec4480de2b@googlegroups.com> Subject: Re: Array of std_logic_vector From: KJ Injection-Date: Tue, 28 Jan 2020 16:45:11 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9628 On Tuesday, January 28, 2020 at 10:35:56 AM UTC-5, digita...@gmail.com >=20 > Is there a better way to do this. As a note, I tried the VHDL 2008 switc= h in Modelsim but it just started complaining about my (others =3D> (others= =3D> =E2=80=980=E2=80=99) assignments. A better way to be to define PACKET_REG_TYPE a bit differently and then use= it for common_stream_header like this: type PACKET_REG_TYPE is array (natural range <>) of std_logic_vector(7 down= to 0); signal common_stream_header : PACKET_REG_TYPE(0 to 7); signal stream_1_tx_int : PACKET_REG_TYPE(0 to 127); Then you can assign like this: stream_1_tx_int(3 to 10) <=3D common_stream_header; Note a couple of things: - The basic problem you have is thinking that a 64 entry array is equivalen= t to an 8x8 array, it's not. - PACKET_REG_TYPE is now an unconstrained array. When you declare signals/= variables of that type you need to supply the range as shown. - The assignment of the particular 'bytes' of stream_1_tx_int is all done i= n one step. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:12 2024 X-Received: by 2002:a05:620a:211c:: with SMTP id l28mr23432891qkl.423.1580241200201; Tue, 28 Jan 2020 11:53:20 -0800 (PST) X-Received: by 2002:a81:368d:: with SMTP id d135mr18371434ywa.2.1580241199984; Tue, 28 Jan 2020 11:53:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no8389258qtd.0!news-out.google.com!w29ni830qtc.0!nntp.google.com!g89no8389249qtd.0!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Jan 2020 11:53:19 -0800 (PST) In-Reply-To: <39a6ef79-424e-49cf-b723-a3e0b6a20f31@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.10; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.10 References: <39a6ef79-424e-49cf-b723-a3e0b6a20f31@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6c240cde-92b0-404b-9ad8-7153ce49f6b5@googlegroups.com> Subject: Re: Array of std_logic_vector From: Rick C Injection-Date: Tue, 28 Jan 2020 19:53:20 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9629 On Tuesday, January 28, 2020 at 10:35:56 AM UTC-5, digita...@gmail.com wrot= e: > type PACKET_REG_TYPE is array (0 to 127) of std_logic_vector(7 downto 0); > =20 > signal common_stream_header : std_logic_vector(63 downto 0); > signal stream_1_tx_int : PACKET_REG_TYPE; > =20 > =20 > stream_1_tx_int(3 to 10) <=3D common_stream_header; -- FAIL. Same number= bits on each side?? > Target type dut_lib.spis_sclk_pkg.PACKET_REG_TYPE in signal assignment is= different from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR. > (vcom-1272) Length of expected is 8; length of actual is 64. > =20 > stream_1_tx_int(3 to 4) <=3D common_stream_header(63 downto 48); -- FAIL= . > Target type dut_lib.spis_sclk_pkg.PACKET_REG_TYPE in signal assignment is= different from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR. > (vcom-1272) Length of expected is 2; length of slice name is 16. > =20 > stream_1_tx_int(3 to 4) <=3D PACKET_REG_TYPE(common_stream_header(63 dow= nto 48)); -- FAIL. > (vcom-1583) Illegal type converson from 'ieee.std_logic_1164.STD_LOGIC_VE= CTOR' to 'dut_lib.spis_sclk_pkg.PACKET_REG_TYPE' (array element type differ= ence). > (vcom-1272) Length of type "PACKET_REG_TYPE" is 1046; length of operand i= s 16. > (vcom-1272) Length of expected is 2; length of actual is 1046. > =20 > stream_1_tx_int(3 to 4) <=3D common_stream_header(63 downto 56) & comm= on_stream_header(55 downto 48); -- PASS. >=20 > I have an array of bytes as defined above. I want to make assignments to= multiple array elements at a time but am having a lot of trouble. In the = first example I try to assign a 64-bit signal to 8 elements of the array wh= ich ends up being 64-bits as well. It doesn=E2=80=99t work.=20 >=20 > I can=E2=80=99t figure why none of the examples of array assignment work?= ? I even tried type casting. I finally got my code to compile with the las= t example but it makes coding cumbersome.=20 You could try defining a function that accepts as input the common_stream_h= eader data type and returns the array slice you need. I assume you want to= avoid the typing of four lines to do the assignment in multiple places. T= he function will encapsulate that. =20 > Is there a better way to do this. As a note, I tried the VHDL 2008 switc= h in Modelsim but it just started complaining about my (others =3D> (others= =3D> =E2=80=980=E2=80=99) assignments. I would figure out what is going on with this. VHDL2008 doesn't break thin= gs that I know of.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:13 2024 X-Received: by 2002:a05:620a:b19:: with SMTP id t25mr26428339qkg.82.1580267436493; Tue, 28 Jan 2020 19:10:36 -0800 (PST) X-Received: by 2002:a5b:8c5:: with SMTP id w5mr18301860ybq.488.1580267436316; Tue, 28 Jan 2020 19:10:36 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!g89no9431557qtd.0!news-out.google.com!w29ni883qtc.0!nntp.google.com!g89no9431554qtd.0!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Jan 2020 19:10:35 -0800 (PST) In-Reply-To: <3f18b468-75b0-40a7-830b-6fec4480de2b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=65.92.40.70; posting-account=-3m9WQoAAADqph1cWZ4uX0b-9dwN4Ozr NNTP-Posting-Host: 65.92.40.70 References: <39a6ef79-424e-49cf-b723-a3e0b6a20f31@googlegroups.com> <3f18b468-75b0-40a7-830b-6fec4480de2b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Array of std_logic_vector From: digitalguy33@gmail.com Injection-Date: Wed, 29 Jan 2020 03:10:36 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9630 Thank you for your reply. It is really helpful. From this I take it that s= ince PACKET_REG_TYPE is specified as a byte then all assignments must be ba= sed on a byte.=20 I didn=E2=80=99t paste all of the code but there is another array of ADC da= ta: type ADC_REG_TYPE is array (0 to 20) of std_logic_vector(31 downto 0).= In order to assign this ADC data to my stream array I take it I would hav= e to repackage it like: Signal adc_data : PACKET_REG_TYPE(0 to 83). Then I could assign the whole thing at once: stream_1_tx_int(11 to 94) <=3D adc_data; Or I could assign one channel as: stream_1_tx_data(11 to 14) <=3D adc_data(0 to 3); Thanks again for your help. From newsfish@newsfish Thu Aug 1 00:45:13 2024 X-Received: by 2002:ad4:498d:: with SMTP id t13mr26194795qvx.58.1580299008649; Wed, 29 Jan 2020 03:56:48 -0800 (PST) X-Received: by 2002:a25:618a:: with SMTP id v132mr19407648ybb.95.1580299008287; Wed, 29 Jan 2020 03:56:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!g89no10598246qtd.0!news-out.google.com!w29ni938qtc.0!nntp.google.com!g89no10598242qtd.0!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Jan 2020 03:56:47 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:60b3:dc83:f48:6ac2; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:60b3:dc83:f48:6ac2 References: <39a6ef79-424e-49cf-b723-a3e0b6a20f31@googlegroups.com> <3f18b468-75b0-40a7-830b-6fec4480de2b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7621ac73-23df-4755-a198-5b26b6bb33c4@googlegroups.com> Subject: Re: Array of std_logic_vector From: KJ Injection-Date: Wed, 29 Jan 2020 11:56:48 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 39 Xref: reader01.eternal-september.org comp.lang.vhdl:9631 On Tuesday, January 28, 2020 at 10:10:39 PM UTC-5, digita...@gmail.com wrot= e: > I didn=E2=80=99t paste all of the code but there is another array of ADC = data: type ADC_REG_TYPE is array (0 to 20) of std_logic_vector(31 downto 0= ). In order to assign this ADC data to my stream array I take it I would h= ave to repackage it like: Signal adc_data : PACKET_REG_TYPE(0 to 83). >=20 > Then I could assign the whole thing at once: > stream_1_tx_int(11 to 94) <=3D adc_data; >=20 Yes, but since ADC data is an array of 32 bit things, you would need to man= ually convert between 32 bit words and 8 bit ones. However, to do this con= version you could build on what you have. type PACKET_REG_TYPE32 is array(natural range <>) of std_logic_vector(31 do= wnto 0); Then create a function that converts a 32 bit word into an array of four by= tes. The declaration for this is shown below, you would write the body of = the function. function ToPacketRegType(Inp: std_logic_vector(31 downto 0)) return PACKET_= REG_TYPE; Then create a function that converts PACKET_REG_TYPE32 to PACKET_REG_TYPE b= y iterating and calling the function ToPacketRegType. Again, you would wri= te the body of the function. function ToPacketRegType(Inp: PACKET_REG_TYPE32) return PACKET_REG_TYPE; Now that you have these to helper functions you can convert directly from y= our ADC data array like this AdcDataPacketRegType <=3D ToPacketRegType(AdcData); Alternatively, you would dispense with AdcDataPacketRegType and simply assi= gn ToPacketRegType(AdcData) into the appropriate range in your packet. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:14 2024 X-Received: by 2002:ae9:c317:: with SMTP id n23mr8839191qkg.356.1580443151692; Thu, 30 Jan 2020 19:59:11 -0800 (PST) X-Received: by 2002:a25:868e:: with SMTP id z14mr6662335ybk.413.1580443151425; Thu, 30 Jan 2020 19:59:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 30 Jan 2020 19:59:11 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=14.139.183.221; posting-account=ELp5SgoAAABoisgkAl0GoNIS2IZ5Ghtl NNTP-Posting-Host: 14.139.183.221 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8771ee7d-f4bb-483e-9327-1599fe432613@googlegroups.com> Subject: needs help with vhdl coding From: sweetymalutty@gmail.com Injection-Date: Fri, 31 Jan 2020 03:59:11 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9632 I have created a FIFO for 32bit registers(holds 16 registers).Now I need to= call the first 32 bit register from the FIFO to my main code and check the= LSB bit position of the 32 bit register to see if it is set to '1'. Iam no= t sure how this can be done. Can anyone please help me with this? I would a= lso like to know is it possible to use this FIFO as a package? Please help = me... From newsfish@newsfish Thu Aug 1 00:45:14 2024 X-Received: by 2002:aed:2a87:: with SMTP id t7mr9064685qtd.384.1580447354255; Thu, 30 Jan 2020 21:09:14 -0800 (PST) X-Received: by 2002:a25:e696:: with SMTP id d144mr7001614ybh.316.1580447354067; Thu, 30 Jan 2020 21:09:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 30 Jan 2020 21:09:13 -0800 (PST) In-Reply-To: <8771ee7d-f4bb-483e-9327-1599fe432613@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.10; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.10 References: <8771ee7d-f4bb-483e-9327-1599fe432613@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <230d9afa-382a-4d1d-9cd8-46ee06c8a9a1@googlegroups.com> Subject: Re: needs help with vhdl coding From: Rick C Injection-Date: Fri, 31 Jan 2020 05:09:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9633 On Thursday, January 30, 2020 at 10:59:13 PM UTC-5, sweety...@gmail.com wro= te: > I have created a FIFO for 32bit registers(holds 16 registers).Now I need = to call the first 32 bit register from the FIFO to my main code and check t= he LSB bit position of the 32 bit register to see if it is set to '1'. Iam = not sure how this can be done. Can anyone please help me with this? I would= also like to know is it possible to use this FIFO as a package? Please hel= p me... It would help tremendously if you pared your code down to the essential par= t of accessing the register file and showed it to us. =20 Sectioning your code is a good habit to develop. Write it in small blocks = that can be thought about separately and seen separately. =20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:14 2024 X-Received: by 2002:ac8:42d7:: with SMTP id g23mr9648516qtm.206.1580463434202; Fri, 31 Jan 2020 01:37:14 -0800 (PST) X-Received: by 2002:a81:f00d:: with SMTP id p13mr6926794ywm.275.1580463434004; Fri, 31 Jan 2020 01:37:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 31 Jan 2020 01:37:13 -0800 (PST) In-Reply-To: <8771ee7d-f4bb-483e-9327-1599fe432613@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <8771ee7d-f4bb-483e-9327-1599fe432613@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <90e918d8-9df4-4ea0-9d6e-14a048f4e8e3@googlegroups.com> Subject: Re: needs help with vhdl coding From: Thomas Stanka Injection-Date: Fri, 31 Jan 2020 09:37:14 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9634 Am Freitag, 31. Januar 2020 04:59:13 UTC+1 schrieb sweety...@gmail.com: > I have created a FIFO for 32bit registers(holds 16 registers).Now I need to call the first 32 bit register from the FIFO to my main code and check the LSB bit You created a Fifo. Now imagine you would read out the first entry of the fifo and check if bit 0 of the first entry is equal to '1'. As far as I understand that is your task, should be easy for someone creting a Fifo. bye tHomas From newsfish@newsfish Thu Aug 1 00:45:15 2024 X-Received: by 2002:ac8:7b45:: with SMTP id m5mr22095392qtu.360.1580691208023; Sun, 02 Feb 2020 16:53:28 -0800 (PST) X-Received: by 2002:a0d:f783:: with SMTP id h125mr16828448ywf.196.1580691207873; Sun, 02 Feb 2020 16:53:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 2 Feb 2020 16:53:27 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=188.29.164.188; posting-account=4Wh9agoAAAC-3AFSSi8aeATF4VsVRtML NNTP-Posting-Host: 188.29.164.188 References: <032d467e-aa54-46bd-857a-6015a969b455@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <533a1db6-d952-494c-acb1-a0fd36f290f5@googlegroups.com> Subject: Re: Squaring of a binary number From: favouriteangels45@gmail.com Injection-Date: Mon, 03 Feb 2020 00:53:28 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9635 There has to be something for there to be nothing From newsfish@newsfish Thu Aug 1 00:45:15 2024 X-Received: by 2002:a05:620a:a54:: with SMTP id j20mr2058707qka.92.1580988539441; Thu, 06 Feb 2020 03:28:59 -0800 (PST) X-Received: by 2002:a25:d9d4:: with SMTP id q203mr2661241ybg.274.1580988539177; Thu, 06 Feb 2020 03:28:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Feb 2020 03:28:58 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=14.139.183.221; posting-account=ELp5SgoAAABoisgkAl0GoNIS2IZ5Ghtl NNTP-Posting-Host: 14.139.183.221 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: vhdl code not working From: sweetymalutty@gmail.com Injection-Date: Thu, 06 Feb 2020 11:28:59 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9636 I have created a register file that holds 4 32 bit registers.Now i would l= ike to check whether the first 3 bits of the first register(CTL) is 1 and t= hen check if the 1st bit of 2nd register is 1 .If so the BC_en bit should g= o high.....which is not happening....can anyone please see the code below a= nd help me?=20 ...........................................................................= . library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std_UNSIGNED.ALL; =20 entity cntrregFile is port ( =20 input : in std_logic_vector (31 downto 0); writeEnable : in std_logic; clk : in std_logic; readregSel : in std_logic_vector (2 downto 0); writeregSel : in std_logic_vector (2 downto 0); readEnable : in std_logic; output : out std_logic_vector (31 downto 0); bc_en : out std_logic ); end cntrregFile; architecture behavioral of cntrregFile is type registerFile is array(0 to 3) of std_logic_vector(31 downto 0); signal registers : registerFile; signal CTL : std_logic_vector(31 downto 0); signal BC_CTL : std_logic_vector(31 downto 0); signal BC_FIFO_CTL : std_logic_vector(31 downto 0); signal ENCDEC_CTL : std_logic_vector(31 downto 0); begin =20 process (clk,writeregSel,writeEnable,readregSel,readEnable) is begin if (rising_edge(clk) and writeEnable=3D'1' ) then =20 if ( writeregSel=3D"000") then registers (to_integer(writeregSel)) <=3D input ; elsif ( writeregSel=3D"001") then registers (to_integer(writeregSel)) <=3D input ; elsif ( writeregSel=3D"010") then registers (to_integer(writeregSel)) <=3D input ; elsif ( writeregSel=3D"011") then registers (to_integer(writeregSel)) <=3D input ; =20 end if; elsif (rising_edge(clk) and readEnable=3D'1') then if (readregSel=3D"000") then CTL <=3D registers(to_integer(readregSel)); output <=3D CTL; =20 elsif(readregSel=3D"001") then BC_CTL <=3D registers(to_integer(readregSel)); output<=3D BC_CTL; elsif(readregSel=3D"010") then BC_FIFO_CTL <=3D registers(to_integer(readregSel)); output<=3D BC_FIFO_CTL; elsif(readregSel=3D"011") then ENCDEC_CTL <=3D registers(to_integer(readregSel)); output<=3DENCDEC_CTL ; =20 end if; end if; end process; process (clk,CTL,BC_CTL) is begin if (CTL(0)=3D '1') and (CTL(1)=3D'1') and=20 (CTL(2)=3D'0') and (CTL(3)=3D'0')then if (BC_CTL(0) =3D'1') then bc_en<=3D '1'; else bc_en<=3D'0'; end if; end if; end process; end behavioral; From newsfish@newsfish Thu Aug 1 00:45:15 2024 X-Received: by 2002:a0c:c389:: with SMTP id o9mr3275069qvi.232.1581008668366; Thu, 06 Feb 2020 09:04:28 -0800 (PST) X-Received: by 2002:a81:6c55:: with SMTP id h82mr4002564ywc.311.1581008668143; Thu, 06 Feb 2020 09:04:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Feb 2020 09:04:27 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.10; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.10 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <222c11ee-08a3-44a3-9901-b15bb5e8b781@googlegroups.com> Subject: Re: vhdl code not working From: Rick C Injection-Date: Thu, 06 Feb 2020 17:04:28 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 7310 X-Received-Body-CRC: 3728049550 Xref: reader01.eternal-september.org comp.lang.vhdl:9637 On Thursday, February 6, 2020 at 6:29:01 AM UTC-5, sweety...@gmail.com wrot= e: > I have created a register file that holds 4 32 bit registers.Now i would= like to check whether the first 3 bits of the first register(CTL) is 1 and= then check if the 1st bit of 2nd register is 1 .If so the BC_en bit should= go high.....which is not happening....can anyone please see the code below= and help me?=20 >=20 > .........................................................................= ... > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > use ieee.numeric_std_UNSIGNED.ALL; > =20 > entity cntrregFile is > port > ( =20 > input : in std_logic_vector (31 downto 0); > writeEnable : in std_logic; > clk : in std_logic; > readregSel : in std_logic_vector (2 downto 0); > writeregSel : in std_logic_vector (2 downto 0); > readEnable : in std_logic; > output : out std_logic_vector (31 downto 0); > bc_en : out std_logic > ); > end cntrregFile; > architecture behavioral of cntrregFile is > type registerFile is array(0 to 3) of std_logic_vector(31 downto 0); > signal registers : registerFile; > signal CTL : std_logic_vector(31 downto 0); > signal BC_CTL : std_logic_vector(31 downto 0); > signal BC_FIFO_CTL : std_logic_vector(31 downto 0); > signal ENCDEC_CTL : std_logic_vector(31 downto 0); >=20 > begin > =20 > process (clk,writeregSel,writeEnable,readregSel,readEnable) is >=20 > begin >=20 > if (rising_edge(clk) and writeEnable=3D'1' ) then > =20 > if ( writeregSel=3D"000") then > registers (to_integer(writeregSel)) <=3D input ; > elsif ( writeregSel=3D"001") then > registers (to_integer(writeregSel)) <=3D input ; > elsif ( writeregSel=3D"010") then > registers (to_integer(writeregSel)) <=3D input ; > elsif ( writeregSel=3D"011") then > registers (to_integer(writeregSel)) <=3D input ; > =20 > end if; > elsif (rising_edge(clk) and readEnable=3D'1') then > if (readregSel=3D"000") then > CTL <=3D registers(to_integer(readregSel)); > output <=3D CTL; > =20 > elsif(readregSel=3D"001") then > BC_CTL <=3D registers(to_integer(readregSel)); > output<=3D BC_CTL; > elsif(readregSel=3D"010") then > BC_FIFO_CTL <=3D registers(to_integer(readregSel)); > output<=3D BC_FIFO_CTL; > elsif(readregSel=3D"011") then > ENCDEC_CTL <=3D registers(to_integer(readregSel)); > output<=3DENCDEC_CTL ; > =20 > end if; > end if; > end process; >=20 > process (clk,CTL,BC_CTL) is >=20 > begin >=20 > if (CTL(0)=3D '1') and (CTL(1)=3D'1') and=20 > (CTL(2)=3D'0') and (CTL(3)=3D'0')then > if (BC_CTL(0) =3D'1') then > bc_en<=3D '1'; > else > bc_en<=3D'0'; > end if; > end if; >=20 > end process; > end behavioral; A couple of small issues that aren't your problem. A clocked process only = needs the signals in the sensitivity list that are prerequisites to any of = the outputs changing. So it should include the clock signal and if you had= an async input such as reset, that too. But only if the reset or any othe= r signal is asynchronous. So clean up your sensitivity list and your simul= ations will run faster.=20 Then by convention there is an outer conditional to detect the rising edge = of the clock and all other logic is inside this structure as separate condi= tionals. I can't say this causes any problems, but I've never seen anyone = do it in two separate conditionals so I can't say for sure. But it will b= e easier to get help if your code has the same basic structure as everyone = else's.=20 Your use of IEEE.STD_LOGIC_UNSIGNED along with ieee.numeric_std_UNSIGNED ha= s several problems. The former is deprecated and you should stop using it.= The latter is not even a thing... the name is ieee.numeric_std. It inclu= des both signed and unsigned types. =20 Another style issue which may be causing a failure (not sure) is with writi= ng the registers. You are using a conditional to decode the register selec= t, then you are addressing the register directly by turning writeregSel int= o an integer. You only need to do one of those things, not both. =20 There is a mismatch with the number of registers (4) and the possible regis= ters selected by the select lines (8 or 3 depending on whether or not they = are 1-hot). So which is right?=20 Do you realize that when reading you have a register delay between the read= enable and the register value being saved in CTL, BC_CTL, BC_FIFO_CTL and = ENCDEC_CTL? Then you add another register delay before assigning those val= ues to output? I'm not saying this is wrong, I just want to make sure you = have it right from the assignment.=20 The register delays can be important to your application and in particular = to the decoding. Right now the decode is on the registers CTL and BC_CTL w= hile you are also storing the data in the register file "registers". regis= ters is updated when you write the register file. CTL and BC_CTL are only = written when you read the register file. =20 So I think you have many errors in your code that are logical errors. I su= ggest that you try drawing a block diagram of the logic you would use to im= plement this design. Show the registers, data flow and decodes. Then you = can write code to describe that structure and it should be a closer match.= =20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: vhdl code not working Date: Tue, 11 Feb 2020 10:27:51 -0600 Organization: A noiseless patient Spider Lines: 203 Message-ID: References: <222c11ee-08a3-44a3-9901-b15bb5e8b781@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 11 Feb 2020 16:27:54 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="50bd8d40527820042e4a3d68b6f569c4"; logging-data="28694"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/vOYf8QmcNWnBpSqCQ0BtNjs/isPBk2iE=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:PSjzyEsbDQWeVJNNADntuUEDgP8= In-Reply-To: <222c11ee-08a3-44a3-9901-b15bb5e8b781@googlegroups.com> Xref: reader01.eternal-september.org comp.lang.vhdl:9638 On 2020-02-06 11:04, Rick C wrote: > On Thursday, February 6, 2020 at 6:29:01 AM UTC-5, sweety...@gmail.com wrote: >> I have created a register file that holds 4 32 bit registers.Now i would like to check whether the first 3 bits of the first register(CTL) is 1 and then check if the 1st bit of 2nd register is 1 .If so the BC_en bit should go high.....which is not happening....can anyone please see the code below and help me? >> >> ............................................................................ >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> use IEEE.STD_LOGIC_ARITH.ALL; >> use IEEE.STD_LOGIC_UNSIGNED.ALL; >> use ieee.numeric_std_UNSIGNED.ALL; >> >> entity cntrregFile is >> port >> ( >> input : in std_logic_vector (31 downto 0); >> writeEnable : in std_logic; >> clk : in std_logic; >> readregSel : in std_logic_vector (2 downto 0); >> writeregSel : in std_logic_vector (2 downto 0); >> readEnable : in std_logic; >> output : out std_logic_vector (31 downto 0); >> bc_en : out std_logic >> ); >> end cntrregFile; >> architecture behavioral of cntrregFile is >> type registerFile is array(0 to 3) of std_logic_vector(31 downto 0); >> signal registers : registerFile; >> signal CTL : std_logic_vector(31 downto 0); >> signal BC_CTL : std_logic_vector(31 downto 0); >> signal BC_FIFO_CTL : std_logic_vector(31 downto 0); >> signal ENCDEC_CTL : std_logic_vector(31 downto 0); >> >> begin >> >> process (clk,writeregSel,writeEnable,readregSel,readEnable) is >> >> begin >> >> if (rising_edge(clk) and writeEnable='1' ) then >> >> if ( writeregSel="000") then >> registers (to_integer(writeregSel)) <= input ; >> elsif ( writeregSel="001") then >> registers (to_integer(writeregSel)) <= input ; >> elsif ( writeregSel="010") then >> registers (to_integer(writeregSel)) <= input ; >> elsif ( writeregSel="011") then >> registers (to_integer(writeregSel)) <= input ; >> >> end if; >> elsif (rising_edge(clk) and readEnable='1') then >> if (readregSel="000") then >> CTL <= registers(to_integer(readregSel)); >> output <= CTL; >> >> elsif(readregSel="001") then >> BC_CTL <= registers(to_integer(readregSel)); >> output<= BC_CTL; >> elsif(readregSel="010") then >> BC_FIFO_CTL <= registers(to_integer(readregSel)); >> output<= BC_FIFO_CTL; >> elsif(readregSel="011") then >> ENCDEC_CTL <= registers(to_integer(readregSel)); >> output<=ENCDEC_CTL ; >> >> end if; >> end if; >> end process; >> >> process (clk,CTL,BC_CTL) is >> >> begin >> >> if (CTL(0)= '1') and (CTL(1)='1') and >> (CTL(2)='0') and (CTL(3)='0')then >> if (BC_CTL(0) ='1') then >> bc_en<= '1'; >> else >> bc_en<='0'; >> end if; >> end if; >> >> end process; >> end behavioral; > > A couple of small issues that aren't your problem. A clocked process only needs the signals in the sensitivity list that are prerequisites to any of the outputs changing. So it should include the clock signal and if you had an async input such as reset, that too. But only if the reset or any other signal is asynchronous. So clean up your sensitivity list and your simulations will run faster. > > Then by convention there is an outer conditional to detect the rising edge of the clock and all other logic is inside this structure as separate conditionals. I can't say this causes any problems, but I've never seen anyone do it in two separate conditionals so I can't say for sure. But it will be easier to get help if your code has the same basic structure as everyone else's. > > Your use of IEEE.STD_LOGIC_UNSIGNED along with ieee.numeric_std_UNSIGNED has several problems. The former is deprecated and you should stop using it. The latter is not even a thing... the name is ieee.numeric_std. It includes both signed and unsigned types. > > > Another style issue which may be causing a failure (not sure) is with writing the registers. You are using a conditional to decode the register select, then you are addressing the register directly by turning writeregSel into an integer. You only need to do one of those things, not both. > > There is a mismatch with the number of registers (4) and the possible registers selected by the select lines (8 or 3 depending on whether or not they are 1-hot). So which is right? > > Do you realize that when reading you have a register delay between the read enable and the register value being saved in CTL, BC_CTL, BC_FIFO_CTL and ENCDEC_CTL? Then you add another register delay before assigning those values to output? I'm not saying this is wrong, I just want to make sure you have it right from the assignment. > > The register delays can be important to your application and in particular to the decoding. Right now the decode is on the registers CTL and BC_CTL while you are also storing the data in the register file "registers". registers is updated when you write the register file. CTL and BC_CTL are only written when you read the register file. > > So I think you have many errors in your code that are logical errors. I suggest that you try drawing a block diagram of the logic you would use to implement this design. Show the registers, data flow and decodes. Then you can write code to describe that structure and it should be a closer match. > I'll echo Rick's comments. A clocked process should contain only the clock signal in the sensitivity list, and possibly also the reset signal if you are using an asynchronous reset. Your second process shouldn't contain the clk signal because it is not a clocked process. Forget the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED packages. Those are old, non-standard packages that were developed by Synopsis before IEEE came out with the numberic_std package. VHDL purists will argue that they shouldn't even be in the ieee library, because they were not developed by IEEE, but that is where tool vendors usually put them. Use ieee.numeric_std instead. You need to understand the difference between variable assignments and signal assignments in VHDL. Variable assignments happen immediately, like in common programming languages, before the next statement is executed. Signal assignments do not happen immediately. What they do is put an event into the simulator's event queue to be processed later. For example, let's take a look at two statements from your code: CTL <= registers(to_integer(readregSel)); output <= CTL; What that says is: Put an event into the simulator's event queue to assign the current value of registers(0) to the signal CTL. Put an event into the simulator's event queue to assign the current value of CTL to the signal "output". So CTL and OUTPUT do not necessary get the same value. OUTPUT gets the value that CTL already had BEFORE the assignment CTL <= registers(to_integer(readregSel)); got carried out. Variable assignments in VHDL take place immediately. Variables don't trigger events or other processes. Signals in VHDL hold both a value and time and event information. Signals can trigger other processes. It isn't clear from your code just what you were trying to accomplish, but take a look at the way I recoded it to see if it might be closer to your intentions: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.ALL; entity cntrregFile is port ( input : in std_logic_vector (31 downto 0); writeEnable : in std_logic; clk : in std_logic; readregSel : in std_logic_vector (2 downto 0); writeregSel : in std_logic_vector (2 downto 0); readEnable : in std_logic; output : out std_logic_vector (31 downto 0); bc_en : out std_logic ); end cntrregFile; architecture behavioral of cntrregFile is type registerFile is array(0 to 3) of std_logic_vector(31 downto 0); signal registers : registerFile; signal CTL : std_logic_vector(31 downto 0); signal BC_CTL : std_logic_vector(31 downto 0); signal BC_FIFO_CTL : std_logic_vector(31 downto 0); signal ENCDEC_CTL : std_logic_vector(31 downto 0); begin clk_proc: process (clk) is variable reg_addr : integer range 0 to 3; begin if (rising_edge(clk) ) then if writeEnable='1' and writeregSel(2)='0' then reg_addr := to_integer(writeregSel(1 downto 0)); registers(reg_addr) <= input ; end if; if readEnable='1' then if (readregSel="000") then CTL <= registers(0); end if; if (readregSel="001") then BC_CTL <= registers(1); end if; if (readregSel="010") then BC_FIFO_CTL <= registers(2); end if; if (readregSel="011") then ENCDEC_CTL <= registers(3); end if; if readregSel(2)='0' then reg_addr := to_integer(readregSel(1 downto 0)); output <= registers(reg_addr); end if; end if; end if; end process; bc_en <= CTL(0) and CTL(1) and not CTL(2) and BC_CTL(0); end behavioral; Charles Bailey From newsfish@newsfish Thu Aug 1 00:45:16 2024 X-Received: by 2002:ac8:4351:: with SMTP id a17mr7632791qtn.133.1581520371765; Wed, 12 Feb 2020 07:12:51 -0800 (PST) X-Received: by 2002:a81:30a:: with SMTP id 10mr10213962ywd.162.1581520371565; Wed, 12 Feb 2020 07:12:51 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 Feb 2020 07:12:51 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.10; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.10 References: <222c11ee-08a3-44a3-9901-b15bb5e8b781@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: vhdl code not working From: Rick C Injection-Date: Wed, 12 Feb 2020 15:12:51 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9639 Good comments all. I just want to post my library inclusion code as anothe= r example. I typically use the IEEE standard libraries as well as some of = my own project oriented definitions. =20 library ieee; use ieee.std_logic_1164.all; Use ieee.numeric_std.all; Library Common; Use Common.Stuff.all; Use Common.conversions.all; Library Hardware; Use Hardware.IRIG_Defs.all; The Common library has my own code I use on every project, hence the name "= Common". The last library is a project specific library mostly with consta= nts for hardware registers, but also with functions that handle simple data= conversions, bit extractions and etc. =20 It's very useful to have your own libraries that you can easily port betwee= n projects. The only problem with this is that every tool seems to expect = you to put your code in a directory structure they create for your project = rather than putting all their stuff in a sub-directory under yours to keep = it out of sight, out of mind. So these library files often get copied arou= nd rather than trying to point back to another file outside of the project = directory.=20 I believe I've tried to talk to the vendors about that, but they are so ent= renched in their ways changing anything so simple as the location of the so= urce code in the directory structure is a virtual movement of the mountain.= So rather than being able to simply delete their directory structure when= I want to back up and archive my code, I have to manually dig in and delet= e intertwined files. =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:16 2024 X-Received: by 2002:ad4:4e50:: with SMTP id eb16mr22060786qvb.34.1581561916340; Wed, 12 Feb 2020 18:45:16 -0800 (PST) X-Received: by 2002:a25:5f0b:: with SMTP id t11mr13473485ybb.196.1581561915999; Wed, 12 Feb 2020 18:45:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer02.am4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 Feb 2020 18:45:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:1460:a1ab:2ee0:e2a0; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:1460:a1ab:2ee0:e2a0 References: <222c11ee-08a3-44a3-9901-b15bb5e8b781@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <944c72e1-c832-427e-8df3-ca9b730d28cd@googlegroups.com> Subject: Re: vhdl code not working From: KJ Injection-Date: Thu, 13 Feb 2020 02:45:16 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2388 X-Received-Body-CRC: 2716414200 Xref: reader01.eternal-september.org comp.lang.vhdl:9640 On Wednesday, February 12, 2020 at 10:13:33 AM UTC-5, Rick C wrote: >=20 > It's very useful to have your own libraries that you can easily port betw= een projects. The only problem with this is that every tool seems to expec= t you to put your code in a directory structure they create for your projec= t rather than putting all their stuff in a sub-directory under yours to kee= p it out of sight, out of mind. So these library files often get copied ar= ound rather than trying to point back to another file outside of the projec= t directory.=20 If you use version control such as Subversion and of course many others, th= en the true master copy of the file is inside that version control system, = not in some other folder on your hard drive. Each individual project would= reference the source from version control and place it where the tool is h= appy about it. No need to reference source files that are in some other fo= lder. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: vhdl code not working Date: Thu, 13 Feb 2020 14:01:49 -0800 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <222c11ee-08a3-44a3-9901-b15bb5e8b781@googlegroups.com> <944c72e1-c832-427e-8df3-ca9b730d28cd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 13 Feb 2020 22:01:51 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="4635710699a2c7834e0c8f8a3b47607e"; logging-data="19971"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18HEKXxXuSHkKPigJOPNLGj" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 Cancel-Lock: sha1:OlS8seoYmK6At8BGfH0DP3dgVGw= In-Reply-To: <944c72e1-c832-427e-8df3-ca9b730d28cd@googlegroups.com> Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9641 On 2/12/20 6:45 PM, KJ wrote: > On Wednesday, February 12, 2020 at 10:13:33 AM UTC-5, Rick C wrote: >> >> It's very useful to have your own libraries that you can easily port between projects. The only problem with this is that every tool seems to expect you to put your code in a directory structure they create for your project rather than putting all their stuff in a sub-directory under yours to keep it out of sight, out of mind. So these library files often get copied around rather than trying to point back to another file outside of the project directory. > > If you use version control such as Subversion and of course many others, then the true master copy of the file is inside that version control system, not in some other folder on your hard drive. Each individual project would reference the source from version control and place it where the tool is happy about it. No need to reference source files that are in some other folder. > > Kevin Jennings > Expanding on that, we use Subversion to control all of our projects, and all of our common libraries as well. Projects using those libraries get local checkouts of the library using svn:externals (git has a similar thing called submodules). Then when we make release tags from the project, we insist that it be against a release tagged version of the library too. From newsfish@newsfish Thu Aug 1 00:45:17 2024 X-Received: by 2002:ac8:1206:: with SMTP id x6mr6940817qti.55.1581780230284; Sat, 15 Feb 2020 07:23:50 -0800 (PST) X-Received: by 2002:a81:6c55:: with SMTP id h82mr6486690ywc.311.1581780230057; Sat, 15 Feb 2020 07:23:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 15 Feb 2020 07:23:49 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=188.29.165.9; posting-account=XBQhYAoAAABnCWgBVr6GmAb5Ft7DRK17 NNTP-Posting-Host: 188.29.165.9 References: <7f5888a1-f4e9-4be7-a769-4ffe213014fd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9940d8cd-49e1-4334-ac64-8101bccb69c0@googlegroups.com> Subject: Re: 2 digit dice (random counter 1 - 6) From: dil91255@gmail.com Injection-Date: Sat, 15 Feb 2020 15:23:50 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9642 Can I see the code please From newsfish@newsfish Thu Aug 1 00:45:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Volker Kriszeit Newsgroups: comp.lang.vhdl Subject: Can you look into your design using an assert statement? Date: Mon, 17 Feb 2020 21:34:17 +0100 Organization: A noiseless patient Spider Lines: 24 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: reader02.eternal-september.org; posting-host="4459bf33d0dc2ab9ce8615979295d33e"; logging-data="8776"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+tfUtuqj7CqmyF+l8+pTUE4WB2sQncdTs=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:ARmVHdyHXjFQfHQqso2mKBGQEnI= Xref: reader01.eternal-september.org comp.lang.vhdl:9643 Hi folks, currently I'm developing a small 2-stage RISC processor. For that, I use the ALDEC Active-HDL 10.5 simulator to have a look into the design for debugging purposes. That's working fine, but I want to switch to a VHDL testbench to automate the validations. Is there any possibility in the main testbench to get access to signals deep down in my design when I want to ASSERT some signal? I have asked google but it always responds with some somewhat trivial syntax definitions for the ASSERT statement. Is there something like ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report "readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE in VHDL? Or am I bound to the top level signals and can't look into the design using ASSERT? What would be the proper way to do this in a testbench? I prefer to not alter the design to pass internal signals to the top level to be able to check them. TIA From newsfish@newsfish Thu Aug 1 00:45:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: Can you look into your design using an assert statement? Date: Mon, 17 Feb 2020 21:37:54 -0600 Organization: A noiseless patient Spider Lines: 36 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 18 Feb 2020 03:37:55 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="9a1168ecad811b30bc311ae6c9262627"; logging-data="20151"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+1mGr3VbyhJrYNbLubj5y0s4FOxy19VKg=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:r4lEjeSd0/nkHmhiUi81Mcp656s= In-Reply-To: Xref: reader01.eternal-september.org comp.lang.vhdl:9644 On 2020-02-17 14:34, Volker Kriszeit wrote: > Hi folks, > > currently I'm developing a small 2-stage RISC processor. For that, I use > the ALDEC Active-HDL 10.5 simulator to have a look into the design for > debugging purposes. That's working fine, but I want to switch to a VHDL > testbench to automate the validations. > > Is there any possibility in the main testbench to get access to signals > deep down in my design when I want to ASSERT some signal? I have asked > google but it always responds with some somewhat trivial syntax > definitions for the ASSERT statement. > > Is there something like > ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report > "readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE > in VHDL? > > Or am I bound to the top level signals and can't look into the design > using ASSERT? What would be the proper way to do this in a testbench? I > prefer to not alter the design to pass internal signals to the top level > to be able to check them. > > TIA > I think your best best would be to put the ASSERT statement in the VHDL entity/architecture where the signal exists. ASSERT statements are ignored by synthesis tools. I'm not familiar with ALDEC Active-HDL but most commercial simulators have the capability to put a watch on any signal in the design using the simulator's scripting language, such as TCL. You can have simulator take some action, such as printing out a message, when the signal meets some test condition. So, that would be another approach. Charles Bailey From newsfish@newsfish Thu Aug 1 00:45:18 2024 X-Received: by 2002:a0c:a910:: with SMTP id y16mr15982160qva.139.1582015280057; Tue, 18 Feb 2020 00:41:20 -0800 (PST) X-Received: by 2002:a25:3813:: with SMTP id f19mr17369489yba.316.1582015279730; Tue, 18 Feb 2020 00:41:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Feb 2020 00:41:19 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=14.139.183.221; posting-account=ELp5SgoAAABoisgkAl0GoNIS2IZ5Ghtl NNTP-Posting-Host: 14.139.183.221 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5c954e4d-e0b4-4670-b3dc-e258c2ada830@googlegroups.com> Subject: Re: vhdl code not working From: sweetymalutty@gmail.com Injection-Date: Tue, 18 Feb 2020 08:41:20 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9645 Thankyou so much everyone for replying. I've made some changes to my code as you all have suggested and now its working perfectly. From newsfish@newsfish Thu Aug 1 00:45:18 2024 X-Received: by 2002:a05:620a:c91:: with SMTP id q17mr19428192qki.168.1582033754533; Tue, 18 Feb 2020 05:49:14 -0800 (PST) X-Received: by 2002:a81:4b50:: with SMTP id y77mr15764710ywa.258.1582033754336; Tue, 18 Feb 2020 05:49:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Feb 2020 05:49:14 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <139c7db4-8528-4642-bb57-d99936c56a45@googlegroups.com> Subject: Re: Can you look into your design using an assert statement? From: Thomas Stanka Injection-Date: Tue, 18 Feb 2020 13:49:14 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9646 Hello, Am Montag, 17. Februar 2020 21:34:19 UTC+1 schrieb Volker Kriszeit: > Is there something like > ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report > "readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE > in VHDL? VHDL 2008 provides a mechanisms to access hierarchy. This allows something like ALIAS internalReadport << MyProcessor.HazardDetectionUnit.readPortAOp >>; .. ASSERT internalReadport='1'.... Additionally ALDEC has similar to Modelsim a propritary mechanism to access signals inside, see the documentation of ALDEC for details, but be aware that this mechanism is simulator dependend and therefore not valid VHDL. regards, Thomas From newsfish@newsfish Thu Aug 1 00:45:18 2024 X-Received: by 2002:ac8:740f:: with SMTP id p15mr17036860qtq.211.1582040150968; Tue, 18 Feb 2020 07:35:50 -0800 (PST) X-Received: by 2002:a5b:c84:: with SMTP id i4mr19561099ybq.32.1582040150774; Tue, 18 Feb 2020 07:35:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Feb 2020 07:35:50 -0800 (PST) In-Reply-To: <5c954e4d-e0b4-4670-b3dc-e258c2ada830@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.10; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.10 References: <5c954e4d-e0b4-4670-b3dc-e258c2ada830@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13a601db-6e41-453a-a8dc-6f829a04d8b1@googlegroups.com> Subject: Re: vhdl code not working From: Rick C Injection-Date: Tue, 18 Feb 2020 15:35:50 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9647 On Tuesday, February 18, 2020 at 3:41:21 AM UTC-5, sweety...@gmail.com wrote: > Thankyou so much everyone for replying. I've made some changes to my code as you all have suggested and now its working perfectly. If you want some constructive criticism you can post your final code here. I can assure you that working code is not your best goal. There are folks here with lots of experience who can help you write code that is easier to read and easier to debug. -- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Volker Kriszeit Newsgroups: comp.lang.vhdl Subject: Re: Can you look into your design using an assert statement? Date: Tue, 18 Feb 2020 17:24:43 +0100 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: <139c7db4-8528-4642-bb57-d99936c56a45@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: reader02.eternal-september.org; posting-host="17df1fbaafaea06ba7f91c0f93044f8e"; logging-data="15305"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+JrqBFw/fLzXquiCpHBpRHL1IixLt1Gr8=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:xwO9PkPpyeyk4S9alD9y7cLki8I= Xref: reader01.eternal-september.org comp.lang.vhdl:9648 In article <139c7db4-8528-4642-bb57-d99936c56a45@googlegroups.com>, usenet_nospam_valid@stanka-web.de says... > > Hello, > > Am Montag, 17. Februar 2020 21:34:19 UTC+1 schrieb Volker Kriszeit: > > Is there something like > > ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report > > "readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE > > in VHDL? > > VHDL 2008 provides a mechanisms to access hierarchy. This allows something like > > ALIAS internalReadport << MyProcessor.HazardDetectionUnit.readPortAOp >>; > .. > ASSERT internalReadport='1'.... > > > Additionally ALDEC has similar to Modelsim a propritary mechanism to access signals inside, see the documentation of ALDEC for details, but be aware that this mechanism is simulator dependend and therefore not valid VHDL. > > regards, > > Thomas Hello Thomas, thank you for your suggestion! I'm going to try the VHDL-2008 ALIAS statement. Looks good, seems to be exactly what I need. If that doesn't work, I'll dive into the depths of the simulator. regards, Volker From newsfish@newsfish Thu Aug 1 00:45:19 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Volker Kriszeit Newsgroups: comp.lang.vhdl Subject: Re: Can you look into your design using an assert statement? Date: Tue, 18 Feb 2020 17:27:44 +0100 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: reader02.eternal-september.org; posting-host="17df1fbaafaea06ba7f91c0f93044f8e"; logging-data="15305"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+rpQOj550Br0JgEB+70mre5yI7fdRMXiI=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:qp/vnoNE8ni4tkZFVKXY55gjWow= Xref: reader01.eternal-september.org comp.lang.vhdl:9649 In article , logicguy76@gmail.com says... > I think your best best would be to put the ASSERT statement in the VHDL > entity/architecture where the signal exists. ASSERT statements are > ignored by synthesis tools. > > I'm not familiar with ALDEC Active-HDL but most commercial simulators > have the capability to put a watch on any signal in the design using the > simulator's scripting language, such as TCL. You can have simulator > take some action, such as printing out a message, when the signal meets > some test condition. So, that would be another approach. > > Charles Bailey Hi Charles, I'm defintely going to try this, if the suggestion Thomas made (using VHDL-2008 ALIAS statement) doesn't work for me. Thanks & best regards, Volker From newsfish@newsfish Thu Aug 1 00:45:20 2024 X-Received: by 2002:ac8:5154:: with SMTP id h20mr20425569qtn.43.1582073476366; Tue, 18 Feb 2020 16:51:16 -0800 (PST) X-Received: by 2002:a5b:c84:: with SMTP id i4mr21683827ybq.32.1582073476212; Tue, 18 Feb 2020 16:51:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer02.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Feb 2020 16:51:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=71.181.87.199; posting-account=tpu9BAoAAAAZL2gZtrWqYIYAoMw9iVDq NNTP-Posting-Host: 71.181.87.199 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <60c6e063-5e93-4f26-88a6-9d09121979b7@googlegroups.com> Subject: Re: Can you look into your design using an assert statement? From: brimdavis@gmail.com Injection-Date: Wed, 19 Feb 2020 00:51:16 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1992 X-Received-Body-CRC: 3710338710 Xref: reader01.eternal-september.org comp.lang.vhdl:9650 Volker wrote: > > I'm defintely going to try this, if the suggestion Thomas made (using > VHDL-2008 ALIAS statement) doesn't work for me. > Another option for pre-2008 VHDL signal monitoring, without using vendor specific simulator extensions, is to put a copy of the signals needing to be traced into a package, where they can then be driven from the appropriate level of the hierarchy. I used this approach to provide the simulator trace dumps for my own homebrew RISC verification test bench many years ago, code examples here: https://github.com/brimdavis/yard-1/blob/master/hdl/cores/y1a/y1a_probe_pkg.vhd https://github.com/brimdavis/yard-1/blob/master/hdl/cores/y1a/y1a_probe.vhd -Brian From newsfish@newsfish Thu Aug 1 00:45:20 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Volker Kriszeit Newsgroups: comp.lang.vhdl Subject: Re: Can you look into your design using an assert statement? Date: Fri, 21 Feb 2020 21:14:09 +0100 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <60c6e063-5e93-4f26-88a6-9d09121979b7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: reader02.eternal-september.org; posting-host="a86aa146f2935930ab6bad91d753e868"; logging-data="16325"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+d0T5bXzwFj5q31Xz/MnPS0hPyMwKNytk=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:fQm3/9xT9V71p4JHl/feU4Sl4nM= Xref: reader01.eternal-september.org comp.lang.vhdl:9651 In article <60c6e063-5e93-4f26-88a6-9d09121979b7@googlegroups.com>, brimdavis@gmail.com says... > Another option for pre-2008 VHDL signal monitoring, without using vendor specific simulator extensions, is to put a copy of the signals needing to be traced into a package, where they can then be driven from the appropriate level of the hierarchy. > > I used this approach to provide the simulator trace dumps for my own homebrew RISC verification test bench many years ago, code examples here: > > https://github.com/brimdavis/yard-1/blob/master/hdl/cores/y1a/y1a_probe_pkg.vhd > https://github.com/brimdavis/yard-1/blob/master/hdl/cores/y1a/y1a_probe.vhd > > -Brian Thanks, Brian! I'll try this once my design gets bigger. For the time being I decided to use the VHDL-2008 ALIAS statement, as Thomas suggested. This works very well for me. Regards, Volker From newsfish@newsfish Thu Aug 1 00:45:20 2024 X-Received: by 2002:a05:6214:18eb:: with SMTP id ep11mr636375qvb.91.1582660630194; Tue, 25 Feb 2020 11:57:10 -0800 (PST) X-Received: by 2002:a25:b84e:: with SMTP id b14mr1024888ybm.200.1582660630035; Tue, 25 Feb 2020 11:57:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.am4!peer.am4.highwinds-media.com!news.highwinds-media.com!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Feb 2020 11:57:09 -0800 (PST) In-Reply-To: <1f2e1ef.0504060739.597f1af3@posting.google.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=73.92.48.141; posting-account=OM9LjwoAAAARaiSYMVOwOG0Wn9kQcmQB NNTP-Posting-Host: 73.92.48.141 References: <1f2e1ef.0504060739.597f1af3@posting.google.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <701fbe88-9856-4334-9dc1-d33c8ae788df@googlegroups.com> Subject: Re: VHDL to schematic conversion From: historytimes@gmail.com Injection-Date: Tue, 25 Feb 2020 19:57:10 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 8 X-Received-Bytes: 1568 X-Received-Body-CRC: 1625731655 Xref: reader01.eternal-september.org comp.lang.vhdl:9652 On Wednesday, April 6, 2005 at 8:39:19 AM UTC-7, khansa wrote: > Please mention a tool that can accepts VHDL code and converts it into > a circuit schematic(preferably at the register transfer level or gate > level). Does ORCAD have such an option? RTLVision PRO and StarVision PRO can do this. https://edadirect.com/product/rtlvision-pro/ https://edadirect.com/product/starvision-pro/ From newsfish@newsfish Thu Aug 1 00:45:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer03.am4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx38.iad.POSTED!not-for-mail Newsgroups: comp.lang.vhdl X-Mozilla-News-Host: snews://usnews.usenetnow.net:563 From: mag Subject: Open Source Silicon IP Survey User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 17 Message-ID: X-Complaints-To: abuse@usenetnow.net NNTP-Posting-Date: Fri, 28 Feb 2020 18:24:11 UTC Organization: usenetnow - www.usenetnow.net Date: Fri, 28 Feb 2020 10:24:10 -0800 X-Received-Bytes: 1372 X-Received-Body-CRC: 424090427 Xref: reader01.eternal-september.org comp.lang.vhdl:9653 Are you an engineer working on a chip design project that makes use of silicon IP? Have you considered using open source silicon IP but then decided not to move forward and used instead silicon IP from a different source? If so, we would like to better understand your thinking with respect to this decision and what may influence you to use open source silicon IP in the future. If you would like to share your thoughts on this matter, please fill out the survey below: https://www.surveymonkey.com/r/5Q6YDKF Thank you for your time and your input. From newsfish@newsfish Thu Aug 1 00:45:21 2024 X-Received: by 2002:a37:9683:: with SMTP id y125mr4058666qkd.450.1583515032475; Fri, 06 Mar 2020 09:17:12 -0800 (PST) X-Received: by 2002:a5b:9d1:: with SMTP id y17mr4927576ybq.133.1583515032077; Fri, 06 Mar 2020 09:17:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Mar 2020 09:17:11 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2600:1007:b101:4f09:3d10:c874:cbda:265f; posting-account=pibsvgoAAABxhbauGNsxsqT8t-1DSRgF NNTP-Posting-Host: 2600:1007:b101:4f09:3d10:c874:cbda:265f User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> Subject: Std_logic_vector assignment with variable length From: taylor.cj39@gmail.com Injection-Date: Fri, 06 Mar 2020 17:17:12 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 28 Xref: reader01.eternal-september.org comp.lang.vhdl:9654 Hello good people of google, I am trying to assign a certain part of a SLV(std_logic_vector) to another shorter SLV, and forcing the remaining to be '0'. Ex, lets assign the middle 5 bits of big_word to small word. -- Signal big_word :std_logic_vector(10 - 1 downto 0) := (others => '0'); Signal small_word :std_logic_vector(5 - 1 downto 0) := (others => '0'); ... Begin -- I can of course use this, but this is not very elegant for large SLVs Big_word <= "000" & small_word & "00"; --I would like to do something more like: Big_word <= (7 -1 downto 2 => small_word, others => '0'); --The tool I am using (vivado 2018.3) complains about small_word not being of type std_ulogic. Well the word is larger than 1 bit, so that is an issue. -- My constraints are: VHDL '87 Using ieee.std_logic_1164.all Using ieee.numeric_std Make this assignment in 1 line I really appreciate the help CT From newsfish@newsfish Thu Aug 1 00:45:21 2024 X-Received: by 2002:ac8:7cb0:: with SMTP id z16mr4839839qtv.276.1583527709720; Fri, 06 Mar 2020 12:48:29 -0800 (PST) X-Received: by 2002:a0d:fb42:: with SMTP id l63mr6356171ywf.67.1583527709447; Fri, 06 Mar 2020 12:48:29 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Mar 2020 12:48:29 -0800 (PST) In-Reply-To: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> Subject: Re: Std_logic_vector assignment with variable length From: Rick C Injection-Date: Fri, 06 Mar 2020 20:48:29 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9655 On Friday, March 6, 2020 at 12:17:15 PM UTC-5, CT wrote: > Hello good people of google, > > I am trying to assign a certain part of a SLV(std_logic_vector) to another shorter SLV, and forcing the remaining to be '0'. > > Ex, lets assign the middle 5 bits of big_word to small word. > -- > > Signal big_word :std_logic_vector(10 - 1 downto 0) := (others => '0'); > Signal small_word :std_logic_vector(5 - 1 downto 0) := (others => '0'); > > ... > Begin > > -- I can of course use this, but this is not very elegant for large SLVs > Big_word <= "000" & small_word & "00"; > > --I would like to do something more like: > Big_word <= (7 -1 downto 2 => small_word, others => '0'); > --The tool I am using (vivado 2018.3) complains about small_word not being of type std_ulogic. Well the word is larger than 1 bit, so that is an issue. If this is being done in a process you can always do it with two assignments. Big_word <= (others => '0'); Big_word (7 -1 downto 2) <= small_word; -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:22 2024 X-Received: by 2002:a05:620a:8c8:: with SMTP id z8mr5949636qkz.205.1583547419072; Fri, 06 Mar 2020 18:16:59 -0800 (PST) X-Received: by 2002:a25:9882:: with SMTP id l2mr7614786ybo.143.1583547418679; Fri, 06 Mar 2020 18:16:58 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Mar 2020 18:16:58 -0800 (PST) In-Reply-To: <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2600:1007:b121:4be3:6940:1dad:b84:c247; posting-account=pibsvgoAAABxhbauGNsxsqT8t-1DSRgF NNTP-Posting-Host: 2600:1007:b121:4be3:6940:1dad:b84:c247 References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Std_logic_vector assignment with variable length From: CT Injection-Date: Sat, 07 Mar 2020 02:16:59 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9656 Rick, Thanks for the input. I have done this in a process before with the method you mentioned. Do you know of a 1 or 2 lines solution when NOT in a process? CT From newsfish@newsfish Thu Aug 1 00:45:22 2024 X-Received: by 2002:a05:620a:228e:: with SMTP id o14mr5896747qkh.39.1583551028872; Fri, 06 Mar 2020 19:17:08 -0800 (PST) X-Received: by 2002:a25:24d6:: with SMTP id k205mr7687207ybk.77.1583551025537; Fri, 06 Mar 2020 19:17:05 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Mar 2020 19:17:05 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> Subject: Re: Std_logic_vector assignment with variable length From: Rick C Injection-Date: Sat, 07 Mar 2020 03:17:08 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9657 On Friday, March 6, 2020 at 9:17:01 PM UTC-5, CT wrote: > Rick, >=20 > Thanks for the input. >=20 > I have done this in a process before with the method you mentioned. >=20 > Do you know of a 1 or 2 lines solution when NOT in a process? >=20 > CT I would have expected your original solution to have worked. I believe thi= s was only supported once VHDL-2008 came out. Is your tool set for 2008? = Often this has to be enabled since by default tools frequently don't suppor= t these "modern extensions". Or it is possible it is simply not supported.= =20 Oh, wait! I see in your original post you are limited to VHDL '87. So the= re's the rub! =20 Doulos is a great source of info on issues like this. Here is a page talki= ng about the 2008 extensions.=20 https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_eas= e/ Search down the page for "Vectors in aggregates". They explain this was on= ly added in 2008. What tool are you using? I would be hard pressed to use= a tool that is so out of sync with the real world. =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:22 2024 X-Received: by 2002:ac8:5452:: with SMTP id d18mr7803083qtq.43.1583592981891; Sat, 07 Mar 2020 06:56:21 -0800 (PST) X-Received: by 2002:a25:ba8c:: with SMTP id s12mr9393750ybg.144.1583592981509; Sat, 07 Mar 2020 06:56:21 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Mar 2020 06:56:21 -0800 (PST) In-Reply-To: <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:40a:8301:1640:9cc4:1a86:2a32:54fc; posting-account=pibsvgoAAABxhbauGNsxsqT8t-1DSRgF NNTP-Posting-Host: 2601:40a:8301:1640:9cc4:1a86:2a32:54fc References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> Subject: Re: Std_logic_vector assignment with variable length From: CT Injection-Date: Sat, 07 Mar 2020 14:56:21 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9658 Rick, I am using vivado 2018.3. I believe it is defaulted to VHDL 87. I will look= into upgrading to 08. I'm still green here, and wanted to write my design = in a way that could be used in as many places as possible. VHDL 08 is suppo= rted most everywhere you say? I'll have to do some reading up on this. That link is a great resource, I will keep that in mind. Thanks again CT From newsfish@newsfish Thu Aug 1 00:45:23 2024 X-Received: by 2002:a37:a6cf:: with SMTP id p198mr8400123qke.298.1583603167080; Sat, 07 Mar 2020 09:46:07 -0800 (PST) X-Received: by 2002:a25:24d6:: with SMTP id k205mr10580865ybk.77.1583603166810; Sat, 07 Mar 2020 09:46:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Mar 2020 09:46:06 -0800 (PST) In-Reply-To: <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d1e7c58-0ec0-41dc-9ec2-950da1418a2e@googlegroups.com> Subject: Re: Std_logic_vector assignment with variable length From: Rick C Injection-Date: Sat, 07 Mar 2020 17:46:07 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9659 On Saturday, March 7, 2020 at 9:56:24 AM UTC-5, CT wrote: > Rick, >=20 > I am using vivado 2018.3. I believe it is defaulted to VHDL 87. I will lo= ok into upgrading to 08. I'm still green here, and wanted to write my desig= n in a way that could be used in as many places as possible. VHDL 08 is sup= ported most everywhere you say? I'll have to do some reading up on this. >=20 > That link is a great resource, I will keep that in mind. >=20 > Thanks again >=20 > CT https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug901-= vivado-synthesis.pdf Chapter 5, page 177. =20 https://www.xilinx.com/support/answers/62005.html --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:23 2024 X-Received: by 2002:ae9:c003:: with SMTP id u3mr17083896qkk.337.1583789942019; Mon, 09 Mar 2020 14:39:02 -0700 (PDT) X-Received: by 2002:a25:ba8c:: with SMTP id s12mr19813160ybg.144.1583789941650; Mon, 09 Mar 2020 14:39:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Mar 2020 14:39:01 -0700 (PDT) In-Reply-To: <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:7daf:8f8f:fa30:1642; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:7daf:8f8f:fa30:1642 References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Std_logic_vector assignment with variable length From: Rick C Injection-Date: Mon, 09 Mar 2020 21:39:02 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9660 On Saturday, March 7, 2020 at 9:56:24 AM UTC-5, CT wrote: > Rick, >=20 > I am using vivado 2018.3. I believe it is defaulted to VHDL 87. I will lo= ok into upgrading to 08. I'm still green here, and wanted to write my desig= n in a way that could be used in as many places as possible. VHDL 08 is sup= ported most everywhere you say? I'll have to do some reading up on this. >=20 > That link is a great resource, I will keep that in mind. >=20 > Thanks again >=20 > CT Do us a favor and report back once you have found a solution to your proble= m. It's nice to learn what you've found out.=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:23 2024 X-Received: by 2002:a05:620a:806:: with SMTP id s6mr3218046qks.235.1583938909934; Wed, 11 Mar 2020 08:01:49 -0700 (PDT) X-Received: by 2002:a25:be86:: with SMTP id i6mr3384901ybk.507.1583938909588; Wed, 11 Mar 2020 08:01:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Mar 2020 08:01:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2600:1007:b118:e155:1031:a0bb:816e:e199; posting-account=pibsvgoAAABxhbauGNsxsqT8t-1DSRgF NNTP-Posting-Host: 2600:1007:b118:e155:1031:a0bb:816e:e199 References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f68da09-c3ef-4dca-8f2a-b5a71c9e677c@googlegroups.com> Subject: Re: Std_logic_vector assignment with variable length From: CT Injection-Date: Wed, 11 Mar 2020 15:01:49 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 6 Xref: reader01.eternal-september.org comp.lang.vhdl:9661 Unfortunately even with vhdl 08 the solution: Big_word <= (7 -1 downto 2 => small_word, others => '0'); Does not work. When this is used, the whole big_word signal is assigned to '0'. I will keep trying with vhdl 08 and report back once ive found a solution From newsfish@newsfish Thu Aug 1 00:45:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Std_logic_vector assignment with variable length Date: Wed, 11 Mar 2020 09:27:15 -0700 Organization: A noiseless patient Spider Lines: 23 Message-ID: References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> <6f68da09-c3ef-4dca-8f2a-b5a71c9e677c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 11 Mar 2020 16:27:16 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="d096b44ae23197d8b0e00d70a54e5d57"; logging-data="21287"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19nH83Q69JHkschwrVfB95t" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 Cancel-Lock: sha1:2DhHg0lmPr3gagbduOzRkcddrkI= In-Reply-To: <6f68da09-c3ef-4dca-8f2a-b5a71c9e677c@googlegroups.com> Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9662 On 3/11/20 8:01 AM, CT wrote: > Unfortunately even with vhdl 08 the solution: > > Big_word <= (7 -1 downto 2 => small_word, others => '0'); > > Does not work. When this is used, the whole big_word signal is assigned to '0'. > > I will keep trying with vhdl 08 and report back once ive found a solution > Slices like that only operate with single bit values. You can write it as a function or procedure though. That way you can do sequential assignment. function pad_right(val:std_logic_vector, len:integer) return std_logic_vector is variable x : std_logic_vector(len-1 downto 0) := (others => '0'); begin x(len-1 downto len-(val'length)) := val; return x; end function pad_right; big_word <= pad_right(small_word, big_word'length); From newsfish@newsfish Thu Aug 1 00:45:24 2024 X-Received: by 2002:a37:85c2:: with SMTP id h185mr3732564qkd.446.1583946801726; Wed, 11 Mar 2020 10:13:21 -0700 (PDT) X-Received: by 2002:a25:6d54:: with SMTP id i81mr3892379ybc.323.1583946801295; Wed, 11 Mar 2020 10:13:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!news.muarf.org!nntpfeed.proxad.net!feeder1-1.proxad.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Mar 2020 10:13:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> <6f68da09-c3ef-4dca-8f2a-b5a71c9e677c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2b221c73-fcdc-4fe8-95af-b805641cc1fc@googlegroups.com> Subject: Re: Std_logic_vector assignment with variable length From: Rick C Injection-Date: Wed, 11 Mar 2020 17:13:21 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9663 On Wednesday, March 11, 2020 at 12:27:19 PM UTC-4, Rob Gaddi wrote: > On 3/11/20 8:01 AM, CT wrote: > > Unfortunately even with vhdl 08 the solution: > >=20 > > Big_word <=3D (7 -1 downto 2 =3D> small_word, others =3D> '0'); > >=20 > > Does not work. When this is used, the whole big_word signal is assigned= to '0'. > >=20 > > I will keep trying with vhdl 08 and report back once ive found a soluti= on > >=20 >=20 > Slices like that only operate with single bit values. Can you explain what you mean by "slices like that"??? Like what? =20 Here is a hard to find example of exactly the slice aggregate operation the= OP is talking about.=20 https://books.google.com/books?id=3DETxLguPMEY0C&pg=3DPA166&lpg=3DPA166&dq= =3DVHDL+slice+in+an+array+aggregate&source=3Dbl&ots=3Dq9wZSq_TB_&sig=3DACfU= 3U3hcaEpAlXpDSw93ilUOjLnmPUIHg&hl=3Den&sa=3DX&ved=3D2ahUKEwiMm9DE75LoAhX1mX= IEHXgcDKEQ6AEwBnoECAgQAQ#v=3Donepage&q=3DVHDL%20slice%20in%20an%20array%20a= ggregate&f=3Dfalse Scroll down to p167. =20 > You can write it as a function or procedure though. That way you can do= =20 > sequential assignment. >=20 > function pad_right(val:std_logic_vector, len:integer) return std_logic_ve= ctor is > variable x : std_logic_vector(len-1 downto 0) :=3D (others =3D> '0'); > begin > x(len-1 downto len-(val'length)) :=3D val; > return x; > end function pad_right; >=20 > big_word <=3D pad_right(small_word, big_word'length); The function suggestion might be the best to get past the issue and get the= work done.=20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:24 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Std_logic_vector assignment with variable length Date: Wed, 11 Mar 2020 12:45:08 -0700 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> <6f68da09-c3ef-4dca-8f2a-b5a71c9e677c@googlegroups.com> <2b221c73-fcdc-4fe8-95af-b805641cc1fc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 11 Mar 2020 19:45:10 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="d096b44ae23197d8b0e00d70a54e5d57"; logging-data="8292"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18GFSosb/dux9kHUo4LBejo" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 Cancel-Lock: sha1:bDViHZ2qIJO4X3MIuP1cp2gK1jc= In-Reply-To: <2b221c73-fcdc-4fe8-95af-b805641cc1fc@googlegroups.com> Content-Language: en-US Xref: reader01.eternal-september.org comp.lang.vhdl:9664 On 3/11/20 10:13 AM, Rick C wrote: > On Wednesday, March 11, 2020 at 12:27:19 PM UTC-4, Rob Gaddi wrote: >> On 3/11/20 8:01 AM, CT wrote: >>> Unfortunately even with vhdl 08 the solution: >>> >>> Big_word <= (7 -1 downto 2 => small_word, others => '0'); >>> >>> Does not work. When this is used, the whole big_word signal is assigned to '0'. >>> >>> I will keep trying with vhdl 08 and report back once ive found a solution >>> >> >> Slices like that only operate with single bit values. > > Can you explain what you mean by "slices like that"??? Like what? > > Here is a hard to find example of exactly the slice aggregate operation the OP is talking about. > > https://books.google.com/books?id=ETxLguPMEY0C&pg=PA166&lpg=PA166&dq=VHDL+slice+in+an+array+aggregate&source=bl&ots=q9wZSq_TB_&sig=ACfU3U3hcaEpAlXpDSw93ilUOjLnmPUIHg&hl=en&sa=X&ved=2ahUKEwiMm9DE75LoAhX1mXIEHXgcDKEQ6AEwBnoECAgQAQ#v=onepage&q=VHDL%20slice%20in%20an%20array%20aggregate&f=false > > Scroll down to p167. > > >> You can write it as a function or procedure though. That way you can do >> sequential assignment. >> >> function pad_right(val:std_logic_vector, len:integer) return std_logic_vector is >> variable x : std_logic_vector(len-1 downto 0) := (others => '0'); >> begin >> x(len-1 downto len-(val'length)) := val; >> return x; >> end function pad_right; >> >> big_word <= pad_right(small_word, big_word'length); > > The function suggestion might be the best to get past the issue and get the work done. > You're right. Per 9.3.3.3 of the 2008 LRM: --- For an element association with a choice that is a discrete range and an expression of the element type of the aggregate, the value of the expression is the element at each index value in the range. For an element association with a choice that is a discrete range and an expression of the type of the aggregate, each element of the value of the expression is the value of the element of the aggregate at the matching index value in the range. --- I don't think I've ever trusted that a tool was going to implement this properly. From newsfish@newsfish Thu Aug 1 00:45:25 2024 X-Received: by 2002:a37:4dc4:: with SMTP id a187mr9275592qkb.436.1584037389877; Thu, 12 Mar 2020 11:23:09 -0700 (PDT) X-Received: by 2002:a25:6d54:: with SMTP id i81mr10277640ybc.323.1584037389467; Thu, 12 Mar 2020 11:23:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Mar 2020 11:23:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:40a:8301:1640:a536:83ec:b70c:5a3a; posting-account=pibsvgoAAABxhbauGNsxsqT8t-1DSRgF NNTP-Posting-Host: 2601:40a:8301:1640:a536:83ec:b70c:5a3a References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> <6f68da09-c3ef-4dca-8f2a-b5a71c9e677c@googlegroups.com> <2b221c73-fcdc-4fe8-95af-b805641cc1fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Std_logic_vector assignment with variable length From: CT Injection-Date: Thu, 12 Mar 2020 18:23:09 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9665 Thanks guys, Youve helped me find a solution that fits my very specific requirements. Se= eing as that you guys are definitely more experienced than I, and it dosen'= t seem like you use the method I am trying to do very frequently, what meth= ods do you prefer for this task (assigning a part of a slv to another slv, = the rest '0')? Using the function Rob used? Or always making this sort of assignment in a = combinational process? CT From newsfish@newsfish Thu Aug 1 00:45:25 2024 X-Received: by 2002:ad4:49b2:: with SMTP id u18mr8802354qvx.102.1584038140485; Thu, 12 Mar 2020 11:35:40 -0700 (PDT) X-Received: by 2002:a5b:9d1:: with SMTP id y17mr10897937ybq.133.1584038140339; Thu, 12 Mar 2020 11:35:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Mar 2020 11:35:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <794fd92c-78fe-4a60-95e3-b7cadb70e83d@googlegroups.com> <28b5a568-4478-4f39-abab-fcd7dbe3fae5@googlegroups.com> <916883cf-5f47-4fbb-968b-12663d8b3570@googlegroups.com> <282f1026-9c08-4847-bdab-63301f883e8b@googlegroups.com> <6f68da09-c3ef-4dca-8f2a-b5a71c9e677c@googlegroups.com> <2b221c73-fcdc-4fe8-95af-b805641cc1fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3a70b005-bd1c-4ab1-b450-31c674b5a4d3@googlegroups.com> Subject: Re: Std_logic_vector assignment with variable length From: Rick C Injection-Date: Thu, 12 Mar 2020 18:35:40 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9666 On Thursday, March 12, 2020 at 2:23:12 PM UTC-4, CT wrote: > Thanks guys, >=20 > Youve helped me find a solution that fits my very specific requirements. = Seeing as that you guys are definitely more experienced than I, and it dose= n't seem like you use the method I am trying to do very frequently, what me= thods do you prefer for this task (assigning a part of a slv to another slv= , the rest '0')? >=20 > Using the function Rob used? Or always making this sort of assignment in = a combinational process? Unless it were part of a conditional, what would be the value of assigning = part of an array permanently to zero? In a conditional this could be used = since the '0' parts might have other values for other input combinations. = But in a simple assignment the '0' parts would always be zero. In that cas= e I likely would have three concurrent assignment statements, one each for = the left and right zeros and one for the variable part.=20 I don't use functions very often unless they are part of a library with pot= ential reuse. Likely I just never developed the habit. It's not like the = modularization isn't useful. =20 --=20 Rick C. ++ Get 1,000 miles of free Supercharging ++ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:25 2024 X-Received: by 2002:a37:a08b:: with SMTP id j133mr2374480qke.265.1584615966266; Thu, 19 Mar 2020 04:06:06 -0700 (PDT) X-Received: by 2002:a25:9985:: with SMTP id p5mr3498824ybo.359.1584615966005; Thu, 19 Mar 2020 04:06:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Mar 2020 04:06:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=62.255.51.195; posting-account=LeHQ-AoAAACmTmp65ZSgTKE01o8Ev31S NNTP-Posting-Host: 62.255.51.195 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <33b312bb-e17d-44d7-95ad-b4513684337c@googlegroups.com> Subject: Re: Memory Initialization Files in Modelsim From: gemmagilmore@hotmail.com Injection-Date: Thu, 19 Mar 2020 11:06:06 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 25 Xref: reader01.eternal-september.org comp.lang.vhdl:9667 On Monday, 19 January 2004 07:39:17 UTC, ALuPin wrote: > Dear Sir or Madam, > > I want to simulate a VHDL design. It includes RAM structures > with .mif files (memory initialization files in QuartusII). > Modelsim seems not to support that kind of files. > So I use .hex files. > In QuartusII they can be included in the MegaWizard- > PlugInManager. > But how do I involve these .hex files when simulating in Modelsim? > Do they have to be compiled additionally to the > design VHDL files or do they have to be linked to in the testbench? > When trying to simulate after compiling the VHDL modules I get > an error message "Fatal error ... altera_mf.vhd ... not found". > > Kind regards > Andres Vazquez > G & D > System Development Fast Forward 15 years..... Following loading of a design in to Modelsim (vsim command), data can be imported into any piece of memory to intialise it (mem load command). Check out the command reference from the the Modelsim/Questa Help menue, it has all the info you need. rgds, GG - VHDL D&V Engineer. From newsfish@newsfish Thu Aug 1 00:45:26 2024 X-Received: by 2002:ac8:4895:: with SMTP id i21mr7398685qtq.55.1584697133837; Fri, 20 Mar 2020 02:38:53 -0700 (PDT) X-Received: by 2002:a25:cf97:: with SMTP id f145mr11331834ybg.106.1584697133524; Fri, 20 Mar 2020 02:38:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2020 02:38:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=195.159.112.170; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 195.159.112.170 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Kickstart your FPGA or ASIC verification with free, open source VHDL interface models (BFMs, VVCs, VIP) From: "espen.tallaksen@bitvis.no" Injection-Date: Fri, 20 Mar 2020 09:38:53 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 48 Xref: reader01.eternal-september.org comp.lang.vhdl:9668 AXI4-lite, AXI4-stream, Avalon MM, Avalon Stream, SBI, SPI, I2C, UART, GPIO= , GMII and RGMII are all free, open source BFMs and VVCs from UVVM. These i= nterface handling procedures and models are all implemented in standard VHD= L and can be used with normal VHDL 2008 compatible simulators like Modelsim= , Questa, Riviera Pro, Active HDL and GHDL. UVVM also has a significant number of support VIP available as free open so= urce. This includes Clock generator, Scoreboard, Queue, Watchdog and Error = Injection - in additon of course to the Utility Library with lots of testbe= nch infrastructure support procedures like check_value, check_stable, await= _value, await_change, random, clock_generator, block_flag, await_barrier, e= tc... UVVM has interface models for all the interfaces above, and more are coming= . So what is an interface model? In UVVM that could be either BFMs (Bus Fun= ctional Models) or VVCs (Verification Components). A BFM in UVVM is just a = set of procedures allowing simple commands like 'axilite_write(
, <= data>)' to be executed from a test sequencer/driver. Calling this procedure= results in a complete axilite access being handled by the procedure, with = all the signal wiggling required to write the given data to the given addre= ss location. These high level commands (or transactions) allow all interfac= es of the DUT to be accessed in a very simple and understandable manner, ma= king it easy even for SW and HW designers to write good tests. The procedur= e will also log the access so you get a good overview of what is happening = during the simulation. A check-procedure like 'axilite_check(
, )' will even give you a mismatch report if the actual data from= the AXI4-lite interface does not match your expected data. The VVCs basically provide the same functionality as the BFM, and a VVC doe= s in fact use a BFM to handle the actual interface access. The main advanta= ge of using VVCs is that this allows us to access any number of interfaces = simultaneously, whereas a procedure is basically blocking the process calli= ng the procedure - until the procedure is finished - after completing the i= nterface access. Other advantages of VVCs are queuing of commands, structur= ed handling of split transactions, better interface control (e.g. between a= ccesses), and the possibility to add more functionality. VVCs are excellent= for reuse. We recommend to use BFMs when you don't need to check simultaneous action o= n multiple interfaces, as using BFMs and the Utility Library is dead simple= (according to feedback). Thus we also recommend anyone starting with UVVM = to first start using the Utility Library and BFMs. For more complex design = challenges, VVCs are recommended. Writing test sequences for VVCs is in fac= t as simple as writing test sequences using BFMs only. You can find links to Gitbub download, UVVM forum and more info under https= ://uvvm.org/ NOTE: We recommnend new users to start with UVVM light, which includes the = utility library and all the BFMs: https://github.com/UVVM/UVVM_Light From newsfish@newsfish Thu Aug 1 00:45:26 2024 X-Received: by 2002:ac8:27f2:: with SMTP id x47mr23163230qtx.302.1584994691890; Mon, 23 Mar 2020 13:18:11 -0700 (PDT) X-Received: by 2002:a25:9005:: with SMTP id s5mr39499408ybl.143.1584994691606; Mon, 23 Mar 2020 13:18:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Mar 2020 13:18:11 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=100.34.101.182; posting-account=h5h-SwoAAADcc_e83pZ0Y3HaAOZ8ZvpK NNTP-Posting-Host: 100.34.101.182 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3b50afa1-a72e-45b8-b692-2d7de31304a4@googlegroups.com> Subject: PipelineC - Autopipeline your VHDL and more! Help wanted! From: Julian Kemmerer Injection-Date: Mon, 23 Mar 2020 20:18:11 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 218 Xref: reader01.eternal-september.org comp.lang.vhdl:9669 Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost hardware description language - A compiler that produces VHDL for specific devices/operating frequencies I am looking for: - anyone who wants to help me develop (Python, VHDL, C) - suggestions on how to make PipelineC more useful/new features - project ideas (heyo open source folks) In the mean time, I am also here to share my most interesting example so fa= r: Using PipelineC with an AWS F1 instance. https://github.com/JulianKemmerer/PipelineC/wiki/AWS-F1-DMA-Example I have made an AMI that you can use to play around with. However, it cannot= be made public; I can only share it with specific AWS accounts, please mes= sage me if interested. I want to share with you why I think PipelineC is particularly powerful: First, it can mostly replace VHDL/Verilog for describing low level, clock b= y clock, hardware control logic. Consider the following generic VHDL: -- Combinatorial logic with a storage register signal the_reg : some_type_t; signal the_wire : some_type_t; process(input, the_reg) is -- inputs sync to clk variable input_variable: some_type_t; variable the_reg_variable : some_type_t; begin input_variable :=3D input; the_reg_variable :=3D the_reg; ... Do work with 'input_variable', 'the_reg_variable' and other variables, functions, etc and it kinda looks like C ... the_wire <=3D the_reg_variable; end process; the_reg <=3D the_wire when rising_edge(clk); output <=3D the_wire; The equivalent PipelineC is some_type_t the_reg; some_type_t some_func_name(some_type_t input) { ... Do work with 'input', 'the_reg' ... and other variables, functions, etc... // Return=3D=3Doutput return the_reg; } Using that functionality I was able write very RTL-esque serialize+deserial= ize logic for the AXI4 interface that the AWS F1 shell logic provides to 'c= ustomer logic' for DMA. The AXI4 is deserialized to a stream of 4096 byte i= nput data chunks that can be processed by a 'work' function. I find that most HLS tools have trouble giving the user this sort of low le= vel control, probably under the assumption that its too low level and not m= eant for software folks to be concerned with. Most hardware description lan= guages are built for exactly this though. Second, PipelineC can replace the most basic feature of other HLS tools: au= to-pipelineing functions: This AWS example sums 1024 floating point values via an N clock cycle pipel= ined binary tree of 1023 floating point adders (soft logic, not hard cores = yet). Below is the PipelineC code: float work(float inputs[1024]) { // All the nodes of the tree in arrays so can be written using loop= s // ~log2(N) levels, max of N values in parallel float nodes[11][1024]; // Unused elements optimize away =20 // Assign inputs to level 0 uint32_t i; for(i=3D0; i<1024; i=3Di+1) { nodes[0][i] =3D inputs[i]; } =20 // Do the computation starting at level 1 uint32_t n_adds; n_adds =3D 1024/2; uint32_t level; for(level=3D1; level<11; level=3Dlevel+1) { =20 // Parallel sums at this level for(i=3D0; i Date: Sat, 28 Mar 20 19:47:56 UTC Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder5.feed.usenet.farm!feeder2.usenet.farm!feed.usenet.farm!news.usenet.farm Xref: reader01.eternal-september.org comp.lang.vhdl:9670 Protect yourself and your loved ones ! KILL the coronavirus right now ! And save LOTS OF CASH New tested, scientificly proven and amazing antivirus against coronavirus using Chloroquine and Colchicine at very low price (33% discount) Satisfaction garanteed or your money back ! http://als0p.atwebpages.com/coronavirus/coronavirus-en.php Protgez-vous et vos proches! TUEZ le coronavirus ds maintenant! Et conomisez BEAUCOUP D'ARGENT Nouvel antivirus test, scientifiquement prouv et tonnant contre le coronavirus utilisant la Chloroquine et la Colchicine trs bas prix (33% de rduction) Satisfaction garantie ou agrent remie ! http://als0p.atwebpages.com/coronavirus/coronavirus-fr.php From newsfish@newsfish Thu Aug 1 00:45:27 2024 X-Ufhash: PWx2fFrBFk1aG3ZCE5FxUXH6RYr8WmuQJiNoKQEo2dF7z5hUt7KbxJDEqT72gcHgYohLvVZsBfG%2F%2FZ4EMsL28F0MmvZhKKZ%2BLrxlgGMM2hz09RogdI6KXMOlPiuqMYIz8WMyMhGDHppdCwdZ0YGHOxVSikliZXvoSCkPUCoCv7apNWmtIG58GnXbpcf7k97cbFDWPOECHW62Md5d%2Fm%2FmmAp1P9is%2F82EaBQYS8vyMxieDvyB0NxpQnUGyvqXU5wV Message-Id: Date: Sat, 18 Apr 20 16:23:10 UTC Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder3.usenet.farm!feeder2.usenet.farm!feed.usenet.farm!news.usenet.farm Organization: Usenet.Farm From: killvirus@coronavirus.com Newsgroups: comp.lang.vhdl Subject: coronavirus COVID-19 Xref: reader01.eternal-september.org comp.lang.vhdl:9671 coronavirus COVID-19 http://www.grex.org/~henced/coronavirus.html From newsfish@newsfish Thu Aug 1 00:45:27 2024 X-Received: by 2002:a05:620a:1f1:: with SMTP id x17mr4578165qkn.330.1587659671853; Thu, 23 Apr 2020 09:34:31 -0700 (PDT) X-Received: by 2002:a5b:48c:: with SMTP id n12mr8582797ybp.133.1587659671649; Thu, 23 Apr 2020 09:34:31 -0700 (PDT) Newsgroups: comp.lang.vhdl Date: Thu, 23 Apr 2020 09:34:31 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=31.31.151.104; posting-account=v4kPxAoAAAAwxTgbyCQJmQN_-O8qB5LL NNTP-Posting-Host: 31.31.151.104 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <62930b82-6fe5-408a-b24f-98ce9af3761b@googlegroups.com> Subject: LA PUTTANACCIA COSTANZA BARRAI DI SONY PICTURES ENTERTAINMENT LONDON , NATA A MILANO IL 1.1.1999, PRENDE CAZZI IN CULO FINANCO DI 40 CENTIMETRI (OLTRE CHE DI CAVALLI E CANI)! From: "LUIGI BISIGNANI - MAI PIU' COL PEDOFILO BERLUSCONI" Injection-Date: Thu, 23 Apr 2020 16:34:31 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!feed.ac-versailles.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Xref: reader01.eternal-september.org comp.lang.vhdl:9672 PRENDE CAZZI IN CULO DI 40 CM, LA TROIA NAZISTA COSTANZA BARRAI, NATA A MIL= ANO IL 1.1.1999 (SONY LONDON)! PRENDE CAZZI DI 35 CM IN CULO: LA PUTTANONA = COSTANZA RACHELE BARRAI, NINFOMANE COCAINOMANE PORNOSTAR NATA A MILANO IL 1= .1.1999. LO FA SIA PRESSO L'UNIVERISTY OF BATH, CHE PRESSO SONY PICTURES EN= TERTAINMENT, CHE IN TANTISSIMI FILM PORNO https://twitter.com/Inculatemimucho https://twitter.com/InculatemiTanto E' NOTA PUTTANA MEGA COCAINOMANE: COSTANZA RACHELE BARRAI, GIA' ABITANTE A = MILANO IN VIA IPPODROMO 105!!!!!!!!!!!! E' SCHIFOSA BALDRACCA SEMPRE SBORRA= TISSIMA DENTRO AL CULO: COSTANZA RACHELE BARRAI! SEMPRE A CIUCCIARE E PREND= ERE CAZZI NELL'ANO, IN FIGA ED IN BOCCA, PRESSO L'INTERNATIONAL SCHOOL MILA= NO!! https://mpak-suse1.akamaized.net/res/usericon/507/icon-21714507-322.jpg E' LURIDA MIGNOTTONA: COSTANZA RACHELE BARRAI, SEMPRE A FARE SESSO DEPRAVAT= O E PERVERTITO, ANCHE MOLTO LESBICO, PRESSO L'UNIVERSITY OF BATH!! https://= dok7xy59qfw9h.cloudfront.net/194/934/091/-469996989-1scbatj-gp4df4lqqhaij0p= /original/file.jpg E' DEPRAVATA BAGASCIA SEMPRE SCOPATA E SBORRATA PROFONDAMENTE DENTRO AL CUL= O: COSTANZA RACHELE BARRAI (SONY PICTURES ENTERTAINMENT). E' SEMPRE LI A PR= ENDERE CAZZI DI OGNI COLORE ( SPECIE NERO, MA NON SOLO), LUNGHI MEZZO METRO= , PER POI FARSI RIEMPIRE L'ANO DI TANTISSIMA SBORRA, LA IMMENSA TROIA COSTA= NZA RACHELE BARRAI, NATA A MILANO IL 1.1.1999 ( https://uk.linkedin.com/in/= costanza-rachele-barrai-3a5b97a7 ) !!!!!!!!! E' NINFOMANE ZOCCOLISSIMA: COS= TANZA RACHELE BARRAI, DA ANNI FACENTE FILM PORNO AMATORIALI A GO GO ( QUI I= N UNA FOTO RIPRENDENTELA PROPRIO A SEGUITO DI UNA MEGA INCULATA EFFETTUATA = AL ZOCCOLONE COSTANZA RACHELE BARRAI STESSO, SODOMIZZAZIONI, D'ALTRONDE, DA= SEMPRE, DA LEI, ADORATISSIME http://www.hotanalxxx.com/contents/videos_scr= eenshots/0/43/400x300/1.jpg ) ! FACCIAMO UN BIS IN DUE OTHER WAY, NOW, PLEA= SE... E' PUTTANONA SEMPRE SCOPATA IN CULO: COSTANZA BARRAI, GIA' ABITANTE A= MILANO IN VIA IPPODROMO 105! https://i1.sndcdn.com/avatars-000123698582-6z= u6yw-t500x500.jpg E' NOTA TROIA MEGA COCAINOMANE: COSTANZA BARRAI, NATA A MILANO IL 1.1.1999!= E' SCHIFOSISSIMA BALDRACCA: COSTANZA RACHELE BARRAI, SEMPRE A CIUCCIARE E = PRENDERE CAZZI IN CULO, FIGA E BOCCA, PRESSO L'INTERNATIONAL SCHOOL MILANO!= ! https://mpak-suse1.akamaized.net/res/usericon/507/icon-21714507-322.jpg E= ' LURIDA MIGNOTTONA: COSTANZA BARRAI, SEMPRE A FARE SESSO DEPRAVATO E PERVE= RTITO, ANCHE MOLTO LESBICO, PRESSO L'UNIVERSITY OF BATH!! https://dok7xy59q= fw9h.cloudfront.net/194/934/091/-469996989-1scbatj-gp4df4lqqhaij0p/original= /file.jpg E' DEPRAVATA BAGASCIA SEMPRE SCOPATA E SBORRATA PROFONDAMENTE DENTRO AL CUL= O: COSTANZA BARRAI (SONY PICTURES ENTERTAINMENT). E' SEMPRE LI A PRENDERE C= AZZI DI OGNI COLORE ( SPECIE NERO, MA NON SOLO), LUNGHI MEZZO METRO, PER PO= I FARSI RIEMPIRE L'ANO DI TANTISSIMA SBORRA, COSTANZA BARRAI NATA A MILANO = IL 1.1.1999 ( https://uk.linkedin.com/in/costanza-rachele-barrai-3a5b97a7 )= !!!!!!!!! E' NINFOMANE ZOCCOLISSIMA: COSTANZA BARRAI, DA ANNI FACENTE FILM= PORNO AMATORIALI A GO GO ( QUI IN UNA FOTO RIPRENDENTELA PROPRIO A SEGUITO= DI UNA MEGA INCULATA EFFETTUATA AL ZOCCOLONE COSTANZA BARRAI STESSO, SODOM= IZZAZIONI, D'ALTRONDE, DA SEMPRE, DA LEI, ADORATISSIME http://www.hotanalxx= x.com/contents/videos_screenshots/0/43/400x300/1.jpg) ! DA MILLENNI SI DICE= " SANGUE MARCIO MAI MENTE". INFATTI, PADRE DI QUESTA MEGA TROIA APPENA DES= CRITTA E' IL NOTO ASSASSINO E RICICLA SOLDI MAFIOSI PAOLO BARRAI NATO A MIL= ANO IL 28.6.65. NOTO IN TUTTO IL MONDO COME "IL PEDOFILO DEL BITCOIN!!!!!!!= !!!!!! https://2.bp.blogspot.com/-TIIF8_LQnCg/XFNdyLDVuqI/AAAAAAAA00o/e68obqilk60R= Qt0a9K-RUDTOxqa4gWbdwCLcBGAs/s1600/Indagato%2Baiuta%2Ble%2BListe%2BCiviche.= jpg http://www.bluerating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un= -ex-promotore-che-ha-violato-gli-obblighi-informativi https://groups.google.com/forum/#!topic/comp.lang.python/aRdLu8PIHXg https://comp.os.vms.narkive.com/4oz5XcuY/il-verme-criminale-paolo-barrai-il= -nuovo-sito-lo-fara-a-san-vittore-trattasi-di-un-mandante-di http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai https://www.tvsvizzera.it/tvs/al-servizio-dei-martino_il-banchiere-della--n= drangheta/44129050 https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ From newsfish@newsfish Thu Aug 1 00:45:27 2024 X-Received: by 2002:ac8:4e86:: with SMTP id 6mr234520qtp.37.1588194434027; Wed, 29 Apr 2020 14:07:14 -0700 (PDT) X-Received: by 2002:a25:4b07:: with SMTP id y7mr393429yba.438.1588194433575; Wed, 29 Apr 2020 14:07:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder5.feed.usenet.farm!feed.usenet.farm!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Apr 2020 14:07:13 -0700 (PDT) In-Reply-To: <382d6281-244f-48d7-a0ae-ff76e69316db@p24g2000yqm.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=172.90.11.147; posting-account=nHW1ZgoAAACAtn_pao5AsqW54-8ISdeW NNTP-Posting-Host: 172.90.11.147 References: <382d6281-244f-48d7-a0ae-ff76e69316db@p24g2000yqm.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: free waveform drawing tool From: gabriel.kudishevich@cwcsilverlake.org Injection-Date: Wed, 29 Apr 2020 21:07:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 13 Xref: reader01.eternal-september.org comp.lang.vhdl:9673 On Friday, February 5, 2010 at 1:28:06 AM UTC-8, Serkan wrote: > Any suggestions for a free waveform drawing tool? >=20 > inkscape or word alike tools take too much time for edition. > some free tools does not let more than 10 clock cycles > some free tools does not let more than 5 or 6 signals >=20 > kind regards > serkan For there to be a website like the Harmonic Editor associated with Electron= ic Music Company only this time to be able to draw and edit a waveform onli= ne. All you need to do to find what I am talking about is to search up: "Ha= rmonic editor Electronic Music" And it will give you it. From newsfish@newsfish Thu Aug 1 00:45:27 2024 X-Received: by 2002:ac8:758a:: with SMTP id s10mr15046581qtq.217.1588868381199; Thu, 07 May 2020 09:19:41 -0700 (PDT) X-Received: by 2002:a25:d609:: with SMTP id n9mr23414092ybg.316.1588868381031; Thu, 07 May 2020 09:19:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 May 2020 09:19:40 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=208.87.233.180; posting-account=HE50FwoAAAAizyX6H2JDICRbcMyZRI8u NNTP-Posting-Host: 208.87.233.180 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: fixed point tools From: zack_sheffield@selinc.com Injection-Date: Thu, 07 May 2020 16:19:41 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9674 Hello, For those of you who do DSP modeling in Python, I've recently released a pa= ckage that supports fixed point arithmetic. The existing open source tools = are lackluster and MATLAB doesn't nicely fit into our simulation/testing wo= rkflow. Just trying to get the word out for a higher adoption rate! Documentation is here: https://fixedpoint.readthedocs.io Gihub repo is here: https://github.com/Schweitzer-Engineering-Laboratories/fixedpoint Compatible with Python 3.8.0 and later. Install from PyPI with pip: pip install fixedpoint From newsfish@newsfish Thu Aug 1 00:45:28 2024 X-Received: by 2002:aed:221c:: with SMTP id n28mr3942533qtc.235.1589456952624; Thu, 14 May 2020 04:49:12 -0700 (PDT) X-Received: by 2002:a25:7406:: with SMTP id p6mr6128710ybc.319.1589456952270; Thu, 14 May 2020 04:49:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 May 2020 04:49:11 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2003:de:2f29:9d00:7c82:5523:45de:f084; posting-account=uAdKBAoAAAAynyp-1im5p3hq6CRPCBsl NNTP-Posting-Host: 2003:de:2f29:9d00:7c82:5523:45de:f084 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> Subject: Newbee in VHDL ... why is this not working? From: Christoph Linden Injection-Date: Thu, 14 May 2020 11:49:12 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 326 Xref: reader01.eternal-september.org comp.lang.vhdl:9675 Hi all, I am getting into VHDL right now and doing the first implementation of some architecutres. For me to learn I follow nand2tetris, that uses its own HDL and translating that for my learning into VHDL. I am at the point of createing a 4bit adder with carry look ahead. I have defined two entities CLA4 and Add4LAC. CLA4 is supposed to calculate the look ahead carry Add4LAC is a 4bit adder with carry that uses CLA4 to calculate the carries of every bit. I also have written a testbench to check it with ModelSim. The result is weird and I do not understand it at all. I have defined in my simulator the following signals: a,b (3 downto 0) --operands cin --carry in sum (3 downto 0) -- output of the sum carry -- carry output. for testing purposes i also added the expected results as csum and ccarry (compare sum and compare carry). If I now run it, with the following input: a <= "0000"; b <= "0000"; cin <= '0'; csum <= "0000"; ccarry <= '0'; The result is not as in csum and ccarry, but instead: # a b cin sum coutcsum ccout # 0000 0000 0 UUUU 0 0000 0 # ** Note: Result Mismatch! # Time: 10 ns Iteration: 0 Instance: /add4lactb # 1111 1111 0 UU00 0 1110 1 # ** Note: Result Mismatch! # Time: 20 ns Iteration: 0 Instance: /add4lactb Can someone please help me to understand what is wrong? I am getting undefined output ... ??? I must have made a generic mistake and have no idea what it is. Even stepping through the code with ModelSim does not give any hint. Here is the code: -- Full 16 bit adder for Hack Computer with look ahead carry -- From the book nand2tetris, translated to vhdl -- by Christoph Linden -- Look ahead carry calculation for 4 bits. -- length to be defined as constant c_WordWidth library ieee; use ieee.std_logic_1164.all; entity CLA4 is port( -- inputs i_g : in std_logic_vector (3 downto 0); i_p : in std_logic_vector (3 downto 0); i_cin : in std_logic; -- outputs o_cout : out std_logic_vector (3 downto 0) ); end entity; architecture cal4 of CLA4 is signal cp0 : std_logic; signal cp0p1 : std_logic; signal cp0p1p2 : std_logic; signal cp0p1p2p3 : std_logic; signal g0p1 : std_logic; signal g0p1p2 : std_logic; signal g0p1p2p3 : std_logic; signal g1p2 : std_logic; signal g1p2p3 : std_logic; signal g2p3 : std_logic; begin process (i_p, i_g, i_cin) is begin -- caculate bit 1 preproduct and carry out 0 -- And(a=p[0],b=cin,out=p0c); -- Or(a=p0c,b=g[0],out=cout[0]); cp0 <= i_p(0) and i_cin; o_cout(0) <= cp0 or i_g(0); -- calculate bit 2 preproduct and carry out 1 -- And3Way(a=cin, b=p[0], c=p[1], out=cp0p1); -- And(a=g[0],b=p[1],out=g0p1); -- Or3Way(a=cp0p1,b=g0p1,c=g[1],out=cout[1]); cp0p1 <= i_cin and i_p(0) and i_p(1); g0p1 <= i_g(0) and i_p(1); o_cout(1) <= cp0p1 or g0p1 or i_g(1); --calculate bit 3 preproducts and carry out 2 -- And4Way(a=cin, b=p[0], c=p[1], d=p[2], out=cp0p1p2); -- And3Way(a=g[0],b=p[1],c=p[2],out=g0p1p2); -- And(a=g[1],b=p[2],out=g1p2); -- Or4Way(a=cp0p1p2,b=g0p1p2,c=g1p2,d=g[2],out=cout[2]); cp0p1p2 <= i_cin and i_p(0) and i_p(1) and i_p(2); g0p1p2 <= i_g(0) and i_p(1) and i_p(2); g1p2 <= i_g(1) and i_p(2); o_cout(2) <= cp0p1p2 or g0p1p2 or g1p2 or i_g(2); --calculate bit 4 preproducts and carry out 4 -- And5Way(a=cin, b=p[0], c=p[1], d=p[2], e=p[3], out=cp0p1p2p3); -- And4Way(a=g[0], b=p[1], c=p[2], d=p[3], out=g0p1p2p3); -- And3Way(a=g[1],b=p[2],c=p[3],out=g1p2p3); -- And(a=g[2],b=p[3],out=g2p3); -- Or5Way(a=cp0p1p2p3,b=g0p1p2p3,c=g1p2p3,d=g2p3, e=g[3],out=cout[3]); cp0p1p2p3 <= i_cin and i_p(0) and i_p(1) and i_p(2) and i_p(3); g0p1p2p3 <= i_g(0) and i_p(1) and i_p(2) and i_p(3); g1p2p3 <= i_g(1) and i_p(2) and i_p(3); g2p3 <= i_g(2) and i_p(3); o_cout(3) <= cp0p1p2p3 and g0p1p2p3 and g1p2p3 and g2p3; end process; end architecture; -- a 4 bit carry look ahead adder. library ieee; use ieee.std_logic_1164.all; entity Add4LAC is port( -- inputs i_a : in std_logic_vector (3 downto 0); i_b : in std_logic_vector (3 downto 0); i_cin : in std_logic; -- outputs o_sum : out std_logic_vector (3 downto 0); o_carry : out std_logic ); end entity; architecture add4lac of Add4LAC is component CLA4 port( -- inputs i_g : in std_logic_vector (3 downto 0); i_p : in std_logic_vector (3 downto 0); i_cin : in std_logic := 'L'; -- outputs o_cout : out std_logic_vector (3 downto 0) ); end component; signal g0,g1,g2,g3 : std_logic; signal p0,p1,p2,p3 : std_logic; signal c0,c1,c2 : std_logic; begin u1: CLA4 port map( i_g(0) => g0, i_g(1) => g1, i_g(2) => g2, i_g(3) => g3, i_p(0) => p0, i_p(1) => p1, i_p(2) => p2, i_p(3) => p3, o_cout(0) => c0, o_cout(1) => c1, o_cout(2) => c2, o_cout(3) => o_carry ); process (i_a,i_b,i_cin) is begin -- Bit 0 g0 <= i_a(0) and i_b(0); p0 <= i_a(0) xor i_b(0); o_sum(0) <= p0 xor i_cin; -- Bit 1 g1 <= i_a(1) and i_b(1); p1 <= i_a(1) xor i_b(1); o_sum(1) <= p1 xor c0; -- Bit 2 g2 <= i_a(2) and i_b(2); p2 <= i_a(2) xor i_b(2); o_sum(2) <= p2 xor c1; -- Bit 3 g3 <= i_a(3) and i_b(3); p3 <= i_a(3) xor i_b(3); o_sum(3) <= p3 xor c2; end process; end architecture; Here is the tb code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; use ieee.std_logic_textio.all; entity Add4LACTB is end entity; architecture sim of Add4LACTB is signal a,b,sum,csum : std_logic_vector (3 downto 0); signal cin,carry,ccarry : std_logic; component Add4LAC port( -- inputs i_a : in std_logic_vector (3 downto 0); i_b : in std_logic_vector (3 downto 0); i_cin : in std_logic; -- outputs o_sum : out std_logic_vector (3 downto 0); o_carry : out std_logic ); end component; begin Adder1: Add4LAC port map( i_a => a, i_b => b, i_cin => cin, o_sum => sum, o_carry => carry ); process is variable v_myline : line; begin write(v_myline, string'(" a"), left, 5); write(v_myline, string'(" b"), left, 5); write(v_myline, string'(" cin"), left, 5); write(v_myline, string'(" sum"), left, 5); write(v_myline, string'(" cout"), left, 5); write(v_myline, string'("csum"), left, 5); write(v_myline, string'("ccout"), left, 5); writeline(output, v_myline); -- testscenarios --set a %B0000000000000000, --set b %B0000000000000000, --set a %B0000000000000000, --set b %B1111111111111111, --set a %B1111111111111111, --set b %B1111111111111111, --set a %B1010101010101010, --set b %B0101010101010101, --set a %B0011110011000011, --set b %B0000111111110000, --set a %B0001001000110100, --set b %B1001100001110110, a <= "0000"; b <= "0000"; cin <= '0'; csum <= "0000"; ccarry <= '0'; wait for 10 ns; write(v_myline, a, left, 5); write(v_myline, b, left, 5); write(v_myline, cin, left, 5); write(v_myline, sum, left, 5); write(v_myline, carry, left, 5); write(v_myline, csum, left, 5); write(v_myline, ccarry, left, 5); writeline(output, v_myline); if sum /= csum or carry /= ccarry then report "Result Mismatch!"; -- wait ; end if; a <= "1111"; b <= "1111"; cin <= '0'; csum <= "1110"; ccarry <= '1'; wait for 10 ns; write(v_myline, a, left, 5); write(v_myline, b, left, 5); write(v_myline, cin, left, 5); write(v_myline, sum, left, 5); write(v_myline, carry, left, 5); write(v_myline, csum, left, 5); write(v_myline, ccarry, left, 5); writeline(output, v_myline); if sum /= csum or carry /= ccarry then report "Result Mismatch!"; wait ; end if; wait; end process; end architecture; From newsfish@newsfish Thu Aug 1 00:45:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp1-2.free.fr!not-for-mail Subject: Re: Newbee in VHDL ... why is this not working? Newsgroups: comp.lang.vhdl References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> From: Nicolas Matringe Date: Thu, 14 May 2020 14:29:54 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 31 Message-ID: <5ebd39c2$0$24258$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 14 May 2020 14:29:54 CEST NNTP-Posting-Host: 88.123.153.23 X-Trace: 1589459394 news-1.free.fr 24258 88.123.153.23:11908 X-Complaints-To: abuse@proxad.net Xref: reader01.eternal-september.org comp.lang.vhdl:9676 Hello On 2020-05-14 13:49, Christoph Linden wrote: > Hi all, > I am getting into VHDL right now and doing the first implementation of some architecutres. For me to learn I follow nand2tetris, that uses its own HDL and translating that for my learning into VHDL. [...] > process (i_p, i_g, i_cin) is > > begin > -- caculate bit 1 preproduct and carry out 0 > -- And(a=p[0],b=cin,out=p0c); > -- Or(a=p0c,b=g[0],out=cout[0]); > > cp0 <= i_p(0) and i_cin; > o_cout(0) <= cp0 or i_g(0); [...] This won't work. You're treating signals as variables, which they are not. Remember VHDL is NOT software. A signal gets its value assigned at the end of the process. In the snippet above, cp0 equal 'U' because it's never been assigned anything yet. Then you compute a value (i_p(0) and i_cin) to be assigned to cp0. On the next line, though, cp0 is still equal to 'U' because the computed value will not be assigned until the end of the process. Depending on what you want to do, you can either write a second process that will compute o_cout(0) based on cp0, or make cp0 a variable (local to the process) instead of a signal (local to the architecture) Nicolas From newsfish@newsfish Thu Aug 1 00:45:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Newbee in VHDL ... why is this not working? Date: Thu, 14 May 2020 15:53:37 +0300 Organization: An impatient and LOUD arachnid Lines: 27 Message-ID: References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain Injection-Info: reader02.eternal-september.org; posting-host="baaf57e9bb84db255d1abf5a95f293b7"; logging-data="6821"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+nMgh0cfmLbXnnhz6gAyh1" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) Cancel-Lock: sha1:HbVzgoUc88v/gcGf9v5jlTgxKFA= sha1:SifzTS2Bep7EAuUzfTbhVCtCfrs= Xref: reader01.eternal-september.org comp.lang.vhdl:9677 Christoph Linden writes: > Hi all, > I am getting into VHDL right now and doing the first implementation of some architecutres. For me to learn I follow nand2tetris, that uses its own HDL and translating that for my learning into VHDL. Doesn't seem like a great way to learn. Do you have a software background? Anyways, a quick comment on the CLA4. > architecture cal4 of CLA4 is [...] > begin > > process (i_p, i_g, i_cin) is > > begin > cp0p1 <= i_cin and i_p(0) and i_p(1); > g0p1 <= i_g(0) and i_p(1); > o_cout(1) <= cp0p1 or g0p1 or i_g(1); The nature of hardware is such that these three assignments happen in parallel, hence your o_cout(1) ends up being U at time 0. Same for o_cout(2). I don't remember off hand how to code such primitives in VHDL but somehow you need to add delay between these assignments. Or do the assignment all at once. From newsfish@newsfish Thu Aug 1 00:45:29 2024 X-Received: by 2002:aed:2d44:: with SMTP id h62mr4773385qtd.217.1589466969084; Thu, 14 May 2020 07:36:09 -0700 (PDT) X-Received: by 2002:a25:3484:: with SMTP id b126mr7653953yba.133.1589466968773; Thu, 14 May 2020 07:36:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 May 2020 07:36:08 -0700 (PDT) In-Reply-To: <5ebd39c2$0$24258$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2003:de:2f29:9d00:7c82:5523:45de:f084; posting-account=uAdKBAoAAAAynyp-1im5p3hq6CRPCBsl NNTP-Posting-Host: 2003:de:2f29:9d00:7c82:5523:45de:f084 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> Subject: Re: Newbee in VHDL ... why is this not working? From: Christoph Linden Injection-Date: Thu, 14 May 2020 14:36:09 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 3478 X-Received-Body-CRC: 3168546376 Xref: reader01.eternal-september.org comp.lang.vhdl:9678 Am Donnerstag, 14. Mai 2020 14:29:56 UTC+2 schrieb Nicolas Matringe: > > This won't work. You're treating signals as variables, which they are > not. Remember VHDL is NOT software. > A signal gets its value assigned at the end of the process. In the > snippet above, cp0 equal 'U' because it's never been assigned anything > yet. Then you compute a value (i_p(0) and i_cin) to be assigned to cp0. > On the next line, though, cp0 is still equal to 'U' because the computed > value will not be assigned until the end of the process. > Depending on what you want to do, you can either write a second process > that will compute o_cout(0) based on cp0, or make cp0 a variable (local > to the process) instead of a signal (local to the architecture) > > Nicolas Hi Nicolas, thanks for the response. Also Thanks Anssi. Trying to add some additional information. I just transferred it from the HDL of nand2tetris, so that might be a bad way of doing so. What I want to create is a combinational logic (actually defining it at gate level), where those things propagate through. Obiously I could write an adder in a much simpler way in VHDL, but that is not my goal. I try to first implement it as close to the gate level as posible without writing gate (e.g. AND, NOT, XOR gates). What I am looking for is something like a propagation delay as it will happen naturally. If I would wire discrete AND/OR Chips and want to do a ( a AND b ) OR c I would simply wire the output of the AND chip to the one input of the or gate and then with propagation delay of both gates I will receive the output at OR. This is what I assume that all the statements would automatically do. Can you please explain quickly how I would achieve that without implementing real gates and "wire" them up in VHDL but using a similar construct? Or in other words, how would you create this and/or example from above. Now I try to split this into processes... I tried to avoid variables. Is variables a common thing to use in normal VHDL designs? I thougt it is more for use in loops, that in the end do not result in logic, but just in the behaviour description... From newsfish@newsfish Thu Aug 1 00:45:29 2024 X-Received: by 2002:ad4:4d44:: with SMTP id m4mr5302449qvm.236.1589468379539; Thu, 14 May 2020 07:59:39 -0700 (PDT) X-Received: by 2002:a25:b5c7:: with SMTP id d7mr3713628ybg.77.1589468379120; Thu, 14 May 2020 07:59:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 May 2020 07:59:38 -0700 (PDT) In-Reply-To: <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2003:de:2f29:9d00:7c82:5523:45de:f084; posting-account=uAdKBAoAAAAynyp-1im5p3hq6CRPCBsl NNTP-Posting-Host: 2003:de:2f29:9d00:7c82:5523:45de:f084 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbee in VHDL ... why is this not working? From: Christoph Linden Injection-Date: Thu, 14 May 2020 14:59:39 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 176 Xref: reader01.eternal-september.org comp.lang.vhdl:9679 Okay reworked it and (besides a bug in there) it now does what it supposed to do. However I am not sure if that is how you would do such things normally. Should I use a fully -- Look ahead carry calculation for 4 bits. -- length to be defined as constant c_WordWidth library ieee; use ieee.std_logic_1164.all; entity CLA4 is port( -- inputs i_g : in std_logic_vector (3 downto 0); i_p : in std_logic_vector (3 downto 0); i_cin : in std_logic; -- outputs o_cout : out std_logic_vector (3 downto 0) ); end entity; architecture cla4 of CLA4 is signal cp0 : std_logic; signal cp0p1 : std_logic; signal cp0p1p2 : std_logic; signal cp0p1p2p3 : std_logic; signal g0p1 : std_logic; signal g0p1p2 : std_logic; signal g0p1p2p3 : std_logic; signal g1p2 : std_logic; signal g1p2p3 : std_logic; signal g2p3 : std_logic; begin process (i_p, i_g, i_cin) is begin -- caculate bit 1 preproduct and carry out 0 -- And(a=p[0],b=cin,out=p0c); -- Or(a=p0c,b=g[0],out=cout[0]); cp0 <= i_p(0) and i_cin; -- calculate bit 2 preproduct and carry out 1 -- And3Way(a=cin, b=p[0], c=p[1], out=cp0p1); -- And(a=g[0],b=p[1],out=g0p1); -- Or3Way(a=cp0p1,b=g0p1,c=g[1],out=cout[1]); cp0p1 <= i_cin and i_p(0) and i_p(1); g0p1 <= i_g(0) and i_p(1); --calculate bit 3 preproducts and carry out 2 -- And4Way(a=cin, b=p[0], c=p[1], d=p[2], out=cp0p1p2); -- And3Way(a=g[0],b=p[1],c=p[2],out=g0p1p2); -- And(a=g[1],b=p[2],out=g1p2); -- Or4Way(a=cp0p1p2,b=g0p1p2,c=g1p2,d=g[2],out=cout[2]); cp0p1p2 <= i_cin and i_p(0) and i_p(1) and i_p(2); g0p1p2 <= i_g(0) and i_p(1) and i_p(2); g1p2 <= i_g(1) and i_p(2); --calculate bit 4 preproducts and carry out 4 -- And5Way(a=cin, b=p[0], c=p[1], d=p[2], e=p[3], out=cp0p1p2p3); -- And4Way(a=g[0], b=p[1], c=p[2], d=p[3], out=g0p1p2p3); -- And3Way(a=g[1],b=p[2],c=p[3],out=g1p2p3); -- And(a=g[2],b=p[3],out=g2p3); -- Or5Way(a=cp0p1p2p3,b=g0p1p2p3,c=g1p2p3,d=g2p3, e=g[3],out=cout[3]); cp0p1p2p3 <= i_cin and i_p(0) and i_p(1) and i_p(2) and i_p(3); g0p1p2p3 <= i_g(0) and i_p(1) and i_p(2) and i_p(3); g1p2p3 <= i_g(1) and i_p(2) and i_p(3); g2p3 <= i_g(2) and i_p(3); end process; process (cp0,cp0p1,g0p1,cp0p1p2,g0p1p2, g1p2,cp0p1p2p3,g0p1p2p3,g1p2p3,g2p3,i_g) is begin o_cout(0) <= cp0 or i_g(0); o_cout(1) <= cp0p1 or g0p1 or i_g(1); o_cout(2) <= cp0p1p2 or g0p1p2 or g1p2 or i_g(2); o_cout(3) <= cp0p1p2p3 or g0p1p2p3 or g1p2p3 or g2p3 or i_g(3); end process; end architecture; -- a 4 bit carry look ahead adder. library ieee; use ieee.std_logic_1164.all; entity Add4LAC is port( -- inputs i_a : in std_logic_vector (3 downto 0); i_b : in std_logic_vector (3 downto 0); i_cin : in std_logic; -- outputs o_sum : out std_logic_vector (3 downto 0); o_carry : out std_logic ); end entity; architecture add4lac of Add4LAC is component CLA4 port( -- inputs i_g : in std_logic_vector (3 downto 0); i_p : in std_logic_vector (3 downto 0); i_cin : in std_logic := 'L'; -- outputs o_cout : out std_logic_vector (3 downto 0) ); end component; signal g0,g1,g2,g3 : std_logic; signal p0,p1,p2,p3 : std_logic; signal c0,c1,c2 : std_logic; begin u1: CLA4 port map( i_g(0) => g0, i_g(1) => g1, i_g(2) => g2, i_g(3) => g3, i_p(0) => p0, i_p(1) => p1, i_p(2) => p2, i_p(3) => p3, o_cout(0) => c0, o_cout(1) => c1, o_cout(2) => c2, o_cout(3) => o_carry ); process (i_a,i_b,i_cin) is begin -- Bit 0 g0 <= i_a(0) and i_b(0); p0 <= i_a(0) xor i_b(0); -- Bit 1 g1 <= i_a(1) and i_b(1); p1 <= i_a(1) xor i_b(1); -- Bit 2 g2 <= i_a(2) and i_b(2); p2 <= i_a(2) xor i_b(2); -- Bit 3 g3 <= i_a(3) and i_b(3); p3 <= i_a(3) xor i_b(3); end process; process(c0,c1,c2,p0,p1,p2,p3) is begin o_sum(0) <= p0 xor i_cin; o_sum(1) <= p1 xor c0; o_sum(2) <= p2 xor c1; o_sum(3) <= p3 xor c2; end process; end architecture; From newsfish@newsfish Thu Aug 1 00:45:29 2024 X-Received: by 2002:ac8:27ef:: with SMTP id x44mr5488098qtx.233.1589475585194; Thu, 14 May 2020 09:59:45 -0700 (PDT) X-Received: by 2002:a25:cf4e:: with SMTP id f75mr9631798ybg.106.1589475583274; Thu, 14 May 2020 09:59:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 May 2020 09:59:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <14758d82-eeb4-4ddd-9616-709b63ea2162@googlegroups.com> Subject: Re: Newbee in VHDL ... why is this not working? From: Rick C Injection-Date: Thu, 14 May 2020 16:59:45 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9680 On Thursday, May 14, 2020 at 10:59:41 AM UTC-4, Christoph Linden wrote: > Okay reworked it and (besides a bug in there) it now does what it suppose= d to do. >=20 > However I am not sure if that is how you would do such things normally. >=20 > Should I use a fully=20 >=20 > -- Look ahead carry calculation for 4 bits. > -- length to be defined as constant c_WordWidth >=20 > library ieee; > use ieee.std_logic_1164.all; >=20 > entity CLA4 is >=20 > port( > -- inputs > i_g : in std_logic_vector (3 downto 0); > i_p : in std_logic_vector (3 downto 0); > i_cin : in std_logic; > =09 > -- outputs > o_cout : out std_logic_vector (3 downto 0) ); >=20 > end entity; >=20 > architecture cla4 of CLA4 is >=20 > signal cp0 : std_logic; > signal cp0p1 : std_logic; > signal cp0p1p2 : std_logic; > signal cp0p1p2p3 : std_logic; > signal g0p1 : std_logic; > signal g0p1p2 : std_logic; > signal g0p1p2p3 : std_logic; > signal g1p2 : std_logic; > signal g1p2p3 : std_logic; > signal g2p3 : std_logic; >=20 > begin=09 > =09 > process (i_p, i_g, i_cin) is >=20 > begin > -- caculate bit 1 preproduct and carry out 0 > -- And(a=3Dp[0],b=3Dcin,out=3Dp0c); > -- Or(a=3Dp0c,b=3Dg[0],out=3Dcout[0]); >=20 > cp0 <=3D i_p(0) and i_cin; > =09 > -- calculate bit 2 preproduct and carry out 1 > -- And3Way(a=3Dcin, b=3Dp[0], c=3Dp[1], out=3Dcp0p1); > -- And(a=3Dg[0],b=3Dp[1],out=3Dg0p1); > -- Or3Way(a=3Dcp0p1,b=3Dg0p1,c=3Dg[1],out=3Dcout[1]); > =09 > cp0p1 <=3D i_cin and i_p(0) and i_p(1); > g0p1 <=3D i_g(0) and i_p(1); > =09 > --calculate bit 3 preproducts and carry out 2 > -- And4Way(a=3Dcin, b=3Dp[0], c=3Dp[1], d=3Dp[2], out=3Dcp0p1p2); > -- And3Way(a=3Dg[0],b=3Dp[1],c=3Dp[2],out=3Dg0p1p2); > -- And(a=3Dg[1],b=3Dp[2],out=3Dg1p2); > -- Or4Way(a=3Dcp0p1p2,b=3Dg0p1p2,c=3Dg1p2,d=3Dg[2],out=3Dcout[2]); > =09 > cp0p1p2 <=3D i_cin and i_p(0) and i_p(1) and i_p(2); > g0p1p2 <=3D i_g(0) and i_p(1) and i_p(2); > g1p2 <=3D i_g(1) and i_p(2); > =09 > =09 > --calculate bit 4 preproducts and carry out 4 > -- And5Way(a=3Dcin, b=3Dp[0], c=3Dp[1], d=3Dp[2], e=3Dp[3], out=3Dcp0p1p= 2p3); > -- And4Way(a=3Dg[0], b=3Dp[1], c=3Dp[2], d=3Dp[3], out=3Dg0p1p2p3); > -- And3Way(a=3Dg[1],b=3Dp[2],c=3Dp[3],out=3Dg1p2p3); > -- And(a=3Dg[2],b=3Dp[3],out=3Dg2p3); > -- Or5Way(a=3Dcp0p1p2p3,b=3Dg0p1p2p3,c=3Dg1p2p3,d=3Dg2p3, e=3Dg[3],out= =3Dcout[3]); > =09 > cp0p1p2p3 <=3D i_cin and i_p(0) and i_p(1) and i_p(2) and i_p(3); > g0p1p2p3 <=3D i_g(0) and i_p(1) and i_p(2) and i_p(3); > g1p2p3 <=3D i_g(1) and i_p(2) and i_p(3); > g2p3 <=3D i_g(2) and i_p(3); > end process; > =09 > process (cp0,cp0p1,g0p1,cp0p1p2,g0p1p2, > g1p2,cp0p1p2p3,g0p1p2p3,g1p2p3,g2p3,i_g) is > begin > o_cout(0) <=3D cp0 or i_g(0); > o_cout(1) <=3D cp0p1 or g0p1 or i_g(1); > o_cout(2) <=3D cp0p1p2 or g0p1p2 or g1p2 or i_g(2); > o_cout(3) <=3D cp0p1p2p3 or g0p1p2p3 or g1p2p3 or g2p3 or i_g(3); > end process; >=20 > end architecture; >=20 >=20 > -- a 4 bit carry look ahead adder. > library ieee; > use ieee.std_logic_1164.all; >=20 > entity Add4LAC is >=20 > port( > -- inputs > i_a : in std_logic_vector (3 downto 0); > i_b : in std_logic_vector (3 downto 0); > i_cin : in std_logic; > =09 > -- outputs > o_sum : out std_logic_vector (3 downto 0); > o_carry : out std_logic ); >=20 > end entity; >=20 > architecture add4lac of Add4LAC is >=20 > component CLA4 > port( > -- inputs > i_g : in std_logic_vector (3 downto 0); > i_p : in std_logic_vector (3 downto 0); > i_cin : in std_logic :=3D 'L'; > =09 > -- outputs > o_cout : out std_logic_vector (3 downto 0) ); > end component; >=20 > signal g0,g1,g2,g3 : std_logic; > signal p0,p1,p2,p3 : std_logic; > signal c0,c1,c2 : std_logic; > =09 > begin > =20 > u1: CLA4 > port map( > i_g(0) =3D> g0, > i_g(1) =3D> g1, > i_g(2) =3D> g2, > i_g(3) =3D> g3, > i_p(0) =3D> p0, > i_p(1) =3D> p1, > i_p(2) =3D> p2, > i_p(3) =3D> p3, > o_cout(0) =3D> c0, > o_cout(1) =3D> c1, > o_cout(2) =3D> c2, > o_cout(3) =3D> o_carry ); > =09 > process (i_a,i_b,i_cin) is > begin > -- Bit 0 > g0 <=3D i_a(0) and i_b(0); > p0 <=3D i_a(0) xor i_b(0); >=20 > -- Bit 1 > g1 <=3D i_a(1) and i_b(1); > p1 <=3D i_a(1) xor i_b(1); > =09 > -- Bit 2 > g2 <=3D i_a(2) and i_b(2); > p2 <=3D i_a(2) xor i_b(2); > =09 > -- Bit 3 > g3 <=3D i_a(3) and i_b(3); > p3 <=3D i_a(3) xor i_b(3); > =09 > end process; > =09 > process(c0,c1,c2,p0,p1,p2,p3) is > begin > o_sum(0) <=3D p0 xor i_cin; > o_sum(1) <=3D p1 xor c0; > o_sum(2) <=3D p2 xor c1; > o_sum(3) <=3D p3 xor c2; > end process; > =09 > =09 > end architecture; You seem to like processes for everything. There is no reason to put this = particular code into processes. It can all be concurrent logic outside of = processes. Then to test your code you would normally create a test fixture= to instantiate your adder code, supply inputs and check outputs. Processe= s are useful for combinational logic to group signals when they share the s= ame inputs. When assignments don't share the same inputs related assignmen= ts can be grouped using white space with a lot less typing. =20 process (cp0,cp0p1,g0p1,cp0p1p2,g0p1p2, g1p2,cp0p1p2p3,g0p1p2p3,g1p2p3,g2p3,i_g) is begin ... end process; Way too much typing for me.=20 Just my 2000 millicents worth. =20 BTW, the question in your post seems to have been cut off.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:29 2024 X-Received: by 2002:a0c:ba2e:: with SMTP id w46mr833062qvf.120.1589496359943; Thu, 14 May 2020 15:45:59 -0700 (PDT) X-Received: by 2002:a25:7406:: with SMTP id p6mr886364ybc.319.1589496359685; Thu, 14 May 2020 15:45:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 May 2020 15:45:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> Subject: Re: Newbee in VHDL ... why is this not working? From: Rick C Injection-Date: Thu, 14 May 2020 22:45:59 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9681 On Thursday, May 14, 2020 at 10:59:41 AM UTC-4, Christoph Linden wrote: > Okay reworked it and (besides a bug in there) it now does what it supposed to do. > > However I am not sure if that is how you would do such things normally. > > Should I use a fully I don't know, you didn't finish the question. You might look at the regularity in the calculations and use looping constructs to evaluate them. Then you would need either processes or generate statements. For example, just as you use a vector for o_sum (which you never declare either internally or as an output) you can define your intermediate terms as vectors letting the index point to the right one at the right time. You will need to give this a bit of thought and a nice diagram of the arrangement of the logical entities would help to see the regularity of the problem being solved. Here is your code without the processes. -- Look ahead carry calculation for 4 bits. -- length to be defined as constant c_WordWidth library ieee; use ieee.std_logic_1164.all; entity CLA4 is port( -- inputs i_g : in std_logic_vector (3 downto 0); i_p : in std_logic_vector (3 downto 0); i_cin : in std_logic; -- outputs o_cout : out std_logic_vector (3 downto 0) ); end entity; architecture cla4 of CLA4 is signal cp0 : std_logic; signal cp0p1 : std_logic; signal cp0p1p2 : std_logic; signal cp0p1p2p3 : std_logic; signal g0p1 : std_logic; signal g0p1p2 : std_logic; signal g0p1p2p3 : std_logic; signal g1p2 : std_logic; signal g1p2p3 : std_logic; signal g2p3 : std_logic; begin cp0 <= i_p(0) and i_cin; cp0p1 <= i_cin and i_p(0) and i_p(1); g0p1 <= i_g(0) and i_p(1); cp0p1p2 <= i_cin and i_p(0) and i_p(1) and i_p(2); g0p1p2 <= i_g(0) and i_p(1) and i_p(2); g1p2 <= i_g(1) and i_p(2); cp0p1p2p3 <= i_cin and i_p(0) and i_p(1) and i_p(2) and i_p(3); g0p1p2p3 <= i_g(0) and i_p(1) and i_p(2) and i_p(3); g1p2p3 <= i_g(1) and i_p(2) and i_p(3); g2p3 <= i_g(2) and i_p(3); o_cout(0) <= cp0 or i_g(0); o_cout(1) <= cp0p1 or g0p1 or i_g(1); o_cout(2) <= cp0p1p2 or g0p1p2 or g1p2 or i_g(2); o_cout(3) <= cp0p1p2p3 or g0p1p2p3 or g1p2p3 or g2p3 or i_g(3); -- Bit 1 g1 <= i_a(1) and i_b(1); p1 <= i_a(1) xor i_b(1); -- Bit 2 g2 <= i_a(2) and i_b(2); p2 <= i_a(2) xor i_b(2); -- Bit 3 g3 <= i_a(3) and i_b(3); p3 <= i_a(3) xor i_b(3); o_sum(0) <= p0 xor i_cin; o_sum(1) <= p1 xor c0; o_sum(2) <= p2 xor c1; o_sum(3) <= p3 xor c2; end architecture; -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:30 2024 X-Received: by 2002:ad4:4a8b:: with SMTP id h11mr2035112qvx.232.1589522425670; Thu, 14 May 2020 23:00:25 -0700 (PDT) X-Received: by 2002:a25:14d6:: with SMTP id 205mr3054030ybu.113.1589522425312; Thu, 14 May 2020 23:00:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 May 2020 23:00:25 -0700 (PDT) In-Reply-To: <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2003:de:2f29:9d00:7c82:5523:45de:f084; posting-account=uAdKBAoAAAAynyp-1im5p3hq6CRPCBsl NNTP-Posting-Host: 2003:de:2f29:9d00:7c82:5523:45de:f084 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbee in VHDL ... why is this not working? From: Christoph Linden Injection-Date: Fri, 15 May 2020 06:00:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9682 Am Freitag, 15. Mai 2020 00:46:01 UTC+2 schrieb Rick C: Thank you Rick, very helpful. 1. Unfortunately I do not know anymore what the questions should have been.= I believe it was in the ballpark how I can do this similar to a structural= design but without defining single and gates. 2. The o_sum part. The problem is, that for whatever reason google.groups = interpreted part of the code as "quote". So if you click on the quote you s= ee, that it is actually two entities. One entity is calculating the carry l= ook ahead and the other is doing the actual add of the four bits. That is why it looks so weird if you do not unfold the quote. But anyhow I understood what you was saying and yes, I just used the proces= s, because I did not understood that I do not need to use process all the t= ime.=20 I will give it a try. Is the following understanding correct: Process for sequential (a must to react on the clock and the edge of the si= gnal) no process for combinatory circuits (such as ALU designs) From newsfish@newsfish Thu Aug 1 00:45:30 2024 X-Received: by 2002:ad4:434a:: with SMTP id q10mr2160224qvs.81.1589526177102; Fri, 15 May 2020 00:02:57 -0700 (PDT) X-Received: by 2002:a25:2a8c:: with SMTP id q134mr4018136ybq.143.1589526176850; Fri, 15 May 2020 00:02:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder5.feed.usenet.farm!feed.usenet.farm!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!82.197.223.106.MISMATCH!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 May 2020 00:02:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <22aabed2-3179-411e-b824-4f4783d5052e@googlegroups.com> Subject: Re: Newbee in VHDL ... why is this not working? From: Rick C Injection-Date: Fri, 15 May 2020 07:02:57 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9683 On Friday, May 15, 2020 at 2:00:27 AM UTC-4, Christoph Linden wrote: > Am Freitag, 15. Mai 2020 00:46:01 UTC+2 schrieb Rick C: > Thank you Rick, very helpful. >=20 > 1. Unfortunately I do not know anymore what the questions should have bee= n. I believe it was in the ballpark how I can do this similar to a structur= al design but without defining single and gates. >=20 > 2. The o_sum part. The problem is, that for whatever reason google.group= s interpreted part of the code as "quote". So if you click on the quote you= see, that it is actually two entities. One entity is calculating the carry= look ahead and the other is doing the actual add of the four bits. >=20 > That is why it looks so weird if you do not unfold the quote. >=20 > But anyhow I understood what you was saying and yes, I just used the proc= ess, because I did not understood that I do not need to use process all the= time.=20 >=20 > I will give it a try. >=20 > Is the following understanding correct: >=20 > Process for sequential (a must to react on the clock and the edge of the = signal) >=20 > no process for combinatory circuits (such as ALU designs) It is obvious you are just getting started, so I understand. I had no one = to ask when I learned to use VHDL. I took a week course and the instructor= sucked so badly he answered questions wrong. It's one thing not to know, = but giving out bad info is terrible.=20 I won't say you should not use a process for combinational circuits. A pro= cess is of no value for simple assignments to signals. Processes also have= variables which are updated immediately, unlike signals which are not upda= ted until the process ends and the simulation proceeds to the next time ste= p which is a delta time step. That's a bit complicated and I'm happy to ex= plain it if you want. Most people consider that signals are updated at the= end of the process which is essentially correct. =20 Concurrent code does not use variables. Every concurrent assignment is act= ually a process. It runs whenever any of the inputs change state, just lik= e a process. Essentially all concurrent code produces logic that runs in p= arallel. Even the process statement is concurrent code creating a process = that runs in parallel with other processes including the concurrent logic. = Hence the name concurrent.=20 Variables can used in sequential code such as processes, functions and proc= edures. They allow code to be written in a similar manner to code written = for CPUs which are executed sequentially. For example you can write=20 a :=3D b + c;=20 a :=3D a + d; This would add b, c and d and assign it to a in the order shown. If a were= a signal, the last assignment in the process would be the only one taking = effect. Notice a different assignment operator is used for signals <=3D an= d variables :=3D=20 Often beginners confuse processes with subroutines like sequential programm= ing languages use. You don't seem to have that confusion. =20 So there are many ways to do the job. It also makes a difference if you ar= e working with VHDL 2008 or an older version. There are many improvements = in 2008 that makes coding easier. Often you must enable VHDL 2008 in your = tool even if it is capable. =20 I hope this helps.=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:30 2024 X-Received: by 2002:a05:620a:2290:: with SMTP id o16mr2728846qkh.410.1589540801303; Fri, 15 May 2020 04:06:41 -0700 (PDT) X-Received: by 2002:a25:14d6:: with SMTP id 205mr4722640ybu.113.1589540800987; Fri, 15 May 2020 04:06:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 May 2020 04:06:40 -0700 (PDT) In-Reply-To: <22aabed2-3179-411e-b824-4f4783d5052e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2003:de:2f29:9d00:7c82:5523:45de:f084; posting-account=uAdKBAoAAAAynyp-1im5p3hq6CRPCBsl NNTP-Posting-Host: 2003:de:2f29:9d00:7c82:5523:45de:f084 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> <22aabed2-3179-411e-b824-4f4783d5052e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbee in VHDL ... why is this not working? From: Christoph Linden Injection-Date: Fri, 15 May 2020 11:06:41 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9684 Am Freitag, 15. Mai 2020 09:02:59 UTC+2 schrieb Rick C: > On Friday, May 15, 2020 at 2:00:27 AM UTC-4, Christoph Linden wrote: > > Am Freitag, 15. Mai 2020 00:46:01 UTC+2 schrieb Rick C: > > Thank you Rick, very helpful. > >=20 > > 1. Unfortunately I do not know anymore what the questions should have b= een. I believe it was in the ballpark how I can do this similar to a struct= ural design but without defining single and gates. > >=20 > > 2. The o_sum part. The problem is, that for whatever reason google.gro= ups interpreted part of the code as "quote". So if you click on the quote y= ou see, that it is actually two entities. One entity is calculating the car= ry look ahead and the other is doing the actual add of the four bits. > >=20 > > That is why it looks so weird if you do not unfold the quote. > >=20 > > But anyhow I understood what you was saying and yes, I just used the pr= ocess, because I did not understood that I do not need to use process all t= he time.=20 > >=20 > > I will give it a try. > >=20 > > Is the following understanding correct: > >=20 > > Process for sequential (a must to react on the clock and the edge of th= e signal) > >=20 > > no process for combinatory circuits (such as ALU designs) >=20 > It is obvious you are just getting started, so I understand. I had no on= e to ask when I learned to use VHDL. I took a week course and the instruct= or sucked so badly he answered questions wrong. It's one thing not to know= , but giving out bad info is terrible.=20 >=20 > I won't say you should not use a process for combinational circuits. A p= rocess is of no value for simple assignments to signals. Processes also ha= ve variables which are updated immediately, unlike signals which are not up= dated until the process ends and the simulation proceeds to the next time s= tep which is a delta time step. That's a bit complicated and I'm happy to = explain it if you want. Most people consider that signals are updated at t= he end of the process which is essentially correct. =20 >=20 > Concurrent code does not use variables. Every concurrent assignment is a= ctually a process. It runs whenever any of the inputs change state, just l= ike a process. Essentially all concurrent code produces logic that runs in= parallel. Even the process statement is concurrent code creating a proces= s that runs in parallel with other processes including the concurrent logic= . Hence the name concurrent.=20 >=20 > Variables can used in sequential code such as processes, functions and pr= ocedures. They allow code to be written in a similar manner to code writte= n for CPUs which are executed sequentially. For example you can write=20 >=20 > a :=3D b + c;=20 > a :=3D a + d; >=20 > This would add b, c and d and assign it to a in the order shown. If a we= re a signal, the last assignment in the process would be the only one takin= g effect. Notice a different assignment operator is used for signals <=3D = and variables :=3D=20 >=20 > Often beginners confuse processes with subroutines like sequential progra= mming languages use. You don't seem to have that confusion. =20 >=20 > So there are many ways to do the job. It also makes a difference if you = are working with VHDL 2008 or an older version. There are many improvement= s in 2008 that makes coding easier. Often you must enable VHDL 2008 in you= r tool even if it is capable. =20 >=20 > I hope this helps.=20 >=20 > --=20 >=20 > Rick C. >=20 > -- Get 1,000 miles of free Supercharging > -- Tesla referral code - https://ts.la/richard11209 Thank you so much Rick, that really helps and is highly appreciated. I was aware of the parallelity of execution, but actually the process is on= ly update one time... So you are right, what I would need to do would be pu= tting each line in a process, which is pretty much pointless. I came from nand2tetris, which has a much more simplified HDL to get the pr= inciples of chip design transported/tought. I now wanted to get into a real= HDL to implement this chip (a very simple 16bit processor) into an FPGA.= =20 So i learned some of the tutorials from https://vhdlwhiz.com/, which helped= alot - for instance all the basic gates and muxers and stuff I could imple= ment easily. But at that point I struggled because of simply not really und= erstanding what a process does and why something within a process is not th= e same as a simple concurrent logic without any process. You helped me on that alot and it is now much clearer. I am pretty sure I w= ill stumble accross it again in the future, as things are getting more comp= licated, but for now. THANKS A MILLION, really appreciated. From newsfish@newsfish Thu Aug 1 00:45:30 2024 X-Received: by 2002:a0c:b992:: with SMTP id v18mr2949790qvf.223.1589542801620; Fri, 15 May 2020 04:40:01 -0700 (PDT) X-Received: by 2002:a25:bb47:: with SMTP id b7mr4458616ybk.200.1589542801403; Fri, 15 May 2020 04:40:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 May 2020 04:40:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> <22aabed2-3179-411e-b824-4f4783d5052e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <077604e0-c438-4ead-ab8e-6570c3969541@googlegroups.com> Subject: Re: Newbee in VHDL ... why is this not working? From: Rick C Injection-Date: Fri, 15 May 2020 11:40:01 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9685 On Friday, May 15, 2020 at 7:06:42 AM UTC-4, Christoph Linden wrote: > Am Freitag, 15. Mai 2020 09:02:59 UTC+2 schrieb Rick C: > > On Friday, May 15, 2020 at 2:00:27 AM UTC-4, Christoph Linden wrote: > > > Am Freitag, 15. Mai 2020 00:46:01 UTC+2 schrieb Rick C: > > > Thank you Rick, very helpful. > > >=20 > > > 1. Unfortunately I do not know anymore what the questions should have= been. I believe it was in the ballpark how I can do this similar to a stru= ctural design but without defining single and gates. > > >=20 > > > 2. The o_sum part. The problem is, that for whatever reason google.g= roups interpreted part of the code as "quote". So if you click on the quote= you see, that it is actually two entities. One entity is calculating the c= arry look ahead and the other is doing the actual add of the four bits. > > >=20 > > > That is why it looks so weird if you do not unfold the quote. > > >=20 > > > But anyhow I understood what you was saying and yes, I just used the = process, because I did not understood that I do not need to use process all= the time.=20 > > >=20 > > > I will give it a try. > > >=20 > > > Is the following understanding correct: > > >=20 > > > Process for sequential (a must to react on the clock and the edge of = the signal) > > >=20 > > > no process for combinatory circuits (such as ALU designs) > >=20 > > It is obvious you are just getting started, so I understand. I had no = one to ask when I learned to use VHDL. I took a week course and the instru= ctor sucked so badly he answered questions wrong. It's one thing not to kn= ow, but giving out bad info is terrible.=20 > >=20 > > I won't say you should not use a process for combinational circuits. A= process is of no value for simple assignments to signals. Processes also = have variables which are updated immediately, unlike signals which are not = updated until the process ends and the simulation proceeds to the next time= step which is a delta time step. That's a bit complicated and I'm happy t= o explain it if you want. Most people consider that signals are updated at= the end of the process which is essentially correct. =20 > >=20 > > Concurrent code does not use variables. Every concurrent assignment is= actually a process. It runs whenever any of the inputs change state, just= like a process. Essentially all concurrent code produces logic that runs = in parallel. Even the process statement is concurrent code creating a proc= ess that runs in parallel with other processes including the concurrent log= ic. Hence the name concurrent.=20 > >=20 > > Variables can used in sequential code such as processes, functions and = procedures. They allow code to be written in a similar manner to code writ= ten for CPUs which are executed sequentially. For example you can write=20 > >=20 > > a :=3D b + c;=20 > > a :=3D a + d; > >=20 > > This would add b, c and d and assign it to a in the order shown. If a = were a signal, the last assignment in the process would be the only one tak= ing effect. Notice a different assignment operator is used for signals <= =3D and variables :=3D=20 > >=20 > > Often beginners confuse processes with subroutines like sequential prog= ramming languages use. You don't seem to have that confusion. =20 > >=20 > > So there are many ways to do the job. It also makes a difference if yo= u are working with VHDL 2008 or an older version. There are many improveme= nts in 2008 that makes coding easier. Often you must enable VHDL 2008 in y= our tool even if it is capable. =20 > >=20 > > I hope this helps.=20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > -- Get 1,000 miles of free Supercharging > > -- Tesla referral code - https://ts.la/richard11209 >=20 > Thank you so much Rick, that really helps and is highly appreciated. >=20 > I was aware of the parallelity of execution, but actually the process is = only update one time... So you are right, what I would need to do would be = putting each line in a process, which is pretty much pointless. >=20 > I came from nand2tetris, which has a much more simplified HDL to get the = principles of chip design transported/tought. I now wanted to get into a re= al HDL to implement this chip (a very simple 16bit processor) into an FPGA.= =20 >=20 > So i learned some of the tutorials from https://vhdlwhiz.com/, which help= ed alot - for instance all the basic gates and muxers and stuff I could imp= lement easily. But at that point I struggled because of simply not really u= nderstanding what a process does and why something within a process is not = the same as a simple concurrent logic without any process. >=20 > You helped me on that alot and it is now much clearer. I am pretty sure I= will stumble accross it again in the future, as things are getting more co= mplicated, but for now. >=20 > THANKS A MILLION, really appreciated. No problem. I didn't realize you were working on an actual design. I thou= ght this was a learning exercise. =20 If you are targeting FPGAs, there is no point in trying to implement a carr= y lookahead, at least not for 16 bits. Every FPGA I know of uses a fast ca= rry chain optimized in the silicon which runs much faster than any sort of = speedup implemented in the LUTs in the FPGA fabric. They use a similar sor= t of carry speedup involving a transmission gate which is faster than a log= ic gate. So each stage has a logic delay which all bits execute in paralle= l and the ripple carry which is a small fraction of a ns per bit. =20 So unless you are doing the carry lookahead as an exercise, just typing the= addition of your signals is all you need to do. Oh, and using ieee.numeri= c_std. That will let you use signed or unsigned data types for your adder.= Or you can use integer types with the range restricted to 16 bits. That = could be lesson 2 if you are interested.=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:31 2024 X-Received: by 2002:a05:620a:108e:: with SMTP id g14mr4242329qkk.337.1589560812750; Fri, 15 May 2020 09:40:12 -0700 (PDT) X-Received: by 2002:a25:4ac7:: with SMTP id x190mr5297058yba.106.1589560812363; Fri, 15 May 2020 09:40:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 May 2020 09:40:12 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2402:8100:2180:cbbe:0:0:d4:65ed; posting-account=9Vb7SwoAAAC6jUk7CPOoSLbIfqaz1-25 NNTP-Posting-Host: 2402:8100:2180:cbbe:0:0:d4:65ed User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c9fafc3-8654-4082-9785-c47f58e7d456@googlegroups.com> Subject: breaking an image into blocks and compute histogram of each block using vhdl From: rsdeshwal@gmail.com Injection-Date: Fri, 15 May 2020 16:40:12 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9686 How to break an image into blocks and compute histogram of each block using vhdl ? I have to break an image of 128*128 into 16 *16 blocks and need to compute the histogram of each block... Please help me at the earliest...thanks From newsfish@newsfish Thu Aug 1 00:45:31 2024 X-Received: by 2002:ac8:4e06:: with SMTP id c6mr1397331qtw.360.1589566438971; Fri, 15 May 2020 11:13:58 -0700 (PDT) X-Received: by 2002:a25:d8cf:: with SMTP id p198mr7152004ybg.119.1589566438796; Fri, 15 May 2020 11:13:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 May 2020 11:13:58 -0700 (PDT) In-Reply-To: <1c9fafc3-8654-4082-9785-c47f58e7d456@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <1c9fafc3-8654-4082-9785-c47f58e7d456@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1126ea34-433e-417d-8812-4dd5ee820a73@googlegroups.com> Subject: Re: breaking an image into blocks and compute histogram of each block using vhdl From: Rick C Injection-Date: Fri, 15 May 2020 18:13:58 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9687 On Friday, May 15, 2020 at 12:40:14 PM UTC-4, rsde...@gmail.com wrote: > How to break an image into blocks and compute histogram of each block using vhdl ? I have to break an image of 128*128 into 16 *16 blocks and need to compute the histogram of each block... > > Please help me at the earliest...thanks Can you define the equations you would use to do this? Can you show the algorithm in pseudo-code? What is the histogram of? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:32 2024 X-Received: by 2002:a0c:c506:: with SMTP id x6mr7089746qvi.188.1589615053147; Sat, 16 May 2020 00:44:13 -0700 (PDT) X-Received: by 2002:a25:b94:: with SMTP id 142mr11873188ybl.14.1589615052768; Sat, 16 May 2020 00:44:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 16 May 2020 00:44:12 -0700 (PDT) In-Reply-To: <1126ea34-433e-417d-8812-4dd5ee820a73@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2402:8100:218b:ed39:0:0:12a:c46c; posting-account=9Vb7SwoAAAC6jUk7CPOoSLbIfqaz1-25 NNTP-Posting-Host: 2402:8100:218b:ed39:0:0:12a:c46c References: <1c9fafc3-8654-4082-9785-c47f58e7d456@googlegroups.com> <1126ea34-433e-417d-8812-4dd5ee820a73@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <771475c7-52df-4533-96bd-4f53fff98fd3@googlegroups.com> Subject: Re: breaking an image into blocks and compute histogram of each block using vhdl From: rsdeshwal@gmail.com Injection-Date: Sat, 16 May 2020 07:44:13 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9688 This is my task to do and I have no idea how to break the image into blocks and then Compute histogram...I am waiting for solution.. From newsfish@newsfish Thu Aug 1 00:45:32 2024 X-Received: by 2002:a0c:aed7:: with SMTP id n23mr1808961qvd.179.1589636228550; Sat, 16 May 2020 06:37:08 -0700 (PDT) X-Received: by 2002:a25:2a8c:: with SMTP id q134mr15470407ybq.143.1589636228220; Sat, 16 May 2020 06:37:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder.usenetexpress.com!tr3.eu1.usenetexpress.com!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!82.197.223.106.MISMATCH!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 16 May 2020 06:37:07 -0700 (PDT) In-Reply-To: <771475c7-52df-4533-96bd-4f53fff98fd3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2600:1:9162:3e53:61b9:26d:866:b115; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1:9162:3e53:61b9:26d:866:b115 References: <1c9fafc3-8654-4082-9785-c47f58e7d456@googlegroups.com> <1126ea34-433e-417d-8812-4dd5ee820a73@googlegroups.com> <771475c7-52df-4533-96bd-4f53fff98fd3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <401aede9-306f-490f-aa09-8892d0f2935b@googlegroups.com> Subject: Re: breaking an image into blocks and compute histogram of each block using vhdl From: KJ Injection-Date: Sat, 16 May 2020 13:37:08 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9689 You have seen a checkerboard at some point in your life, right? That should be enough help to break up your image into blocks. Compute the histogram of each square on your checkerboard. While you're waiting, read up a bit on the task you're trying to complete and post what you've found. Don't expect others to do your assignment Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-a.proxad.net!nnrp1-1.free.fr!not-for-mail Subject: Re: Newbee in VHDL ... why is this not working? Newsgroups: comp.lang.vhdl References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> <22aabed2-3179-411e-b824-4f4783d5052e@googlegroups.com> From: Nicolas Matringe Date: Sun, 17 May 2020 13:43:56 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 27 Message-ID: <5ec1237c$0$5894$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 17 May 2020 13:43:56 CEST NNTP-Posting-Host: 88.123.153.23 X-Trace: 1589715836 news-4.free.fr 5894 88.123.153.23:15904 X-Complaints-To: abuse@proxad.net Xref: reader01.eternal-september.org comp.lang.vhdl:9690 On 2020-05-15 13:06, Christoph Linden wrote: > I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless. You don't have to put each line in a process, just write concurrent assignments (which are, actually, implicit processes without all the fuss) Writing a <= b and c; outside of a process is strictly equivalent to process (b, c) begin a <= b and c; end process; You can therefore write a <= b and c; d <= a or e; and it will give you exactly d <= (b and c) or e; as long as it's NOT in a process. Nicolas From newsfish@newsfish Thu Aug 1 00:45:33 2024 X-Received: by 2002:a37:a455:: with SMTP id n82mr17617805qke.258.1589820501181; Mon, 18 May 2020 09:48:21 -0700 (PDT) X-Received: by 2002:a25:787:: with SMTP id 129mr27377772ybh.359.1589820500941; Mon, 18 May 2020 09:48:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 18 May 2020 09:48:20 -0700 (PDT) In-Reply-To: <5ec1237c$0$5894$426a34cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2003:de:2f29:9d00:4c7d:7e4c:8d35:bfb6; posting-account=uAdKBAoAAAAynyp-1im5p3hq6CRPCBsl NNTP-Posting-Host: 2003:de:2f29:9d00:4c7d:7e4c:8d35:bfb6 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> <22aabed2-3179-411e-b824-4f4783d5052e@googlegroups.com> <5ec1237c$0$5894$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <681b4c56-66fe-430d-92a0-45f9996323a2@googlegroups.com> Subject: Re: Newbee in VHDL ... why is this not working? From: Christoph Linden Injection-Date: Mon, 18 May 2020 16:48:21 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9691 Am Sonntag, 17. Mai 2020 13:43:58 UTC+2 schrieb Nicolas Matringe: > On 2020-05-15 13:06, Christoph Linden wrote: >=20 > > I was aware of the parallelity of execution, but actually the process i= s only update one time... So you are right, what I would need to do would b= e putting each line in a process, which is pretty much pointless. >=20 > You don't have to put each line in a process, just write concurrent=20 > assignments (which are, actually, implicit processes without all the fuss= ) >=20 > Writing >=20 > a <=3D b and c; >=20 > outside of a process is strictly equivalent to >=20 > process (b, c) > begin > a <=3D b and c; > end process; >=20 > You can therefore write >=20 > a <=3D b and c; > d <=3D a or e; >=20 > and it will give you exactly d <=3D (b and c) or e; > as long as it's NOT in a process. >=20 > Nicolas Thanks for the explanation ... it comes together step by step. and that is = why I am doing this as a learning experience based on an already existing d= esign I did within the nand2tetris course with a very simplified HDL. Actually the HDL has only structural design and also comes with nothing lik= e processes... My journey goes on now with mixed design and then getting in= to a full behavioural implementation. As Rick mentioned ... obviously I cou= ld simply use sum=3Da+b; and would be fine. But that was to easy :-) From newsfish@newsfish Thu Aug 1 00:45:33 2024 X-Received: by 2002:aed:2496:: with SMTP id t22mr19064020qtc.2.1589840572479; Mon, 18 May 2020 15:22:52 -0700 (PDT) X-Received: by 2002:a25:4b07:: with SMTP id y7mr31069567yba.438.1589840572328; Mon, 18 May 2020 15:22:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 18 May 2020 15:22:52 -0700 (PDT) In-Reply-To: <681b4c56-66fe-430d-92a0-45f9996323a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <7025897f-3878-4054-8447-8ddcaad73a76@googlegroups.com> <5ebd39c2$0$24258$426a74cc@news.free.fr> <2a38b1dc-23b1-4dd2-b7ff-72cfe46c7e14@googlegroups.com> <5da27fb4-1e69-4cc3-be90-e5d69857820c@googlegroups.com> <22aabed2-3179-411e-b824-4f4783d5052e@googlegroups.com> <5ec1237c$0$5894$426a34cc@news.free.fr> <681b4c56-66fe-430d-92a0-45f9996323a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2e72a5bb-9c8a-4be1-b488-e090c2682bdf@googlegroups.com> Subject: Re: Newbee in VHDL ... why is this not working? From: Rick C Injection-Date: Mon, 18 May 2020 22:22:52 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 63 Xref: reader01.eternal-september.org comp.lang.vhdl:9692 On Monday, May 18, 2020 at 12:48:24 PM UTC-4, Christoph Linden wrote: > Am Sonntag, 17. Mai 2020 13:43:58 UTC+2 schrieb Nicolas Matringe: > > On 2020-05-15 13:06, Christoph Linden wrote: > >=20 > > > I was aware of the parallelity of execution, but actually the process= is only update one time... So you are right, what I would need to do would= be putting each line in a process, which is pretty much pointless. > >=20 > > You don't have to put each line in a process, just write concurrent=20 > > assignments (which are, actually, implicit processes without all the fu= ss) > >=20 > > Writing > >=20 > > a <=3D b and c; > >=20 > > outside of a process is strictly equivalent to > >=20 > > process (b, c) > > begin > > a <=3D b and c; > > end process; > >=20 > > You can therefore write > >=20 > > a <=3D b and c; > > d <=3D a or e; > >=20 > > and it will give you exactly d <=3D (b and c) or e; > > as long as it's NOT in a process. > >=20 > > Nicolas >=20 > Thanks for the explanation ... it comes together step by step. and that i= s why I am doing this as a learning experience based on an already existing= design I did within the nand2tetris course with a very simplified HDL. >=20 > Actually the HDL has only structural design and also comes with nothing l= ike processes... My journey goes on now with mixed design and then getting = into a full behavioural implementation. As Rick mentioned ... obviously I c= ould simply use sum=3Da+b; and would be fine. But that was to easy :-) You might get more applicable experience trying to program something with a= state machine. That can let you see the advantages and disadvantages of p= rocesses, procedures, functions and just plain old concurrent logic and for= get about coding structurally... I mean as a low level technique stringing = gates together.=20 One that is often taught in school is an elevator. You can start with one = that goes between two floors. There is one in a building I frequent and od= dly enough it has two buttons, 1 and 2 rather than the one button required = since you don't really have a choice where to go. You just need an "other = floor" button. =20 Maybe I'll go into the elevator business and specialize in simplified eleva= tor controls. One button takes you to a random floor. You keep pushing it= until you get where you want to go.=20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:33 2024 X-Received: by 2002:ac8:3f5d:: with SMTP id w29mr4749772qtk.192.1589975736047; Wed, 20 May 2020 04:55:36 -0700 (PDT) X-Received: by 2002:a5b:5c6:: with SMTP id w6mr6321759ybp.188.1589975735688; Wed, 20 May 2020 04:55:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 May 2020 04:55:35 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=124.123.105.58; posting-account=QiLJMgoAAABpeHrmeV7h834rj2EKvTyA NNTP-Posting-Host: 124.123.105.58 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: System Verilog From: avanikvh123@gmail.com Injection-Date: Wed, 20 May 2020 11:55:36 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9693 In a simple up counter , how do I make the number of bits of the counter programmable? From newsfish@newsfish Thu Aug 1 00:45:34 2024 X-Received: by 2002:ad4:4d44:: with SMTP id m4mr7405912qvm.236.1590014829956; Wed, 20 May 2020 15:47:09 -0700 (PDT) X-Received: by 2002:a25:2a8c:: with SMTP id q134mr13847469ybq.143.1590014829740; Wed, 20 May 2020 15:47:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 May 2020 15:47:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <826c151d-845b-49f4-b0e6-a0a7767a1a4e@googlegroups.com> Subject: Re: System Verilog From: Rick C Injection-Date: Wed, 20 May 2020 22:47:09 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9694 On Wednesday, May 20, 2020 at 7:55:38 AM UTC-4, avani...@gmail.com wrote: > In a simple up counter , how do I make the number of bits of the counter programmable? You might try asking in the Verilog group rather than a VHDL group. While there certainly are people here familiar with System Verilog, you can expect more of them in the Verilog newsgroup. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:34 2024 X-Received: by 2002:aed:3aa3:: with SMTP id o32mr17662949qte.364.1591479492569; Sat, 06 Jun 2020 14:38:12 -0700 (PDT) X-Received: by 2002:a25:4487:: with SMTP id r129mr27203487yba.14.1591479492196; Sat, 06 Jun 2020 14:38:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Jun 2020 14:38:11 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=31.31.151.104; posting-account=fqiLNwoAAACxh6M36Pnzf8NP-rvFKYRV NNTP-Posting-Host: 31.31.151.104 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: =?UTF-8?Q?=C3=89_DA_ARRESTARE_L=27AVVOCATO_KILLER_DANIELE_MINOTTI=21_?= =?UTF-8?Q?=C3=89_DAVVERO_DA_ARRESTARE_L=27AVVOCATO_SATANISTA=2C_PEDOSATANISTA=2C?= =?UTF-8?Q?_NAZISTA=2C_SATANAZISTA=2C_MASSONE_DI_TIPO_ASSASSINO=2C_PEDOFILO_D?= =?UTF-8?Q?ANIELE_MINOTTI_DI_CRIMINALISSIMO_STUDIO_LEGALE_LISI=21?= From: SIMONA PREMOLI EX MARINA-BERLUSCONI-S LESBIAN-LOVER Injection-Date: Sat, 06 Jun 2020 21:38:12 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 549 Xref: reader01.eternal-september.org comp.lang.vhdl:9695 =C3=89 DA ARRESTARE L'AVVOCATO ASSASSINO DANIELE MINOTTI! =C3=89 DAVVERO DA= ARRESTARE L'AVVOCATO SATANISTA, PEDOSATANISTA, NAZISTA, SATANAZISTA, MASSO= NE DI TIPO OMICIDA, PEDOFILO, ASSASSINO DANIELE MINOTTI DI CRIMINALISSIMO S= TUDIO LEGALE LISI: RAPISCE, INCULA, AMMAZZA TANTI BAMBINI PER VENDERNE GLI = ORGANI! COME DA QUESTA ABERRANTE FOTO https://steemitimages.com/p/3auKdN6FdQE37hxp1zh1p7U4iqfKLDE9AdpKRQpQV5g36Go= ZLfg7ABa1V4fE2z?format=3Dmatch&mode=3Dfit&width=3D640 E' DAVVERO DA ARRESTARE IMMEDIATAMENTE L'AVV ASSASSINO E PEDERASTA DANIELE = MINOTTI DI RAPALLO E GENOVA: IL NOTISSIMO PEDOFILO INCULA ED AMMAZZA BAMBIN= I DANIELE MINOTTI!!! AVVOCATO MALAVITOSISSIMO, STUPRANTE INFANTI ED ADOLESC= ENTI, COME PURE OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LI= SI DI LECCE E MILANO E DI CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDIO LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI= MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PIU' = DI SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! = E' STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA ED UCCIDE= I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO DANIELE MINOTTI! QUESTO AVVOCATO= SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI RAPALLO= E GENOVA. https://www.flickr.com/photos/danieleminotti/ RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://www.py.cz/pipermail/python/2017-March/012979.html 1 OGNI SETTIMANA SGOZZA OLTRE CHE CANI, GATTI E SERPENTI, TANTI BAMBINI, IN R= ITI SATANICI. IN TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEGUONO.. = I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMAZZATI, = FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRIO DALL'= AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI DI RAPALLO E GENO= VA https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI MEGA OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://genova.repubblica.it/cronaca/2011/06/14/news/riti_voodoo_al_cimiter= o_di_staglieno-17668927/ https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO KILLER= , NAZISTA E PEDOFILO, STUPRANTE ED UCCIDENTE BAMBINI SU BAMBINI: DANIELE MI= NOTTI DI RAPALLO E GENOVA! Criminalissimo Studio Cirenei Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg ). A CAPO, ANZI, A KAPO' DI SETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA = ASSASSINA CHIAMATA " AMMAZZIAMO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCO= NI". E' AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GE= NOVA E RAPALLO. VEDI QUESTO LINK https://www.py.cz/pipermail/python/2017-April/013002.html UNITO IN CIO' AL PARIMENTI AVVOCATO MASSONE, NAZISTA, LADRO, TRUFFATORE, RI= CICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPPOLITO= . ED AI PARIMENTI SATANAZISTI, CORROTTI, MEGA COCAINOMANI E NOTISSIMI PEDOF= ILI MARIO GIORDANO, CLAUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSE= LMA DEL'OLIO ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTA= TO REGISTA PEDERASTA INCULA BAMBINI GIUSEPPE LAZZARI DI BRESCIA http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 ( CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, E' PAPPA = E CICCIA CON LA PURE MOLTISSIMO PEDOFILA ANSELMA DELL'OLIO STESSA https://www.imdb.com/title/tt1828287/reviews http://www.sentirsidire.it/su-di-me/ VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO A QUESTO LINK https://www.youtube.com/watch?v=3DDLR-DJJWl_M RIPORTANTE UNA TRASMISSIONE DEL NOIOSISSIMO GIGI MARZULLO, CON LA TROIONA S= TUPRA BAMBINI ANSELMA DELL'OLIO ED IL REGISTA PEDERASTA INCULA BAMBINI GIUS= EPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLETTUALMENTE, DIFENDENDO E PR= UOMOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULLLALA' CHE CASO, LA SCHIFOSA= MENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORCO NAZISTA, FIGLIO DI CANE, DA S= EMPRE SUPER PEDERASTA GIULIANO FERRARA, INSIEME AL REGISTA PEDOFILO STUPRA = BAMBINI GIUSEPPE LAZZARI, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN FATTO LEVA= RE... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI CIO' CHE VINCENT= ISSIMAMENTE STIAM QUI SCRIVENDO). IL TUTTO INSIEME ANCHE AL TRE VOLTE FINIT= O IN GALERA PAOLO BARRAI DI CRIMINALISSIMA BITCOIN CRYPTOECONOMY, DI CRIMIN= ALISSIMA BITINCUBATOR & VENTURE, DI CRIMINALISSIMA CRYPTOPOLYS, CRIMINALISS= IMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMINALISSIMO BLOG MERCATO "MERDATO"= LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL GLOBO TERRESTRE, COME "IL PEDOFI= LO DEL BITCOIN" https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg https://twitter.com/megliomortiche1 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ). 2 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). =E3=80=80 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 4 E POI ANCORA.. http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! =E3=80=80 5 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ =E3=80=80 =E3=80=80 6 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html https://twitter.com/LavaPaolo ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg 7 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/company D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ =E3=80=80 8 AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://www.instagram.com/p/Bcc0zWonbtv/ E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO https://www.spreaker.com/user/10297125 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". 9 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA ANSELMA DELL=E2=80=99OLIO E GIUSEPPE LAZZARI,= VI FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIP= O QUESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/ https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!! 10 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! https://www.py.cz/pipermail/python/2018-February/013212.html 11 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o) Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:45:34 2024 X-Received: by 2002:a37:2710:: with SMTP id n16mr26492101qkn.149.1591679883790; Mon, 08 Jun 2020 22:18:03 -0700 (PDT) X-Received: by 2002:a5b:843:: with SMTP id v3mr3817696ybq.106.1591679883586; Mon, 08 Jun 2020 22:18:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Jun 2020 22:18:03 -0700 (PDT) In-Reply-To: <1c9fafc3-8654-4082-9785-c47f58e7d456@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2a02:908:953:1b00:641f:f493:a809:d299; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 2a02:908:953:1b00:641f:f493:a809:d299 References: <1c9fafc3-8654-4082-9785-c47f58e7d456@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <57af41b2-37f0-44f9-b929-1bcbc5f23096o@googlegroups.com> Subject: Re: breaking an image into blocks and compute histogram of each block using vhdl From: Nikolaos Kavvadias Injection-Date: Tue, 09 Jun 2020 05:18:03 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9696 =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, 15 =CE= =9C=CE=B1=CE=90=CE=BF=CF=85 2020 - 6:40:14 =CE=BC.=CE=BC. UTC+2, =CE=BF =CF= =87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 rsde...@gmail.com =CE=AD=CE=B3=CF= =81=CE=B1=CF=88=CE=B5: > How to break an image into blocks and compute histogram of each block usi= ng vhdl ? I have to break an image of 128*128 into 16 *16 blocks and need t= o compute the histogram of each block...=20 >=20 > Please help me at the earliest...thanks Why not try to implement this in C/C++ and HLS? See Chapter 8.2 in http://kastner.ucsd.edu/wp-content/uploads/2018/03/admin= /pp4fpgas.pdf From newsfish@newsfish Thu Aug 1 00:45:35 2024 X-Received: by 2002:a0c:e941:: with SMTP id n1mr28779888qvo.105.1592948447122; Tue, 23 Jun 2020 14:40:47 -0700 (PDT) X-Received: by 2002:a25:3c85:: with SMTP id j127mr39668790yba.359.1592948446727; Tue, 23 Jun 2020 14:40:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 23 Jun 2020 14:40:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=104.163.189.179; posting-account=1KJTegoAAACNNjO5X1C7vepo2eo2ZuCe NNTP-Posting-Host: 104.163.189.179 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: process problem in VHDL From: albert.pierre1000@gmail.com Injection-Date: Tue, 23 Jun 2020 21:40:47 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9697 Hello, I'm working on a project using a CPLD. All the functions of my code are wor= king, but the overcurrent detection (OCD). It's been long time since I used VHDL. So I'm a bit rusted. I would aprecia= te it , if someone could have a look at my problem. The function is not so complicated. When I receive the OCD signal (DOI4, ac= tive low), I need to raise a flag as an output (OCD_FLAG) set to '1' for sa= y 1 sec, then to '0' for another 1 sec. During the period when the signal O= CD_FLAG is set to '1', the load will be disconnected so the circuitry will = not report an OCD anymore (even if it is still present) so the signal DOI(4= ) should be 1 (deactivated).=20 The idea is to cut off the load of the circuit when an overcurrent is detec= ted, let some time for the component to lower their temperature, then react= ivate the load during 1 sec and after that period check if the overcurrent = is still here. here is the signal declared earlier in the code: -- inputs DOI :in std_logic_vector(10 DOWNTO 1); (my inputs signals: DOI(= 4) is used for the overcurrent CPLD_CLK :in std_logic; CLOSE_OUT :in std_logic; -- outputs OCD_FLAG :out std_logic; --internal signals RST :in std_logic; signal OCD_CNT : std_logic_vector(20 downto 0) :=3D "00000000000000= 0000000"; here is a bit of my code: HICCUP: process (RST,CLOSE_OUT,CPLD_CLK) begin elsif (rising_edge(CPLD_CLK)) then -- deactivation if DOI(4) =3D '0' then=20 if OCD_CNT(20) =3D '0' then OCD_CNT <=3D OCD_CNT + 1; end if; else=20 OCD_CNT <=3D '0' & OCD_CNT(20 downto 1); end if; -- shotdown duration if OCD_CNT(20) =3D '1' then=20 OCD_CNT <=3D OCD_CNT + 1; end if; end if; end process; OCD_FLAG <=3D OCD_CNT(20); the problem I have is that the OCD_FLAG never change its state. always '1'. I try a solution using while....loop but I'm not sure I can use this comman= d in a process.=20 If there is a simple way I'm interested in any information that can help me= to progress. Thank you, Pierre From newsfish@newsfish Thu Aug 1 00:45:35 2024 X-Received: by 2002:a05:620a:1456:: with SMTP id i22mr22390083qkl.423.1592954937193; Tue, 23 Jun 2020 16:28:57 -0700 (PDT) X-Received: by 2002:a5b:843:: with SMTP id v3mr42878548ybq.106.1592954936928; Tue, 23 Jun 2020 16:28:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 23 Jun 2020 16:28:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: process problem in VHDL From: Rick C Injection-Date: Tue, 23 Jun 2020 23:28:57 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9698 On Tuesday, June 23, 2020 at 5:40:49 PM UTC-4, albert.p...@gmail.com wrote: > Hello, >=20 > I'm working on a project using a CPLD. All the functions of my code are w= orking, but the overcurrent detection (OCD). >=20 > It's been long time since I used VHDL. So I'm a bit rusted. I would aprec= iate it , if someone could have a look at my problem. >=20 > The function is not so complicated. When I receive the OCD signal (DOI4, = active low), I need to raise a flag as an output (OCD_FLAG) set to '1' for = say 1 sec, then to '0' for another 1 sec. During the period when the signal= OCD_FLAG is set to '1', the load will be disconnected so the circuitry wil= l not report an OCD anymore (even if it is still present) so the signal DOI= (4) should be 1 (deactivated).=20 >=20 > The idea is to cut off the load of the circuit when an overcurrent is det= ected, let some time for the component to lower their temperature, then rea= ctivate the load during 1 sec and after that period check if the overcurren= t is still here. >=20 > here is the signal declared earlier in the code: >=20 > -- inputs > DOI :in std_logic_vector(10 DOWNTO 1); (my inputs signals: DO= I(4) is used for the overcurrent > CPLD_CLK :in std_logic; > CLOSE_OUT :in std_logic; > -- outputs > OCD_FLAG :out std_logic; >=20 > --internal signals > RST :in std_logic; > signal OCD_CNT : std_logic_vector(20 downto 0) :=3D "000000000000= 000000000"; >=20 >=20 > here is a bit of my code: >=20 > HICCUP: process (RST,CLOSE_OUT,CPLD_CLK) > begin > elsif (rising_edge(CPLD_CLK)) then > -- deactivation > if DOI(4) =3D '0' then=20 > if OCD_CNT(20) =3D '0' then > OCD_CNT <=3D OCD_CNT + 1; > end if; > else=20 > OCD_CNT <=3D '0' & OCD_CNT(20 downto 1); > end if; > -- shotdown duration > if OCD_CNT(20) =3D '1' then=20 > OCD_CNT <=3D OCD_CNT + 1; > end if; > end if; > end process; >=20 > OCD_FLAG <=3D OCD_CNT(20); >=20 >=20 > the problem I have is that the OCD_FLAG never change its state. always '1= '. >=20 > I try a solution using while....loop but I'm not sure I can use this comm= and in a process.=20 > If there is a simple way I'm interested in any information that can help = me to progress. It sounds to me like you want to time OCD_FLAG high for a second and then l= ow for a second triggered by DOI(4) being high. Once the end of this two s= econd cycle is reached the function should be back in it's starting state w= here it can resume waiting for DOI(4) to go high. =20 You haven't shown all of the code for this process, but why is CLOSE_OUT in= the sensitivity list? That typically won't cause a problem in simulation = or synthesis though. =20 I think the problem is just your implementation of the state machine. I do= n't know how you initialize the counter, but I don't understand your handli= ng of it. You have two independent conditionals to control the counter. Y= ou may not realize that whichever assignment is last made to the counter is= the one that takes effect. So while DOI(4) is '0' the counter will free r= un. Is DOI(4) =3D '0' the active state or is '1' the active state? =20 The counter will free run because while DOI(4) is '0' and the counter msb i= s '0' it will be incremented in the first conditional. Then when the count= er msb is '1' it will continue to be incremented since this is the last ass= ignment and will take precedence. So the counter will be in an arbitrary s= tate at any given time. =20 When DOI(4) is '1' the counter is right shifted with the msb becoming '0'..= . unless it is already a '1' in which case the final assignment has precede= nce again and simply increments it.=20 I think you just need to look at your logic. Try drawing a state machine. = There will be two states, asserting OCD_FLAG and not asserting the flag. = Once the counter reaches a terminal count it should stop. This will requir= e detecting the terminal count just before rolling over to setting the msb.= =20 I would use a down counter. Then the terminal count is zero. When the DOI= (4) signal is asserted you can resume the count down with the next count se= tting the OCD_FLAG (counter msb). After that the count down will resume un= til it reaches zero again.=20 You can even avoid the extra logic of the zero comparison by detecting that= the next count msb is '1'. That requires separating the counter register = from the counter logic. So create a next count value in a concurrent logic= statement outside the process.=20 next_cnt <=3D cur_cnt - 1; process (... elsif (rising_edge(CPLD_CLK)) then=20 if (next_cnt /=3D -1) or (DOI(4) =3D '1') then cur_cnt <=3D next_cnt; end_if; end_if; end process; BTW, how are you incrementing an SLV? Shouldn't you be using a signed or u= nsigned data type? If you use a signed type you can use my trick above whi= ch should make use of the carry out from the counter carry chain.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:35 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer02.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx12.am4.POSTED!not-for-mail Newsgroups: comp.lang.vhdl X-Mozilla-News-Host: news://news.virginmedia.com:119 Reply-To: hans64@htminuslab.com From: HT-Lab Subject: VHDL2019 info User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200624-2, 24/06/2020), Outbound message X-Antivirus-Status: Clean Lines: 9 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 25 Jun 2020 11:08:59 UTC Organization: virginmedia.com Date: Thu, 25 Jun 2020 12:08:59 +0100 X-Received-Bytes: 1087 X-Received-Body-CRC: 3319710027 Xref: reader01.eternal-september.org comp.lang.vhdl:9699 I stumbled across this link which has some good VHDL2019 info: https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/ Make sure to raise Service Requests with your simulator vendor for the feature you want to see added. If we don't ask the answer is always no.... Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:45:36 2024 X-Received: by 2002:ac8:3a84:: with SMTP id x4mr3855986qte.361.1597190866285; Tue, 11 Aug 2020 17:07:46 -0700 (PDT) X-Received: by 2002:a25:5056:: with SMTP id e83mr53277632ybb.507.1597190866004; Tue, 11 Aug 2020 17:07:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 11 Aug 2020 17:07:45 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=50.35.94.116; posting-account=MCuIyAoAAABhyXJvMbOBS9PDz4_d4m08 NNTP-Posting-Host: 50.35.94.116 References: <7255ca83-e552-4591-969e-910b23c47e57@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f065ca4-70de-453c-86a9-ccf3e7b73efeo@googlegroups.com> Subject: Re: Code Review: SPI Transmitter From: Rob Anderson Injection-Date: Wed, 12 Aug 2020 00:07:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9700 For the core SPI lets keep it brief, the SPI interface is basically just a = shift register and it combines the transmitter and receiver. The clock come= s from an external source so resynchronization needs to be done but I would= argue that belongs outside of the SPI component; normally what I do is mak= e a couple holding registers and use a single phase semaphore (t-flop). It is better to use a uart if there is a reliable clock available, the SPI = clock is asynchronous and unpredictable. Here is my SPI block, it has been in several ASICs. There was once a schema= tic version. There are a couple signals to the external interface to trigge= r command interpretation or writing the data. Feel free to use it as GPL2 -- spi_block.vhd is the SPI communication interface -- simple 8 bit interface.=20 -- CPOL=3D0, CPHA=3D1 (shift output on low edge, capture rising edge) -- Note: first bit is high bit which is driven when CSB goes low. -- ldcr=3D1 on load cycle, cyc_6=3D1 on interpret cycle before this -- ld data will parallel load on ldcr=3D1 cycle. -- LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; use work.misc_pkg.all; ENTITY spi_block IS PORT ( OBUF: OUT byte; CR : OUT byte; ld : IN byte; SCK : IN std_logic; MOSI : IN std_logic; CSB : IN std_logic; MISO : OUT std_logic; ldcr : OUT std_logic; cyc_6 : OUT std_logic ); END spi_block; architecture rtl of spi_block is -- output mapping signal CRi,mx : byte; signal misoi,ldcri,cyc_6i : std_logic; signal miso_d:std_logic; -- init by POR -- internal signals signal ct: std_logic_vector(2 downto 0); -- 8 count signal sh_ldn : std_logic; begin -- mappings: OBUF<=3Dmx; MISO <=3D misoi after 2 ns; ldcr <=3D ldcri; cyc_6 <=3D cyc_6i; CR <=3D CRi after 2 ns; CRi(0) <=3D MOSI; CRi(7 downto 1) <=3D mx(6 downto 0); ldcri <=3D '1' when ct =3D "111" else '0'; cyc_6i <=3D '1' when ct =3D "110" else '0'; sh_ldn <=3D '0' when ct =3D "000" else '1'; miso_d<=3Dld(7) when sh_ldn=3D'0' else mx(7); -- mux for miso data at start -- Count the bits output on falling edge, parallel load when =3D"111" process(SCK,CSB) begin if (CSB=3D'1') then ct <=3D (others=3D>'0') ; elsif (SCK'event and SCK=3D'0') then ct <=3D std_logic_vector(signed(ct) + 1) ; end if; end process; -- use a latch for MISO to provide setup and hold for the master. -- make sure this synthesizes a latch process(SCK,miso_d)=20 begin -- MISO latch if SCK =3D '0' then=20 misoi<=3Dmiso_d;=20 end if; end process; -- IO is a parallel load shift register. -- this will be done by gated register. process(SCK) begin if (SCK'event and SCK=3D'1') then -- load and shift on + edge if CSB=3D'0' then mx(0) <=3D mosi; if sh_ldn=3D'0' then -- load at first clock mx(7 downto 1) <=3D ld(6 downto 0); else mx(7 downto 1) <=3D mx(6 downto 0); end if; end if; end if; end process; end rtl; -- spi_block From newsfish@newsfish Thu Aug 1 00:45:36 2024 X-Received: by 2002:a0c:e8c9:: with SMTP id m9mr12310084qvo.178.1598405275296; Tue, 25 Aug 2020 18:27:55 -0700 (PDT) X-Received: by 2002:a25:da02:: with SMTP id n2mr17803352ybf.316.1598405274846; Tue, 25 Aug 2020 18:27:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Aug 2020 18:27:54 -0700 (PDT) In-Reply-To: <826c151d-845b-49f4-b0e6-a0a7767a1a4e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2606:a000:1127:d3ec:7903:d9a9:34f0:aa1e; posting-account=EzNFQQoAAACdg0shgQS8psfoinOcIDNu NNTP-Posting-Host: 2606:a000:1127:d3ec:7903:d9a9:34f0:aa1e References: <826c151d-845b-49f4-b0e6-a0a7767a1a4e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: System Verilog From: Yasaswini Ravuri Injection-Date: Wed, 26 Aug 2020 01:27:55 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 11 Xref: reader01.eternal-september.org comp.lang.vhdl:9701 On Wednesday, May 20, 2020 at 6:47:11 PM UTC-4, gnuarm.del...@gmail.com wrote: > On Wednesday, May 20, 2020 at 7:55:38 AM UTC-4, avani...@gmail.com wrote: > > In a simple up counter , how do I make the number of bits of the counter programmable? > You might try asking in the Verilog group rather than a VHDL group. While there certainly are people here familiar with System Verilog, you can expect more of them in the Verilog newsgroup. > > -- > > Rick C. > > - Get 1,000 miles of free Supercharging > - Tesla referral code - https://ts.la/richard11209 could you give me the link to the group please? From newsfish@newsfish Thu Aug 1 00:45:36 2024 X-Received: by 2002:a0c:b51c:: with SMTP id d28mr12407064qve.71.1598412366959; Tue, 25 Aug 2020 20:26:06 -0700 (PDT) X-Received: by 2002:a5b:947:: with SMTP id x7mr20723477ybq.106.1598412366786; Tue, 25 Aug 2020 20:26:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Aug 2020 20:26:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:ede8:1be1:e769:7a1b; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:ede8:1be1:e769:7a1b References: <826c151d-845b-49f4-b0e6-a0a7767a1a4e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: System Verilog From: Rick C Injection-Date: Wed, 26 Aug 2020 03:26:06 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 21 Xref: reader01.eternal-september.org comp.lang.vhdl:9702 On Tuesday, August 25, 2020 at 9:27:57 PM UTC-4, Yasaswini Ravuri wrote: > On Wednesday, May 20, 2020 at 6:47:11 PM UTC-4, gnuarm.del...@gmail.com wrote: > > On Wednesday, May 20, 2020 at 7:55:38 AM UTC-4, avani...@gmail.com wrote: > > > In a simple up counter , how do I make the number of bits of the counter programmable? > > You might try asking in the Verilog group rather than a VHDL group. While there certainly are people here familiar with System Verilog, you can expect more of them in the Verilog newsgroup. > > > > -- > > > > Rick C. > > > > - Get 1,000 miles of free Supercharging > > - Tesla referral code - https://ts.la/richard11209 > could you give me the link to the group please? I don't know about link, but it should be where ever you found this group, but up one level and then under verilog. comp.lang.verilog. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:37 2024 X-Received: by 2002:a0c:b626:: with SMTP id f38mr3189899qve.0.1599156950997; Thu, 03 Sep 2020 11:15:50 -0700 (PDT) X-Received: by 2002:a25:ef44:: with SMTP id w4mr4330566ybm.188.1599156950843; Thu, 03 Sep 2020 11:15:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Sep 2020 11:15:50 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <85170ff5-a937-4c16-96e4-c0c4cbcbfb1co@googlegroups.com> Subject: What is a Processor and Software in Context of Reliability Analysis? From: Rick C Injection-Date: Thu, 03 Sep 2020 18:15:50 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 45 Xref: reader01.eternal-september.org comp.lang.vhdl:9703 How is a "processor" defined when considering requirements on developing a = design? A project I am on is shoving software into HDL to design an FPGA w= hich is being considered "hardware". I'm not fighting it because FPGAs are= what I do. Board level design is a necessary evil to support the FPGA. If= not for the desire to make approval easier the FPGA would not be on the bo= ard. I'm concerned that the thinking it will take less effort to get approval on= the FPGA than approval on the equivalent software running on an MCU. I'm = not seeing a basis for this comparison. =20 The context is medical equipment, specifically a ventilator. I'm working o= n one of the many open source projects that have sprung up in response to C= OVID-19. =20 The functionality of the FPGA is to detect the alarm conditions. To do tha= t the FPGA requires sensor readings of pressures, O2 levels, temperature an= d a couple of voltages. Fixed calculations will be performed, not under co= ntrol of any software, rather state machines. The issue is whether any of = this constitutes "processor software" since at some level there is source c= ode that is compiled by tools. =20 Compare to the C programs being developed for the MCU as well as to the sch= ematic editors and layout software that are used to generate the Gerber fil= es and pick and place files for automated assembly. Where does the definition of "processor software" begin and end?=20 As an aside, I'm much more fluent in VHDL than Verilog. This project has a= number of members who are engineers with a well known British consumer pro= duct manufacturer. They seem to only work in Verilog, so they have yet to = find anyone who can participate in a code review.=20 If anyone here would like to help with the project we can use programmers a= nd especially someone to help with the requirements documents... what littl= e we have. OpenVent-Bristol https://openventbristol.co.uk/ Even better is someone with connections to companies who would be intereste= d in obtaining required approvals and manufacturing the devices.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:37 2024 X-Received: by 2002:a0c:b203:: with SMTP id x3mr22380657qvd.97.1599533070867; Mon, 07 Sep 2020 19:44:30 -0700 (PDT) X-Received: by 2002:a25:3754:: with SMTP id e81mr31163354yba.133.1599533070676; Mon, 07 Sep 2020 19:44:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Sep 2020 19:44:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:d810:d8f:7330:5534; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:d810:d8f:7330:5534 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Reverse ?? Operator From: Rick C Injection-Date: Tue, 08 Sep 2020 02:44:30 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9704 I'm starting a new project so I need to come up the learning curve again. = I always forget details of the language when I don't use it for some time. = =20 I think I'm not so much not remembering something that is in the language a= s it is I'm thinking of something that's NOT in the language, but I wish it= were. I'm probably mixing my poor recollection of C with my poor recollec= tion of VHDL. =20 VHDL has a ?? operator that converts a std_logic or bit value to Boolean. = It took me a while to realize I'm looking for something that does the oppos= ite, converts a Boolean to a std_logic value. =20 I can do what I want to do using when and else, but they tend to make the l= ine more crowded, so if the expression is a bit wordy (what isn't in VHDL) = it runs onto two lines. I also don't like the syntax which spreads the two= alternatives to opposite ends of the statement.=20 The syntax I'm remembering is something like=20 A <=3D condition ?? X : Y I think this is the C construct. I just have this image in my mind of this= being trotted out as a new VHDL feature, or something like it. =20 So someone tell me I'm totally misremembering it. I've dug the Internet an= d not found any gold. I'm pretty sure I would have found it if it were the= re.=20 Or is there a conversion for boolean to std_logic? I seem to remember sear= ching that the other day and finding nothing other than examples of your ow= n conversion function.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:37 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.mb-net.net!open-news-network.org!news.bgeserver.de!bgepartei.de!news2.open-news-network.org!.POSTED.109.180.43.180!not-for-mail From: Mike Perkins Newsgroups: comp.lang.vhdl Subject: Re: Reverse ?? Operator Date: Tue, 8 Sep 2020 13:36:10 +0100 Organization: news2.open-news-network.org Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 8 Sep 2020 12:36:10 -0000 (UTC) Injection-Info: news2.open-news-network.org; posting-host="109.180.43.180"; logging-data="8606"; mail-complaints-to="abuse@bgeserver.de" User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 In-Reply-To: Content-Language: en-GB Xref: reader01.eternal-september.org comp.lang.vhdl:9705 On 08/09/2020 03:44:30, Rick C wrote: > I'm starting a new project so I need to come up the learning curve again. I always forget details of the language when I don't use it for some time. > > I think I'm not so much not remembering something that is in the language as it is I'm thinking of something that's NOT in the language, but I wish it were. I'm probably mixing my poor recollection of C with my poor recollection of VHDL. > > VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I'm looking for something that does the opposite, converts a Boolean to a std_logic value. > > I can do what I want to do using when and else, but they tend to make the line more crowded, so if the expression is a bit wordy (what isn't in VHDL) it runs onto two lines. I also don't like the syntax which spreads the two alternatives to opposite ends of the statement. > > The syntax I'm remembering is something like > > A <= condition ?? X : Y > > I think this is the C construct. I just have this image in my mind of this being trotted out as a new VHDL feature, or something like it. > > So someone tell me I'm totally misremembering it. I've dug the Internet and not found any gold. I'm pretty sure I would have found it if it were there. > > Or is there a conversion for boolean to std_logic? I seem to remember searching that the other day and finding nothing other than examples of your own conversion function. That works for C. I presume you're looking for something like this? For VHDL s <= waveform_1 when condition_1 else waveform_2 when condition_2 else ... waveform_n; As per: https://www.ics.uci.edu/~alexv/154/VHDL-Cookbook.pdf In a process it would be more usual to use an if statement -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk From newsfish@newsfish Thu Aug 1 00:45:38 2024 X-Received: by 2002:a37:2cc1:: with SMTP id s184mr50925qkh.357.1599572110267; Tue, 08 Sep 2020 06:35:10 -0700 (PDT) X-Received: by 2002:a5b:287:: with SMTP id x7mr34647637ybl.144.1599572110034; Tue, 08 Sep 2020 06:35:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!xmission!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Sep 2020 06:35:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:d810:d8f:7330:5534; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:d810:d8f:7330:5534 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> Subject: Re: Reverse ?? Operator From: Rick C Injection-Date: Tue, 08 Sep 2020 13:35:10 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 73 Xref: reader01.eternal-september.org comp.lang.vhdl:9706 On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote: > On 08/09/2020 03:44:30, Rick C wrote: > > I'm starting a new project so I need to come up the learning curve agai= n. I always forget details of the language when I don't use it for some ti= me. > >=20 > > I think I'm not so much not remembering something that is in the langua= ge as it is I'm thinking of something that's NOT in the language, but I wis= h it were. I'm probably mixing my poor recollection of C with my poor reco= llection of VHDL. > >=20 > > VHDL has a ?? operator that converts a std_logic or bit value to Boolea= n. It took me a while to realize I'm looking for something that does the o= pposite, converts a Boolean to a std_logic value. > >=20 > > I can do what I want to do using when and else, but they tend to make t= he line more crowded, so if the expression is a bit wordy (what isn't in VH= DL) it runs onto two lines. I also don't like the syntax which spreads the= two alternatives to opposite ends of the statement. > >=20 > > The syntax I'm remembering is something like > >=20 > > A <=3D condition ?? X : Y > >=20 > > I think this is the C construct. I just have this image in my mind of = this being trotted out as a new VHDL feature, or something like it. > >=20 > > So someone tell me I'm totally misremembering it. I've dug the Interne= t and not found any gold. I'm pretty sure I would have found it if it were= there. > >=20 > > Or is there a conversion for boolean to std_logic? I seem to remember = searching that the other day and finding nothing other than examples of you= r own conversion function. >=20 > That works for C. I presume you're looking for something like this? >=20 > For VHDL > s <=3D waveform_1 when condition_1 else > waveform_2 when condition_2 else > ... > waveform_n; >=20 > As per: > https://www.ics.uci.edu/~alexv/154/VHDL-Cookbook.pdf >=20 > In a process it would be more usual to use an if statement Yeah, I'm trying to make this construct a simple one line piece of code. F= or the time being I've created a function: function b_to_sl (X : boolean) return std_logic is begin if X then return '1'; else return '0'; end if; end b_to_sl; Called thusly: Spkr_Blip <=3D b_to_sl(Button_Press(I) =3D Buttons_Past(I)); It just seems something like b_to_sl should/could be part of the language o= r a standard library. I noticed when I google searched on it, there was no= shortage of others asking the same question. =20 The above test is checking for a change in the button state. The input is = Buttons which is low true so Buttons_Past is low true while Button_Press is= the debounced version and high true. I think I should add Buttons_ht, a h= igh true version of the input signal and make everything from that point on= high true to keep the logic easier to read.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:38 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx26.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Reverse ?? Operator Newsgroups: comp.lang.vhdl References: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200907-8, 07/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 43 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Tue, 08 Sep 2020 15:21:50 UTC Organization: virginmedia.com Date: Tue, 8 Sep 2020 16:21:50 +0100 X-Received-Bytes: 2641 X-Received-Body-CRC: 2145423781 Xref: reader01.eternal-september.org comp.lang.vhdl:9707 On 08/09/2020 14:35, Rick C wrote: > On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote: >> On 08/09/2020 03:44:30, Rick C wrote: .. >>> VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I'm looking for something that does the opposite, converts a Boolean to a std_logic value. >>> .. > Yeah, I'm trying to make this construct a simple one line piece of code. For the time being I've created a function: > > function b_to_sl (X : boolean) return std_logic is begin > if X then return '1'; else return '0'; end if; end b_to_sl; > I hit exactly the same issue many years ago and a VHDL guru's called Tricky (if I remember correctly) suggested to use simple functions. Like most VHDL engineers I now have a package with lots of helper functions I collected over the years. Here is a good site with lots of conversion functions: https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html However, the reason for replying is that I also tried to use the ?? operator recently and failed to make it work, I had something like: if (?? (OR slvarray(1 downto 0)) OR (a > b)) then.. however, to make it work you need extra brackets as in : if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then.. Or to simplify, you need (??(non_boolean)) Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I just added the brackets and moved on with life..... I am sure somebody with more VHDL knowledge can explain why the extra (non-obvious) brackets are required. Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:45:38 2024 X-Received: by 2002:a0c:80c3:: with SMTP id 61mr341715qvb.13.1599588181464; Tue, 08 Sep 2020 11:03:01 -0700 (PDT) X-Received: by 2002:a5b:287:: with SMTP id x7mr134573ybl.144.1599588181181; Tue, 08 Sep 2020 11:03:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Sep 2020 11:03:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:d810:d8f:7330:5534; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:d810:d8f:7330:5534 References: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Reverse ?? Operator From: Rick C Injection-Date: Tue, 08 Sep 2020 18:03:01 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9708 On Tuesday, September 8, 2020 at 11:21:54 AM UTC-4, HT-Lab wrote: > On 08/09/2020 14:35, Rick C wrote: > > On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote: > >> On 08/09/2020 03:44:30, Rick C wrote: > .. > >>> VHDL has a ?? operator that converts a std_logic or bit value to Bool= ean. It took me a while to realize I'm looking for something that does the= opposite, converts a Boolean to a std_logic value. > >>> > .. > > Yeah, I'm trying to make this construct a simple one line piece of code= . For the time being I've created a function: > >=20 > > function b_to_sl (X : boolean) return std_logic is begin > > if X then return '1'; else return '0'; end if; end b_to_sl; > >=20 >=20 > I hit exactly the same issue many years ago and a VHDL guru's called=20 > Tricky (if I remember correctly) suggested to use simple functions. Like= =20 > most VHDL engineers I now have a package with lots of helper functions I= =20 > collected over the years. Here is a good site with lots of conversion=20 > functions: >=20 > https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-t= o-integer.html >=20 > However, the reason for replying is that I also tried to use the ??=20 > operator recently and failed to make it work, I had something like: >=20 > if (?? (OR slvarray(1 downto 0)) OR (a > b)) then.. >=20 > however, to make it work you need extra brackets as in : >=20 > if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then.. >=20 > Or to simplify, you need (??(non_boolean)) >=20 > Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I= =20 > just added the brackets and moved on with life..... >=20 > I am sure somebody with more VHDL knowledge can explain why the extra=20 > (non-obvious) brackets are required. >=20 > Hans > www.ht-lab.com Can't say for sure, but likely it's a matter of precedence. The second OR = tries to operate on the boolean and the std_logic from the first OR before = the ?? has had a chance to do its thing. The extra set of parenthesis set = the order straight. =20 When I do my work I use a library or two, but this a many years collection = of stuff, much of which is obsolete, but still is needed by some code, some= where. I will need to start a project specific package at some point just = like I'm going to need to split the HDL into multiple files for multiple en= tities rather than putting them all together in one. =20 For now I'm just focusing on getting some functionality going. =20 I'm using the Lattice tools with ActiveHDL for simulation which I've used m= any time. It seems to only work with files located in the source directory= within the project. I can add a source file from outside of the project, = but it gets copied into the project directory. =20 I don't want to have to use their project directory for the source files be= cause they are essentially commingled with the other 5 billion trash files = every design creates which I have no interest in backing up. Is there a wa= y to tell it to work with the files in *MY* directory which is not in the p= roject? I thought I knew how to do this, but I guess not. It's not easy t= o find info on this sort of thing. I did find one page that simply says, "= don't fight with the tools, the tools always win." =20 :(=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:38 2024 X-Received: by 2002:a37:6786:: with SMTP id b128mr1696604qkc.396.1599623967769; Tue, 08 Sep 2020 20:59:27 -0700 (PDT) X-Received: by 2002:a25:ef44:: with SMTP id w4mr2875726ybm.188.1599623967537; Tue, 08 Sep 2020 20:59:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Sep 2020 20:59:27 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:1c4d:377e:c6b:c170; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:1c4d:377e:c6b:c170 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Active HDL From: Rick C Injection-Date: Wed, 09 Sep 2020 03:59:27 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9709 I don't recall having much difficulty when using the Aldec Active-HDL simul= ator before. This time I'm having trouble figuring out the controls. =20 I can't find a control to stop the simulation if it is into a long run and = early on I see a something I want to investigate. The only controls that s= eem to stop the simulation kill the waveform data. What's worse is the "En= d simulation" control also loses track of the top of Top-Level module so it= has to be reset to run again. The help file isn't much good at searching f= or info on this. =20 I've tried to figure out how to get the tool to save all the signals data s= o I don't have to rerun the simulation every time I think of a new signal I= want to see. Again, the manual isn't much help because it points me to a = setting to allow all signals to be saved, but that control is grayed out an= d I can't find anything explaining why. Even a Google search doesn't find = anything. =20 What is just as bad or worse is that the durn tools make copies of your sou= rce files rather than working with the ones you create and presumably edit.= So for now I'm copying the files over to the project directory with each = edit. =20 I seem to recall being fairly effective using this tool in the past. Has t= he tool changed that much or have I?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsreader4.netcologne.de!news.netcologne.de!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.ams4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!buffer1.nntp.dca1.giganews.com!buffer2.nntp.dca1.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 09 Sep 2020 09:38:40 -0500 Reply-To: mk@mkesc.co.uk Subject: Re: Active HDL Newsgroups: comp.lang.vhdl References: From: Michael Kellett Date: Wed, 9 Sep 2020 15:38:42 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Message-ID: <4rOdnZQXbNttdcXCnZ2dnUU7-IXNnZ2d@giganews.com> Lines: 25 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-yZQDJutPXoZoPLaRR5n9Q522MgU14rKEgmvUXomkEGjMhrxQ8dP+l7p7suCWclST+Z3HGudepzB4HS/!3sPG6p2FQnF68N0k1VAj2YRpJ/W1y61aKmJ31rY/99bftrhxjrhQmngL3+biYbfEkZ4fxsnA7+oH X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3009 X-Received-Bytes: 3292 X-Received-Body-CRC: 578959877 Xref: reader01.eternal-september.org comp.lang.vhdl:9710 On 09/09/2020 04:59, Rick C wrote: > I don't recall having much difficulty when using the Aldec Active-HDL simulator before. This time I'm having trouble figuring out the controls. > > I can't find a control to stop the simulation if it is into a long run and early on I see a something I want to investigate. The only controls that seem to stop the simulation kill the waveform data. What's worse is the "End simulation" control also loses track of the top of Top-Level module so it has to be reset to run again. The help file isn't much good at searching for info on this. > > I've tried to figure out how to get the tool to save all the signals data so I don't have to rerun the simulation every time I think of a new signal I want to see. Again, the manual isn't much help because it points me to a setting to allow all signals to be saved, but that control is grayed out and I can't find anything explaining why. Even a Google search doesn't find anything. > > What is just as bad or worse is that the durn tools make copies of your source files rather than working with the ones you create and presumably edit. So for now I'm copying the files over to the project directory with each edit. > > I seem to recall being fairly effective using this tool in the past. Has the tool changed that much or have I? > Are you using a paid for version of the free one from Lattice ? I'm away from home and office this week (on hols) but I'll take a look when I get back. I usually design in Aldec and the FPGA tools are pointed at the source files it generates - so I don't get you copy problem. I think I usually run the simulation from start again if I add signals. I pay them a fortune for maintenance and support so I can ask the questions ! MK From newsfish@newsfish Thu Aug 1 00:45:39 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: Reverse ?? Operator Date: Wed, 9 Sep 2020 23:39:37 -0500 Organization: A noiseless patient Spider Lines: 66 Message-ID: References: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 10 Sep 2020 04:39:38 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="ff5360c16a0a89031831652966feff8d"; logging-data="14891"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+yQ+fjoho5ou3evdiWu91ksfztZ0YzK4s=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:Q8e/Sfm9mB5oTupOOhv3aZZiXr0= In-Reply-To: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> Xref: reader01.eternal-september.org comp.lang.vhdl:9711 On 2020-09-08 08:35, Rick C wrote: > On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote: >> On 08/09/2020 03:44:30, Rick C wrote: >>> I'm starting a new project so I need to come up the learning curve again. I always forget details of the language when I don't use it for some time. >>> >>> I think I'm not so much not remembering something that is in the language as it is I'm thinking of something that's NOT in the language, but I wish it were. I'm probably mixing my poor recollection of C with my poor recollection of VHDL. >>> >>> VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I'm looking for something that does the opposite, converts a Boolean to a std_logic value. >>> >>> I can do what I want to do using when and else, but they tend to make the line more crowded, so if the expression is a bit wordy (what isn't in VHDL) it runs onto two lines. I also don't like the syntax which spreads the two alternatives to opposite ends of the statement. >>> >>> The syntax I'm remembering is something like >>> >>> A <= condition ?? X : Y >>> >>> I think this is the C construct. I just have this image in my mind of this being trotted out as a new VHDL feature, or something like it. >>> >>> So someone tell me I'm totally misremembering it. I've dug the Internet and not found any gold. I'm pretty sure I would have found it if it were there. >>> >>> Or is there a conversion for boolean to std_logic? I seem to remember searching that the other day and finding nothing other than examples of your own conversion function. >> >> That works for C. I presume you're looking for something like this? >> >> For VHDL >> s <= waveform_1 when condition_1 else >> waveform_2 when condition_2 else >> ... >> waveform_n; >> >> As per: >> https://www.ics.uci.edu/~alexv/154/VHDL-Cookbook.pdf >> >> In a process it would be more usual to use an if statement > > Yeah, I'm trying to make this construct a simple one line piece of code. For the time being I've created a function: > > function b_to_sl (X : boolean) return std_logic is begin > if X then return '1'; else return '0'; end if; end b_to_sl; > > Called thusly: > > Spkr_Blip <= b_to_sl(Button_Press(I) = Buttons_Past(I)); > > It just seems something like b_to_sl should/could be part of the language or a standard library. I noticed when I google searched on it, there was no shortage of others asking the same question. > > The above test is checking for a change in the button state. The input is Buttons which is low true so Buttons_Past is low true while Button_Press is the debounced version and high true. I think I should add Buttons_ht, a high true version of the input signal and make everything from that point on high true to keep the logic easier to read. > VHDL2008 contains functions to do comparisons of std_logic, which would normally return a Boolean result, but return a std_logic result. From the 2008 IEEE std_logic_1164.vhdl package source file: -- the following operations are predefined -- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC; -- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC; -- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC; -- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC; -- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC; -- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC; -- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC; -- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC; Charles Bailey From newsfish@newsfish Thu Aug 1 00:45:39 2024 X-Received: by 2002:a05:620a:4084:: with SMTP id f4mr9652752qko.449.1599761414858; Thu, 10 Sep 2020 11:10:14 -0700 (PDT) X-Received: by 2002:a25:c049:: with SMTP id c70mr14736066ybf.403.1599761414702; Thu, 10 Sep 2020 11:10:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Sep 2020 11:10:14 -0700 (PDT) In-Reply-To: <4rOdnZQXbNttdcXCnZ2dnUU7-IXNnZ2d@giganews.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <4rOdnZQXbNttdcXCnZ2dnUU7-IXNnZ2d@giganews.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Active HDL From: Rick C Injection-Date: Thu, 10 Sep 2020 18:10:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4655 X-Received-Body-CRC: 434280493 Xref: reader01.eternal-september.org comp.lang.vhdl:9712 On Wednesday, September 9, 2020 at 10:38:49 AM UTC-4, Michael Kellett wrote= : > On 09/09/2020 04:59, Rick C wrote: > > I don't recall having much difficulty when using the Aldec Active-HDL s= imulator before. This time I'm having trouble figuring out the controls. > >=20 > > I can't find a control to stop the simulation if it is into a long run = and early on I see a something I want to investigate. The only controls th= at seem to stop the simulation kill the waveform data. What's worse is the= "End simulation" control also loses track of the top of Top-Level module s= o it has to be reset to run again. The help file isn't much good at searchi= ng for info on this. > >=20 > > I've tried to figure out how to get the tool to save all the signals da= ta so I don't have to rerun the simulation every time I think of a new sign= al I want to see. Again, the manual isn't much help because it points me t= o a setting to allow all signals to be saved, but that control is grayed ou= t and I can't find anything explaining why. Even a Google search doesn't f= ind anything. > >=20 > > What is just as bad or worse is that the durn tools make copies of your= source files rather than working with the ones you create and presumably e= dit. So for now I'm copying the files over to the project directory with e= ach edit. > >=20 > > I seem to recall being fairly effective using this tool in the past. H= as the tool changed that much or have I? > >=20 > Are you using a paid for version of the free one from Lattice ? >=20 > I'm away from home and office this week (on hols) but I'll take a look=20 > when I get back. >=20 > I usually design in Aldec and the FPGA tools are pointed at the source=20 > files it generates - so I don't get you copy problem. >=20 > I think I usually run the simulation from start again if I add signals. >=20 > I pay them a fortune for maintenance and support so I can ask the=20 > questions ! I'm using the free version from Lattice. I did buy the Lattice tools once = and ordered the version with Modelsim. But before they shipped it they had= switched vendors. I was pretty pissed with the bait and switch, but got n= o traction with them. By the time I got over it I found I could barely tel= l the difference. =20 My usage tends to be very sporadic so rather than pay for maintenance I jus= t kept using the old version. But the last couple of laptop purchases rath= er than drag the licensing stuff around I just started using the free tool.= =20 So if you work in the directory location for the simulation tools, do you c= opy the files to the location for the synthesis tools? Or is the synthesis= tool more flexible? =20 My issue is that both tools create lots of chaff files that I don't want to= even see, much less back up. So I prefer to keep all my source files in a= directory tree separate from the tools. Then I back up everything in that= source directory tree making my life easy. Hmmmm... I think Windows has l= inks. Maybe I can create links in the tool /src directory that point to my= real source directory. I should work out the bugs while the file count is= still just two.=20 Thanks for the support. Enjoy your holiday.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:39 2024 X-Received: by 2002:ac8:c44:: with SMTP id l4mr10312941qti.2.1599775268030; Thu, 10 Sep 2020 15:01:08 -0700 (PDT) X-Received: by 2002:a25:8448:: with SMTP id r8mr14789116ybm.119.1599775267852; Thu, 10 Sep 2020 15:01:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Sep 2020 15:01:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Reverse ?? Operator From: Rick C Injection-Date: Thu, 10 Sep 2020 22:01:08 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 102 X-Received-Bytes: 5739 X-Received-Body-CRC: 2128683093 Xref: reader01.eternal-september.org comp.lang.vhdl:9713 On Thursday, September 10, 2020 at 12:39:42 AM UTC-4, Charles Bailey wrote: > On 2020-09-08 08:35, Rick C wrote: > > On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote: > >> On 08/09/2020 03:44:30, Rick C wrote: > >>> I'm starting a new project so I need to come up the learning curve ag= ain. I always forget details of the language when I don't use it for some = time. > >>> > >>> I think I'm not so much not remembering something that is in the lang= uage as it is I'm thinking of something that's NOT in the language, but I w= ish it were. I'm probably mixing my poor recollection of C with my poor re= collection of VHDL. > >>> > >>> VHDL has a ?? operator that converts a std_logic or bit value to Bool= ean. It took me a while to realize I'm looking for something that does the= opposite, converts a Boolean to a std_logic value. > >>> > >>> I can do what I want to do using when and else, but they tend to make= the line more crowded, so if the expression is a bit wordy (what isn't in = VHDL) it runs onto two lines. I also don't like the syntax which spreads t= he two alternatives to opposite ends of the statement. > >>> > >>> The syntax I'm remembering is something like > >>> > >>> A <=3D condition ?? X : Y > >>> > >>> I think this is the C construct. I just have this image in my mind o= f this being trotted out as a new VHDL feature, or something like it. > >>> > >>> So someone tell me I'm totally misremembering it. I've dug the Inter= net and not found any gold. I'm pretty sure I would have found it if it we= re there. > >>> > >>> Or is there a conversion for boolean to std_logic? I seem to remembe= r searching that the other day and finding nothing other than examples of y= our own conversion function. > >> > >> That works for C. I presume you're looking for something like this? > >> > >> For VHDL > >> s <=3D waveform_1 when condition_1 else > >> waveform_2 when condition_2 else > >> ... > >> waveform_n; > >> > >> As per: > >> https://www.ics.uci.edu/~alexv/154/VHDL-Cookbook.pdf > >> > >> In a process it would be more usual to use an if statement > > > > Yeah, I'm trying to make this construct a simple one line piece of code= . For the time being I've created a function: > > > > function b_to_sl (X : boolean) return std_logic is begin > > if X then return '1'; else return '0'; end if; end b_to_sl; > > > > Called thusly: > > > > Spkr_Blip <=3D b_to_sl(Button_Press(I) =3D Buttons_Past(I)); > > > > It just seems something like b_to_sl should/could be part of the langua= ge or a standard library. I noticed when I google searched on it, there wa= s no shortage of others asking the same question. > > > > The above test is checking for a change in the button state. The input= is Buttons which is low true so Buttons_Past is low true while Button_Pres= s is the debounced version and high true. I think I should add Buttons_ht,= a high true version of the input signal and make everything from that poin= t on high true to keep the logic easier to read. > > >=20 > VHDL2008 contains functions to do comparisons of std_logic, which would= =20 > normally return a Boolean result, but return a std_logic result. >=20 > From the 2008 IEEE std_logic_1164.vhdl package source file: > -- the following operations are predefined >=20 > -- function "?=3D" (l, r : STD_ULOGIC) return STD_ULOGIC; > -- function "?=3D" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC; >=20 > -- function "?/=3D" (l, r : STD_ULOGIC) return STD_ULOGIC; > -- function "?/=3D" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC; >=20 > -- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC; > -- function "?<=3D" (l, r : STD_ULOGIC) return STD_ULOGIC; > -- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC; > -- function "?>=3D" (l, r : STD_ULOGIC) return STD_ULOGIC; >=20 > Charles Bailey That works in this case. I was comparing two bits of unsigned for being no= t alike and wasn't thinking I could just XNOR them. Geeze! The ?/=3D work= s as well. Thanks It's been too long since I've used this language.=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:40 2024 X-Received: by 2002:a0c:8f02:: with SMTP id z2mr6731342qvd.21.1599776902851; Thu, 10 Sep 2020 15:28:22 -0700 (PDT) X-Received: by 2002:a5b:287:: with SMTP id x7mr16468424ybl.144.1599776902716; Thu, 10 Sep 2020 15:28:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader01.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Sep 2020 15:28:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=70.33.172.5; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 70.33.172.5 References: <4rOdnZQXbNttdcXCnZ2dnUU7-IXNnZ2d@giganews.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <25f26c9f-87dd-4715-96ec-eebda5adfdbco@googlegroups.com> Subject: Re: Active HDL From: Rick C Injection-Date: Thu, 10 Sep 2020 22:28:22 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9714 This thing is really starting to piss me off. I can't understand some of t= he things it does. Now the cursor won't stay where I put it. It keeps mov= ing to the end of the simulation a few seconds after I let go of it, EVEN I= F I'M STILL HOLDING ONTO IT WITH THE CURSOR!!!=20 I can drag it around as much as I like, but as soon as I pause on something= it will snap back to the end of the simulation time. Oh! It's not just t= he cursor, the view in the waveform window moves to include the end of the = simulation time as well. So I can't zoom in on anything else.=20 Is Aldec just trying to mess with me???=20 I would say the simulation was still running, but the last message in the c= onsole says, "# KERNEL: stopped at time: 4500 ms"=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:40 2024 X-Received: by 2002:ac8:1c43:: with SMTP id j3mr10442525qtk.302.1600023909064; Sun, 13 Sep 2020 12:05:09 -0700 (PDT) X-Received: by 2002:a25:3185:: with SMTP id x127mr15798410ybx.77.1600023908863; Sun, 13 Sep 2020 12:05:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!tncsrv06.tnetconsulting.net!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 13 Sep 2020 12:05:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <159a8f5a-6455-4039-8fa0-31a999e74892o@googlegroups.com> Subject: Generics Default vs. From: Rick C Injection-Date: Sun, 13 Sep 2020 19:05:09 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 27 X-Received-Bytes: 2163 X-Received-Body-CRC: 4117959367 Xref: reader02.eternal-september.org comp.lang.vhdl:9715 I use a generic to pass into the code a clock frequency as a real number in= MHz. When an entity needs to measure time it can use that value to set cl= ock counts. To make life simple (or maybe the opposite, not sure) I set a = default for each entity... ENTITY Spkr_Drvr IS GENERIC ( CLK_MHZ : REAL :=3D 16.000 ); port( ... I don't recall what made me adopt this method. But I believe I encountered= an instance where the generic was not passed in for whatever reason. I wo= uld expect that to be flagged as an error. But I expect it wasn't. =20 Anyway, I would expect a value passed into an entity to take the value pass= ed in and over ride the default value in the generic declaration. Is that = what will happen? I will have at least two levels of this. If the top lev= el gets a different value passed into it during simulation or in synthesis,= will the value passed in take precedence? =20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:40 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp1-2.free.fr!not-for-mail Subject: Re: Generics Default vs. Newsgroups: comp.lang.vhdl References: <159a8f5a-6455-4039-8fa0-31a999e74892o@googlegroups.com> From: Nicolas Matringe Date: Sun, 13 Sep 2020 21:55:39 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <159a8f5a-6455-4039-8fa0-31a999e74892o@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Lines: 9 Message-ID: <5f5e793b$0$13559$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 13 Sep 2020 21:55:39 CEST NNTP-Posting-Host: 88.123.153.23 X-Trace: 1600026939 news-4.free.fr 13559 88.123.153.23:6455 X-Complaints-To: abuse@proxad.net Xref: reader02.eternal-september.org comp.lang.vhdl:9716 On 2020-09-13 21:05, Rick C wrote: [...] > Anyway, I would expect a value passed into an entity to take the value passed in and over ride the default value in the generic declaration. Is that what will happen? I will have at least two levels of this. If the top level gets a different value passed into it during simulation or in synthesis, will the value passed in take precedence? > The answer is pretty short and straightforward : yes. I've been using this method for years without any problem. Nicolas From newsfish@newsfish Thu Aug 1 00:45:41 2024 X-Received: by 2002:a37:a0cf:: with SMTP id j198mr10390655qke.408.1600029738546; Sun, 13 Sep 2020 13:42:18 -0700 (PDT) X-Received: by 2002:a25:ef44:: with SMTP id w4mr15392925ybm.188.1600029738386; Sun, 13 Sep 2020 13:42:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 13 Sep 2020 13:42:18 -0700 (PDT) In-Reply-To: <5f5e793b$0$13559$426a34cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <159a8f5a-6455-4039-8fa0-31a999e74892o@googlegroups.com> <5f5e793b$0$13559$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Generics Default vs. From: Rick C Injection-Date: Sun, 13 Sep 2020 20:42:18 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9717 On Sunday, September 13, 2020 at 3:55:42 PM UTC-4, Nicolas Matringe wrote: > On 2020-09-13 21:05, Rick C wrote: > [...] > > Anyway, I would expect a value passed into an entity to take the value = passed in and over ride the default value in the generic declaration. Is t= hat what will happen? I will have at least two levels of this. If the top= level gets a different value passed into it during simulation or in synthe= sis, will the value passed in take precedence? > >=20 >=20 > The answer is pretty short and straightforward : yes. > I've been using this method for years without any problem. >=20 > Nicolas Thanks,=20 I've been doing this stuff for a long time, but not in the last couple of y= ears or maybe more. I guess I'm forgetting a lot of details. I am spendin= g a bunch of time online trying to find simpler ways to write what I want t= o do. I just tried to look up a way to do a conditional assignment in sequ= ential code without an IF and without specifying the ELSE part since it sho= uld hold the value rather than change it. One really old reference (some u= niversity that took it down ages ago) says omitting the ELSE of a condition= al signal assignment is "wrong". Another site shows an example of it. Of = course they want to warn that it can cause instantiation of latches, but if= it's already in a clocked process that ain't happenin'. =20 It's times like these that I realize why people like Verilog. lol=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:41 2024 X-Received: by 2002:a37:2715:: with SMTP id n21mr19687078qkn.401.1600199685849; Tue, 15 Sep 2020 12:54:45 -0700 (PDT) X-Received: by 2002:a25:1f44:: with SMTP id f65mr30811426ybf.438.1600199685697; Tue, 15 Sep 2020 12:54:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Sep 2020 12:54:45 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Clocked Process, but Outside of the Clocked IF From: Rick C Injection-Date: Tue, 15 Sep 2020 19:54:45 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 39 Xref: reader02.eternal-september.org comp.lang.vhdl:9718 This is a good example of how rusty I am. I like to use variables where I = can because it localizes the scope. So I have an accumulator that is incre= mented in a clocked process. Then I want to use a portion of the result de= pending on a control, much like a mux, but no register is required, just co= mbinatorial logic. =20 process (rst, clk) is=20 variable... begin if (rst)=20 ... initialization stuff elsif (rising_edge(Clk)) then accum :=3D (accum + input) mod modulus; end if; if (condition) then=20 output <=3D accum / 2; else output <=3D accum; end if;=20 end process;=20 I want to say that while the non-clocked IF will be synthesize as combinato= rial logic and not a register. In the simulation it will look like a regis= ter because the value will change on the rising edge of the clock because a= ccum is a variable and so updated right away. Accum will be registered, bu= t output will not be. =20 Or will accum not be registered and output registered??? I guess I could t= ry some synthesis to see what happens.=20 I'm pretty sure I've done this sort of thing before and it works fine. =20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:41 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: Clocked Process, but Outside of the Clocked IF Date: Tue, 15 Sep 2020 21:12:08 -0500 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 16 Sep 2020 02:12:10 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="2564dc14cf19e368e8161498945652c8"; logging-data="32080"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qmWIsLBlT3MdK+J+juNwCtaxsDyhIOYk=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:vJVYL5lU9WtH0UOgZGL/GNoXyds= In-Reply-To: Xref: reader02.eternal-september.org comp.lang.vhdl:9719 On 2020-09-15 14:54, Rick C wrote: > This is a good example of how rusty I am. I like to use variables where I can because it localizes the scope. So I have an accumulator that is incremented in a clocked process. Then I want to use a portion of the result depending on a control, much like a mux, but no register is required, just combinatorial logic. > > process (rst, clk) is > variable... > begin > if (rst) > ... initialization stuff > elsif (rising_edge(Clk)) then > accum := (accum + input) mod modulus; > end if; > > if (condition) then > output <= accum / 2; > else > output <= accum; > end if; > > end process; > > I want to say that while the non-clocked IF will be synthesize as combinatorial logic and not a register. In the simulation it will look like a register because the value will change on the rising edge of the clock because accum is a variable and so updated right away. Accum will be registered, but output will not be. > > Or will accum not be registered and output registered??? I guess I could try some synthesis to see what happens. > > I'm pretty sure I've done this sort of thing before and it works fine. > Based on my experience, I would be inclined to make accum a signal and assign output in a separate concurrent statement like this: output <= (accum / 2) when condition else accum; That way accum will be registered for sure and output will not. Also, based on many years of experience doing timing analysis on million+ latch ASICs, I would highly recommend using synchronous rather than asynchronous resets wherever possible. signal accum : ... ; process (clk) is begin if (rising_edge(Clk)) then if (rst) ... initialization stuff else accum <= (accum + input) mod modulus; end if; end if; end process; Charles Bailey From newsfish@newsfish Thu Aug 1 00:45:42 2024 X-Received: by 2002:ae9:ebd0:: with SMTP id b199mr21200455qkg.39.1600226787243; Tue, 15 Sep 2020 20:26:27 -0700 (PDT) X-Received: by 2002:a25:b0a3:: with SMTP id f35mr29689821ybj.323.1600226787060; Tue, 15 Sep 2020 20:26:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.alt.net!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Sep 2020 20:26:26 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <437ef172-7820-4534-b8a9-9217811b4871o@googlegroups.com> Subject: Re: Clocked Process, but Outside of the Clocked IF From: Rick C Injection-Date: Wed, 16 Sep 2020 03:26:27 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 95 Xref: reader02.eternal-september.org comp.lang.vhdl:9720 On Tuesday, September 15, 2020 at 10:12:14 PM UTC-4, Charles Bailey wrote: > On 2020-09-15 14:54, Rick C wrote: > > This is a good example of how rusty I am. I like to use variables wher= e I can because it localizes the scope. So I have an accumulator that is i= ncremented in a clocked process. Then I want to use a portion of the resul= t depending on a control, much like a mux, but no register is required, jus= t combinatorial logic. > > > > process (rst, clk) is > > variable... > > begin > > if (rst) > > ... initialization stuff > > elsif (rising_edge(Clk)) then > > accum :=3D (accum + input) mod modulus; > > end if; > > > > if (condition) then > > output <=3D accum / 2; > > else > > output <=3D accum; > > end if; > > > > end process; > > > > I want to say that while the non-clocked IF will be synthesize as combi= natorial logic and not a register. In the simulation it will look like a r= egister because the value will change on the rising edge of the clock becau= se accum is a variable and so updated right away. Accum will be registered= , but output will not be. > > > > Or will accum not be registered and output registered??? I guess I cou= ld try some synthesis to see what happens. > > > > I'm pretty sure I've done this sort of thing before and it works fine. > > > Based on my experience, I would be inclined to make accum a signal and=20 > assign output in a separate concurrent statement like this: > output <=3D (accum / 2) when condition else accum; >=20 > That way accum will be registered for sure and output will not. The expression is a bit more complex than that and I was trying to limit th= e scope of signals/variables. But you are probably right. This likely wou= ld be confusing to anyone seeing this code in the clocked process. =20 I am pretty sure the assignment to output will not be clocked. The reset c= ode is not clocked. But clarity is also important.=20 > Also, based on many years of experience doing timing analysis on=20 > million+ latch ASICs, I would highly recommend using synchronous rather= =20 > than asynchronous resets wherever possible. > signal accum : ... ; >=20 > process (clk) is > begin > if (rising_edge(Clk)) then > if (rst) > ... initialization stuff > else > accum <=3D (accum + input) mod modulus; > end if; > end if; > end process; This is an FPGA where you get an async reset whether you like it or not. I= will need to go through the design and either remove the resets or connect= them to local reset generators that aren't sensitive to the timing of the = reset release, like a shift register where only one bit changes at a time. = Then it won't matter if the different FFs come out of reset at different t= imes. =20 Again, I'm forgetting much of what I used to know well. Now that I think a= bout it, I seem to recall the initialization in the declarations are what t= ranslate to the config reset states. At least that is true in the technolo= gies I've used. Need to check their synthesis user guide. Yes, they show = the signal declaration setting the config value of the FF. I don't have an= y other signal to drive the RST signal anyway. To make sure it comes out o= f config properly, I need to provide a global reset with local re-sync to t= he clock I suppose. =20 Maybe that's overkill. Very little of this device runs on the main clock r= ate. It's all clocked by the main clock, but the enables are very slow. T= here's only a small amount of circuitry that will be sensitive to the timin= g of the config reset release. =20 Thanks for making me think about this.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer02.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx24.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Clocked Process, but Outside of the Clocked IF Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200915-12, 15/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 20 Message-ID: <_Ii8H.52727$y14.29769@fx24.am4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Wed, 16 Sep 2020 06:59:06 UTC Organization: virginmedia.com Date: Wed, 16 Sep 2020 07:59:04 +0100 X-Received-Bytes: 1590 X-Received-Body-CRC: 2871799566 Xref: reader02.eternal-september.org comp.lang.vhdl:9721 On 16/09/2020 03:12, Charles Bailey wrote: > On 2020-09-15 14:54, Rick C wrote: .. > > Also, based on many years of experience doing timing analysis on > million+ latch ASICs, I would highly recommend using synchronous rather > than asynchronous resets wherever possible. Yes on ASIC's an asynchronous reset requires extra logic but this does not generally apply to FPGA's. Although I haven't checked I believe Microchip still recommends async reset for their FPGA's. I would advice you read up on the Wire satellite mission which in effect was lost due to the use of a Synchronous instead of an Asynchronous reset (Actel FPGA). Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:45:42 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer03.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx22.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Reverse ?? Operator Newsgroups: comp.lang.vhdl References: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200915-12, 15/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 51 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Wed, 16 Sep 2020 07:04:55 UTC Organization: virginmedia.com Date: Wed, 16 Sep 2020 08:04:53 +0100 X-Received-Bytes: 3346 X-Received-Body-CRC: 3173183503 Xref: reader02.eternal-september.org comp.lang.vhdl:9722 On 08/09/2020 19:03, Rick C wrote: > On Tuesday, September 8, 2020 at 11:21:54 AM UTC-4, HT-Lab wrote: >> On 08/09/2020 14:35, Rick C wrote: >>> On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote: >>>> On 08/09/2020 03:44:30, Rick C wrote: >> .. >>>>> VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I'm looking for something that does the opposite, converts a Boolean to a std_logic value. >>>>> >> .. >>> Yeah, I'm trying to make this construct a simple one line piece of code. For the time being I've created a function: >>> >>> function b_to_sl (X : boolean) return std_logic is begin >>> if X then return '1'; else return '0'; end if; end b_to_sl; >>> >> >> I hit exactly the same issue many years ago and a VHDL guru's called >> Tricky (if I remember correctly) suggested to use simple functions. Like >> most VHDL engineers I now have a package with lots of helper functions I >> collected over the years. Here is a good site with lots of conversion >> functions: >> >> https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html >> >> However, the reason for replying is that I also tried to use the ?? >> operator recently and failed to make it work, I had something like: >> >> if (?? (OR slvarray(1 downto 0)) OR (a > b)) then.. >> >> however, to make it work you need extra brackets as in : >> >> if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then.. >> >> Or to simplify, you need (??(non_boolean)) >> >> Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I >> just added the brackets and moved on with life..... >> >> I am sure somebody with more VHDL knowledge can explain why the extra >> (non-obvious) brackets are required. >> >> Hans >> www.ht-lab.com > > Can't say for sure, but likely it's a matter of precedence. The second OR tries to operate on the boolean and the std_logic from the first OR before the ?? has had a chance to do its thing. The extra set of parenthesis set the order straight. I am not sure, from what I know ?? is just an overloaded function so ??() should be resolved before OR which has the lowest precedence, Regards, Hans. From newsfish@newsfish Thu Aug 1 00:45:43 2024 X-Received: by 2002:ac8:424a:: with SMTP id r10mr23241056qtm.211.1600277453363; Wed, 16 Sep 2020 10:30:53 -0700 (PDT) X-Received: by 2002:a25:1f44:: with SMTP id f65mr37212298ybf.438.1600277453218; Wed, 16 Sep 2020 10:30:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!news.uzoreto.com!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Sep 2020 10:30:52 -0700 (PDT) In-Reply-To: <_Ii8H.52727$y14.29769@fx24.am4> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <_Ii8H.52727$y14.29769@fx24.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Clocked Process, but Outside of the Clocked IF From: Rick C Injection-Date: Wed, 16 Sep 2020 17:30:53 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 42 Xref: reader02.eternal-september.org comp.lang.vhdl:9723 On Wednesday, September 16, 2020 at 2:59:10 AM UTC-4, HT-Lab wrote: > On 16/09/2020 03:12, Charles Bailey wrote: > > On 2020-09-15 14:54, Rick C wrote: > .. > >=20 > > Also, based on many years of experience doing timing analysis on=20 > > million+ latch ASICs, I would highly recommend using synchronous rather= =20 > > than asynchronous resets wherever possible. >=20 > Yes on ASIC's an asynchronous reset requires extra logic but this does=20 > not generally apply to FPGA's. Although I haven't checked I believe=20 > Microchip still recommends async reset for their FPGA's. >=20 > I would advice you read up on the Wire satellite mission which in effect= =20 > was lost due to the use of a Synchronous instead of an Asynchronous=20 > reset (Actel FPGA). >=20 > Hans > www.ht-lab.com Interesting. I would point to the designers as failing in two of the three= conclusions drawn, failure to account for startup values and not reading a= ll the documentation. I'm guilty of the second myself since it can be over= whelming to start in on a mountain of reading for a new device. But then I= don't design multi-million dollar satellites. =20 I don't agree with the third conclusion that an async reset is required. T= he issue with the sync reset is the absence of a clock. That is the real i= ssue, although I suppose a clock can fail. But if the clock has failed, wh= at good will the reset do? =20 I'm good with only using sync resets. My purpose in using an express async= reset has always been to show the intent for the configuration state of lo= gic, but that can also be done with initialization of signals. =20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:43 2024 X-Received: by 2002:a37:a3cf:: with SMTP id m198mr24678264qke.410.1600280494726; Wed, 16 Sep 2020 11:21:34 -0700 (PDT) X-Received: by 2002:a25:a85:: with SMTP id 127mr20643989ybk.143.1600280494500; Wed, 16 Sep 2020 11:21:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Sep 2020 11:21:34 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6761f291-8561-49e7-a85c-6897a287c043o@googlegroups.com> Subject: Re: Reverse ?? Operator From: Rick C Injection-Date: Wed, 16 Sep 2020 18:21:34 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 62 Xref: reader02.eternal-september.org comp.lang.vhdl:9724 On Wednesday, September 16, 2020 at 3:04:59 AM UTC-4, HT-Lab wrote: > On 08/09/2020 19:03, Rick C wrote: > > On Tuesday, September 8, 2020 at 11:21:54 AM UTC-4, HT-Lab wrote: > >> On 08/09/2020 14:35, Rick C wrote: > >>> On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote: > >>>> On 08/09/2020 03:44:30, Rick C wrote: > >> .. > >>>>> VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I'm looking for something that does the opposite, converts a Boolean to a std_logic value. > >>>>> > >> .. > >>> Yeah, I'm trying to make this construct a simple one line piece of code. For the time being I've created a function: > >>> > >>> function b_to_sl (X : boolean) return std_logic is begin > >>> if X then return '1'; else return '0'; end if; end b_to_sl; > >>> > >> > >> I hit exactly the same issue many years ago and a VHDL guru's called > >> Tricky (if I remember correctly) suggested to use simple functions. Like > >> most VHDL engineers I now have a package with lots of helper functions I > >> collected over the years. Here is a good site with lots of conversion > >> functions: > >> > >> https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html > >> > >> However, the reason for replying is that I also tried to use the ?? > >> operator recently and failed to make it work, I had something like: > >> > >> if (?? (OR slvarray(1 downto 0)) OR (a > b)) then.. > >> > >> however, to make it work you need extra brackets as in : > >> > >> if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then.. > >> > >> Or to simplify, you need (??(non_boolean)) > >> > >> Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I > >> just added the brackets and moved on with life..... > >> > >> I am sure somebody with more VHDL knowledge can explain why the extra > >> (non-obvious) brackets are required. > >> > >> Hans > >> www.ht-lab.com > > > > Can't say for sure, but likely it's a matter of precedence. The second OR tries to operate on the boolean and the std_logic from the first OR before the ?? has had a chance to do its thing. The extra set of parenthesis set the order straight. > > I am not sure, from what I know ?? is just an overloaded function so > ??() should be resolved before OR which has the lowest precedence, > > > Regards, > Hans. I don't think being overloaded affects the priority. Why do you say OR is lower than ??... It's hard to find info on ?? for VHDL. I haven't seen it in any precedence lists. Turns out ?? is hard to search on. In Google it is treated as nothing at all. Bing will return proper results on just ??, but not on VHDL ?? or even VHDL "??" . Go figure. -- Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:43 2024 X-Received: by 2002:a37:a250:: with SMTP id l77mr25861875qke.219.1600321885359; Wed, 16 Sep 2020 22:51:25 -0700 (PDT) X-Received: by 2002:a5b:287:: with SMTP id x7mr39326521ybl.144.1600321885213; Wed, 16 Sep 2020 22:51:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer02.ams4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Sep 2020 22:51:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <_Ii8H.52727$y14.29769@fx24.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3b1581f7-7d66-474c-93c8-8d92a92cbf29o@googlegroups.com> Subject: Re: Clocked Process, but Outside of the Clocked IF From: Rick C Injection-Date: Thu, 17 Sep 2020 05:51:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3183 X-Received-Body-CRC: 576916859 Xref: reader02.eternal-september.org comp.lang.vhdl:9725 Damn! I find resetting an FPGA design to be one of the harder tasks in wor= king with them. I recall my first design I included both a sync reset and = an async reset. The software guy asked me why so many resets (there's also= the configure input on the chip). =20 So I now have a design that has battery backup, so it will need to boot up = configuration once and run indefinitely. The processor is treated as suspe= ct at all times, so no reset is provided for him to mess up the FPGA with. = =20 I really need to remove all the reset code and find another way to specify = the initial state of all the FFs. Using an initialization in the declarati= on seems to be recommended by at least some users and in app notes. But wh= en a signal is an output it is less clear how well that will work. The sig= nal can be initialized in the output declaration, but I've seen some indica= tion this might actually be treated as a conflict like a second driver to t= he assignments that actually drive the output. =20 Anyone know? Will this work in both simulation and synthesis?=20 ENTITY MotorControl IS GENERIC ( CLK_MHZ : REAL :=3D 32.0E6 ); port ( Clk : in std_logic; Rst : in std_logic; Mot_Restart : in std_logic; Mot_Overcur : in std_logic; Mot_Off : out std_logic :=3D '0' -- <<<<=20 ); end MotorControl; I'm worried if it will work with Gowin devices even if it works with other = tool brands. Seems their synthesis tool is in house. All their examples a= re Verilog where the register has to be declared separately from the output= . I guess that's what I'll need to do for VHDL as well. =20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:44 2024 X-Received: by 2002:aed:25d1:: with SMTP id y17mr14588783qtc.375.1600327344043; Thu, 17 Sep 2020 00:22:24 -0700 (PDT) X-Received: by 2002:a25:d40c:: with SMTP id m12mr24111290ybf.273.1600327343740; Thu, 17 Sep 2020 00:22:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Sep 2020 00:22:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=14.139.197.83; posting-account=fOQNAAoAAAAWxqA-_cmtEnbjRdZbUKtm NNTP-Posting-Host: 14.139.197.83 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: TCL Error From: "Kr. Sheelvardhan Banty" Injection-Date: Thu, 17 Sep 2020 07:22:24 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9726 When I try to open a new project in Modelsim It gives me this error:- ** Error: (vlib-35) Failed to create directory "C:/intelFPGA/20.1/work". Permission denied. (errno = EACCES) child process exited abnormally while executing "exec $vlib $worklib" (procedure "Project::create" line 45) invoked from within "Project::create $Project(dlg_proj_location) $Project(CurProj_NewName) $Project(dlg_proj_libname) $Project(dlg_initial_ini) $Project(dlg_ini_copy)" (procedure "Project::applyCreate" line 3) invoked from within "Project::applyCreate .pcd" invoked from within ".pcd.bb.button0 invoke" ("uplevel" body line 1) invoked from within "uplevel #0 [list $w invoke]" (procedure "tk::ButtonUp" line 24) invoked from within "tk::ButtonUp .pcd.bb.button0" (command bound to event) From newsfish@newsfish Thu Aug 1 00:45:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx20.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: TCL Error Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200916-18, 16/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 41 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 17 Sep 2020 07:48:43 UTC Organization: virginmedia.com Date: Thu, 17 Sep 2020 08:48:44 +0100 X-Received-Bytes: 2211 X-Received-Body-CRC: 2324815608 Xref: reader02.eternal-september.org comp.lang.vhdl:9727 Looks like you have hit some read/write permissions. Try creating a simple design outside of the installation tree: vlib work vmap work work vlog/vcom xx I would also strongly advice not to use Modelsim projects, a .do or .tcl file is all you need and far more flexible. If you are worried about compile time you can use vmake+make. Good luck, Hans www.ht-lab.com On 17/09/2020 08:22, Kr. Sheelvardhan Banty wrote: > When I try to open a new project in Modelsim It gives me this error:- > > ** Error: (vlib-35) Failed to create directory "C:/intelFPGA/20.1/work". > Permission denied. (errno = EACCES) > child process exited abnormally > while executing > "exec $vlib $worklib" > (procedure "Project::create" line 45) > invoked from within > "Project::create $Project(dlg_proj_location) $Project(CurProj_NewName) $Project(dlg_proj_libname) $Project(dlg_initial_ini) $Project(dlg_ini_copy)" > (procedure "Project::applyCreate" line 3) > invoked from within > "Project::applyCreate .pcd" > invoked from within > ".pcd.bb.button0 invoke" > ("uplevel" body line 1) > invoked from within > "uplevel #0 [list $w invoke]" > (procedure "tk::ButtonUp" line 24) > invoked from within > "tk::ButtonUp .pcd.bb.button0" > (command bound to event) > From newsfish@newsfish Thu Aug 1 00:45:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer02.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx29.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Clocked Process, but Outside of the Clocked IF Newsgroups: comp.lang.vhdl References: <_Ii8H.52727$y14.29769@fx24.am4> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200916-18, 16/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 50 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 17 Sep 2020 08:33:33 UTC Organization: virginmedia.com Date: Thu, 17 Sep 2020 09:33:34 +0100 X-Received-Bytes: 3354 X-Received-Body-CRC: 200298245 Xref: reader02.eternal-september.org comp.lang.vhdl:9728 On 16/09/2020 18:30, Rick C wrote: > On Wednesday, September 16, 2020 at 2:59:10 AM UTC-4, HT-Lab wrote: >> On 16/09/2020 03:12, Charles Bailey wrote: >>> On 2020-09-15 14:54, Rick C wrote: >> .. >>> >>> Also, based on many years of experience doing timing analysis on >>> million+ latch ASICs, I would highly recommend using synchronous rather >>> than asynchronous resets wherever possible. >> >> Yes on ASIC's an asynchronous reset requires extra logic but this does >> not generally apply to FPGA's. Although I haven't checked I believe >> Microchip still recommends async reset for their FPGA's. >> >> I would advice you read up on the Wire satellite mission which in effect >> was lost due to the use of a Synchronous instead of an Asynchronous >> reset (Actel FPGA). >> >> Hans >> www.ht-lab.com > > Interesting. I would point to the designers as failing in two of the three conclusions drawn, failure to account for startup values and not reading all the documentation. I'm guilty of the second myself since it can be overwhelming to start in on a mountain of reading for a new device. But then I don't design multi-million dollar satellites. > > I don't agree with the third conclusion that an async reset is required. Third conclusion? My advice is not to assume sync reset is the best solution for all FPGAs or designs. The issue with the sync reset is the absence of a clock. That is the real issue, although I suppose a clock can fail. But if the clock has failed, what good will the reset do? It is not a clock failure which is the issue as that is an easy one to detect. The real problem are power supplies, clock domain and clock stability issues as they can all make your synchronous reset misbehave. In addition most reset input signals (push button, POR etc) are asynchronous so meta stability measures (async asserted, sync negated) are recommended. If you are working on some user appliance then pressing the reset button twice is not a big deal but you are working on a ventilator right? Hans www.ht-lab.com > > I'm good with only using sync resets. My purpose in using an express async reset has always been to show the intent for the configuration state of logic, but that can also be done with initialization of signals. > From newsfish@newsfish Thu Aug 1 00:45:44 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer02.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx06.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Reverse ?? Operator Newsgroups: comp.lang.vhdl References: <012f4ff5-eaf0-4b09-b5b0-bb68693a0be7o@googlegroups.com> <6761f291-8561-49e7-a85c-6897a287c043o@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <6761f291-8561-49e7-a85c-6897a287c043o@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200916-18, 16/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 81 Message-ID: <1DF8H.1625969$Sg4.834785@fx06.am4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 17 Sep 2020 09:02:53 UTC Organization: virginmedia.com Date: Thu, 17 Sep 2020 10:02:53 +0100 X-Received-Bytes: 4492 X-Received-Body-CRC: 4049782538 Xref: reader02.eternal-september.org comp.lang.vhdl:9729 On 16/09/2020 19:21, Rick C wrote: > On Wednesday, September 16, 2020 at 3:04:59 AM UTC-4, HT-Lab wrote: >> On 08/09/2020 19:03, Rick C wrote: >>> On Tuesday, September 8, 2020 at 11:21:54 AM UTC-4, HT-Lab wrote: >>>> On 08/09/2020 14:35, Rick C wrote: >>>>> On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote: >>>>>> On 08/09/2020 03:44:30, Rick C wrote: >>>> .. >>>>>>> VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I'm looking for something that does the opposite, converts a Boolean to a std_logic value. >>>>>>> >>>> .. >>>>> Yeah, I'm trying to make this construct a simple one line piece of code. For the time being I've created a function: >>>>> >>>>> function b_to_sl (X : boolean) return std_logic is begin >>>>> if X then return '1'; else return '0'; end if; end b_to_sl; >>>>> >>>> >>>> I hit exactly the same issue many years ago and a VHDL guru's called >>>> Tricky (if I remember correctly) suggested to use simple functions. Like >>>> most VHDL engineers I now have a package with lots of helper functions I >>>> collected over the years. Here is a good site with lots of conversion >>>> functions: >>>> >>>> https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html >>>> >>>> However, the reason for replying is that I also tried to use the ?? >>>> operator recently and failed to make it work, I had something like: >>>> >>>> if (?? (OR slvarray(1 downto 0)) OR (a > b)) then.. >>>> >>>> however, to make it work you need extra brackets as in : >>>> >>>> if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then.. >>>> >>>> Or to simplify, you need (??(non_boolean)) >>>> >>>> Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I >>>> just added the brackets and moved on with life..... >>>> >>>> I am sure somebody with more VHDL knowledge can explain why the extra >>>> (non-obvious) brackets are required. >>>> >>>> Hans >>>> www.ht-lab.com >>> >>> Can't say for sure, but likely it's a matter of precedence. The second OR tries to operate on the boolean and the std_logic from the first OR before the ?? has had a chance to do its thing. The extra set of parenthesis set the order straight. >> >> I am not sure, from what I know ?? is just an overloaded function so >> ??() should be resolved before OR which has the lowest precedence, >> >> >> Regards, >> Hans. > > I don't think being overloaded affects the priority. Why do you say OR is lower than ??... I didn't, I said ?? should be resolved before the OR. I assumed ??(x) is similar to something like std2bool(x) in which case "std2bool(x) OR" is the same as "(std2bool(x)) OR" but with the ?? this is not the case. It's hard to find info on ?? for VHDL. I haven't seen it in any precedence lists. Because it is an overloaded function (see std_logic_1164.vhd) > > Turns out ?? is hard to search on. In Google it is treated as nothing at all. Bing will return proper results on just ??, but not on VHDL ?? or even VHDL "??" . Go figure. Yes I had difficulties googling it as well and only found the Doulos page, I suspect ?? is not widely used in the VHDL community. Hans www.ht-lab.com > From newsfish@newsfish Thu Aug 1 00:45:45 2024 X-Received: by 2002:a37:a250:: with SMTP id l77mr26582529qke.219.1600338144485; Thu, 17 Sep 2020 03:22:24 -0700 (PDT) X-Received: by 2002:a25:404:: with SMTP id 4mr42475732ybe.22.1600338144188; Thu, 17 Sep 2020 03:22:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Sep 2020 03:22:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=14.139.197.83; posting-account=fOQNAAoAAAAWxqA-_cmtEnbjRdZbUKtm NNTP-Posting-Host: 14.139.197.83 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2950e1f1-bb05-4015-bcbe-474b67ff57f3n@googlegroups.com> Subject: Re: TCL Error From: "Kr. Sheelvardhan Banty" Injection-Date: Thu, 17 Sep 2020 10:22:24 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9730 On Thursday, 17 September 2020 at 13:18:47 UTC+5:30, HT-Lab wrote: > Looks like you have hit some read/write permissions. Try creating a > simple design outside of the installation tree: > > vlib work > vmap work work > vlog/vcom xx > > I would also strongly advice not to use Modelsim projects, a .do or .tcl > file is all you need and far more flexible. If you are worried about > compile time you can use vmake+make. > > Good luck, > Hans > www.ht-lab.com > On 17/09/2020 08:22, Kr. Sheelvardhan Banty wrote: > > When I try to open a new project in Modelsim It gives me this error:- > > > > ** Error: (vlib-35) Failed to create directory "C:/intelFPGA/20.1/work". > > Permission denied. (errno = EACCES) > > child process exited abnormally > > while executing > > "exec $vlib $worklib" > > (procedure "Project::create" line 45) > > invoked from within > > "Project::create $Project(dlg_proj_location) $Project(CurProj_NewName) $Project(dlg_proj_libname) $Project(dlg_initial_ini) $Project(dlg_ini_copy)" > > (procedure "Project::applyCreate" line 3) > > invoked from within > > "Project::applyCreate .pcd" > > invoked from within > > ".pcd.bb.button0 invoke" > > ("uplevel" body line 1) > > invoked from within > > "uplevel #0 [list $w invoke]" > > (procedure "tk::ButtonUp" line 24) > > invoked from within > > "tk::ButtonUp .pcd.bb.button0" > > (command bound to event) > > I always get the message :- Transcript : permission denied From newsfish@newsfish Thu Aug 1 00:45:45 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx46.ams4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: TCL Error Newsgroups: comp.lang.vhdl References: <2950e1f1-bb05-4015-bcbe-474b67ff57f3n@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <2950e1f1-bb05-4015-bcbe-474b67ff57f3n@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200917-4, 17/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 32 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 17 Sep 2020 11:02:12 UTC Organization: virginmedia.com Date: Thu, 17 Sep 2020 12:02:12 +0100 X-Received-Bytes: 1969 X-Received-Body-CRC: 789884022 Xref: reader02.eternal-september.org comp.lang.vhdl:9731 On 17/09/2020 11:22, Kr. Sheelvardhan Banty wrote: > On Thursday, 17 September 2020 at 13:18:47 UTC+5:30, HT-Lab wrote: >> Looks like you have hit some read/write permissions. Try creating a >> simple design outside of the installation tree: >> >> vlib work >> vmap work work >> vlog/vcom xx >> >> I would also strongly advice not to use Modelsim projects, a .do or .tcl >> file is all you need and far more flexible. If you are worried about >> compile time you can use vmake+make. >> >> Good luck, >> Hans >> www.ht-lab.com >> On 17/09/2020 08:22, Kr. Sheelvardhan Banty wrote: >>> When I try to open a new project in Modelsim It gives me this error:- >>> .. > I always get the message :- > Transcript : permission denied > The transcript output is written to a text file to the same work directory Modelsim is complaining about. Have you checked the permissions for the "C:/intelFPGA/20.1/work" directory? have you tried another directory? Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:45:45 2024 X-Received: by 2002:a05:620a:1227:: with SMTP id v7mr30111728qkj.265.1600363735019; Thu, 17 Sep 2020 10:28:55 -0700 (PDT) X-Received: by 2002:a25:c444:: with SMTP id u65mr3645465ybf.188.1600363734809; Thu, 17 Sep 2020 10:28:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Sep 2020 10:28:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <_Ii8H.52727$y14.29769@fx24.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <75c1bd32-ca01-4ddf-9fe6-8eb1cabebccbo@googlegroups.com> Subject: Re: Clocked Process, but Outside of the Clocked IF From: Rick C Injection-Date: Thu, 17 Sep 2020 17:28:55 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9732 On Thursday, September 17, 2020 at 4:33:37 AM UTC-4, HT-Lab wrote: > On 16/09/2020 18:30, Rick C wrote: > > On Wednesday, September 16, 2020 at 2:59:10 AM UTC-4, HT-Lab wrote: > >> On 16/09/2020 03:12, Charles Bailey wrote: > >>> On 2020-09-15 14:54, Rick C wrote: > >> .. > >>> > >>> Also, based on many years of experience doing timing analysis on > >>> million+ latch ASICs, I would highly recommend using synchronous rath= er > >>> than asynchronous resets wherever possible. > >> > >> Yes on ASIC's an asynchronous reset requires extra logic but this does > >> not generally apply to FPGA's. Although I haven't checked I believe > >> Microchip still recommends async reset for their FPGA's. > >> > >> I would advice you read up on the Wire satellite mission which in effe= ct > >> was lost due to the use of a Synchronous instead of an Asynchronous > >> reset (Actel FPGA). > >> > >> Hans > >> www.ht-lab.com > >=20 > > Interesting. I would point to the designers as failing in two of the t= hree conclusions drawn, failure to account for startup values and not readi= ng all the documentation. I'm guilty of the second myself since it can be = overwhelming to start in on a mountain of reading for a new device. But th= en I don't design multi-million dollar satellites. > >=20 > > I don't agree with the third conclusion that an async reset is required= . =20 >=20 > Third conclusion? My advice is not to assume sync reset is the best=20 > solution for all FPGAs or designs. I mean in the report. They had three conclusions. The third is "there sho= uld be a direct asynchronous path from the reset input for initialising the= device state, being independent of any clock activity". =20 > The issue with the sync reset is the absence of a clock. That is the=20 > real issue, although I suppose a clock can fail. But if the clock has=20 > failed, what good will the reset do? That would be covered by the same issues that must be managed by the start = up consideration. Many FPGAs do not specify behavior at the very start of = the power up process. So no assumptions can be made about any control outp= uts and must be independently managed. This will also deal with any reset = related issues in the absence of a clock.=20 > It is not a clock failure which is the issue as that is an easy one to=20 > detect. The real problem are power supplies, clock domain and clock=20 > stability issues as they can all make your synchronous reset misbehave.= =20 > In addition most reset input signals (push button, POR etc) are=20 > asynchronous so meta stability measures (async asserted, sync negated)=20 > are recommended. Power supply issues result in no controls being specified to work, includin= g async resets.=20 The async nature of power on reset release is always an issue in FPGAs and = must be managed. The real problem is that even if the global power on rese= t is synchronous, the propagation can be slow enough to not meet the synchr= onous setup time. So it must be managed locally, but only on certain criti= cal circuits.=20 > If you are working on some user appliance then pressing the reset button= =20 > twice is not a big deal but you are working on a ventilator right? Yes, but it doesn't power up/down. It has battery backup and the FPGA may = never be powered down. But of course it has to be designed to power up cor= rectly. That will be local sync resets that start state machines and such.= Essentially, each critical circuit needs to be immune to problems from th= e release of the global async reset. Not hard to do at all. Much of my de= sign relies on timing enables. If these enables are not released for a cou= ple of clock cycles after the global async reset is released that's 99% of = the design already. Then the remaining circuity needs to be handled on its= own.=20 Other than power up, there are no resets because there is no trusted source= of a reset. Maybe building something into the touch pad would be a good i= dea??? Maybe not.=20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:46 2024 X-Received: by 2002:a37:84f:: with SMTP id 76mr30540674qki.251.1600389314554; Thu, 17 Sep 2020 17:35:14 -0700 (PDT) X-Received: by 2002:a5b:287:: with SMTP id x7mr45242874ybl.144.1600389314393; Thu, 17 Sep 2020 17:35:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer02.ams4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Sep 2020 17:35:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Crikey! From: Rick C Injection-Date: Fri, 18 Sep 2020 00:35:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2515 X-Received-Body-CRC: 2058727658 Xref: reader02.eternal-september.org comp.lang.vhdl:9733 Sometimes I think they just wanted to mess with people when they designed V= HDL. I recall some long ago conversations with one of the guys who helped = design VHDL and while he understood the language well, he understood it the= same way a newly hired legal associate understands the law. He knew most = of the rules, but didn't understand how to usefully apply them to do what n= eeded to be done. That's what senior partners are for. More recently it s= eems like they've changed VHDL in ways that make it much more usable, but n= ot always. Sometime there are things that seem like they should work, but = just don't.=20 So my most recent issue is this statement...=20 Sound_Run <=3D Alarm_Src ?/=3D (others =3D> '0'); The compiler complains that it doesn't understand what size the aggregate s= hould be. Is that because while Alarm_Src is well defined, the comparison = operator can accept many different operand widths and the tool can't see ac= ross the operator??? =20 Alarm_Src is defined as Alarm_Type which is defined=20 subtype Alarm_Type is unsigned (Technical_Sel downto Tidal_Vol_Sel); Where the two values in the range are integer constants.=20 This works... Sound_Run <=3D Alarm_Src ?/=3D (Alarm_Src'range =3D> '0'); I should understand this, but I don't. =20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:46 2024 X-Received: by 2002:a0c:cd0d:: with SMTP id b13mr18293014qvm.53.1600447880907; Fri, 18 Sep 2020 09:51:20 -0700 (PDT) X-Received: by 2002:a05:6902:50e:: with SMTP id x14mr2198603ybs.273.1600447880656; Fri, 18 Sep 2020 09:51:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Sep 2020 09:51:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Crikey! From: KJ Injection-Date: Fri, 18 Sep 2020 16:51:20 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 17 Xref: reader02.eternal-september.org comp.lang.vhdl:9734 On Thursday, September 17, 2020 at 8:35:17 PM UTC-4, gnuarm.del...@gmail.co= m wrote: >=20 > Sound_Run <=3D Alarm_Src ?/=3D (others =3D> '0');=20 >=20 > The compiler complains that it doesn't understand what size the aggregate= should be. Is that because while Alarm_Src is well defined, the comparison= operator can accept many different operand widths and the tool can't see a= cross the operator???=20 >=20 Basically, yes. However, if all somebody told you is "(others =3D> '0')", = and asked how wide the vector is, you wouldn't be able to answer the questi= on. The compiler is the same way. It needs to know the width of the vecto= r. While the operator can work with any size vectors, those vectors still = must have defined ranges. Otherwise, how can it check that the vectors are= the same size? Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:46 2024 X-Received: by 2002:ad4:458f:: with SMTP id x15mr18381327qvu.33.1600448477389; Fri, 18 Sep 2020 10:01:17 -0700 (PDT) X-Received: by 2002:a25:27c1:: with SMTP id n184mr50899848ybn.319.1600448477249; Fri, 18 Sep 2020 10:01:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Sep 2020 10:01:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <14018232-27de-4af9-af15-5a2198e3bb56o@googlegroups.com> Subject: Re: Crikey! From: Rick C Injection-Date: Fri, 18 Sep 2020 17:01:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 37 Xref: reader02.eternal-september.org comp.lang.vhdl:9735 On Friday, September 18, 2020 at 12:51:23 PM UTC-4, KJ wrote: > On Thursday, September 17, 2020 at 8:35:17 PM UTC-4, gnuarm.del...@gmail.= com wrote: > >=20 > > Sound_Run <=3D Alarm_Src ?/=3D (others =3D> '0');=20 > >=20 > > The compiler complains that it doesn't understand what size the aggrega= te should be. Is that because while Alarm_Src is well defined, the comparis= on operator can accept many different operand widths and the tool can't see= across the operator???=20 > >=20 > Basically, yes. However, if all somebody told you is "(others =3D> '0')"= , and asked how wide the vector is, you wouldn't be able to answer the ques= tion. The compiler is the same way. It needs to know the width of the vec= tor. While the operator can work with any size vectors, those vectors stil= l must have defined ranges. Otherwise, how can it check that the vectors a= re the same size? >=20 > Kevin Jennings The vector is as wide as the other input to the ?/=3D operator. I would ex= pect that to be obvious to anyone looking at the code. But it's not obviou= s to the tool. That's my point. Many times in the past I recall the tool = not being able to under stand an intent that is patently obvious which was = eventually fixed in the language like "000" being assigned to a std_logic_v= ector because the tools didn't know you weren't trying to assign a bit vect= or to an slv. =20 This would seem to be another case of the tools not being able to understan= d what is actually rather obvious. I keep saying I'm going to learn Verilo= g. Maybe I should have used this project as my learning curve. =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:47 2024 X-Received: by 2002:a37:638d:: with SMTP id x135mr17731892qkb.60.1600449905962; Fri, 18 Sep 2020 10:25:05 -0700 (PDT) X-Received: by 2002:a25:bfcf:: with SMTP id q15mr20113070ybm.133.1600449905828; Fri, 18 Sep 2020 10:25:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Sep 2020 10:25:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> Subject: VHDL Real Rounding From: Rick C Injection-Date: Fri, 18 Sep 2020 17:25:05 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9736 CLK_HZ : REAL := 33.554432E6 -- 2^25 . . . constant MS_MAX_Cnt : integer := integer(ROUND(CLK_HZ/1000.0)) - 1; What should be the value of MS_MAX_Cnt, 33,555, 33,554 or 33,553? I say 33,553, the Aldec simulator says 33,554. Who's right? What am I missing about the operation of ROUND ? The definition says it adds 0.5 before taking the FLOOR of positive values. Even with the 0.5 added the FLOOR should make the value 33,554.0 then with the integer conversion 33,554 then minus 1 to give 33,553. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:47 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 18 Sep 2020 14:13:47 -0500 Reply-To: mk@mkesc.co.uk Subject: Re: Crikey! Newsgroups: comp.lang.vhdl References: <14018232-27de-4af9-af15-5a2198e3bb56o@googlegroups.com> From: Michael Kellett Date: Fri, 18 Sep 2020 20:13:53 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <14018232-27de-4af9-af15-5a2198e3bb56o@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Message-ID: Lines: 22 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-QvNlQcFNR7SHCUzdMNz2V0Nfz/zQmf8Hh3Vja6TI1iY4AUgGppDuIxFhHvklN/vaZVJRDO5jD3WKS7F!2bc5/t+QSmZWhl64fajxe0sroJtSGX+DpqZKrQSy1DOfhZPWcoKxL79ExbUTFY/nLzNzmQclvCYK X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3232 Xref: reader02.eternal-september.org comp.lang.vhdl:9737 On 18/09/2020 18:01, Rick C wrote: > On Friday, September 18, 2020 at 12:51:23 PM UTC-4, KJ wrote: >> On Thursday, September 17, 2020 at 8:35:17 PM UTC-4, gnuarm.del...@gmail.com wrote: >>> >>> Sound_Run <= Alarm_Src ?/= (others => '0'); >>> >>> The compiler complains that it doesn't understand what size the aggregate should be. Is that because while Alarm_Src is well defined, the comparison operator can accept many different operand widths and the tool can't see across the operator??? >>> >> Basically, yes. However, if all somebody told you is "(others => '0')", and asked how wide the vector is, you wouldn't be able to answer the question. The compiler is the same way. It needs to know the width of the vector. While the operator can work with any size vectors, those vectors still must have defined ranges. Otherwise, how can it check that the vectors are the same size? >> >> Kevin Jennings > > The vector is as wide as the other input to the ?/= operator. I would expect that to be obvious to anyone looking at the code. But it's not obvious to the tool. That's my point. Many times in the past I recall the tool not being able to under stand an intent that is patently obvious which was eventually fixed in the language like "000" being assigned to a std_logic_vector because the tools didn't know you weren't trying to assign a bit vector to an slv. > > This would seem to be another case of the tools not being able to understand what is actually rather obvious. I keep saying I'm going to learn Verilog. Maybe I should have used this project as my learning curve. > I'm not so sure that Verilog will help you much, with VHDL the compiler refuses to guess, sometimes pedantically. Verilog is like an enthusiastic puppy, it tries to guess what you want and sometimes gets it horribly wrong, and you don't find out until it doesn't work. MK From newsfish@newsfish Thu Aug 1 00:45:47 2024 X-Received: by 2002:a0c:a4c5:: with SMTP id x63mr18809267qvx.58.1600457994052; Fri, 18 Sep 2020 12:39:54 -0700 (PDT) X-Received: by 2002:a25:9c01:: with SMTP id c1mr40526826ybo.106.1600457993833; Fri, 18 Sep 2020 12:39:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Sep 2020 12:39:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <14018232-27de-4af9-af15-5a2198e3bb56o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6cc33c6c-feab-4677-97df-0307e269ff5fo@googlegroups.com> Subject: Re: Crikey! From: Rick C Injection-Date: Fri, 18 Sep 2020 19:39:54 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 71 Xref: reader02.eternal-september.org comp.lang.vhdl:9738 On Friday, September 18, 2020 at 3:13:51 PM UTC-4, Michael Kellett wrote: > On 18/09/2020 18:01, Rick C wrote: > > On Friday, September 18, 2020 at 12:51:23 PM UTC-4, KJ wrote: > >> On Thursday, September 17, 2020 at 8:35:17 PM UTC-4, gnuarm.del...@gma= il.com wrote: > >>> > >>> Sound_Run <=3D Alarm_Src ?/=3D (others =3D> '0'); > >>> > >>> The compiler complains that it doesn't understand what size the aggre= gate should be. Is that because while Alarm_Src is well defined, the compar= ison operator can accept many different operand widths and the tool can't s= ee across the operator??? > >>> > >> Basically, yes. However, if all somebody told you is "(others =3D> '0= ')", and asked how wide the vector is, you wouldn't be able to answer the q= uestion. The compiler is the same way. It needs to know the width of the = vector. While the operator can work with any size vectors, those vectors s= till must have defined ranges. Otherwise, how can it check that the vector= s are the same size? > >> > >> Kevin Jennings > >=20 > > The vector is as wide as the other input to the ?/=3D operator. I woul= d expect that to be obvious to anyone looking at the code. But it's not ob= vious to the tool. That's my point. Many times in the past I recall the t= ool not being able to under stand an intent that is patently obvious which = was eventually fixed in the language like "000" being assigned to a std_log= ic_vector because the tools didn't know you weren't trying to assign a bit = vector to an slv. > >=20 > > This would seem to be another case of the tools not being able to under= stand what is actually rather obvious. I keep saying I'm going to learn Ve= rilog. Maybe I should have used this project as my learning curve. > >=20 > I'm not so sure that Verilog will help you much, with VHDL the compiler= =20 > refuses to guess, sometimes pedantically. Verilog is like an=20 > enthusiastic puppy, it tries to guess what you want and sometimes gets=20 > it horribly wrong, and you don't find out until it doesn't work. That is what I've heard, but I believe it's not so much a puppy wildly gues= sing as it is a matter of consistently making assumptions that the programm= er must learn about. That part is not really different from VHDL, but the = part about VHDL stubbornly refusing to act until it is told in excruciating= detail what is intended while Verilog doesn't hold your hand and makes it'= s assumptions whether you understand or not. =20 I'm still having issues with VHDL and in at least one case it is exactly th= e same as Verilog, other than expected with no warning. I opened another t= hread about rounding of real values not working as I expected. I guess I n= eed to write some code to explore this and figure out what is happening. = =20 Even if VHDL gives you warnings that prevent mistakes, it's a bloody PITA t= o program in sometimes. My other language is Forth where it doesn't make a= ssumptions of any sort. You just have to make it do what you want with a w= hip and chair. Actually no whip or chair needed. More like giving you all= the sharp and power tools you want as long as you know how to use them wit= hout getting hurt. =20 My real problem with all this is working with them intermittently. It can = be years between significant projects. But it seems every time I have to o= pen Pandora's box again, I find a new something in there that I hadn't seen= before. My code does keep getting better even if it is a PITA to relearn.= =20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:48 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (gtwrek) Newsgroups: comp.lang.vhdl Subject: Re: Crikey! Date: Fri, 18 Sep 2020 20:19:10 -0000 (UTC) Organization: Sonic Lines: 25 Message-ID: References: <14018232-27de-4af9-af15-5a2198e3bb56o@googlegroups.com> Injection-Date: Fri, 18 Sep 2020 20:19:10 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="8b5f7f6b89dc4ce470acbe28789bcbc8"; logging-data="9853"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ShB+/d9gwfxDKV+QCddWV" Cancel-Lock: sha1:9EBnDfUqyaMTSa0IF+vzTBIJNBA= Originator: gtwrek@sonic.net (gtwrek) X-Newsreader: trn 4.0-test77 (Sep 1, 2010) Xref: reader02.eternal-september.org comp.lang.vhdl:9739 In article , Michael Kellett wrote: >> This would seem to be another case of the tools not being able to understand what is actually rather obvious. I keep saying I'm going to learn Verilog. Maybe I should >have used this project as my learning curve. >> >I'm not so sure that Verilog will help you much, with VHDL the compiler >refuses to guess, sometimes pedantically. Verilog is like an >enthusiastic puppy, it tries to guess what you want and sometimes gets >it horribly wrong, and you don't find out until it doesn't work. Don't want to start a language war, but this characterization is completely wrong about verilog. The verilog rules are less hard typed, than VHDL but there's no "guessing" involved AT ALL within the language. There's very few cases of ambiguous behaviour in the standard. And for those that do exists the complementary abiguous behavior likely exists in VHDL too, or has solid ways for the RTL designer to avoid problems because of the "undefined" or "implementation" defined behavior. There are well and good reasons to prefer one VHDL over Verilog, however this characterization misses the mark. Regards, Mark From newsfish@newsfish Thu Aug 1 00:45:48 2024 X-Received: by 2002:ac8:1108:: with SMTP id c8mr22271319qtj.323.1600461900466; Fri, 18 Sep 2020 13:45:00 -0700 (PDT) X-Received: by 2002:a25:1f44:: with SMTP id f65mr52969205ybf.438.1600461900293; Fri, 18 Sep 2020 13:45:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Sep 2020 13:44:59 -0700 (PDT) In-Reply-To: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> Subject: Re: VHDL Real Rounding From: Rick C Injection-Date: Fri, 18 Sep 2020 20:45:00 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9740 On Friday, September 18, 2020 at 1:25:09 PM UTC-4, Rick C wrote: > CLK_HZ : REAL :=3D 33.554432E6 -- 2^25 > . > . > . > constant MS_MAX_Cnt : integer :=3D integer(ROUND(CLK_HZ/1000.0)) - 1; >=20 > What should be the value of MS_MAX_Cnt, 33,555, 33,554 or 33,553? =20 >=20 > I say 33,553, the Aldec simulator says 33,554. Who's right?=20 >=20 > What am I missing about the operation of ROUND ?=20 >=20 > The definition says it adds 0.5 before taking the FLOOR of positive value= s. Even with the 0.5 added the FLOOR should make the value 33,554.0 then w= ith the integer conversion 33,554 then minus 1 to give 33,553. =20 I'm not sure what I was doing wrong, but I added statements to do the above= calculation one step at a time and it's getting the right number correctly= now with the original statement. So the count is right, but the time valu= e in the simulation is not right. =20 CLK_HZ : REAL :=3D 33.554432E6 constant Clock_Half_Period : time :=3D 500 ms / CLK_HZ; Clk_gen: Clk <=3D not Clk after Clock_Half_Period; The clock period measured in the simulator is always 29.8 ns no matter what= resolution I set for the simulation time value. With the resolution set t= o 10 fs I just measured the time of a clock and it is 29,800 ps. It should= be 29,802 ps if rounded. That 2 ps is about two clock cycles out of the 1= ms time period. I was trying to set limits for an assert to automatically= check this time. If I can't get the clock rate right, I won't be able to = check any timings to full resolution... although I suppose the xtal isn't m= uch more accurate than this, slightly lower than 1 clock cycle per ms. =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:48 2024 X-Received: by 2002:a37:6786:: with SMTP id b128mr36677884qkc.396.1600477811206; Fri, 18 Sep 2020 18:10:11 -0700 (PDT) X-Received: by 2002:a25:9c01:: with SMTP id c1mr42084461ybo.106.1600477810988; Fri, 18 Sep 2020 18:10:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Sep 2020 18:10:10 -0700 (PDT) In-Reply-To: <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <093837c3-653a-4683-bac7-0b2ed1909d52o@googlegroups.com> Subject: Re: VHDL Real Rounding From: Rick C Injection-Date: Sat, 19 Sep 2020 01:10:11 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9741 On Friday, September 18, 2020 at 4:45:02 PM UTC-4, Rick C wrote: > On Friday, September 18, 2020 at 1:25:09 PM UTC-4, Rick C wrote: > > CLK_HZ : REAL :=3D 33.554432E6 -- 2^25 > > . > > . > > . > > constant MS_MAX_Cnt : integer :=3D integer(ROUND(CLK_HZ/1000.0)) - 1; > >=20 > > What should be the value of MS_MAX_Cnt, 33,555, 33,554 or 33,553? =20 > >=20 > > I say 33,553, the Aldec simulator says 33,554. Who's right?=20 > >=20 > > What am I missing about the operation of ROUND ?=20 > >=20 > > The definition says it adds 0.5 before taking the FLOOR of positive val= ues. Even with the 0.5 added the FLOOR should make the value 33,554.0 then= with the integer conversion 33,554 then minus 1 to give 33,553. =20 >=20 > I'm not sure what I was doing wrong, but I added statements to do the abo= ve calculation one step at a time and it's getting the right number correct= ly now with the original statement. So the count is right, but the time va= lue in the simulation is not right. =20 >=20 > CLK_HZ : REAL :=3D 33.554432E6 >=20 > constant Clock_Half_Period : time :=3D 500 ms / CLK_HZ; >=20 > Clk_gen: Clk <=3D not Clk after Clock_Half_Period; >=20 > The clock period measured in the simulator is always 29.8 ns no matter wh= at resolution I set for the simulation time value. With the resolution set= to 10 fs I just measured the time of a clock and it is 29,800 ps. It shou= ld be 29,802 ps if rounded. That 2 ps is about two clock cycles out of the= 1 ms time period. I was trying to set limits for an assert to automatical= ly check this time. If I can't get the clock rate right, I won't be able t= o check any timings to full resolution... although I suppose the xtal isn't= much more accurate than this, slightly lower than 1 clock cycle per ms. = =20 I thought maybe I had found the problem, Clock_Half_Period being half the c= lock period getting rounded. But it should still be 14,901 ps so unless it= is being rounded at something larger than 1 ps that's not it. The value o= f Clock_Half_Period is reported to be 14,900 ps. I tried setting the value= to 14,901 ps and it still reports as 14,900 ps. So that seems to be the r= oot of the problem. I can't find a setting that will allow me to set this = to the pico second. =20 I was looking at some code to view this in more detail that uses an Aldec l= ibrary for time and without changing any of my code other than adding the l= ibrary and a couple of lines to show the system resolution, it is now showi= ng the value of Clock_Half_Period as 14,901 ps! Some irony, the Aldec code= writes to "output" and it never shows up on the console, so I never got an= answer to that one. Anyone knows where that goes? =20 That gets me close enough. There is still around 10 or 15 ns error in the = clock rate over a millisecond and about that much again error because of ro= unding the count in my circuit, so the total is just under 25 ns error. Th= at's what I set the test to. Now I'm testing a much slower strobe the same= way. No error reports there either. So this seems to be working now. I = wonder what happens if I take out the Aldec time library? =20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: David Higton Newsgroups: comp.lang.vhdl Subject: Re: VHDL Real Rounding Date: Sat, 19 Sep 2020 21:31:13 +0100 Organization: Home Lines: 41 Message-ID: <070b9bb258.DaveMeUK@BeagleBoard-xM> References: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> Injection-Info: reader02.eternal-september.org; posting-host="164e826ced5173aae1e6637329cc8b6c"; logging-data="29376"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ODd1wc9YoRS/a/ou1EX1XrtjlqtHcKf4=" User-Agent: Messenger-Pro/8.03 (MsgServe/8.01) (RISC-OS/5.27) NewsHound/v1.52-32 Cancel-Lock: sha1:o6jrDwdB3LtRQTEBaqdJSoTe8zM= Xref: reader02.eternal-september.org comp.lang.vhdl:9742 In message <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> Rick C wrote: > On Friday, September 18, 2020 at 1:25:09 PM UTC-4, Rick C wrote: > > CLK_HZ : REAL := 33.554432E6 -- 2^25 . . . > > constant MS_MAX_Cnt : integer := integer(ROUND(CLK_HZ/1000.0)) - 1; > > > > What should be the value of MS_MAX_Cnt, 33,555, 33,554 or 33,553? > > > > I say 33,553, the Aldec simulator says 33,554. Who's right? > > > > What am I missing about the operation of ROUND ? > > > > The definition says it adds 0.5 before taking the FLOOR of positive > > values. Even with the 0.5 added the FLOOR should make the value 33,554.0 > > then with the integer conversion 33,554 then minus 1 to give 33,553. > > I'm not sure what I was doing wrong, but I added statements to do the above > calculation one step at a time and it's getting the right number correctly > now with the original statement. So the count is right, but the time value > in the simulation is not right. > > CLK_HZ : REAL := 33.554432E6 > > constant Clock_Half_Period : time := 500 ms / CLK_HZ; > > Clk_gen: Clk <= not Clk after Clock_Half_Period; > > The clock period measured in the simulator is always 29.8 ns no matter what > resolution I set for the simulation time value. With the resolution set to > 10 fs I just measured the time of a clock and it is 29,800 ps. It should > be 29,802 ps if rounded. That 2 ps is about two clock cycles out of the 1 > ms time period. I was trying to set limits for an assert to automatically > check this time. If I can't get the clock rate right, I won't be able to > check any timings to full resolution... although I suppose the xtal isn't > much more accurate than this, slightly lower than 1 clock cycle per ms. Since VHDL fundamentally works in time, not frequency, why not define the clock period (or half period) rather than the frequency? David From newsfish@newsfish Thu Aug 1 00:45:49 2024 X-Received: by 2002:a0c:dd81:: with SMTP id v1mr27214993qvk.62.1600651676526; Sun, 20 Sep 2020 18:27:56 -0700 (PDT) X-Received: by 2002:a25:c444:: with SMTP id u65mr21280540ybf.188.1600651676323; Sun, 20 Sep 2020 18:27:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 20 Sep 2020 18:27:56 -0700 (PDT) In-Reply-To: <070b9bb258.DaveMeUK@BeagleBoard-xM> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:dcf6:3e7e:76b0:5da9; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:dcf6:3e7e:76b0:5da9 References: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> <070b9bb258.DaveMeUK@BeagleBoard-xM> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <10566bf8-9c45-4f12-9c83-39e562ddd5e2o@googlegroups.com> Subject: Re: VHDL Real Rounding From: Rick C Injection-Date: Mon, 21 Sep 2020 01:27:56 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9743 On Saturday, September 19, 2020 at 4:31:37 PM UTC-4, David Higton wrote: > In message <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> > Rick C wrote: >=20 > > On Friday, September 18, 2020 at 1:25:09 PM UTC-4, Rick C wrote: > > > CLK_HZ : REAL :=3D 33.554432E6 -- 2^25 . . . > > > constant MS_MAX_Cnt : integer :=3D integer(ROUND(CLK_HZ/1000.0)) - = 1; > > >=20 > > > What should be the value of MS_MAX_Cnt, 33,555, 33,554 or 33,553? =20 > > >=20 > > > I say 33,553, the Aldec simulator says 33,554. Who's right?=20 > > >=20 > > > What am I missing about the operation of ROUND ?=20 > > >=20 > > > The definition says it adds 0.5 before taking the FLOOR of positive > > > values. Even with the 0.5 added the FLOOR should make the value 33,5= 54.0 > > > then with the integer conversion 33,554 then minus 1 to give 33,553. = =20 > >=20 > > I'm not sure what I was doing wrong, but I added statements to do the a= bove > > calculation one step at a time and it's getting the right number correc= tly > > now with the original statement. So the count is right, but the time v= alue > > in the simulation is not right. =20 > >=20 > > CLK_HZ : REAL :=3D 33.554432E6 > >=20 > > constant Clock_Half_Period : time :=3D 500 ms / CLK_HZ; > >=20 > > Clk_gen: Clk <=3D not Clk after Clock_Half_Period; > >=20 > > The clock period measured in the simulator is always 29.8 ns no matter = what > > resolution I set for the simulation time value. With the resolution se= t to > > 10 fs I just measured the time of a clock and it is 29,800 ps. It shou= ld > > be 29,802 ps if rounded. That 2 ps is about two clock cycles out of th= e 1 > > ms time period. I was trying to set limits for an assert to automatica= lly > > check this time. If I can't get the clock rate right, I won't be able = to > > check any timings to full resolution... although I suppose the xtal isn= 't > > much more accurate than this, slightly lower than 1 clock cycle per ms.= =20 >=20 > Since VHDL fundamentally works in time, not frequency, why not define > the clock period (or half period) rather than the frequency? >=20 > David Yeah, that's not an entirely bad idea, but it doesn't change the nature of = this issue, limited control of resolution in simulation time. Or more accu= rately, the issue is not understanding how to control the resolution in tim= e. I'm starting to think the problem I've seen is that the setting I'm adj= usting doesn't take effect unless the simulator program is closed and reope= ned or something similar, like maybe the project. My computer crapped out = the other day and the value in simulation is now accurate to 100 ps. =20 It is working well enough and I've spent enough time investigating this mat= ter. At least I know that something will ultimately make it work with a ne= w time resolution setting, just not sure if I have to rub my tummy and pat = my head while doing it or not. =20 Thanks for responding.=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:49 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer03.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx46.ams4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Clocked Process, but Outside of the Clocked IF Newsgroups: comp.lang.vhdl References: <_Ii8H.52727$y14.29769@fx24.am4> <75c1bd32-ca01-4ddf-9fe6-8eb1cabebccbo@googlegroups.com> From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <75c1bd32-ca01-4ddf-9fe6-8eb1cabebccbo@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200920-6, 20/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 63 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Mon, 21 Sep 2020 07:28:13 UTC Organization: virginmedia.com Date: Mon, 21 Sep 2020 08:28:12 +0100 X-Received-Bytes: 4648 X-Received-Body-CRC: 342271522 Xref: reader02.eternal-september.org comp.lang.vhdl:9744 On 17/09/2020 18:28, Rick C wrote: > On Thursday, September 17, 2020 at 4:33:37 AM UTC-4, HT-Lab wrote: >> On 16/09/2020 18:30, Rick C wrote: >>> On Wednesday, September 16, 2020 at 2:59:10 AM UTC-4, HT-Lab wrote: >>>> On 16/09/2020 03:12, Charles Bailey wrote: >>>>> On 2020-09-15 14:54, Rick C wrote: >>>> .. >>>>> >>>>> Also, based on many years of experience doing timing analysis on >>>>> million+ latch ASICs, I would highly recommend using synchronous rather >>>>> than asynchronous resets wherever possible. >>>> >>>> Yes on ASIC's an asynchronous reset requires extra logic but this does >>>> not generally apply to FPGA's. Although I haven't checked I believe >>>> Microchip still recommends async reset for their FPGA's. >>>> >>>> I would advice you read up on the Wire satellite mission which in effect >>>> was lost due to the use of a Synchronous instead of an Asynchronous >>>> reset (Actel FPGA). >>>> >>>> Hans >>>> www.ht-lab.com >>> >>> Interesting. I would point to the designers as failing in two of the three conclusions drawn, failure to account for startup values and not reading all the documentation. I'm guilty of the second myself since it can be overwhelming to start in on a mountain of reading for a new device. But then I don't design multi-million dollar satellites. >>> >>> I don't agree with the third conclusion that an async reset is required. .. > I mean in the report. They had three conclusions. The third is "there should be a direct asynchronous path from the reset input for initialising the device state, being independent of any clock activity". Did you understand how this satellite failed and how an async reset could have saved it? >> The issue with the sync reset is the absence of a clock. That is the >> real issue, although I suppose a clock can fail. But if the clock has >> failed, what good will the reset do? Ough, you might want to think about that last statement again. > Power supply issues result in no controls being specified to work, including async resets. Really? Either you still don't understand asynchronous resets or you simply looking for an argument which I don't have time for, sorry. Hans. www.ht-lab.com > > The async nature of power on reset release is always an issue in FPGAs and must be managed. The real problem is that even if the global power on reset is synchronous, the propagation can be slow enough to not meet the synchronous setup time. So it must be managed locally, but only on certain critical circuits. > > >> If you are working on some user appliance then pressing the reset button >> twice is not a big deal but you are working on a ventilator right? > > Yes, but it doesn't power up/down. It has battery backup and the FPGA may never be powered down. But of course it has to be designed to power up correctly. That will be local sync resets that start state machines and such. Essentially, each critical circuit needs to be immune to problems from the release of the global async reset. Not hard to do at all. Much of my design relies on timing enables. If these enables are not released for a couple of clock cycles after the global async reset is released that's 99% of the design already. Then the remaining circuity needs to be handled on its own. > > Other than power up, there are no resets because there is no trusted source of a reset. Maybe building something into the touch pad would be a good idea??? Maybe not. > From newsfish@newsfish Thu Aug 1 00:45:49 2024 X-Received: by 2002:ac8:6f50:: with SMTP id n16mr23994242qtv.190.1600674699900; Mon, 21 Sep 2020 00:51:39 -0700 (PDT) X-Received: by 2002:a25:a85:: with SMTP id 127mr50279368ybk.143.1600674699664; Mon, 21 Sep 2020 00:51:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Sep 2020 00:51:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:dcf6:3e7e:76b0:5da9; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:dcf6:3e7e:76b0:5da9 References: <_Ii8H.52727$y14.29769@fx24.am4> <75c1bd32-ca01-4ddf-9fe6-8eb1cabebccbo@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <64ee4aca-0f41-4651-a8a3-d9098df12742o@googlegroups.com> Subject: Re: Clocked Process, but Outside of the Clocked IF From: Rick C Injection-Date: Mon, 21 Sep 2020 07:51:39 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 89 Xref: reader02.eternal-september.org comp.lang.vhdl:9745 On Monday, September 21, 2020 at 3:28:16 AM UTC-4, HT-Lab wrote: > On 17/09/2020 18:28, Rick C wrote: > > On Thursday, September 17, 2020 at 4:33:37 AM UTC-4, HT-Lab wrote: > >> On 16/09/2020 18:30, Rick C wrote: > >>> On Wednesday, September 16, 2020 at 2:59:10 AM UTC-4, HT-Lab wrote: > >>>> On 16/09/2020 03:12, Charles Bailey wrote: > >>>>> On 2020-09-15 14:54, Rick C wrote: > >>>> .. > >>>>> > >>>>> Also, based on many years of experience doing timing analysis on > >>>>> million+ latch ASICs, I would highly recommend using synchronous ra= ther > >>>>> than asynchronous resets wherever possible. > >>>> > >>>> Yes on ASIC's an asynchronous reset requires extra logic but this do= es > >>>> not generally apply to FPGA's. Although I haven't checked I believe > >>>> Microchip still recommends async reset for their FPGA's. > >>>> > >>>> I would advice you read up on the Wire satellite mission which in ef= fect > >>>> was lost due to the use of a Synchronous instead of an Asynchronous > >>>> reset (Actel FPGA). > >>>> > >>>> Hans > >>>> www.ht-lab.com > >>> > >>> Interesting. I would point to the designers as failing in two of the= three conclusions drawn, failure to account for startup values and not rea= ding all the documentation. I'm guilty of the second myself since it can b= e overwhelming to start in on a mountain of reading for a new device. But = then I don't design multi-million dollar satellites. > >>> > >>> I don't agree with the third conclusion that an async reset is requir= ed. >=20 > .. >=20 > > I mean in the report. They had three conclusions. The third is "there= should be a direct asynchronous path from the reset input for initialising= the device state, being independent of any clock activity". >=20 > Did you understand how this satellite failed and how an async reset=20 > could have saved it? I understand, but the failure was in the design process, not the lack of an= async reset. The idea of adding an async reset to every design ignores th= e fact that not all designs have the same requirements. In my case the FPG= A already provides a power on reset that is independent of an outside clock= working on an internal clock. Other than that no reset is required. Addi= ng any sort of additional reset uses logic for no benefit.=20 > >> The issue with the sync reset is the absence of a clock. That is the > >> real issue, although I suppose a clock can fail. But if the clock has > >> failed, what good will the reset do? >=20 > Ough, you might want to think about that last statement again. Please tell me what else was working or not working when the clock failed. = These are system issues, not simply a requirement for an async reset. Thi= s one solution doesn't fix every problem.=20 > > Power supply issues result in no controls being specified to work, incl= uding async resets. >=20 > Really? Yes, if the power supply is out of spec there is no guarantee any of the lo= gic will work correctly, reset or not. If the power supply signal goes bel= ow the voltage of the inputs the device will go into latchup. What good is= a reset signal then?=20 > Either you still don't understand asynchronous resets or you simply=20 > looking for an argument which I don't have time for, sorry. If you would actually try to discuss the issue rather than being silly abou= t insisting on an async reset without basing the opinion on reason and fact= s, maybe we could have a discussion.=20 Sorry you weren't interested in discussing the topic.=20 --=20 Rick C. ++ Get 1,000 miles of free Supercharging ++ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:50 2024 X-Received: by 2002:a0c:e04e:: with SMTP id y14mr491933qvk.38.1600700855068; Mon, 21 Sep 2020 08:07:35 -0700 (PDT) X-Received: by 2002:a25:4116:: with SMTP id o22mr402858yba.119.1600700854809; Mon, 21 Sep 2020 08:07:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Sep 2020 08:07:34 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2601:147:4002:f4bf:dcf6:3e7e:76b0:5da9; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2601:147:4002:f4bf:dcf6:3e7e:76b0:5da9 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL Static Signals From: Rick C Injection-Date: Mon, 21 Sep 2020 15:07:35 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9746 # Error: COMP96_0228: TestBench/Alarm_top_TB.vhd : (219, 26): The actual mu= st be denoted by a static signal name, if the actual is associated with a s= ignal parameter of any mode. signal Buttons : unsigned(3 downto 0); procedure Test_Button ( signal Buttons, Button_Action : in unsigned(3 downto 0); index : in integer range 3 downto 0; value : in std_logic) is begin -- wait until '1' =3D Buttons(index); wait until falling_edge(Buttons(index)); assert false report "Checking button " & integer'image(index); assert (Button_Action(index) =3D value) report "Invalid button action detected at time " &=20 time'image(now) & " button action =3D " & std_logic'image(Button_Action(index)); end procedure Test_Button; . . . test_KP: process is begin Test_Button (Buttons, Button_Press, 0, '0'); ... I think I get what a static signal is, but I'm not clear on what exactly is= wrong. They refer to the "actual" which is the value passed into the func= tion, no? What is not static about "Buttons"??? Is it the fact that the v= alue is not known until the code is run??? This error goes away when I rem= ove the signal designation from the declaration of parameters, but then it = barfs on using it to invoke the falling_edge function because it's not a si= gnal. =20 I'm so confused! Why does VHDL care if I make this a signal? Rather than = citing seemingly arbitrary VHDL rules, can anyone explain what problem this= rule is addressing?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:50 2024 X-Received: by 2002:a37:64d4:: with SMTP id y203mr706250qkb.359.1600707388802; Mon, 21 Sep 2020 09:56:28 -0700 (PDT) X-Received: by 2002:a25:3b91:: with SMTP id i139mr1102618yba.316.1600707388624; Mon, 21 Sep 2020 09:56:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer03.ams4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Sep 2020 09:56:28 -0700 (PDT) In-Reply-To: <10566bf8-9c45-4f12-9c83-39e562ddd5e2o@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=50.38.36.249; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.38.36.249 References: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> <070b9bb258.DaveMeUK@BeagleBoard-xM> <10566bf8-9c45-4f12-9c83-39e562ddd5e2o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e23e7e0-7abc-4278-8288-c4854790c956n@googlegroups.com> Subject: Re: VHDL Real Rounding From: Jim Lewis Injection-Date: Mon, 21 Sep 2020 16:56:28 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1607 X-Received-Body-CRC: 3392290264 Xref: reader02.eternal-september.org comp.lang.vhdl:9747 You could do your clock as: ClkProc : process begin Clk <= '0', '1' after Clock_Half_Period; wait for Clock_Period; end process ClkProc ; Divide by 2 issues will manifest WRT the placement of the rising edge, however, the time period between rising edges is Clock_Period. From newsfish@newsfish Thu Aug 1 00:45:50 2024 X-Received: by 2002:ac8:3ac4:: with SMTP id x62mr465771qte.279.1600707667073; Mon, 21 Sep 2020 10:01:07 -0700 (PDT) X-Received: by 2002:a25:1455:: with SMTP id 82mr1215410ybu.274.1600707666875; Mon, 21 Sep 2020 10:01:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Sep 2020 10:01:06 -0700 (PDT) In-Reply-To: <6e23e7e0-7abc-4278-8288-c4854790c956n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=50.38.36.249; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.38.36.249 References: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> <070b9bb258.DaveMeUK@BeagleBoard-xM> <10566bf8-9c45-4f12-9c83-39e562ddd5e2o@googlegroups.com> <6e23e7e0-7abc-4278-8288-c4854790c956n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7ac0b4c8-fda8-492a-adc5-6fcd4d167731n@googlegroups.com> Subject: Re: VHDL Real Rounding From: Jim Lewis Injection-Date: Mon, 21 Sep 2020 17:01:07 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9748 The previous post is similar to how CreateClock in the OSVVM library works. if you want to check that out, see https://github.com/OSVVM/OSVVM and look at the file TbUtilPkg.vhd. Create clock also allows for non-even duty cycles. From newsfish@newsfish Thu Aug 1 00:45:51 2024 X-Received: by 2002:a05:6214:1784:: with SMTP id ct4mr3188574qvb.10.1600734698516; Mon, 21 Sep 2020 17:31:38 -0700 (PDT) X-Received: by 2002:a25:b122:: with SMTP id g34mr3667713ybj.196.1600734698303; Mon, 21 Sep 2020 17:31:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Sep 2020 17:31:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=190.180.114.238; posting-account=EO_TKQoAAAA3En6FtORsBFifo6jP5PTf NNTP-Posting-Host: 190.180.114.238 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Error of IP of CI 7483 From: Victor Salazar Injection-Date: Tue, 22 Sep 2020 00:31:38 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9749 when i try to compile thisin ModelSim.. LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; LIBRARY work; ENTITY Lab_2 IS PORT ( ina1 : IN STD_LOGIC; ina2 : IN STD_LOGIC; ina3 : IN STD_LOGIC; ina4 : IN STD_LOGIC; inb1 : IN STD_LOGIC; inb2 : IN STD_LOGIC; inb3 : IN STD_LOGIC; inb4 : IN STD_LOGIC; o1 : OUT STD_LOGIC; o2 : OUT STD_LOGIC; o3 : OUT STD_LOGIC; o4 : OUT STD_LOGIC; outacarreo : OUT STD_LOGIC ); END Lab_2; ARCHITECTURE bdf_type OF Lab_2 IS --ATTRIBUTE black_box : BOOLEAN; --ATTRIBUTE noopt : BOOLEAN; COMPONENT 7483 PORT(C0 : IN STD_LOGIC; B4 : IN STD_LOGIC; A1 : IN STD_LOGIC; A2 : IN STD_LOGIC; B1 : IN STD_LOGIC; B2 : IN STD_LOGIC; A3 : IN STD_LOGIC; B3 : IN STD_LOGIC; A4 : IN STD_LOGIC; S3 : OUT STD_LOGIC; S4 : OUT STD_LOGIC; S2 : OUT STD_LOGIC; C4 : OUT STD_LOGIC; S1 : OUT STD_LOGIC) END COMPONENT; --ATTRIBUTE black_box OF 7483 : COMPONENT IS true; --ATTRIBUTE noopt OF 7483 : COMPONENT IS true; SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC; SIGNAL o11 : STD_LOGIC; SIGNAL o12 : STD_LOGIC; SIGNAL o13 : STD_LOGIC; SIGNAL o14 : STD_LOGIC; BEGIN SYNTHESIZED_WIRE_16 <= '0'; b2v_inst : 7483 PORT MAP(B4 => inb4, A1 => ina1, A2 => ina2, B1 => inb1, B2 => inb2, A3 => ina3, B3 => inb3, A4 => ina4, S3 => SYNTHESIZED_WIRE_19, S4 => SYNTHESIZED_WIRE_20, S2 => SYNTHESIZED_WIRE_17, C4 => SYNTHESIZED_WIRE_12, S1 => SYNTHESIZED_WIRE_1); b2v_inst1 : 7483 PORT MAP(B4 => SYNTHESIZED_WIRE_16, A1 => SYNTHESIZED_WIRE_1, A2 => SYNTHESIZED_WIRE_17, B1 => SYNTHESIZED_WIRE_16, B2 => SYNTHESIZED_WIRE_18, A3 => SYNTHESIZED_WIRE_19, B3 => SYNTHESIZED_WIRE_18, A4 => SYNTHESIZED_WIRE_20, S3 => o13, S4 => o14, S2 => o12, C4 => SYNTHESIZED_WIRE_15, S1 => o11); SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_20; SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_19 OR SYNTHESIZED_WIRE_17; SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_12 OR SYNTHESIZED_WIRE_13; outacarreo <= SYNTHESIZED_WIRE_18 OR SYNTHESIZED_WIRE_15; o1 <= o11; o2 <= o12; o3 <= o13; o4 <= o14; END bdf_type; it gives me this error... ** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER From newsfish@newsfish Thu Aug 1 00:45:51 2024 X-Received: by 2002:ac8:6f50:: with SMTP id n16mr2428316qtv.190.1600736546592; Mon, 21 Sep 2020 18:02:26 -0700 (PDT) X-Received: by 2002:a25:27c1:: with SMTP id n184mr3652196ybn.319.1600736546300; Mon, 21 Sep 2020 18:02:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Sep 2020 18:02:26 -0700 (PDT) In-Reply-To: <6e23e7e0-7abc-4278-8288-c4854790c956n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <80ef20dc-a184-49f9-a255-8b2dda4330ffo@googlegroups.com> <7c23ede7-48f0-48db-bd48-756c93c31d03o@googlegroups.com> <070b9bb258.DaveMeUK@BeagleBoard-xM> <10566bf8-9c45-4f12-9c83-39e562ddd5e2o@googlegroups.com> <6e23e7e0-7abc-4278-8288-c4854790c956n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL Real Rounding From: Rick C Injection-Date: Tue, 22 Sep 2020 01:02:26 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9750 On Monday, September 21, 2020 at 12:56:31 PM UTC-4, Jim Lewis wrote: > You could do your clock as: > ClkProc : process > begin > Clk <=3D '0', '1' after Clock_Half_Period;=20 > wait for Clock_Period; > end process ClkProc ;=20 >=20 > Divide by 2 issues will manifest WRT the placement of the rising edge, ho= wever, the time period between rising edges is Clock_Period. Thanks for the suggestion, but I don't think that really addresses the issu= e which is control of the simulator timing resolution. I think my real iss= ue is the timing resolution setting in the simulator doesn't have an impact= until something is reset, possibly the entire program closing. Until I fi= nd out I'm happy with the current 100 ps resolution. =20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:51 2024 X-Received: by 2002:ac8:1626:: with SMTP id p35mr2939727qtj.326.1600748372494; Mon, 21 Sep 2020 21:19:32 -0700 (PDT) X-Received: by 2002:a25:2e43:: with SMTP id b3mr4402977ybn.144.1600748372307; Mon, 21 Sep 2020 21:19:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Sep 2020 21:19:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d04078f-dcdf-419f-969b-ce495353c67eo@googlegroups.com> Subject: Re: Error of IP of CI 7483 From: Rick C Injection-Date: Tue, 22 Sep 2020 04:19:32 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 140 Xref: reader02.eternal-september.org comp.lang.vhdl:9751 On Monday, September 21, 2020 at 8:31:40 PM UTC-4, Victor Salazar wrote: > when i try to compile thisin ModelSim.. > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > LIBRARY work; > > ENTITY Lab_2 IS > PORT > ( > ina1 : IN STD_LOGIC; > ina2 : IN STD_LOGIC; > ina3 : IN STD_LOGIC; > ina4 : IN STD_LOGIC; > inb1 : IN STD_LOGIC; > inb2 : IN STD_LOGIC; > inb3 : IN STD_LOGIC; > inb4 : IN STD_LOGIC; > o1 : OUT STD_LOGIC; > o2 : OUT STD_LOGIC; > o3 : OUT STD_LOGIC; > o4 : OUT STD_LOGIC; > outacarreo : OUT STD_LOGIC > ); > END Lab_2; > > ARCHITECTURE bdf_type OF Lab_2 IS > > --ATTRIBUTE black_box : BOOLEAN; > --ATTRIBUTE noopt : BOOLEAN; > > COMPONENT 7483 > PORT(C0 : IN STD_LOGIC; > B4 : IN STD_LOGIC; > A1 : IN STD_LOGIC; > A2 : IN STD_LOGIC; > B1 : IN STD_LOGIC; > B2 : IN STD_LOGIC; > A3 : IN STD_LOGIC; > B3 : IN STD_LOGIC; > A4 : IN STD_LOGIC; > S3 : OUT STD_LOGIC; > S4 : OUT STD_LOGIC; > S2 : OUT STD_LOGIC; > C4 : OUT STD_LOGIC; > S1 : OUT STD_LOGIC) > END COMPONENT; > --ATTRIBUTE black_box OF 7483 : COMPONENT IS true; > --ATTRIBUTE noopt OF 7483 : COMPONENT IS true; > > SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC; > SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC; > SIGNAL o11 : STD_LOGIC; > SIGNAL o12 : STD_LOGIC; > SIGNAL o13 : STD_LOGIC; > SIGNAL o14 : STD_LOGIC; > > BEGIN > SYNTHESIZED_WIRE_16 <= '0'; > > > > b2v_inst : 7483 > PORT MAP(B4 => inb4, > A1 => ina1, > A2 => ina2, > B1 => inb1, > B2 => inb2, > A3 => ina3, > B3 => inb3, > A4 => ina4, > S3 => SYNTHESIZED_WIRE_19, > S4 => SYNTHESIZED_WIRE_20, > S2 => SYNTHESIZED_WIRE_17, > C4 => SYNTHESIZED_WIRE_12, > S1 => SYNTHESIZED_WIRE_1); > > > b2v_inst1 : 7483 > PORT MAP(B4 => SYNTHESIZED_WIRE_16, > A1 => SYNTHESIZED_WIRE_1, > A2 => SYNTHESIZED_WIRE_17, > B1 => SYNTHESIZED_WIRE_16, > B2 => SYNTHESIZED_WIRE_18, > A3 => SYNTHESIZED_WIRE_19, > B3 => SYNTHESIZED_WIRE_18, > A4 => SYNTHESIZED_WIRE_20, > S3 => o13, > S4 => o14, > S2 => o12, > C4 => SYNTHESIZED_WIRE_15, > S1 => o11); > > > SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_20; > > > SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_19 OR SYNTHESIZED_WIRE_17; > > > SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_12 OR SYNTHESIZED_WIRE_13; > > > outacarreo <= SYNTHESIZED_WIRE_18 OR SYNTHESIZED_WIRE_15; > > o1 <= o11; > o2 <= o12; > o3 <= o13; > o4 <= o14; > > END bdf_type; > > it gives me this error... > > ** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER The line above is saying there is an error detected at line 50. Do you know where line 50 is? The other clue they give is when they say "near 7483". Where do you see 7483 and how is it being used? The final clue is the words, "expecting IDENTIFIER". If they are referring to "7483" and saying "expecting IDENTIFIER" what does that tell you? How much VHDL have you written? Do you know the rules for identifiers in VHDL? Check your references. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:52 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Error of IP of CI 7483 Date: Tue, 22 Sep 2020 22:55:23 +0300 Organization: An impatient and LOUD arachnid Lines: 10 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain Injection-Info: reader02.eternal-september.org; posting-host="487800e243071622cf718aaa4dfdae89"; logging-data="11171"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/yzLcKxVmuRMhckusuewjT" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) Cancel-Lock: sha1:yGu3gAbSs31pkdvfkojXUl9pGl4= sha1:VajUiBQwaenVLoCa6VmXX6cylFA= Xref: reader02.eternal-september.org comp.lang.vhdl:9752 Victor Salazar writes: > it gives me this error... > > ** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER In VHDL basic identifiers start with a letter. In other words, you can't name your component 7483, that's a syntax error. (There are extended identifiers too but those don't allow 7483 as an identifier either.) From newsfish@newsfish Thu Aug 1 00:45:52 2024 X-Received: by 2002:a05:620a:661:: with SMTP id a1mr6611863qkh.92.1600806543945; Tue, 22 Sep 2020 13:29:03 -0700 (PDT) X-Received: by 2002:a25:5381:: with SMTP id h123mr9086022ybb.413.1600806543667; Tue, 22 Sep 2020 13:29:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Sep 2020 13:29:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Error of IP of CI 7483 From: KJ Injection-Date: Tue, 22 Sep 2020 20:29:03 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9753 On Tuesday, September 22, 2020 at 3:55:27 PM UTC-4, Anssi Saari wrote: > Victor Salazar writes: > > > it gives me this error... > > > > ** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER > In VHDL basic identifiers start with a letter. In other words, you can't > name your component 7483, that's a syntax error. (There are extended > identifiers too but those don't allow 7483 as an identifier either.) If you want 7483 as an identifier, you need to add the extended identifier backslash character before and after These are wrong... COMPONENT 7483 b2v_inst1 : 7483 These are correct COMPONENT \7483\ b2v_inst1 : \7483\ Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:52 2024 X-Received: by 2002:ac8:60d9:: with SMTP id i25mr6512070qtm.209.1600808009038; Tue, 22 Sep 2020 13:53:29 -0700 (PDT) X-Received: by 2002:a25:3b91:: with SMTP id i139mr9236844yba.316.1600808008833; Tue, 22 Sep 2020 13:53:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Sep 2020 13:53:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72af404e-f3e8-46a1-9813-5b520d755d60n@googlegroups.com> Subject: Re: VHDL Static Signals From: KJ Injection-Date: Tue, 22 Sep 2020 20:53:29 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9754 On Monday, September 21, 2020 at 11:07:37 AM UTC-4, gnuarm.del...@gmail.com= wrote: > I think I get what a static signal is, but I'm not clear on what exactly = is wrong. They refer to the "actual" which is the value passed into the fun= ction, no? What is not static about "Buttons"??? Is it the fact that the va= lue is not known until the code is run??? This error goes away when I remov= e the signal designation from the declaration of parameters, but then it ba= rfs on using it to invoke the falling_edge function because it's not a sign= al.=20 >=20 It's not 'Buttons' that the complaint is about, but 'Buttons(index)' which = is the input parameter to the falling_edge function. 'Buttons(index)' is n= ot static, hence the complaint. I don't know what problem this VHDL rule i= s addressing with the rule, but thought I'd clarify the actual complaint in= case someone else might know the reason for the rule. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:53 2024 X-Received: by 2002:a37:2715:: with SMTP id n21mr7490895qkn.401.1600817297641; Tue, 22 Sep 2020 16:28:17 -0700 (PDT) X-Received: by 2002:a25:a85:: with SMTP id 127mr11812555ybk.143.1600817297420; Tue, 22 Sep 2020 16:28:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Sep 2020 16:28:17 -0700 (PDT) In-Reply-To: <72af404e-f3e8-46a1-9813-5b520d755d60n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <72af404e-f3e8-46a1-9813-5b520d755d60n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <41c53d65-bbb6-4a32-a1af-6f0a0e200ef1o@googlegroups.com> Subject: Re: VHDL Static Signals From: Rick C Injection-Date: Tue, 22 Sep 2020 23:28:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9755 On Tuesday, September 22, 2020 at 4:53:31 PM UTC-4, KJ wrote: > On Monday, September 21, 2020 at 11:07:37 AM UTC-4, gnuarm.del...@gmail.c= om wrote: >=20 > > I think I get what a static signal is, but I'm not clear on what exactl= y is wrong. They refer to the "actual" which is the value passed into the f= unction, no? What is not static about "Buttons"??? Is it the fact that the = value is not known until the code is run??? This error goes away when I rem= ove the signal designation from the declaration of parameters, but then it = barfs on using it to invoke the falling_edge function because it's not a si= gnal.=20 > >=20 > It's not 'Buttons' that the complaint is about, but 'Buttons(index)' whic= h is the input parameter to the falling_edge function. 'Buttons(index)' is= not static, hence the complaint. I don't know what problem this VHDL rule= is addressing with the rule, but thought I'd clarify the actual complaint = in case someone else might know the reason for the rule. >=20 > Kevin Jennings Thanks. I eventually figured that out. It is the selection of the bit in = the procedure that it is complaining about. I changed the code to pass in = only the one bit of interest and in the process changed the nature of the t= est organization a bit too. These are button presses and I wish to test th= e debounce circuit.=20 Often I have a harder time constructing a test module than I did designing = the code. =20 I haven't found much use for procedures in the past, but that is likely a c= hicken and egg thing. I didn't use them because I wasn't familiar with the= m and I wasn't familiar with them because I didn't use them. In this case = it is allowing a simpler structure of the test code, so well worth a bit of= effort to get it working. The assert error messages alone can be rather m= essy when repeated in a body of code.=20 --=20 Rick C. ++ Get 1,000 miles of free Supercharging ++ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx36.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Error of IP of CI 7483 Newsgroups: comp.lang.vhdl References: From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 200922-12, 22/09/2020), Outbound message X-Antivirus-Status: Clean Lines: 30 Message-ID: X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Wed, 23 Sep 2020 08:18:18 UTC Organization: virginmedia.com Date: Wed, 23 Sep 2020 09:18:19 +0100 X-Received-Bytes: 2066 X-Received-Body-CRC: 3127190792 Xref: reader02.eternal-september.org comp.lang.vhdl:9756 On 22/09/2020 21:29, KJ wrote: > On Tuesday, September 22, 2020 at 3:55:27 PM UTC-4, Anssi Saari wrote: >> Victor Salazar writes: >> >>> it gives me this error... >>> >>> ** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near "7483": expecting IDENTIFIER >> In VHDL basic identifiers start with a letter. In other words, you can't >> name your component 7483, that's a syntax error. (There are extended >> identifiers too but those don't allow 7483 as an identifier either.) > > If you want 7483 as an identifier, you need to add the extended identifier backslash character before and after > > These are wrong... > COMPONENT 7483 > b2v_inst1 : 7483 > > These are correct > COMPONENT \7483\ > b2v_inst1 : \7483\ > > Kevin Jennings > Interesting, I have never seen this in any source code, I just tried it out and indeed it works fine. I suspect this is just a side effect on the language and not something VHDL users have actually asked for? Thanks, Hans. www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:45:53 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Error of IP of CI 7483 Date: Wed, 23 Sep 2020 13:46:06 +0300 Organization: An impatient and LOUD arachnid Lines: 17 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain Injection-Info: reader02.eternal-september.org; posting-host="e47f9bd97115d5c7724ffb436307edb8"; logging-data="10618"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/fDAM1gXkRJD87aKte3uMt" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) Cancel-Lock: sha1:ZpQb22abLT0weccTULNN45F8vx4= sha1:xlnz7PAJrUm08ghg9EIZ82aIhDQ= Xref: reader02.eternal-september.org comp.lang.vhdl:9757 HT-Lab writes: > On 22/09/2020 21:29, KJ wrote: >> These are correct >> COMPONENT \7483\ >> b2v_inst1 : \7483\ >> >> Kevin Jennings > Interesting, I have never seen this in any source code, I just tried > it out and indeed it works fine. I suspect this is just a side effect > on the language and not something VHDL users have actually asked for? It was apparently added to VHDL'93 so I guess someone did ask for it. I think it's common in synthesis generated names at least? Anyways, I think the syntax is awful and didn't show an example for that reason. From newsfish@newsfish Thu Aug 1 00:45:54 2024 X-Received: by 2002:a37:638d:: with SMTP id x135mr252796qkb.60.1600872315408; Wed, 23 Sep 2020 07:45:15 -0700 (PDT) X-Received: by 2002:a05:6902:4ae:: with SMTP id r14mr544016ybs.22.1600872314991; Wed, 23 Sep 2020 07:45:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 Sep 2020 07:45:14 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4cc6d444-7c58-4d68-8706-8d0541974b1dn@googlegroups.com> Subject: Re: Error of IP of CI 7483 From: KJ Injection-Date: Wed, 23 Sep 2020 14:45:15 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3741 X-Received-Body-CRC: 301669321 Xref: reader02.eternal-september.org comp.lang.vhdl:9758 On Wednesday, September 23, 2020 at 6:46:10 AM UTC-4, Anssi Saari wrote: > HT-Lab writes:=20 >=20 > > On 22/09/2020 21:29, KJ wrote:=20 >=20 > >> These are correct=20 > >> COMPONENT \7483\=20 > >> b2v_inst1 : \7483\=20 > >>=20 > >> Kevin Jennings=20 >=20 > > Interesting, I have never seen this in any source code, I just tried=20 > > it out and indeed it works fine. I suspect this is just a side effect= =20 > > on the language and not something VHDL users have actually asked for? > It was apparently added to VHDL'93 so I guess someone did ask for it. I= =20 > think it's common in synthesis generated names at least? Anyways, I=20 > think the syntax is awful and didn't show an example for that reason. I use the extended identifier backslash in simulation models for ICs as a w= ay for the VHDL names to remain faithful to the datasheet. In the original= post, the '7483' is clearly referring to an IC. But an actual datasheet t= hat you could (and should) reference in your model might be the SN7483 . S= o to avoid the extended character backslash, I would call the entity SN7483= and there is no confusion. Where it gets trickier can be for the signal pin names on the IC. Names li= ke the following come up on old and new parts: 1A io2/lvds15p/crc_error In the first case you could rename it as 'A1', in the second maybe you repl= ace the forward slash with an underscore but these changes morph the VHDL m= odel pin name away from what the manufacturer has named the pin so it can l= ead to confusion by any future user of that model. It's 'better' to just u= se the manufacturer's pin name in the form of an extended identifier like t= his \1A\ \io2/lvds15p/crc_error\ 'Better' of course is a relative thing that depends on the user. Because t= he extended identifier notation is not commonly known, it can create its ow= n confusion. However, renaming things creates confusion as well. I don't = know for sure what motivated the change to the language in 1993 that added = the extended identifier but I suspect that it was for exactly this situatio= n of being able to specify the manufacturer's name 'as-is'. For one's own design code, the designer names the entity and the in/out sig= nals so there is probably no good reason for using the extended identifier. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:54 2024 X-Received: by 2002:a05:620a:5b1:: with SMTP id q17mr972875qkq.384.1600980418630; Thu, 24 Sep 2020 13:46:58 -0700 (PDT) X-Received: by 2002:a25:5ed4:: with SMTP id s203mr841451ybb.427.1600980418349; Thu, 24 Sep 2020 13:46:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2020 13:46:58 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <16b509e0-20b7-4361-a3e6-45174693e87fo@googlegroups.com> Subject: VHDL, easy peasy, right? From: Rick C Injection-Date: Thu, 24 Sep 2020 20:46:58 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9759 Another day, another syntax issue...=20 In my project library file.=20 constant LED_Data_Max : natural :=3D 23; subtype LED_Data_Type is unsigned (LED_Data_Max downto 0); type LED_RED_rng is range 23 downto 16; type LED_GRN_rng is range 15 downto 8; type LED_BLU_rng is range 7 downto 0; In the entity... procedure CommonAssert ( LED_addr : natural; RGB : LED_Data_Type; Color_Ref : LED_Data_Type ) is begin assert (RGB =3D Color_Ref) report " LED " & integer'image(LED_addr) & " error, time =3D " & time'image(now) & ", Red =3D " & to_hstring(RGB(LED_RED_rng)) & ... The error complains about LED_RED_rng "Type of discrete range is different from the corresponding index" I just don't get what I am doing wrong. What would the discrete range "typ= e" be??? Is this the same sort of problem I had previously where a non-con= stant can't be used to select a bit from a vector? Or is it so restrictive= that I can't even use a fixed range of bits that aren't the entire vector?= =20 I would say I'm ready to use Verilog but I think that might be even more cl= umsy when trying to do things like this particular detail.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:54 2024 X-Received: by 2002:ac8:7251:: with SMTP id l17mr2894561qtp.364.1601011577545; Thu, 24 Sep 2020 22:26:17 -0700 (PDT) X-Received: by 2002:a25:5985:: with SMTP id n127mr3076115ybb.53.1601011577260; Thu, 24 Sep 2020 22:26:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2020 22:26:16 -0700 (PDT) In-Reply-To: <16b509e0-20b7-4361-a3e6-45174693e87fo@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=176.59.70.168; posting-account=n7aJ0QoAAAAM9S9cFo4hml0ohYBnwXyL NNTP-Posting-Host: 176.59.70.168 References: <16b509e0-20b7-4361-a3e6-45174693e87fo@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9144336d-71d6-4081-8f9f-ca8d26494e0fo@googlegroups.com> Subject: Re: VHDL, easy peasy, right? From: andrew_b Injection-Date: Fri, 25 Sep 2020 05:26:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: base64 X-Received-Bytes: 1520 X-Received-Body-CRC: 3701409257 Xref: reader02.eternal-september.org comp.lang.vhdl:9760 0YfQtdGC0LLQtdGA0LMsIDI0INGB0LXQvdGC0Y/QsdGA0Y8gMjAyMCDQsy4sIDIzOjQ3OjAxIFVU QyszINC/0L7Qu9GM0LfQvtCy0LDRgtC10LvRjCBSaWNrIEMg0L3QsNC/0LjRgdCw0Ls6DQo+ICAg dHlwZSBMRURfUkVEX3JuZwlpcyByYW5nZSAyMyBkb3dudG8gMTY7DQoNCnN1YnR5cGUgTEVEX1JF RF9ybmcgaXMgaW50ZWdlciByYW5nZSAyMyBkb3dudG8gMTY7DQoNCi0tIA0KQW5kcmV3DQo= From newsfish@newsfish Thu Aug 1 00:45:55 2024 X-Received: by 2002:a37:6393:: with SMTP id x141mr383223qkb.238.1601045814751; Fri, 25 Sep 2020 07:56:54 -0700 (PDT) X-Received: by 2002:a25:5381:: with SMTP id h123mr5617566ybb.413.1601045814516; Fri, 25 Sep 2020 07:56:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2020 07:56:54 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=151.74.144.1; posting-account=dDnn2woAAAB9om-9d_J88-x8bqc00M3o NNTP-Posting-Host: 151.74.144.1 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72935462-ba97-4e1f-a43a-f033186f17ccn@googlegroups.com> Subject: vhdl help project From: Babyla Injection-Date: Fri, 25 Sep 2020 14:56:54 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 3 Xref: reader02.eternal-september.org comp.lang.vhdl:9761 I'm a beginner in vhdl and I'm developing a parking management system. At the moment I have made a "basic" version that seems to work properly. This includes a counter to manage the entry and exit of cars and provided the number of available parking spaces. Now I would like to take another step forward! I would like to implement a control unit to manage the parking payment, but maybe it is too complicated for a beginner, what do you think? I would like that when a car enters, the time is memorized and when it leaves, the user must enter the parking number and the difference in time and cost will be calculated. Being at first experiences I have difficulty in modeling this. From newsfish@newsfish Thu Aug 1 00:45:55 2024 X-Received: by 2002:a0c:c244:: with SMTP id w4mr140602qvh.12.1601049823148; Fri, 25 Sep 2020 09:03:43 -0700 (PDT) X-Received: by 2002:a25:8e05:: with SMTP id p5mr6535980ybl.370.1601049822925; Fri, 25 Sep 2020 09:03:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2020 09:03:42 -0700 (PDT) In-Reply-To: <9144336d-71d6-4081-8f9f-ca8d26494e0fo@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <16b509e0-20b7-4361-a3e6-45174693e87fo@googlegroups.com> <9144336d-71d6-4081-8f9f-ca8d26494e0fo@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL, easy peasy, right? From: Rick C Injection-Date: Fri, 25 Sep 2020 16:03:43 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 33 Xref: reader02.eternal-september.org comp.lang.vhdl:9762 On Friday, September 25, 2020 at 1:26:20 AM UTC-4, andrew_b wrote: > =D1=87=D0=B5=D1=82=D0=B2=D0=B5=D1=80=D0=B3, 24 =D1=81=D0=B5=D0=BD=D1=82= =D1=8F=D0=B1=D1=80=D1=8F 2020 =D0=B3., 23:47:01 UTC+3 =D0=BF=D0=BE=D0=BB=D1= =8C=D0=B7=D0=BE=D0=B2=D0=B0=D1=82=D0=B5=D0=BB=D1=8C Rick C =D0=BD=D0=B0=D0= =BF=D0=B8=D1=81=D0=B0=D0=BB: > > type LED_RED_rng is range 23 downto 16; >=20 > subtype LED_RED_rng is integer range 23 downto 16; That doesn't do what I want. RGB is 24 bit data and I wish to extract the = upper 8 bits. That requires a range. I don't want to do the math in every= use, so a named range.=20 This is provided in the standard. But I am not using it correctly and I do= n't understand why.=20 To make it more clear, there are two more named ranges and two more lines o= f similar code.=20 ", Green =3D " & to_hstring(RGB(LED_GRN_rng)) &=20 ", Blue =3D " & to_hstring(RGB(LED_BLU_rng)) &=20 To use the subtype you've defined it would need to be=20 ", Red =3D " & to_hstring(RGB(LED_RED_rng'range)) &=20 which is still more complexity than desired. =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:55 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed3-b.proxad.net!nnrp1-1.free.fr!not-for-mail Subject: Re: VHDL, easy peasy, right? Newsgroups: comp.lang.vhdl References: <16b509e0-20b7-4361-a3e6-45174693e87fo@googlegroups.com> <9144336d-71d6-4081-8f9f-ca8d26494e0fo@googlegroups.com> From: Nicolas Matringe Date: Fri, 25 Sep 2020 23:24:55 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Lines: 24 Message-ID: <5f6e6027$0$21612$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Sep 2020 23:24:55 CEST NNTP-Posting-Host: 88.123.153.23 X-Trace: 1601069095 news-1.free.fr 21612 88.123.153.23:15626 X-Complaints-To: abuse@proxad.net Xref: reader02.eternal-september.org comp.lang.vhdl:9763 On 9/25/20 6:03 PM, Rick C wrote: > On Friday, September 25, 2020 at 1:26:20 AM UTC-4, andrew_b wrote: >> четверг, 24 сентября 2020 г., 23:47:01 UTC+3 пользователь Rick C написал: >>> type LED_RED_rng is range 23 downto 16; >> >> subtype LED_RED_rng is integer range 23 downto 16; > > That doesn't do what I want. Well I really think it does. [...] > To use the subtype you've defined it would need to be > > ", Red = " & to_hstring(RGB(LED_RED_rng'range)) & > > which is still more complexity than desired. No, the range attribute is only defined for objects of the array types. Again, I really think Andrew's suggestion is the way to go (I would have used natural instead of integer but it doesn't change anything) Nicolas From newsfish@newsfish Thu Aug 1 00:45:56 2024 X-Received: by 2002:a05:620a:89e:: with SMTP id b30mr2534100qka.231.1601076272346; Fri, 25 Sep 2020 16:24:32 -0700 (PDT) X-Received: by 2002:a05:6902:50e:: with SMTP id x14mr2121659ybs.273.1601076272091; Fri, 25 Sep 2020 16:24:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2020 16:24:31 -0700 (PDT) In-Reply-To: <5f6e6027$0$21612$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <16b509e0-20b7-4361-a3e6-45174693e87fo@googlegroups.com> <9144336d-71d6-4081-8f9f-ca8d26494e0fo@googlegroups.com> <5f6e6027$0$21612$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL, easy peasy, right? From: Rick C Injection-Date: Fri, 25 Sep 2020 23:24:32 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9764 On Friday, September 25, 2020 at 5:24:58 PM UTC-4, Nicolas Matringe wrote: > On 9/25/20 6:03 PM, Rick C wrote: > > On Friday, September 25, 2020 at 1:26:20 AM UTC-4, andrew_b wrote: > >> =D1=87=D0=B5=D1=82=D0=B2=D0=B5=D1=80=D0=B3, 24 =D1=81=D0=B5=D0=BD=D1= =82=D1=8F=D0=B1=D1=80=D1=8F 2020 =D0=B3., 23:47:01 UTC+3 =D0=BF=D0=BE=D0=BB= =D1=8C=D0=B7=D0=BE=D0=B2=D0=B0=D1=82=D0=B5=D0=BB=D1=8C Rick C=20 > =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BB: > >>> type LED_RED_rng is range 23 downto 16; > >> > >> subtype LED_RED_rng is integer range 23 downto 16; > > > > That doesn't do what I want. > Well I really think it does. >=20 >=20 > [...] > > To use the subtype you've defined it would need to be > > > > ", Red =3D " & to_hstring(RGB(LED_RED_rng'range)) & > > > > which is still more complexity than desired. >=20 > No, the range attribute is only defined for objects of the array types.= =20 > Again, I really think Andrew's suggestion is the way to go (I would have= =20 > used natural instead of integer but it doesn't change anything) >=20 > Nicolas Please show me what you mean. I don't see how to use an integer subtype to= select the bits 23 downto 16 in the array RGB. Is it just =20 RGB(LED_RED_rng) ???=20 I would not expect that to work. Perhaps you can explain?=20 I did see an example showing=20 type Field_Range is range UPPER_BOUND downto LOWER_BOUND; It was in a discussion rather than from an authoritative source.=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:56 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!buffer1.nntp.ams1.giganews.com!buffer2.nntp.ams1.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 26 Sep 2020 01:15:24 -0500 Reply-To: mk@mkesc.co.uk Subject: Re: vhdl help project Newsgroups: comp.lang.vhdl References: <72935462-ba97-4e1f-a43a-f033186f17ccn@googlegroups.com> From: Michael Kellett Date: Sat, 26 Sep 2020 07:15:29 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <72935462-ba97-4e1f-a43a-f033186f17ccn@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Message-ID: Lines: 22 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-3uFRptF8g0IgTgI/OY0cYxnZfxQKvR2d3j57897KfE6inci+pKjEk5EAzOkcVoX2gG1Q+9TLnSLARl7!vKLhHn6Fqn3RAVBOhL1j8CAyAnILPl7udfoSZPNhNrLNMq2qMKRRRg95v6nhrmnIcP/wnlpDdn4= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2716 Xref: reader02.eternal-september.org comp.lang.vhdl:9765 On 25/09/2020 15:56, Babyla wrote: > I'm a beginner in vhdl and I'm developing a parking management system. > At the moment I have made a "basic" version that seems to work properly. This includes a counter to manage the entry and exit of cars and provided the number of available parking spaces. > Now I would like to take another step forward! I would like to implement a control unit to manage the parking payment, but maybe it is too complicated for a beginner, what do you think? > I would like that when a car enters, the time is memorized and when it leaves, the user must enter the parking number and the difference in time and cost will be calculated. Being at first experiences I have difficulty in modeling this. > This seems to be a very strange project for VHDL (and I assume an FPGA). You will need a clock and to have the ability to store times and manipulate them and then use time differences to access a look up table of charges. None of this is very difficult in VHDL or on FPGA but it is much, much cheaper and easier to develop on a micro controller in C or C++. If it's just for learning then fair enough. I would start by defining the task in natural langauge. Then break it into small steps, maybe a flow chart and/or state diagram if you like them. Then a set of requirements if you are a pedantic type. And so on, just like any other project. There are lots of books and plenty of web stuff about describing/modelling problems. MK From newsfish@newsfish Thu Aug 1 00:45:56 2024 X-Received: by 2002:aed:2b86:: with SMTP id e6mr3232157qtd.86.1601101673096; Fri, 25 Sep 2020 23:27:53 -0700 (PDT) X-Received: by 2002:a25:730a:: with SMTP id o10mr3837912ybc.403.1601101672844; Fri, 25 Sep 2020 23:27:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2020 23:27:52 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <72935462-ba97-4e1f-a43a-f033186f17ccn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: vhdl help project From: Rick C Injection-Date: Sat, 26 Sep 2020 06:27:53 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9766 On Saturday, September 26, 2020 at 2:15:28 AM UTC-4, Michael Kellett wrote: > On 25/09/2020 15:56, Babyla wrote: > > I'm a beginner in vhdl and I'm developing a parking management system. > > At the moment I have made a "basic" version that seems to work properly. This includes a counter to manage the entry and exit of cars and provided the number of available parking spaces. > > Now I would like to take another step forward! I would like to implement a control unit to manage the parking payment, but maybe it is too complicated for a beginner, what do you think? > > I would like that when a car enters, the time is memorized and when it leaves, the user must enter the parking number and the difference in time and cost will be calculated. Being at first experiences I have difficulty in modeling this. > > > This seems to be a very strange project for VHDL (and I assume an FPGA). > You will need a clock and to have the ability to store times and > manipulate them and then use time differences to access a look up table > of charges. None of this is very difficult in VHDL or on FPGA but it is > much, much cheaper and easier to develop on a micro controller in C or C++. > If it's just for learning then fair enough. > I would start by defining the task in natural langauge. > Then break it into small steps, maybe a flow chart and/or state diagram > if you like them. > Then a set of requirements if you are a pedantic type. > And so on, just like any other project. > > There are lots of books and plenty of web stuff about > describing/modelling problems. > > MK If you are the pedantic type you can develop a set of requirements after you have designed the circuits. If you are the effective type you will develop the requirements first. It saves time in the long run. Requirements writing is a skill like any other. Do a good job and you will be effective. Ignore that part of your work and the entire project will suffer. But if you are designing a hobby project, requirements are virtually never done. So we don't learn how to do them well and feel they are not useful. That's simply a sign that they are not understood. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:57 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed2-a.proxad.net!nnrp1-2.free.fr!not-for-mail Subject: Re: VHDL, easy peasy, right? Newsgroups: comp.lang.vhdl References: <16b509e0-20b7-4361-a3e6-45174693e87fo@googlegroups.com> <9144336d-71d6-4081-8f9f-ca8d26494e0fo@googlegroups.com> <5f6e6027$0$21612$426a74cc@news.free.fr> From: Nicolas Matringe Date: Sat, 26 Sep 2020 11:14:10 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Lines: 48 Message-ID: <5f6f0663$0$6206$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 26 Sep 2020 11:14:11 CEST NNTP-Posting-Host: 88.123.153.23 X-Trace: 1601111651 news-3.free.fr 6206 88.123.153.23:15036 X-Complaints-To: abuse@proxad.net Xref: reader02.eternal-september.org comp.lang.vhdl:9767 On 9/26/20 1:24 AM, Rick C wrote: > On Friday, September 25, 2020 at 5:24:58 PM UTC-4, Nicolas Matringe wrote: >> On 9/25/20 6:03 PM, Rick C wrote: >> > On Friday, September 25, 2020 at 1:26:20 AM UTC-4, andrew_b wrote: >> >> четверг, 24 сентября 2020 г., 23:47:01 UTC+3 пользователь Rick C >> написал: >> >>> type LED_RED_rng is range 23 downto 16; >> >> >> >> subtype LED_RED_rng is integer range 23 downto 16; >> > >> > That doesn't do what I want. >> Well I really think it does. >> >> >> [...] >> > To use the subtype you've defined it would need to be >> > >> > ", Red = " & to_hstring(RGB(LED_RED_rng'range)) & >> > >> > which is still more complexity than desired. >> >> No, the range attribute is only defined for objects of the array types. >> Again, I really think Andrew's suggestion is the way to go (I would have >> used natural instead of integer but it doesn't change anything) >> >> Nicolas > > Please show me what you mean. I don't see how to use an integer subtype to select the bits 23 downto 16 in the array RGB. Is it just > > RGB(LED_RED_rng) > > ??? > > I would not expect that to work. Perhaps you can explain? Well I'm sorry I can't explain the reasons behind this, I'm not an LRM expert. I am absolutely no authoritative source. I know, because I've used it in the past, that you can define a subtype and use it as a range, at least in the declaration of an array object : subtype my_range is natural range 23 downto 16; signal my_vector is std_logic_vector(my_range); I see no reason why this wouldn't work in your case. Why don't you give it a try ? Nicolas From newsfish@newsfish Thu Aug 1 00:45:57 2024 X-Received: by 2002:a05:620a:140d:: with SMTP id d13mr6636201qkj.330.1601167438991; Sat, 26 Sep 2020 17:43:58 -0700 (PDT) X-Received: by 2002:a25:868c:: with SMTP id z12mr7870336ybk.195.1601167438839; Sat, 26 Sep 2020 17:43:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 26 Sep 2020 17:43:58 -0700 (PDT) In-Reply-To: <5f6f0663$0$6206$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <16b509e0-20b7-4361-a3e6-45174693e87fo@googlegroups.com> <9144336d-71d6-4081-8f9f-ca8d26494e0fo@googlegroups.com> <5f6e6027$0$21612$426a74cc@news.free.fr> <5f6f0663$0$6206$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <67a1a10d-c2cc-4727-b3c2-562c25405f9eo@googlegroups.com> Subject: Re: VHDL, easy peasy, right? From: Rick C Injection-Date: Sun, 27 Sep 2020 00:43:58 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9768 On Saturday, September 26, 2020 at 5:14:14 AM UTC-4, Nicolas Matringe wrote= : > On 9/26/20 1:24 AM, Rick C wrote: > > On Friday, September 25, 2020 at 5:24:58 PM UTC-4, Nicolas Matringe=20 > wrote: > >> On 9/25/20 6:03 PM, Rick C wrote: > >> > On Friday, September 25, 2020 at 1:26:20 AM UTC-4, andrew_b wrote= : > >> >> =D1=87=D0=B5=D1=82=D0=B2=D0=B5=D1=80=D0=B3, 24 =D1=81=D0=B5=D0= =BD=D1=82=D1=8F=D0=B1=D1=80=D1=8F 2020 =D0=B3., 23:47:01 UTC+3 =D0=BF=D0=BE= =D0=BB=D1=8C=D0=B7=D0=BE=D0=B2=D0=B0=D1=82=D0=B5=D0=BB=D1=8C Rick C > >> =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BB: > >> >>> type LED_RED_rng is range 23 downto 16; > >> >> > >> >> subtype LED_RED_rng is integer range 23 downto 16; > >> > > >> > That doesn't do what I want. > >> Well I really think it does. > >> > >> > >> [...] > >> > To use the subtype you've defined it would need to be > >> > > >> > ", Red =3D " & to_hstring(RGB(LED_RED_rng'range)) & > >> > > >> > which is still more complexity than desired. > >> > >> No, the range attribute is only defined for objects of the array type= s. > >> Again, I really think Andrew's suggestion is the way to go (I would h= ave > >> used natural instead of integer but it doesn't change anything) > >> > >> Nicolas > > > > Please show me what you mean. I don't see how to use an integer=20 > subtype to select the bits 23 downto 16 in the array RGB. Is it just > > > > RGB(LED_RED_rng) > > > > ??? > > > > I would not expect that to work. Perhaps you can explain? > Well I'm sorry I can't explain the reasons behind this, I'm not an LRM=20 > expert. I am absolutely no authoritative source. > I know, because I've used it in the past, that you can define a subtype= =20 > and use it as a range, at least in the declaration of an array object : >=20 > subtype my_range is natural range 23 downto 16; > signal my_vector is std_logic_vector(my_range); >=20 > I see no reason why this wouldn't work in your case. Why don't you give= =20 > it a try ? >=20 > Nicolas Ok, but you aren't saying it will work, you are saying it might work, try i= t. Sort of the hydroxychloroquine approach. =20 I've worked around the issue now and have moved onto other parts of the des= ign. When I have the time I may try it. =20 Thanks,=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:57 2024 X-Received: by 2002:a05:6214:929:: with SMTP id dk9mr5212189qvb.60.1601395418284; Tue, 29 Sep 2020 09:03:38 -0700 (PDT) X-Received: by 2002:a5b:ad1:: with SMTP id a17mr6659577ybr.488.1601395417956; Tue, 29 Sep 2020 09:03:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2020 09:03:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: 64 Bit Integers From: Rick C Injection-Date: Tue, 29 Sep 2020 16:03:38 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9769 I know the standard requires 32 bit signed integer range, but does not rest= rict vendors from supplying larger ranges. However extending the range of = "integer" may break existing code. Is there any consideration to a new dat= a type which would be larger integers? Then the usages would be independen= t and not subject to breaking existing code. =20 I think the same thing applies to the REAL type. It's just that many langu= ages allow simple indication of the size of integer and real you wish to wo= rk with. Why is this so hard to figure out in HDL?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:58 2024 X-Received: by 2002:a05:6214:929:: with SMTP id dk9mr5517490qvb.60.1601399610158; Tue, 29 Sep 2020 10:13:30 -0700 (PDT) X-Received: by 2002:a25:5985:: with SMTP id n127mr7295707ybb.53.1601399609965; Tue, 29 Sep 2020 10:13:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2020 10:13:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Variable Registers From: Rick C Injection-Date: Tue, 29 Sep 2020 17:13:30 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 28 Xref: reader02.eternal-september.org comp.lang.vhdl:9770 I typically don't use variables much, but I like the limited scope which me= ans fewer "global" signals cluttering up the declaration portion of an enti= ty. But they can be a bit tricky to use because of the nature of the assig= nments.=20 I was just sculpting a section of code that used a couple of down counters = as variables and kept finding myself altering the value before I checked it= . To work around that I had to do multiple assignments in multiple branche= s of IFs. Using a signal I would have made one assignment at the top of th= e section of code, the default case, then one other assignment in a single = branch of the IFs. Since the counter value was in the first conditional th= at could not be done with a variable as it would be examining the updated v= alue. =20 In the end I had to use three assignments instead of two more clear ones to= avoid the signal declaration. =20 Signals are also easier to show in the waveform display during simulation a= s I can throw up everything in the entity in one click. The variables requ= ire a little more work.=20 Not sure I have a question, just a comment really. =20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:58 2024 X-Received: by 2002:ac8:1626:: with SMTP id p35mr6533134qtj.326.1601543967548; Thu, 01 Oct 2020 02:19:27 -0700 (PDT) X-Received: by 2002:a25:730a:: with SMTP id o10mr9414617ybc.403.1601543967322; Thu, 01 Oct 2020 02:19:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2020 02:19:27 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <31021fd3-4e2e-41d5-9bf5-d6ae2e05d940o@googlegroups.com> Subject: VHDL Don't Care From: Rick C Injection-Date: Thu, 01 Oct 2020 09:19:27 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 74 Xref: reader02.eternal-september.org comp.lang.vhdl:9771 I have a clumsy section of code that is simply complex combinational with n= o good way around it. There are 14 inputs compared to several vectors, red= uced to a single bit to control a few nested IF statements. In each IF sta= tement there are WITH statements with six selections to assign values to a = signal. This is all encapsulated in a function.=20 In most of the WITH statements there is one selection that is a don't care = since it won't be used. I'm wondering if VHDL has any way to make use of t= he don't care to optimize the decoding logic which I expect to be rather la= rge. =20 In two of the IF branches a similar issue arises in that the selection sign= al of the WITH is actually irrelevant since none of the cases other than on= e will be used. I can leave out the WITH, but I'm not sure that would prod= uce more simple logic than if the selection signal were used with a don't c= are. =20 So other than trying synthesis with the code written with don't cares, how = can I know if this will help or even work at all? The only info I can find= on VHDL don't cares relates to specific language features like std_match()= or case? =20 Using case? in place of with doesn't actually help since the optimization i= s not about the selection value. But that does make me realize I am only u= sing six of eight possible values of the selection value. That signal is a= n integer range 0 to 5, but that will still be implemented as a 3 bit signa= l in the logic. So there are two possible inputs not specified. Will that= create a latch in the combinational logic or will the range specification = prevent that??? I suppose an others clause will help with that, but it sti= ll would be better with an assignment of a don't care. =20 Maybe it would be good to show some code. =20 subtype Alarm_Type is unsigned (Alarm_Sel_Max downto Tidal_Vol_Sel); subtype Tone_Seq is natural range 0 to 5; function Alarm_Tones (Sequence_Num : Tone_Seq; Alarm_Src : Alarm_Type) return natural is variable ret_val : natural range 0 to Step_Max :=3D 0; begin if (Alarm_Src(Tick_Sel) then ret_val :=3D twokHz_step; -- Sequence_Num always =3D 0 elsif (Alarm_Src(Boop_Sel)) then ret_val :=3D G3_step; -- Sequence_Num always =3D 0 elsif (OR (Alarm_Src AND VentTones)) then with Sequence_Num select ret_val :=3D C4_step when 0, A4_step when 1, F4_step when 2, (others =3D> '-') when 3, -- tone 3 is a gap tone A4_step when 4, F4_step when 5; elsif (OR (Alarm_Src AND OxygenTones)) then with Sequence_Num select ret_val :=3D C5_step when 0, B4_step when 1, and so forth for many lines... The case of "when 3" above will recur in every subsequent ELSIF. So in the= end, the explicit case of Sequence_Num =3D 3 as well as the unreachable ca= ses of Sequence_Num =3D 6 and 7 can be optimized as the tool sees fit. Thi= s may end up being a rather complex bit of logic so I think it does need at= tention for optimization.=20 I have not yet installed the Gowin tools. Maybe I need to do that and try = some cases. The synthesis docs don't talk about this at all.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:58 2024 X-Received: by 2002:a05:620a:1478:: with SMTP id j24mr7142024qkl.93.1601548779966; Thu, 01 Oct 2020 03:39:39 -0700 (PDT) X-Received: by 2002:a25:5ed4:: with SMTP id s203mr9135303ybb.427.1601548779594; Thu, 01 Oct 2020 03:39:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2020 03:39:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:bd80:3a2:f435:b27; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:bd80:3a2:f435:b27 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5b5f1647-4e27-4b1b-85d5-e9c72e6ad49fn@googlegroups.com> Subject: Re: 64 Bit Integers From: KJ Injection-Date: Thu, 01 Oct 2020 10:39:39 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9772 On Tuesday, September 29, 2020 at 12:03:42 PM UTC-4, gnuarm.del...@gmail.co= m wrote: > I know the standard requires 32 bit signed integer range, but does not re= strict vendors from supplying larger ranges. However extending the range of= "integer" may break existing code. Is there any consideration to a new dat= a type which would be larger integers? Then the usages would be independent= and not subject to breaking existing code.=20 Larger integers were added to VHDL-2019 Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:59 2024 X-Received: by 2002:a05:620a:140d:: with SMTP id d13mr7390225qkj.330.1601552632909; Thu, 01 Oct 2020 04:43:52 -0700 (PDT) X-Received: by 2002:a25:b122:: with SMTP id g34mr9709066ybj.196.1601552632597; Thu, 01 Oct 2020 04:43:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2020 04:43:52 -0700 (PDT) In-Reply-To: <5b5f1647-4e27-4b1b-85d5-e9c72e6ad49fn@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: <5b5f1647-4e27-4b1b-85d5-e9c72e6ad49fn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <62310fda-d61b-45e1-b09e-796dab3b46d0n@googlegroups.com> Subject: Re: 64 Bit Integers From: KJ Injection-Date: Thu, 01 Oct 2020 11:43:52 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 14 Xref: reader02.eternal-september.org comp.lang.vhdl:9773 On Thursday, October 1, 2020 at 6:39:42 AM UTC-4, KJ wrote: > On Tuesday, September 29, 2020 at 12:03:42 PM UTC-4, gnuarm.del...@gmail.= com wrote:=20 > > I know the standard requires 32 bit signed integer range, but does not = restrict vendors from supplying larger ranges. However extending the range = of "integer" may break existing code. Is there any consideration to a new d= ata type which would be larger integers? Then the usages would be independe= nt and not subject to breaking existing code. > Larger integers were added to VHDL-2019=20 Specifically, VHDL-2019 defines... The range of INTEGER is implementation dependent and shall include the rang= e =E2=80=93(2^63) to (2^63)=E2=80=931 inclusive. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:45:59 2024 X-Received: by 2002:aed:2e05:: with SMTP id j5mr7867126qtd.94.1601564523321; Thu, 01 Oct 2020 08:02:03 -0700 (PDT) X-Received: by 2002:a05:6902:4ae:: with SMTP id r14mr10958659ybs.22.1601564523165; Thu, 01 Oct 2020 08:02:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2020 08:02:02 -0700 (PDT) In-Reply-To: <62310fda-d61b-45e1-b09e-796dab3b46d0n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <5b5f1647-4e27-4b1b-85d5-e9c72e6ad49fn@googlegroups.com> <62310fda-d61b-45e1-b09e-796dab3b46d0n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <550ca176-48ef-44b5-a053-1579e82ad283o@googlegroups.com> Subject: Re: 64 Bit Integers From: Rick C Injection-Date: Thu, 01 Oct 2020 15:02:03 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9774 On Thursday, October 1, 2020 at 7:43:55 AM UTC-4, KJ wrote: > On Thursday, October 1, 2020 at 6:39:42 AM UTC-4, KJ wrote: > > On Tuesday, September 29, 2020 at 12:03:42 PM UTC-4, gnuarm.del...@gmai= l.com wrote:=20 > > > I know the standard requires 32 bit signed integer range, but does no= t restrict vendors from supplying larger ranges. However extending the rang= e of "integer" may break existing code. Is there any consideration to a new= data type which would be larger integers? Then the usages would be indepen= dent and not subject to breaking existing code. > > Larger integers were added to VHDL-2019=20 >=20 > Specifically, VHDL-2019 defines... > The range of INTEGER is implementation dependent and shall include the ra= nge =E2=80=93(2^63) to (2^63)=E2=80=931 inclusive. >=20 > Kevin Jennings Ok, that's great. Now we just need to wait for the various vendors to embr= ace the new standard. =20 Thanks, I'm not sure how I was not aware this standard had been approved. = I'm sure it was mentioned here. I see in searches it covers some new aspec= ts of interfaces. I should read up on that to see if it is useful for me.= =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:45:59 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.mb-net.net!open-news-network.org!news.bgeserver.de!bgepartei.de!news2.open-news-network.org!.POSTED.109.180.43.176!not-for-mail From: Mike Perkins Newsgroups: comp.lang.vhdl Subject: Re: VHDL Don't Care Date: Sat, 3 Oct 2020 13:17:56 +0100 Organization: news2.open-news-network.org Message-ID: References: <31021fd3-4e2e-41d5-9bf5-d6ae2e05d940o@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 3 Oct 2020 12:17:58 -0000 (UTC) Injection-Info: news2.open-news-network.org; posting-host="109.180.43.176"; logging-data="4738"; mail-complaints-to="abuse@bgeserver.de" User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 In-Reply-To: <31021fd3-4e2e-41d5-9bf5-d6ae2e05d940o@googlegroups.com> Content-Language: en-GB Xref: reader02.eternal-september.org comp.lang.vhdl:9775 On 01/10/2020 10:19:27, Rick C wrote: > I have a clumsy section of code that is simply complex combinational with no good way around it. There are 14 inputs compared to several vectors, reduced to a single bit to control a few nested IF statements. In each IF statement there are WITH statements with six selections to assign values to a signal. This is all encapsulated in a function. > > In most of the WITH statements there is one selection that is a don't care since it won't be used. I'm wondering if VHDL has any way to make use of the don't care to optimize the decoding logic which I expect to be rather large. > > In two of the IF branches a similar issue arises in that the selection signal of the WITH is actually irrelevant since none of the cases other than one will be used. I can leave out the WITH, but I'm not sure that would produce more simple logic than if the selection signal were used with a don't care. > > So other than trying synthesis with the code written with don't cares, how can I know if this will help or even work at all? The only info I can find on VHDL don't cares relates to specific language features like std_match() or case? > > Using case? in place of with doesn't actually help since the optimization is not about the selection value. But that does make me realize I am only using six of eight possible values of the selection value. That signal is an integer range 0 to 5, but that will still be implemented as a 3 bit signal in the logic. So there are two possible inputs not specified. Will that create a latch in the combinational logic or will the range specification prevent that??? I suppose an others clause will help with that, but it still would be better with an assignment of a don't care. > > Maybe it would be good to show some code. > > subtype Alarm_Type is unsigned (Alarm_Sel_Max downto Tidal_Vol_Sel); > subtype Tone_Seq is natural range 0 to 5; > > > function Alarm_Tones (Sequence_Num : Tone_Seq; > Alarm_Src : Alarm_Type) return natural is > variable ret_val : natural range 0 to Step_Max := 0; > begin > if (Alarm_Src(Tick_Sel) then > ret_val := twokHz_step; -- Sequence_Num always = 0 > elsif (Alarm_Src(Boop_Sel)) then > ret_val := G3_step; -- Sequence_Num always = 0 > elsif (OR (Alarm_Src AND VentTones)) then > with Sequence_Num select ret_val := > C4_step when 0, > A4_step when 1, > F4_step when 2, > (others => '-') when 3, -- tone 3 is a gap tone > A4_step when 4, > F4_step when 5; > elsif (OR (Alarm_Src AND OxygenTones)) then > with Sequence_Num select ret_val := > C5_step when 0, > B4_step when 1, > > and so forth for many lines... > > The case of "when 3" above will recur in every subsequent ELSIF. So in the end, the explicit case of Sequence_Num = 3 as well as the unreachable cases of Sequence_Num = 6 and 7 can be optimized as the tool sees fit. This may end up being a rather complex bit of logic so I think it does need attention for optimization. > > I have not yet installed the Gowin tools. Maybe I need to do that and try some cases. The synthesis docs don't talk about this at all. Could you concatenate the signals into a composite signal and then use a case statement. That might be neater? Not sure if 'don't care' works with all synthesis packages -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk From newsfish@newsfish Thu Aug 1 00:46:00 2024 X-Received: by 2002:ac8:6f49:: with SMTP id n9mr7132053qtv.143.1601737564249; Sat, 03 Oct 2020 08:06:04 -0700 (PDT) X-Received: by 2002:a25:d8d5:: with SMTP id p204mr9079390ybg.507.1601737563985; Sat, 03 Oct 2020 08:06:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Oct 2020 08:06:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <31021fd3-4e2e-41d5-9bf5-d6ae2e05d940o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66a9fafe-2e72-4795-bc2e-7706dbc81c28o@googlegroups.com> Subject: Re: VHDL Don't Care From: Rick C Injection-Date: Sat, 03 Oct 2020 15:06:04 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9776 On Saturday, October 3, 2020 at 8:18:02 AM UTC-4, Mike Perkins wrote: > On 01/10/2020 10:19:27, Rick C wrote: > > I have a clumsy section of code that is simply complex combinational wi= th no good way around it. There are 14 inputs compared to several vectors,= reduced to a single bit to control a few nested IF statements. In each IF= statement there are WITH statements with six selections to assign values t= o a signal. This is all encapsulated in a function. > >=20 > > In most of the WITH statements there is one selection that is a don't c= are since it won't be used. I'm wondering if VHDL has any way to make use = of the don't care to optimize the decoding logic which I expect to be rathe= r large. > >=20 > > In two of the IF branches a similar issue arises in that the selection = signal of the WITH is actually irrelevant since none of the cases other tha= n one will be used. I can leave out the WITH, but I'm not sure that would = produce more simple logic than if the selection signal were used with a don= 't care. > >=20 > > So other than trying synthesis with the code written with don't cares, = how can I know if this will help or even work at all? The only info I can = find on VHDL don't cares relates to specific language features like std_mat= ch() or case? > >=20 > > Using case? in place of with doesn't actually help since the optimizati= on is not about the selection value. But that does make me realize I am on= ly using six of eight possible values of the selection value. That signal = is an integer range 0 to 5, but that will still be implemented as a 3 bit s= ignal in the logic. So there are two possible inputs not specified. Will = that create a latch in the combinational logic or will the range specificat= ion prevent that??? I suppose an others clause will help with that, but it= still would be better with an assignment of a don't care. > >=20 > > Maybe it would be good to show some code. > >=20 > > subtype Alarm_Type is unsigned (Alarm_Sel_Max downto Tidal_Vol_Sel); > > subtype Tone_Seq is natural range 0 to 5; > >=20 > >=20 > > function Alarm_Tones (Sequence_Num : Tone_Seq; > > Alarm_Src : Alarm_Type) return natural is > > variable ret_val : natural range 0 to Step_Max :=3D 0; > > begin > > if (Alarm_Src(Tick_Sel) then > > ret_val :=3D twokHz_step; -- Sequence_Num always =3D 0 > > elsif (Alarm_Src(Boop_Sel)) then > > ret_val :=3D G3_step; -- Sequence_Num always =3D 0 > > elsif (OR (Alarm_Src AND VentTones)) then > > with Sequence_Num select ret_val :=3D > > C4_step when 0, > > A4_step when 1, > > F4_step when 2, > > (others =3D> '-') when 3, -- tone 3 is a gap tone > > A4_step when 4, > > F4_step when 5; > > elsif (OR (Alarm_Src AND OxygenTones)) then > > with Sequence_Num select ret_val :=3D > > C5_step when 0, > > B4_step when 1, > >=20 > > and so forth for many lines... > >=20 > > The case of "when 3" above will recur in every subsequent ELSIF. So in= the end, the explicit case of Sequence_Num =3D 3 as well as the unreachabl= e cases of Sequence_Num =3D 6 and 7 can be optimized as the tool sees fit. = This may end up being a rather complex bit of logic so I think it does nee= d attention for optimization. > >=20 > > I have not yet installed the Gowin tools. Maybe I need to do that and = try some cases. The synthesis docs don't talk about this at all. >=20 > Could you concatenate the signals into a composite signal and then use a= =20 > case statement. That might be neater? Not sure if 'don't care' works=20 > with all synthesis packages The structure is not the issue. The don't care you are referring to would = be associated with bits in the selection specification for each case and wo= uld actually apply to the case? statement. No?=20 I'm trying to find info on whether assignment to a don't care value is indi= cated in the VHDL spec as well as which tools support it. While there is a= lot of info on VHDL-2018 supporting don't care in conditionals, not so muc= h on assigning don't care to signals and variables.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:00 2024 X-Received: by 2002:a0c:a085:: with SMTP id c5mr8006051qva.30.1601755832844; Sat, 03 Oct 2020 13:10:32 -0700 (PDT) X-Received: by 2002:a5b:ad1:: with SMTP id a17mr9379968ybr.488.1601755832561; Sat, 03 Oct 2020 13:10:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Oct 2020 13:10:32 -0700 (PDT) In-Reply-To: <66a9fafe-2e72-4795-bc2e-7706dbc81c28o@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:9c57:bd6a:5ede:793a; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:9c57:bd6a:5ede:793a References: <31021fd3-4e2e-41d5-9bf5-d6ae2e05d940o@googlegroups.com> <66a9fafe-2e72-4795-bc2e-7706dbc81c28o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <34011183-f393-4008-b85e-621edaadcc4en@googlegroups.com> Subject: Re: VHDL Don't Care From: KJ Injection-Date: Sat, 03 Oct 2020 20:10:32 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 24 Xref: reader02.eternal-september.org comp.lang.vhdl:9777 On Saturday, October 3, 2020 at 11:06:06 AM UTC-4, gnuarm.del...@gmail.com = wrote: > On Saturday, October 3, 2020 at 8:18:02 AM UTC-4, Mike Perkins wrote:=20 > I'm trying to find info on whether assignment to a don't care value is in= dicated in the VHDL spec as well as which tools support it. Don't care is not a VHDL spec thing. Don't care is part of the std_logic_1= 164 package. Your example code is not valid because ret_val is defined as = a natural, not a std_logic_vector so the assignment of "(others =3D> '-') w= hen 3" to ret_val is invalid. You can work around this by defining ret_val= as type unsigned in which case the "(others =3D> '-') when 3" will work, b= ut all of your other definitions such as 'C4_step' will have to change to u= nsigned as well. To your question about what happens when synthesis encounters such an assig= nment, the answer I believe will be tool specific. If I recall correctly, = when Quartus comes across an assignment such as "x <=3D '-';" it will issue= a warning that it is converting a metavalue (the '-') to '0'. I could be = wrong, but I don't think it will do any analysis to say, would it be better= to assign '1', '0' or just leave 'x' unchanged. This is probably the anal= ysis that you would like it to do. Maybe search for "metavalue assignment"= or "assigning a metavalue to a signal" or some such thing with your synthe= sis tool to see if it says what it does. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:00 2024 X-Received: by 2002:a05:620a:7f6:: with SMTP id k22mr12993513qkk.337.1601879740446; Sun, 04 Oct 2020 23:35:40 -0700 (PDT) X-Received: by 2002:a05:6902:50e:: with SMTP id x14mr16871387ybs.273.1601879740226; Sun, 04 Oct 2020 23:35:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Oct 2020 23:35:39 -0700 (PDT) In-Reply-To: <8vd33f$q9q$1@nnrp1.deja.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=134.102.8.235; posting-account=11lgEgkAAADAed_CCxAF76lgYpLanCLj NNTP-Posting-Host: 134.102.8.235 References: <8ts39q$cth$1@nslave2.tin.it> <3a1a055f.7833118@news.micron.net> <8vd33f$q9q$1@nnrp1.deja.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0df7c0b5-2175-435b-9aa5-12b1e98c25dcn@googlegroups.com> Subject: Re: VHDL compiler and simulator for student From: rezaul karim Injection-Date: Mon, 05 Oct 2020 06:35:40 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9778 On Tuesday, November 21, 2000 at 7:01:21 AM UTC+1, Srinivasan Venkataramanan wrote: > Hi, > In article <3a1a055f...@news.micron.net>, > nospam_...@hotmail.com (Ed Davis) wrote: > > I am also a student have have found this free tool great for doing > > VHDL homework. > > > > http://www.symphonyeda.com/ > > > > It has no GUI or debugger, but hey, its free. I love it. > > > A free simple GUI for VHDLSimli is available at > http://www.symphonyeda.com/contribs.htm#Simtool > I haven't used this (as I prefer command line mode) although. > Cheers, > Srini > > > -- > Srinivasan Venkataramanan > ASIC Design Engineer > Chennai, India > > Sent via Deja.com http://www.deja.com/ > Before you buy. Hello good morning I would like to get HDL simulator for free of cost. could anybody suggest me , how can get that simulator? Regards Md Karim From newsfish@newsfish Thu Aug 1 00:46:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!buffer1.nntp.ams1.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 05 Oct 2020 03:13:44 -0500 Reply-To: mk@mkesc.co.uk Subject: Re: VHDL compiler and simulator for student Newsgroups: comp.lang.vhdl References: <8ts39q$cth$1@nslave2.tin.it> <3a1a055f.7833118@news.micron.net> <8vd33f$q9q$1@nnrp1.deja.com> <0df7c0b5-2175-435b-9aa5-12b1e98c25dcn@googlegroups.com> From: Michael Kellett Date: Mon, 5 Oct 2020 09:13:42 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: <0df7c0b5-2175-435b-9aa5-12b1e98c25dcn@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Message-ID: Lines: 38 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-miyEzspRThN7C9CbMg1pTWqY7W2+a175BdvGozi4Ukqxz3l3K2+LyEOmX9hexCG5gWBv9EuM6WABlfA!8lTm6kOnlkADNxkU75/qjPTZPJlT5SHL19gTSU85lqYPpiwIsEvkxZzu187PZgqNI5T7nAFj3o+p X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2516 Xref: reader02.eternal-september.org comp.lang.vhdl:9779 On 05/10/2020 07:35, rezaul karim wrote: > On Tuesday, November 21, 2000 at 7:01:21 AM UTC+1, Srinivasan Venkataramanan wrote: >> Hi, >> In article <3a1a055f...@news.micron.net>, >> nospam_...@hotmail.com (Ed Davis) wrote: >>> I am also a student have have found this free tool great for doing >>> VHDL homework. >>> >>> http://www.symphonyeda.com/ >>> >>> It has no GUI or debugger, but hey, its free. I love it. >>> >> A free simple GUI for VHDLSimli is available at >> http://www.symphonyeda.com/contribs.htm#Simtool >> I haven't used this (as I prefer command line mode) although. >> Cheers, >> Srini >>> >> -- >> Srinivasan Venkataramanan >> ASIC Design Engineer >> Chennai, India >> >> Sent via Deja.com http://www.deja.com/ >> Before you buy. > Hello good morning > I would like to get HDL simulator for free of cost. > could anybody suggest me , how can get that simulator? > Regards > Md Karim > That original post is 20 years old! You can download free design tools suites from Intel/Altera, Xilinx, Lattice and Microchip. They all include simulators, for VHDL and Verilog. For basic work they would all be OK. MK From newsfish@newsfish Thu Aug 1 00:46:01 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: VHDL compiler and simulator for student Date: Mon, 5 Oct 2020 23:44:43 -0500 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <8ts39q$cth$1@nslave2.tin.it> <3a1a055f.7833118@news.micron.net> <8vd33f$q9q$1@nnrp1.deja.com> <0df7c0b5-2175-435b-9aa5-12b1e98c25dcn@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 6 Oct 2020 04:44:46 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="6760731831590f5d38dde0a78b84354d"; logging-data="21464"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18kmxNGQonpt+eap1Mef6Srz0kCdcgTRwI=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:55wxVUsTvp1DCN9qyBxT3ga1rO8= In-Reply-To: Xref: reader02.eternal-september.org comp.lang.vhdl:9780 On 2020-10-05 03:13, Michael Kellett wrote: > On 05/10/2020 07:35, rezaul karim wrote: >> Hello good morning >> I would like to get HDL simulator for free of cost. >> could anybody suggest me , how can get that simulator? >> Regards >> Md Karim >> > That original post is 20 years old! > > You can download free design tools suites from Intel/Altera, Xilinx, > Lattice and Microchip. They all include simulators, for VHDL and > Verilog. For basic work they would all be OK. > > MK There is also ghdl (http://ghdl.free.fr/), which is completely free. I have found it to be surprisingly capable. There is no gui, it's batch mode only, but I have simulated some fairly large designs with it and its support of the VHDL language is surprisingly good. Charles Bailey From newsfish@newsfish Thu Aug 1 00:46:01 2024 X-Received: by 2002:a37:5144:: with SMTP id f65mr2280055qkb.351.1602822774055; Thu, 15 Oct 2020 21:32:54 -0700 (PDT) X-Received: by 2002:a05:6902:4c5:: with SMTP id v5mr2687097ybs.106.1602822773835; Thu, 15 Oct 2020 21:32:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Oct 2020 21:32:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Time From: Rick C Injection-Date: Fri, 16 Oct 2020 04:32:54 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9781 I'm writing a test bench where there are a series of actions in the Unit Un= der Test (UUT). There should be a pause at which time I'd like the test be= nch to write out the result of the actions. I'm not sure how to detect thi= s lull. I'm thinking of having each action (think bus transactions) update= a signal with the present time. A concurrent statement would use this var= iable plus a constant offset to activate and trigger a process. =20 trig <=3D '1' when now =3D (last_command + 5 ms) else '0';=20 process (trig) is ... Or I suppose I could use a process with a wait statement=20 process is=20 wait until now =3D (last_command + 5 ms);=20 ... I haven't tested either of these but I think they will both work.=20 Any other ideas? =20 Can an assert statement be used for this??? =20 assert not (now =3D (last_command + 5 ms)) report...=20 Ultimately the report is the useful part, but I haven't thought about the d= etails and there might be more to do than what a single report can handle.= =20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:02 2024 X-Received: by 2002:ad4:42c6:: with SMTP id f6mr7081792qvr.21.1602908180173; Fri, 16 Oct 2020 21:16:20 -0700 (PDT) X-Received: by 2002:a5b:70b:: with SMTP id g11mr8763594ybq.323.1602908180000; Fri, 16 Oct 2020 21:16:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2020 21:16:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Aggregates on the Left Side of the Assignment From: Rick C Injection-Date: Sat, 17 Oct 2020 04:16:20 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9782 I can't figure out what is wrong with this left side aggregate. The right = side is clearly defined. The left side is a std_logic combined with an uns= igned which is not inappropriate as far as I can tell. Synplify and Active= HDL both compile it ok, but ActiveHDL gives a run time error...=20 # RUNTIME: Fatal Error: RUNTIME_0046 VHDL_test.vhd (27): Incompatible range= s; left: (0 to 3), right: (0 downto 0). signal count, nxt_cnt : unsigned(2 downto 0) :=3D (others =3D> '0'); signal Test_Out_v : std_logic :=3D '0'; begin Clk_gen: Clk <=3D not Clk after Clock_Half_Period; (Carry_Out, nxt_cnt) <=3D RESIZE(count, nxt_cnt'length + 1) - 1; Pointing to the above line. It doesn't point to any part of the line.=20 I'm stumped on this one.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:02 2024 X-Received: by 2002:a37:6688:: with SMTP id a130mr728904qkc.219.1603199970156; Tue, 20 Oct 2020 06:19:30 -0700 (PDT) X-Received: by 2002:a25:5709:: with SMTP id l9mr3716956ybb.488.1603199969831; Tue, 20 Oct 2020 06:19:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2020 06:19:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <69db9585-8e99-4873-a703-42957854e2d4n@googlegroups.com> Subject: Re: Aggregates on the Left Side of the Assignment From: KJ Injection-Date: Tue, 20 Oct 2020 13:19:30 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 18 Xref: reader02.eternal-september.org comp.lang.vhdl:9783 On Saturday, October 17, 2020 at 12:16:22 AM UTC-4, gnuarm.del...@gmail.com= wrote: > I can't figure out what is wrong with this left side aggregate. The right= side is clearly defined. The left side is a std_logic combined with an uns= igned which is not inappropriate as far as I can tell. Synplify and ActiveH= DL both compile it ok, but ActiveHDL gives a run time error...=20 >=20 > # RUNTIME: Fatal Error: RUNTIME_0046 VHDL_test.vhd (27): Incompatible ran= ges; left: (0 to 3), right: (0 downto 0).=20 >=20 >=20 > I'm stumped on this one.=20 >=20 Try using Modelsim (it works using the code you posted in comp.arch.fpga al= ong with the change you noted in this post) or GHDL (I didn't try it). Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:02 2024 X-Received: by 2002:a05:620a:851:: with SMTP id u17mr2957460qku.344.1603204407762; Tue, 20 Oct 2020 07:33:27 -0700 (PDT) X-Received: by 2002:a25:8752:: with SMTP id e18mr4292805ybn.133.1603204407503; Tue, 20 Oct 2020 07:33:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2020 07:33:27 -0700 (PDT) In-Reply-To: <69db9585-8e99-4873-a703-42957854e2d4n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <69db9585-8e99-4873-a703-42957854e2d4n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Aggregates on the Left Side of the Assignment From: Rick C Injection-Date: Tue, 20 Oct 2020 14:33:27 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 36 X-Received-Bytes: 3123 X-Received-Body-CRC: 609018950 Xref: reader02.eternal-september.org comp.lang.vhdl:9784 On Tuesday, October 20, 2020 at 9:19:34 AM UTC-4, KJ wrote: > On Saturday, October 17, 2020 at 12:16:22 AM UTC-4, gnuarm.del...@gmail.c= om wrote: > > I can't figure out what is wrong with this left side aggregate. The rig= ht side is clearly defined. The left side is a std_logic combined with an u= nsigned which is not inappropriate as far as I can tell. Synplify and Activ= eHDL both compile it ok, but ActiveHDL gives a run time error...=20 > >=20 > > # RUNTIME: Fatal Error: RUNTIME_0046 VHDL_test.vhd (27): Incompatible r= anges; left: (0 to 3), right: (0 downto 0).=20 > >=20 > > >=20 > > I'm stumped on this one.=20 > >=20 >=20 > Try using Modelsim (it works using the code you posted in comp.arch.fpga = along with the change you noted in this post) or GHDL (I didn't try it). Changing literally any part of this assignment allows it to work. Obviousl= y getting rid of the left side aggregate allows it work. Changing the RESI= ZE to a simple concatenation allows it to work ("0" & count). Changing the= integer 1 to an unsigned constant (in spite of the name) allows it to work= . I have no doubt it is an Active-HDL bug at this point. =20 Now my problem is how to let Aldec know the bug exists. Neither Aldec nor = Lattice has a mechanism to report bugs if you aren't currently under a main= tenance plan. Lattice doesn't even have forums any longer. They used to h= ave people scan the forums once in a while. Dropping the forums cuts off a= ll means of unpaid support. I haven't found anything at Aldec either.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:03 2024 X-Received: by 2002:ac8:705b:: with SMTP id y27mr3728699qtm.192.1603397328730; Thu, 22 Oct 2020 13:08:48 -0700 (PDT) X-Received: by 2002:a25:dfd4:: with SMTP id w203mr5449205ybg.215.1603397328474; Thu, 22 Oct 2020 13:08:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Oct 2020 13:08:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=50.38.36.249; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.38.36.249 References: <69db9585-8e99-4873-a703-42957854e2d4n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <84117b8c-c0ce-43a0-9e0b-0cf51a31cb1an@googlegroups.com> Subject: Re: Aggregates on the Left Side of the Assignment From: Jim Lewis Injection-Date: Thu, 22 Oct 2020 20:08:48 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1401 X-Received-Body-CRC: 3526856714 Xref: reader02.eternal-september.org comp.lang.vhdl:9785 Can you post a minimum example that can be pasted into a file and independently tested? From newsfish@newsfish Thu Aug 1 00:46:03 2024 X-Received: by 2002:ae9:eb0e:: with SMTP id b14mr3140643qkg.39.1603401446189; Thu, 22 Oct 2020 14:17:26 -0700 (PDT) X-Received: by 2002:a25:578a:: with SMTP id l132mr5705297ybb.200.1603401446003; Thu, 22 Oct 2020 14:17:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Oct 2020 14:17:25 -0700 (PDT) In-Reply-To: <84117b8c-c0ce-43a0-9e0b-0cf51a31cb1an@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <69db9585-8e99-4873-a703-42957854e2d4n@googlegroups.com> <84117b8c-c0ce-43a0-9e0b-0cf51a31cb1an@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Aggregates on the Left Side of the Assignment From: Rick C Injection-Date: Thu, 22 Oct 2020 21:17:26 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9786 On Thursday, October 22, 2020 at 4:08:51 PM UTC-4, Jim Lewis wrote: > Can you post a minimum example that can be pasted into a file and independently tested? Sure, this has been hashed out in stackexchange to the point I'm pretty convinced it is a simulator bug. It works on Modelsim and ghdl or if very minor changes are made to the code as noted in the comments. I use 4 space tabs. Google shouldn't wrap the lines but your reader might. It will be interesting to find that it is my code and not a bug. -- Test synthesis of counters and carry out flags library ieee; use ieee.NUMERIC_STD.all; use ieee.std_logic_1164.all; -- use work.Common.all; entity VHDL_test is generic( CLK_HZ : REAL := 33.554432E6 ); port( -- Clk : in std_logic := '1'; Cnt_En : in std_logic := '1'; Test_Out_a : out std_logic; Carry_Out_a : out std_logic ); end VHDL_test; architecture TB_ARCH of VHDL_test is constant Clock_Half_Period : time := 500 ms / CLK_HZ; -- 14901 ps; constant Cntr_Width : positive := 8; constant Cntr_Modulus : positive := 2**Cntr_Width; constant One_uns : unsigned(Cntr_Width downto 0) := "000000001"; signal Clk : std_logic := '1'; signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others => '0'); begin Clk_gen: Clk <= not Clk after Clock_Half_Period; -- comment out for synth (Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a'length + 1) - 1; -- fails -- (Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a'length + 1) - One_uns; -- works -- (Carry_Out_a, nxt_cnt_a) <= ("0" & Count_a) - 1; -- works test_ag: process (Clk) is begin if rising_edge(Clk) then Test_Out_a <= Carry_Out_a; if (Cnt_En OR not Carry_Out_a) then Count_a <= nxt_cnt_a; end if; end if; end process test_ag; end TB_ARCH; -- VHDL_test -- Rick C. -- Get 1,500 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:03 2024 X-Received: by 2002:a05:620a:b0b:: with SMTP id t11mr8804782qkg.369.1603559126979; Sat, 24 Oct 2020 10:05:26 -0700 (PDT) X-Received: by 2002:a25:5c85:: with SMTP id q127mr10974587ybb.413.1603559126817; Sat, 24 Oct 2020 10:05:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 24 Oct 2020 10:05:26 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=86.169.3.243; posting-account=V1jZlgoAAACuMOVJko6cBV0aO1ISWIGy NNTP-Posting-Host: 86.169.3.243 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <18825139-ef25-4400-b53d-f7333b2645b2n@googlegroups.com> Subject: Implementing entity from a different library From: Andrey Kapustin Injection-Date: Sat, 24 Oct 2020 17:05:26 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9787 I have a VHDL library "core" that declares entity "IBusUnit". In a different VHDL design I say "library core; use core.IBusUnit; architecture RamUnit of IBusUnit is ..." - but the VHDL compiler complains "Cannot find referenced entity declaration "IBusUnit"". Could someone tell me what I am doing wrong here? Thanks in advance, Andrey From newsfish@newsfish Thu Aug 1 00:46:04 2024 X-Received: by 2002:ac8:16d8:: with SMTP id y24mr12086425qtk.283.1603620451436; Sun, 25 Oct 2020 03:07:31 -0700 (PDT) X-Received: by 2002:a25:e6d7:: with SMTP id d206mr14132794ybh.144.1603620451276; Sun, 25 Oct 2020 03:07:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 25 Oct 2020 03:07:31 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: integer_vector From: Rick C Injection-Date: Sun, 25 Oct 2020 10:07:31 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9788 Looking for a good way to support initialized block rams in my design I fou= nd that VHDL-2008 includes some new predefined array types such as integer_= vector, an array of integers.=20 Integers are either 32 or even 64 bits, so that would be a rather wide memo= ry. Is there a way to restrict the range of the integer of such an array? = =20 I'd like to have a single file for the definition of a block ram because it= will require a synthesis attribute which likely won't port well. So rathe= r than scatter this issue around the design, a single module seems like a g= ood idea. The memory module also needs to support initialization. Not sur= e of the best way to support that. I'm thinking a constant array passed in= through a generic. =20 I'm still fuzzy on the details of how to make this all work together. I gu= ess I could have a file with the constant array definition. Then the appli= cation code can instantiate the memory array with the constant initializati= on array as a generic. =20 I've always heard that memory is best written as an array of integers for s= imulation efficiency. But that requires limiting the range of the integer.= If the integer_vector type is used it would seem the word size is fixed a= t whatever the synthesis vendor provides in their defaults. Or is there a = way to restrict the range of the integers without a special type for each w= idth?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:04 2024 X-Received: by 2002:a37:a896:: with SMTP id r144mr2150245qke.11.1603804285371; Tue, 27 Oct 2020 06:11:25 -0700 (PDT) X-Received: by 2002:a25:6fc4:: with SMTP id k187mr3216252ybc.195.1603804285076; Tue, 27 Oct 2020 06:11:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Oct 2020 06:11:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1e566c68-342f-49d0-a81b-aabb19fd5272n@googlegroups.com> Subject: Re: integer_vector From: KJ Injection-Date: Tue, 27 Oct 2020 13:11:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9789 On Sunday, October 25, 2020 at 6:07:33 AM UTC-4, gnuarm.del...@gmail.com wr= ote: > Looking for a good way to support initialized block rams in my design I f= ound that VHDL-2008 includes some new predefined array types such as intege= r_vector, an array of integers.=20 >=20 > Integers are either 32 or even 64 bits, so that would be a rather wide me= mory. Is there a way to restrict the range of the integer of such an array?= =20 >=20 Use a subtype. Example subtype MyInteger is natural range 0 to 255. You c= an then define MyIntegerVector to be an array of MyInteger. > I'd like to have a single file for the definition of a block ram because = it will require a synthesis attribute which likely won't port well. So rath= er than scatter this issue around the design, a single module seems like a = good idea. The memory module also needs to support initialization. Not sure= of the best way to support that. I'm thinking a constant array passed in t= hrough a generic.=20 Yes, passing the integer array in as a generic will work. >=20 > I'm still fuzzy on the details of how to make this all work together. I g= uess I could have a file with the constant array definition. Then the appli= cation code can instantiate the memory array with the constant initializati= on array as a generic.=20 >=20 > I've always heard that memory is best written as an array of integers for= simulation efficiency. But that requires limiting the range of the integer= . If the integer_vector type is used it would seem the word size is fixed a= t whatever the synthesis vendor provides in their defaults. Or is there a w= ay to restrict the range of the integers without a special type for each wi= dth?=20 >=20 As I mentioned you can use an integer subtype to limit the range of the int= egers. However, another way is to use integer and then limit the range whe= n you go to fit it into the actual memory which likely has a std_logic_vect= or interface to it. That means you will limit the range when you convert t= he integer to an unsigned when you tell it the number of bits. The 'best' = approach will depend on exactly what your memory block interface looks like= but here are a couple of considerations: - If you use a subtype but you accidentally include a number that is out of= range such as 256 for subtype MyInteger then the compiler will flag an err= or. - If you use std_logic_vector(to_unsigned(...)) to fit it into the memory t= hen the numeric_std library will toss a warning when it tries to convert 25= 6 to an 8 bit value, but convert it to 0. Then you're depending on your ab= ility to notice the warning to find the design error. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:04 2024 X-Received: by 2002:aed:3809:: with SMTP id j9mr2714130qte.197.1603814278952; Tue, 27 Oct 2020 08:57:58 -0700 (PDT) X-Received: by 2002:a25:4946:: with SMTP id w67mr4559291yba.143.1603814278770; Tue, 27 Oct 2020 08:57:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Oct 2020 08:57:58 -0700 (PDT) In-Reply-To: <1e566c68-342f-49d0-a81b-aabb19fd5272n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <1e566c68-342f-49d0-a81b-aabb19fd5272n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: integer_vector From: Rick C Injection-Date: Tue, 27 Oct 2020 15:57:58 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9790 On Tuesday, October 27, 2020 at 9:11:28 AM UTC-4, KJ wrote: > On Sunday, October 25, 2020 at 6:07:33 AM UTC-4, gnuarm.del...@gmail.com = wrote: > > Looking for a good way to support initialized block rams in my design I= found that VHDL-2008 includes some new predefined array types such as inte= ger_vector, an array of integers.=20 > >=20 > > Integers are either 32 or even 64 bits, so that would be a rather wide = memory. Is there a way to restrict the range of the integer of such an arra= y?=20 > >=20 > Use a subtype. Example subtype MyInteger is natural range 0 to 255. You= can then define MyIntegerVector to be an array of MyInteger. >=20 > > I'd like to have a single file for the definition of a block ram becaus= e it will require a synthesis attribute which likely won't port well. So ra= ther than scatter this issue around the design, a single module seems like = a good idea. The memory module also needs to support initialization. Not su= re of the best way to support that. I'm thinking a constant array passed in= through a generic.=20 > Yes, passing the integer array in as a generic will work. >=20 > >=20 > > I'm still fuzzy on the details of how to make this all work together. I= guess I could have a file with the constant array definition. Then the app= lication code can instantiate the memory array with the constant initializa= tion array as a generic.=20 > >=20 > > I've always heard that memory is best written as an array of integers f= or simulation efficiency. But that requires limiting the range of the integ= er. If the integer_vector type is used it would seem the word size is fixed= at whatever the synthesis vendor provides in their defaults. Or is there a= way to restrict the range of the integers without a special type for each = width?=20 > >=20 > As I mentioned you can use an integer subtype to limit the range of the i= ntegers. However, another way is to use integer and then limit the range w= hen you go to fit it into the actual memory which likely has a std_logic_ve= ctor interface to it. That means you will limit the range when you convert= the integer to an unsigned when you tell it the number of bits. =20 Yes, I understand the nature of VHDL. The issue is that if the width of th= e data is specified in the type definition of the memory, the memory code i= s specific to that data width and many modules will be required, one for ea= ch data width, so not the best option.=20 > The 'best' approach will depend on exactly what your memory block interfa= ce looks like but here are a couple of considerations: > - If you use a subtype but you accidentally include a number that is out = of range such as 256 for subtype MyInteger then the compiler will flag an e= rror. I believe the simulator will flag the error at run time. In fact it is a f= atal error and stops the simulation.=20 > - If you use std_logic_vector(to_unsigned(...)) to fit it into the memory= then the numeric_std library will toss a warning when it tries to convert = 256 to an 8 bit value, but convert it to 0. Then you're depending on your = ability to notice the warning to find the design error. The best way I've found is to allow the memory declaration to remain unboun= ded integers. In fact, I use the predefined type integer_vector. The I/O = will be vectors for address and data. Conversions between the vectors and = the memory integers define the word widths in a way that the tools then set= the implemented size of the memory without direct specification of the int= eger range. =20 Once I realized this was already happening in the conversions it was simple= to think of the memory widths through the I/O data width specification gen= eric. =20 So the solution is to do nothing with the integers making up the memory and= let the conversions set the word widths.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:05 2024 X-Received: by 2002:ae9:dcc1:: with SMTP id q184mr948871qkf.436.1604043680743; Fri, 30 Oct 2020 00:41:20 -0700 (PDT) X-Received: by 2002:a5b:70b:: with SMTP id g11mr1669838ybq.323.1604043680548; Fri, 30 Oct 2020 00:41:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!fdn.fr!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Oct 2020 00:41:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Active-HDL issues with another VHDL-2008 construct From: Rick C Injection-Date: Fri, 30 Oct 2020 07:41:20 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9791 CASE? and '-' as a wildcard. It's part of the standard. case? pretty much has one purpose as far as I know, to accept '-' as a wildcard. Yet it rejects my code... :( # KERNEL: Fatal Error: Don't care ('-') value in the matching select/case statement expression. procedure Cmnd_Parse ( Command : in unsigned(8 downto 0); Right_Left : in String; Cmnd_Time : in time ) is begin case? Command is when 9x"000" => assert false report Right_Left & " - NOP with enable detected"; when 9x"001" => assert false report Right_Left & " - Clear Display command"; when 9x"002" => assert false report Right_Left & " - Return Home command"; when b"0000001--" => ... There are a number of matching expressions with the wildcard '-' after this. This has got to be an issue with the simulator, right? I guess I can try a test case that isn't so large, but this will be the second feature I've found that Aldec doesn't support so well. I hate to rip out all this code, but it looks like I'll have to replace it with IF statements and they will work better comparing from the high end down, so the order of comparisons will be opposite ... lots of editing. Fun... -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:05 2024 X-Received: by 2002:a37:c441:: with SMTP id h1mr3636147qkm.298.1604083577285; Fri, 30 Oct 2020 11:46:17 -0700 (PDT) X-Received: by 2002:a25:3c81:: with SMTP id j123mr5642113yba.359.1604083577109; Fri, 30 Oct 2020 11:46:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Oct 2020 11:46:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66f49f1b-5702-494d-9f3a-037288bdac8eo@googlegroups.com> Subject: Re: Active-HDL issues with another VHDL-2008 construct From: Rick C Injection-Date: Fri, 30 Oct 2020 18:46:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 46 Xref: reader02.eternal-september.org comp.lang.vhdl:9792 On Friday, October 30, 2020 at 3:41:22 AM UTC-4, Rick C wrote: > CASE? and '-' as a wildcard. It's part of the standard. case? pretty mu= ch has one purpose as far as I know, to accept '-' as a wildcard. Yet it r= ejects my code... :(=20 >=20 > # KERNEL: Fatal Error: Don't care ('-') value in the matching select/case= statement expression. >=20 > procedure Cmnd_Parse ( > Command : in unsigned(8 downto 0); > Right_Left : in String; > Cmnd_Time : in time ) is > begin > case? Command is > when 9x"000" =3D> > assert false report Right_Left & " - NOP with enable detected"; > when 9x"001" =3D> > assert false report Right_Left & " - Clear Display command"; > when 9x"002" =3D> > assert false report Right_Left & " - Return Home command"; > when b"0000001--" =3D> > ...=20 >=20 > There are a number of matching expressions with the wildcard '-' after th= is. =20 >=20 > This has got to be an issue with the simulator, right? I guess I can try= a test case that isn't so large, but this will be the second feature I've = found that Aldec doesn't support so well.=20 >=20 > I hate to rip out all this code, but it looks like I'll have to replace i= t with IF statements and they will work better comparing from the high end = down, so the order of comparisons will be opposite ... lots of editing. Fu= n...=20 I seem to get a lot of responses to my posts in stackexchange, particularly= from Brian Drummond. He has indicated the problem is not my code, but a n= umber of tools still fail this simple exercise even though they appear to s= upport case? So the wild card '-' is to be avoided when portability of co= de is important even if the code runs with your tools. =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:05 2024 X-Received: by 2002:a37:9d94:: with SMTP id g142mr2487786qke.92.1604282577187; Sun, 01 Nov 2020 18:02:57 -0800 (PST) X-Received: by 2002:a25:d2c5:: with SMTP id j188mr17831635ybg.32.1604282576928; Sun, 01 Nov 2020 18:02:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Nov 2020 18:02:56 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=2804:14c:5ba9:8c8d:0:0:0:1000; posting-account=nc12jQoAAABzIZcjk3v4RZers7IAuxms NNTP-Posting-Host: 2804:14c:5ba9:8c8d:0:0:0:1000 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <19127792-bd3e-4ac6-9fcb-72714481b2fbn@googlegroups.com> Subject: "Missing one or more actuals for elements of formal "a_b"." From: Hugo Souza Injection-Date: Mon, 02 Nov 2020 02:02:57 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9793 Hello! I'm doing homework and i'm meant to produce a 32 bits ULA with a for generate, i've been succesful in doing each separate function it's meant to do, but on the for I get this weird error. COMP96 Compile Architecture "arch_ULA_All" of Entity "ULA_All" ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "a_b"." "ULA_All.vhd" 66 0 ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "b_b"." "ULA_All.vhd" 67 0 ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "Less_b"." "ULA_All.vhd" 68 0 ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "Result_b"." "ULA_All.vhd" 72 0 COMP96 ERROR COMP96_0333: "Formal must be locally static name." "ULA_All.vhd" 76 16 COMP96 ERROR COMP96_0333: "Formal must be locally static name." "ULA_All.vhd" 77 16 COMP96 ERROR COMP96_0333: "Formal must be locally static name." "ULA_All.vhd" 78 16 COMP96 ERROR COMP96_0333: "Formal must be locally static name." "ULA_All.vhd" 81 16 COMP96 ERROR COMP96_0207: "No actual specified for local port "Carryln_b"." "ULA_All.vhd" 75 6 COMP96 ERROR COMP96_0122: "Symbol "ULA_Body_all" has already been declared in this scope." "ULA_All.vhd" 84 4 ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "a_b"." "ULA_All.vhd" 85 0 ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "b_b"." "ULA_All.vhd" 86 0 ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "Less_b"." "ULA_All.vhd" 87 0 ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "CarryOut_b"." "ULA_All.vhd" 91 0 ELBWRITE ERROR ELBWRITE_0018: "Missing one or more actuals for elements of formal "Result_b"." "ULA_All.vhd" 92 0 COMP96 Compile failure 15 Errors 1 Warnings Analysis time : 0.1 [s] Exit code expected: 0, received: 1 Done Code for this --------------------------------------------------------% -- ULA_Body % -- Entradas: a_h, b_h, Less_h, Binvert_h e Carryln_h % -- Saidas: Operation_h, CarryOut_h e Result_h % -- Dependencias: somador_comp, mult4x1 e mult2x1 % --------------------------------------------------------% library ieee; use ieee.std_logic_1164.all; entity ULA_All is port (a, b: in std_logic_vector (31 downto 0); Less: in std_logic; Bnegate: in std_logic; Operation: in std_logic_vector (1 downto 0); Zero, Overflow: out std_logic); end ULA_All; architecture arch_ULA_All of ULA_All is -----------------------------|Componentes|------------------------ component ULA_Head is port (a_h, b_h, Less_h, Binvert_h, Carryln_h: in std_logic; Operation_h: in std_logic_vector (1 downto 0); CarryOut_h, Result_h: out std_logic); end component ULA_Head; component ULA_Body is port (a_b, b_b, Less_b: in std_logic_vector (29 downto 0); Carryln_b, Binvert_b: in std_logic; Operation_b: in std_logic_vector (1 downto 0); CarryOut_b, Result_b: out std_logic_vector (29 downto 0)); end component ULA_Body; component ULA_Footer is port (a_f, b_f, Less_f, Binvert_f, Carryln_f: in std_logic; Operation_f: in std_logic_vector (1 downto 0); Result_f, Set_f, Overflow_s: out std_logic); end component ULA_Footer; ----------------------------------------------------------------- signal resp_all : std_logic_vector (31 downto 0); --Head signal carry_head : std_logic; --signal : std_logic_vector (31 downto 0); --Body signal carry_body : std_logic; --signal : std_logic_vector (31 downto 0); --Footer signal Set_footer : std_logic; --signal : std_logic_vector (31 downto 0); ----------------------------------------------------------------- begin --HEAD ULA_Head_all : ULA_Head port map(a_h => a(0), b_h => b(0), Less_h => Set_footer, Binvert_h => Bnegate, Carryln_h => Bnegate, Operation_h => Operation, CarryOut_h => carry_head, Result_h => resp_all(0)); --END HEAD --BODY ULA_Body_all : ULA_Body port map (a_b(0) => a(1), b_b(0) => b(1), Less_b(0) => Less, Carryln_b => carry_head, Binvert_b => Bnegate, Operation_b => Operation, Result_b(0) => resp_all(1)); ULA_ALL: for i in 1 to 28 generate ULA_Body_all : ULA_Body port map (a_b(i) => a(i+1), b_b(i) => b(i+1), Less_b(i) => Less, Binvert_b => Bnegate, Operation_b => Operation, Result_b(i) => resp_all(i+1)); end generate; ULA_Body_all : ULA_Body port map (a_b(29) => a(30), b_b(29) => b(30), Less_b(29) => Less, Carryln_b => carry_head, Binvert_b => Bnegate, Operation_b => Operation, CarryOut_b(29) => carry_body, Result_b(29) => resp_all(30)); --END BODY --FOOTER ULA_Footer_all : ULA_Footer port map (a_f => a(31), b_f => b(31), Less_f => Less, Binvert_f => Bnegate, Carryln_f => carry_body, Operation_f => Operation, Result_f => resp_all(31), Set_f => Set_footer, Overflow_s => Overflow); --END FOOTER end arch_ULA_All; From newsfish@newsfish Thu Aug 1 00:46:05 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: "Missing one or more actuals for elements of formal "a_b"." Date: Mon, 02 Nov 2020 11:53:35 +0200 Organization: An impatient and LOUD arachnid Lines: 11 Message-ID: References: <19127792-bd3e-4ac6-9fcb-72714481b2fbn@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain Injection-Info: reader02.eternal-september.org; posting-host="39699bfd424d0b0bcb7eca6e0af89e29"; logging-data="16370"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18BBqYte9yGuIQb7gxit0N5" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) Cancel-Lock: sha1:9PEecDmzYc+LWT0oRnpvBBpE0yo= sha1:JPpz7a9QR860TEyHsK1cRz1n8Lc= Xref: reader02.eternal-september.org comp.lang.vhdl:9794 Hugo Souza writes: > Hello! I'm doing homework and i'm meant to produce a 32 bits ULA with a for generate, i've been succesful in doing each separate function it's meant to do, but on the for I get this weird error. >From the code I'd guess your instantiations are not really what you intend. Do you really need 30 instances of this ULA_Body component since that's what you're doing? But hard to say since I have no idea what you're trying to do here? The only ULA I'm familiar with is the ULA chip on old Sinclair Spectrum computers but this looks like an ALU? From newsfish@newsfish Thu Aug 1 00:46:06 2024 X-Received: by 2002:a0c:c18a:: with SMTP id n10mr55273qvh.54.1604541514206; Wed, 04 Nov 2020 17:58:34 -0800 (PST) X-Received: by 2002:a25:bf89:: with SMTP id l9mr604126ybk.22.1604541513796; Wed, 04 Nov 2020 17:58:33 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!aioe.org!peer01.ams4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Nov 2020 17:58:33 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=50.38.36.249; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.38.36.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <25cfdd97-21fa-4438-8d34-d53b8356cf6dn@googlegroups.com> Subject: Re: Active-HDL issues with another VHDL-2008 construct From: Jim Lewis Injection-Date: Thu, 05 Nov 2020 01:58:34 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2149 X-Received-Body-CRC: 856737196 Xref: reader02.eternal-september.org comp.lang.vhdl:9795 Case? does not allow the targets to overlap. To fully access correctness = or not with your code would require the rest of the code. =20 > # KERNEL: Fatal Error: Don't care ('-') value in the matching select/case= statement expression.=20 This seems to imply that during simulation, the "Command" input has a'-' in= it, which is an=20 error in your code. >From 1076-2008: "For a matching case statement in which the expression is of type STD_ULOGI= C, or an array type whose element type is STD_ULOGIC, it is an error if the value of the expression i= s the scalar value '=E2=80=93' or an array value containing '=E2=80=93' as an element." Verilog does not have this sort of a check by the language and it is a disa= ster for them. Run your simulation, single step and observe the value of Command that make= s it stop. That will help you confirm this. =20 Best Regards, Jim From newsfish@newsfish Thu Aug 1 00:46:06 2024 X-Received: by 2002:a37:2753:: with SMTP id n80mr345998qkn.353.1604546742382; Wed, 04 Nov 2020 19:25:42 -0800 (PST) X-Received: by 2002:a5b:70b:: with SMTP id g11mr784733ybq.323.1604546742219; Wed, 04 Nov 2020 19:25:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Nov 2020 19:25:41 -0800 (PST) In-Reply-To: <25cfdd97-21fa-4438-8d34-d53b8356cf6dn@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <25cfdd97-21fa-4438-8d34-d53b8356cf6dn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e039d80-fc28-41ac-811d-52dd73b9ce81o@googlegroups.com> Subject: Re: Active-HDL issues with another VHDL-2008 construct From: Rick C Injection-Date: Thu, 05 Nov 2020 03:25:42 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9796 On Wednesday, November 4, 2020 at 8:58:36 PM UTC-5, Jim Lewis wrote: > Case? does not allow the targets to overlap. To fully access correctnes= s or not > with your code would require the rest of the code. =20 Thanks for your reply. Yeah, the code is gone so I could get something to = work. There was no overlapping. The "commands" are essentially priority e= ncoded or whatever you want to call it as each command is defined by the fi= rst '1' from the left. So commands are "00000001", "0000001-", "000001--",= etc. No overlapping. I ended up reworking it as IF command(7) =3D '1'..= . ELSIF command(6) =3D '1'... ELSIF command(5) =3D '1'... ect. =20 The case? would have been less typing, maybe, but certainly more clear I th= ink. 6 vs. half dozen I guess. Actually, I'm just disappointed that there= are still bugs in VHDL-2008 features after 12 friggin years!=20 > > # KERNEL: Fatal Error: Don't care ('-') value in the matching select/ca= se statement expression.=20 > This seems to imply that during simulation, the "Command" input has a'-' = in it, which is an=20 > error in your code. >=20 > From 1076-2008: > "For a matching case statement in which the expression is of type STD_ULO= GIC, or an array type whose > element type is STD_ULOGIC, it is an error if the value of the expression= is the scalar value '=E2=80=93' or an array > value containing '=E2=80=93' as an element." No, the input expression has no '-' in it. That value comes from some logi= c driven by a state machine. Possibly a 'X' or 'U' would appear at time 0,= but not much chance of a '-' being generated from synthesizable logic. Th= e CASE? is in the test bench code that is checking the commands that are se= nt by the synthesized logic. =20 > Verilog does not have this sort of a check by the language and it is a di= saster for them. >=20 > Run your simulation, single step and observe the value of Command that ma= kes it stop. > That will help you confirm this. =20 I think this error is showing up at time 0, not sure. Actually, probably n= ot. I think there is a wait for a falling edge, so not time zero I guess. = The process would be run, but not this code. I should generate a test case= , but I tried reporting another error to Aldec and got the "talk to your FP= GA vendor, it's their code now" stiff arm and Lattice was polite but has no= t responded following the initial contact.=20 Bottom line is not much point in preparing a test case if they don't want t= o hear about it.=20 When they talk about "expression is of type STD_ULOGIC" I assume they inclu= de any closely related types like std_logic and arrays of same like unsigne= d? VHDL has so many rules it is hard to remember all the rules and terms a= nd just everything. Maybe I need to retire to Florida. =20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:06 2024 X-Received: by 2002:a05:620a:13b9:: with SMTP id m25mr7368982qki.467.1604782097400; Sat, 07 Nov 2020 12:48:17 -0800 (PST) X-Received: by 2002:a25:a481:: with SMTP id g1mr10510822ybi.319.1604782097151; Sat, 07 Nov 2020 12:48:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Nov 2020 12:48:16 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1b27adc3-3378-4da4-a6ec-1a068aa4e113o@googlegroups.com> Subject: Re: "Non-static aggregate with multiple choices has non-static others choice." From: Rick C Injection-Date: Sat, 07 Nov 2020 20:48:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9797 On Saturday, March 23, 2013 at 6:20:27 PM UTC-4, rickman wrote: > This is the code, >=20 > Bias <=3D (Bias(Bias'high-1) =3D> '1', others =3D> '0'); >=20 > This is the error, >=20 > "Non-static aggregate with multiple choices has non-static others choice.= " >=20 > When I looked this up on the web they talk about things like using a=20 > loop index to select the bit in the word. Another page mentions that=20 > the items in an aggregate must be non-overlapping. If they need to be=20 > non-overlapping what is the point of the others? I could have sworn=20 > that I was told using others to fill in the remainder of a vector was ok= =20 > as long as it was last in the aggregate. >=20 > A post from 2003 used a fixed index into the vector, so it seems the=20 > problem is not from the use of Bias'high in the index. >=20 > This kind of thing is what drives people nuts about VHDL. For some of=20 > us it is a short trip. I still run into this problem from time to time. For whatever reason this = is still not an intuitive matter for me. I guess I don't have a clear unde= rstanding of globally and locally static to recognize the issue before I ge= t the error message. =20 Anyway, in my current matter I am trying to set a single bit to '1' in an u= nsigned and the rest '0'. I decided the least annoying way to deal with th= is is two separate assignments.=20 Temp :=3D (others =3D> '0');=20 Temp(Index) :=3D '1';=20 rather than=20 Temp :=3D (Index =3D> '1', others =3D> '0');=20 Index is passed into a procedure while Temp is a variable.=20 procedure Test_Button (signal Button_Action : in unsigned; DelayA : in time; DelayB : in time; Index : integer ) is variable Temp : unsigned (Button_Action'range) :=3D Button_Action;=20 I like to keep my code tight and neat as it helps me with understanding it = when I return to it later. But at some point you have to accept your losse= s and move on. This is not just me working, but a team effort with total s= trangers working together using different tools, so the code needs to work = across platforms. One guy is a total Xilinx freak. So obviously he is usi= ng Vivado or whatever name Xilinx gave their tools.=20 Consider this as a note to self, but comment if you wish. When I search fo= r problems these days I'm as likely to find my own posts on a topic as much= as anything else.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:07 2024 X-Received: by 2002:ac8:70cd:: with SMTP id g13mr10174060qtp.345.1604862924161; Sun, 08 Nov 2020 11:15:24 -0800 (PST) X-Received: by 2002:a25:578a:: with SMTP id l132mr13870781ybb.200.1604862924022; Sun, 08 Nov 2020 11:15:24 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Nov 2020 11:15:23 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <71029c04-cec8-42b1-b733-4e1b7342bc33o@googlegroups.com> Subject: Attribute default From: Rick C Injection-Date: Sun, 08 Nov 2020 19:15:24 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9798 'Last_event is the time of the "last" event on a signal. In my simulation = the signal has not had an event when it is first checked. The value return= ed seems to be a rather large value. I did some searching and didn't find = this anywhere and don't have a copy of the language reference manual. =20 Also, what is the definition of "last"? Is that the previous event or the = current on if the signal has just had an event and no time has elapsed? I'= m talking about a process with the signal as it's trigger. Will 'Last_even= t give the current time or the previous time of change? =20 I'm trying to check setup and hold times. When they are 0, it can be a bit= hard to distinguish.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:07 2024 X-Received: by 2002:ad4:4514:: with SMTP id k20mr22064790qvu.1.1605059935057; Tue, 10 Nov 2020 17:58:55 -0800 (PST) X-Received: by 2002:a25:5ce:: with SMTP id 197mr18182103ybf.53.1605059934759; Tue, 10 Nov 2020 17:58:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 10 Nov 2020 17:58:54 -0800 (PST) In-Reply-To: <71029c04-cec8-42b1-b733-4e1b7342bc33o@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=50.38.36.249; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.38.36.249 References: <71029c04-cec8-42b1-b733-4e1b7342bc33o@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ccd43f5-1b38-42d5-bce5-f4ed40cea1e3n@googlegroups.com> Subject: Re: Attribute default From: Jim Lewis Injection-Date: Wed, 11 Nov 2020 01:58:55 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9799 Did you ask Google? =20 Here is what Google says: S'Last_event: the amount of time since last event occurred on S, if no eve= nt has yet occurred it returns Time'High Here is what the VHDL LRM says: S'LAST_EVENT=20 Kind: Function. Prefix: Any signal denoted by the static signal name S. Result type: Type TIME. Result: The amount of time that has elapsed since the last event occurred o= n signal S. Specifically: For a signal S, S'LAST_EVENT returns the smallest value T of type TIME such= that S'EVENT =3D TRUE during any simulation cycle at time NOW =E2=80=93 T, if su= ch a value exists; otherwise, it returns TIME'HIGH. Hence if 'event is true, then 'last_event =3D 0. =20 You might want to look at the Vital timing library as it has setup and hold= checkers. If you cannot find anything else, I recommend Rick Munden's bo= ok, "ASIC and FPGA Verification" If you truely want to write your own, you might want to read up on 'delayed= and postponed. Although, I prefer to log process run times to instead and= use the function now. From newsfish@newsfish Thu Aug 1 00:46:07 2024 X-Received: by 2002:ad4:5381:: with SMTP id i1mr22869576qvv.21.1605065707258; Tue, 10 Nov 2020 19:35:07 -0800 (PST) X-Received: by 2002:a25:3c81:: with SMTP id j123mr31411749yba.359.1605065707030; Tue, 10 Nov 2020 19:35:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 10 Nov 2020 19:35:06 -0800 (PST) In-Reply-To: <4ccd43f5-1b38-42d5-bce5-f4ed40cea1e3n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <71029c04-cec8-42b1-b733-4e1b7342bc33o@googlegroups.com> <4ccd43f5-1b38-42d5-bce5-f4ed40cea1e3n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3ac97b2b-f443-41eb-8bea-515dc9945217o@googlegroups.com> Subject: Re: Attribute default From: Rick C Injection-Date: Wed, 11 Nov 2020 03:35:07 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9800 On Tuesday, November 10, 2020 at 8:58:57 PM UTC-5, Jim Lewis wrote: > Did you ask Google? =20 > Here is what Google says: > S'Last_event: the amount of time since last event occurred on S, if no e= vent has yet occurred it returns Time'High >=20 > Here is what the VHDL LRM says: > S'LAST_EVENT=20 > Kind: Function. > Prefix: Any signal denoted by the static signal name S. > Result type: Type TIME. > Result: The amount of time that has elapsed since the last event occurred= on > signal S. Specifically: > For a signal S, S'LAST_EVENT returns the smallest value T of type TIME su= ch that > S'EVENT =3D TRUE during any simulation cycle at time NOW =E2=80=93 T, if = such a value exists; > otherwise, it returns TIME'HIGH. >=20 > Hence if 'event is true, then 'last_event =3D 0. =20 >=20 > You might want to look at the Vital timing library as it has setup and ho= ld checkers. If you cannot find anything else, I recommend Rick Munden's = book, "ASIC and FPGA Verification" >=20 > If you truely want to write your own, you might want to read up on 'delay= ed and postponed. Although, I prefer to log process run times to instead a= nd use the function now. Where did you find that on Google? I didn't find anything useful. I did p= ost this to stackexchange.com and got a response a couple of days ago. As = you say, the standard says assigned signals are time'high which makes them = easy to detect. =20 Thanks for the suggestions. I'm about done with this test bench, but I'll = keep Vital in mind for the next one. =20 When it came to the definition of "last" it reminded me of the Seinfeld jok= e about the meaning of "next" Wednesday. "If I had meant THIS Wednesday, I= 've have said THIS Wednesday".=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:08 2024 X-Received: by 2002:a37:652:: with SMTP id 79mr1590415qkg.144.1605267836103; Fri, 13 Nov 2020 03:43:56 -0800 (PST) X-Received: by 2002:a25:5ce:: with SMTP id 197mr2531363ybf.53.1605267835897; Fri, 13 Nov 2020 03:43:55 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Nov 2020 03:43:55 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=62.78.229.57; posting-account=Qvf1hgoAAACDgIUF9_qoviC54R7UhwJW NNTP-Posting-Host: 62.78.229.57 References: <36B0468F.2016173@mentorg.com> <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> <5c61e7a7$0$3533$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: printf() function like C in VHDL ? From: francis cagney Injection-Date: Fri, 13 Nov 2020 11:43:56 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 18 Xref: reader02.eternal-september.org comp.lang.vhdl:9801 Actually I came here because I was wondering about a printf for vhdl. 21 year old thread updated less than 2 years ago. There are 2 printf type implementations https://github.com/xcthulhu/coded_aperture_vhdl c_vhdl library has null terminated strings, regex, stdio, and variable argument printf or sprintf, fprintf. It has not been maintained since 10 years. https://github.com/suoto/hdl_string_format This one was last updated 5 years ago and is limited On Tuesday, 12 February 2019 at 00:00:21 UTC+2, gnuarm.del wrote: > > Do you realize you just replied to a 20 years old thread ? > > > > Nicolas > Some things are timeless.... :) > > Rick C. From newsfish@newsfish Thu Aug 1 00:46:08 2024 X-Received: by 2002:a37:77c5:: with SMTP id s188mr5635038qkc.266.1605332066594; Fri, 13 Nov 2020 21:34:26 -0800 (PST) X-Received: by 2002:a25:aac5:: with SMTP id t63mr7617339ybi.22.1605332066406; Fri, 13 Nov 2020 21:34:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Nov 2020 21:34:26 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9d3d7f5b-c405-49b5-ac07-8cacb75633c8n@googlegroups.com> Subject: 'image of Enumerated Types From: "gnuarm.del...@gmail.com" Injection-Date: Sat, 14 Nov 2020 05:34:26 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9802 I never realized that if you use characters to enumerate a type, when you use the 'image attribute on it you get the apostrophes along with the character! type Pixel_t is ('_', '@'); function pixel (Data : natural) return string is variable temp : string (1 to 3); begin temp := Pixel_t'image(Pixel_t'Val(Data)); report "Pixel - temp = """ & temp & """"; results in NOTE : Pixel - temp = "'_'" Am I the only one surprised by this? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:08 2024 X-Received: by 2002:a37:4796:: with SMTP id u144mr16887224qka.235.1605564348609; Mon, 16 Nov 2020 14:05:48 -0800 (PST) X-Received: by 2002:a25:4189:: with SMTP id o131mr25854396yba.95.1605564348392; Mon, 16 Nov 2020 14:05:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 16 Nov 2020 14:05:48 -0800 (PST) In-Reply-To: <9d3d7f5b-c405-49b5-ac07-8cacb75633c8n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=50.38.36.249; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.38.36.249 References: <9d3d7f5b-c405-49b5-ac07-8cacb75633c8n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <905888e5-b1db-4d15-976d-819a19052485n@googlegroups.com> Subject: Re: 'image of Enumerated Types From: Jim Lewis Injection-Date: Mon, 16 Nov 2020 22:05:48 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 2 Xref: reader02.eternal-september.org comp.lang.vhdl:9803 Have you tried the VHDL-2008, to_string? It was added due to this issue and since it can be overloaded. From newsfish@newsfish Thu Aug 1 00:46:09 2024 X-Received: by 2002:ae9:e317:: with SMTP id v23mr4106457qkf.152.1605697230961; Wed, 18 Nov 2020 03:00:30 -0800 (PST) X-Received: by 2002:a25:d7d8:: with SMTP id o207mr6163590ybg.274.1605697230800; Wed, 18 Nov 2020 03:00:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Nov 2020 03:00:30 -0800 (PST) In-Reply-To: <905888e5-b1db-4d15-976d-819a19052485n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <9d3d7f5b-c405-49b5-ac07-8cacb75633c8n@googlegroups.com> <905888e5-b1db-4d15-976d-819a19052485n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <20236b96-cd06-4e39-8f49-7c883a8c5f23n@googlegroups.com> Subject: Re: 'image of Enumerated Types From: "gnuarm.del...@gmail.com" Injection-Date: Wed, 18 Nov 2020 11:00:30 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9804 On Monday, November 16, 2020 at 5:05:50 PM UTC-5, j...@synthworks.com wrote= : > Have you tried the VHDL-2008, to_string?=20 >=20 > It was added due to this issue and since it can be overloaded. Mostly the reason is I was not aware of that one. I guess I've been blowin= g right past all the times I must have seen it. I was aware of to_hstring(= ). So to_string() will give the character without the enclosing apostrophe= s? Why would they have implemented 'image that way in the first place? = =20 VHDL had some unusual thinkers in the mix when it was being developed. I h= ad occasion to converse with one and when asked why some feature was so mes= sed up he dug into the bowels to explain the logical analysis of the standa= rd. It was an effort to get him to understand the question was "Why is it = that way?" which pretty much meant nothing to him. It just was as if no on= e developing the language considered that anyone might want to use the lang= uage for productive work. It was financed by the government, no?=20 I worked with the people developing the Enhanced Modular Signal Processor. = Great ideas early on, but then reality had to be faced and after some year= s of ever diminishing expectations it bit the dust. A previous job was wi= th a company designing array processors... a DSP chip in rack cabinets befo= re anyone thought about DSP on a chip, like the Cray. All the concepts of = data flow, etc. could have been implemented on any machine really. But the= y were designing custom hardware to go in subs and ships and such, mostly w= ater cooled. Then there was the odd duck that would fly where weight was t= he premium consideration. It couldn't be everything to everyone.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:09 2024 X-Received: by 2002:a37:5f42:: with SMTP id t63mr8481590qkb.449.1605742518366; Wed, 18 Nov 2020 15:35:18 -0800 (PST) X-Received: by 2002:a25:e805:: with SMTP id k5mr16597606ybd.32.1605742518144; Wed, 18 Nov 2020 15:35:18 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Nov 2020 15:35:17 -0800 (PST) In-Reply-To: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=84.198.244.197; posting-account=EL_XigoAAADHfLPlITuhtQb83Nk8Aggn NNTP-Posting-Host: 84.198.244.197 References: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI OMICIDA A LUGAN From: FRANCESCO CARBONE USEMLAB MALTA Injection-Date: Wed, 18 Nov 2020 23:35:18 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9805 E' DA ARRESTARE PAOLO BARRAI, IL PEDOFILO ASSASSINO DEL BITCOIN, DI TERRABI= TCOIN E DI TELEGRAM! ATTIVO A RICICLARE CASH DI NDRANGHETA VIA CRIMINALE IC= O EIDOO! E SOLDI LERCISSIMI DI LEGA LADRONA, PURE A PORTO SEGURO, IN BRASIL= E, OVE INFATTI SCAPPAVA IL LEGHISTA ORA IN CARCERE: LUCA SOSTEGNI! E' DA ARRESTARE SUBITO: PAOLO BARRAI, FACENTE MIGLIAIA DI TRUFFE E RICICLAG= GI DI SOLDI CRIMINALI, VIA TELEGRAM ( NOTO COME "IL PEDOFILO DI TERRABITCOI= N E DEL BITCOIN). IL DELINQUENTE LEGHISTA LUCA SOSTEGNI, ORA IN GALERA, STA= VA SCAPPANDO IN BRASILE A PORTO SEGURO, DOVE IL VERME MALAVITOSO PAOLO BARR= AI HA LAVATO PARTE DEI 49 MLN =E2=82=AC RUBATI DA LEGA LADRONA! E' STATO IL= REGISTA MALAVITOSO DELL'OPERAZIONE "EIDOO RICICLA SOLDI MAFIOSI PER LA NDR= ANGHETA"! IL GIA' 3 VOLTE FINITO IN GALERA, IL DELINQUENTE PAOLO BARRAI ABI= TAVA A MILANO, IN VIA IPPODROMO 105 (ZONA SAN SIRO- CERTOSA). ED IN ZONA SA= N SIRO - CERTOSA, I RAS NDRANGHETISTI ERANO I MEGA ASSASSINI GIULIANO MARTI= NO, VINCENZO MARTINO E DOMENICO MARTINO. https://milano.repubblica.it/cronaca/2015/03/09/news/_ndrangheta_la_procura= _di_milano_chiede_il_processo_per_la_cosca_che_voleva_mettere_le_mani_su_sa= n_siro-109119504/ ED INFATTI, STA BESTIA DELINQUENTISSIMA DI PAOLO BARRAI, NATO A MILANO IL 2= 8.6.1965, SPACCIAVA COCAINA UN PO' IN TUTTO IL NORD ITALIA, COME PURE IN CA= NTON TICINO, IN CIONNESSIONE PROPRIO COL NDRANGHETISTA OMICIDA GIULIO MARTI= NO, COL NDRANGHETISTA OMICIDA VINCENZO MARTINO E COL NDRANGHETISTA OMICIDA = DOMENICO MARTINO. COME PURE PER IL FACCENDIERE CRIMINALISSIMO FRANCO LONGO.= POSE POI TUTTA STA GANG MALAVITOSA IN CONTATTO COL PORCO CRIMINALISSIMO OL= IVER CAMPONOVO DI CHIASSO! COME DA QUESTO STUPENDO DOCUMENTARIO: https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l AL PUNTO, NOW, PLEASE AND STRA PLEASE. E' UN PEDOFILO ASSASSINO, SPACCIATORE DI COCAINA E MEGA RICICLA SOLDI MAFIO= SI: PAOLO BARRAI ( CRIMINALISSIMA BIGBIT, CRIMINALISSIMA CRYPTOLAB E CRIMIN= ALISSIMA CRYPTOPOLIS)! NATO A MILANO IL 28.6.1965! https://twitter.com/megliomortiche1 HA APPENA RICICLATO SOLDI ASSASSINI DI NDRANGHETA IN MALAVITOSA ICO EIDOO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html E' UN LADRO E TRUFFATORE CHE TI AZZERA TUTTI I RISPARMI: PAOLO BARRAI! E' U= N IDIOTA CHE SBAGLIA, SEMPRE, SEMPRE E STRA SEMPRE IN BORSA: PAOLO BARRAI! = E' UN NAZISTA, RAZZISTA, KU KLUK KLANISTA, SUPER STRA ANTISEMITA PAOLO BARR= AI! E' UN PEDOFILO INCULA ED AMMAZZA BAMBINI: PAOLO BARRAI! E' UN TERRORIST= A DI ESTREMA DESTRA, NONCHE' UNO SPIETATISSIMO ASSASSINO: PAOLO BARRAI! ED = E' PROTETTO DAI PIU' BASTARDI ASSASSINI NAZISTI SERVIZI SEGRETI, TIPO QUELL= I DEL FIGLIO DI CANE PEDOFILO E KILLER DONALD TRUMP E NON SOLO... NON ABBIA= MO NULLA CONTRO GLI USA MA TUTTO CONTRO STO PEZZO DI MERDA MAFIOSO, RICICLA= SOLDI MAFIOSI, MACCARTISTA, NAZISTA, RAZZISTA, KUKLUKKLANISTA, LADRO, TRUF= FATORE, DITTATORE CHE E' IL VERME PEDOFILO DONALD TRUMP E NE SIAM FIERISSIM= I https://www.vox.com/world/2018/9/12/17764132/trump-fbi-russia-new-york-time= s-craig-unger https://www.washingtonpost.com/outlook/trumps-businesses-are-full-of-dirty-= russian-money-the-scandal-is-thats-legal/2019/03/29/11b812da-5171-11e9-88a1= -ed346f0ec94f_story.html?noredirect=3Don&utm_term=3D.ec8f6c557406 https://www.vice.com/en_us/article/ppx7b9/a-brief-history-of-donald-trump-a= nd-the-mafia https://www.dailymail.co.uk/news/article-3716125/How-Trump-Mob-offer-not-re= fuse-killing-building-skyscraper-Donald-s-shrewdest-investment-MAFIA.html https://www.elconfidencial.com/mundo/2019-04-03/donald-trump-siempre-miente= -jugando-al-golf_1920226/ https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiTsE= CA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores https://www.fitsnews.com/wp-content/uploads/2017/10/trump-pig-694x1024.jpg = ) ED E' TANTO QUANTO UN COCAINOMANE PAZZO E MANIACO FACENTE FILM PORNO EFFETT= UANDO SESSO ORALE CON CAVALLI: PAOLO PIETRO BARRAI, NATO A MILANO IL 28.6.1= 965 ( NON PER NIENTE E' NOTISSIMO IN TUTTO IL MONDO COME " CCC CIUCCIA CAZZ= I DI CAVALLO PAOLO BARRAI")! https://twitter.com/megliomortiche1/status/1100194746675458048 OLTRE CHE LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN BORSA, AZZERANT= E I RISPARMI DI TUTTI E SEMPRE! OLTRE A STRA ESSERE UN NAZI-ST-ALKER VIA IN= TERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TORTURATORE OMICIDA! O= LTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A = SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA = FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/repubblica/archivio= /repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio= .html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png ). OLTRE AD ESSERE STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 E= URO, PER MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.blue= rating.com/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-c= he-ha-violato-gli-obblighi-informativi http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://www.corrieredellacalabria.it/cronaca/item/141842-il-riciclaggio-del= le-cosche-in-svizzera-facevano-tutti-cosi/ https://www.ilfattoquotidiano.it/2018/05/17/ndrangheta-e-riciclaggio-in-can= ton-ticino-cosi-fan-tutti-un-fiduciario-si-confessa-alla-tv-svizzera/436037= 2/ http://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-della= -ndrangheta-29f7ee00 http://ilpunto-borsainvestimenti.blogspot.com/2017/10/cryptopolis-il-debutt= o-di-un-figlio.html - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://in.memory.of.e.tern.al/comp.lang.tcl/thread/4226231 - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html - AL NOTO PEDOFILO OMOSESSUALE E KU KLUK KLANISTA, NAZISTISSIMO GIACOMO ZUC= CO DI CRIMINALISSIMA BLOCKCHAINLABIT, DI CRIMINALISSIMA BHB - BLOCKCHAINLAB= , DI CRIMINALISSIMA WMO https://www.facebook.com/giacomo.zucco - AL NOTO PEDOFILO NAZISTA, MAFOSO E KU KLUK KLANISTA ARNOLD CAZARES DI LAR= EDO TEXAS https://www.linkedin.com/in/arnoldcazares - AL FIGLIO DI PUTTANA STALKER VIA INTERNET, NONCHE' PURE NOTISSIMO PEDOFIL= O MEGA COCAINIMANE LUCA MORISI ( CHE AMA FARSI CHIAMARE ^ SATANAZISTISSIMEN= TE^ ... LA BESTIA, IN QUANTO FACEVA PARTE DELLE BESTIE DI SATANA, LE QUALI = ERANO NOTORIAMENTE TUTT'UNO CON LEGA LADRONA https://danielesensi.blogspot.com/2010/01/la-disperazione-di-una-mamma-mio-= figlio.html ED A CUI INFATTI FAREMO FARE UNA FINE "BESTIALISSIMA" https://www.welt.de/politik/ausland/plus180987808/Italien-Der-maechtige-Unb= ekannte-hinter-dem-Biest.html ) EFFETTUA MEGA TRUFFE, ORDINA OMICIDI, FINANZIA PEDOFILIA ON LINE, RICICLA S= OLDI SUPER ASSASSINI A LUGANO!!! Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesenti= , immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto, m= assone nazifascista, nonche' famosissimo ladro, truffatore, azzera risparmi= di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo p= edofilo Paolo Pietro Barrai ( che venne cacciato da Citibank, a fine anni 9= 0, per terrificanti frodi che li effettuava, come da finale di questo artic= olo https://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19= /maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html il grande banchi= ere Giulio Di Cerbo licenzio' in tronco il verme criminalissimo Paolo Barra= i e lo fece condannare al carcere, pochi anni dopo, il bastardo nazista e n= dranghetista assassino Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo= apparire il tutto come morte naturale .... vedi giustissimo commento scrit= to qui http://giuliodicerbo.blogspot.com/2018/02/dear-i-am-very-sorry-for-b= eing-late-to.html ). Di delinquentissima Medicalchain, di delinquentissima = Cryptolab S A, di delinquentissima Bigbit, di delinquentissima Bitcoin Cryp= toeconomy, di delinquentissima Bitincubator & Venture, di delinquentissima = Bgbit News Channel e delinquentissima @bigbitnewschannel. Attraverso i qual= i strumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, f= allimentare trader Federico Izzi di Roma (che campa, di fatto, riciclando s= oldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda c= riminalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da= chiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo d= ella Camorra"). Sti due pezzi di merda criminalissimi spennano " i polli de= l web=C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, = totalmente fallimentari ( delinquentissimo servizio chiamato Bigbit) Costoro ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima e super stra ndranghet= ista Eidoo). https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ Si, proprio cosi', insieme al figlio di puttana Natale Ferrara di Reggio Ca= labria o Natale Massimiliano Ferrara di Reggio Calabria, uno scarafaggio de= lla Ndrangheta ( e di fallimentarissima Eidoo). Che e' passato da allevare = pollame con la sua amatissima Ndrangheta a spennare penne ai " polli del we= b", che idiotissimamente cadono nelle sue trappole criminalissime ogni gior= no. https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Imboscatosi ora qui in Svizzera, per non finire in galera, ben appunto, a R= eggio Calabria. Che ha rifilato a la merda di Ico completamente fallimentar= e chiamata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone nazista, razzista, ku kluk klanista, mafioso, ri= cicla soldi mafosi, pedofilo Donald Trump ( https://2.bp.blogspot.com/-LPBPPLwaZ84/WIAPeEY9HCI/AAAAAAAAMsA/HmIOC-MJiT= sECA3dzebwRakgAzLyIU9ugCLcB/s1600/trump%2Band%2Bhooker.jpg https://whyweprotest.net/attachments/trump-pedophile-one-jpg.259858/ http://www.bubbleofdelusions.com/images/donald-trump-pedophile2.jpg https://www.newstalk.com/Donald-Trump-accused-of-statutory-rape-assault-and= -battery-against-13yearold-girl https://www.noticiasaominuto.com/mundo/1045873/trump-tera-participado-em-fe= stas-com-muita-cocaina-e-jovens-menores ) sta cercando, insieme al pezzo di merda nazistissimo ed assassino Jamie Dim= on ( http://wallstreetonparade.com/2016/09/strange-deaths-of-jpmorgan-worke= rs-continue/ ) di tirargli su detta merda! Il tutto, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, t= ira su, come al solito, anche, i suoi tre grammi giornalieri di cocaina, pr= esso la White "Powder" House! https://www.thedailybeast.com/the-drug-trafficker-donald-trump-risked-his-c= asino-empire-to-protect Torniamo in ogni caso, ora, al punto iniziale, jetzt, bitte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo ca= cciato immediatamente il ladrone, truffatore, pure mandante di omicidi e no= tissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, truff= atore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai na= to a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries. Fr= a i tantissimi crimini che lo stesso effettua, per noi banchieri svizzeri, = il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per la M= afia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, noto f= iduciario di ndrangheta, come pure insieme al pezzo di merda super stra ndr= anghetista Natale Ferrara di Eidoo )! https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ Come anche, lava soldi rubati o frutti di mega mazzette in connessione a Le= ga Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non so= lo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi ( = il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi alt= rui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma prima= menzionato, noto, non per niente, in tutto il capoluogo laziale, sia come = "Er Zio Romolo incula bambini, come anche " Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich ( ora Vontobel Bank). Il puzzo = della merda, scusate il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi mega omicida dal figlio di troiacci= a criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato Lugano, dal fi= glio di troiaccia criminalissimo Daniele Albisetti di Banca dello Stato Lug= ano, dal figlio di troiaccia criminalissimo Claudio Genasci di Banca dello = Stato Lugano, dal figlio di troiaccia criminalissimo Patrick Lafranchi di B= anca dello Stato Lugano, dal figlio di troiaccia criminalissimo Gabriele Za= nzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA= -SARASIN ZURICH PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO BAN= K VONTOBEL ZURICH. https://ch.linkedin.com/in/andreasnigg https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D146032483 From newsfish@newsfish Thu Aug 1 00:46:09 2024 X-Received: by 2002:ac8:5ccc:: with SMTP id s12mr3280798qta.364.1606925141180; Wed, 02 Dec 2020 08:05:41 -0800 (PST) X-Received: by 2002:a25:a4a1:: with SMTP id g30mr5135320ybi.195.1606925140965; Wed, 02 Dec 2020 08:05:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Dec 2020 08:05:40 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=81.214.105.189; posting-account=pLH8UQoAAAAOvd_GH-V6-au5DM93YCWw NNTP-Posting-Host: 81.214.105.189 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5cc19373-11c8-4450-af54-ff2f9cc9e7ecn@googlegroups.com> Subject: =?UTF-8?Q?For_example=2C_with_the_swap_input_in_it=2C_=22from_0x45F3?= =?UTF-8?Q?_to_0xF345=22=2C_the_F=C4=B1fo_memory_design?= From: =?UTF-8?B?QXlrdXQgWcSxbGTEsXo=?= Injection-Date: Wed, 02 Dec 2020 16:05:41 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9806 H=C4=B1 I am electronic and comunicaiton engeneering student.Our teacher g= ave us a project assignment, but at first he asked for the fifo memory, I c= reated the code for it, but I could not come up with an idea in the swap pa= rt, I will be glad if you help me. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fifomemory is Generic( FIFO_DERINLIGI : integer :=3D 250 ;=20 VERI_UZUNLUGU : integer :=3D 24; FIFO_DOLUYOR : integer :=3D 250; FIFO_BOSALIYOR : integer :=3D 10 ); Port (=20 in_clk : in std_logic; in_rst : in std_logic; in_yaz: in std_logic; in_oku : in std_logic; in_data: in std_logic_vector(VERI_UZUNLUGU -1 downto 0); out_doluyor: out std_logic; out_dolu: out std_logic; out_data: out std_logic_vector(VERI_UZUNLUGU -1 downto 0); out_data_vld: out std_logic; out_bosaliyor: out std_logic; out_bos: out std_logic ); end fifomemory; architecture Behavioral of fifomemory is type t_FIFO_DATA is array (0 to FIFO_DERINLIGI -1)of std_logic_vector(VERI= _UZUNLUGU -1 downto 0); signal r_FIFO_DATA: t_FIFO_DATA :=3D (others =3D>(others=3D>'0')); signal r_fifo_sayac: integer range -1 to FIFO_DERINLIGI +1 :=3D0; signal ind_yaz : integer range 0 to FIFO_DERINLIGI -1 :=3D0;=09 signal ind_oku : integer range 0 to FIFO_DERINLIGI -1 :=3D0; signal bayrak_dolu : std_logic :=3D '0'; signal bayrak_bos: std_logic :=3D '0'; signal r_data_vld: std_logic :=3D '0'; signal r_data : std_logic_vector(VERI_UZUNLUGU -1 downto 0) :=3D (others = =3D> '0'); =09 begin out_data <=3D r_data; out_data_vld <=3D r_data_vld; out_dolu <=3D '1' when r_fifo_sayac =3D FIFO_DERINLIGI else '0'; out_bos <=3D '1' when r_fifo_sayac =3D 0 else '0'; bayrak_dolu <=3D '1' when r_fifo_sayac =3D FIFO_DERINLIGI else '0'; bayrak_bos <=3D '1' when r_fifo_sayac=3D 0 else '0'; out_doluyor <=3D '1' when r_fifo_sayac > FIFO_DOLUYOR else '0'; out_bosaliyor <=3D '1' when r_fifo_sayac < FIFO_BOSALIYOR else '0'; process (in_clk, in_rst) begin=20 if in_rst =3D '1' then=20 r_FIFO_DATA<=3D (others =3D> (others =3D>'0')); r_fifo_sayac <=3D 0; ind_yaz <=3D 0; ind_oku <=3D 0; r_data_vld <=3D '0'; r_data <=3D (others =3D> '0'); elsif rising_edge(in_clk) then if in_yaz =3D '1' and in_oku =3D '0' then r_fifo_sayac <=3D r_fifo_sayac + 1; elsif in_yaz =3D '0' and in_yaz =3D '1' then=20 r_fifo_sayac <=3D r_fifo_sayac - 1; end if; if in_yaz =3D '1' and bayrak_dolu =3D '0' then=20 if ind_yaz =3D FIFO_DERINLIGI - 1 then=20 ind_yaz<=3D 0; else=20 ind_yaz <=3D ind_yaz + 1; end if; end if; if(in_oku =3D '1' and bayrak_bos =3D'0') then=20 if ind_oku =3D FIFO_DERINLIGI - 1 then ind_oku <=3D 0; else=20 ind_oku <=3D ind_oku + 1; end if ;=09 r_data <=3D r_FIFO_DATA (ind_oku); r_data_vld<=3D '1'; else=20 r_data_vld <=3D '0'; end if; end if; if in_yaz =3D '1' then=20 r_FIFO_DATA(ind_yaz)<=3D in_data; end if; end process; end Behavioral; From newsfish@newsfish Thu Aug 1 00:46:10 2024 X-Received: by 2002:a05:622a:14e:: with SMTP id v14mr29136291qtw.298.1607907162407; Sun, 13 Dec 2020 16:52:42 -0800 (PST) X-Received: by 2002:a25:7795:: with SMTP id s143mr34036103ybc.53.1607907162221; Sun, 13 Dec 2020 16:52:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 13 Dec 2020 16:52:41 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: use IEEE.STD_LOGIC_UNSIGNED.ALL; From: "gnuarm.del...@gmail.com" Injection-Date: Mon, 14 Dec 2020 00:52:42 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9807 I was reading a vendor's code for simulation of their DSP blocks and found this... use IEEE.STD_LOGIC_UNSIGNED.ALL; The horror! I really don't think I've ever tried to use this library. I assume it actually has to work though, right? The problem is mixing signed and unsigned I believe. Browsing through the library I noticed what appears to be a unary +. Looking it up I see a web page that says it has no effect. What is this for? More importantly, should I worry about any issues with the vendor using such an out of date, deprecated library? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:10 2024 X-Received: by 2002:ac8:714c:: with SMTP id h12mr36980137qtp.361.1608055945605; Tue, 15 Dec 2020 10:12:25 -0800 (PST) X-Received: by 2002:a25:1e43:: with SMTP id e64mr46162865ybe.273.1608055945449; Tue, 15 Dec 2020 10:12:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Dec 2020 10:12:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <595027a9-979b-4ff9-8181-4a6dd91e8de7n@googlegroups.com> Subject: Re: use IEEE.STD_LOGIC_UNSIGNED.ALL; From: KJ Injection-Date: Tue, 15 Dec 2020 18:12:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9808 On Sunday, December 13, 2020 at 7:52:44 PM UTC-5, gnuarm.del...@gmail.com w= rote: > I was reading a vendor's code for simulation of their DSP blocks and foun= d this...=20 >=20 > use IEEE.STD_LOGIC_UNSIGNED.ALL;=20 >=20 OK, but that is in the vendor's code, not yours. >=20 > I really don't think I've ever tried to use this library. I assume it act= ually has to work though, right? The problem is mixing signed and unsigned = I believe.=20 >=20 It could be a possible problem for the vendor. Do they mix signed and unsi= gned? If there simulation models work, do you care? > Browsing through the library I noticed what appears to be a unary +. Look= ing it up I see a web page that says it has no effect. What is this for?=20 >=20 Dunno. > More importantly, should I worry about any issues with the vendor using s= uch an out of date, deprecated library?=20 >=20 Does your testing show a functional problem? Just because the code may be = old and not state of the art, doesn't mean that it doesn't work correctly. = Even if it is new code, it's still up to the vendor and if it is functiona= lly correct, what exactly would you complain about to the vendor? Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:10 2024 X-Received: by 2002:a05:622a:88:: with SMTP id o8mr38142522qtw.241.1608061531621; Tue, 15 Dec 2020 11:45:31 -0800 (PST) X-Received: by 2002:a25:bdc7:: with SMTP id g7mr44791397ybk.427.1608061531451; Tue, 15 Dec 2020 11:45:31 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Dec 2020 11:45:31 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <50db05e5-2f33-4e67-a560-e0d08fa78d96n@googlegroups.com> Subject: User Defined Operators From: "gnuarm.del...@gmail.com" Injection-Date: Tue, 15 Dec 2020 19:45:31 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 17 Xref: reader02.eternal-september.org comp.lang.vhdl:9809 Is this possible? I can't find much info on the Internet addressing the po= ssibility. Seems they only talk about overloading existing operators. =20 I created an example to define a new OR operator for integers as if they we= re 32 bits. That seemed to work ok. But when I called it "Ralph", the com= piler complains, not at the definition, but at the usage. It seems to init= ial accept that, but when it sees the second operand (or maybe on completio= n of recognizing the Ralph operator) it barfs say it was expecting a WHEN. = =20 So it is illegal to define new operators?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:10 2024 X-Received: by 2002:a05:620a:16c9:: with SMTP id a9mr9019653qkn.94.1608101577564; Tue, 15 Dec 2020 22:52:57 -0800 (PST) X-Received: by 2002:a25:c7c6:: with SMTP id w189mr47890163ybe.403.1608101577299; Tue, 15 Dec 2020 22:52:57 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Dec 2020 22:52:56 -0800 (PST) In-Reply-To: <595027a9-979b-4ff9-8181-4a6dd91e8de7n@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <595027a9-979b-4ff9-8181-4a6dd91e8de7n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: use IEEE.STD_LOGIC_UNSIGNED.ALL; From: "gnuarm.del...@gmail.com" Injection-Date: Wed, 16 Dec 2020 06:52:57 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9810 On Tuesday, December 15, 2020 at 1:12:28 PM UTC-5, KJ wrote: > On Sunday, December 13, 2020 at 7:52:44 PM UTC-5, gnuarm.del...@gmail.com= wrote:=20 > > I was reading a vendor's code for simulation of their DSP blocks and fo= und this...=20 > >=20 > > use IEEE.STD_LOGIC_UNSIGNED.ALL;=20 > > > OK, but that is in the vendor's code, not yours. > >=20 > > I really don't think I've ever tried to use this library. I assume it a= ctually has to work though, right? The problem is mixing signed and unsigne= d I believe.=20 > > > It could be a possible problem for the vendor. Do they mix signed and uns= igned? If there simulation models work, do you care? Of course I care, I have to use their models to simulate. Now that I see = the code details, I suppose I could try inferring the code. My initial att= empt using a multiplier and adder produced two DSP units, one for the multi= plier and one for the adder, not so good. I expect that had to do with dat= a widths or something. =20 > > Browsing through the library I noticed what appears to be a unary +. Lo= oking it up I see a web page that says it has no effect. What is this for?= =20 > > > Dunno. > > More importantly, should I worry about any issues with the vendor using= such an out of date, deprecated library?=20 > > > Does your testing show a functional problem? Just because the code may be= old and not state of the art, doesn't mean that it doesn't work correctly.= Even if it is new code, it's still up to the vendor and if it is functiona= lly correct, what exactly would you complain about to the vendor?=20 The vendor did not exist four years ago, so the code can't be too old. I'm= using the code to find out exactly how their parts work. The documentatio= n leaves a lot to the imagination which is not so good when designing with = things. I won't know if the code doesn't work until I run it on a chip. = Since I have no hardware that's not so easy as yet.=20 The up side is I haven't found too many surprises. Some things I expected = would be controls are actually configuration details, such as Add/Sub selec= tion. Their block diagrams show control signals that are registered (imply= ing real time controls) but never show up in the simulation code. They cal= l the adder an ALU and even talk about it doing arithmetic and *logic* func= tions, but it does nothing other than add or subtract as far as I can tell,= it's an accumulator with a real time enable for the output feedback. Is t= hat what anyone would think was logic? =20 They have inputs ASIGN and BSIGN which rather than acting as sign inputs fo= r subtraction, are controls for sign extension vs. zero fill. At least tha= t's something. =20 I've always thought it odd that the libraries needed to be added with every= module. Now I'm glad so this library doesn't muck up my code. But then I= tend to not use std_logic_vector mostly because I don't like all the typin= g. lol=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:11 2024 X-Received: by 2002:ac8:70cd:: with SMTP id g13mr17094877qtp.345.1608577181607; Mon, 21 Dec 2020 10:59:41 -0800 (PST) X-Received: by 2002:a25:a86:: with SMTP id 128mr23257982ybk.370.1608577181377; Mon, 21 Dec 2020 10:59:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Dec 2020 10:59:41 -0800 (PST) In-Reply-To: <5cc19373-11c8-4450-af54-ff2f9cc9e7ecn@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=204.148.35.130; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 204.148.35.130 References: <5cc19373-11c8-4450-af54-ff2f9cc9e7ecn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6d084d8d-d04e-448f-bc41-71c8bc674861n@googlegroups.com> Subject: =?UTF-8?Q?Re=3A_For_example=2C_with_the_swap_input_in_it=2C_=22from_0x?= =?UTF-8?Q?45F3_to_0xF345=22=2C_the_F=C4=B1fo_memory_design?= From: "gnuarm.del...@gmail.com" Injection-Date: Mon, 21 Dec 2020 18:59:41 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9811 On Wednesday, December 2, 2020 at 11:05:43 AM UTC-5, aykut...@gmail.com wro= te: > H=C4=B1 I am electronic and comunicaiton engeneering student.Our teacher = gave us a project assignment, but at first he asked for the fifo memory, I = created the code for it, but I could not come up with an idea in the swap p= art, I will be glad if you help me.=20 >=20 > library IEEE;=20 > use IEEE.STD_LOGIC_1164.ALL;=20 > use IEEE.STD_LOGIC_UNSIGNED.ALL;=20 >=20 > entity fifomemory is=20 > Generic(=20 > FIFO_DERINLIGI : integer :=3D 250 ;=20 > VERI_UZUNLUGU : integer :=3D 24;=20 > FIFO_DOLUYOR : integer :=3D 250;=20 > FIFO_BOSALIYOR : integer :=3D 10=20 > );=20 > Port (=20 > in_clk : in std_logic;=20 > in_rst : in std_logic;=20 > in_yaz: in std_logic;=20 > in_oku : in std_logic;=20 > in_data: in std_logic_vector(VERI_UZUNLUGU -1 downto 0);=20 > out_doluyor: out std_logic;=20 > out_dolu: out std_logic;=20 > out_data: out std_logic_vector(VERI_UZUNLUGU -1 downto 0);=20 > out_data_vld: out std_logic;=20 > out_bosaliyor: out std_logic;=20 > out_bos: out std_logic=20 > );=20 > end fifomemory;=20 >=20 > architecture Behavioral of fifomemory is=20 > type t_FIFO_DATA is array (0 to FIFO_DERINLIGI -1)of std_logic_vector(VER= I_UZUNLUGU -1 downto 0);=20 > signal r_FIFO_DATA: t_FIFO_DATA :=3D (others =3D>(others=3D>'0'));=20 > signal r_fifo_sayac: integer range -1 to FIFO_DERINLIGI +1 :=3D0;=20 > signal ind_yaz : integer range 0 to FIFO_DERINLIGI -1 :=3D0;=20 > signal ind_oku : integer range 0 to FIFO_DERINLIGI -1 :=3D0;=20 > signal bayrak_dolu : std_logic :=3D '0';=20 > signal bayrak_bos: std_logic :=3D '0';=20 > signal r_data_vld: std_logic :=3D '0';=20 > signal r_data : std_logic_vector(VERI_UZUNLUGU -1 downto 0) :=3D (others = =3D> '0');=20 >=20 > begin=20 > out_data <=3D r_data;=20 > out_data_vld <=3D r_data_vld;=20 > out_dolu <=3D '1' when r_fifo_sayac =3D FIFO_DERINLIGI else '0';=20 > out_bos <=3D '1' when r_fifo_sayac =3D 0 else '0';=20 > bayrak_dolu <=3D '1' when r_fifo_sayac =3D FIFO_DERINLIGI else '0';=20 > bayrak_bos <=3D '1' when r_fifo_sayac=3D 0 else '0';=20 > out_doluyor <=3D '1' when r_fifo_sayac > FIFO_DOLUYOR else '0';=20 > out_bosaliyor <=3D '1' when r_fifo_sayac < FIFO_BOSALIYOR else '0';=20 >=20 > process (in_clk, in_rst)=20 > begin=20 > if in_rst =3D '1' then=20 > r_FIFO_DATA<=3D (others =3D> (others =3D>'0'));=20 > r_fifo_sayac <=3D 0;=20 > ind_yaz <=3D 0;=20 > ind_oku <=3D 0;=20 > r_data_vld <=3D '0';=20 > r_data <=3D (others =3D> '0');=20 > elsif rising_edge(in_clk) then=20 > if in_yaz =3D '1' and in_oku =3D '0' then=20 > r_fifo_sayac <=3D r_fifo_sayac + 1;=20 > elsif in_yaz =3D '0' and in_yaz =3D '1' then=20 > r_fifo_sayac <=3D r_fifo_sayac - 1;=20 > end if;=20 > if in_yaz =3D '1' and bayrak_dolu =3D '0' then=20 > if ind_yaz =3D FIFO_DERINLIGI - 1 then=20 > ind_yaz<=3D 0;=20 > else=20 > ind_yaz <=3D ind_yaz + 1;=20 > end if;=20 > end if;=20 > if(in_oku =3D '1' and bayrak_bos =3D'0') then=20 > if ind_oku =3D FIFO_DERINLIGI - 1 then=20 > ind_oku <=3D 0;=20 > else=20 > ind_oku <=3D ind_oku + 1;=20 > end if ;=20 > r_data <=3D r_FIFO_DATA (ind_oku);=20 > r_data_vld<=3D '1';=20 > else=20 > r_data_vld <=3D '0';=20 > end if;=20 > end if;=20 > if in_yaz =3D '1' then=20 > r_FIFO_DATA(ind_yaz)<=3D in_data;=20 > end if;=20 > end process;=20 > end Behavioral; Somewhere in the code swap the high byte and the low byte. You don't show = the calling sequence and your default bit width is 24, so I'm not sure how = to code this generally, the requirement is not clear. So I'll assume the r= equirement is to swap the high bits with the low bits regardless of bus siz= e.=20 out_data(VERI_UZUNLUGU -1 downto VERI_UZUNLUGU / 2) <=3D r_data((VERI_UZUNL= UGU / 2) -1 downto 0); out_data((VERI_UZUNLUGU / 2) -1 downto 0) <=3D r_data(VERI_UZUNLUGU -1 down= to VERI_UZUNLUGU / 2); VERI_UZUNLUGU must be even. You might want to add an assert statement to = verify this. But not required since an odd value will cause a mismatch in = these assignments and cause an error. An assert will give a very clear err= or report though instead of a cryptic syntax error.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:11 2024 X-Received: by 2002:a37:9d56:: with SMTP id g83mr13839847qke.38.1612134921877; Sun, 31 Jan 2021 15:15:21 -0800 (PST) X-Received: by 2002:a25:bb12:: with SMTP id z18mr22426229ybg.488.1612134921604; Sun, 31 Jan 2021 15:15:21 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.szaf.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 31 Jan 2021 15:15:21 -0800 (PST) In-Reply-To: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=31.31.151.104; posting-account=0u-_QgoAAABVd19iXB71E2R2Sl8DPf16 NNTP-Posting-Host: 31.31.151.104 References: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <76bd5f91-9335-4428-8755-f2e295bdbba1n@googlegroups.com> Subject: Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI OMICIDA A LUGAN From: Andreas Nigg Injection-Date: Sun, 31 Jan 2021 23:15:21 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9812 On Friday, November 9, 2018 at 9:12:26 PM UTC+1, pippot...@outlook.com wrot= e: > FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIA= MANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E = COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAV= A SOLDI OMICIDA A LUGANO!=20 >=20 > Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pesen= ti, immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quanto,= massone nazifascista, nonche' famosissimo ladro, truffatore, azzera rispar= mi di ognuno che gli abbocca via iternet e non solo, nonche' criminalissimo= pedofilo Paolo Barrai. Di delinquentissima Bigbit, delinquentissima Bgbit = News Channel e delinquentissima @bigbitnewschannel. Attraverso i quali stru= menti, lui ed il fallitissimo, idiota, davvero deficente, incapace, fallime= ntare trader Federico Izzi di Roma (che campa, di fatto, riciclando soldi m= afiosi e facendo film pedopornofrafici, tanto e' vero che sta merda crimina= lissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da chiun= que, come "Er Zio Romolo incula bambini e pure come Er Zio Romolo della Cam= orra"). Sti due pezzi di merda criminalissimi spennano " i polli del web=C2= =A8, vendendo loro abbonamenti annuali su criptovalute e non solo, totalmen= te fallimentari ( delinquentissimo servizio chiamato Bigbit)=20 > Che ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso most= rarvi centinaia di casi, venuti, disperati, a piangersene da me, a proposit= o). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno sca= rafaggio della Ndrangheta ( e di fallimentarissima Eidoo). Si, proprio cosi= ', insieme al figlio di puttana Natale Massimiliano Ferrara di Reggio Calab= ria, uno scarafaggio della Ndrangheta ( e di fallimentarissima Eidoo). Imbo= scatosi qui in Svizzera, per non finire in galera, ben appunto, a Reggio Ca= labria. Che ha rifilato a la merda di Ico completamente fallimentare chiama= ta Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdone = nazipedofilo Donald Trump sta cercando di tirargli su detta merda, il tutto= , ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, tira su, = come al solito, anche, i suoi tre grammi giornalieri di cocaina, presso la = White "Powder" House) . Torniamo in ogni caso, ora, al punto iniziale, bitt= e. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbiamo= cacciato immediatamente il ladrone, truffatore, pure mandante di omicidi e= notissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, tr= uffatore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barrai= nato a Milano il 28.6.1965), dalla lista di nostri Banking Intermediaries.= Fra i tantissimi crimini che lo stesso effettua, per noi banchieri svizzer= i, il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per l= a Mafia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, not= o fiduciario di ndrangheta)!=20 > Come anche, lava soldi rubati o frutti di mega mazzette in connessione a = Lega Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e non = solo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berlusconi = ( il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi a= ltrui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma pri= ma menzionato, noto, non per niente, in tutto il capoluogo laziale, sia com= e "Er Zio Romolo incula bambini, che come Er Zio Romolo della Camorra"). Ni= ente merda nella nuova Finter Bank Zurich. Il puzzo della merda, scusate il= temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi meg= a omicida dal figlio di puttana criminalissimo Fabrizio Cieslakiewicz di Ba= nca dello Stato Lugano, dal figlio di puttana criminalissimo Daniele Albise= tti di Banca dello Stato Lugano, dal figlio di puttana criminalissimo Claud= io Genasci di Banca dello Stato Lugano, dal figlio di puttana criminalissim= o Patrick Lafranchi di Banca dello Stato Lugano, dal figlio di puttana crim= inalissimo Gabriele Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!!= =20 > ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAF= RA-SARASIN ZURICH. IL LEGHISTA NAZISTA ED ASSASSINO PAOLO BARRAI (NOTO IN TUTTO IL MONDO COME = IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI MILANO, COME PUR= E DA PROCURA DI LUGANO, DA SCOTLAND YARD LONDRA, DA FBI NEW YORK E POLICIA = CIVIL DI PORTO SEGURO (BRASILE). IL TUTTO VIA INTERPOL ED EUROPOL! 1 =C3=89 DAVVERO PEDOFILO ED ASSASSINO: PAOLO BARRAI DI CRIMINALE TERRA BITCO= IN! IL CRIMINALE LEGHISTA LUCA SOSTEGNI, INCARCERATO, SCAPPAVA IN CITATA PO= RTO SEGURO (BR), DOVE L'OMICIDA PAOLO BARRAI HA RICICLATO PARTE DEI 49 MLN = =E2=82=AC RUBATI DA LEGA LADRONA! (ECCONE LE PROVE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 ) =C3=89 TRUFFATORE, PEDOFILO E KILLER: PAOLO BARRAI, NATO A MILANO IL 28.6.1= 965 ( O TRUFFATORE, PEDOFILO E KILLER: PAOLO PIETRO BARRAI, NATO A MILANO I= L 28.6.1965). DI CRIMINALE TERRA BITCOIN (ASSOCIAZIONE CON INTENTO DI FOTTE= RE, FREGARE, SPENNARE POLLI VIA INTERNET, IL TUTTO VIA TELEGRAM) E CRIMINAL= ISSIMO BLOG MERCATO LIBERO, ALIAS "MERDATO" LIBERO! INDAGATO, AL MOMENTO, D= ALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD= LONDRA E DA FBI NEW YORK. HA RICICLATO 21 MLN ASSASSINI DI NDRANGHETA, IN FALLENTISSIMA ICO EIDOO (IN= SIEME AL MALAVITOSO NATALE FERRARA DI REGGIO CALABRIA, DA DECENNI PUNCIUTO,= OSSIA AFFILIATO UFFICIALMENTE ALLA NDRANGHETA, INSIEME AL MALAVITOSO PAOLO= CARDEN=C3=81 DI FREGA SOLDI BLOG VINCITORI E VINTI, INSIEME AL MALAVITOSO = STEFANO BASSI DI FREGA SOLDI BLOG IL GRANDE BLUFF, INSIEME AL MALAVITOSO FE= DERICO IZZI, NOTO COME "ER ZIOROMOLO DELLA CAMORRA", LI VEDETE TUTTI IN FOT= O QUI https://3.bp.blogspot.com/-6WRXJQbHe08/WSBR0uTrMLI/AAAAAAAAY2g/L8c3w9= GGr3wpG7yWxBBeOohzhWa7iJ7uQCLcB/s1600/18558610_10156258698827281_4591948382= 498991167_o.jpg ) 2 CHECK EVERY DETAIL BOUT IT, HERE https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit 3 IL PEDERASTA OMICIDA PAOLO BARRAI =C3=89 ANCHE DI UNO DEI PRINICIPALI CRIMI= NALI UNENTI NDRANGHETA E MASSONERIA. =C3=89 DA SEMPRE UN CAPO SANTISTA (OSS= IA NDRANGHETISTA MASSONE). INFATTI ERA PAPPA E CICCIA CON L'ARRESTATO MASSO= NE NDRANGHETISTA BERLUSCONICCHIO GIANCARLO PITTELLI (http://www.iacchite.bl= og/giancarlo-pittelli-laffarista-massone-dei-boss-della-ndrangheta/ ). ED E= RA CICCIA E PAPPA PURE CON GRAN PARTE DEI 334 MASSONI NDRANGHETISTI ARRESTA= TI DAL GRANDE PM NICOLA GRATTERI NEL DICEMBRE 2019 ( https://www.ilprimaton= azionale.it/cronaca/ndrangheta-334-arresti-onorevoli-massoni-colonnello-cos= che-140387/ ). MI PRESENTO. SONO IL RIVOLUZIONARIO A FINI DI BENE: ANDREAS NIGG VICE PRESIDENT AND HEAD= OF ASSET MANAGEMENT. PRESSO SAFRA-SARASIN BANK ZURICH PRIMA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK VONTOBEL ZURI= CH. https://citywireselector.com/manager/andreas-nigg/d2395 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTER = BANK ZURICH DEL MASSONE LEGHISTA E NAZISTA CARLO PESENTI (NOTO PARTNER OMOS= ESSUALE DEL SATANISTA MASSONE FEDERICO TRABUCCO DI KAIROS). ED IO IN PERSON= A, ANDREAS NIGG, ORDINAI SUBITO DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI = A STA BESTIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL= 28.6.1965. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA, CAMORRA, PEDOFI= LO STRAGISTA SILVIO BERLUSCONI, LESBICA PEDOFILA ASSASSINA MARINA BERLUSCON= I E 49 MILIONI DI =E2=82=AC RUBATI DA LEGA LADRONA? DA LONTANO 3.000 KM (NO= N SONO ANTI OMOSESSUALI O LESBICHE, mA ODIO L'IPOICRISIA E LA MAFIOSA OMERT= =C3=81 CHE DA SEMPRE REGNA IN ITALIA, LA MIA RIVOLUZIONE, LA RIVOLUZIONE DI= ANDREAS NIGG DI BANK SAFRA SARASIN ZURICH, RADER=C3=81 A ZERO STA BERLUSCO= NICCHIA IPOCRISIA ED OMERT=C3=81 PUZZOLENTE, ALLA BASE DI OGNI MALE, NEL PA= ESE DEL GRANDE SANDRO PERTINI)! HO ALTRE TONNELLATE DI COSE DA SCRIVERE SU STO PEDOFILO ASSASSINO, LAVA SOL= DI CRIMINALI E NAZIRAZZISTA DI PAOLO BARRAI, MA LO FAR=C3=93 CON CALMA ED A= TTRAVERSO ALTRI MILIONI DI MIEI SCRITTI. ORA DEVO VINCERE NEI MERCATI PER = SAFRA-SARASIN BANK ZURICH. HASTA LA VISTORIA SIEMPRE. (VICTORIA NON COMUNISTA, MA ALLA VINCENTISSIMO ... CI SIAMO CAPITI) ANDREAS NIGG. SAFRA-SARASIN BANK ZURICH. 4 Anzi, meglio ribadire... Quando come Vontobel Bank Zurich, abbiamo comprato Finter Bank Zurich, dai = massoni leghisti e nazifascisti Pesenti, immediatamente abbiamo chiuso tutt= i i conti connessi, al, tanto quanto, massone leghista nazifascista, nonche= ' famoso ladro, truffatore, azzera risparmi di ognuno che gli abbocca via i= nternet e non solo, nonch=C3=A9 pedofilo Paolo Pietro Barrai ( che venne ca= cciato da Citibank, a fine anni 90, per terrificanti frodi che li effettuav= a, come da finale di questo articolo https://ricerca.repubblica.it/repubbli= ca/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-so= tto-torchio.html il grande banchiere Giulio Di Cerbo licenzio' in tronco il= verme criminalissimo Paolo Barrai e lo fece condannare al carcere, pochi a= nni dopo, il bastardo nazista e ndranghetista killer Paolo Barrai fece amma= zzare Giulio Di Cerbo, facendo fintamente apparire il tutto come morte natu= rale... il tutto via Massonerie Fasciste e Servizi Segreti Fascisti a cui i= l pedofilo assassino Paolo Pietro Barrai =C3=A9 connessissimo). Di delinque= ntissima Medicalchain, di delinquentissima Cryptolab S A, di delinquentissi= ma Bigbit, di delinquentissima Bitcoin Cryptoeconomy, di delinquentissima B= itincubator & Venture, di delinquentissima Bgbit News Channel e delinquenti= ssima Terra Bitcoin. Attraverso i quali strumenti, lui ed il fallitissimo, = idiota, davvero incapace e fallimentare trader Federico Izzi di Roma (che c= ampa, di fatto, riciclando soldi mafiosi e facendo film pedopornofrafici, t= anto e' vero che sta merda criminale di Federico Izzi di Roma, e' noto sull= e rivere del Tevere, da chiunque, come "Er Zio Romolo incula bambini" e pur= e come "Er Zio Romolo della Camorra") spennano " i polli del web=C2=A8, ven= dendo loro abbonamenti annuali su criptovalute e non solo, totalmente falli= mentari! A fra non molto via altri miei miliardi di scritti che preparer=C3=B3! ANDREAS NIGG. SAFRA-SARASIN BANK ZURICH. From newsfish@newsfish Thu Aug 1 00:46:11 2024 X-Received: by 2002:a05:6214:1103:: with SMTP id e3mr17854223qvs.12.1612218880747; Mon, 01 Feb 2021 14:34:40 -0800 (PST) X-Received: by 2002:a25:a86:: with SMTP id 128mr25267069ybk.370.1612218880012; Mon, 01 Feb 2021 14:34:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.uzoreto.com!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 1 Feb 2021 14:34:39 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=84.198.244.196; posting-account=zOs1jwoAAAA1_l85uThj5P9phTRPQSXe NNTP-Posting-Host: 84.198.244.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <534a8a87-24df-40d6-a7ac-904f7f4363ccn@googlegroups.com> Subject: =?UTF-8?Q?=C3=89_PEDOFILO_ASSASSINO=2C_L=27AVVOCATO_NAZISTA_DANIELE_MI?= =?UTF-8?Q?NOTTI_DI_GENOVA_E_CRIMINALE_STUDIO_LEGALE_LISI_=28https=3A=2F=2Fecam?= =?UTF-8?Q?pus=2Eaicel=2Eorg=2Fwp=2Dcontent=2Fuploads=2FDaniele=2DMinotti=2D300x300=2Ejpg?= =?UTF-8?Q?_=29=21_NONCHE=27_DI_MASSONERIE_SATANISTE_E_SERVIZI_SEGRETI_BERLUS?= =?UTF-8?Q?CONIANI_STRAGISTI=21?= From: PEDOFILO SATANISTASSASSINO DANIELE MINOTTI Injection-Date: Mon, 01 Feb 2021 22:34:40 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 556 Xref: reader02.eternal-september.org comp.lang.vhdl:9813 =C3=89 PEDOFILO ASSASSINO, L'AVVOCATO NAZISTA DANIELE MINOTTI DI GENOVA E C= RIMINALE STUDIO LEGALE LISI (https://ecampus.aicel.org/wp-content/uploads/D= aniele-Minotti-300x300.jpg )! NONCHE' DI MASSONERIE SATANISTE E SERVIZI SEG= RETI BERLUSCONIANI STRAGISTI! =C3=89 DAVVERO DA ARRESTARE L'AVVOCATO SATANISTA, NAZISTA, SATANAZISTA, MAS= SONE DI TIPO OMICIDA, PEDOFILO, ASSASSINO DANIELE MINOTTI DI CRIMINALISSIMO= STUDIO LEGALE LISI: RAPISCE, INCULA, AMMAZZA TANTI BAMBINI PER VENDERNE GL= I ORGANI! COME DA QUESTA ALTRA ABERRANTE FOTO https://steemitimages.com/p/3auKdN6FdQE37hxp1zh1p7U4iqfKLDE9AdpKRQpQV5g36Go= ZLfg7ABa1V4fE2z?format=3Dmatch&mode=3Dfit&width=3D640 E' DAVVERO DA ARRESTARE IMMEDIATAMENTE L'AVV ASSASSINO E PEDERASTA DANIELE = MINOTTI DI RAPALLO E GENOVA: IL NOTISSIMO PEDOFILO INCULA ED AMMAZZA BAMBIN= I DANIELE MINOTTI!!! AVVOCATO MALAVITOSISSIMO, STUPRANTE INFANTI ED ADOLESC= ENTI, COME PURE OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LI= SI DI LECCE E MILANO E DI CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDIO LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI= MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PIU' = DI SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVERO)! = E' STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA ED UCCIDE= I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO DANIELE MINOTTI! QUESTO AVVOCATO= SATANISTA, NAZISTA, SATANAZISTA, DEPRAVATO, PERVERTITO, KILLER, DI RAPALLO= E GENOVA. https://www.flickr.com/photos/danieleminotti/ RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI, SEMPRE PIU' PEDERASTA ANCHE LUI: PIERSILVIO BER= LUSCONI! SI, SI E' PROPRIO COSI': E' DA ARRESTARE SUBITO L ' AVVOCATO SATAN= ISTA, NAZISTA, ^SATA-N-AZISTA^, PEDOFILO ED OMICIDA: DANIELE MINOTTI DI GEN= OVA E RAPALLO! ASSASSINO LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORIST= A DI ESTREMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, = AIZZANTE TANTI SUICIDI CON STILE TIPICO DI AGENTE SEGRETO IN COPERTO DI TIP= O STRAGISTA E SVASTICATO! https://www.py.cz/pipermail/python/2017-March/012979.html 1 OGNI SETTIMANA SGOZZA OLTRE CHE CANI, GATTI E SERPENTI, TANTI BAMBINI, IN R= ITI SATANICI. IN TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEGUONO.. = I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMAZZATI, = FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, POPRIO DALL'= AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI DI RAPALLO E GENO= VA https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI MEGA OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://genova.repubblica.it/cronaca/2011/06/14/news/riti_voodoo_al_cimiter= o_di_staglieno-17668927/ https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO KILLER= , NAZISTA E PEDOFILO, STUPRANTE ED UCCIDENTE BAMBINI SU BAMBINI: DANIELE MI= NOTTI DI RAPALLO E GENOVA! Criminalissimo Studio Cirenei Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE ED ASSASSINO DANIELE MINOTTI ( QUI IN CHIARO SCURO MASSONICO, PER MANDAR= E OVVI MESSAGGI SATANISTI E KILLER https://www.flickr.com/photos/danieleminotti/ https://studiolegalelisi.it/wp-content/uploads/2019/04/Daniele-Minotti.jpg ). A CAPO, ANZI, A KAPO' DI SETTA ASSASSINA DAL NOME ELOQUENTISSIMO! SETTA = ASSASSINA CHIAMATA " AMMAZZIAMO PER NOSTRO SATANA IN TERRA: SILVIO BERLUSCO= NI". E' AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI: DANIELE MINOTTI DI GE= NOVA E RAPALLO. VEDI QUESTO LINK https://www.py.cz/pipermail/python/2017-April/013002.html UNITO IN CIO' AL PARIMENTI AVVOCATO MASSONE, NAZISTA, LADRO, TRUFFATORE, RI= CICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPPOLITO= . ED AI PARIMENTI SATANAZISTI, CORROTTI, MEGA COCAINOMANI E NOTISSIMI PEDOF= ILI MARIO GIORDANO, CLAUDIO CERASA, PAOLO LIGUORI, GIULIANO FERRARA ED ANSE= LMA DEL'OLIO ( " PAZZI MA NON SCEMI", COME AMANO DEFINIRSI). ED ALL'ARRESTA= TO REGISTA CINEMATOGRAFICO PEDERASTA INCULA BAMBINI GIUSEPPE LAZZARI DI BRE= SCIA http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 ( CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, E' PAPPA = E CICCIA CON LA PURE MOLTISSIMO PEDOFILA ANSELMA DELL'OLIO STESSA https://www.imdb.com/title/tt1828287/reviews http://www.sentirsidire.it/su-di-me/ VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO A QUESTO LINK https://www.youtube.com/watch?v=3DDLR-DJJWl_M RIPORTANTE UNA TRASMISSIONE DEL NOIOSISSIMO GIGI MARZULLO, CON LA TROIONA S= TUPRA BAMBINI ANSELMA DELL'OLIO ED IL REGISTA CINEMATOGRAFICO PEDERASTA INC= ULA BAMBINI GIUSEPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLETTUALMENTE,= DIFENDENDO E PRUOMOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULLLALA' CHE C= ASO, LA SCHIFOSAMENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORCO NAZISTA, FIGL= IO DI CANE, DA SEMPRE SUPER PEDERASTA GIULIANO FERRARA, INSIEME AL REGISTA = CINEMATOGRAFICO PEDOFILO STUPRA BAMBINI GIUSEPPE LAZZARI, QUESTO VIDEO, ORA= , DA YOU TUBE, LO HAN FATTO LEVARE... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSC= ATO LE PROVE DI CIO' CHE VINCENTISSIMAMENTE STIAM QUI SCRIVENDO). IL TUTTO = INSIEME ANCHE AL TRE VOLTE FINITO IN GALERA PAOLO BARRAI DI CRIMINALISSIMA = BITCOIN CRYPTOECONOMY, DI CRIMINALISSIMA BITINCUBATOR & VENTURE, DI CRIMINA= LISSIMA CRYPTOPOLYS, CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA EIDOO E CRIMI= NALISSIMO BLOG MERCATO "MERDATO" LIBERO ( NOTO, NON PER NULLA, IN TUTTO IL = GLOBO TERRESTRE, COME "IL PEDOFILO DEL BITCOIN" https://oneway2day.files.wordpress.com/2019/01/4e793-barrai2bind-pag01.jpg https://twitter.com/megliomortiche1 https://pbs.twimg.com/media/CIB3862WcAA8F7c.png http://www.bluerating.com/trading/179-promotori/28601-qmultaq-da-70mila-eur= o-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ). 2 ED INSIEME AL PARIMENTI NOTO PEDOFIL-O-MOSESSUALE CLAUDIO CERASA DI TWITTER= ED IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C.LO S= E SI E' SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOSTRA, CAMORR= A, NDRANGHETA, NAZISMO E NUOVA P2)! E VISTO CHE ABBIAMO CITATO COSA NOSTRA:= RICORDIAMO PLEASE, CHE DETTO PEDERASTA PALERMITANO DI CLAUDIO CERASA E' AF= FILIATO DA ANNI A COSA NOSTRA: FAMIGLIA CIMINNA, MANDAMENTO DI CACCAMO! BUT LETS' GO PER PUNTI, NOW. LET'S GO, PLEASE. IAMM BELL, IA'! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI ( PER QUESTO E' OVVIO TUTT'UNO COL PEDOFI= LO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI https://www.ilfattoquotidiano.it/2014/07/22/fede-la-storia-di-berlusconi-ma= fia-mafia-mafia-sosteneva-famiglia-mangano/1068423/ http://espresso.repubblica.it/inchieste/2018/02/23/news/soldi-che-cadono-da= l-cielo-come-e-nata-la-fininvest-1.318649 https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI ASSASSINI DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTA= PO, DI CARATTERE TECNOLOGICO E MILITARE ( IL TUTTO INISIEME AI MASSONI NAZI= STI, MASSO-NA-ZISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCESCA OCCHIONER= O https://www.repubblica.it/cronaca/2017/01/10/news/cyberspionaggio_occhioner= o_chi_sono_i_due_arrestati-155752442/ https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ https://www.leggo.it/news/italia/l_ingegnere_massone_la_manager_ecco_fratel= li_spiavano_politici_istituzioni-2187281.html https://interestingpress.blogspot.com/2017/01/lingegnere-e-la-maratoneta-la= -rete-di.html https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS..GLI ULTIMI DUE, FINITI IN GATTABUIA, SPERIAMO AL PIU' PR= ESTO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, G= IA' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html http://www.affaritaliani.it/economia/finpart-a-livolsi-tre-anni-per-bancaro= tta030412.html ). =E3=80=80 3 IL TUTTO COME DA ORDINI DI SUO PAPPONE NONCHE' PEDOFILO SPAPPOLA MAGISTRATI= SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA COI BAS= TARDI ASSASSINI ( GIA' FINITI IN GALERA) GAETANO SAYA E RICCARDO SINDOCA, P= OI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) GIULIANO TAVAROLI ED EMA= NUELE CIPRIANI, POI COI BASTARDI ASSASSINI ( GIA' FINITI IN GALERA) ROBERTO= PREATONI, ERNESTO PREATONI E FABIO GHIONI http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html POI COI BASTARDI ASSASSINI (GIA' FINITI IN GALERA) RENATO FARINA, "POMPINAR= O" PIO POMPA, NICOLO' POLLARI E MEGA PEZZO DI MERDA KILLER MARCO MANCINI ( = CHE, MAI DA DIMENTICARE, INTENDEVANO AMMAZZARE CHIUNQUE "OSASSE" ESSERE NON= VERME BERLUSCONICCHIO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OM= ICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI, MALORI, INCIDENTI IL TUTTO LO RISCONTRATE PRESSO QUESTI VINCENTISSIMI LINKS https://www.corriere.it/Primo_Piano/Cronache/2007/06_Giugno/06/biondani_fer= mare_i_pm.html https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 http://www.repubblica.it/2010/01/sezioni/cronaca/segreto-parziale/giudizio-= sismi/giudizio-sismi.html http://www1.adnkronos.com/Archivio/AdnAgenzia/2006/11/09/Politica/SERVIZI-S= EGRETI-LESPRESSO-I-DEPISTAGGI-NELLE-CARTE-DI-POMPA_130505.php http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ http://www.bastaitalia.org/perche-hanno-assassinato-giorgio-panto/ https://www.ilfattoquotidiano.it/2017/01/17/cucchi-aldrovandi-e-gli-altri-a= ssassinati-chiamiamo-le-cose-con-il-loro-nome/3322193/ http://espresso.repubblica.it/attualita/cronaca/2012/09/28/news/cosi-hanno-= ucciso-mastrogiovanni-1.46861 4 E POI ANCORA.. http://www.abystron.org/expo/italia/2010/segreti-di-stato.aspx https://forum.termometropolitico.it/514196-csm-il-sismi-spio-i-magistrati-4= 6.html https://www.hwupgrade.it/forum/archive/index.php/t-2117753.html https://comedonchisciotte.org/pezzi-eversivi-di-uno-stato-a-pezzi/ http://www.pmli.it/sismicolpivanemiciberlusconi.htm https://www.agoravox.it/Documenti-segreti-made-in-Italy.html http://forum.enti.it/viewtopic.php?t=3D66625 http://www.grnet.it/news/news-news/19-segreto-di-stato-sulle-schedature-ill= egali-berlusconi-salva-pollari-a-pompa/ https://attituderagusa.wordpress.com/2010/01/06/servizi-deviati-la-storia-s= i-ripete-ma-adesso-ce-il-segreto-di-stato/ http://ferdinandoimposimato.blogspot.pe/2007/07/il-sismi-gate-il-caso-polla= ri.html http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA SI APPOGG= IA AI NAZI-ST-ALKERS CORROTTI, SATANISTI E PARIMENTI ASSASSINI VITTORIO FEL= TRI, FRANCO BECHIS, PIETRO SENALDI, FAUSTO CARIOTI E MAURIZIO BELPIETRO! TORNIAMO IN OGNI CASO, ORA, ALL'EFFERATO AVVOCATO PEDOFILO E KILLER DANIELE= MINOTTI DI GENOVA E RAPALLO, NOW, PLEASE! SUA LA SETTA DI SATANISTI, ANZI, SUA LA SETTA DI SATA-N-AZISTI STUPRA BAMBI= NI, CON DENTRO IL PARI PEDERASTA GIULIANO FERRARA, IL PARI PEDERASTA CLAUDI= O CERASA ( FIGLIO DI ALTRO NOTO PEDOFILO, IL GIORNALISTA CRIMINALISSIMO GIU= SEPPE CERASA: PENSATE CHE QUESTA COPPIA DI PEDERASTA PADRE E FIGLIO HAN SCR= ITTO LIBRI PER DIFENDERE I NOTI PEDOFILI DI RIGNANO, SI, I PEDOFILI COMPARI= DEL NOTISSIMO PARI "PEDOFILO DI SATANA" GIANFRANCO SCANCARELLO DI CANALE 5 http://www.gay.it/community/forums/topic/il-pedofilo-satanista-e-lautore-di= -buona-domenica-di-maur https://www.cinquantamila.it/storyTellerArticolo.php?storyId=3D000000013493= 7 IN QUESTO, FOTOCOPIA DEL PARI PEDOFILO MAURIZIO COSTANZO E PARI PEDOFILO ^M= AXIMO^: SILVIO BERLUSCONI https://www.independent.co.uk/voices/comment/silvio-berlusconis-latest-appe= al-and-a-string-of-paedophilia-and-rape-rulings-that-shame-italy-9046607.ht= ml https://www.ibtimes.co.uk/silvio-berlusconi-paid-10m-bribes-bunga-bunga-gir= ls-paedophile-prostitution-trial-1508692 )! =E3=80=80 5 NATO A PALERMO, AFFILIATO MAFIOSO, ANZI, "PUNCIUTO MAFIOSO" DA ANNI. PARTE = DELLA FAMIGLIA MAFIOSA MEG-A-SSASSINA DEI CIMINNA, MANDAMENTO DI CACCAMO. E= D E' STATO POSTO IN GOPPA AL FOGLIO, POI, IN QUANTO AMANTE OMOSESSUALE DI G= IULIANO FERRARA. ABBIAMO ANCHE PARECCHIE FOTO A PROPOSITO ( NON PER NIENTE,= IL SATANISTA PEDERASTA GIULIANO FERRARA, CONSIGLIA QUI, IL FARE SESSO RICC= HIONESCO, CONTRO NATURA E PERVERTITO https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ). STESSA COSA PER IL PARI PEDERASTA, GIA' FINITO 3 VOLTE IN GALERA: PAOLO BAR= RAI DI CRIMINALISSIMA CRYPTOLAB, CRIMINALISSIMA BITINCUBATOR, CRIMINALISSIM= A EIDOO, CRIMINALISSIMA CRYPTOPOLIS, CRIMINALISSIMA BLOCKCHAIN INVEST, CRIM= INALISSIMA BIGBIT E BIGBITGOLD, CRIMINALISSIMA WMO SAGL LUGANO, CRIMINALISS= IMA WORLD MAN OPPORTUNITIES LUGANO, CRIMINALISSIMA WMO SA PANAMA, CRIMINALI= SSIMA BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CRIMINALISSIMO BLOG MERCAT= O LIBERO ALIAS "MERDATO" LIBERO (SU CUI TROVATE TUTTO, QUI http://lists.spline.de/pipermail/fli4l_opt/2014-September/000727.html ). ED IL PARI PEDERASTA STEFANO BASSI DI TORINO E DE IL GRANDE BLUFF https://twitter.com/grandebluff https://it-it.facebook.com/stefano.bassi.758 TUTT'UNO CON LA NDRANGHETA E DA DECENNI. CINTURA FRA GLI ASSASSINI CALABRES= I BASATI A TORINO: ADOLFO CREA E ALDO COSIMO CREA http://www.torinotoday.it/cronaca/operazione-big-bang-ndrangheta-torino-arr= esto-adolfo-aldo-cosimo-crea.html ED IL "FORSE GIA' CITATO", BEN NOTO SPAPPOLA MAGISTRATI ED ACCERTATISSIMO P= EDOFILO SILVIO BERLUSCONI. https://www.linkiesta.it/it/article/2013/06/25/napolitano-non-nominare-sena= tore-a-vita-un-pedofilo/14626/ https://it-it.facebook.com/FALCONE-E-BORSELLINO-UCCISI-DA-BERLUSCONI-134602= 469910010/ =E3=80=80 =E3=80=80 6 PER NON PARLARE DEL PARI PEDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIO= SI, SATANISTA PAZZO PAOLO CARDEN=C3=80 https://www.py.cz/pipermail/python/2017-September/013036.html https://twitter.com/LavaPaolo ( IN QUESTA TERRIFICANTE FOTO, CON SUA SATANAZISTISSIMA FACCIA RIPRESA GIUS= TO PRIMA DI UNA MESSA NERA EFFETTUATA A MACERATA, A CUI FECE SEGUITO LO STU= PRO DI SEI BAMBINI, POI UCCISI PROPRIO DALL'ECONOMISTA PEDOFILO ED ASSASSIN= O PAOLO CARDEN=C3=80, QUINDI FATTI A PEZZI ED IMBOSCATI IN TANTI BOSCHI DEL= MACERATESE STESSO https://a.mytrend.it/authors/1385.jpg COME DA COTANTO DI QUESTI ARTICOLI https://www.corriereadriatico.it/marche/marche_ancona_bambini_penelope_kyen= ge_scomparsi-1055541.html https://www.cronachemaceratesi.it/2016/05/24/spariti-nel-nulla-nelle-marche= -si-cercano-558-persone/811406/ ). RESIDENTE A PENNA SAN GIOVANNI (MACERATA), VIA UMBERTO I, NR 41 ( O ANCHE P= EDOFILO INCULA BAMBINI E MEGA RICICLA SOLDI MAFIOSI PAOLO CARDEN=C3=80 RESI= DENTE A FALERONE IN VIA POZZO 105: PENSATE CHE STO BASTARDO ASSASSINO E PED= ERASTA DI PAOLO CARDEN=C3=80 HA DECISO DI ANDARE A VIVERE IN UNA VIA CHE SI= CHIAMA VIA POZZO, PROPRIO "IN MEMORIA" DI TANTI BAMBINI CHE STUPRATO, UCCI= SO E BUTTATO IN POZZI QUA E LA, COME DALLO STESSO DETTO E MOLTE VOLTE). DI = CRIMINALISSIMA CARDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PA= RTNERS DI VIA MONTESSORI 6 E 8 DI FALERONE (FM) - Tel: 0734.710786 E DI CRIMINALISSIMO BLOG VINCITORI E VINTI (CHE OVVIAMENTE SERVE A LAVARE C= ASH ASSASSINO, DI MAFIA, NDRANGHETA E CAMORRA http://www.anconatoday.it/cronaca/gratteri-nicaso-ndrangheta-fiumi-oro-marc= he-ancona.html https://www.cronachemaceratesi.it/2015/05/29/mafia-nelle-marche-nessuno-ne-= parla-la-denuncia-di-ambra-ruggeri-e-negli-appalti-delle-grandi-opere/66207= 1/ https://www.cronachemaceratesi.it/2017/09/07/tonnellate-di-droga-dal-mare-i= -traffici-della-camorra-nelle-marche-e-larresto-di-andrea-reccia/1008382/ ) UNITO IN CIO' AL PARI PEDOFILO STEFANO CARDENA' SEMPRE DI CRIMINALISSIMA CA= RDEN=C3=80 CONSULTING E CRIMINALISSIMA CARDEN=C3=80 AND PARTNERS DI FALERON= E, VIA MONTESSORI 6 ED 8! https://pbs.twimg.com/profile_images/427506611897528320/m6uFCCda.jpeg 7 IL TUTTO PURE UNITISSIMO AL MEGA RICICLA SOLDI DI COSA NOSTRA E NDRANGHETA,= ROCCO TRIPODI DI CRIMINALISSIMA HYPO TIROL BANK PARMA..E DI NAZISTA CASA P= OUND http://it.viadeo.com/it/profile/rocco.tripodi PARTE DELLA NAZIGANG E' IN STRA PIENO IL BASTARDO FASCIORAZZISTA E MEGA RIC= ICLA SOLDI MAFIOSI, GIACOMO ZUCCO DI CRIMINALISSIMA BLOCHAINLAB, CRIMINALIS= SIMA BHB NETWORK, CRIMINALISSIMA BLOCKCHAINLABIT E CRIMINALISSIMA BHB-BLOCK= CHAINLAB (OLTRE CHE PRIMA MENZIONATI KU KLUK KLANISTI, NAZIRAZZISTI TEA PAR= TIES). https://www.youtube.com/channel/UCVDHAgnt5MKt7srlJ38Vn2A TRATTASI DI ALTRO CIUCCIA CAZZI MORTI DI SILVIO BERLUSCONI, CON GRAVISSIMI = PRECEDENTI PENALI ( QUI IN UN PROCESSO A PROPOSITO DI SOLITI BASTARDISSIMI = CRIMINI DEL PEDOFILO SPAPPOLA MAGISTRATI SILVIO BERLUSCONI E SUA DIARREA CR= IMINALISSIMA GUIDO PODESTA' https://www.radioradicale.it/scheda/397502/processo-a-guido-podesta-ed-altr= i-per-falso-ideologico?i=3D271737 ). CHE, PER LO STESSO PEGGIORE CRIMINALE IN CRAVATTA DI TUTTO IL MONDO E DI TU= TTI I TEMPI, SILVIO BERLUSCONI, MEGA RICICLA SOLDI KILLER DI BEN 7 NDRINE B= ASATE NEL MILANESE. FRA CUI LA MEGA SANGUINARIA NDRINA DI SANTO PASQUALE MO= RABITO https://www.ilfattoquotidiano.it/2015/01/06/ndrangheta-milano-grandi-famigl= ie-legate-calabresi/1318389/ . COME DELL'EFFERATO KILLER CAMORRISTA SALVATORE POTENZA! https://milano.repubblica.it/cronaca/2017/04/03/news/camorra_milano_sequest= rato_ristorante_donna_sophia-162086270/ DI STA TOPAIA MALAVITOSA FA PARTE IN STRA PIENO IL VERME CALABRESE TUTT'UNO= CON LA NDRANGHETA, AFFILIATISSIMO A MEGA ASSASSINE NDRINE DI SINGEN ED ENG= EN (D) https://correctiv.org/en/latest-stories/mafia-it/2015/01/29/la-ndrangheta-a= -engen-i-boss-reggini-in-germania-e-svizzera/ E FRAUNFELD (CH), https://www.repubblica.it/cronaca/2014/08/22/news/_ndrangheta_scoperta_cosc= a_in_svizzera_18_fermi_a_frauenfeld_da_40_anni-94273843/ PORCO CRIMINALISSIMO NATALE MASSIMILANO FERRARA O PORCO CRIMINALISSIMA NATA= LE FERRARA CHE SIA, DI GIA' CITATA CRIMINALISSIMA ICO CHIAMATA EIDOO. SCAPP= ATO IN SVIZZERA, IN QUANTO TEMEVA MANETTE DI PM ANTI MAFIA DI TIPO CALABRES= E! https://eidoo.io/company D'ALTRONDE, EIDOO E' UNA ICO DELLA NDRANGHETA, SI, PROPRIO DELLA NDRANGHETA= , QUINDI, E' SEGUITA DAI NDRANGHETISTI ASSASSINI PAOLO BARRAI E NATALE FERR= ARA https://www.rsi.ch/la1/programmi/informazione/falo/Bella-gente-10423994.htm= l https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.linkiesta.it/it/article/2019/04/03/ndrangheta-bitcoin/41655/ =E3=80=80 8 AND THEN AGAIN AND AGAIN AND AGAIN... FAN PARTE DI QUESTA GANG NAZINDRANGHETISTA, IL PARI PEDERASTA MAURIZIO BARB= ERO DI TECHNOSKY MONTESETTEPANI E DI ALBA https://twitter.com/mlnews_com?lang=3Des https://it.linkedin.com/in/maurizio-barbero-a521978 (CHE ERA CIO' CHE UNIVA IL BASTARDO HITLERIANO GIULIO OCCHIONERO AD ENAV, D= I CUI, NON PER NIENTE, TECHNOSKY MONTESETTEPANI, SOCIETA' CONTROLLATA DA SE= RVIZI SEGRETI DI ESTREMA DESTRA SPESSISSIMO ANCHE ASSASSINI, E' IN PIENO, P= ARTE). ED IL NOTO RICICLA SOLDI MAFIOSI, MOSTRUOSO DELINQUENTE MATTEO PARDU DI CRI= MINALISSIMO STUDIO DI COMMERCIALISTI DEL SOLDATO DI LA SPEZIA! https://it.linkedin.com/in/matteo-pardu-90658820 ED ANCORA, DELLA FASCIOMAFIOSA GANG ERA PARTE LA NOTA SATANISTA PEDOFILA EL= ISA COGNO DI CRIMINALISSIMA FONDAZIONE FERRERO E CRIMINALISSIMA FRUIMEX SAS= ALBA E TORINO. https://groups.google.com/forum/#!topic/it.hobby.viaggi/xwbvyifTcHI https://www.instagram.com/p/Bcc0zWonbtv/ E LA NOTA PEDOFILA, TANTO QUANTO, PIERA CLERICO DI FRUIMEX SAS ALBA E TORIN= O ( SUA ZOCCOLISSIMA MADRE https://it.linkedin.com/in/piera-clerico-77793388 https://groups.google.com/forum/#!topic/ocufe1/7h0eFzyS-Z0 ) LE ULTIME DUE, INDAGATISSIME DA VARIE PROCURE PIEMONTESI, IN QUANTO IDEATRI= CI E ORDINANTI TANTI OMICIDI E SPARIZIONI DI MATRICE SATANISTA, AVVENUTI NE= L CUNEENSE http://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-se= tte-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ AND THERE WE GO AGAIN AND AGAIN... DELLA "SATANAZISTA" GANG E' STRA PARTE IL PARI PEDERASTA, SEMPRE AZZERANTE = I RISPAhttps://www.spreaker.com/user/10297125RMI DI TUTTI: FEDERICO IZZI "T= RADER" DETTO "ZIO ROMOLO https://www.spreaker.com/user/10297125 ( CHE SBAGLIA IN BORSA, COME MINIMO, 11 VOLTE SU 10, E CAMPA SOLO E SEMPRE = RICICLANDO CASH ASSASSINO DEI GIRI LERCI DI MAFIA CAPITALE E DI CAMORRISTI = PRESENTI NEL BASSO LAZIO )". 9 PER NON DIRE DEL NOTO PORCO INCULA BAMBINI E MEGA RICICLA CASH MAFIOSO ANDR= EA SCARSI DI CRIMINALISSIMA CFO https://www.linkedin.com/in/andrea-scarsi-67a04a9 FIGLIO DI NOTISSIMO GINECOLOGO SATANISTA E PEDOFILO ALESSANDRO SCARSI DI LA= TINA, CHE AMMAZZAVA BAMBINI SU BAMBINI PER LEVARGLI ORGANI DA VENDERE! E CH= E STUPRAVA E FACEVA ABORTIRE PROSTITUTE MINORENNI ALBANESI A GOGO E CHE PER= TUTTO QUESTO E=E2=80=99 FINITO IN GALERA http://www.telefree.it/news.php?op=3Dview&id=3D2285 PER NON PARLARE DEI PRIMA CITATI=E2=80=A6 NOTA PEDOFILA ANSELMA DEL=E2=80=99OLIO (SPOSATA COL MERDONE NAZISTA, MAFIOS= O, CAMORRISTA, NDRANGHETISTA, PEDOFIL-O-MOSESSUALE SATANISTISSIMO GIULIANO = FERRARA, CHE QUI AMMMETTE LUI STESSO CHE AMA BERE IL SANGUE DI CHI FA AMMAZ= ZARE https://www.nuovaresistenza.org/2013/06/ferrara-horror-berro-il-sangue-di-c= hi-esulta-alla-condanna-di-berlusconi-articolotre-quotidiano-online-indipen= dente-e-di-inchiesta/ SE COSTORO NON SONO TAPPETINI MERDOSI DI DELLO STRAGISTA SPAPPOLA MAGISTRAT= I SILVIO BERLUSCONI... PEDOFILO ASSASSINO PROPRIO COME GIULIANO FERRARA, DA= NIELE MINOTTI, CLAUDIO CERASA, MAURIZIO COSTANZO E GIANFRANCO SCANCARELLO).= ED IL GIA=E2=80=99 ARRESTATO PER AVER STUPRATO BAMBINI DI 11 ANNI, REGISTA= BRESCIANO PEDERASTA PAZZO GIUSEPPE LAZZARI http://milano.repubblica.it/cronaca/2016/08/09/news/pedofilia-145677361/ ( NON PER NIENTE=E2=80=A6 FRA LA PERVERTITA SESSUALE SATANISTA ANSELMA DELL= =E2=80=99OLIO ED IL REGISTA CINEMATOGRAFICO PEDERASTA GIUSEPPE LAZZARI, VI = FURONO MOLTE SLINGUATE "PEDOFILESCO-MEDIATICHE", NEGLI ULTIMI ANNI, TIPO QU= ESTA http://video.corriere.it/sesso-11enne-arrestato-regista-giuseppe-lazzari-l-= intervista-rai/4287e44c-5e41-11e6-bfed-33aa6b5e1635 ) MA ORA=E2=80=A6 COME CANTAVA LA GRANDISSIMA LYNN COLLINS, PRODOTTA DALL=E2= =80=99ANCORA PIU=E2=80=99 GRANDE JAMES BROWN=E2=80=A6 "AGAIN AND AGAIN AND AGAIN"!!! https://www.youtube.com/watch?v=3DwB5KgOXHcxc VI RACCOMANDO TANTISSIMO: NASCONDETE I VOSTRI FIGLI, PLEASE, DA NOTO AVVOCA= TO PEDOFIL-O-MOSESSUALE DANIELE MINOTTI (FACEBOOK)! NOTISSIMO AVVOCATO PEDERASTA INCULA BAMBINI DANIELE MINOTTI DI RAPALLO, GEN= OVA E SANTA MARGHERITA LIGURE, A LEGGERE SUO PALLONARO FACEBOOK ACCOUNT. DA= ANNI ISCRITTO PRESSO GLI ANIMALI PAZZI CHE STUPRANO ADOLESCENTI E BIMBI, O= SSIA I PORCI DEPRAVATISSIMI DI " ORGOGLIO PEDOFILO" http://www.today.it/rassegna/giornata-orgoglio-pedofilo.html PEZZO DI MERDA CHE DA ANNI DIFENDE PEDOFILI COME LUI, CON CUI STUPRA, AMMAZ= ZA, FA A PEZZI E SOTTERRA OVUNQUE, CENTINAIA E CENTINAIA DI NEONATI, BAMBIN= I ED ADOLESCENTI https://www.ilsecoloxix.it/genova/2008/08/14/news/la-badante-sgozzata-denun= cio-uno-stupro-1.33388756 http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 ( E SE GOOGLATE DANIELE MINOTTI IN GENERALE, VEDRETE CHE IN TUTTI I SUOI AR= TICOLI, SOTTILISSIMAMENTE, E PURE MANCO TANTO SOTTILISSIMAMENTE, LO STESSO = SEMPRE DIFENDE I PEDOFILI, OVVIO, E' LUI UN VERME ASSASSINO E SODOMIZZA BAM= BINI, IN PRIMIS E STRA PRIMIS ECCO TRE ESEMPINI SU COME IL VERME PEDOFILO DANIELE MINOTTI AMI INCULARE A = MORTE I BAMBINI, PER POI UCCIDERLI E SOTTERRARLI IN BOSCHI PIEMONTESI E LIG= URI, QUI https://www.punto-informatico.it/sed-lex-quando-il-ministro-viola-la-legge/ https://it.diritto.internet.narkive.com/8omMHg7U/pedopornofobia-che-nervi http://www.minotti.net/2007/06/18/quel-sito-oscurato/ )!! 10 E' SUA LA SETTA DI SATANISTI STUPRA ED AMMAZZA BIMBI CON DENTRO IL REGISTA,= ACCLARATISSIMAMENTE PEDOFILO, GIUSEPPE LAZZARI (ARRESTATO) http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 LA NOTA PEDOFILA TANTO QUANTO, ANSELMA DELL'OLIO ( CHE, COME AVETE VISTO E = RI VEDRETE IN UN VIDEO QUI A SEGUITO, COME DA' DEL GENIO, DA' DEL FENOMENO,= DI CONTINUO, AL SUO COMPARE DI ORGE SODOMIZZA RAGAZZINI: GIUSEPPE LAZZARI Sentirsidire...un Film fenomeno, da vedere [Anselma Dell'Olio] https://www.youtube.com/watch?v=3DDLR-DJJWl_M ). ED IL, NOTORIAMENTE, DA SEMPRE PEDOFIL-O-MOSESSUALE GIULIANO FERRARA ( CHE = CONSIGLIA A TUTTI DI DIVENIRE RICCHIONI PEDERASTA COME SE STESSO, QUI, CHE = SCHIFO E CHE STRA VOMITO: https://www.blitzquotidiano.it/politica-italiana/giuliano-ferrara-omosessua= lita-giochetto-consiglio-contro-natura-1483446/ ) ! PER FINIRE: SICCOME ALLA CENSURA ASSASSINA ED AL MALE DI STI ASSASSINI FASC= IOPEDERASTA BERLUSCONICCHI NON CI ADATTEREMO MAI E POI MAI, PIUTTOSTO, MEGL= IO MORTI, E DA SUBITO ( L'ITALIA, ANZI LA MERDASSASINA DI BERLUSCONIA O REN= ZUSCONIA O SALVINUSCONIA CHE SIA, E' AL 77MO POSTO, RIPETO, E' AL SETTANTES= IMO POSTO IN LIBERTA' DI STAMPA, A LIVELLO MONDIALE... DIETRO A DITTATURE M= EGA KILLER AFRICANE, ASIATICHE E LATINO AMERICANE, E DETTO QUESTO... http:/= /www.lastampa.it/2016/04/20/esteri/libert-di-stampa-litalia-crolla-ora-al-p= osto-jl0lw7T7ev7j31hRKIpCwJ/pagina.html ). A VOI ORA IL TESTO PRIMA CITATO = DI UN IMMIGRATO RUMENO, STEFAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGU= E, ALLORCHE' POCO PIU' CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO= , NONCHE' VERMINOSO PEDOFILO DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA = ( I POSTS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATT= I TUTTI CANCELLARE DALL'ASSASSINO NAZISTA MAFIOSO PEDOFILO DANIELE MINOTTI.= .. OVVIO, HA LA COSCIENZA LERCIA, SE LA FA SOTTO A PROPOSITO CHE LA SUA PER= VERTITISSIMA PEDERASTA ED OMICIDA REALTA' POSSA VENIRE A GALLA..LA FAREMO V= ENIRE E STRA VENIRE A GALLA NOI.. MEGLIO MORTI CHE ARRESI Y DE STRA VERDAAA= D!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN CHE A PROPOSIT= O DI TUTTO QUESTO, HA POSTO IN ESSERE ANCHE QUESTO FANTASTICO TWITTER ACCOU= NT https://twitter.com/APederasta ). GUARDATE DA VOI STESSI, PLEASE, CHE PE= DOFILO ASSASSINO E SATANAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI DAN= IELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE NEONATI, BAMB= INI ED ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI = MEZZA ITALIA, OPS SORRY, INTENDEVO DIRE SUA "ME.DAFASCIOMAFIOSA DI BERLUSCO= NIA") !!!!!!!!!!! https://www.py.cz/pipermail/python/2018-February/013212.html 11 Ciao tuti e scusate de mio italiano. Io sono rumeno e non me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni. E bene, nel 2009, lo avvocato di giri nazifascisti misti= a Cosa Nostra, Camorra, Ndrangheta, Daniele Minotti di Rapallo e Genova, m= i diede tre grammi di cocaina da vendere misti a qualcosa che te fa perdere= sensi... mi fece svenire apposta e mentre ero mas di morto che vivo, me so= domizzo'. Vi era anche pancione pieno di merda, pedofilissimo Giuliano Ferr= ara de Il Foglio a guardare, ridere, cercare de masturbarse invano esendo n= oto impotente da sempre. Vi era anche il banchero pure immensamente pedofil= o Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi Banca Carim Rimini= ). E sua moglie, nota prostituta, tante quanto schifosamente pedofila Raffa= ella Vaccari, sempre de Rimini. Il filio de putana avvocato Daniele Minotti= , criminalissimo avvocato di Rapallo e Genova me sodomizzo' insieme ad altr= i sei di suoi giri fascisti e mafiosi. Ho anche prove di tuto questo. Io, o= ra, Stefan Cumescu di Genova, quartiere Caruggi, facio il muratore, basta d= roga, basta prostituirsi (como doveti de fare a seguito di questo stupro, p= er poter rimanere vivo, per non venire amazato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini de avvocato Daniele Minot= ti). Guadanio un decimo di quanto guadaniavo prima e lavoro il triplo di qu= anto prima. Ma preferisco di questo, sento la mia vita uno poco di maggiore= securo. Ma avvocato di Hitler, Vallanzasca e Satana, avvocato filio de put= ana di Silvio Berlusconi e Giuliano Ferrara, nazista e mafioso pederasta Da= niele Minotti di Genova e Rapallo, davvero fa parte di setta di maniaci ses= suali omosessuali molto pericolosi. Ciao. Stefan. Posti Scripto (scusate pe mio italiano picolino e latino ancora mas picolin= o) Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= depravatissime fate da incula bambini Daniele Minotti con Don Riccardo Sep= pia, ma ora non vedo tanto di piu' in giro de lo steso testo. Alora sai cos= a facio? Di mia iniciativa facio cut and copy e provo di riproporlo io da t= ute parti e pe tuta mi vita. Ciao da Stefan e ri scusa di mio italiano ... = ma presto volio di fare corsi di sera di miliorarlo. Ciao. Stefan Cumescu, = sodomizate quasi a morte da pedofilo assasino Daniele Minotti de Rapallo et= Genova. From newsfish@newsfish Thu Aug 1 00:46:11 2024 X-Received: by 2002:ac8:6f06:: with SMTP id g6mr1190516qtv.360.1612863059308; Tue, 09 Feb 2021 01:30:59 -0800 (PST) X-Received: by 2002:a25:670b:: with SMTP id b11mr20410106ybc.274.1612863059059; Tue, 09 Feb 2021 01:30:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 9 Feb 2021 01:30:58 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=212.88.255.210; posting-account=0u-_QgoAAABVd19iXB71E2R2Sl8DPf16 NNTP-Posting-Host: 212.88.255.210 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: IL LEGHISTA KILLER E PEDERASTA INCULA ED AMMAZZA BAMBINI, PAOLO BARRAI (NOTO IN TUTTO IL MONDO COME IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI MILANO, PROCURA DI LUGANO, SCOTLAND YARD LONDRA E POLICIA CIVIL DI PORTO SEGURO (BRASILE). From: Andreas Nigg Bank J Safra Sarasin Zurich Injection-Date: Tue, 09 Feb 2021 09:30:59 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 182 Xref: reader02.eternal-september.org comp.lang.vhdl:9814 IL TUTTO VIA INTERPOL ED EUROPOL! 1 =C3=89 DAVVERO PEDOFILO ED ASSASSINO: PAOLO BARRAI DI CRIMINALE TERRA BITCO= IN! IL CRIMINALE LEGHISTA LUCA SOSTEGNI, INCARCERATO, SCAPPAVA IN CITATA PO= RTO SEGURO (BR), DOVE L'OMICIDA PAOLO BARRAI HA RICICLATO PARTE DEI 49 MLN = =E2=82=AC RUBATI DA LEGA LADRONA! (ECCONE LE PROVE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 ) =C3=89 TRUFFATORE, PEDOFILO E KILLER: PAOLO BARRAI, NATO A MILANO IL 28.6.1= 965 ( O TRUFFATORE, PEDOFILO E KILLER: PAOLO PIETRO BARRAI, NATO A MILANO I= L 28.6.1965). DI CRIMINALE TERRA BITCOIN (ASSOCIAZIONE CON INTENTO DI FOTTE= RE, FREGARE, SPENNARE POLLI VIA INTERNET, IL TUTTO VIA TELEGRAM) E CRIMINAL= ISSIMO BLOG MERCATO LIBERO, ALIAS "MERDATO" LIBERO! INDAGATO, AL MOMENTO, D= ALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD= LONDRA E DA FBI NEW YORK. HA RICICLATO 21 MLN ASSASSINI DI NDRANGHETA, IN FALLENTISSIMA ICO EIDOO (IN= SIEME AL MALAVITOSO NATALE FERRARA DI REGGIO CALABRIA, DA DECENNI PUNCIUTO,= OSSIA AFFILIATO UFFICIALMENTE ALLA NDRANGHETA, INSIEME AL MALAVITOSO PAOLO= CARDEN=C3=81 DI FREGA SOLDI BLOG VINCITORI E VINTI, INSIEME AL MALAVITOSO = STEFANO BASSI DI FREGA SOLDI BLOG IL GRANDE BLUFF, INSIEME AL MALAVITOSO FE= DERICO IZZI, NOTO COME "ER ZIOROMOLO DELLA CAMORRA", LI VEDETE TUTTI IN FOT= O QUI https://3.bp.blogspot.com/-6WRXJQbHe08/WSBR0uTrMLI/AAAAAAAAY2g/L8c3w9= GGr3wpG7yWxBBeOohzhWa7iJ7uQCLcB/s1600/18558610_10156258698827281_4591948382= 498991167_o.jpg ) 2 CHECK EVERY DETAIL BOUT IT, HERE AVETE MIGLIA DI DETTAGLI E PROVE QUI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit 3 IL PEDERASTA OMICIDA PAOLO BARRAI =C3=89 ANCHE DI UNO DEI PRINICIPALI CRIMI= NALI UNENTI NDRANGHETA E MASSONERIA. =C3=89 DA SEMPRE UN CAPO SANTISTA (OSS= IA NDRANGHETISTA MASSONE). INFATTI ERA PAPPA E CICCIA CON L'ARRESTATO MASSO= NE NDRANGHETISTA BERLUSCONICCHIO GIANCARLO PITTELLI (http://www.iacchite.bl= og/giancarlo-pittelli-laffarista-massone-dei-boss-della-ndrangheta/ ). ED E= RA CICCIA E PAPPA PURE CON GRAN PARTE DEI 334 MASSONI NDRANGHETISTI ARRESTA= TI DAL GRANDE PM NICOLA GRATTERI NEL DICEMBRE 2019 ( https://www.ilprimaton= azionale.it/cronaca/ndrangheta-334-arresti-onorevoli-massoni-colonnello-cos= che-140387/ ). MI PRESENTO. SONO IL RIVOLUZIONARIO A FINI DI BENE: ANDREAS NIGG , VICE PRESIDENT AND HE= AD OF ASSET MANAGEMENT. PRESSO SAFRA-SARASIN BANK ZURICH PRIMA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK VONTOBEL ZURI= CH. https://citywireselector.com/manager/andreas-nigg/d2395 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTER = BANK ZURICH DEL MASSONE LEGHISTA E NAZISTA CARLO PESENTI (NOTO PARTNER OMOS= ESSUALE DEL SATANISTA MASSONE FEDERICO TRABUCCO DI KAIROS). ED IO IN PERSON= A, ANDREAS NIGG, ORDINAI SUBITO DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI = A STA BESTIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL= 28.6.1965. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA, CAMORRA, PEDOFI= LO STRAGISTA SILVIO BERLUSCONI, LESBICA PEDOFILA ASSASSINA MARINA BERLUSCON= I E 49 MILIONI DI =E2=82=AC RUBATI DA LEGA LADRONA? DA LONTANO 3.000 KM (NO= N SONO ANTI OMOSESSUALI O LESBICHE, mA ODIO L'IPOICRISIA E LA MAFIOSA OMERT= =C3=81 CHE DA SEMPRE REGNA IN ITALIA, LA MIA RIVOLUZIONE, LA RIVOLUZIONE DI= ANDREAS NIGG DI BANK SAFRA SARASIN ZURICH, RADER=C3=81 A ZERO STA BERLUSCO= NICCHIA IPOCRISIA ED OMERT=C3=81 PUZZOLENTE, ALLA BASE DI OGNI MALE, NEL PA= ESE DEL GRANDE SANDRO PERTINI)! E NON SCORDIAMO CHE IL LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN B= ORSA, AZZERANTE I RISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI =C3=89 PURE UN N= AZI-ST-ALKER VIA INTERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TOR= TURATORE OMICIDA! OLTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( I= N UN PRIMO CASO, A SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN= CITIBANK, COME DA FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/= repubblica/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-ter= enzio-sotto-torchio.html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ HA FATTO 66 (DI PROPOSITO NUMERO SATANICO) FILM PORNO CON CAVALLI E BAMBINI= , BEVENDO SPERMA EQUINO ED INCULANDO A SANGUE BAMBINI SU BAMBINI https://groups.google.com/g/comp.lang.python/c/aRdLu8PIHXg 4 =C3=89 STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 EURO, PER = MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.bluerating.co= m/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-che-ha-vio= lato-gli-obblighi-informativi SNIFFAVA CHILI DI COCAINA E STUPRAVA RAGAZZINE COL SERIAL RAPIST ALBERTO GE= NOVESE (ENTRAMBI SON PARTI DI CRIMINALISSIMA LOGGIA DEL DRAGO DEL PEDOFILO = SPAPPOLA MAGISTRATI SILVIO BERLUSCONI) https://www.fanpage.it/milano/story/alberto-genovese-arrestato/ https://www.ilfattoquotidiano.it/2021/01/26/alberto-genovese-dichiarava-red= diti-da-dipendente-proseguono-gli-accertamenti-fiscali-su-imprenditore-accu= sato-di-stupro/6078470/ EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html Vada costui a a riciclare soldi mafiosi o rubati da Lega Ladrona, dal figli= o di troiaccia criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato L= ugano, dal figlio di troiaccia criminalissimo Daniele Albisetti di Banca de= llo Stato Lugano, dal figlio di troiaccia criminalissimo Claudio Genasci di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Patrick L= afranchi di Banca dello Stato Lugano, dal figlio di troiaccia criminalissim= o Gabriele Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! Per finire ribadisco Quando come Vontobel Bank Zurich, abbiamo comprato Finter Bank Zurich, dai = massoni leghisti e nazifascisti Pesenti, immediatamente abbiamo chiuso tutt= i i conti connessi, al, tanto quanto, massone leghista nazifascista, nonche= ' famoso ladro, truffatore, azzera risparmi di ognuno che gli abbocca via i= nternet e non solo, nonch=C3=A9 pedofilo Paolo Pietro Barrai ( che venne ca= cciato da Citibank, a fine anni 90, per terrificanti frodi che li effettuav= a, come da finale di questo articolo https://ricerca.repubblica.it/repubbli= ca/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-so= tto-torchio.html il grande banchiere Giulio Di Cerbo licenzio' in tronco il= verme criminalissimo Paolo Barrai e lo fece condannare al carcere, pochi a= nni dopo, il bastardo nazista e ndranghetista killer Paolo Barrai fece amma= zzare Giulio Di Cerbo, facendo fintamente apparire il tutto come morte natu= rale... il tutto via Massonerie Fasciste e Servizi Segreti Fascisti a cui i= l pedofilo assassino Paolo Pietro Barrai =C3=A9 connessissimo). Di delinque= ntissima Medicalchain, di delinquentissima Cryptolab S A, di delinquentissi= ma Bigbit, di delinquentissima Bitcoin Cryptoeconomy, di delinquentissima B= itincubator & Venture, di delinquentissima Bgbit News Channel e delinquenti= ssima Terra Bitcoin. Attraverso i quali strumenti, lui ed il fallitissimo, = idiota, davvero incapace e fallimentare trader Federico Izzi di Roma (che c= ampa, di fatto, riciclando soldi mafiosi e facendo film pedopornofrafici, t= anto e' vero che sta merda criminale di Federico Izzi di Roma, e' noto sull= e rivere del Tevere, da chiunque, come "Er Zio Romolo incula bambini" e pur= e come "Er Zio Romolo della Camorra") spennano " i polli del web=C2=A8, ven= dendo loro abbonamenti annuali su criptovalute e non solo, totalmente falli= mentari! A fra non molto via altri miei miliardi di scritti che preparer=C3=B3! ANDREAS NIGG. SAFRA-SARASIN BANK ZURICH. From newsfish@newsfish Thu Aug 1 00:46:12 2024 X-Received: by 2002:a0c:b2d3:: with SMTP id d19mr8930946qvf.21.1613258441802; Sat, 13 Feb 2021 15:20:41 -0800 (PST) X-Received: by 2002:a25:9383:: with SMTP id a3mr13051786ybm.215.1613258441561; Sat, 13 Feb 2021 15:20:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Feb 2021 15:20:41 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=84.198.244.196; posting-account=zOs1jwoAAAA1_l85uThj5P9phTRPQSXe NNTP-Posting-Host: 84.198.244.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4a0008ee-b842-4bd7-8556-a26e82e6d05dn@googlegroups.com> Subject: =?UTF-8?Q?=C3=89_DAVVERO_DA_ARRESTARE_L=27AVVOCATO_PEDOFILO_ED_ASSAS?= =?UTF-8?Q?SINO_DANIELE_MINOTTI_DI_CRIMINALE_STUDIO_LEGALE_LISI=21=21=21?= From: PEDOFILO SATANISTASSASSINO DANIELE MINOTTI Injection-Date: Sat, 13 Feb 2021 23:20:41 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 232 Xref: reader02.eternal-september.org comp.lang.vhdl:9815 =C3=89 DAVVERO DA ARRESTARE L'AVVOCATO PEDOFILO ED ASSASSINO DANIELE MINOTT= I DI CRIMINALE STUDIO LEGALE LISI. L'AVVOCATO SATANISTA, NAZISTA, SATA=E5= =8D=90NAZISTA, PEDERASTA, OMICIDA DANIELE MINOTTI DI RAPALLO E GENOVA: RAPI= SCE, INCULA, UCCIDE TANTI BAMBINI, ANCHE PER VENDERNE GLI ORGANI COME DA QUESTA ABERRANTISSIMA FOTO https://steemitimages.com/p/3auKdN6FdQE37hxp1zh1p7U4iqfKLDE9AdpKRQpQV5g36Go= ZLfg7ABa1V4fE2z?format=3Dmatch&mode=3Dfit&width=3D640 1 =C3=89 DI PERICOLO PUBBLICO ENORME, L'AVV ASSASSINO E PEDERASTA DANIELE MIN= OTTI DI RAPALLO E GENOVA: IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIEL= E MINOTTI!!! AVVOCATO MALAVITOSO, STUPRANTE INFANTI ED ADOLESCENTI, COME PU= RE OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E= MILANO E DI CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDIO LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI= MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PI=C3= =9A DI SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVER= O)! =C3=89 STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA E= D UCCIDE I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO DANIELE MINOTTI! QUESTO = AVVOCATO SATANISTA, NAZISTA, SATA=E5=8D=90NAZISTA, DEPRAVATO, KILLER, DI RA= PALLO E GENOVA (LO VEDETE A SINISTRA, SOPRA SCRITTA ECOMMERCE https://i.yti= mg.com/vi/LDoNHVqzee8/maxresdefault.jpg) RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI: PIERSILVIO BERLUSCONI! SI, SI =C3=89 PROPRIO CO= S=C3=8D: =C3=89 DA ARRESTARE SUBITO L'AVVOCATO SATANISTA, NAZISTA, SATA=E5= =8D=90NAZISTA, PEDOFILO ED OMICIDA DANIELE MINOTTI DI GENOVA E RAPALLO! ASS= ASSINO MASSONE, LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORISTA DI ESTR= EMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, AIZZANTE = TANTI SUICIDI CON STILE TIPICO DA AGENTE SEGRETO IN COPERTO DI TIPO STRAGIS= TA E SVASTICATO! https://www.py.cz/pipermail/python/2017-March/012979.html OGNI SETTIMANA SGOZZA OLTRE CHE CANI, GATTI E SERPENTI, TANTI BAMBINI, IN R= ITI SATANICI. IN TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEGUONO.. = I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMAZZATI, = FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, PROPRIO DALL= 'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI DI RAPALLO E GEN= OVA https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI MEGA OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://genova.repubblica.it/cronaca/2011/06/14/news/riti_voodoo_al_cimiter= o_di_staglieno-17668927/ https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO KILLER= , SATA=E5=8D=90NAZISTA E PEDOFILO, STUPRANTE ED UCCIDENTE BAMBINI SU BAMBIN= I: DANIELE MINOTTI DI RAPALLO E GENOVA! Criminalissimo Studio Cirenei Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE E KILLER DANIELE MINOTTI (QUI IN CHIARO SCURO MASSONICO, PER MANDARE OVV= I MESSAGGI MASSONICO:SATANISTI https://i.pinimg.com/280x280_RS/6d/04/4f/6d0= 44f51fa89a71606e662cbb3346b7f.jpg ). A CAPO, ANZI, A KAP=C3=93 DI UNA SETTA= ASSASSINA DAL NOME ELOQUENTISSIMO : " AMMAZZIAMO PER NOSTRO SATANA IN TERR= A: SILVIO BERLUSCONI". =C3=89 AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI:= DANIELE MINOTTI DI GENOVA E RAPALLO. 2 UNITO IN CI=C3=93 AL PARIMENTI AVVOCATO MASSONE, FASCISTA, LADRO, TRUFFATOR= E, RICICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPP= OLITO. ED INSIEME AL VERME SATA=E5=8D=90NAZISTA E MEGA COCAINOMANE MARIO GI= ORDANO (FOTO ELOQUENTISSIMA A PROPOSITO https://pbs.twimg.com/media/EDH0lay= WsAEw_NO?format=3Djpg&name=3Dsmall ). ED INSIEME AL MAFIOSO AFFILIATO A COS= A NOSTRA CLAUDIO CERASA, FRA L'ALTRO PURE NOTO PEDOFILO (AFFILIATO MAFIOSO = CLAUDIO CERASA: PUNCIUTO PRESSO FAMIGLIA MEGA ASSASSINA CIMINNA, MANDAMENTO= DI CACCAMO). ED INSIEME AL PRIMA TERRORISTA DI SINISTRA, POI TERRORISTA DI= DESTRA PAOLO LIGUORI. ED INSIEME AL NOTO OMOSESSUALE PEDERASTA CHE PAGA DA= DECENNI RAGAZZINI AFFINCH=C3=89 LO INCULINO: GIULIANO FERRARA! ED INSIEME = ALLA NOTISSIMA PEDOFILA ANSELMA DEL'OLIO ( TUTTI " PAZZI MA NON SCEMI", COM= E AMANO DEFINIRSI). E PURE INSIEME AL GI=C3=81 ARRESTATO PEDOFILO GIUSEPPE LAZZARI: REGISTA CIN= EMATOGRAFICO DROGA, INCULA ED AMMAZZA BAMBINI DI BRESCIA ( REGISTA CINEMATOGRAFICO SUPER COCAINOMANE E PEDERASTA GIUSEPPE LAZZARI DI= BRESCIA http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, =C3=89 PAPP= A E CICCIA CON LA MASSONA PEDOFILA ANSELMA DELL'OLIO https://www.imdb.com/title/tt1828287/reviews VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO GUARDABILE A QUESTO LINK https://www.youtube.com/watch?v=3DDLR-DJJWl_M RIPORTANTE UNA TRASMISSIONE DEL NOIOSO GIGI MARZULLO, CON LA PEDOFILA SATAN= ISTA, BERLUSCONICCHIA E DEPRAVATA ANSELMA DELL'OLIO ED IL REGISTA CINEMATOG= RAFICO STUPRA BAMBINI GIUSEPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLET= TUALMENTE, DIFENDENDO E PRUOMUOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULL= LAL=C3=81 CHE CASO, LA SCHIFOSAMENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORC= O NAZISTA, FIGLIO DI CANE, DA SEMPRE PEDOFILISSIMO GIULIANO FERRARA, INSIEM= E AL REGISTA IN QUESTIONE, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN RESO NON = PI=C3=9A PUBBLICO... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI C= IO' CHE VINCENTISSIMAMENTE SCRIVIAMO). IL TUTTO INSIEME AL NOTO ASSASSINO E PARI PEDOFILO PAOLO BARRAI DI CRIMINAL= ISSIMA TERRABITCOIN https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.rsi.ch/la1/programmi/informazione/falo/tutti-i-servizi/Bella-ge= nte-10474214.html IL TUTTO, POI, PURE INSIEME AL PARIMENTI, PRIMA CITATO, PEDERASTA CLAUDIO C= ERASA DE IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C= ULO, SE SI =C3=89 SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOST= RA, CAMORRA, NDRANGHETA, NAZISMO E P2/P3/P4/P999..999 PNUGLASORRT)! BUT LETS' GO PER PUNTI, PLEASE. IAMM BELL, I=C3=81! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI (PER QUESTO =C3=89 OVVIO TUTT'UNO COL PED= OFILO MACELLA MAGISTRATI SILVIO BERLUSCONI, SUO PEZZO DI MERDA NAZISTA FIGL= IO PIERSILVIO BERLUSCONI https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ E SUA FIGLIA, MANDANTE DI OMICIDI E LESBICA DEPRAVATA MARINA B= ERLUSCONI https://groups.google.com/g/pt.rec.desporto.futebol/c/VdkasMcS6FQ= ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI KILLER DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTAPO,= DI CARATTERE TECNOLOGICO E MILITARE. IL TUTTO CON REGIA DEI BANCHIERI MEGA= RICICLA SOLDI MAFIOSI ENNIO DORIS E MASSIMO DORIS DI BANCA MEDIOLANUM, COM= E PURE DEI MASSONI NAZIFASCISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCES= CA OCCHIONERO https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ 3 IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS. GLI ULTIMI 2, FINITI IN GATTABUIA, SPERIAMO AL PIU' PRES= TO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, GIA= ' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html KAP=C3=93 DI TUTTO QUESTO, =C3=89 OVVIAMENTE IL MACELLA MAGISTRATI E PEDOFI= LO SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA VIA B= ASTARDI ASSASSINI ARRESTATI GAETANO SAYA E RICCARDO SINDOCA, POI VIA BASTAR= DI ASSASSINI ARRESTATI GIULIANO TAVAROLI ED EMANUELE CIPRIANI, POI VIA BAST= ARDI ASSASSINI ARRESTATI LEO ZAGAMI E PAOLO BARRAI, POI VIA BASTARDI ASSASS= INI ARRESTATI GIOELE MAGALDI E GIANFRANCO PECORARO ALIAS GIOVANNI FRANCESCO= CARPEORO, POI VIA BASTARDI ASSASSINI ARRESTATI ROBERTO PREATONI, ERNESTO P= REATONI E FABIO GHIONI POI VIA BASTARDI ASSASSINI ARRESTATI RENATO FARINA, "POMPINARO" PIO POMPA, = NICOL=C3=93 POLLARI E VERMINOSO KILLER MARCO MANCINI ( QUESTI ULTIMI, CHE, = NEVER FORGET, INTENDEVANO AMMAZZARE, FRA 2001 E 2006, CHIUNQUE "OSASSE" ESS= ERE NON TOPO DI FOGNA BERLUSCONICCHIO COME LORO, VIA "DISARTICOLAZIONI DI T= IPO TRAUMATICO", OSSIA OMICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI= , MALORI, INCIDENTI VEDI QUESTI VINCENTISSIMI LINKS http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l http://www.pmli.it/sismicolpivanemiciberlusconi.htm ). MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA DI DANIEL= E MINOTTI, SI APPOGGIA AI NAZI=E5=8D=90STALKERS CORROTTI, MASSONI SATANISTI= E PARIMENTI ASSASSINI VITTORIO FELTRI, FRANCO BECHIS, PIETRO SENALDI, FAUS= TO CARIOTI E MAURIZIO BELPIETRO! AVVOCATO FIGLIO DI PUTTANA ASSASSINO E PEDOFILO DANIELE MINOTTI DI RAPALLO = E GENOVA, CHE, NON PER NIENTE, DIFENDE PEDOFILI KILLERS COME LUI, A MAN BAS= SA ( FRA TOPI DI FOGNA SANGUINARI E PERVERTITI CI SI CAPISCE) ECCONE PROVE A TONNELLATE https://www.ilsecoloxix.it/genova/2008/08/14/news/la-badante-sgozzata-denun= cio-uno-stupro-1.33388756 http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 TROVATE QUALSIASI ALTRA INFORMAZIONE SUL MASSONE NAZISTA, SUL SATANISTA NAZ= ISTA, SUL SATA=E5=8D=90NAZISTA, PEDOFILO, PEDERASTA, ASSASSINO DANIELE MINO= TTI DI RAPALLO E GENOVA, QUI: https://www.py.cz/pipermail/python/2017-April/013002.html 4 PER CONCLUDERE, A VOI ORA IL TESTO PRIMA CITATO DI UN IMMIGRATO RUMENO, STE= FAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGUE, ALLORCH=C3=89 POCO PIU' = CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO, NONCHE' PEDOFILO INCU= LA ED AMMAZZA BAMBINI DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA ( I POS= TS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATTI TUTTI= CANCELLARE DALL'ASSASSINO DANIELE MINOTTI... OVVIO, HA LA COSCIENZA LERCIA= , SE LA FA SOTTO A PROPOSITO CHE LA SUA PERVERTITA PEDERASTA ED OMICIDA REA= LT=C3=81 VENGA A GALLA..LA FAREMO VENIRE E STRA VENIRE A GALLA NOI.. MEGLIO= MORTI CHE ARRESI Y DE VERDAD!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN, CHE A PROPOSI= TO DI TUTTO QUESTO, NE SCRIVE EROICAMANTE QUI https://www.py.cz/pipermail/p= ython/2017-April/013002.html ). GUARDATE DA VOI STESSI, PLEASE, CHE PEDOFIL= O ASSASSINO E SATA=E5=8D=90NAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI= DANIELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE BAMBINI E= D ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI MEZZA= ITALIA, OPPURE PER SQUARTARE GLI STESSI ALLO SCOPO DI VENDERNE GLI ORGANI https://steemitimages.com/p/3auKdN6FdQE37hxp1zh1p7U4iqfKLDE9AdpKRQpQV5g36Go= ZLfg7ABa1V4fE2z?format=3Dmatch&mode=3Dfit&width=3D640)! Ciao tuti e scusate de mio italiano. Io sono rumeno e nun me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni e lo criminale Daniele Minotti me faceva vendere tanta co= caina per lui, dicendomi "sei minorenne, non te possono far niente". Ebbene= , nel 2009, l'avvocato di giri nazisti misti a Cosa Nostra, Camorra, Ndrang= heta, Daniele Minotti di Rapallo e Genova, mi fece bere qualcosa, con dentr= o ovvia droga che te fa perdere sensi... mi fece svenire apposta e mentre e= ro mas morto che vivo, me sodomizzo'. Vi era anche pancione pieno di merda,= pedofilo Giuliano Ferrara de Il Foglio a guardare, ridere, cercare de mast= urbarse invano esendo noto impotente da sempre. Vi era anche el banchero im= mensamente pedofilo Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi = Banca Carim Rimini). E sua moglie, nota prostituta, sempre in club scambist= i a prendere cazzi in culo a raffica, tanto quanto satanista e pedofila Raf= faella Vaccari, sempre de Rimini (li vedete qui http://chiamamicitta.it/wp-= content/uploads/2016/10/gabri-e-raffa.jpg). Il figlio di puttana avvocato D= aniele Minotti, criminalissimo avvocato di Rapallo e Genova me sodomizz=C3= =B3 insieme ad altri di suoi giri fascisti e mafiosi. Ho anche prove di tut= to questo. Io, ora, Stefan Cumescu di Genova, facio il muratore, basta drog= a, basta prostituirsi (como dovetti de fare a seguito di questo stupro, per= poter rimanere vivo, per non venire ammazzato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini e spacciatore di cocaina = di avvocato Daniele Minotti). Guadanio un decimo di quanto guadaniavo prima= e lavoro il triplo di quanto prima. Ma preferisco ci=C3=B3, sento la mia v= ita uno poco di maggiore securo. Ma avvocato di Hitler, Vallanzasca e Satan= a, avvocato filio de putana di pedofilo assassino Silvio Berlusconi e Giuli= ano Ferrara, il massone nazista, assassino e pederasta Daniele Minotti di G= enova e Rapallo, davvero fa parte di setta di maniaci sessuali omosessuali = killer. Ciao. Stefan Cumescu. PS Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= omosessuali pedofilesche fate da incula bambini Daniele Minotti con Don Ri= ccardo Seppia, ma ora non vedo tanto di piu' in giro, lo steso testo. Alora= sai cosa facio? Prover=C3=B3 a rintracciarlo e riproporlo io, da tute part= i e pe tuta mi vita. From newsfish@newsfish Thu Aug 1 00:46:12 2024 X-Received: by 2002:a37:4589:: with SMTP id s131mr9042902qka.269.1613258547764; Sat, 13 Feb 2021 15:22:27 -0800 (PST) X-Received: by 2002:a25:670b:: with SMTP id b11mr13847306ybc.274.1613258547504; Sat, 13 Feb 2021 15:22:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Feb 2021 15:22:27 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=84.198.244.196; posting-account=zOs1jwoAAAA1_l85uThj5P9phTRPQSXe NNTP-Posting-Host: 84.198.244.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e571371-db53-4227-8ac9-55590e5e310an@googlegroups.com> Subject: =?UTF-8?Q?=C3=89_DAVVERO_DA_ARRESTARE_L=27AVVOCATO_PEDOFILO_ED_ASSAS?= =?UTF-8?Q?SINO_DANIELE_MINOTTI_DI_CRIMINALE_STUDIO_LEGALE_LISI=21=21=21?= From: PEDOFILO SATANISTASSASSINO DANIELE MINOTTI Injection-Date: Sat, 13 Feb 2021 23:22:27 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9816 =C3=89 DAVVERO DA ARRESTARE L'AVVOCATO PEDOFILO ED ASSASSINO DANIELE MINOTT= I DI CRIMINALE STUDIO LEGALE LISI. L'AVVOCATO SATANISTA, NAZISTA, SATA=E5= =8D=90NAZISTA, PEDERASTA, OMICIDA DANIELE MINOTTI DI RAPALLO E GENOVA: RAPI= SCE, INCULA, UCCIDE TANTI BAMBINI, ANCHE PER VENDERNE GLI ORGANI COME DA QUESTA ABERRANTISSIMA FOTO https://steemitimages.com/p/3auKdN6FdQE37hxp1zh1p7U4iqfKLDE9AdpKRQpQV5g36Go= ZLfg7ABa1V4fE2z?format=3Dmatch&mode=3Dfit&width=3D640 1 =C3=89 DI PERICOLO PUBBLICO ENORME, L'AVV ASSASSINO E PEDERASTA DANIELE MIN= OTTI DI RAPALLO E GENOVA: IL NOTO PEDOFILO INCULA ED AMMAZZA BAMBINI DANIEL= E MINOTTI!!! AVVOCATO MALAVITOSO, STUPRANTE INFANTI ED ADOLESCENTI, COME PU= RE OMICIDA: DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI DI LECCE E= MILANO E DI CRIMINALISSIMO STUDIO LEGALE CIRENEI DI RAPALLO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDIO LEGALE MASSONICO-CRIMINALE, DA SEMPRE TUTT'UNO CON MEGA ASSASSINI DI= MAFIA, CAMORRA, NDRANGHETA E COME DA SUA SPECIALITA' PUGLIESE, ANCOR PI=C3= =9A DI SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGGIANA, MAFIA DI SAN SEVER= O)! =C3=89 STALKER ASSASSINO VIA INTERNET, NONCHE' PEDERASTA CHE VIOLENTA E= D UCCIDE I BIMBI, QUESTO AVVOCATO DELINQUENTISSIMO DANIELE MINOTTI! QUESTO = AVVOCATO SATANISTA, NAZISTA, SATA=E5=8D=90NAZISTA, DEPRAVATO, KILLER, DI RA= PALLO E GENOVA (LO VEDETE A SINISTRA, SOPRA SCRITTA ECOMMERCE https://i.yti= mg.com/vi/LDoNHVqzee8/maxresdefault.jpg) RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO, RICICLA SOLDI MAFIOSI: PIERSILVIO BERLUSCONI! SI, SI =C3=89 PROPRIO CO= S=C3=8D: =C3=89 DA ARRESTARE SUBITO L'AVVOCATO SATANISTA, NAZISTA, SATA=E5= =8D=90NAZISTA, PEDOFILO ED OMICIDA DANIELE MINOTTI DI GENOVA E RAPALLO! ASS= ASSINO MASSONE, LUCIFERINO, RAZZISTA, KU KLUK KLANISTA! TERRRORISTA DI ESTR= EMA DESTRA, CORROTTO, LADRO, TRUFFATORE, ORDINANTE MOLTI OMICIDI, AIZZANTE = TANTI SUICIDI CON STILE TIPICO DA AGENTE SEGRETO IN COPERTO DI TIPO STRAGIS= TA E SVASTICATO! https://www.py.cz/pipermail/python/2017-March/012979.html OGNI SETTIMANA SGOZZA OLTRE CHE CANI, GATTI E SERPENTI, TANTI BAMBINI, IN R= ITI SATANICI. IN TUTTA LIGURIA E PIEMONTE (COME DA LINKS CHE QUI SEGUONO.. = I FAMOSI 5 STUDENTI SCOMPARSI NEL CUNEENSE FURONO ASSOLUTAMENTE AMMAZZATI, = FATTI A PEZZI E SOTTERRATI IN VARI BOSCHI PIEMONTESI E LIGURI, PROPRIO DALL= 'AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI DI RAPALLO E GEN= OVA https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html FRA L'ALTRO, PRESENTISSIMO ANCHE A PROPOSITO DI QUESTI ALTRI LINKS, RIPORTA= NTI DEMONIACI MEGA OMICIDA CRIMINI http://www.ilsecoloxix.it/p/genova/2011/11/12/AOPeneMB-satanisti_misteri_tr= agedia.shtml https://genova.repubblica.it/cronaca/2011/06/14/news/riti_voodoo_al_cimiter= o_di_staglieno-17668927/ https://cesnur.com/il-satanismo/le-chiese-di-satana-a-torino/ ) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO KILLER= , SATA=E5=8D=90NAZISTA E PEDOFILO, STUPRANTE ED UCCIDENTE BAMBINI SU BAMBIN= I: DANIELE MINOTTI DI RAPALLO E GENOVA! Criminalissimo Studio Cirenei Sede di Rapallo (GE) Via della Libert=C3=A0, 4/10 =E2=80=93 16035 RAPALLO (GE) Tel. +39 0185 57880 Sede di Genova Via XX Settembre 3/13 16121 =E2=80=93 GENOVA NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE E KILLER DANIELE MINOTTI (QUI IN CHIARO SCURO MASSONICO, PER MANDARE OVV= I MESSAGGI MASSONICO:SATANISTI https://i.pinimg.com/280x280_RS/6d/04/4f/6d0= 44f51fa89a71606e662cbb3346b7f.jpg ). A CAPO, ANZI, A KAP=C3=93 DI UNA SETTA= ASSASSINA DAL NOME ELOQUENTISSIMO : " AMMAZZIAMO PER NOSTRO SATANA IN TERR= A: SILVIO BERLUSCONI". =C3=89 AVVOCATO PEDERASTA INCULA ED AMMAZZA BAMBINI:= DANIELE MINOTTI DI GENOVA E RAPALLO. 2 UNITO IN CI=C3=93 AL PARIMENTI AVVOCATO MASSONE, FASCISTA, LADRO, TRUFFATOR= E, RICICLA SOLDI MAFIOSI, PEDERASTA ED ASSASSINO FULVIO SARZANA DI SANT'IPP= OLITO. ED INSIEME AL VERME SATA=E5=8D=90NAZISTA E MEGA COCAINOMANE MARIO GI= ORDANO (FOTO ELOQUENTISSIMA A PROPOSITO https://pbs.twimg.com/media/EDH0lay= WsAEw_NO?format=3Djpg&name=3Dsmall ). ED INSIEME AL MAFIOSO AFFILIATO A COS= A NOSTRA CLAUDIO CERASA, FRA L'ALTRO PURE NOTO PEDOFILO (AFFILIATO MAFIOSO = CLAUDIO CERASA: PUNCIUTO PRESSO FAMIGLIA MEGA ASSASSINA CIMINNA, MANDAMENTO= DI CACCAMO). ED INSIEME AL PRIMA TERRORISTA DI SINISTRA, POI TERRORISTA DI= DESTRA PAOLO LIGUORI. ED INSIEME AL NOTO OMOSESSUALE PEDERASTA CHE PAGA DA= DECENNI RAGAZZINI AFFINCH=C3=89 LO INCULINO: GIULIANO FERRARA! ED INSIEME = ALLA NOTISSIMA PEDOFILA ANSELMA DEL'OLIO ( TUTTI " PAZZI MA NON SCEMI", COM= E AMANO DEFINIRSI). E PURE INSIEME AL GI=C3=81 ARRESTATO PEDOFILO GIUSEPPE LAZZARI: REGISTA CIN= EMATOGRAFICO DROGA, INCULA ED AMMAZZA BAMBINI DI BRESCIA ( REGISTA CINEMATOGRAFICO SUPER COCAINOMANE E PEDERASTA GIUSEPPE LAZZARI DI= BRESCIA http://pbmystic.rdfig.net/?page=3D001-forum.ssjs&sub=3Dfidonet_altcompa&thr= ead=3D38 CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, NON PER NIENTE, =C3=89 PAPP= A E CICCIA CON LA MASSONA PEDOFILA ANSELMA DELL'OLIO https://www.imdb.com/title/tt1828287/reviews VI ERA PRIMA ANCHE UN INTERESSANTISISMO VIDEO GUARDABILE A QUESTO LINK https://www.youtube.com/watch?v=3DDLR-DJJWl_M RIPORTANTE UNA TRASMISSIONE DEL NOIOSO GIGI MARZULLO, CON LA PEDOFILA SATAN= ISTA, BERLUSCONICCHIA E DEPRAVATA ANSELMA DELL'OLIO ED IL REGISTA CINEMATOG= RAFICO STUPRA BAMBINI GIUSEPPE LAZZARI, CHE, DI FATTO, SLINGUAVANO INTELLET= TUALMENTE, DIFENDENDO E PRUOMUOVENDO LE RAGIONI DELLA LORO PEDOFILIA... ULL= LAL=C3=81 CHE CASO, LA SCHIFOSAMENTE PEDOFILA ANSELMA DELLL'OLIO ED IL PORC= O NAZISTA, FIGLIO DI CANE, DA SEMPRE PEDOFILISSIMO GIULIANO FERRARA, INSIEM= E AL REGISTA IN QUESTIONE, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN RESO NON = PI=C3=9A PUBBLICO... OVVIO, SENTENDOSI SGAMATI, HAN IMBOSCATO LE PROVE DI C= IO' CHE VINCENTISSIMAMENTE SCRIVIAMO). IL TUTTO INSIEME AL NOTO ASSASSINO E PARI PEDOFILO PAOLO BARRAI DI CRIMINAL= ISSIMA TERRABITCOIN https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://www.rsi.ch/la1/programmi/informazione/falo/tutti-i-servizi/Bella-ge= nte-10474214.html IL TUTTO, POI, PURE INSIEME AL PARIMENTI, PRIMA CITATO, PEDERASTA CLAUDIO C= ERASA DE IL FOGLIO (FOGLIO, SI, MA DA USARSI SOLO E SEMPRE PER PULIRSI IL C= ULO, SE SI =C3=89 SENZA CARTA IGIENICA, BUT OCHO..E' INFETTATO DI COSA NOST= RA, CAMORRA, NDRANGHETA, NAZISMO E P2/P3/P4/P999..999 PNUGLASORRT)! BUT LETS' GO PER PUNTI, PLEASE. IAMM BELL, I=C3=81! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO PEDOFILO E NAZISTA DANIELE MINOTTI!= RICICLA PURE MOLTI SOLDI MAFIOSI (PER QUESTO =C3=89 OVVIO TUTT'UNO COL PED= OFILO MACELLA MAGISTRATI SILVIO BERLUSCONI, SUO PEZZO DI MERDA NAZISTA FIGL= IO PIERSILVIO BERLUSCONI https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ E SUA FIGLIA, MANDANTE DI OMICIDI E LESBICA DEPRAVATA MARINA B= ERLUSCONI https://groups.google.com/g/pt.rec.desporto.futebol/c/VdkasMcS6FQ= ) E=E2=80=99 PURE UN AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! VICINO A TERRORISTI KILLER DI ESTREMA DESTRA! CREANTE NUOVE OVRA E GESTAPO,= DI CARATTERE TECNOLOGICO E MILITARE. IL TUTTO CON REGIA DEI BANCHIERI MEGA= RICICLA SOLDI MAFIOSI ENNIO DORIS E MASSIMO DORIS DI BANCA MEDIOLANUM, COM= E PURE DEI MASSONI NAZIFASCISTI UBALDO LIVOLSI, GIULIO OCCHIONERO E FRANCES= CA OCCHIONERO https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ 3 IL PRIMO DI CRIMINALISSIMA LIVOLSI-IAQUINTA & PARTNERS E CRIMINALISSIMA LIV= OLSI AND PARTNERS. GLI ULTIMI 2, FINITI IN GATTABUIA, SPERIAMO AL PIU' PRES= TO, COPIATI IN QUESTO ANCHE DAL PRIMO, CHE HA IN GOPPA, NON PER NIENTE, GIA= ' UNA MEGA CONDANNA AL CARCERE PER IL FALLIMENTO FINPART https://it.fashionnetwork.com/news/Finpart-giudici-Milano-condannano-Livols= i-a-tre-anni,245937.html KAP=C3=93 DI TUTTO QUESTO, =C3=89 OVVIAMENTE IL MACELLA MAGISTRATI E PEDOFI= LO SILVIO BERLUSCONI. ORGANIZZANTE NUOVE OVRA E GESTAPO KILLER, PRIMA VIA B= ASTARDI ASSASSINI ARRESTATI GAETANO SAYA E RICCARDO SINDOCA, POI VIA BASTAR= DI ASSASSINI ARRESTATI GIULIANO TAVAROLI ED EMANUELE CIPRIANI, POI VIA BAST= ARDI ASSASSINI ARRESTATI LEO ZAGAMI E PAOLO BARRAI, POI VIA BASTARDI ASSASS= INI ARRESTATI GIOELE MAGALDI E GIANFRANCO PECORARO ALIAS GIOVANNI FRANCESCO= CARPEORO, POI VIA BASTARDI ASSASSINI ARRESTATI ROBERTO PREATONI, ERNESTO P= REATONI E FABIO GHIONI POI VIA BASTARDI ASSASSINI ARRESTATI RENATO FARINA, "POMPINARO" PIO POMPA, = NICOL=C3=93 POLLARI E VERMINOSO KILLER MARCO MANCINI ( QUESTI ULTIMI, CHE, = NEVER FORGET, INTENDEVANO AMMAZZARE, FRA 2001 E 2006, CHIUNQUE "OSASSE" ESS= ERE NON TOPO DI FOGNA BERLUSCONICCHIO COME LORO, VIA "DISARTICOLAZIONI DI T= IPO TRAUMATICO", OSSIA OMICIDI, RIPETO OMICIDI, MASCHERATI DA FINTI SUICIDI= , MALORI, INCIDENTI VEDI QUESTI VINCENTISSIMI LINKS http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l http://www.pmli.it/sismicolpivanemiciberlusconi.htm ). MEDIATICAMENTE, STA MERDA ASSASSINA BERLUSCONAZISTA E PADANAZISTA DI DANIEL= E MINOTTI, SI APPOGGIA AI NAZI=E5=8D=90STALKERS CORROTTI, MASSONI SATANISTI= E PARIMENTI ASSASSINI VITTORIO FELTRI, FRANCO BECHIS, PIETRO SENALDI, FAUS= TO CARIOTI E MAURIZIO BELPIETRO! AVVOCATO FIGLIO DI PUTTANA ASSASSINO E PEDOFILO DANIELE MINOTTI DI RAPALLO = E GENOVA, CHE, NON PER NIENTE, DIFENDE PEDOFILI KILLERS COME LUI, A MAN BAS= SA ( FRA TOPI DI FOGNA SANGUINARI E PERVERTITI CI SI CAPISCE) ECCONE PROVE A TONNELLATE https://www.ilsecoloxix.it/genova/2008/08/14/news/la-badante-sgozzata-denun= cio-uno-stupro-1.33388756 http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 TROVATE QUALSIASI ALTRA INFORMAZIONE SUL MASSONE NAZISTA, SUL SATANISTA NAZ= ISTA, SUL SATA=E5=8D=90NAZISTA, PEDOFILO, PEDERASTA, ASSASSINO DANIELE MINO= TTI DI RAPALLO E GENOVA, QUI: https://www.py.cz/pipermail/python/2017-April/013002.html 4 PER CONCLUDERE, A VOI ORA IL TESTO PRIMA CITATO DI UN IMMIGRATO RUMENO, STE= FAN CUMESCU. NARCOTIZZATO E POI INCULATO A SANGUE, ALLORCH=C3=89 POCO PIU' = CHE BAMBINO, DAL MASSONE NAZIFASCISTA E FILO MAFIOSO, NONCHE' PEDOFILO INCU= LA ED AMMAZZA BAMBINI DANIELE MINOTTI, AVVOCATO DI RAPALLO E GENOVA ( I POS= TS DI STEFAN CUMESCU, DI CUI ERA STRA COLMA LA RETE, SONO STATI FATTI TUTTI= CANCELLARE DALL'ASSASSINO DANIELE MINOTTI... OVVIO, HA LA COSCIENZA LERCIA= , SE LA FA SOTTO A PROPOSITO CHE LA SUA PERVERTITA PEDERASTA ED OMICIDA REA= LT=C3=81 VENGA A GALLA..LA FAREMO VENIRE E STRA VENIRE A GALLA NOI.. MEGLIO= MORTI CHE ARRESI Y DE VERDAD!!!)!!!!!! ECCO LO SCIOCCANTISSIMO TESTO DI STEFAN A PROPOSITO ( STEFAN, CHE A PROPOSI= TO DI TUTTO QUESTO, NE SCRIVE EROICAMANTE QUI https://www.py.cz/pipermail/p= ython/2017-April/013002.html ). GUARDATE DA VOI STESSI, PLEASE, CHE PEDOFIL= O ASSASSINO E SATA=E5=8D=90NAZISTA SIA STO PEZZO DI MERDA CRIMINALISSIMO DI= DANIELE MINOTTI ( AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE BAMBINI E= D ADOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI MEZZA= ITALIA, OPPURE PER SQUARTARE GLI STESSI ALLO SCOPO DI VENDERNE GLI ORGANI https://steemitimages.com/p/3auKdN6FdQE37hxp1zh1p7U4iqfKLDE9AdpKRQpQV5g36Go= ZLfg7ABa1V4fE2z?format=3Dmatch&mode=3Dfit&width=3D640)! Ciao tuti e scusate de mio italiano. Io sono rumeno e nun me nascondo: me c= hiamo Stefan Cumescu e sono stato sodomizzato con violenza da avvocato assa= ssino Daniele Minotti di Rapallo e Genova, esatamente nel estate 2009! Alor= a tenievo 13 anni e lo criminale Daniele Minotti me faceva vendere tanta co= caina per lui, dicendomi "sei minorenne, non te possono far niente". Ebbene= , nel 2009, l'avvocato di giri nazisti misti a Cosa Nostra, Camorra, Ndrang= heta, Daniele Minotti di Rapallo e Genova, mi fece bere qualcosa, con dentr= o ovvia droga che te fa perdere sensi... mi fece svenire apposta e mentre e= ro mas morto che vivo, me sodomizzo'. Vi era anche pancione pieno di merda,= pedofilo Giuliano Ferrara de Il Foglio a guardare, ridere, cercare de mast= urbarse invano esendo noto impotente da sempre. Vi era anche el banchero im= mensamente pedofilo Gabriele Silvagni di Rimini ( di ricicla soldi mafiosi = Banca Carim Rimini). E sua moglie, nota prostituta, sempre in club scambist= i a prendere cazzi in culo a raffica, tanto quanto satanista e pedofila Raf= faella Vaccari, sempre de Rimini (li vedete qui http://chiamamicitta.it/wp-= content/uploads/2016/10/gabri-e-raffa.jpg). Il figlio di puttana avvocato D= aniele Minotti, criminalissimo avvocato di Rapallo e Genova me sodomizz=C3= =B3 insieme ad altri di suoi giri fascisti e mafiosi. Ho anche prove di tut= to questo. Io, ora, Stefan Cumescu di Genova, facio il muratore, basta drog= a, basta prostituirsi (como dovetti de fare a seguito di questo stupro, per= poter rimanere vivo, per non venire ammazzato, e doveti de prostituirmi pr= oprie su ordine de Mafia Berlusconiana e Fascismo Berlusconiano, a Genova, = rapresentati da questo bastardo sodomizza bambini e spacciatore di cocaina = di avvocato Daniele Minotti). Guadanio un decimo di quanto guadaniavo prima= e lavoro il triplo di quanto prima. Ma preferisco ci=C3=B3, sento la mia v= ita uno poco di maggiore securo. Ma avvocato di Hitler, Vallanzasca e Satan= a, avvocato filio de putana di pedofilo assassino Silvio Berlusconi e Giuli= ano Ferrara, il massone nazista, assassino e pederasta Daniele Minotti di G= enova e Rapallo, davvero fa parte di setta di maniaci sessuali omosessuali = killer. Ciao. Stefan Cumescu. PS Io vedevo in giro uno belo testo che parlava di tuto questo...anche de orge= omosessuali pedofilesche fate da incula bambini Daniele Minotti con Don Ri= ccardo Seppia, ma ora non vedo tanto di piu' in giro, lo steso testo. Alora= sai cosa facio? Prover=C3=B3 a rintracciarlo e riproporlo io, da tute part= i e pe tuta mi vita. From newsfish@newsfish Thu Aug 1 00:46:12 2024 X-Received: by 2002:ad4:576e:: with SMTP id r14mr22326521qvx.52.1613522203119; Tue, 16 Feb 2021 16:36:43 -0800 (PST) X-Received: by 2002:a25:86d1:: with SMTP id y17mr31918708ybm.370.1613522202776; Tue, 16 Feb 2021 16:36:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Feb 2021 16:36:42 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: google-groups.googlegroups.com; posting-host=84.198.244.196; posting-account=0u-_QgoAAABVd19iXB71E2R2Sl8DPf16 NNTP-Posting-Host: 84.198.244.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ce9d13d-7f6c-4675-88f7-2764105212b3n@googlegroups.com> Subject: IL LEGHISTA INCULA ED AMMAZZA BAMBINI PAOLO BARRAI (NOTO IN TUTTO IL MONDO COME IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI MILANO, PROCURA DI LUGANO, SCOTLAND YARD LONDRA, FBI NEW YORK, POLICIA CIVIL DI PORTO SEGURO (BR). From: Andreas Nigg Bank J Safra Sarasin Zurich Injection-Date: Wed, 17 Feb 2021 00:36:43 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 189 Xref: reader02.eternal-september.org comp.lang.vhdl:9817 IL LEGHISTA INCULA ED AMMAZZA BAMBINI AOLO BARRAI (NOTO IN TUTTO IL MONDO C= OME IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI MILANO, PROC= URA DI LUGANO, SCOTLAND YARD LONDRA, FBI NEW YORK, POLICIA CIVIL DI PORTO S= EGURO (BR). IL LEGHISTA PEDERASTA INCULA ED AMMAZZA BAMBINI PAOLO BARRAI (NOTO IN TUTTO= IL MONDO COME IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI M= ILANO, PROCURA DI LUGANO, SCOTLAND YARD LONDRA, FBI NEW YORK E POLICIA CIVI= L DI PORTO SEGURO (BR). IL TUTTO VIA INTERPOL ED EUROPOL! 1 =C3=89 DAVVERO PEDOFILO ED ASSASSINO: PAOLO BARRAI DI CRIMINALE TERRA BITCO= IN! IL CRIMINALE LEGHISTA LUCA SOSTEGNI, INCARCERATO, SCAPPAVA IN CITATA PO= RTO SEGURO (BR), DOVE L'OMICIDA PAOLO BARRAI HA RICICLATO PARTE DEI 49 MLN = =E2=82=AC RUBATI DA LEGA LADRONA! (ECCONE LE PROVE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 ) =C3=89 TRUFFATORE, PEDOFILO E KILLER: PAOLO BARRAI, NATO A MILANO IL 28.6.1= 965 ( O TRUFFATORE, PEDOFILO E KILLER: PAOLO PIETRO BARRAI, NATO A MILANO I= L 28.6.1965). DI CRIMINALE TERRA BITCOIN (ASSOCIAZIONE CON INTENTO DI FOTTE= RE, FREGARE, SPENNARE POLLI VIA INTERNET, IL TUTTO VIA TELEGRAM) E CRIMINAL= ISSIMO BLOG MERCATO LIBERO, ALIAS "MERDATO" LIBERO! INDAGATO, AL MOMENTO, D= ALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD= LONDRA E DA FBI NEW YORK. HA RICICLATO 21 MLN ASSASSINI DI NDRANGHETA, IN FALLENTISSIMA ICO EIDOO (IN= SIEME AL MALAVITOSO NATALE FERRARA DI REGGIO CALABRIA, DA DECENNI PUNCIUTO,= OSSIA AFFILIATO UFFICIALMENTE ALLA NDRANGHETA, INSIEME AL MALAVITOSO PAOLO= CARDEN=C3=81 DI FREGA SOLDI BLOG VINCITORI E VINTI, INSIEME AL MALAVITOSO = STEFANO BASSI DI FREGA SOLDI BLOG IL GRANDE BLUFF, INSIEME AL MALAVITOSO FE= DERICO IZZI, NOTO COME "ER ZIOROMOLO DELLA CAMORRA", LI VEDETE TUTTI IN FOT= O QUI https://3.bp.blogspot.com/-6WRXJQbHe08/WSBR0uTrMLI/AAAAAAAAY2g/L8c3w9= GGr3wpG7yWxBBeOohzhWa7iJ7uQCLcB/s1600/18558610_10156258698827281_4591948382= 498991167_o.jpg ) 2 CHECK EVERY DETAIL BOUT IT, HERE AVETE MIGLIA DI DETTAGLI E PROVE QUI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit 3 IL PEDERASTA OMICIDA PAOLO BARRAI =C3=89 ANCHE DI UNO DEI PRINICIPALI CRIMI= NALI UNENTI NDRANGHETA E MASSONERIA. =C3=89 DA SEMPRE UN CAPO SANTISTA (OSS= IA NDRANGHETISTA MASSONE). INFATTI ERA PAPPA E CICCIA CON L'ARRESTATO MASSO= NE NDRANGHETISTA BERLUSCONICCHIO GIANCARLO PITTELLI (http://www.iacchite.bl= og/giancarlo-pittelli-laffarista-massone-dei-boss-della-ndrangheta/ ). ED E= RA CICCIA E PAPPA PURE CON GRAN PARTE DEI 334 MASSONI NDRANGHETISTI ARRESTA= TI DAL GRANDE PM NICOLA GRATTERI NEL DICEMBRE 2019 ( https://www.ilprimaton= azionale.it/cronaca/ndrangheta-334-arresti-onorevoli-massoni-colonnello-cos= che-140387/ ). MI PRESENTO. SONO IL RIVOLUZIONARIO A FINI DI BENE: ANDREAS NIGG , VICE PRESIDENT AND HE= AD OF ASSET MANAGEMENT. PRESSO SAFRA-SARASIN BANK ZURICH PRIMA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK VONTOBEL ZURI= CH. https://citywireselector.com/manager/andreas-nigg/d2395 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTER = BANK ZURICH DEL MASSONE LEGHISTA E NAZISTA CARLO PESENTI (NOTO PARTNER OMOS= ESSUALE DEL SATANISTA MASSONE FEDERICO TRABUCCO DI KAIROS). ED IO IN PERSON= A, ANDREAS NIGG, ORDINAI SUBITO DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI = A STA BESTIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL= 28.6.1965. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA, CAMORRA, PEDOFI= LO STRAGISTA SILVIO BERLUSCONI, LESBICA PEDOFILA ASSASSINA MARINA BERLUSCON= I E 49 MILIONI DI =E2=82=AC RUBATI DA LEGA LADRONA? DA LONTANO 3.000 KM (NO= N SONO ANTI OMOSESSUALI O LESBICHE, mA ODIO L'IPOICRISIA E LA MAFIOSA OMERT= =C3=81 CHE DA SEMPRE REGNA IN ITALIA, LA MIA RIVOLUZIONE, LA RIVOLUZIONE DI= ANDREAS NIGG DI BANK SAFRA SARASIN ZURICH, RADER=C3=81 A ZERO STA BERLUSCO= NICCHIA IPOCRISIA ED OMERT=C3=81 PUZZOLENTE, ALLA BASE DI OGNI MALE, NEL PA= ESE DEL GRANDE SANDRO PERTINI)! E NON SCORDIAMO CHE IL LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN B= ORSA, AZZERANTE I RISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI =C3=89 PURE UN N= AZI-ST-ALKER VIA INTERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TOR= TURATORE OMICIDA! OLTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( I= N UN PRIMO CASO, A SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN= CITIBANK, COME DA FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/= repubblica/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-ter= enzio-sotto-torchio.html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ HA FATTO 66 (DI PROPOSITO NUMERO SATANICO) FILM PORNO CON CAVALLI E BAMBINI= , BEVENDO SPERMA EQUINO ED INCULANDO A SANGUE BAMBINI SU BAMBINI https://groups.google.com/g/comp.lang.python/c/aRdLu8PIHXg 4 =C3=89 STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 EURO, PER = MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.bluerating.co= m/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-che-ha-vio= lato-gli-obblighi-informativi SNIFFAVA CHILI DI COCAINA E STUPRAVA RAGAZZINE COL SERIAL RAPIST ALBERTO GE= NOVESE (ENTRAMBI SON PARTI DI CRIMINALISSIMA LOGGIA DEL DRAGO DEL PEDOFILO = SPAPPOLA MAGISTRATI SILVIO BERLUSCONI) https://www.fanpage.it/milano/story/alberto-genovese-arrestato/ https://www.ilfattoquotidiano.it/2021/01/26/alberto-genovese-dichiarava-red= diti-da-dipendente-proseguono-gli-accertamenti-fiscali-su-imprenditore-accu= sato-di-stupro/6078470/ EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html Vada costui a a riciclare soldi mafiosi o rubati da Lega Ladrona, dal figli= o di troiaccia criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato L= ugano, dal figlio di troiaccia criminalissimo Daniele Albisetti di Banca de= llo Stato Lugano, dal figlio di troiaccia criminalissimo Claudio Genasci di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Patrick L= afranchi di Banca dello Stato Lugano, dal figlio di troiaccia criminalissim= o Gabriele Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! Per finire ribadisco Quando come Vontobel Bank Zurich, abbiamo comprato Finter Bank Zurich, dai = massoni leghisti e nazifascisti Pesenti, immediatamente abbiamo chiuso tutt= i i conti connessi, al, tanto quanto, massone leghista nazifascista, nonche= ' famoso ladro, truffatore, azzera risparmi di ognuno che gli abbocca via i= nternet e non solo, nonch=C3=A9 pedofilo Paolo Pietro Barrai ( che venne ca= cciato da Citibank, a fine anni 90, per terrificanti frodi che li effettuav= a, come da finale di questo articolo https://ricerca.repubblica.it/repubbli= ca/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-so= tto-torchio.html il grande banchiere Giulio Di Cerbo licenzio' in tronco il= verme criminalissimo Paolo Barrai e lo fece condannare al carcere, pochi a= nni dopo, il bastardo nazista e ndranghetista killer Paolo Barrai fece amma= zzare Giulio Di Cerbo, facendo fintamente apparire il tutto come morte natu= rale... il tutto via Massonerie Fasciste e Servizi Segreti Fascisti a cui i= l pedofilo assassino Paolo Pietro Barrai =C3=A9 connessissimo). Di delinque= ntissima Medicalchain, di delinquentissima Cryptolab S A, di delinquentissi= ma Bigbit, di delinquentissima Bitcoin Cryptoeconomy, di delinquentissima B= itincubator & Venture, di delinquentissima Bgbit News Channel e delinquenti= ssima Terra Bitcoin. Attraverso i quali strumenti, lui ed il fallitissimo, = idiota, davvero incapace e fallimentare trader Federico Izzi di Roma (che c= ampa, di fatto, riciclando soldi mafiosi e facendo film pedopornofrafici, t= anto e' vero che sta merda criminale di Federico Izzi di Roma, e' noto sull= e rivere del Tevere, da chiunque, come "Er Zio Romolo incula bambini" e pur= e come "Er Zio Romolo della Camorra") spennano " i polli del web=C2=A8, ven= dendo loro abbonamenti annuali su criptovalute e non solo, totalmente falli= mentari! A fra non molto via altri miei miliardi di scritti che preparer=C3=B3! From newsfish@newsfish Thu Aug 1 00:46:13 2024 X-Received: by 2002:a37:a8cc:: with SMTP id r195mr19972655qke.151.1613992329891; Mon, 22 Feb 2021 03:12:09 -0800 (PST) X-Received: by 2002:a25:aa43:: with SMTP id s61mr34217362ybi.32.1613992329691; Mon, 22 Feb 2021 03:12:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Feb 2021 03:12:09 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=31.31.151.104; posting-account=0u-_QgoAAABVd19iXB71E2R2Sl8DPf16 NNTP-Posting-Host: 31.31.151.104 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6d06b4b5-59c3-4b9e-9828-75ee511c2e4bn@googlegroups.com> Subject: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI MAFIOSI A LUGANO! From: Andreas Nigg Bank J Safra Sarasin Zurich Injection-Date: Mon, 22 Feb 2021 11:12:09 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9818 IL LEGHISTA INCULA ED AMMAZZA BAMBINI PAOLO PIETRO BARRAI (NOTO IN TUTTO IL= MONDO COME IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI MILA= NO, PROCURA DI LUGANO, SCOTLAND YARD LONDRA, FBI NEW YORK, POLICIA CIVIL DI= PORTO SEGURO (BR). IL TUTTO VIA INTERPOL ED EUROPOL! 1 =C3=89 DAVVERO PEDOFILO ED ASSASSINO: PAOLO BARRAI DI CRIMINALE TERRA BITCO= IN! IL CRIMINALE LEGHISTA LUCA SOSTEGNI, INCARCERATO, SCAPPAVA IN CITATA PO= RTO SEGURO (BR), DOVE L'OMICIDA PAOLO BARRAI HA RICICLATO PARTE DEI 49 MLN = =E2=82=AC RUBATI DA LEGA LADRONA! (ECCO LE PROVE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 ) =C3=89 TRUFFATORE, PEDOFILO E KILLER: PAOLO PIETRO BARRAI, NATO A MILANO IL= 28.6.1965 ( O TRUFFATORE, PEDOFILO E KILLER: PAOLO BARRAI, NATO A MILANO I= L 28.6.1965). DI CRIMINALE TERRA BITCOIN (ASSOCIAZIONE CON INTENTO DI FOTTE= RE, FREGARE, SPENNARE POLLI VIA INTERNET, IL TUTTO VIA TELEGRAM) E CRIMINAL= ISSIMO BLOG MERCATO LIBERO, ALIAS "MERDATO" LIBERO! INDAGATO, AL MOMENTO, D= ALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD= LONDRA E DA FBI NEW YORK. HA RICICLATO 21 MLN ASSASSINI DI NDRANGHETA, IN FALLENTISSIMA ICO EIDOO (IN= SIEME AL MALAVITOSO NATALE FERRARA DI REGGIO CALABRIA, DA DECENNI PUNCIUTO,= OSSIA AFFILIATO UFFICIALMENTE ALLA NDRANGHETA, INSIEME AL MALAVITOSO PAOLO= CARDEN=C3=81 DI FREGA SOLDI BLOG VINCITORI E VINTI, INSIEME AL MALAVITOSO = STEFANO BASSI DI FREGA SOLDI BLOG IL GRANDE BLUFF, INSIEME AL MALAVITOSO FE= DERICO IZZI, NOTO COME "ER ZIOROMOLO DELLA CAMORRA", LI VEDETE TUTTI IN FOT= O QUI https://3.bp.blogspot.com/-6WRXJQbHe08/WSBR0uTrMLI/AAAAAAAAY2g/L8c3w9= GGr3wpG7yWxBBeOohzhWa7iJ7uQCLcB/s1600/18558610_10156258698827281_4591948382= 498991167_o.jpg ) 2 CHECK EVERY DETAIL BOUT IT, HERE AVETE MIGLIA DI DETTAGLI E PROVE QUI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit 3 IL PEDERASTA OMICIDA PAOLO BARRAI =C3=89 ANCHE DI UNO DEI PRINICIPALI CRIMI= NALI UNENTI NDRANGHETA E MASSONERIA. =C3=89 DA SEMPRE UN CAPO SANTISTA (OSS= IA NDRANGHETISTA MASSONE). INFATTI ERA PAPPA E CICCIA CON L'ARRESTATO MASSO= NE NDRANGHETISTA BERLUSCONICCHIO GIANCARLO PITTELLI (http://www.iacchite.bl= og/giancarlo-pittelli-laffarista-massone-dei-boss-della-ndrangheta/ ). ED E= RA CICCIA E PAPPA PURE CON GRAN PARTE DEI 334 MASSONI NDRANGHETISTI ARRESTA= TI DAL GRANDE PM NICOLA GRATTERI NEL DICEMBRE 2019 ( https://www.ilprimaton= azionale.it/cronaca/ndrangheta-334-arresti-onorevoli-massoni-colonnello-cos= che-140387/ ). MI PRESENTO. SONO IL RIVOLUZIONARIO A FINI DI BENE: ANDREAS NIGG , VICE PRESIDENT AND HE= AD OF ASSET MANAGEMENT. PRESSO SAFRA-SARASIN BANK ZURICH PRIMA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK VONTOBEL ZURI= CH. https://citywireselector.com/manager/andreas-nigg/d2395 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTER = BANK ZURICH DEL MASSONE LEGHISTA E NAZISTA CARLO PESENTI (NOTO PARTNER OMOS= ESSUALE DEL SATANISTA MASSONE FEDERICO TRABUCCO DI KAIROS). ED IO IN PERSON= A, ANDREAS NIGG, ORDINAI SUBITO DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI = A STA BESTIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL= 28.6.1965. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA, CAMORRA, PEDOFI= LO STRAGISTA SILVIO BERLUSCONI, LESBICA PEDOFILA ASSASSINA MARINA BERLUSCON= I E 49 MILIONI DI =E2=82=AC RUBATI DA LEGA LADRONA? DA LONTANO 3.000 KM (NO= N SONO ANTI OMOSESSUALI O LESBICHE, mA ODIO L'IPOICRISIA E LA MAFIOSA OMERT= =C3=81 CHE DA SEMPRE REGNA IN ITALIA, LA MIA RIVOLUZIONE, LA RIVOLUZIONE DI= ANDREAS NIGG DI BANK SAFRA SARASIN ZURICH, RADER=C3=81 A ZERO STA BERLUSCO= NICCHIA IPOCRISIA ED OMERT=C3=81 PUZZOLENTE, ALLA BASE DI OGNI MALE, NEL PA= ESE DEL GRANDE SANDRO PERTINI)! E NON SCORDIAMO CHE IL LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN B= ORSA, AZZERANTE I RISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI =C3=89 PURE UN N= AZI-ST-ALKER VIA INTERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TOR= TURATORE OMICIDA! OLTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( I= N UN PRIMO CASO, A SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN= CITIBANK, COME DA FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/= repubblica/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-ter= enzio-sotto-torchio.html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ HA FATTO 66 (DI PROPOSITO NUMERO SATANICO) FILM PORNO CON CAVALLI E BAMBINI= , BEVENDO SPERMA EQUINO ED INCULANDO A SANGUE BAMBINI SU BAMBINI https://groups.google.com/g/comp.lang.python/c/aRdLu8PIHXg 4 =C3=89 STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 EURO, PER = MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.bluerating.co= m/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-che-ha-vio= lato-gli-obblighi-informativi SNIFFAVA CHILI DI COCAINA E STUPRAVA RAGAZZINE COL SERIAL RAPIST ALBERTO GE= NOVESE (ENTRAMBI SON PARTI DI CRIMINALISSIMA LOGGIA DEL DRAGO DEL PEDOFILO = SPAPPOLA MAGISTRATI SILVIO BERLUSCONI) https://www.fanpage.it/milano/story/alberto-genovese-arrestato/ https://www.ilfattoquotidiano.it/2021/01/26/alberto-genovese-dichiarava-red= diti-da-dipendente-proseguono-gli-accertamenti-fiscali-su-imprenditore-accu= sato-di-stupro/6078470/ EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html Vada costui a a riciclare soldi mafiosi o rubati da Lega Ladrona, dal figli= o di troiaccia criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato L= ugano, dal figlio di troiaccia criminalissimo Daniele Albisetti di Banca de= llo Stato Lugano, dal figlio di troiaccia criminalissimo Claudio Genasci di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Patrick L= afranchi di Banca dello Stato Lugano, dal figlio di troiaccia criminalissim= o Gabriele Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! Per finire ribadisco Quando come Vontobel Bank Zurich, abbiamo comprato Finter Bank Zurich, dai = massoni leghisti e nazifascisti Pesenti, immediatamente abbiamo chiuso tutt= i i conti connessi, al, tanto quanto, massone leghista nazifascista, nonche= ' famoso ladro, truffatore, azzera risparmi di ognuno che gli abbocca via i= nternet e non solo, nonch=C3=A9 pedofilo Paolo Pietro Barrai ( che venne ca= cciato da Citibank, a fine anni 90, per terrificanti frodi che li effettuav= a, come da finale di questo articolo https://ricerca.repubblica.it/repubbli= ca/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-so= tto-torchio.html il grande banchiere Giulio Di Cerbo licenzio' in tronco il= verme criminalissimo Paolo Barrai e lo fece condannare al carcere, pochi a= nni dopo, il bastardo nazista e ndranghetista killer Paolo Barrai fece amma= zzare Giulio Di Cerbo, facendo fintamente apparire il tutto come morte natu= rale... il tutto via Massonerie Fasciste e Servizi Segreti Fascisti a cui i= l pedofilo assassino Paolo Pietro Barrai =C3=A9 connessissimo). Di delinque= ntissima Medicalchain, di delinquentissima Cryptolab S A, di delinquentissi= ma Bigbit, di delinquentissima Bitcoin Cryptoeconomy, di delinquentissima B= itincubator & Venture, di delinquentissima Bgbit News Channel e delinquenti= ssima Terra Bitcoin. Attraverso i quali strumenti, lui ed il fallitissimo, = idiota, davvero incapace e fallimentare trader Federico Izzi di Roma (che c= ampa, di fatto, riciclando soldi mafiosi e facendo film pedopornofrafici, t= anto e' vero che sta merda criminale di Federico Izzi di Roma, e' noto sull= e rivere del Tevere, da chiunque, come "Er Zio Romolo incula bambini" e pur= e come "Er Zio Romolo della Camorra") spennano " i polli del web=C2=A8, ven= dendo loro abbonamenti annuali su criptovalute e non solo, totalmente falli= mentari! From newsfish@newsfish Thu Aug 1 00:46:13 2024 X-Received: by 2002:ac8:7257:: with SMTP id l23mr19900767qtp.350.1614719290143; Tue, 02 Mar 2021 13:08:10 -0800 (PST) X-Received: by 2002:a25:23d2:: with SMTP id j201mr33666576ybj.53.1614719289966; Tue, 02 Mar 2021 13:08:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Mar 2021 13:08:09 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=84.198.244.196; posting-account=pSOKAQoAAAAhnZ2yXOaf-dyixoA5DjNQ NNTP-Posting-Host: 84.198.244.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <73b297cf-40b5-4183-ba37-a330c77565f7n@googlegroups.com> Subject: FIGLIO DI TROIONA PAOLO PIETRO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO) COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI MAFIOSI E... From: "ANDREAS NIGG. BANK J SAFRA SARASIN ZURICH." Injection-Date: Tue, 02 Mar 2021 21:08:10 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9819 FIGLIO DI PUTTANONA PAOLO PIETRO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO= CHIAMANO IN TUTTO IL MONDO) COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI= , FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI MAFIOSI E ...RUBA= TI DA LEGA LADRONA! IL NAZISTA ASSASSINO PAOLO BARRAI (NOTO COME IL PEDOFILO DEL BITCOIN) =C3= =89 INDAGATO AL MOMENTO DA PROCURA DI MILANO, COME PURE DA PROCURA DI LUGAN= O, SCOTLAND YARD LONDRA ED FBI NEW YORK. IL TUTTO VIA INTERPOL ED EUROPOL. =C3=89 DA DECENNI PEDOFILO ED ASSASSINO: PAOLO PIETRO BARRAI DI CRIMINALE T= ERRA BITCOIN! IL DELINQUENTE LEGHISTA LUCA SOSTEGNI, GI=C3=81 INCARCERATO, SCAPPAVA A POR= TO SEGURO (BR), DOVE L'OMICIDA PAOLO BARRAI HA LAVATO PARTE DEI 49 MLN =E2= =82=AC RUBATI DA LEGA LADRONA! https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://pbs.twimg.com/media/CIB3862WcAA8F7c.png https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 ! =C3=89 TRUFFATORE, PEDOFILO E KILLER: PAOLO PIETRO BARRAI DI CRIMINALE TERR= A BITCOIN (PRESSO SITO CRIMINALE: TELEGRAM) E BLOG MERCATO LIBERO, ALIAS "M= ERDATO" LIBERO! =C3=89 BESTIA CRIMINALE CHE ORDINA PURE TANTI OMICIDI! INDA= GATO, AL MOMENTO, DALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGAN= O, DA SCOTLAND YARD LONDRA E DA FBI NEW YORK. +TROVATE VINCENTISSIMAMENTE QUI, A PROPOSITO Di SUO AVER RICICLATO 21 MLN A= SSASSINI DI NDRANGHETA, IN FALLENTISSIMA ICO EIDOO https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://blockfxgold.com/crypto/italian-mafia-launders-money-through-crypto/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit TRATTASI ANCHE DI UNO DEI PRINICIPALI PORCI UNENTI NDRANGHETA E MASSONERIA.= =C3=89 DA SEMPRE SANTISTA (OSSIA NDRANGHETISTA MASSONE). PAPPA E CICCIA CO= N L'ARRESTATO MASSONE NDRANGHETISTA BERLUSCONICCHIO GIANCARLO PITTELLI (htt= p://www.iacchite.blog/giancarlo-pittelli-laffarista-massone-dei-boss-della-= ndrangheta/ ). E CICCIA E PAPPA PURE CON GRAN PARTE DEI 334 MASSONI NDRANGH= ETISTI ARRESTATI DAL GRANDE PM NICOLA GRATTERI NEL DICEMBRE 2019 ( https://= www.ilprimatonazionale.it/cronaca/ndrangheta-334-arresti-onorevoli-massoni-= colonnello-cosche-140387/ ). MI PRESENTO. SONO IL RIVOLUZIONARISSIMO BANCHIERE ANDREAS NIGG. VICE PRESIDENT AND HEAD = OF ASSET MANAGEMENT PRESSO SAFRA-SARASIN BANK ZURICH https://citywireselector.com/manager/andreas-nigg/d2395 PRIMA, BEN APPUNTO, VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK= VONTOBEL ZURICH. https://www.bloomberg.com/research/stocks/private/person.asp?personId=3D302= 73980&privcapId=3D1460324 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTER = BANK ZURICH DEI MASSONI NAZISTI E LEGHISTI PESENTI. ED IO IN PERSONA, ANDRE= AS NIGG, ORDINAIO SUBITO DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI A STA B= ESTIA CRIMINALISSIMA DI PAOLO BARRAI, NATO A MILANO IL 28.6.1965. IN QUANTO= PUZZAVANO DI MEGA FURTI E CORRUZIONE DI LEGA LADRONA, COME PURE DI NDRANGH= ETA, COSA NOSTRA E CAMORRA, DA LONTANO 3.000 KM. MUMBLE, MUMBLE, MUMBLE... SONO SVIZZERO, ICH BIN SCHWEIZER, QUINDI SONO UN = UOMO PRECISO. AMO LA PRECISIONE. PER VIA DI QUESTO, ANALIZZIAMO BEN BENE, O= GNI CONCETTO, DA ORA IN AVANTI, PLEASE! DICEVAMO..... L'ASSASSINO PEDOFILO PAOLO =C2=A8PIETRO BARRAI =C3=89 PURE UN PEDERASTA CHE= STUPRA ED AMMAZZA TANTI BAMBINI (LO FA PER VENDERNE GLI ORGANI COME DA QUE= STA ABERRANTE FOTO https://steemitimages.com/p/3auKdN6FdQE37hxp1zh1p7U4iqfK= LDE9AdpKRQpQV5g36GoZLfg7ABa1V4fE2z?format=3Dmatch&mode=3Dfit&width=3D640 ).= HA RICICLATO EURO ASSASSINI DI NDRANGHETA IN MALAVITOSISSIMA E BANCAROTTIE= RA ICO EIDOO! E' STATO CACCIATO DA CITIBANK E FATTO CONDANNARE A GALERA DA = CITIBANK! HA FATTO FILM PEDOPORNOGRAFICI, STUPRANDO QUASI A MORTE TANTI BAM= BINI! HA UCCISO LUI STESSO, TANTI BAMBINI, PER PRENDER LORO ORGANI E TRAFFI= CARLI! HA FATTO FILM PORNO CON CAVALLI, BEVENDO LITRI DI SPERMA EQUINO E FA= CENDOSI SODOMIZZARE DA FALLI DI CAVALLI LUNGHI 40 CM! E' STATO MULTATO DA C= ONSOB BEN 70.000 EURO! HA 23 CAUSE, CON GENTE DI MEZZA DITTATURA FASCIOMAFI= OSA DI BERLUSCONIA, A CUI HA AZZERATO I RISPARMI! PER SCAPPARE DALLE QUALI,= SI E' ORA RIFUGIATO A LONDRA, OVE FA TANTI POMPINI AL NAZISTA NIGEL FARAGE= AFFINCHE' LO PROTEGGA! E' STATO CONDANNATO AL CARCERE IN BRASILE, ANCHE PE= R PEDERASTIA VIOLENTA ( E PER ALTRI TANTISSIMI CRIMINI)! NON NE AZZECCA MAI= MEZZA UNA IN BORSA, OVE AZZERA I RISPARMI DI TUTTI E SEMPRE! E VI E' TANTI= SSIMO PIU', DI CUI SCRIVEREMO FINO A 15 MINUTI DOPO LA NOSTRA MORTE! SCUSATE MIO ITALIANO SCARSO, HO PREPARATO UN SUNTO DEL TUTTO, IN QUESTO TES= TO DIVISO IN 4 PARTI, CHE PRESTO ESPANDER=C3=93 IL PI=C3=9A POSSIBILE FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMA= NO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E CO= L PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA = SOLDI MAFIOSI A LUGANO! /// IL LEGHISTA INCULA ED AMMAZZA BAMBINI PAOLO PIETRO BARRAI (NOTO IN TUTTO IL= MONDO COME IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI MILA= NO, PROCURA DI LUGANO, SCOTLAND YARD LONDRA, FBI NEW YORK, POLICIA CIVIL DI= PORTO SEGURO (BR). IL TUTTO VIA INTERPOL ED EUROPOL! 1 =C3=89 DAVVERO PEDOFILO ED ASSASSINO: PAOLO BARRAI DI CRIMINALE TERRA BITCO= IN! IL CRIMINALE LEGHISTA LUCA SOSTEGNI, INCARCERATO, SCAPPAVA IN CITATA PO= RTO SEGURO (BR), DOVE L'OMICIDA PAOLO BARRAI HA RICICLATO PARTE DEI 49 MLN = =E2=82=AC RUBATI DA LEGA LADRONA! (ECCO LE PROVE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 ) =C3=89 TRUFFATORE, PEDOFILO E KILLER: PAOLO PIETRO BARRAI, NATO A MILANO IL= 28.6.1965 ( O TRUFFATORE, PEDOFILO E KILLER: PAOLO BARRAI, NATO A MILANO I= L 28.6.1965). DI CRIMINALE TERRA BITCOIN (ASSOCIAZIONE CON INTENTO DI FOTTE= RE, FREGARE, SPENNARE POLLI VIA INTERNET, IL TUTTO VIA TELEGRAM) E CRIMINAL= ISSIMO BLOG MERCATO LIBERO, ALIAS "MERDATO" LIBERO! INDAGATO, AL MOMENTO, D= ALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD= LONDRA E DA FBI NEW YORK. HA RICICLATO 21 MLN ASSASSINI DI NDRANGHETA, IN FALLENTISSIMA ICO EIDOO (IN= SIEME AL MALAVITOSO NATALE FERRARA DI REGGIO CALABRIA, DA DECENNI PUNCIUTO,= OSSIA AFFILIATO UFFICIALMENTE ALLA NDRANGHETA, INSIEME AL MALAVITOSO PAOLO= CARDEN=C3=81 DI FREGA SOLDI BLOG VINCITORI E VINTI, INSIEME AL MALAVITOSO = STEFANO BASSI DI FREGA SOLDI BLOG IL GRANDE BLUFF, INSIEME AL MALAVITOSO FE= DERICO IZZI, NOTO COME "ER ZIOROMOLO DELLA CAMORRA", LI VEDETE TUTTI IN FOT= O QUI https://3.bp.blogspot.com/-6WRXJQbHe08/WSBR0uTrMLI/AAAAAAAAY2g/L8c3w9= GGr3wpG7yWxBBeOohzhWa7iJ7uQCLcB/s1600/18558610_10156258698827281_4591948382= 498991167_o.jpg ) 2 CHECK EVERY DETAIL BOUT IT, HERE AVETE MIGLIA DI DETTAGLI E PROVE QUI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit 3 IL PEDERASTA OMICIDA PAOLO BARRAI =C3=89 ANCHE DI UNO DEI PRINICIPALI CRIMI= NALI UNENTI NDRANGHETA E MASSONERIA. =C3=89 DA SEMPRE UN CAPO SANTISTA (OSS= IA NDRANGHETISTA MASSONE). INFATTI ERA PAPPA E CICCIA CON L'ARRESTATO MASSO= NE NDRANGHETISTA BERLUSCONICCHIO GIANCARLO PITTELLI (http://www.iacchite.bl= og/giancarlo-pittelli-laffarista-massone-dei-boss-della-ndrangheta/ ). ED E= RA CICCIA E PAPPA PURE CON GRAN PARTE DEI 334 MASSONI NDRANGHETISTI ARRESTA= TI DAL GRANDE PM NICOLA GRATTERI NEL DICEMBRE 2019 ( https://www.ilprimaton= azionale.it/cronaca/ndrangheta-334-arresti-onorevoli-massoni-colonnello-cos= che-140387/ ). MI PRESENTO. SONO IL RIVOLUZIONARIO A FINI DI BENE: ANDREAS NIGG , VICE PRESIDENT AND HE= AD OF ASSET MANAGEMENT. PRESSO SAFRA-SARASIN BANK ZURICH PRIMA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK VONTOBEL ZURI= CH. https://citywireselector.com/manager/andreas-nigg/d2395 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTER = BANK ZURICH DEL MASSONE LEGHISTA E NAZISTA CARLO PESENTI (NOTO PARTNER OMOS= ESSUALE DEL SATANISTA MASSONE FEDERICO TRABUCCO DI KAIROS). ED IO IN PERSON= A, ANDREAS NIGG, ORDINAI SUBITO DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI = A STA BESTIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO IL= 28.6.1965. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA, CAMORRA, PEDOFI= LO STRAGISTA SILVIO BERLUSCONI, LESBICA PEDOFILA ASSASSINA MARINA BERLUSCON= I E 49 MILIONI DI =E2=82=AC RUBATI DA LEGA LADRONA, DA LONTANO 3.000 KM (NO= N SONO ANTI OMOSESSUALI O LESBICHE, MA ODIO L'IPOICRSIA E LA MAFIOSA OMERT= =C3=81 CHE DA SEMPRE REGNA IN ITALIA, LA MIA RIVOLUZIONE, LA RIVOLUZIONE DI= ANDREAS NIGG DI BANK SAFRA SARASIN ZURICH, RADER=C3=81 A ZERO STA BERLUSCO= NICCHIA IPOCRISIA ED OMERT=C3=81 PUZZOLENTE, ALLA BASE DI OGNI MALE, NEL PA= ESE DEL GRANDE SANDRO PERTINI)! E NON SCORDIAMO CHE IL LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN B= ORSA, AZZERANTE I RISPARMI DI TUTTI E SEMPRE, PAOLO PIETRO BARRAI =C3=89 PU= RE UN NAZI=E5=8D=90STALKER VIA INTERNET, AIZZATORE DI SUICIDI, MANDANTE DI = OMICIDI, E TORTURATORE OMICIDA! OLTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE I= N CARCERE" ( IN UN PRIMO CASO, A SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE= EFFETTUAVA IN CITIBANK, COME DA FINALE DI QUESTO ARTICOLO https://ricerca.= repubblica.it/repubblica/archivio/repubblica/2001/02/19/maxi-evasione-da-40= 0-miliardi-terenzio-sotto-torchio.html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ HA FATTO 66 (DI PROPOSITO NUMERO SATANICO) FILM PORNO CON CAVALLI E BAMBINI= , BEVENDO SPERMA EQUINO ED INCULANDO PURE A MORTE, BAMBINI SU BAMBINI https://groups.google.com/g/comp.lang.python/c/aRdLu8PIHXg 4 =C3=89 STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 EURO, PER = MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.bluerating.co= m/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-che-ha-vio= lato-gli-obblighi-informativi SNIFFAVA CHILI DI COCAINA E STUPRAVA RAGAZZINE COL SERIAL RAPIST ALBERTO GE= NOVESE (ENTRAMBI SON PARTI DI CRIMINALISSIMA LOGGIA DEL DRAGO DEL PEDOFILO = SPAPPOLA MAGISTRATI SILVIO BERLUSCONI) https://www.fanpage.it/milano/story/alberto-genovese-arrestato/ https://www.ilfattoquotidiano.it/2021/01/26/alberto-genovese-dichiarava-red= diti-da-dipendente-proseguono-gli-accertamenti-fiscali-su-imprenditore-accu= sato-di-stupro/6078470/ EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html Vada costui a a riciclare soldi mafiosi o rubati da Lega Ladrona, dal figli= o di troiaccia criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato L= ugano, dal figlio di troiaccia criminalissimo Daniele Albisetti di Banca de= llo Stato Lugano, dal figlio di troiaccia criminalissimo Claudio Genasci di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Patrick L= afranchi di Banca dello Stato Lugano, dal figlio di troiaccia criminalissim= o Gabriele Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! Per finire ribadisco Quando come Vontobel Bank Zurich, abbiamo comprato Finter Bank Zurich, dai = massoni leghisti e nazifascisti Pesenti, immediatamente abbiamo chiuso tutt= i i conti connessi, al, tanto quanto, massone leghista nazifascista, nonche= ' famoso ladro, truffatore, azzera risparmi di ognuno che gli abbocca via i= nternet e non solo, nonch=C3=A9 pedofilo Paolo Pietro Barrai ( che venne ca= cciato da Citibank, a fine anni 90, per terrificanti frodi che li effettuav= a, come da finale di questo articolo https://ricerca.repubblica.it/repubbli= ca/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-so= tto-torchio.html il grande banchiere Giulio Di Cerbo licenzio' in tronco il= verme criminalissimo Paolo Barrai e lo fece condannare al carcere, pochi a= nni dopo, il bastardo nazista e ndranghetista killer Paolo Barrai fece amma= zzare Giulio Di Cerbo, facendo fintamente apparire il tutto come morte natu= rale... il tutto via Massonerie Fasciste e Servizi Segreti Fascisti a cui i= l pedofilo assassino Paolo Pietro Barrai =C3=A9 connessissimo). Di delinque= ntissima Medicalchain, di delinquentissima Cryptolab S A, di delinquentissi= ma Bigbit, di delinquentissima Bitcoin Cryptoeconomy, di delinquentissima B= itincubator & Venture, di delinquentissima Bgbit News Channel e delinquenti= ssima Terra Bitcoin. Attraverso i quali strumenti, lui ed il fallitissimo, = idiota, davvero incapace e fallimentare trader Federico Izzi di Roma (che c= ampa, di fatto, riciclando soldi mafiosi e facendo film pedopornofrafici, t= anto e' vero che sta merda criminale di Federico Izzi di Roma, e' noto sull= e rivere del Tevere, da chiunque, come "Er Zio Romolo incula bambini" e pur= e come "Er Zio Romolo della Camorra") spennano " i polli del web=C2=A8, ven= dendo loro abbonamenti annuali su criptovalute e non solo, totalmente falli= mentari! From newsfish@newsfish Thu Aug 1 00:46:13 2024 X-Received: by 2002:a05:6214:76f:: with SMTP id f15mr11354022qvz.56.1614987794066; Fri, 05 Mar 2021 15:43:14 -0800 (PST) X-Received: by 2002:a25:bd12:: with SMTP id f18mr17179141ybk.403.1614987793777; Fri, 05 Mar 2021 15:43:13 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Mar 2021 15:43:13 -0800 (PST) In-Reply-To: <76bd5f91-9335-4428-8755-f2e295bdbba1n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=84.198.244.196; posting-account=0u-_QgoAAABVd19iXB71E2R2Sl8DPf16 NNTP-Posting-Host: 84.198.244.196 References: <3e696401-dcf9-4d05-8ce5-d45283bccc48@googlegroups.com> <76bd5f91-9335-4428-8755-f2e295bdbba1n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a6a5fe1-d6b9-431e-9514-5a7a65778817n@googlegroups.com> Subject: Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CHIAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), LAVA SOLDI OMICIDA A LUGAN From: Andreas Nigg Bank J Safra Sarasin Zurich Injection-Date: Fri, 05 Mar 2021 23:43:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9820 IL LEGHISTA INCULA ED AMMAZZA BAMBINI PAOLO BARRAI (NOTO IN TUTTO IL MONDO = COME IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI MILANO, PRO= CURA DI LUGANO, SCOTLAND YARD LONDRA, FBI NEW YORK, POLICIA CIVIL DI PORTO = SEGURO (BR). 1 AGAIN AND AGAIN IL LEGHISTA PEDERASTA INCULA ED AMMAZZA BAMBINI PAOLO PIETRO BARRAI (NOTO I= N TUTTO IL MONDO COME IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCU= RA DI MILANO, PROCURA DI LUGANO, SCOTLAND YARD LONDRA, FBI NEW YORK E POLIC= IA CIVIL DI PORTO SEGURO (BR). IL TUTTO VIA INTERPOL ED EUROPOL! =C3=89 DAVVERO PEDOFILO ED ASSASSINO: PAOLO BARRAI DI CRIMINALE TERRA BITCO= IN! IL CRIMINALE LEGHISTA LUCA SOSTEGNI, INCARCERATO, SCAPPAVA IN CITATA PO= RTO SEGURO (BR), DOVE L'OMICIDA PAOLO BARRAI HA RICICLATO PARTE DEI 49 MLN = =E2=82=AC RUBATI DA LEGA LADRONA! (ECCONE LE PROVE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 ) =C3=89 TRUFFATORE, PEDOFILO E KILLER: PAOLO BARRAI, NATO A MILANO IL 28.6.1= 965 ( O TRUFFATORE, PEDOFILO E KILLER: PAOLO PIETRO BARRAI, NATO A MILANO I= L 28.6.1965). DI CRIMINALE TERRA BITCOIN (ASSOCIAZIONE CON INTENTO DI FOTTE= RE, FREGARE, SPENNARE POLLI VIA INTERNET, IL TUTTO VIA TELEGRAM) E CRIMINAL= ISSIMO BLOG MERCATO LIBERO, ALIAS "MERDATO" LIBERO! INDAGATO, AL MOMENTO, D= ALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YARD= LONDRA E DA FBI NEW YORK. HA RICICLATO 21 MLN ASSASSINI DI NDRANGHETA, IN FALLENTISSIMA ICO EIDOO (IN= SIEME AL MALAVITOSO NATALE FERRARA DI REGGIO CALABRIA, DA DECENNI PUNCIUTO,= OSSIA AFFILIATO UFFICIALMENTE ALLA NDRANGHETA, INSIEME AL MALAVITOSO PAOLO= CARDEN=C3=81 DI FREGA SOLDI BLOG VINCITORI E VINTI, INSIEME AL MALAVITOSO = STEFANO BASSI DI FREGA SOLDI BLOG IL GRANDE BLUFF, INSIEME AL MALAVITOSO FE= DERICO IZZI, NOTO COME "ER ZIOROMOLO DELLA CAMORRA", LI VEDETE TUTTI IN FOT= O QUI https://3.bp.blogspot.com/-6WRXJQbHe08/WSBR0uTrMLI/AAAAAAAAY2g/L8c3w9= GGr3wpG7yWxBBeOohzhWa7iJ7uQCLcB/s1600/18558610_10156258698827281_4591948382= 498991167_o.jpg ) 2 CHECK EVERY DETAIL BOUT IT, HERE AVETE MIGLIA DI DETTAGLI E PROVE QUI https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-bl= ockchain-invest/ https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-cripto= -elvetiche/ https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e-s= vizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit 3 IL PEDERASTA OMICIDA PAOLO BARRAI =C3=89 ANCHE DI UNO DEI PRINICIPALI CRIMI= NALI UNENTI NDRANGHETA E MASSONERIA. =C3=89 DA SEMPRE UN CAPO SANTISTA (OSS= IA NDRANGHETISTA MASSONE). INFATTI ERA PAPPA E CICCIA CON L'ARRESTATO MASSO= NE NDRANGHETISTA BERLUSCONICCHIO GIANCARLO PITTELLI (http://www.iacchite.bl= og/giancarlo-pittelli-laffarista-massone-dei-boss-della-ndrangheta/ ). ED E= RA CICCIA E PAPPA PURE CON GRAN PARTE DEI 334 MASSONI NDRANGHETISTI ARRESTA= TI DAL GRANDE PM NICOLA GRATTERI NEL DICEMBRE 2019 ( https://www.ilprimaton= azionale.it/cronaca/ndrangheta-334-arresti-onorevoli-massoni-colonnello-cos= che-140387/ ). MI PRESENTO. SONO IL RIVOLUZIONARIO A FINI DI BENE: ANDREAS NIGG , VICE PRESIDENT AND HE= AD OF ASSET MANAGEMENT. PRESSO SAFRA-SARASIN BANK ZURICH PRIMA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK VONTOBEL ZURI= CH. https://citywireselector.com/manager/andreas-nigg/d2395 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTER = BANK ZURICH DEL MASSONE LEGHISTA E NAZISTA CARLO PESENTI (NOTO PARTNER OMOS= ESSUALE DEL SATANISTA MASSONE FEDERICO TRABUCCO DI KAIROS). ED IO IN PERSON= A, ANDREAS NIGG, ORDINAI SUBITO DI CHIUDERE TUTTI I CONTI BANCARI CONNESSI = A STA BESTIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO PIETRO BARRAI, NATO A MI= LANO IL 28.6.1965. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA, CAMORRA,= PEDOFILO STRAGISTA SILVIO BERLUSCONI, LESBICA PEDOFILA ASSASSINA MARINA BE= RLUSCONI E 49 MILIONI DI =E2=82=AC RUBATI DA LEGA LADRONA? DA LONTANO 3.000= KM (NON SONO ANTI OMOSESSUALI O LESBICHE, mA ODIO L'IPOICRISIA E LA MAFIOS= A OMERT=C3=81 CHE DA SEMPRE REGNA IN ITALIA, LA MIA RIVOLUZIONE, LA RIVOLUZ= IONE DI ANDREAS NIGG DI BANK SAFRA SARASIN ZURICH, RADER=C3=81 A ZERO STA B= ERLUSCONICCHIA IPOCRISIA ED OMERT=C3=81 PUZZOLENTE, ALLA BASE DI OGNI MALE,= NEL PAESE DEL GRANDE SANDRO PERTINI)! E NON SCORDIAMO CHE IL LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN B= ORSA, AZZERANTE I RISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI =C3=89 PURE UN N= AZI-ST-ALKER VIA INTERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICIDI, E TOR= TURATORE OMICIDA! OLTRE AD ESSERE STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( I= N UN PRIMO CASO, A SEGUITO DI ENORMI CRIMINALISSIME FRODI CHE EFFETTUAVA IN= CITIBANK, COME DA FINALE DI QUESTO ARTICOLO https://ricerca.repubblica.it/= repubblica/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-ter= enzio-sotto-torchio.html PER POI CONOSCERE ALTRA GALERA ANCHE IN BRASILE E PURE PER PEDOFILIA OMOSES= SUALE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.be/2011/03/quem-e-pietro-paolo-barrai= .html http://www.geraldojose.com.br/mobile/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato/ HA FATTO 66 (DI PROPOSITO NUMERO SATANICO) FILM PORNO CON CAVALLI E BAMBINI= , BEVENDO SPERMA EQUINO ED INCULANDO A SANGUE BAMBINI SU BAMBINI https://groups.google.com/g/comp.lang.python/c/aRdLu8PIHXg 4 =C3=89 STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 EURO, PER = MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.bluerating.co= m/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-che-ha-vio= lato-gli-obblighi-informativi SNIFFAVA CHILI DI COCAINA E STUPRAVA RAGAZZINE COL SERIAL RAPIST ALBERTO GE= NOVESE (ENTRAMBI SON PARTI DI CRIMINALISSIMA LOGGIA DEL DRAGO DEL PEDOFILO = SPAPPOLA MAGISTRATI SILVIO BERLUSCONI) https://www.fanpage.it/milano/story/alberto-genovese-arrestato/ https://www.ilfattoquotidiano.it/2021/01/26/alberto-genovese-dichiarava-red= diti-da-dipendente-proseguono-gli-accertamenti-fiscali-su-imprenditore-accu= sato-di-stupro/6078470/ EFFETTUA TUTTI QUESTI MOSTRUOSISSIMI CRIMINI INSIEME -AL NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontran= o/ - AL PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI: FEDERICO IZZI DI ROMA (C= RIMINALISSIMO TRADER ZIO ROMOLO) https://groups.google.com/forum/embed/#!topic/comp.soft-sys.sas/MFpSlsDq72M - AL NOTO SATANISTA, LADRONE, TRUFFATORE, PEDOFILO ECONOMISTA PAOLO CARDEN= =C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html Vada costui a a riciclare soldi mafiosi o rubati da Lega Ladrona, dal figli= o di troiaccia criminalissimo Fabrizio Cieslakiewicz di Banca dello Stato L= ugano, dal figlio di troiaccia criminalissimo Daniele Albisetti di Banca de= llo Stato Lugano, dal figlio di troiaccia criminalissimo Claudio Genasci di= Banca dello Stato Lugano, dal figlio di troiaccia criminalissimo Patrick L= afranchi di Banca dello Stato Lugano, dal figlio di troiaccia criminalissim= o Gabriele Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!! Per finire ribadisco Quando come Vontobel Bank Zurich, abbiamo comprato Finter Bank Zurich, dai = massoni leghisti e nazifascisti Pesenti, immediatamente abbiamo chiuso tutt= i i conti connessi, al, tanto quanto, massone leghista nazifascista, nonche= ' famoso ladro, truffatore, azzera risparmi di ognuno che gli abbocca via i= nternet e non solo, nonch=C3=A9 pedofilo Paolo Pietro Barrai ( che venne ca= cciato da Citibank, a fine anni 90, per terrificanti frodi che li effettuav= a, come da finale di questo articolo https://ricerca.repubblica.it/repubbli= ca/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-so= tto-torchio.html il grande banchiere Giulio Di Cerbo licenzio' in tronco il= verme criminalissimo Paolo Barrai e lo fece condannare al carcere, pochi a= nni dopo, il bastardo nazista e ndranghetista killer Paolo Barrai fece amma= zzare Giulio Di Cerbo, facendo fintamente apparire il tutto come morte natu= rale... il tutto via Massonerie Fasciste e Servizi Segreti Fascisti a cui i= l pedofilo assassino Paolo Pietro Barrai =C3=A9 connessissimo). Di delinque= ntissima Medicalchain, di delinquentissima Cryptolab S A, di delinquentissi= ma Bigbit, di delinquentissima Bitcoin Cryptoeconomy, di delinquentissima B= itincubator & Venture, di delinquentissima Bgbit News Channel e delinquenti= ssima Terra Bitcoin. Attraverso i quali strumenti, lui ed il fallitissimo, = idiota, davvero incapace e fallimentare trader Federico Izzi di Roma (che c= ampa, di fatto, riciclando soldi mafiosi e facendo film pedopornofrafici, t= anto e' vero che sta merda criminale di Federico Izzi di Roma, e' noto sull= e rivere del Tevere, da chiunque, come "Er Zio Romolo incula bambini" e pur= e come "Er Zio Romolo della Camorra") spennano " i polli del web=C2=A8, ven= dendo loro abbonamenti annuali su criptovalute e non solo, totalmente falli= mentari! A fra non molto via altri miei miliardi di scritti che preparer=C3=B3! On Monday, February 1, 2021 at 12:15:24 AM UTC+1, Andreas Nigg Bank J Safra= Sarasin Zurich wrote: > On Friday, November 9, 2018 at 9:12:26 PM UTC+1, pippot...@outlook.com wr= ote:=20 > > FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME LO CH= IAMANO IN TUTTO IL MONDO). COL FIDUCIARIO DI NDRANGHETA, OLIVER CAMPONOVO, = E COL PORCO BRUCIA RISPARMI, FEDERICO IZZI (CRIMINALE TRADER ZIO ROMOLO), L= AVA SOLDI OMICIDA A LUGANO!=20 > >=20 > > Appena abbiamo comprato Finter Bank Zurich dai massoni nazifascisti Pes= enti, immediatamente abbiamo chiuso tutti i conti connessi, al, tanto quant= o, massone nazifascista, nonche' famosissimo ladro, truffatore, azzera risp= armi di ognuno che gli abbocca via iternet e non solo, nonche' criminalissi= mo pedofilo Paolo Barrai. Di delinquentissima Bigbit, delinquentissima Bgbi= t News Channel e delinquentissima @bigbitnewschannel. Attraverso i quali st= rumenti, lui ed il fallitissimo, idiota, davvero deficente, incapace, falli= mentare trader Federico Izzi di Roma (che campa, di fatto, riciclando soldi= mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merda crimi= nalissima di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da chi= unque, come "Er Zio Romolo incula bambini e pure come Er Zio Romolo della C= amorra"). Sti due pezzi di merda criminalissimi spennano " i polli del web= =C2=A8, vendendo loro abbonamenti annuali su criptovalute e non solo, total= mente fallimentari ( delinquentissimo servizio chiamato Bigbit)=20 > > Che ti fan perdere tutti, tutti, e di nuovo tutti i risparmi ( posso mo= strarvi centinaia di casi, venuti, disperati, a piangersene da me, a propos= ito). Insieme al figlio di puttana Natale Ferrara di Reggio Calabria, uno s= carafaggio della Ndrangheta ( e di fallimentarissima Eidoo). Si, proprio co= si', insieme al figlio di puttana Natale Massimiliano Ferrara di Reggio Cal= abria, uno scarafaggio della Ndrangheta ( e di fallimentarissima Eidoo). Im= boscatosi qui in Svizzera, per non finire in galera, ben appunto, a Reggio = Calabria. Che ha rifilato a la merda di Ico completamente fallimentare chia= mata Eidoo, crollata da 7 dollari a 0.60 dollari. Ora, l'altrettanto merdon= e nazipedofilo Donald Trump sta cercando di tirargli su detta merda, il tut= to, ovviamente, mentre lo stesso nazipedofilo merdone Donald Trump, tira su= , come al solito, anche, i suoi tre grammi giornalieri di cocaina, presso l= a White "Powder" House) . Torniamo in ogni caso, ora, al punto iniziale, bi= tte. Appena noi di Bank Vontobel Zurich abbiamo comprato Finter Bank, abbia= mo cacciato immediatamente il ladrone, truffatore, pure mandante di omicidi= e notissimo pedofilo Paolo Barrai nato a Milano il 28.6.1965 ( o ladrone, = truffatore, pure mandante di omicidi e notissimo pedofilo Paolo Pietro Barr= ai nato a Milano il 28.6.1965), dalla lista di nostri Banking Intermediarie= s. Fra i tantissimi crimini che lo stesso effettua, per noi banchieri svizz= eri, il piu' in vista e' che lo stesso lava, lava, lava soldi assassini per= la Mafia ( insieme al figlio di troia delinquentissimo Oliver Camponovo, n= oto fiduciario di ndrangheta)!=20 > > Come anche, lava soldi rubati o frutti di mega mazzette in connessione = a Lega Ladrona ( famosi 49 milioni fregati allo stato di "Berlusconia" e no= n solo). Come dell'altrettanto pedofilo squarta magistrati Silvio Berluscon= i ( il tutto insieme a quel criminale assoluto, truffatore, azzera risparmi= altrui, ricicla proventi assassini e mega pedofilo Federico Izzi di Roma p= rima menzionato, noto, non per niente, in tutto il capoluogo laziale, sia c= ome "Er Zio Romolo incula bambini, che come Er Zio Romolo della Camorra"). = Niente merda nella nuova Finter Bank Zurich. Il puzzo della merda, scusate = il temine, si attacca ai vestiti. Vadano costoro a riciclare i loro soldi m= ega omicida dal figlio di puttana criminalissimo Fabrizio Cieslakiewicz di = Banca dello Stato Lugano, dal figlio di puttana criminalissimo Daniele Albi= setti di Banca dello Stato Lugano, dal figlio di puttana criminalissimo Cla= udio Genasci di Banca dello Stato Lugano, dal figlio di puttana criminaliss= imo Patrick Lafranchi di Banca dello Stato Lugano, dal figlio di puttana cr= iminalissimo Gabriele Zanzi di Banca dello Stato Lugano! Vielen Danke, Ya!!= !=20 > > ANDREAS NIGG. ORA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO S= AFRA-SARASIN ZURICH. > IL LEGHISTA NAZISTA ED ASSASSINO PAOLO BARRAI (NOTO IN TUTTO IL MONDO COM= E IL PEDOFILO DEL BITCOIN) E' DA ANNI INDAGATO DA PROCURA DI MILANO, COME P= URE DA PROCURA DI LUGANO, DA SCOTLAND YARD LONDRA, DA FBI NEW YORK E POLICI= A CIVIL DI PORTO SEGURO (BRASILE). IL TUTTO VIA INTERPOL ED EUROPOL!=20 > 1=20 > =C3=89 DAVVERO PEDOFILO ED ASSASSINO: PAOLO BARRAI DI CRIMINALE TERRA BIT= COIN! IL CRIMINALE LEGHISTA LUCA SOSTEGNI, INCARCERATO, SCAPPAVA IN CITATA = PORTO SEGURO (BR), DOVE L'OMICIDA PAOLO BARRAI HA RICICLATO PARTE DEI 49 ML= N =E2=82=AC RUBATI DA LEGA LADRONA!=20 >=20 > (ECCONE LE PROVE=20 > https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelistecivich= e.jpg=20 > http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-bar= rai.html=20 > https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 )=20 >=20 > =C3=89 TRUFFATORE, PEDOFILO E KILLER: PAOLO BARRAI, NATO A MILANO IL 28.6= .1965 ( O TRUFFATORE, PEDOFILO E KILLER: PAOLO PIETRO BARRAI, NATO A MILANO= IL 28.6.1965). DI CRIMINALE TERRA BITCOIN (ASSOCIAZIONE CON INTENTO DI FOT= TERE, FREGARE, SPENNARE POLLI VIA INTERNET, IL TUTTO VIA TELEGRAM) E CRIMIN= ALISSIMO BLOG MERCATO LIBERO, ALIAS "MERDATO" LIBERO! INDAGATO, AL MOMENTO,= DALLA PROCURA DI MILANO. COME PURE DALLA PROCURA DI LUGANO, DA SCOTLAND YA= RD LONDRA E DA FBI NEW YORK.=20 >=20 > HA RICICLATO 21 MLN ASSASSINI DI NDRANGHETA, IN FALLENTISSIMA ICO EIDOO (= INSIEME AL MALAVITOSO NATALE FERRARA DI REGGIO CALABRIA, DA DECENNI PUNCIUT= O, OSSIA AFFILIATO UFFICIALMENTE ALLA NDRANGHETA, INSIEME AL MALAVITOSO PAO= LO CARDEN=C3=81 DI FREGA SOLDI BLOG VINCITORI E VINTI, INSIEME AL MALAVITOS= O STEFANO BASSI DI FREGA SOLDI BLOG IL GRANDE BLUFF, INSIEME AL MALAVITOSO = FEDERICO IZZI, NOTO COME "ER ZIOROMOLO DELLA CAMORRA", LI VEDETE TUTTI IN F= OTO QUI https://3.bp.blogspot.com/-6WRXJQbHe08/WSBR0uTrMLI/AAAAAAAAY2g/L8c3= w9GGr3wpG7yWxBBeOohzhWa7iJ7uQCLcB/s1600/18558610_10156258698827281_45919483= 82498991167_o.jpg )=20 >=20 > 2=20 > CHECK EVERY DETAIL BOUT IT, HERE > https://valori.it/nel-dedalo-delle-criptovalute-i-nomi-eccellenti-dentro-= blockchain-invest/=20 >=20 > https://valori.it/chiasso-dove-riciclatori-ndrine-e-criptovalute-sincontr= ano/=20 >=20 > https://valori.it/banche-politica-blogger-tutti-gli-affari-dietro-le-crip= to-elvetiche/=20 >=20 > https://valori.it/criptovalute-quei-fondi-in-viaggio-tra-italia-irlanda-e= -svizzera/=20 >=20 > https://it.coinidol.com/mafie-usano-bitcoin/=20 >=20 > https://coinidol.com/mafias-use-bitcoin/=20 >=20 > https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-cry= pto/ > https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA= _RTFow/edit=20 >=20 > 3=20 > IL PEDERASTA OMICIDA PAOLO BARRAI =C3=89 ANCHE DI UNO DEI PRINICIPALI CRI= MINALI UNENTI NDRANGHETA E MASSONERIA. =C3=89 DA SEMPRE UN CAPO SANTISTA (O= SSIA NDRANGHETISTA MASSONE). INFATTI ERA PAPPA E CICCIA CON L'ARRESTATO MAS= SONE NDRANGHETISTA BERLUSCONICCHIO GIANCARLO PITTELLI (http://www.iacchite.= blog/giancarlo-pittelli-laffarista-massone-dei-boss-della-ndrangheta/ ). ED= ERA CICCIA E PAPPA PURE CON GRAN PARTE DEI 334 MASSONI NDRANGHETISTI ARRES= TATI DAL GRANDE PM NICOLA GRATTERI NEL DICEMBRE 2019 ( https://www.ilprimat= onazionale.it/cronaca/ndrangheta-334-arresti-onorevoli-massoni-colonnello-c= osche-140387/ ).=20 >=20 > MI PRESENTO.=20 >=20 > SONO IL RIVOLUZIONARIO A FINI DI BENE: ANDREAS NIGG VICE PRESIDENT AND HE= AD OF ASSET MANAGEMENT. PRESSO SAFRA-SARASIN BANK ZURICH=20 >=20 > PRIMA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK VONTOBEL ZU= RICH.=20 >=20 > https://citywireselector.com/manager/andreas-nigg/d2395=20 >=20 > QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTE= R BANK ZURICH DEL MASSONE LEGHISTA E NAZISTA CARLO PESENTI (NOTO PARTNER OM= OSESSUALE DEL SATANISTA MASSONE FEDERICO TRABUCCO DI KAIROS). ED IO IN PERS= ONA, ANDREAS NIGG, ORDINAI SUBITO DI CHIUDERE TUTTI I CONTI BANCARI CONNESS= I A STA BESTIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO BARRAI, NATO A MILANO = IL 28.6.1965. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA NOSTRA, CAMORRA, PEDO= FILO STRAGISTA SILVIO BERLUSCONI, LESBICA PEDOFILA ASSASSINA MARINA BERLUSC= ONI E 49 MILIONI DI =E2=82=AC RUBATI DA LEGA LADRONA? DA LONTANO 3.000 KM (= NON SONO ANTI OMOSESSUALI O LESBICHE, mA ODIO L'IPOICRISIA E LA MAFIOSA OME= RT=C3=81 CHE DA SEMPRE REGNA IN ITALIA, LA MIA RIVOLUZIONE, LA RIVOLUZIONE = DI ANDREAS NIGG DI BANK SAFRA SARASIN ZURICH, RADER=C3=81 A ZERO STA BERLUS= CONICCHIA IPOCRISIA ED OMERT=C3=81 PUZZOLENTE, ALLA BASE DI OGNI MALE, NEL = PAESE DEL GRANDE SANDRO PERTINI)!=20 >=20 > HO ALTRE TONNELLATE DI COSE DA SCRIVERE SU STO PEDOFILO ASSASSINO, LAVA S= OLDI CRIMINALI E NAZIRAZZISTA DI PAOLO BARRAI, MA LO FAR=C3=93 CON CALMA ED= ATTRAVERSO ALTRI MILIONI DI MIEI SCRITTI. ORA DEVO VINCERE NEI MERCATI PER= SAFRA-SARASIN BANK ZURICH. HASTA LA VISTORIA SIEMPRE.=20 > (VICTORIA NON COMUNISTA, MA ALLA VINCENTISSIMO ... CI SIAMO CAPITI)=20 > ANDREAS NIGG. SAFRA-SARASIN BANK ZURICH.=20 > 4=20 > Anzi, meglio ribadire...=20 > Quando come Vontobel Bank Zurich, abbiamo comprato Finter Bank Zurich, da= i massoni leghisti e nazifascisti Pesenti, immediatamente abbiamo chiuso tu= tti i conti connessi, al, tanto quanto, massone leghista nazifascista, nonc= he' famoso ladro, truffatore, azzera risparmi di ognuno che gli abbocca via= internet e non solo, nonch=C3=A9 pedofilo Paolo Pietro Barrai ( che venne = cacciato da Citibank, a fine anni 90, per terrificanti frodi che li effettu= ava, come da finale di questo articolo https://ricerca.repubblica.it/repubb= lica/archivio/repubblica/2001/02/19/maxi-evasione-da-400-miliardi-terenzio-= sotto-torchio.html il grande banchiere Giulio Di Cerbo licenzio' in tronco = il verme criminalissimo Paolo Barrai e lo fece condannare al carcere, pochi= anni dopo, il bastardo nazista e ndranghetista killer Paolo Barrai fece am= mazzare Giulio Di Cerbo, facendo fintamente apparire il tutto come morte na= turale... il tutto via Massonerie Fasciste e Servizi Segreti Fascisti a cui= il pedofilo assassino Paolo Pietro Barrai =C3=A9 connessissimo). Di delinq= uentissima Medicalchain, di delinquentissima Cryptolab S A, di delinquentis= sima Bigbit, di delinquentissima Bitcoin Cryptoeconomy, di delinquentissima= Bitincubator & Venture, di delinquentissima Bgbit News Channel e delinquen= tissima Terra Bitcoin. Attraverso i quali strumenti, lui ed il fallitissimo= , idiota, davvero incapace e fallimentare trader Federico Izzi di Roma (che= campa, di fatto, riciclando soldi mafiosi e facendo film pedopornofrafici,= tanto e' vero che sta merda criminale di Federico Izzi di Roma, e' noto su= lle rivere del Tevere, da chiunque, come "Er Zio Romolo incula bambini" e p= ure come "Er Zio Romolo della Camorra") spennano " i polli del web=C2=A8, v= endendo loro abbonamenti annuali su criptovalute e non solo, totalmente fal= limentari!=20 > A fra non molto via altri miei miliardi di scritti che preparer=C3=B3!=20 > ANDREAS NIGG. SAFRA-SARASIN BANK ZURICH. From newsfish@newsfish Thu Aug 1 00:46:13 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!feeds.news.ox.ac.uk!news.ox.ac.uk!2.eu.feeder.erje.net!feeder.erje.net!feeder1.feed.usenet.farm!feed.usenet.farm!news-out.netnews.com!news.alt.net!fdc3.netnews.com!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!fx46.ams4.POSTED!not-for-mail Newsgroups: comp.lang.vhdl X-Mozilla-News-Host: news://news.virginmedia.com:119 Reply-To: hans64@htminuslab.com From: HT-Lab Subject: Kudos to Sigasi User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Antivirus: Avast (VPS 210317-0, 17/03/2021), Outbound message X-Antivirus-Status: Clean Lines: 16 Message-ID: <0gJ4I.93945$hcZe.23159@fx46.ams4> X-Complaints-To: http://netreport.virginmedia.com NNTP-Posting-Date: Thu, 18 Mar 2021 14:15:24 UTC Organization: virginmedia.com Date: Thu, 18 Mar 2021 14:15:23 +0000 X-Received-Bytes: 1368 Xref: reader02.eternal-september.org comp.lang.vhdl:9821 Sigasi 4.11 now supports a few VHDL2019 constructs, see this link: https://insights.sigasi.com/releasenotes/sigasi-4.11/ Kudos to Sigasi for this! I have heard rumours Synplicity/Synopsys is planning to support some VHDL2019 constructs, does anybody know what they are planning to support? For the few people on this list, keep pestering your EDA vendor for VHDL2019 support, simply tell them which feature you would like to see added. Regards, Hans www.ht-lab.com From newsfish@newsfish Thu Aug 1 00:46:14 2024 X-Received: by 2002:ac8:5cc4:: with SMTP id s4mr4542851qta.214.1616085941895; Thu, 18 Mar 2021 09:45:41 -0700 (PDT) X-Received: by 2002:a25:d6d5:: with SMTP id n204mr324712ybg.22.1616085941664; Thu, 18 Mar 2021 09:45:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Mar 2021 09:45:41 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=82.56.72.233; posting-account=RpGzdQoAAADW-lmCFe4bg6IYXbbUpTkq NNTP-Posting-Host: 82.56.72.233 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <441a6f60-1dc3-41b0-94f1-fda0db9ebf81n@googlegroups.com> Subject: Multiple Drive Error From: =?UTF-8?Q?Ceyhun_Sar=C4=B1kaya?= Injection-Date: Thu, 18 Mar 2021 16:45:41 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9822 Hi I am getting this error. My block design is this (https://www.linkpicture.com/q/Screenshot-2021-03-18-150349.png) I think needs to be added Mux in FIFO port map. How could I add MUX inside of this code? Thank you so much Regards My scripts like that; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; Library UNISIM; use UNISIM.vcomponents.all; entity myip_v1_0 is generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S00_AXI C_S00_AXI_DATA_WIDTH : integer := 32; C_S00_AXI_ADDR_WIDTH : integer := 5 ); port ( -- Users to add ports here aclk : in std_logic; aresetn : in std_logic; SR0 : in std_logic_vector(31 downto 0); SR1 : in std_logic_vector(31 downto 0); sw_rst : out std_logic; CR0 : out std_logic_vector(31 downto 0); CR1 : out std_logic_vector(31 downto 0); -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S00_AXI s00_axi_aclk : in std_logic; s00_axi_aresetn : in std_logic; s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); s00_axi_awprot : in std_logic_vector(2 downto 0); s00_axi_awvalid : in std_logic; s00_axi_awready : out std_logic; s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); s00_axi_wvalid : in std_logic; s00_axi_wready : out std_logic; s00_axi_bresp : out std_logic_vector(1 downto 0); s00_axi_bvalid : out std_logic; s00_axi_bready : in std_logic; s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); s00_axi_arprot : in std_logic_vector(2 downto 0); s00_axi_arvalid : in std_logic; s00_axi_arready : out std_logic; s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); s00_axi_rresp : out std_logic_vector(1 downto 0); s00_axi_rvalid : out std_logic; s00_axi_rready : in std_logic ); end myip_v1_0; architecture arch_imp of myip_v1_0 is -- component declaration component myip_v1_0_S00_AXI is generic ( C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 5 ); port ( -- Users to add ports here aclk : in std_logic; aresetn : in std_logic; SR0 : in std_logic_vector(31 downto 0); SR1 : in std_logic_vector(31 downto 0); sw_rst : out std_logic; CR0 : out std_logic_vector(31 downto 0); CR1 : out std_logic_vector(31 downto 0); -- User ports ends -- Do not modify the ports beyond this line S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic ); end component myip_v1_0_S00_AXI; COMPONENT DEC_FIFO_32X16 PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; signal fifo_DEC_FIFO_32X16_din : STD_LOGIC_VECTOR(31 DOWNTO 0); signal fifo_DEC_FIFO_32X16_dout : STD_LOGIC_VECTOR(31 DOWNTO 0); -- signal aclk : std_logic; -- signal aresetn : std_logic; -- signal SR0 : std_logic_vector(31 downto 0); -- signal SR1 : std_logic_vector(31 downto 0); -- signal sw_rst : std_logic; -- signal CR0 : std_logic_vector(31 downto 0); -- signal CR1 : std_logic_vector(31 downto 0); signal S0_fifo_full : std_logic; signal S0_fifo_empty : std_logic; signal C0_fifo_full : std_logic; signal C0_fifo_empty : std_logic; signal S1_fifo_full : std_logic; signal S1_fifo_empty : std_logic; signal C1_fifo_full : std_logic; signal C1_fifo_empty : std_logic; signal aresetn_d0 : std_logic := '0'; signal aresetn_d1 : std_logic := '0'; signal axi_aresetn_d0 : std_logic := '0'; signal axi_aresetn_d1 : std_logic := '0'; signal sw_rst_d0 : std_logic := '0'; signal sw_rst_d1 : std_logic := '0'; begin -- Instantiation of Axi Bus Interface S00_AXI myip_v1_0_S00_AXI_inst : myip_v1_0_S00_AXI generic map ( C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH ) port map ( aclk => aclk , aresetn => aresetn, SR0 => SR0, SR1 => SR1, sw_rst => sw_rst, CR0 => CR0, CR1 => CR1, S_AXI_ACLK => s00_axi_aclk, S_AXI_ARESETN => s00_axi_aresetn, S_AXI_AWADDR => s00_axi_awaddr, S_AXI_AWPROT => s00_axi_awprot, S_AXI_AWVALID => s00_axi_awvalid, S_AXI_AWREADY => s00_axi_awready, S_AXI_WDATA => s00_axi_wdata, S_AXI_WSTRB => s00_axi_wstrb, S_AXI_WVALID => s00_axi_wvalid, S_AXI_WREADY => s00_axi_wready, S_AXI_BRESP => s00_axi_bresp, S_AXI_BVALID => s00_axi_bvalid, S_AXI_BREADY => s00_axi_bready, S_AXI_ARADDR => s00_axi_araddr, S_AXI_ARPROT => s00_axi_arprot, S_AXI_ARVALID => s00_axi_arvalid, S_AXI_ARREADY => s00_axi_arready, S_AXI_RDATA => s00_axi_rdata, S_AXI_RRESP => s00_axi_rresp, S_AXI_RVALID => s00_axi_rvalid, S_AXI_RREADY => s00_axi_rready ); -- Add user logic here CDC_aclk_to_s00_axi_aclk: process (s00_axi_aclk) begin if rising_edge(s00_axi_aclk) then aresetn_d0 <= aresetn; aresetn_d1 <= aresetn_d0; end if; end process CDC_aclk_to_s00_axi_aclk; CDC_s00_axi_aclk_to_aclk: process (aclk) begin if rising_edge(aclk) then axi_aresetn_d0 <= s00_axi_aresetn; axi_aresetn_d1 <= axi_aresetn_d0; -- --sw_rst_d0 <= sw_rst; --sw_rst_d1 <= sw_rst_d0; end if; end process CDC_s00_axi_aclk_to_aclk; SR0_fifo : DEC_FIFO_32X16 PORT MAP ( rst => '0', wr_clk => aclk, rd_clk => s00_axi_aclk, din => SR0, wr_en => aresetn, rd_en => aresetn_d1, dout => CR0, full => S0_fifo_full, empty => S0_fifo_empty ); SR1_fifo : DEC_FIFO_32X16 PORT MAP ( rst => '0', wr_clk => aclk, rd_clk => s00_axi_aclk, din => SR1, wr_en => aresetn, rd_en => aresetn_d1, dout => CR1, full => S1_fifo_full, empty => S1_fifo_empty ); CR0_fifo : DEC_FIFO_32X16 PORT MAP ( rst => '0', wr_clk => s00_axi_aclk, rd_clk => aclk, din => SR0, wr_en => s00_axi_aresetn, rd_en => axi_aresetn_d1, dout => CR0, full => C0_fifo_full, empty => C0_fifo_empty ); CR1_fifo : DEC_FIFO_32X16 PORT MAP ( rst => '0', wr_clk => s00_axi_aclk, rd_clk => aclk, din => SR1, wr_en => s00_axi_aresetn, rd_en => axi_aresetn_d1, dout => CR1, full => C1_fifo_full, empty => C1_fifo_empty ); --aclk <= aclk; -- aresetn <= aresetn; sw_rst <= sw_rst_d1; end arch_imp; From newsfish@newsfish Thu Aug 1 00:46:14 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!aioe.org!2MYPvZEHKFprtSUDGAiGOA.user.gioia.aioe.org.POSTED!not-for-mail From: Buzz McCool Newsgroups: comp.lang.vhdl Subject: Re: Multiple Drive Error Date: Thu, 18 Mar 2021 13:15:30 -0700 Organization: Aioe.org NNTP Server Lines: 286 Message-ID: References: <441a6f60-1dc3-41b0-94f1-fda0db9ebf81n@googlegroups.com> NNTP-Posting-Host: 2MYPvZEHKFprtSUDGAiGOA.user.gioia.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.0 X-Notice: Filtered by postfilter v. 0.9.2 Content-Language: en-US Xref: reader02.eternal-september.org comp.lang.vhdl:9823 On 3/18/21 9:45 AM, Ceyhun Sarıkaya wrote: > Hi > I am getting this error. > My block design is this (https://www.linkpicture.com/q/Screenshot-2021-03-18-150349.png) > > I think needs to be added Mux in FIFO port map. How could I add MUX inside of this code? You might have more luck asking on Xilinx's web site. Have you read this already? https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Taming-Multiple-Drivers/ba-p/1034745 > My scripts like that; > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > Library UNISIM; > use UNISIM.vcomponents.all; > > entity myip_v1_0 is > generic ( > -- Users to add parameters here > > -- User parameters ends > -- Do not modify the parameters beyond this line > > > -- Parameters of Axi Slave Bus Interface S00_AXI > C_S00_AXI_DATA_WIDTH : integer := 32; > C_S00_AXI_ADDR_WIDTH : integer := 5 > ); > port ( > -- Users to add ports here > aclk : in std_logic; > aresetn : in std_logic; > SR0 : in std_logic_vector(31 downto 0); > SR1 : in std_logic_vector(31 downto 0); > sw_rst : out std_logic; > CR0 : out std_logic_vector(31 downto 0); > CR1 : out std_logic_vector(31 downto 0); > -- User ports ends > > -- Do not modify the ports beyond this line > > > -- Ports of Axi Slave Bus Interface S00_AXI > s00_axi_aclk : in std_logic; > s00_axi_aresetn : in std_logic; > s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); > s00_axi_awprot : in std_logic_vector(2 downto 0); > s00_axi_awvalid : in std_logic; > s00_axi_awready : out std_logic; > s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); > s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); > s00_axi_wvalid : in std_logic; > s00_axi_wready : out std_logic; > s00_axi_bresp : out std_logic_vector(1 downto 0); > s00_axi_bvalid : out std_logic; > s00_axi_bready : in std_logic; > s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); > s00_axi_arprot : in std_logic_vector(2 downto 0); > s00_axi_arvalid : in std_logic; > s00_axi_arready : out std_logic; > s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); > s00_axi_rresp : out std_logic_vector(1 downto 0); > s00_axi_rvalid : out std_logic; > s00_axi_rready : in std_logic > ); > end myip_v1_0; > > architecture arch_imp of myip_v1_0 is > > -- component declaration > component myip_v1_0_S00_AXI is > generic ( > C_S_AXI_DATA_WIDTH : integer := 32; > C_S_AXI_ADDR_WIDTH : integer := 5 > ); > port ( > -- Users to add ports here > aclk : in std_logic; > aresetn : in std_logic; > SR0 : in std_logic_vector(31 downto 0); > SR1 : in std_logic_vector(31 downto 0); > sw_rst : out std_logic; > CR0 : out std_logic_vector(31 downto 0); > CR1 : out std_logic_vector(31 downto 0); > -- User ports ends > -- Do not modify the ports beyond this line > S_AXI_ACLK : in std_logic; > S_AXI_ARESETN : in std_logic; > S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); > S_AXI_AWPROT : in std_logic_vector(2 downto 0); > S_AXI_AWVALID : in std_logic; > S_AXI_AWREADY : out std_logic; > S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); > S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); > S_AXI_WVALID : in std_logic; > S_AXI_WREADY : out std_logic; > S_AXI_BRESP : out std_logic_vector(1 downto 0); > S_AXI_BVALID : out std_logic; > S_AXI_BREADY : in std_logic; > S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); > S_AXI_ARPROT : in std_logic_vector(2 downto 0); > S_AXI_ARVALID : in std_logic; > S_AXI_ARREADY : out std_logic; > S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); > S_AXI_RRESP : out std_logic_vector(1 downto 0); > S_AXI_RVALID : out std_logic; > S_AXI_RREADY : in std_logic > ); > end component myip_v1_0_S00_AXI; > > COMPONENT DEC_FIFO_32X16 > PORT ( > rst : IN STD_LOGIC; > wr_clk : IN STD_LOGIC; > rd_clk : IN STD_LOGIC; > din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); > wr_en : IN STD_LOGIC; > rd_en : IN STD_LOGIC; > dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); > full : OUT STD_LOGIC; > empty : OUT STD_LOGIC > ); > END COMPONENT; > > signal fifo_DEC_FIFO_32X16_din : STD_LOGIC_VECTOR(31 DOWNTO 0); > signal fifo_DEC_FIFO_32X16_dout : STD_LOGIC_VECTOR(31 DOWNTO 0); > > > -- signal aclk : std_logic; > -- signal aresetn : std_logic; > -- signal SR0 : std_logic_vector(31 downto 0); > -- signal SR1 : std_logic_vector(31 downto 0); > -- signal sw_rst : std_logic; > -- signal CR0 : std_logic_vector(31 downto 0); > -- signal CR1 : std_logic_vector(31 downto 0); > > signal S0_fifo_full : std_logic; > signal S0_fifo_empty : std_logic; > > signal C0_fifo_full : std_logic; > signal C0_fifo_empty : std_logic; > > signal S1_fifo_full : std_logic; > signal S1_fifo_empty : std_logic; > > signal C1_fifo_full : std_logic; > signal C1_fifo_empty : std_logic; > > signal aresetn_d0 : std_logic := '0'; > signal aresetn_d1 : std_logic := '0'; > > signal axi_aresetn_d0 : std_logic := '0'; > signal axi_aresetn_d1 : std_logic := '0'; > > signal sw_rst_d0 : std_logic := '0'; > signal sw_rst_d1 : std_logic := '0'; > > > begin > > -- Instantiation of Axi Bus Interface S00_AXI > myip_v1_0_S00_AXI_inst : myip_v1_0_S00_AXI > generic map ( > C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, > C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH > ) > port map ( > aclk => aclk , > aresetn => aresetn, > SR0 => SR0, > SR1 => SR1, > sw_rst => sw_rst, > CR0 => CR0, > CR1 => CR1, > > S_AXI_ACLK => s00_axi_aclk, > S_AXI_ARESETN => s00_axi_aresetn, > S_AXI_AWADDR => s00_axi_awaddr, > S_AXI_AWPROT => s00_axi_awprot, > S_AXI_AWVALID => s00_axi_awvalid, > S_AXI_AWREADY => s00_axi_awready, > S_AXI_WDATA => s00_axi_wdata, > S_AXI_WSTRB => s00_axi_wstrb, > S_AXI_WVALID => s00_axi_wvalid, > S_AXI_WREADY => s00_axi_wready, > S_AXI_BRESP => s00_axi_bresp, > S_AXI_BVALID => s00_axi_bvalid, > S_AXI_BREADY => s00_axi_bready, > S_AXI_ARADDR => s00_axi_araddr, > S_AXI_ARPROT => s00_axi_arprot, > S_AXI_ARVALID => s00_axi_arvalid, > S_AXI_ARREADY => s00_axi_arready, > S_AXI_RDATA => s00_axi_rdata, > S_AXI_RRESP => s00_axi_rresp, > S_AXI_RVALID => s00_axi_rvalid, > S_AXI_RREADY => s00_axi_rready > ); > > -- Add user logic here > > CDC_aclk_to_s00_axi_aclk: process (s00_axi_aclk) > begin > if rising_edge(s00_axi_aclk) then > aresetn_d0 <= aresetn; > aresetn_d1 <= aresetn_d0; > end if; > end process CDC_aclk_to_s00_axi_aclk; > > CDC_s00_axi_aclk_to_aclk: process (aclk) > begin > if rising_edge(aclk) then > axi_aresetn_d0 <= s00_axi_aresetn; > axi_aresetn_d1 <= axi_aresetn_d0; > -- > --sw_rst_d0 <= sw_rst; > --sw_rst_d1 <= sw_rst_d0; > end if; > end process CDC_s00_axi_aclk_to_aclk; > > SR0_fifo : DEC_FIFO_32X16 > PORT MAP ( > rst => '0', > wr_clk => aclk, > rd_clk => s00_axi_aclk, > din => SR0, > wr_en => aresetn, > rd_en => aresetn_d1, > dout => CR0, > full => S0_fifo_full, > empty => S0_fifo_empty > ); > > SR1_fifo : DEC_FIFO_32X16 > PORT MAP ( > rst => '0', > wr_clk => aclk, > rd_clk => s00_axi_aclk, > din => SR1, > wr_en => aresetn, > rd_en => aresetn_d1, > dout => CR1, > full => S1_fifo_full, > empty => S1_fifo_empty > ); > > CR0_fifo : DEC_FIFO_32X16 > PORT MAP ( > rst => '0', > wr_clk => s00_axi_aclk, > rd_clk => aclk, > din => SR0, > wr_en => s00_axi_aresetn, > rd_en => axi_aresetn_d1, > dout => CR0, > full => C0_fifo_full, > empty => C0_fifo_empty > ); > > > CR1_fifo : DEC_FIFO_32X16 > PORT MAP ( > rst => '0', > wr_clk => s00_axi_aclk, > rd_clk => aclk, > din => SR1, > wr_en => s00_axi_aresetn, > rd_en => axi_aresetn_d1, > dout => CR1, > full => C1_fifo_full, > empty => C1_fifo_empty > ); > > --aclk <= aclk; > -- aresetn <= aresetn; > > > sw_rst <= sw_rst_d1; > > end arch_imp; > From newsfish@newsfish Thu Aug 1 00:46:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Silver Dream ! Newsgroups: comp.lang.vhdl Subject: Re: Kudos to Sigasi Date: Sun, 28 Mar 2021 03:20:55 +0200 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: <0gJ4I.93945$hcZe.23159@fx46.ams4> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 28 Mar 2021 01:20:55 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="f28a0ff97f9768371f9f7c0d84dfbfc1"; logging-data="6049"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CZkPto66Thr4qBXdcCR4o8Aaf+C6IEqs=" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 Cancel-Lock: sha1:3QlzrRMQdfocQv8i7Bhg1Kap2iI= In-Reply-To: <0gJ4I.93945$hcZe.23159@fx46.ams4> Content-Language: en-US Xref: reader02.eternal-september.org comp.lang.vhdl:9824 On 18.03.2021 15:15, HT-Lab wrote: > Sigasi 4.11 now supports a few VHDL2019 constructs, see this link: > > https://insights.sigasi.com/releasenotes/sigasi-4.11/ > > Kudos to Sigasi for this! +1! From newsfish@newsfish Thu Aug 1 00:46:15 2024 X-Received: by 2002:ad4:4b2c:: with SMTP id s12mr21363900qvw.19.1616945128857; Sun, 28 Mar 2021 08:25:28 -0700 (PDT) X-Received: by 2002:a25:6f56:: with SMTP id k83mr33580789ybc.196.1616945128652; Sun, 28 Mar 2021 08:25:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 28 Mar 2021 08:25:28 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=171.241.21.175; posting-account=9mbN_woAAAAnbT_AJKUPbGYA8U8h9rKG NNTP-Posting-Host: 171.241.21.175 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1be53d72-09ea-4d32-a546-c330462f29e5n@googlegroups.com> Subject: 3 bit comparator From: =?UTF-8?B?RMawxqFuZyBExrDGoW5n?= Injection-Date: Sun, 28 Mar 2021 15:25:28 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9825 comparator3bit.vhd:library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity comparator3bit is port ( p : in std_logic_vector(2 downto 0); q : in std_logic_vector(2 downto 0); p_le_q : out std_logic ); end comparator3bit; Architecture Behavior of comparator3bit is begin process (p, q) begin if p '0'); signal p_le_q : std_logic; signal i,j : integer; begin UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q => p_le_q); process begin for i in 0 to 8 loop p <= std_logic_vector(to_unsigned(i+2,3)); q <= std_logic_vector(to_unsigned(i,3)); end loop; wait; end process; end; When I run the simulation comparator3bit_tb and add the wave then the graph does not show p_le_q output. How to fix thanks From newsfish@newsfish Thu Aug 1 00:46:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!aioe.org!FTrC7U7vVkJJ/w0xNe0ZAw.user.gioia.aioe.org.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: Re: 3 bit comparator Date: Mon, 29 Mar 2021 09:57:28 +0300 Organization: Aioe.org NNTP Server Lines: 74 Message-ID: References: <1be53d72-09ea-4d32-a546-c330462f29e5n@googlegroups.com> NNTP-Posting-Host: FTrC7U7vVkJJ/w0xNe0ZAw.user.gioia.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:88.0) Gecko/20100101 Thunderbird/88.0 X-Antivirus: AVG (VPS 210328-4, 03/28/2021), Outbound message X-Notice: Filtered by postfilter v. 0.9.2 Content-Language: en-US X-Antivirus-Status: Clean Xref: reader02.eternal-september.org comp.lang.vhdl:9826 On 28/03/2021 18:25, Dương Dương wrote: > comparator3bit.vhd:library IEEE; > use IEEE.STD_LOGIC_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > entity comparator3bit is > port ( > p : in std_logic_vector(2 downto 0); > q : in std_logic_vector(2 downto 0); > p_le_q : out std_logic > ); > end comparator3bit; > > Architecture Behavior of comparator3bit is > begin > process (p, q) > begin > if p else p_le_q <= '0'; > end if; > end process; > end Behavior; > > comparator3bit_tb.vhd: > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > USE ieee.numeric_std.ALL; > > entity comparator3bit_tb is > end comparator3bit_tb; > > Architecture tb of comparator3bit_tb is > component comparator3bit_tb is > port ( p : in std_logic_vector(2 downto 0); > q : in std_logic_vector(2 downto 0); > p_le_q : out std_logic); > end component; > signal p,q : std_logic_vector(2 downto 0) := (others => '0'); > signal p_le_q : std_logic; > signal i,j : integer; > begin > UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q => p_le_q); > process > begin > for i in 0 to 8 loop > p <= std_logic_vector(to_unsigned(i+2,3)); > q <= std_logic_vector(to_unsigned(i,3)); > end loop; > wait; > end process; > end; > > When I run the simulation comparator3bit_tb and add the wave then the graph does not show p_le_q output. How to fix thanks > you should wait for some time after assigning p and q, try this: for i in 0 to 8 loop for i in 0 to 8 loop p <= std_logic_vector(to_unsigned(i+2,3)); q <= std_logic_vector(to_unsigned(i,3)); end loop; wait; HTH -- Cet email a fait l'objet d'une analyse antivirus par AVG. http://www.avg.com From newsfish@newsfish Thu Aug 1 00:46:15 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!aioe.org!FTrC7U7vVkJJ/w0xNe0ZAw.user.gioia.aioe.org.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: Re: 3 bit comparator Date: Mon, 29 Mar 2021 09:58:49 +0300 Organization: Aioe.org NNTP Server Lines: 90 Message-ID: References: <1be53d72-09ea-4d32-a546-c330462f29e5n@googlegroups.com> NNTP-Posting-Host: FTrC7U7vVkJJ/w0xNe0ZAw.user.gioia.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:88.0) Gecko/20100101 Thunderbird/88.0 X-Antivirus: AVG (VPS 210328-4, 03/28/2021), Outbound message X-Antivirus-Status: Clean X-Notice: Filtered by postfilter v. 0.9.2 Content-Language: en-US Xref: reader02.eternal-september.org comp.lang.vhdl:9827 On 29/03/2021 09:57, Maurice SAAB wrote: > On 28/03/2021 18:25, Dương Dương wrote: >> comparator3bit.vhd:library IEEE; >> use IEEE.STD_LOGIC_1164.all; >> use ieee.std_logic_arith.all; >> use ieee.std_logic_unsigned.all; >> >> entity comparator3bit is >>     port ( >>         p : in std_logic_vector(2 downto 0); >>         q : in std_logic_vector(2 downto 0); >>         p_le_q : out std_logic >>         ); >> end comparator3bit; >> >> Architecture Behavior of comparator3bit is >> begin >>     process (p, q) >>     begin >>     if p>     else p_le_q <= '0'; >>     end if; >>     end process; >> end Behavior; >> >> comparator3bit_tb.vhd: >> library IEEE; >> use IEEE.STD_LOGIC_1164.all; >> use ieee.std_logic_arith.all; >> use ieee.std_logic_unsigned.all; >> USE ieee.numeric_std.ALL; >> >> entity comparator3bit_tb is >> end comparator3bit_tb; >> >> Architecture tb of comparator3bit_tb is >>     component comparator3bit_tb is >>     port ( p : in std_logic_vector(2 downto 0); >>         q : in std_logic_vector(2 downto 0); >>         p_le_q : out std_logic); >>     end component; >>     signal p,q : std_logic_vector(2 downto 0) := (others => '0'); >>     signal p_le_q : std_logic; >>     signal i,j : integer; >> begin >>     UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q >> => p_le_q); >>     process >>     begin >>     for i in 0 to 8 loop >>         p <= std_logic_vector(to_unsigned(i+2,3)); >>         q <= std_logic_vector(to_unsigned(i,3)); >>          end loop; >>     wait; >>     end process; >> end; >> >> When I run the simulation comparator3bit_tb and add the wave then the >> graph does not show p_le_q output. How to fix thanks >> > you should wait for some time after assigning p and q, try this: > for i in 0 to 8 loop >         for i in 0 to 8 loop >         p <= std_logic_vector(to_unsigned(i+2,3)); >         q <= std_logic_vector(to_unsigned(i,3)); >        end loop; >     wait; > HTH > > > > > you should wait for some time after assigning p and q, try this: for i in 0 to 8 loop for i in 0 to 8 loop p <= std_logic_vector(to_unsigned(i+2,3)); q <= std_logic_vector(to_unsigned(i,3)); wait for 100 ns; end loop; wait; HTH -- Cet email a fait l'objet d'une analyse antivirus par AVG. http://www.avg.com From newsfish@newsfish Thu Aug 1 00:46:16 2024 X-Received: by 2002:ad4:5901:: with SMTP id ez1mr31732232qvb.38.1617132479619; Tue, 30 Mar 2021 12:27:59 -0700 (PDT) X-Received: by 2002:a25:6e87:: with SMTP id j129mr45108426ybc.215.1617132479342; Tue, 30 Mar 2021 12:27:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.mixmin.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Mar 2021 12:27:59 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=50.126.66.67; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.126.66.67 References: <0gJ4I.93945$hcZe.23159@fx46.ams4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1199ace9-865f-4971-a48c-86cb1bc14716n@googlegroups.com> Subject: Re: Kudos to Sigasi From: Jim Lewis Injection-Date: Tue, 30 Mar 2021 19:27:59 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9828 +1 for Sigasi and +1 for Aldec who is well into their implementation of 2019. From newsfish@newsfish Thu Aug 1 00:46:16 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: 3 bit comparator Date: Thu, 1 Apr 2021 21:33:59 -0500 Organization: A noiseless patient Spider Lines: 72 Message-ID: References: <1be53d72-09ea-4d32-a546-c330462f29e5n@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Fri, 2 Apr 2021 02:34:03 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="7b158f3edcb820d667879f8c9c1409b9"; logging-data="25269"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/mkht9G834QAJkCZX+U4+/6sRj9cAREYA=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:9XEzbCMoVfzKsjvrlcb73bYVEGM= In-Reply-To: <1be53d72-09ea-4d32-a546-c330462f29e5n@googlegroups.com> Xref: reader02.eternal-september.org comp.lang.vhdl:9829 On 2021-03-28 10:25, Dương Dương wrote: > comparator3bit.vhd:library IEEE; > use IEEE.STD_LOGIC_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > entity comparator3bit is > port ( > p : in std_logic_vector(2 downto 0); > q : in std_logic_vector(2 downto 0); > p_le_q : out std_logic > ); > end comparator3bit; > > Architecture Behavior of comparator3bit is > begin > process (p, q) > begin > if p else p_le_q <= '0'; > end if; > end process; > end Behavior; > > comparator3bit_tb.vhd: > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > USE ieee.numeric_std.ALL; > > entity comparator3bit_tb is > end comparator3bit_tb; > > Architecture tb of comparator3bit_tb is > component comparator3bit_tb is > port ( p : in std_logic_vector(2 downto 0); > q : in std_logic_vector(2 downto 0); > p_le_q : out std_logic); > end component; > signal p,q : std_logic_vector(2 downto 0) := (others => '0'); > signal p_le_q : std_logic; > signal i,j : integer; > begin > UUT : entity work.comparator3bit port map (p => p, q => q ,p_le_q => p_le_q); > process > begin > for i in 0 to 8 loop > p <= std_logic_vector(to_unsigned(i+2,3)); > q <= std_logic_vector(to_unsigned(i,3)); > end loop; > wait; > end process; > end; > > When I run the simulation comparator3bit_tb and add the wave then the graph does not show p_le_q output. How to fix thanks > Main problem: your FOR loop doesn't advance simulation time with each iteration. Your whole simulation completes in 0 ps. Put a WAIT statement, such as "wait for 20 ns;" before the "end loop;" A few other comments: Remove the references to the std_logic_arith and std_logic_unsigned packages. Those are non-standard packages that came from Synopsys, not IEEE, and are considered deprecated. Plus, you are not actually using them anyway. Because your testbench uses entity instantiation for comparator3bit, you don't need the component definition for it. Charles Bailey From newsfish@newsfish Thu Aug 1 00:46:17 2024 X-Received: by 2002:a05:6214:178b:: with SMTP id ct11mr8731067qvb.61.1620833037969; Wed, 12 May 2021 08:23:57 -0700 (PDT) X-Received: by 2002:a25:7109:: with SMTP id m9mr49824100ybc.274.1620833037780; Wed, 12 May 2021 08:23:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 May 2021 08:23:57 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=2402:800:6101:d5d2:b4d9:6a1e:77fd:ce23; posting-account=9mbN_woAAAAnbT_AJKUPbGYA8U8h9rKG NNTP-Posting-Host: 2402:800:6101:d5d2:b4d9:6a1e:77fd:ce23 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2c102433-43d8-4a13-9059-08bf2e3dc96an@googlegroups.com> Subject: flipflop testbenech From: =?UTF-8?B?RMawxqFuZyBExrDGoW5n?= Injection-Date: Wed, 12 May 2021 15:23:57 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9830 i have flipflops.vhdl LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY flipflops IS PORT ( clk : IN STD_LOGIC; d : IN STD_LOGIC; qa : OUT STD_LOGIC; qb : OUT STD_LOGIC; qc : OUT STD_LOGIC); END ENTITY flipflops; ARCHITECTURE beh OF flipflops IS BEGIN -- ARCHITECTURE beh ffa: PROCESS (clk, d) IS BEGIN -- PROCESS ffa IF clk = '1' THEN qa <= d; END IF; END PROCESS ffa; ffb: PROCESS (clk) IS BEGIN -- PROCESS ffb IF rising_edge(clk) THEN qb <= d; END IF; END PROCESS ffb; ffc: PROCESS (clk) IS BEGIN -- PROCESS ffc IF falling_edge(clk) THEN qc <= d; END IF; END PROCESS ffc; END ARCHITECTURE beh; How can i complete flipflops_tb LIBRARY ieee; USE ieee.std_logic_1164.ALL; ------------------------------------------------------------------------------- ENTITY flipflops_tb IS END ENTITY flipflops_tb; ------------------------------------------------------------------------------- ARCHITECTURE test OF flipflops_tb IS -- component ports SIGNAL clk : STD_LOGIC := '1'; SIGNAL d : STD_LOGIC; SIGNAL qa : STD_LOGIC; SIGNAL qb : STD_LOGIC; SIGNAL qc : STD_LOGIC; BEGIN -- ARCHITECTURE test -- component instantiation DUT : ENTITY work.flipflops PORT MAP ( clk => clk, d => d, qa => qa, qb => qb, qc => qc); -- clock generation Clk <= NOT Clk AFTER 10 NS; -- waveform generation WaveGen_Proc : PROCESS BEGIN -- insert signal assignments here d <= '0'; WAIT FOR 5 NS; d <= '1'; WAIT FOR 3 NS; END PROCESS WaveGen_Proc; END ARCHITECTURE test; ------------------------------------------------------------------------------- CONFIGURATION flipflops_tb_test_cfg OF flipflops_tb IS FOR test END FOR; END flipflops_tb_test_cfg; ------------------------------------------------------------------------------- thanks From newsfish@newsfish Thu Aug 1 00:46:17 2024 X-Received: by 2002:ac8:6c22:: with SMTP id k2mr33039701qtu.303.1620837134774; Wed, 12 May 2021 09:32:14 -0700 (PDT) X-Received: by 2002:a25:8b08:: with SMTP id i8mr45991373ybl.370.1620837134525; Wed, 12 May 2021 09:32:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.dns-netz.com!news.freedyn.net!newsfeed.xs4all.nl!newsfeed9.news.xs4all.nl!tr2.eu1.usenetexpress.com!feeder.usenetexpress.com!tr2.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 May 2021 09:32:14 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=2402:800:6101:d5d2:b4d9:6a1e:77fd:ce23; posting-account=9mbN_woAAAAnbT_AJKUPbGYA8U8h9rKG NNTP-Posting-Host: 2402:800:6101:d5d2:b4d9:6a1e:77fd:ce23 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <322243b1-ee04-471d-b586-c8476bac3754n@googlegroups.com> Subject: accumulator From: =?UTF-8?B?RMawxqFuZyBExrDGoW5n?= Injection-Date: Wed, 12 May 2021 16:32:14 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 34 Xref: reader02.eternal-september.org comp.lang.vhdl:9831 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY accumulator IS PORT ( clk : IN STD_LOGIC; rst_n : IN STD_LOGIC; set : IN STD_LOGIC; data_in : IN SIGNED(7 DOWNTO 0); enable : IN STD_LOGIC; accumulator_out : OUT SIGNED(11 DOWNTO 0)); END ENTITY accumulator; ARCHITECTURE beh OF accumulator IS SIGNAL accumulator_reg : SIGNED(11 DOWNTO 0); BEGIN -- ARCHITECTURE beh accumulator_proc : PROCESS (clk, rst_n, set, enable) IS BEGIN -- PROCESS accumulator_proc if rst_n = '0' then accumulator_reg <= (OTHERS => '0'); elsif rst_n = '1' and set = '1' then accumulator_reg <= "0000" & data_in; elsif rst_n = '1' and set = '0' and enable = '1' then accumulator_reg <= accumulator_reg + data_in; end if; END PROCESS accumulator_proc; accumulator_out <= accumulator_reg; END ARCHITECTURE beh; My rst_n signal is synchronous or asynchronous. Help me design this signal in the remaining way. Thanks From newsfish@newsfish Thu Aug 1 00:46:17 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!buffer1.nntp.ams1.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 13 May 2021 09:49:14 -0500 Reply-To: mk@mkesc.co.uk Subject: Re: flipflop testbenech Newsgroups: comp.lang.vhdl References: <2c102433-43d8-4a13-9059-08bf2e3dc96an@googlegroups.com> From: Michael Kellett Date: Thu, 13 May 2021 15:49:14 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <2c102433-43d8-4a13-9059-08bf2e3dc96an@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 8bit Message-ID: Lines: 107 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-q41PjcbXFaHHEI4HLGvPkrL0Ycav8LYRChNVb+2DdzlKjH7VkKXqgTtzVMAeR4OgQghEq8po6qrwqGM!fKyEhSOOf57g9iR/oTVVLzRu7HTv43k21C8TKkkr5JQGp4doWuAUpc38fuvUpmmTJtmLw7EE8IUw X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3621 Xref: reader02.eternal-september.org comp.lang.vhdl:9832 On 12/05/2021 16:23, Dương Dương wrote: > i have flipflops.vhdl > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > > ENTITY flipflops IS > > PORT ( > clk : IN STD_LOGIC; > d : IN STD_LOGIC; > qa : OUT STD_LOGIC; > qb : OUT STD_LOGIC; > qc : OUT STD_LOGIC); > > END ENTITY flipflops; > > ARCHITECTURE beh OF flipflops IS > > BEGIN -- ARCHITECTURE beh > > ffa: PROCESS (clk, d) IS > BEGIN -- PROCESS ffa > IF clk = '1' THEN > qa <= d; > END IF; > END PROCESS ffa; > > ffb: PROCESS (clk) IS > BEGIN -- PROCESS ffb > IF rising_edge(clk) THEN > qb <= d; > END IF; > END PROCESS ffb; > > ffc: PROCESS (clk) IS > BEGIN -- PROCESS ffc > IF falling_edge(clk) THEN > qc <= d; > END IF; > END PROCESS ffc; > > END ARCHITECTURE beh; > > How can i complete flipflops_tb > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > > ------------------------------------------------------------------------------- > > ENTITY flipflops_tb IS > > END ENTITY flipflops_tb; > > ------------------------------------------------------------------------------- > > ARCHITECTURE test OF flipflops_tb IS > > -- component ports > SIGNAL clk : STD_LOGIC := '1'; > SIGNAL d : STD_LOGIC; > SIGNAL qa : STD_LOGIC; > SIGNAL qb : STD_LOGIC; > SIGNAL qc : STD_LOGIC; > > BEGIN -- ARCHITECTURE test > > -- component instantiation > DUT : ENTITY work.flipflops > PORT MAP ( > clk => clk, > d => d, > qa => qa, > qb => qb, > qc => qc); > > -- clock generation > Clk <= NOT Clk AFTER 10 NS; > > -- waveform generation > WaveGen_Proc : PROCESS > BEGIN > -- insert signal assignments here > d <= '0'; > WAIT FOR 5 NS; > d <= '1'; > WAIT FOR 3 NS; > END PROCESS WaveGen_Proc; > > > > END ARCHITECTURE test; > > ------------------------------------------------------------------------------- > > CONFIGURATION flipflops_tb_test_cfg OF flipflops_tb IS > FOR test > END FOR; > END flipflops_tb_test_cfg; > > ------------------------------------------------------------------------------- > thanks > Have you just posted your homework questions ? MK From newsfish@newsfish Thu Aug 1 00:46:18 2024 X-Received: by 2002:a0c:fbc3:: with SMTP id n3mr24910359qvp.3.1626702925374; Mon, 19 Jul 2021 06:55:25 -0700 (PDT) X-Received: by 2002:a25:b793:: with SMTP id n19mr31540924ybh.488.1626702925100; Mon, 19 Jul 2021 06:55:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.mixmin.net!news2.arglkargh.de!news.in-chemnitz.de!3.eu.feeder.erje.net!feeder.erje.net!newsfeed.xs4all.nl!newsfeed7.news.xs4all.nl!news-out.netnews.com!news.alt.net!fdc2.netnews.com!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 Jul 2021 06:55:24 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=173.179.222.254; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j NNTP-Posting-Host: 173.179.222.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: How to manage multiple testcases in a testbench From: Benjamin Couillard Injection-Date: Mon, 19 Jul 2021 13:55:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1890 Xref: reader02.eternal-september.org comp.lang.vhdl:9833 Hi, I'm trying to implement a testbench for a relatively complex module and= I need multiple test cases to cover all the functionnality. I'd like to fi= nd an elegant way to perform multiple testcases without using text files fo= r the stimulus because I find that text files are not really flexible. Here= 's my options so far 1 - Use one testbench file per test case. I don't really like this approach= as I need to duplicate a lot of code amongst the testbench files even if I= put procedure in a package. 2 - Use a generic to specify the testcase, then use a If generate clause to= wrap the stimulus and validation process for each test case. 3 - Put all test cases in a the same process and simply reset the module be= tween each test case. I hesitate between option 2 and 3. Is there another option ?=20 Regards From newsfish@newsfish Thu Aug 1 00:46:18 2024 X-Received: by 2002:a05:620a:1137:: with SMTP id p23mr30112149qkk.490.1626784743612; Tue, 20 Jul 2021 05:39:03 -0700 (PDT) X-Received: by 2002:a25:c60a:: with SMTP id k10mr39394055ybf.53.1626784743258; Tue, 20 Jul 2021 05:39:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Jul 2021 05:39:03 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=204.19.223.19; posting-account=w728HAoAAAAF2xrMb6mkfbhZUlYwqJjV NNTP-Posting-Host: 204.19.223.19 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to manage multiple testcases in a testbench From: KKoorndyk Injection-Date: Tue, 20 Jul 2021 12:39:03 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9834 On Monday, July 19, 2021 at 9:55:26 AM UTC-4, benjamin....@gmail.com wrote: > Hi, I'm trying to implement a testbench for a relatively complex module a= nd I need multiple test cases to cover all the functionnality. I'd like to = find an elegant way to perform multiple testcases without using text files = for the stimulus because I find that text files are not really flexible. He= re's my options so far=20 >=20 > 1 - Use one testbench file per test case. I don't really like this approa= ch as I need to duplicate a lot of code amongst the testbench files even if= I put procedure in a package.=20 >=20 > 2 - Use a generic to specify the testcase, then use a If generate clause = to wrap the stimulus and validation process for each test case.=20 >=20 > 3 - Put all test cases in a the same process and simply reset the module = between each test case.=20 >=20 > I hesitate between option 2 and 3. Is there another option ?=20 >=20 > Regards I use a top level testbench that instantiates a test harness and a generic = testcase like this: ---------------------------------------------------------------------------= ----------------------------------- architecture tb of testbench is component harness is end component harness; component testcase is end component testcase; =20 begin th: component harness; tc: component testcase; end architecture tb; ---------------------------------------------------------------------------= ----------------------------------- The testcase entity is defined in one file and each testcase containing the= stimulus are defined in separate testcase architecture files. I use VHDL = configurations in the testbench to select the appropriate testcase: ---------------------------------------------------------------------------= ----------------------------------- -- Test Configuration 1 (TCFG1) ---------------------------------------------------------------------------= ----------------------------------- configuration tcfg1 of testbench is for tb for th : harness use entity work.harness generic map ( G_LOG_FILENAME =3D> "tcfg1_log", G_WIDTH =3D> 34 ); end for; for tc : testcase use entity work.testcase(tc1) generic map ( G_WIDTH =3D> 34 ); end for; end for; end configuration tcfg1; Then, simulating a specific testcase is done by targeting the corresponding= configuration: $ vsim ${VOPTS} work.tcfg1 From newsfish@newsfish Thu Aug 1 00:46:18 2024 X-Received: by 2002:a05:622a:390:: with SMTP id j16mr25015845qtx.266.1627484628891; Wed, 28 Jul 2021 08:03:48 -0700 (PDT) X-Received: by 2002:a25:568b:: with SMTP id k133mr242657ybb.196.1627484628697; Wed, 28 Jul 2021 08:03:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Jul 2021 08:03:48 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=99.184.241.163; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.241.163 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to manage multiple testcases in a testbench From: KJ Injection-Date: Wed, 28 Jul 2021 15:03:48 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 38 Xref: reader02.eternal-september.org comp.lang.vhdl:9835 On Monday, July 19, 2021 at 9:55:26 AM UTC-4, benjamin....@gmail.com wrote: > Hi, I'm trying to implement a testbench for a relatively complex module a= nd I need multiple test cases to cover all the functionnality. I'd like to = find an elegant way to perform multiple testcases without using text files = for the stimulus because I find that text files are not really flexible. He= re's my options so far=20 >=20 > 1 - Use one testbench file per test case. I don't really like this approa= ch as I need to duplicate a lot of code amongst the testbench files even if= I put procedure in a package.=20 >=20 > 2 - Use a generic to specify the testcase, then use a If generate clause = to wrap the stimulus and validation process for each test case.=20 >=20 > 3 - Put all test cases in a the same process and simply reset the module = between each test case.=20 >=20 > I hesitate between option 2 and 3. Is there another option ?=20 >=20 > Regards I use a variation on #2. However, instead of a generic I use a boolean arr= ay to specify which tests to run. The main test code then simply loops thr= ough the array and calls the test case code if the boolean is true. I defi= ne an enumeration list of the tests mainly to give a readable named list of= all of the tests. The boolean array is an array of that enumeration list.= This is also easy to adjust while in debug mode where I might want to onl= y run either a single test or some subset. Example: type t_TESTS is (TestThis, TestThat, TestSomethingElse); type t_LIST_OF_TESTS is array(t_TESTS) of boolean; constant TestsToRun: t_LIST_OF_TESTS :=3D ( TestThis =3D> TRUE, TestThat =3D> TRUE, TestSomethingElse =3D> TRUE ); Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:19 2024 X-Received: by 2002:ad4:44f3:: with SMTP id p19mr6909780qvt.33.1631283406907; Fri, 10 Sep 2021 07:16:46 -0700 (PDT) X-Received: by 2002:a05:6902:4ee:: with SMTP id w14mr11717249ybs.448.1631283406648; Fri, 10 Sep 2021 07:16:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Sep 2021 07:16:46 -0700 (PDT) In-Reply-To: <5c61e7a7$0$3533$426a34cc@news.free.fr> Injection-Info: google-groups.googlegroups.com; posting-host=176.88.77.8; posting-account=2tch0AoAAADY2XV8K0qsgiVqptPmuHa3 NNTP-Posting-Host: 176.88.77.8 References: <36B0468F.2016173@mentorg.com> <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> <5c61e7a7$0$3533$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e5823fe-8563-4e8c-8cc2-3541b259b75fn@googlegroups.com> Subject: Re: printf() function like C in VHDL ? From: =?UTF-8?Q?=C3=96mer_Ziya_AYDIN?= Injection-Date: Fri, 10 Sep 2021 14:16:46 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 16 Xref: reader02.eternal-september.org comp.lang.vhdl:9836 12 =C5=9Eubat 2019 Sal=C4=B1 tarihinde saat 00:22:50 UTC+3 itibar=C4=B1yla = Nicolas Matringe =C5=9Funlar=C4=B1 yazd=C4=B1: > On 10/02/2019 22:42, Rubel Ahmed wrote:=20 > > On Thursday, January 28, 1999 at 3:00:00 AM UTC-5, Jerome Chaix wrote:= =20 > >> Is there an existing function in VHDL which is the equivalent of=20 > >> printf(%d, var) in language C ?=20 > >=20 > > I do the following and it works for me. though I am a noob.=20 > >=20 > > assert false=20 > > report "show me what you got: "&integer'image(myVar) severity NOTE; > Do you realize you just replied to a 20 years old thread ?=20 >=20 > Nicolas That's amazing lol From newsfish@newsfish Thu Aug 1 00:46:19 2024 X-Received: by 2002:a05:620a:4514:: with SMTP id t20mr777850qkp.114.1631554222866; Mon, 13 Sep 2021 10:30:22 -0700 (PDT) X-Received: by 2002:a5b:f03:: with SMTP id x3mr17332192ybr.546.1631554222660; Mon, 13 Sep 2021 10:30:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 13 Sep 2021 10:30:22 -0700 (PDT) In-Reply-To: <0e5823fe-8563-4e8c-8cc2-3541b259b75fn@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2a02:908:953:1b00:c5e8:743f:590:498f; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 2a02:908:953:1b00:c5e8:743f:590:498f References: <36B0468F.2016173@mentorg.com> <8f37e01f-90de-4601-bfde-21b7617a9372@googlegroups.com> <5c61e7a7$0$3533$426a34cc@news.free.fr> <0e5823fe-8563-4e8c-8cc2-3541b259b75fn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: printf() function like C in VHDL ? From: Nikolaos Kavvadias Injection-Date: Mon, 13 Sep 2021 17:30:22 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 27 Xref: reader02.eternal-september.org comp.lang.vhdl:9837 =CE=A3=CF=84=CE=B9=CF=82 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85= =CE=AE, 10 =CE=A3=CE=B5=CF=80=CF=84=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF= =85 2021 =CF=83=CF=84=CE=B9=CF=82 4:16:49 =CE=BC.=CE=BC. UTC+2, =CE=BF =CF= =87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 =C3=96mer Ziya AYDIN =CE=AD=CE=B3= =CF=81=CE=B1=CF=88=CE=B5: > 12 =C5=9Eubat 2019 Sal=C4=B1 tarihinde saat 00:22:50 UTC+3 itibar=C4=B1yl= a Nicolas Matringe =C5=9Funlar=C4=B1 yazd=C4=B1: > > On 10/02/2019 22:42, Rubel Ahmed wrote:=20 > > > On Thursday, January 28, 1999 at 3:00:00 AM UTC-5, Jerome Chaix wrote= :=20 > > >> Is there an existing function in VHDL which is the equivalent of=20 > > >> printf(%d, var) in language C ?=20 I used to have the package described in http://bear.ces.cwru.edu/VHDL/doc/s= nug2002_20040606_slides.pdf and had used it once or twice. > > >=20 > > > I do the following and it works for me. though I am a noob.=20 > > >=20 > > > assert false=20 > > > report "show me what you got: "&integer'image(myVar) severity NOTE;= =20 > > Do you realize you just replied to a 20 years old thread ?=20 > >=20 > > Nicolas > That's amazing lol From newsfish@newsfish Thu Aug 1 00:46:19 2024 X-Received: by 2002:ac8:111:: with SMTP id e17mr1923229qtg.34.1632808342286; Mon, 27 Sep 2021 22:52:22 -0700 (PDT) X-Received: by 2002:a05:6902:1546:: with SMTP id r6mr5376336ybu.268.1632808341782; Mon, 27 Sep 2021 22:52:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 27 Sep 2021 22:52:21 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=2402:8100:22e0:e917:d16a:88b3:c15e:3e79; posting-account=HkGJVQoAAAB6xWKS794pjj885gJWKopL NNTP-Posting-Host: 2402:8100:22e0:e917:d16a:88b3:c15e:3e79 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Understanding Verilog Code From: Rupinder Goyal Injection-Date: Tue, 28 Sep 2021 05:52:22 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9838 Hi, I am new to verilog. I have written a code but the output is not as expected. I want to know how to interpret the code so that I can debug it? Can someone help me out? The module will get the input bit by bit ( from LSB side) and output a single bit everytime. Output till any particular moment is the 2's complement form of the input read till now. What I want to do is: Outputbit and nextstate change according to inputbit and prestate and then prestate gets the value of nextstate. What actually happening is: The code calculates the nextstate , assigns it to prestate and then outputbit is calculated according to the prestate. Please help me understand the code and how to correct it. `timescale 1ns / 1ps module twoComplement(inputBit, clk, reset, outputBit); input inputBit, clk, reset; output reg outputBit; reg preState, nextState; parameter Carry1 = 1, Carry0 = 0; always @ (posedge clk) begin if (reset) preState <= Carry1; else preState <= nextState; end always @(*) case (preState) Carry1: begin outputBit = inputBit ? 1 : 0; nextState = inputBit ? Carry0 : Carry1; end Carry0: begin outputBit = inputBit ? 0 : 1; nextState = Carry0; end default: begin outputBit = 0; nextState = Carry1; end endcase endmodule TestBench `timescale 1ns / 1ps `include "Q1.v" module testbenchFortwoComplement; reg inp, reset, clock; wire out; twoComplement a(inp, clock, reset, out); initial begin inp = 0; clock = 1; reset = 1; #5 reset = 0; #5 inp = 0; #5 $display("%b", out); #5 inp = 0; #5 $display("%b", out); #5 inp = 1; #5 $display("%b", out); #5 inp = 1; #5 $display("%b", out); #5 inp = 1; #5 $display("%b", out); #5 inp = 0; #5 $display("%b", out); #5 inp = 1; #5 $display("%b", out); #10 $finish; end always begin #5 clock = ~clock; end endmodule From newsfish@newsfish Thu Aug 1 00:46:19 2024 X-Received: by 2002:a37:b045:: with SMTP id z66mr4974681qke.271.1632920092583; Wed, 29 Sep 2021 05:54:52 -0700 (PDT) X-Received: by 2002:a5b:f03:: with SMTP id x3mr13710031ybr.546.1632920092204; Wed, 29 Sep 2021 05:54:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder5.feed.usenet.farm!feeder1.feed.usenet.farm!feed.usenet.farm!tr1.eu1.usenetexpress.com!feeder.usenetexpress.com!tr1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Sep 2021 05:54:51 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=82.194.215.7; posting-account=jIJeYwoAAABTTnDz1ZV_9Dy052PoBoBM NNTP-Posting-Host: 82.194.215.7 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Understanding Verilog Code From: Motaz Injection-Date: Wed, 29 Sep 2021 12:54:52 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 208 Xref: reader02.eternal-september.org comp.lang.vhdl:9839 =D9=81=D9=8A =D8=A7=D9=84=D8=AB=D9=84=D8=A7=D8=AB=D8=A7=D8=A1=D8=8C 28 =D8= =B3=D8=A8=D8=AA=D9=85=D8=A8=D8=B1 2021 =D9=81=D9=8A =D8=AA=D9=85=D8=A7=D9= =85 =D8=A7=D9=84=D8=B3=D8=A7=D8=B9=D8=A9 7:52:24 =D8=B5 UTC+2=D8=8C =D9=83= =D8=AA=D8=A8 rupin...@gmail.com =D8=B1=D8=B3=D8=A7=D9=84=D8=A9 =D9=86=D8=B5= =D9=87=D8=A7: > Hi, I am new to verilog. I have written a code but the output is not as e= xpected. I want to know how to interpret the code so that I can debug it? C= an someone help me out?=20 > The module will get the input bit by bit ( from LSB side) and output a si= ngle bit everytime. Output till any particular moment is the 2's complement= form of the input read till now.=20 > What I want to do is: Outputbit and nextstate change according to inputbi= t and prestate and then prestate gets the value of nextstate.=20 > What actually happening is: The code calculates the nextstate , assigns i= t to prestate and then outputbit is calculated according to the prestate.= =20 >=20 > Please help me understand the code and how to correct it.=20 >=20 >=20 > `timescale 1ns / 1ps=20 >=20 > module twoComplement(inputBit, clk, reset, outputBit);=20 > input inputBit, clk, reset;=20 > output reg outputBit;=20 > reg preState, nextState;=20 > parameter Carry1 =3D 1, Carry0 =3D 0;=20 >=20 > always @ (posedge clk)=20 > begin=20 > if (reset)=20 > preState <=3D Carry1;=20 > else=20 > preState <=3D nextState;=20 > end=20 >=20 > always @(*)=20 > case (preState)=20 > Carry1: begin=20 > outputBit =3D inputBit ? 1 : 0;=20 > nextState =3D inputBit ? Carry0 : Carry1;=20 > end=20 > Carry0: begin=20 > outputBit =3D inputBit ? 0 : 1;=20 > nextState =3D Carry0;=20 > end=20 > default: begin=20 > outputBit =3D 0;=20 > nextState =3D Carry1;=20 > end=20 > endcase=20 > endmodule=20 >=20 >=20 >=20 > TestBench=20 >=20 > `timescale 1ns / 1ps=20 >=20 > `include "Q1.v"=20 >=20 > module testbenchFortwoComplement;=20 > reg inp, reset, clock;=20 > wire out;=20 >=20 > twoComplement a(inp, clock, reset, out);=20 >=20 > initial begin=20 > inp =3D 0;=20 > clock =3D 1;=20 > reset =3D 1;=20 >=20 > #5 reset =3D 0;=20 > #5 inp =3D 0;=20 > #5 $display("%b", out);=20 > #5 inp =3D 0;=20 > #5 $display("%b", out);=20 > #5 inp =3D 1;=20 > #5 $display("%b", out);=20 > #5 inp =3D 1;=20 > #5 $display("%b", out);=20 > #5 inp =3D 1;=20 > #5 $display("%b", out);=20 > #5 inp =3D 0;=20 > #5 $display("%b", out);=20 > #5 inp =3D 1;=20 > #5 $display("%b", out);=20 >=20 >=20 > #10 $finish;=20 > end=20 >=20 > always begin=20 > #5 clock =3D ~clock;=20 > end=20 > endmodule On Tuesday, September 28, 2021 at 7:52:24 AM UTC+2, rupin...@gmail.com wrot= e: > Hi, I am new to verilog. I have written a code but the output is not as e= xpected. I want to know how to interpret the code so that I can debug it? C= an someone help me out?=20 > The module will get the input bit by bit ( from LSB side) and output a si= ngle bit everytime. Output till any particular moment is the 2's complement= form of the input read till now.=20 > What I want to do is: Outputbit and nextstate change according to inputbi= t and prestate and then prestate gets the value of nextstate.=20 > What actually happening is: The code calculates the nextstate , assigns i= t to prestate and then outputbit is calculated according to the prestate.= =20 >=20 > Please help me understand the code and how to correct it.=20 >=20 >=20 > `timescale 1ns / 1ps=20 >=20 > module twoComplement(inputBit, clk, reset, outputBit);=20 > input inputBit, clk, reset;=20 > output reg outputBit;=20 > reg preState, nextState;=20 > parameter Carry1 =3D 1, Carry0 =3D 0;=20 >=20 > always @ (posedge clk)=20 > begin=20 > if (reset)=20 > preState <=3D Carry1;=20 > else=20 > preState <=3D nextState;=20 > end=20 >=20 > always @(*)=20 > case (preState)=20 > Carry1: begin=20 > outputBit =3D inputBit ? 1 : 0;=20 > nextState =3D inputBit ? Carry0 : Carry1;=20 > end=20 > Carry0: begin=20 > outputBit =3D inputBit ? 0 : 1;=20 > nextState =3D Carry0;=20 > end=20 > default: begin=20 > outputBit =3D 0;=20 > nextState =3D Carry1;=20 > end=20 > endcase=20 > endmodule=20 >=20 >=20 >=20 > TestBench=20 >=20 > `timescale 1ns / 1ps=20 >=20 > `include "Q1.v"=20 >=20 > module testbenchFortwoComplement;=20 > reg inp, reset, clock;=20 > wire out;=20 >=20 > twoComplement a(inp, clock, reset, out);=20 >=20 > initial begin=20 > inp =3D 0;=20 > clock =3D 1;=20 > reset =3D 1;=20 >=20 > #5 reset =3D 0;=20 > #5 inp =3D 0;=20 > #5 $display("%b", out);=20 > #5 inp =3D 0;=20 > #5 $display("%b", out);=20 > #5 inp =3D 1;=20 > #5 $display("%b", out);=20 > #5 inp =3D 1;=20 > #5 $display("%b", out);=20 > #5 inp =3D 1;=20 > #5 $display("%b", out);=20 > #5 inp =3D 0;=20 > #5 $display("%b", out);=20 > #5 inp =3D 1;=20 > #5 $display("%b", out);=20 >=20 >=20 > #10 $finish;=20 > end=20 >=20 > always begin=20 > #5 clock =3D ~clock;=20 > end=20 > endmodule Hi, I think the issue is caused by the process of updating the preState.=20 It depends on the clk to update the preState, while the FSM that calculates= the outputBit and nextState updates its values each time ANY signal inside= of it is modified. Meaning that the calculation process updates its values= multiple times before the the preState gets assigned a new value. always @ (posedge clk) begin if (reset) preState <=3D Carry1; else preState <=3D nextState; end I would recommend update the preState reg in the same process as you calcul= ate the outputs of the design . - Motaz From newsfish@newsfish Thu Aug 1 00:46:20 2024 X-Received: by 2002:aed:2794:: with SMTP id a20mr10675783qtd.243.1633688071849; Fri, 08 Oct 2021 03:14:31 -0700 (PDT) X-Received: by 2002:a25:dd46:: with SMTP id u67mr2682996ybg.295.1633688071622; Fri, 08 Oct 2021 03:14:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 Oct 2021 03:14:31 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2402:8100:24eb:6b39:c8a7:8897:55c1:ab61; posting-account=KkG0hwoAAABKJt0TFGQ3QpqlPAZ-5o8t NNTP-Posting-Host: 2402:8100:24eb:6b39:c8a7:8897:55c1:ab61 References: <8ts39q$cth$1@nslave2.tin.it> <3a1a055f.7833118@news.micron.net> <8vd33f$q9q$1@nnrp1.deja.com> <0df7c0b5-2175-435b-9aa5-12b1e98c25dcn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <720f155a-d4ef-4cb0-abe8-5ecb8b023328n@googlegroups.com> Subject: Re: VHDL compiler and simulator for student From: SIDDHARTH SINGH UPADHYAY Injection-Date: Fri, 08 Oct 2021 10:14:31 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 22 Xref: reader02.eternal-september.org comp.lang.vhdl:9840 On Tuesday, October 6, 2020 at 10:14:50 AM UTC+5:30, Charles Bailey wrote: > On 2020-10-05 03:13, Michael Kellett wrote: > > On 05/10/2020 07:35, rezaul karim wrote: > >> Hello good morning > >> I would like to get HDL simulator for free of cost. > >> could anybody suggest me , how can get that simulator? > >> Regards > >> Md Karim > >> > > That original post is 20 years old! > > > > You can download free design tools suites from Intel/Altera, Xilinx, > > Lattice and Microchip. They all include simulators, for VHDL and > > Verilog. For basic work they would all be OK. > > > > MK > There is also ghdl (http://ghdl.free.fr/), which is completely free. I > have found it to be surprisingly capable. There is no gui, it's batch > mode only, but I have simulated some fairly large designs with it and > its support of the VHDL language is surprisingly good. > > Charles Bailey 2000 to 2021 time change but quetion not From newsfish@newsfish Thu Aug 1 00:46:20 2024 X-Received: by 2002:a37:b06:: with SMTP id 6mr4860711qkl.352.1634220259043; Thu, 14 Oct 2021 07:04:19 -0700 (PDT) X-Received: by 2002:a25:bb47:: with SMTP id b7mr6285156ybk.420.1634220258725; Thu, 14 Oct 2021 07:04:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.uzoreto.com!tr3.eu1.usenetexpress.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 Oct 2021 07:04:18 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2001:638:708:300:c8c4:1366:b9c8:fefc; posting-account=11lgEgkAAADAed_CCxAF76lgYpLanCLj NNTP-Posting-Host: 2001:638:708:300:c8c4:1366:b9c8:fefc References: <8ts39q$cth$1@nslave2.tin.it> <3a1a055f.7833118@news.micron.net> <8vd33f$q9q$1@nnrp1.deja.com> <0df7c0b5-2175-435b-9aa5-12b1e98c25dcn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6c14723d-b03f-40ef-bbb2-889df1bdc0b0n@googlegroups.com> Subject: Re: VHDL compiler and simulator for student From: Md Rezaul Karim Injection-Date: Thu, 14 Oct 2021 14:04:19 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 22 Xref: reader02.eternal-september.org comp.lang.vhdl:9841 On Tuesday, October 6, 2020 at 6:44:50 AM UTC+2, Charles Bailey wrote: > On 2020-10-05 03:13, Michael Kellett wrote: > > On 05/10/2020 07:35, rezaul karim wrote: > >> Hello good morning > >> I would like to get HDL simulator for free of cost. > >> could anybody suggest me , how can get that simulator? > >> Regards > >> Md Karim > >> > > That original post is 20 years old! > > > > You can download free design tools suites from Intel/Altera, Xilinx, > > Lattice and Microchip. They all include simulators, for VHDL and > > Verilog. For basic work they would all be OK. > > > > MK > There is also ghdl (http://ghdl.free.fr/), which is completely free. I > have found it to be surprisingly capable. There is no gui, it's batch > mode only, but I have simulated some fairly large designs with it and > its support of the VHDL language is surprisingly good. > > Charles Bailey thanks man From newsfish@newsfish Thu Aug 1 00:46:20 2024 X-Received: by 2002:a05:620a:1269:: with SMTP id b9mr4822494qkl.273.1634220357138; Thu, 14 Oct 2021 07:05:57 -0700 (PDT) X-Received: by 2002:a25:3487:: with SMTP id b129mr5861256yba.249.1634220356857; Thu, 14 Oct 2021 07:05:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 Oct 2021 07:05:56 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2001:638:708:300:c8c4:1366:b9c8:fefc; posting-account=11lgEgkAAADAed_CCxAF76lgYpLanCLj NNTP-Posting-Host: 2001:638:708:300:c8c4:1366:b9c8:fefc References: <8ts39q$cth$1@nslave2.tin.it> <3a1a055f.7833118@news.micron.net> <8vd33f$q9q$1@nnrp1.deja.com> <0df7c0b5-2175-435b-9aa5-12b1e98c25dcn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0fa23b29-0b2f-4097-a081-5cf75ab9e92fn@googlegroups.com> Subject: Re: VHDL compiler and simulator for student From: Md Rezaul Karim Injection-Date: Thu, 14 Oct 2021 14:05:57 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 40 Xref: reader02.eternal-september.org comp.lang.vhdl:9842 On Monday, October 5, 2020 at 10:13:48 AM UTC+2, Michael Kellett wrote: > On 05/10/2020 07:35, rezaul karim wrote: > > On Tuesday, November 21, 2000 at 7:01:21 AM UTC+1, Srinivasan Venkataramanan wrote: > >> Hi, > >> In article <3a1a055f...@news.micron.net>, > >> nospam_...@hotmail.com (Ed Davis) wrote: > >>> I am also a student have have found this free tool great for doing > >>> VHDL homework. > >>> > >>> http://www.symphonyeda.com/ > >>> > >>> It has no GUI or debugger, but hey, its free. I love it. > >>> > >> A free simple GUI for VHDLSimli is available at > >> http://www.symphonyeda.com/contribs.htm#Simtool > >> I haven't used this (as I prefer command line mode) although. > >> Cheers, > >> Srini > >>> > >> -- > >> Srinivasan Venkataramanan > >> ASIC Design Engineer > >> Chennai, India > >> > >> Sent via Deja.com http://www.deja.com/ > >> Before you buy. > > Hello good morning > > I would like to get HDL simulator for free of cost. > > could anybody suggest me , how can get that simulator? > > Regards > > Md Karim > > > That original post is 20 years old! > > You can download free design tools suites from Intel/Altera, Xilinx, > Lattice and Microchip. They all include simulators, for VHDL and > Verilog. For basic work they would all be OK. > > MK Hi Thanks , I have been trying to install it since ten, but it did not work perfectly after installation. From newsfish@newsfish Thu Aug 1 00:46:21 2024 X-Received: by 2002:ad4:5966:: with SMTP id eq6mr89574qvb.116.1639603714505; Wed, 15 Dec 2021 13:28:34 -0800 (PST) X-Received: by 2002:a25:5f11:: with SMTP id t17mr8265112ybb.633.1639603714300; Wed, 15 Dec 2021 13:28:34 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Dec 2021 13:28:34 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:f9ee:1a24:df63:2afe; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:f9ee:1a24:df63:2afe User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Process sensitivity list - why doesn't the process enter when signals on it's sensitivity list change. From: A Injection-Date: Wed, 15 Dec 2021 21:28:34 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 8 Xref: reader02.eternal-september.org comp.lang.vhdl:9843 Hello, I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself. https://www.edaplayground.com/x/Qx_J My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized. Thanks From newsfish@newsfish Thu Aug 1 00:46:21 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!aioe.org!LX3j8ejFoLXdTP0+wM+jVA.user.46.165.242.75.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: Re: Process sensitivity list - why doesn't the process enter when signals on it's sensitivity list change. Date: Thu, 16 Dec 2021 12:50:34 +0200 Organization: Aioe.org NNTP Server Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: gioia.aioe.org; logging-data="55883"; posting-host="LX3j8ejFoLXdTP0+wM+jVA.user.gioia.aioe.org"; mail-complaints-to="abuse@aioe.org"; User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:96.0) Gecko/20100101 Thunderbird/96.0 X-Notice: Filtered by postfilter v. 0.9.2 Content-Language: en-US X-Antivirus-Status: Clean X-Antivirus: AVG (VPS 211215-4, 12/15/2021), Outbound message Xref: reader02.eternal-september.org comp.lang.vhdl:9844 On 15/12/2021 23:28, A wrote: > Hello, > > I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself. > > https://www.edaplayground.com/x/Qx_J > > My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized. > > Thanks in process (A, B, C).... there is no wait statement, so time didn't advances HTH -- Cet email a fait l'objet d'une analyse antivirus par AVG. http://www.avg.com From newsfish@newsfish Thu Aug 1 00:46:21 2024 X-Received: by 2002:a05:620a:4107:: with SMTP id j7mr13040661qko.645.1639679846219; Thu, 16 Dec 2021 10:37:26 -0800 (PST) X-Received: by 2002:a5b:18c:: with SMTP id r12mr15028240ybl.553.1639679845964; Thu, 16 Dec 2021 10:37:25 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Dec 2021 10:37:25 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:90fc:3fb3:685b:a92a; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:90fc:3fb3:685b:a92a References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Process sensitivity list - why doesn't the process enter when signals on it's sensitivity list change. From: A Injection-Date: Thu, 16 Dec 2021 18:37:26 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 21 Xref: reader02.eternal-september.org comp.lang.vhdl:9845 On Thursday, December 16, 2021 at 2:50:49 AM UTC-8, Maurice SAAB wrote: > On 15/12/2021 23:28, A wrote: > > Hello, > > > > I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself. > > > > https://www.edaplayground.com/x/Qx_J > > > > My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized. > > > > Thanks > in process (A, B, C).... there is no wait statement, so time didn't advances > > HTH > > > > -- > Cet email a fait l'objet d'une analyse antivirus par AVG. > http://www.avg.com Process is sensitive to A.B.C - so can't have wait statement in the process. No wait when there is sensitivity list - VHDL rule. From newsfish@newsfish Thu Aug 1 00:46:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!aioe.org!LX3j8ejFoLXdTP0+wM+jVA.user.46.165.242.75.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: Re: Process sensitivity list - why doesn't the process enter when signals on it's sensitivity list change. Date: Thu, 16 Dec 2021 21:37:57 +0200 Organization: Aioe.org NNTP Server Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: gioia.aioe.org; logging-data="47456"; posting-host="LX3j8ejFoLXdTP0+wM+jVA.user.gioia.aioe.org"; mail-complaints-to="abuse@aioe.org"; User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:96.0) Gecko/20100101 Thunderbird/96.0 Content-Language: en-US X-Notice: Filtered by postfilter v. 0.9.2 X-Antivirus-Status: Clean X-Antivirus: AVG (VPS 211215-4, 12/15/2021), Outbound message Xref: reader02.eternal-september.org comp.lang.vhdl:9846 On 16/12/2021 20:37, A wrote: > On Thursday, December 16, 2021 at 2:50:49 AM UTC-8, Maurice SAAB wrote: >> On 15/12/2021 23:28, A wrote: >>> Hello, >>> >>> I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself. >>> >>> https://www.edaplayground.com/x/Qx_J >>> >>> My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized. >>> >>> Thanks >> in process (A, B, C).... there is no wait statement, so time didn't advances >> >> HTH >> >> >> >> -- >> Cet email a fait l'objet d'une analyse antivirus par AVG. >> http://www.avg.com > > Process is sensitive to A.B.C - so can't have wait statement in the process. No wait when there is sensitivity list - VHDL rule. Seems working with my (old) simulator: ENTER: At Time = 0 ns INPUT = 'U''U''U' EXIT: At Time = 0 ns iOUT1 = 'U''U''U' ENTER: At Time = 1 ns INPUT = '0''U''U' EXIT: At Time = 1 ns iOUT1 = '0''U''U' ENTER: At Time = 11 ns INPUT = '0''0''U' EXIT: At Time = 11 ns iOUT1 = '0''0''U' ENTER: At Time = 15 ns INPUT = '0''0''0' EXIT: At Time = 15 ns iOUT1 = '0''0''0' ENTER: At Time = 26 ns INPUT = '1''0''0' EXIT: At Time = 26 ns iOUT1 = '1''0''0' ENTER: At Time = 36 ns INPUT = '1''1''0' EXIT: At Time = 36 ns iOUT1 = '1''1''0' ENTER: At Time = 40 ns INPUT = '1''1''1' EXIT: At Time = 40 ns iOUT1 = '1''1''1' there is ENTER at 36ns when B changes From newsfish@newsfish Thu Aug 1 00:46:22 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: Process sensitivity list - why doesn't the process enter when signals on it's sensitivity list change. Date: Thu, 16 Dec 2021 19:09:59 -0600 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 17 Dec 2021 01:10:02 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="dad400a432ec3c53eaa81b06fe7d1f88"; logging-data="2457"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18AZO2J8C4lRoZnjO/FUFvkAC3PZNdpjrA=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:zDkn053NVgBvIW/WHdGsmQhRJ2Q= In-Reply-To: Xref: reader02.eternal-september.org comp.lang.vhdl:9847 On 2021-12-15 15:28, A wrote: > Hello, > > I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself. > > https://www.edaplayground.com/x/Qx_J > > My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized. > > Thanks > The main problem is that signals B and C are being driven by two processes. Unless you are dealing with tri-state logic this is usually a no-no. Remember that in VHDL a signal is not a variable in the sense that you would think of a variable in a conventional programming language. An assignment statement for a signal (<=) within a process or in a stand-alone concurrent statement creates a driver for that signal. So, in the example you pointed to, B and C have conflicting drivers. Another problem is that signal B appears in the sensitivity list of the first process and also appears on the left-hand side of an assignment statement in that process. This is also usually a no-no since the feedback can cause endless loops in some cases. (Trust me, over the past few months I have been solving some simulator hang problems in somebody else's logic caused by process feedback.) Charles Bailey From newsfish@newsfish Thu Aug 1 00:46:22 2024 X-Received: by 2002:ad4:5dcc:: with SMTP id m12mr3964795qvh.12.1639766831375; Fri, 17 Dec 2021 10:47:11 -0800 (PST) X-Received: by 2002:a25:c6d7:: with SMTP id k206mr5875210ybf.756.1639766831177; Fri, 17 Dec 2021 10:47:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 17 Dec 2021 10:47:10 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:c0ce:7cbc:482b:3d67; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:c0ce:7cbc:482b:3d67 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0a41f27b-8836-4505-8b80-5308f9c216ben@googlegroups.com> Subject: Re: Process sensitivity list - why doesn't the process enter when signals on it's sensitivity list change. From: A Injection-Date: Fri, 17 Dec 2021 18:47:11 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 41 Xref: reader02.eternal-september.org comp.lang.vhdl:9848 On Thursday, December 16, 2021 at 11:38:15 AM UTC-8, Maurice SAAB wrote: > On 16/12/2021 20:37, A wrote: > > On Thursday, December 16, 2021 at 2:50:49 AM UTC-8, Maurice SAAB wrote: > >> On 15/12/2021 23:28, A wrote: > >>> Hello, > >>> > >>> I am perplexed with VHDL behavior in the example I tried on EDA Playground. Here's the link so that you can simulate yourself. > >>> > >>> https://www.edaplayground.com/x/Qx_J > >>> > >>> My question is why doesn't the process enter when 'B' changes? The process seems to remain stuck at time 0 - with A, B, C values as Uninitialized. > >>> > >>> Thanks > >> in process (A, B, C).... there is no wait statement, so time didn't advances > >> > >> HTH > >> > >> > >> > >> -- > >> Cet email a fait l'objet d'une analyse antivirus par AVG. > >> http://www.avg.com > > > > Process is sensitive to A.B.C - so can't have wait statement in the process. No wait when there is sensitivity list - VHDL rule. > Seems working with my (old) simulator: > ENTER: At Time = 0 ns INPUT = 'U''U''U' > EXIT: At Time = 0 ns iOUT1 = 'U''U''U' > ENTER: At Time = 1 ns INPUT = '0''U''U' > EXIT: At Time = 1 ns iOUT1 = '0''U''U' > ENTER: At Time = 11 ns INPUT = '0''0''U' > EXIT: At Time = 11 ns iOUT1 = '0''0''U' > ENTER: At Time = 15 ns INPUT = '0''0''0' > EXIT: At Time = 15 ns iOUT1 = '0''0''0' > ENTER: At Time = 26 ns INPUT = '1''0''0' > EXIT: At Time = 26 ns iOUT1 = '1''0''0' > ENTER: At Time = 36 ns INPUT = '1''1''0' > EXIT: At Time = 36 ns iOUT1 = '1''1''0' > ENTER: At Time = 40 ns INPUT = '1''1''1' > EXIT: At Time = 40 ns iOUT1 = '1''1''1' > > there is ENTER at 36ns when B changes Thanks Maurice. But the reason it worked for you is because I had changed the model (drive A first) to make it work. If you try it again, it'll show the behavior as I explained in my original post. From newsfish@newsfish Thu Aug 1 00:46:23 2024 X-Received: by 2002:ac8:5bca:: with SMTP id b10mr3739798qtb.170.1639767012660; Fri, 17 Dec 2021 10:50:12 -0800 (PST) X-Received: by 2002:a5b:18c:: with SMTP id r12mr6076842ybl.553.1639767012480; Fri, 17 Dec 2021 10:50:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 17 Dec 2021 10:50:12 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:c0ce:7cbc:482b:3d67; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:c0ce:7cbc:482b:3d67 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Process sensitivity list - why doesn't the process enter when signals on it's sensitivity list change. From: A Injection-Date: Fri, 17 Dec 2021 18:50:12 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 41 Xref: reader02.eternal-september.org comp.lang.vhdl:9849 On Thursday, December 16, 2021 at 5:10:05 PM UTC-8, Charles Bailey wrote: > On 2021-12-15 15:28, A wrote:=20 > > Hello,=20 > >=20 > > I am perplexed with VHDL behavior in the example I tried on EDA Playgro= und. Here's the link so that you can simulate yourself.=20 > >=20 > > https://www.edaplayground.com/x/Qx_J=20 > >=20 > > My question is why doesn't the process enter when 'B' changes? The proc= ess seems to remain stuck at time 0 - with A, B, C values as Uninitialized.= =20 > >=20 > > Thanks=20 > > > The main problem is that signals B and C are being driven by two=20 > processes. Unless you are dealing with tri-state logic this is usually=20 > a no-no. Remember that in VHDL a signal is not a variable in the sense=20 > that you would think of a variable in a conventional programming=20 > language. An assignment statement for a signal (<=3D) within a process or= =20 > in a stand-alone concurrent statement creates a driver for that signal.= =20 > So, in the example you pointed to, B and C have conflicting drivers.=20 >=20 > Another problem is that signal B appears in the sensitivity list of the= =20 > first process and also appears on the left-hand side of an assignment=20 > statement in that process. This is also usually a no-no since the=20 > feedback can cause endless loops in some cases. (Trust me, over the=20 > past few months I have been solving some simulator hang problems in=20 > somebody else's logic caused by process feedback.)=20 >=20 > Charles Bailey Thanks Charles. Multiple drivers is a good point. I was aware of this but I= wanted to see if the process would at least enter once, when 'B' changes. = I think since 'A' drives B and since A is 'U' at time zero; when B goes to = '0', the multiple drivers get resolved to 'U' and the sensitivity list does= not see a change in 'B'. Confusing explanation but that's the only way I c= an see why the process does not trigger when 'B' changes at time 1ns. Thank= s again. From newsfish@newsfish Thu Aug 1 00:46:23 2024 X-Received: by 2002:a05:620a:2849:: with SMTP id h9mr16499973qkp.766.1642491404466; Mon, 17 Jan 2022 23:36:44 -0800 (PST) X-Received: by 2002:a5b:dcd:: with SMTP id t13mr30913619ybr.46.1642491404152; Mon, 17 Jan 2022 23:36:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jan 2022 23:36:43 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=151.29.178.131; posting-account=AXSUuQoAAACXwhXPPNv87DD39TdEGi6i NNTP-Posting-Host: 151.29.178.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1603933a-f563-4106-9800-531023b5b1e9n@googlegroups.com> Subject: ces_util_lib, yet another VHDL Utility Library? From: Andrea Campera Injection-Date: Tue, 18 Jan 2022 07:36:44 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 10 Xref: reader02.eternal-september.org comp.lang.vhdl:9850 Yes, another one. This is a library of modules and functions we have been used for over 8 years in our Company, Campera Electronic Systems Srl (www.campera-es.com), in more than 80 projects for our Customers. This library is field and hardware proven, it is the Swiss Army Knife of every FPGA designer. All the modules are vendor independent high quality VHDL code. Realeased under MIT license on GitHub, https://github.com/campera-es/ces_util_lib Feel free to use it, test it, improve it, share it! All the best, Andrea From newsfish@newsfish Thu Aug 1 00:46:24 2024 X-Received: by 2002:a37:b2c1:: with SMTP id b184mr12057121qkf.53.1643042622982; Mon, 24 Jan 2022 08:43:42 -0800 (PST) X-Received: by 2002:a25:bd43:: with SMTP id p3mr24954832ybm.480.1643042622565; Mon, 24 Jan 2022 08:43:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Jan 2022 08:43:42 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=2409:4071:2184:9b30:dd9e:f240:cb2d:9bd9; posting-account=JGJssAoAAACtJh-a0utzwb9BVzLUd8La NNTP-Posting-Host: 2409:4071:2184:9b30:dd9e:f240:cb2d:9bd9 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <95d327a6-7d2e-45a4-bbcd-f2bc735e49b7n@googlegroups.com> Subject: Matlab From: 4AI18EC074 Pranavi K Injection-Date: Mon, 24 Jan 2022 16:43:42 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 1 Xref: reader02.eternal-september.org comp.lang.vhdl:9851 Hi, Where can I find the free version of matlab? From newsfish@newsfish Thu Aug 1 00:46:24 2024 X-Received: by 2002:a05:620a:410:: with SMTP id 16mr12663938qkp.179.1643061811895; Mon, 24 Jan 2022 14:03:31 -0800 (PST) X-Received: by 2002:a25:11c1:: with SMTP id 184mr26134421ybr.259.1643061808917; Mon, 24 Jan 2022 14:03:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Jan 2022 14:03:28 -0800 (PST) In-Reply-To: <95d327a6-7d2e-45a4-bbcd-f2bc735e49b7n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:b855:470c:302a:521; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:b855:470c:302a:521 References: <95d327a6-7d2e-45a4-bbcd-f2bc735e49b7n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <08b2ed30-f029-4ddc-b3d9-299967ed4f84n@googlegroups.com> Subject: Re: Matlab From: KJ Injection-Date: Mon, 24 Jan 2022 22:03:31 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 3 Xref: reader02.eternal-september.org comp.lang.vhdl:9852 On Monday, January 24, 2022 at 11:43:45 AM UTC-5, 4AI18EC074 Pranavi K wrote: > Hi, > Where can I find the free version of matlab? Matlab is not free but there is a 30 day trial available so you can use it for 'free' for that period of time. From newsfish@newsfish Thu Aug 1 00:46:24 2024 Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Matlab References: <95d327a6-7d2e-45a4-bbcd-f2bc735e49b7n@googlegroups.com> <08b2ed30-f029-4ddc-b3d9-299967ed4f84n@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/1.0.3 (Linux) Message-ID: Organization: Newsxs Date: Tue, 25 Jan 2022 09:35:29 +0100 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!news-out.netnews.com!news.alt.net!fdc2.netnews.com!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!feed.abavia.com!abe004.abavia.com!abp002.abavia.com!news.newsxs.nl!not-for-mail Lines: 15 Injection-Date: Tue, 25 Jan 2022 09:35:29 +0100 Injection-Info: news.newsxs.nl; mail-complaints-to="abuse@newsxs.nl" X-Received-Bytes: 1260 Xref: reader02.eternal-september.org comp.lang.vhdl:9853 On 2022-01-24 KJ wrote in comp.lang.vhdl: > On Monday, January 24, 2022 at 11:43:45 AM UTC-5, 4AI18EC074 Pranavi K wrote: >> Hi, >> Where can I find the free version of matlab? > Matlab is not free but there is a 30 day trial available so you can use it for 'free' for that period of time. There are free alternatives that may be of use to you, some listed here: https://www.educba.com/matlab-alternatives/ -- Stef tmps_base = tmps_max; /* protect our mortal string */ -- Larry Wall in stab.c from the perl source code From newsfish@newsfish Thu Aug 1 00:46:25 2024 X-Received: by 2002:a05:6214:5006:: with SMTP id jo6mr3715785qvb.67.1644461657709; Wed, 09 Feb 2022 18:54:17 -0800 (PST) X-Received: by 2002:a25:6405:: with SMTP id y5mr1955453ybb.756.1644461657437; Wed, 09 Feb 2022 18:54:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Feb 2022 18:54:17 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=84.198.244.197; posting-account=92sShAoAAAAzHXgXCOAyZ2siq7qe85er NNTP-Posting-Host: 84.198.244.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <364afc01-4230-4b46-bc31-ca48d86686f2n@googlegroups.com> Subject: =?UTF-8?Q?=23MARINABERLUSCONI_=C3=89_ASSASSINA=2C_LESBICA_E_PEDOFILA=21_?= =?UTF-8?Q?SI=2C_PROPRIO_PROPRIO_COS=C3=8D=21_=C3=89_COCAINOMANE=2C_ASSASSINA_E_PERVE?= =?UTF-8?Q?RTITA_PEDOFILA_COME_IL_PADRE=3A_MARINA_BERLUSCONI_DI_CRIMINALI?= =?UTF-8?Q?SSIMA_=23FININVEST_E_CRIMINALISSIMA_=23MONDADORI=21_ASSASSINA_COME?= =?UTF-8?Q?_SUO_PADRE=3A_IL=2E=2E=2E=2E=2E=2E=2E?= From: ROBERTO LOSAPIO NH ANTI BERLUSCONIANI PRONTIATUTTO Injection-Date: Thu, 10 Feb 2022 02:54:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 491 Xref: reader02.eternal-september.org comp.lang.vhdl:9854 #MARINABERLUSCONI =C3=89 ASSASSINA, LESBICA E PEDOFILA! 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I TOPI DI FOGNA KILLER #SILVIOBERLUSCONI, #P= IERSILVIOBERLUSCONI E #MARINABERLUSCONI HAN FATTO UCCIDERE IN VITA LORO, AL= MENO 900 PERSONE, QUASI SEMPRE PER BENISSIMO! LA LORO SPECIALIT=C3=81 =C3= =89 ORGANIZZARE OMICIDI MASSONICI! OSSIA DA FAR PASSARE PER FINTI SUICIDI, = MALORI, INCIDENTI (VEDI COME HANNO UCCISO LENTAMENTE, IN MANIERA MASSONICIS= SIMA, LA GRANDE #IMANEFADIL, MA PURE GLI AVVOCATI VICINI A IMANE FADIL, #EG= IDIOVERZINI E #MAURORUFFFINI, MA ANCHE TANTISSIMI MAGISTRATI GIOVANI CHE LI= STAVANO INDAGANDO SEGRETAMENTE O NON, COME #GABRIELECHELAZZI, #ALBERTOCAPE= RNA, #PIETROSAVIOTTI, #MARCELLOMUSSO, #FRANKDIMAIO, PER NON DIRE DI COME HA= N MACELLATO GLI EROI #GIOVANNIFALCONE E #PAOLOBORSELLINO)! IL TUTTO IN COMB= UTTA CON SERVIZI SEGRETI NAZI=E5=8D=90FASCISTI, BASTARDA MASSONERIA DI ESTR= EMA DESTRA (VEDI #P2 P2 O #LOGGIADELDRAGO LOGGIA DEL DRAGO, OSSIA LOGGIA PE= RSONALE DEL PEZZO DI MERDA PEDOFILO E STRAGISTA #SILVIOBERLUSCONI). OLTRE C= HE IN STRA COMBUTTA CON LORO VARIE COSA NOSTRA, CAMORRA, NDRANGHETA, MAFIA = RUSSA, MAFIA CINESE, MAFIA COLOMBIANA, MAFIE DI TUTTO IL PIANETA TERRA. OGGI VORREI SCRIVERE PURE, DI QUEL TOPO DI FOGNA CORROTTISSIMO, ANZI "BERLU= $$$CORROTTISSIMO", CHE =C3=89 IL GIUDICE PI=C3=9A STECCATO DEL MONDO: #MARC= OTREMOLADA DEL #RUBYTER! MASSONE DI MILLE LOGGE D'UNGHERIA (MA PURE DI BULG= ARIA, CECOSLOVACCHIA E CAMBOGIA DI POL POT, TANTO CHE CI SIAMO, MEGLIO IRON= IZZARCI SOPRA UN POCO, PLEASE). FOGNA STUPRA GIUSTIZIA MARCO TREMOLADA DEL = RUBY TER, MASSONE SATANISTA NAZI=E5=8D=90FASCISTA CORROTTISSIMO DA SILVIO B= ERLUSCONI, PIERSILVIO BERLUSCONI E MARINA BERLUSCONI! STO BERLU$$$CORROTTO = SGOZZA GIUSTIZIA DI #MARCOTREMOLADA (LO VEDETE QUI https://l450v.alamy.com/450vfr/2ded6pm/milan-italie-30-novembre-2020-milan-= ruby-ter-proces-a-la-foire-president-marco-tremolada-usage-editorial-seulem= ent-credit-agence-de-photo-independante-alamy-live-news-2ded6pm.jpg ) =C3= =89 IL NUOVO #CORRADOCARNEVALE MISTO A #RENATOSQUILLANTE E #VITTORIOMETTA. = ESSENDO IO, ANDREAS NIGG DI BANK J SAFRA SARASIN, STATO DEFINITO BANCHIERE = SVIZZERO DELL'ANNO, SIA NEL 2018, 2019 E 2020, E CON MIA GRAN EMOZIONE, PUR= E NEL 2021, HO FATTO LE MIE INDAGINI E S=C3=93 PER STRA CERTO, CHE STO MASS= ONE NAZI=E5=8D=90FASCISTA PREZZOLATO A PALLONE, DI #MARCOTREMOLADA DEL #RUB= YTER, HA GI=C3=81 A DISPOSIZIONE, PRESSO 7 DIVERSI FIDUCIARI ELVETICI, 3 ML= N DI =E2=82=AC, RICEVUTI AL FINE DI INIZIARE AD AZZOPPARE IL PROCESSO RUBY = TER (COME PUNTUALISSIMAMENTE ACCADUTO IL 3/11/2021). ALTRI 7 MLN DI =E2=82= =AC GLI ARRIVEREBBERO A PROCESSO COMPLETAMENTE MORTO. MI HA CONFERMATO CI= =C3=93, PURE IL VERTICE DEI SERVIZI SEGRETI SVIZZERI (CHE ESSENDO SEGRETI, = MI HAN IMPOSTO DI NON SCRIVERE NOMI E COGNOMI, COSA CHE DA BANCHIERE SPECCH= IATO, RISPETTO) ED IL GRAN MAESTRO DELLA GRAN LOGGIA SVIZZERA: #DOMINIQUEJU= ILLAND. D'ALTRONDE, SE ASCOLTATE SU #RADIORADICALE, TUTTE LE UDIENZE DEL PR= OCESSO, AHIM=C3=89 FARSA, #RUBYTER, VEDRETE CHE STA MERDA CORROTTA, NAZISTA= E NEO PIDUISTA DI #MARCOTREMOLADA DEL #RUBYTER STESSO (GIUDICE CORROTTO DA= SCHIFO, DI 1000 LOGGE D'UNGHERIA, BULGARIA, CECOSLOVACCHIA E PURE DI CAMBO= GIA DI POL POT, TANTO CHE CI SIAMO, MEGLIO IRONIZZARCI SOPRA UN POCO, PLEAS= E), SLINGUA INTELLETTUALMENTE (E FORSE, STILE OMOSESSUALE NAZISTA E COCAINO= MANE #LUCAMORISI, NON SOLO INTELLETTUALMENTE), TUTTE LE VOLTE, CON QUEL FIG= LIO DI CANE BERLU$$$CORRUTTORE CHE =C3=89 L'AVVOCATO CRIMINALISSIMO, DAVVER= O PEZZO DI MERDA, DAVVERO SGOZZATORE BASTARDO DI GIUSTIZIA, DEMOCRAZIA E LI= BERT=C3=81: #FEDERICOCECCONI. OGNI VOLTA CHE VI =C3=89 STATO UN CONTRASTO F= RA GLI EROICI PM #TIZIANASICILIANO E #LUCAGAGLIO E STO FIGLIO DI PUTTANONA = MASSOMAFIOSO E DELINQUENTE, CHE =C3=89 L'AVVOCATO BASTARDO FEDERICO CECCONI= , IL GIUDICE MASSONE E NAZIFASCISTA, TANTO QUANTO STRA CORROTTO, ALIAS IL B= ERLUSCONICCHIO DI MERDA #MARCOTREMOLADA, COSTUI HA SEMPRE DATO RAGIONE AL S= ECONDO. QUESTO APPARE EVIDENTE PURE ALLE MURA DEL TRIBUNALE MENEGHINO. CHE = MI FACCIA AMMAZZARE PURE, STA MERDA PREZZOLATA, STO GIUDICE VENDUTISSIMO, C= ORROTTISSIMO, STO TOPO DI FOGNA DI ARCORE^HARDCORE ( ^ STA PER MASSONERIA S= ATANICA, MA PURE PER VAGINA DISPONIBILE A GO GO... VISTO CHE SCRIVO DI ARCO= RE^HARDCORE), CHE =C3=89 IL GIUDICE CRIMINALISSIMO MARCO TREMOLADA DEL RUBY= TER. MA IO, AL MALE BERLUSCONICCHIO, NON MI PIEGO E PIEGHER=C3=93 MAI, MEG= LIO MORTO PIUTTOSTO. HO POCO TEMPO, DEVO PRODURRE PER LA MIA BANCA, J SAFRA= SARASIN ZURICH. MA QUESTO =C3=89 SOLO UN MINI MINI MINI ANTIPASTO. MILIARD= I DI MIEI POSTS E PROFILI DI OGNI TIPO INVADERANNO TUTTI I SITI DEL MONDO, = FINO A CHE LEGGER=C3=93 CHE TUTTI I BASTARDI MEGA ASSASSINI #BERLUSCONI HAN= FATTO UNA FINE MOLTO PEGGIORE DEI #LIGRESTI O #TANZI, CHE A DIFFERENZA DEI= FIGLI DI PEDOFILI E TROIONE BERLUSCONI, NON HAN MAI PARTICOLARMENTE FATTO = UCCIDERE NESSUNO, E CHE QUINDI, A LORO CONFRONTO, SON ANGELINI (NON ANGELUC= CI, MA ANGELINI, NON #ANTONIOANGELUCCI, QUELLO =C3=89 UN PEDOFILO FASCISTA,= UN MASSONE SATANISTISSIMO, UN PEZZO DI MERDA SATA=E5=8D=90NAZISTA, MAFIOSO= ED ASSASSINO COME SILVIO BERLUSCONI). VENIAMO AI FATTI, NOW, PLEASE. IL CO= CAINOMANE NAZIST=E5=8D=8DASSASSINO #PIERSILVIOBERLUSCONI, IL PEDOFILO MACEL= LA MAGISTRATI #SILVIOBERLUSCONI E LA LESBICA LECCA FIGHE DI BAMBINE E RAGAZ= ZINE #MARINABERLUSCONI, - INSIEME AL FASCISTASSASSINO #ROBERTOJONGHILAVARINI ROBERTO JONGHI LAVARIN= I DI CRIMINALISSIMO ISTITUTO GANASSINI DI RICERCHE BIOMEDICHE E CRIMINALISS= IMO MOVIMENTO #FAREFRONTE FARE FRONTE - INSIEME AL FASCISTASSASSINO #GIANFRANCOSTEFANIZZI (PURE PEDOFILO E FILO N= DRANGHETISTA) DI CRIMINALISSIMO STUDIO MOAI #MOAI #STUDIOMOAI #MOAISTUDIO - INSIEME AL FASCISTASSASSINO, CORROTTO DI MERDA, PAPPA TANGENTI, LADRONE #= CARLOFIDANZA DI FRATELLI (MASSONI E SPECIALMENTE NDRANGHETISTI) D'ITALIA -INSIEME AL TRIONE SCOPATO IN CULO DA 1000 MAFIOSI E NAZISTI #SILVIASARDONE= DI #LEGALADRONA - INSIEME AL FASCISTASSASSINO #PAOLO PARRAI ALIAS #PAOLOPIETROBARRAI (PURE = PEDOFILO ED AFFILIATO ALLA NDRANGHETA) DI CRIMINALE TERRANFT E TERRABITCOIN= #TERRANFT E CRIMINALE #TERRABITCOIN -INSIEME AL FIGLIO DI PUTTANA PEDOFILO ED ASSASSINO #LEOZAGAMI, SI, SCRIVO = PROPRIO DEL MONARCHICO DI MIA GROSSO CAZZO, NAZISTA, RAZZISTA, ANTI SEMITA,= FILO MAFIOSO, TERRORISTA NERO (E CHE INCASSA IN NERO), FROCIONE SEMPRE SBO= RRATO DA TUTTI IN CULO: LEO ZAGAMI. TRA L'ALTRO, PURE NOTO CORNUTONE #LEOZA= GAMI (LA SUA TROIONA MOGLIE #CHRISTYZAGAMI CHRISTY ZAGAMI SE LA SCOPANO IN = TANTISSIMI, IN TANTI CLUB PER SCAMBISTI DI MEZZO MONDO, PRESTO NE DETTAGLIE= REMO A RAFFICA) -INSIEME AL MASSONE ROSACROCIANO NDRANGHETISTA OMICIDA GIANFRANCO PECORARO = #GIANFRANCOPECORARO NOTO COME PEDOFILO ASSASSINO #CARPEORO CARPEORO SON VENUTI SPESSO A CHIEDERMI DI RICICLARE CENTINAIA DI MILIONI DI EURO, DI= MAFIE DI TUTTO IL MONDO, CHE, MI HAN DETTO, HAN SOTTO TERRA, IN VARIE VILL= E LORO, COME PURE UN ALTRE VILLE DI LORO SODALI ASSASSINI. HO SEMPRE SBATTU= TO LORO LA PORTA IN FACCIA. SIA A LORO, CHE A UN LORO AVVOCATO MASSONE, SAT= ANISTA, PEDOFILO, SPECIALISTA NEL RAPIRE, INCULARE ED UCCIDERE BAMBINI PER = VENDERNE GLI ORGANI: #DANIELEMINOTTI DI GENOVA RAPALLO (E A RAPALLO, "GUARD= A CASO", HA RESIDENZA IL TESTA DI CAZZO STRA ASSASSINO #PIERSILVIOBERLUSCON= I). SCRIVER=C3=93 DETTAGLI A PROPOSITO DI QUESTO, IN MILIARDI DI MIEI PROSS= IMI POSTS. PER IL MOMENTO, ORA, INIZIAMO AD ESAMINARE LA FIGURA DI QUESTO A= VVOCATO PEDOFILO, NAZI=E5=8D=90FASCISTA, MASSO=E5=8D=90NAZISTA, SATA=E5=8D= =90NAZISTA, ASSASSINO DANIELE MINOTTI DI CRIMINALISSIMO STUDIO LEGALE LISI.= SONO ANDREAS NIGG DI BANK J SAFRA SARASIN ZURICH. PREMIATO NEL 2018, 2019,= 2020 E 2021 COME BANCHIERE SVIZZERO DELL'ANNO, A BASILEA. IN OGNI CASO, IL= MIO MOTTO =C3=89 MASSIMA UMILT=C3=80, FAME ESTREMA DI VITTORIE E PIEDI PER= TERRA! SON LE UNICHE CHIAVI PER FARE LA STORIA! LEGGETE QUESTO TESTO, ORA, PLEASE, DOVE INIZIO A SCRIVERE PROPRIO DEL MASSO= NE SATANISTA NAZISTA SATA=E5=8D=8DNAZISTA BERLUSCONICCHIO DANIELE MINOTTI: = AVVOCATO ASSASSINO DI GENOVA E CRIMINALE STUDIO LEGALE LISI, NOTO PER RAPIR= E, SODOMIZZARE ED UCCIDERE TANTISSIMI BAMBINI OGNI ANNO. CIAO A TUTTI. https://citywireselector.com/manager/andreas-nigg/d2395 https://ch.linkedin.com/in/andreasnigg https://www.blogger.com/profile/13220677517437640922 1 =C3=89 DA ARRESTARE PRIMA CHE FACCIA UCCIDERE ANCORA, L'AVVOCATO PEDOFILO, = BERLUSCO=E5=8D=90NAZISTA, FASCIOLEGHISTA, ASSASSINO DANIELE MINOTTI (FACEBO= OK, TWITTER) DI GENOVA, RAPALLO E CRIMINALISSIMO STUDIO LEGALE LISI. =C3=89 DA FERMARE PER SEMPRE, L'AVVOCATO SATANISTA, NAZISTA, SATA=E5=8D=90N= AZISTA, PEDERASTA, OMICIDA #DANIELEMINOTTI DI RAPALLO E GENOVA: RAPISCE, IN= CULA, UCCIDE TANTI BIMBI, SIA PER VENDERNE GLI ORGANI (COME DA QUESTA ABERR= ANTE FOTO https://www.newnotizie.it/wp-content/uploads/2016/07/Egypt-Organ-Harvesting= -415x208.jpg), CHE PER RITI MASSONICO^SATANISTI, CHE FA IN MILLE SETTE! =C3=89 DI PERICOLO PUBBLICO ENORME, L'AVV ASSASSINO E PEDERASTA DANIELE MIN= OTTI (FACEBOOK) DI RAPALLO E GENOVA! AVVOCATO STUPRANTE INFANTI ED ADOLESCE= NTI, COME PURE KILLER #DANIELEMINOTTI DI CRIMINALISSIMO #STUDIOLEGALELISI D= I LECCE E MILANO ( https://studiolegalelisi.it/team/daniele-minotti/ STUDIO LEGALE MASSO^MAFIOSO LISI DI LECCE E MILANO, DA SEMPRE TUTT'UNO CON = MEGA KILLERS DI COSA NOSTRA, CAMORRA, NDRANGHETA, E, COME DA SUA SPECIALITA= ' PUGLIESE, ANCOR PI=C3=9A, DI SACRA CORONA UNITA, MAFIA BARESE, MAFIA FOGG= IANA, MAFIA DI SAN SEVERO)! =C3=89 STALKER DIFFAMATORE VIA INTERNET, NONCH= =C3=89 PEDERASTA CHE VIOLENTA ED UCCIDE BIMBI, QUESTO AVVOCATO OMICIDA CHIA= MATO DANIELE MINOTTI! QUESTO AVVOCATO SATANISTA, NAZISTA, SATA=E5=8D=90NAZI= STA, PEDOFILO E SANGUINARIO, DI RAPALLO E GENOVA (LO VEDETE A SINISTRA, SOP= RA SCRITTA ECOMMERCE https://i.ytimg.com/vi/LDoNHVqzee8/maxresdefault.jpg) RAPALLO: OVE ORGANIZZA TRAME OMICIDA E TERRORISMO DI ESTREMA DESTRA, INSIEM= E "AL RAPALLESE" DI RESIDENZA, HITLERIANO, RAZZISTA, KU KLUK KLANISTA, MAFI= OSO E RICICLA SOLDI MAFIOSI COME SUO PADRE: VI ASSICURO, ANCHE ASSASSINO #P= IERSILVIOBERLUSCONI PIERSILVIO BERLUSCONI! SI, SI =C3=89 PROPRIO COS=C3=8D:= =C3=89 DA ARRESTARE SUBITO L'AVVOCATO SATANISTA, NAZISTA, SATA=E5=8D=90NAZ= ISTA, PEDOFILO E KILLER DANIELE MINOTTI DI GENOVA E RAPALLO! https://www.py.cz/pipermail/python/2017-March/012979.html OGNI SETTIMANA SGOZZA, OLTRE CHE GATTI E SERPENTI, TANTI BIMBI, IN RITI SAT= ANICI. IN TUTTO NORD ITALIA (COME DA LINKS CHE QUI SEGUONO, I FAMOSI 5 STUD= ENTI SCOMPARSI NEL CUNEENSE FURONO UCCISI, FATTI A PEZZI E SOTTERRATI IN VA= RI BOSCHI PIEMONTESI E LIGURI, PROPRIO DALL'AVVOCATO SATANISTA, PEDOFILO ED= ASSASSINO DANIELE MINOTTI DI RAPALLO E GENOVA https://www.ilfattoquotidiano.it/2013/05/29/piemonte-5-ragazzi-suicidi-in-s= ette-anni-pm-indagano-sullombra-delle-sette-sataniche/608837/ https://www.adnkronos.com/fatti/cronaca/2019/03/02/satanismo-oltre-mille-sc= omparsi-anni_QDnvslkFZt8H9H4pXziROO.html) E' DAVVERO DA ARRESTARE SUBITO, PRIMA CHE AMMAZZI ANCORA, L'AVVOCATO PEDOFI= LO, STUPRANTE ED UCCIDENTE BAMBINI: #DANIELEMINOTTI DI RAPALLO E GENOVA! https://www.studiominotti.it Studio Legale Minotti Address: Via della Libert=C3=A0, 4, 16035 Rapallo GE, Phone: +39 335 594 9904 NON MOSTRATE MAI E POI MAI I VOSTRI FIGLI AL PEDOFIL-O-MOSESSUALE COCAINOMA= NE E KILLER DANIELE MINOTTI (QUI IN CHIARO SCURO MASSONICO, PER MANDARE OVV= I MESSAGGI LUCIFERINI https://i.pinimg.com/280x280_RS/6d/04/4f/6d044f51fa89= a71606e662cbb3346b7f.jpg ). PURE A CAPO, ANZI A KAP=C3=93 DI UNA SETTA ASSA= SSINA DAL NOME ELOQUENTE : " AMMAZZIAMO PER NOSTRI SATANA IN TERRA: SILVIO = BERLUSCONI, GIORGIA MELONI E MATTEO SALVINI". UNITO IN CI=C3=93, AL PARIMENTI AVVOCATO MASSONE, FASCISTA, LADRO, TRUFFATO= RE, RICICLA SOLDI MAFIOSI, OMICIDA E MOLTO PEDOFILO #FULVIOSARZANADISANTIPP= OLITO FULVIO SARZANA DI SANT'IPPOLITO. ED INSIEME AL VERME SATA=E5=8D=90NAZISTA E COCAINOMANE #MARIOGIORDANO MARIO= GIORDANO. FOTO ELOQUENTE A PROPOSITO https://www.rollingstone.it/cultura/f= enomenologia-delle-urla-di-mario-giordano/541979/ MARIO GIORDANO =C3=89 NOTO MASSONE OMOSESSUALE DI TIPO ^OCCULTO^ (=C3=89 FR= OCIO=E5=8D=90NAZISTA SEGRETO COME IL SEMPRE SCOPATO E SBORRATO IN CULO #LUC= AMORISI), FA MIGLIAIA DI POMPINI E BEVE LITRI DI SPERMA DI RAGAZZINI, PER Q= UESTO AMA TENERE LA BOCCA SEMPRE APERTA. IL TUTTO INSIEME AL MAFIOSO AFFILIATO A COSA NOSTRA #CLAUDIOCERASA, ANCHE L= UI NOTO PEDOFILO (AFFILIATO MAFIOSO CLAUDIO CERASA: PUNCIUTO PRESSO FAMIGLI= A MEGA KILLER CIMINNA, MANDAMENTO DI CACCAMO). 2 ED INSIEME AL PRIMA TERRORISTA DI SINISTRA, POI TERRORISTA DI DESTRA #PAOLO= LIGUORI PAOLO LIGUORI. ED INSIEME AL FIGLIO DI CANE, DA SEMPRE PEDERASTA, A= SSASSINO E SATA=E5=8D=90NAZISTA #GIULIANOFERRARA GIULIANO FERRARA (SI, SCRI= VO PROPRIO DEL MASSONE, COCAINOIMANE, PEDERASTA, CHE PAGA DA ANNI RAGAZZINI= PERCH=C3=89 LO INCULINO: GIULIANO FERRARA #GIULIANOFERRARA)! ED INSIEME AL= LA PEDOFILA PAZZA, STUPRA E TORTURA BAMBINI #ANSELMADELLOLIO ANSELMA DEL'OL= IO (" PAZZA MA NON SCEMA", COME AMA FARSI DEFINIRE). E PURE INSIEME AL GI=C3=81 ARRESTATO, PEDERASTA KILLER GIUSEPPE LAZZARI: RE= GISTA CINEMATOGRAFICO DI BRESCIA CHE DROGA, INCULA ED UCCIDE TANTI BIMBI (REGISTA CINEMATOGRAFICO #GIUSEPPELAZZARI DI BRESCIA, DA DECENNI PEDOFILOMO= SESSUALE E COCAINOMANE https://www.mail-archive.com/racket...@googlegroups.com/msg46801.html CHE, COME VEDETE DA QUESTE BULLSHIT RECENSIONI, =C3=89 PAPPA E CICCIA CON L= A MASSONA PEDOFILA PRIMA CITATA #ANSELMADELLOLIO https://www.imdb.com/title/tt1828287/reviews VI ERA PRIMA UN INTERESSANTE VIDEO PROVANTE LE MIE PAROLE, QUI: https://www.youtube.com/watch?v=3DDLR-DJJWl_M CONNESSO A TRASMISSIONE DEL SOPORIFERO GIGI MARZULLO, CON LA PEDOFILA BERLU= SCONICCHIA #ANSELMADELLOLIO ED IL REGISTA CINEMATOGRAFICO STUPRA ED AMMAZZA= BAMBINI #GIUSEPPELAZZARI, CHE DI FATTO, SLINGUAVANO INTELLETTUALMENTE, DIF= ENDENDO E PRUOMUOVENDO LE RAGIONI DELLA, DA LORO AMATISSIMA, PEDOFILIA...OP= S CHE CASO, LA BESTIA CRIMINAME ANSELMA DELL'OLIO ED IL FIGLIO DI CANE, DA = SEMPRE PEDERASTA E SATA=E5=8D=90NAZISTA ASSASSINO #GIULIANOFERRARA, INSIEME= AL REGISTA PRIMA CITATO, QUESTO VIDEO, ORA, DA YOU TUBE, LO HAN RESO NON P= I=C3=9A PUBBLICO..OVVIO, SENTENDOSI DA NOI SGAMATI, HAN IMBOSCATO LE PROVE = DI CIO' CHE VINCENTISSIMAMENTE STIAM SCRIVENDO). IL TUTTO INSIEME AL NOTO ASSASSINO, PLURI PREGIUDICATO, FASCIO=E5=8D=90LEGH= ISTA, PEDOFILO #PAOLOBARRAI (O NOTO ASSASSINO, PLURI PREGIUDICATO, NAZI=E5= =8D=90LEGHISTA, PEDOFILO PAOLO PIETRO BARRAI #PAOLOPIETROBARRAI O NOTO ASSA= SSINO, PLURI PREGIUDICATO, NAZI=E5=8D=90LEGHISTA, PEDOFILO PIETRO PAOLO BAR= RAI #PIETROPAOLOBARRAI). NOTO TERRORISTA FASCISTA E KILLER PAOLO BARRAI, NA= TO A MILANO IL 28.6.1965, DI CRIMINALISSIMA #TERRABITCOIN #TERRABITCOINCLUB= TERRABITCOIN E CRIMINALISSIMA #TERRANFT TERRANFT. DIETRO IL MEGA RICICLAGG= IO DI 21 MLN DI =E2=82=AC, FATTO PER KILLERS DI NDRANGHETA #FRANCOLONGO, #G= IULIOMARTINO, #DOMENICOMARTINO E #VINCENZOMARTINO, IN FALLITA ICO #EIDOO EI= DOO, IN COMBUTTA COL MASSONE DELINQUENTE, MASSONE E PEDERASTA #OLIVERCAMPON= OVO https://www.tvsvizzera.it/tvs/al-servizio-dei-martino_il-banchiere-della--n= drangheta/44129050 https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit https://www.linkiesta.it/2019/04/ndrangheta-bitcoin/ BUT LETS' GO PER PUNTI, ORA. IAMM BELL, I=C3=81! INCULA TANTI BAMBINI L=E2=80=99AVVOCATO NAZIST=E5=8D=8DASSASSINO DANIELE MI= NOTTI! RICICLA PURE MOLTI SOLDI MAFIOSI (PER QUESTO =C3=89 OVVIO TUTT'UNO C= OL PEDOFILO MACELLA MAGISTRATI #SILVIOBERLUSCONI https://ifarabutti.wordpress.com/2010/02/10/berlusconi-riciclava-i-soldi-de= lla-mafia-2/ COME CON SUA FIGLIA, MANDANTE DI OMICIDI E LESBICA PERVERTITA,= PURE MOLTO PEDOFILA #MARINABERLUSCONI MARINA BERLUSCONI https://groups.goo= gle.com/g/pt.rec.desporto.futebol/c/VdkasMcS6FQ) E=E2=80=99 ANCHE AGENTE SEGRETO IN COPERTO DI TIPO ASSASSINO! DIETRO STO SCHIFO, VI =C3=89 LA REGIA DEL BANCHIERE NAZISTA, LADRO, TRUFFAT= ORE E RICICLA CASH MAFIOSO ENNIO DORIS #ENNIODORIS DI BANCA MEDIOLANUM! E S= UO FIGLIO, MASSONE SATANISTA ANCOR PI=C3=9A LAVA SOLDI MAFIOSI E KILLER #MA= SSIMODORIS MASSIMO DORIS DI BANCA MEDIOLANUM. COME VI SONO PURE I MASSONI ASSASSINI GI=C3=81 CONDANNATI A GALERA: #OSCARD= IMONTIGNY OSCAR DI MONTIGNY, #GIOVANNIPIROVANO GIOVANNI PIROVANO DI CRIMINA= LE BANCA MEDIOLANUM ED IL PEZZO DI MERDA DELINQUENTISSIMO #UBALDOLIVOLSI UB= ALDO LIVOLSI. https://www.ilfattoquotidiano.it/in-edicola/articoli/2021/06/19/e-loscar-de= lla-condanna-4-mesi-per-evasione-fiscale/6235019/ 3 ED I MASSONI, VISCIDAMENTE SPIONI, NAZI=E5=8D=8DRAZZISTI ED ASSASSINI #FRAN= CESCA OCCHIONERO E #GIULIOOCCHIONERO https://www.repubblica.it/cronaca/2018/07/17/news/cyberspionaggio_condannat= i_i_fratelli_occhionero-201982034/ GLI ULTIMI 2, GI=C3=80 FINITI IN CARCERE (PUR SE PROTETTI AI TEMPI DAL LORO= FRATELLO MASSONE, POLIZIOTTO PREZZOLATO #FRANCOGABRIELLI FRANCO GABRIELLI,= CHE QUASI UCCISE IL POLIZIOTTO EROICO #ROBERTODILEGAMI ROBERTO DI LEGAMI, = PERCH=C3=89 "REO" D'AVER FATTO FINIRE IN CARCERE I 2 SPIONI HITLERIANI E KI= LLERS FRANCESCA OCCHIONERO E GIULIO OCCHIONERO https://notizie.tiscali.it/cronaca/articoli/occhionero-massoneria-gabrielli= / ). KAP=C3=93 MAXIMO DI TUTTO QUESTO, =C3=89 OVVIAMENTE, IL MACELLA MAGISTRATI,= VERME STRAGISTA, PEDOFILO STRA ASSASSINO #SILVIOBERLUSCONI SILVIO BERLUSCO= NI (PROTETTO MEDIATICAMENTE PURE DAL MASSONE SATANISTA DI MERDA, VERME FASC= ISTA #PIEROSANSONETTI PIERO SANSONETTI E DALLA TROIONA LESBICA E PEDOFILA #= ANGELAAZZARO ANGELA AZZARO). CHE HA FATTO AMMAZZARE CENTINAIA DI PERSONE, D= AL 87 AD OGGI (FACENDO PASSARE SPESSO, IL TUTTO, PER FINTI SUICIDI, MALORI,= INCIDENTI). PRIMA VIA ARRESTATI MASSONI BASTARDAMENTE ASSASSINI #GAETANOSA= YA GAETANO SAYA E #RICCARDOSINDOCA RICCARDO SINDOCA. POI VIA MASSONI BASTAR= DAMENTE NAZISTI ED OMICIDA =E2=82=ACELISACOGNO ELISA COGNO DI CRIMINALE #FO= NDAZIONEFERRERO FONDAZIONE FERRERO E (TROIA SEMPRE SCOPATA E SBORRATA DENTR= O AL CULO): #CHIARAVALCEPINA CHIARA VALCEPINA. OLTRE CHE VIA MASSONI OMICID= A #AUGUSTOMINZOLINI AUGUSTO MINZOLINI E #MAURIZIOBARBERO MAURIZIO BARBERO D= I #TECHNOSKY TECHNOSKY. E VIA MASSONI ASSASSINI E PEDERASTA #MASSIMILIANOTO= NELLI DI IULM, ARTRIBUNE E #FEDERICOIZZI FEDERICO IZZI (NOTO COME "ER ZIO R= OMOLO DELLA CAMORRA"). COME PURE VIA ARRESTATI MASSONI TRUFFATORI E KILLER = #PAOLOCARDENA PAOLO CARDEN=C3=81 DI CRIMINALE BLOG VINCITORI E VINTI E #STE= FANOBASSI STEFANO BASSI DE IL GRANDE BLUFF #ILGRANDEBLUFF. E POI ANCORA VIA= ARRESTATI MASSONI BASTARDAMENTE ASSASSINI #FRANCESCOPAZIENZA FRANCESCO PAZ= IENZA E #FLAVIOCARBONI FLAVIO CARBONI. QUINDI VIA ARRESTATI MASSONI BASTARD= AMENTE ASSASSINI #GIULIANOTAVAROLI GIULIANO TAVAROLI ED #EMANUELECIPRIANI E= MANUELE CIPRIANI. POI VIA MASSONI BASTARDAMENTE ASSASSINI #GIACOMOZUCCO E G= IACOMO ZUCCO E #NICOLAPORRO NICOLA PORRO. POI VIA AVVOCATI MASSONI, BASTARD= AMENTE ASSASSINI #FEDERICOCECCONI FEDERICO CECCONI E #FRANCOCOPPI FRANCO CO= PPI. E VIA MASSONI NAZISTI BASTARDAMENTE ASSASSINI #FEDELECONFALONIERI FEDE= LE CONFALONIERI ED #YVESCONFALONIERI YVES CONFALONIERI. E MASSONI BASTARDAM= ENTE ANCORA PI=C3=9A HITLERIANI ED ASSASSINI #ROBERTOJONGHILAVARINI ROBERTO= JONGHI LAVARINI E #CARLOFIDANZA CARLO FIDANZA. ED AVVOCATI ANCOR PI=C3=9A = BASTARDAMENTE PEZZI DI MERDA E KILLER #STEFANOPREVITI E #CESAREPREVITI (FIG= LIO DI PUTTANA TRUFFATORE E COMPRATORE DI GIUDICI, BASTARDO SATA=E5=8D=90NA= ZISTA ED ASSASSINO CESARE PREVITI, FINITO IN CARCERE ED USCITO DAL QUALE, P= OI, SMAZZETTANDO COME AL SOLITO). ED ALTRI AVVOCATI MASSONI BASTARDAMENTE A= SSASSINI #FLAVIANOSARZANI FLAVIANO SARZANI E #PIETROMARIAMASCOLO PIETRO MAR= IA MASCOLO (SEMPRE DI CRIMINALE STUDIO LEGALE DEL PEDOFILO OMICIDA STEFANO = PREVITI)! ED ANCORA VIA ARRESTATI MASSONI BASTARDAMENTE ASSASSINI #MARCELLO= DELLUTRI MARCELLO DELL'UTRI E #GIANMARIOFERRAMONTI GIANMARIO FERRAMONTI. PO= I VIA MASSONI BASTARDAMENTE ASSASSINI #GIANLUCAMASSINIROSATI GIANLUCA MASSI= NI ROSATI E #RICCARDOBARRAI RICCARDO BARRAI (QUEST'ULTIMO, FIGLIO DEL PRIMA= CITATO PEDOFILO KILLER #PAOLOBARRAI, I 2, PADRE E FIGLIO, SON NOTI PURE PE= R FARE TANTI FILM PORNO CON CAVALLI, BEVENDO LITRI E LITRI DI SPERMA EQUINO= , GOOGLATE A PROPOSITO: 'CCC CIUCCIA CAZZI DI CAVALLO PAOLO BARRAI' https://groups.google.com/g/comp.lang.python/c/aRdLu8PIHXg ). POI VIA ARRES= TATI MASSONI BASTARDAMENTE ASSASSINI #LEOZAGAMI LEO ZAGAMI E #CHRISTYZAGAMI= CHRISTY ZAGAMI. POI VIA ARRESTATI MASSONI NDRANGHETISTI ED ASSASSINI #GIOELEMAGALDI GIOELE = MAGALDI E #CARPEORO CARPEORO (O ARRESTATO MASSONE NDRANGHETISTA ED ASSASSIN= O #GIANFRANCOPECORARO GIANFRANCO PECORARO O ARRESTATO MASSONE NDRANGHETISTA= ED ASSASSINO #GIANFRANCOCARPEORO GIANFRANCO CARPEORO). 4 QUINDI ANCORA VIA ARRESTATO MASSONE NAZISTA E KILLER #GIANFRANCOSTEFANIZZI = GIANFRANCO STEFANIZZI DI CRIMINALE STUDIO MOAI E PUTTANONA SEMPRE CON CAZZI= DI MEZZO METRO IN CULO: #CECILIAMAROGNA CECILIA MAROGNA ALIAS CECILIA CARO= GNA. E POI PURE VIA VIA ARRESTATI MASSONI BASTARDAMENTE ASSASSINI E STRA RICCHIO= NI #LUCAMORISI LUCA MORISI E #LUCAFAZZO LUCA FAZZO http://www.lastampa.it/2007/11/05/italia/cronache/milano-inchiesta-telecom-= arrestato-roberto-preatoni-Jel0EsmoQhb9EMpqfYjWuI/pagina.html QUINDI ANCORA, VIA MASSONI BASTARDAMENTE ASSASSINI #ROBERTOPREATONI ROBERTO= PREATONI E NOTO PEDERASTA INCULA BAMBINI, FASCISTA, PEDOFILISSIMO #GIANPAO= LOGAMBA DI #BANCALABERTINISYZ (PURE CRIMINALE MEGA RICICLA SOLDI MAFIOSI GI= AN PAOLO GAMBA DI BANCA ALBERTINI SYZ). OLTRE CHE VIA ARRESTATI MASSONI BAS= TARDAMENTE ASSASSINI #MATTEOSALVINI MATTEO SALVINI E #NICOLAMOLTENI NICOLA = MOLTENI. QUINDI VIA ARRESTATI MASSONI BASTARDAMENTE ASSASSINI #TOMMASOLONGO= BARDI TOMMASO LONGOBARDI E #MAURIZIOBELPIETRO MAURIZIO BELPIETRO. AND AGAIN AND AGAIN..VIA ARRESTATI MASSONI BASTARDAMENTE ASSASSINI #RENATOF= ARINA RENATO FARINA E "POMPINARO" #PIOPOMPA PIO POMPA. POI VIA ARRESTATI MA= SSONI BASTARDAMENTE ASSASSINI #NICOLOPOLLARI NICOL=C3=93 POLLARI E #MARCOMA= NCINI MARCO MANCINI (QUESTI ULTIMI, CHE, NEVER FORGET, INTENDEVANO UCCIDERE= , FRA 2001 E 2006, CHIUNQUE "OSASSE" ESSERE NON VERME BERLUSCONICCHIO COME = LORO, VIA "DISARTICOLAZIONI DI TIPO TRAUMATICO", OSSIA OMICIDI MASCHERATI D= A FINTI SUICIDI, MALORI, INCIDENTI... VEDI QUESTI 2 OTTIMI LINKS http://penlib.blogspot.pe/2009/12/spiare-e-colpire-i-dossier-e-la-regia.htm= l http://www.pmli.it/sismicolpivanemiciberlusconi.htm ). MEDIATICAMENTE, STA MERDA OMICIDA BERLUSCO=E5=8D=8DNAZISTA E PADA=E5=8D=8DN= AZISTA DI DANIELE MINOTTI (FACEBOOK), SI APPOGGIA ALLA COCAINOMANE NAZIST= =E5=8D=8DASSASSINA E LESBICA PEDOFILA, SEMPRE LECCANTE FIGHE DI BAMBINE: #M= ARIATERESAMELI MARIA TERESA MELI DI BERLUSCORROTTO GRUPPO #RCS RCS (DEL MAS= SONE PRESTANOME DI BERLUSCONI #BERLUSCONI, NAZISTA, MEGA CORRUTTORE E LADRO= #URBANOCAIRO URBANO CAIRO). COME SI APPOGGIA MEDIATICAMENTE, ALLA PUTTANA = SEMPRE SCOPATA PROFONDAMENTE NEL CULO: #ELISACALESSI DI NAZISTA LIBERO E FA= SCISTA PORTA A PORTA (GRANDE TROIA SCAMBISTA ELISA CALESSI, PRENDENTE CENTI= NAIA DI CAZZI NELL'ANO, IN TANTI CLUB PRIV=C3=89, COME IN VILLE BERLUSCONIC= CHIE, MAFIOSE, HITLERIANE ED ORGIASTICHE VARIE)! AVVOCATO PEDOFILO ED ASSASSINO DANIELE MINOTTI DI RAPALLO E GENOVA, CHE, NO= N PER NIENTE, DIFENDE SEMPRE PEDOFILI OMICIDA COME LUI (FRA ASSASSINI INCUL= A ED AMMAZZA BAMBINI CI SI CAPISCE) ECCO A VOI PROVE A TONNELLATE https://www.ilsecoloxix.it/genova/2008/08/14/news/la-badante-sgozzata-denun= cio-uno-stupro-1.33388756 http://www.ansa.it/liguria/notizie/2014/06/20/adescava-minori-sul-web-conda= nnato_36c57304-90aa-4c7f-8463-c7d610ed10dd.html https://genova.repubblica.it/cronaca/2014/02/26/news/sesso_virtuale_in_camb= io_di_soldi_per_videogame-79717213/ http://www.primocanale.it/notizie/accusato-di-adescare-minori-su-web-condan= na-4-anni-e-4-mesi-142040.html https://iltirreno.gelocal.it/massa/cronaca/2013/04/19/news/casolare-a-luci-= rosse-il-pm-7-anni-e-mezzo-all-ex-dipendente-nca-1.6917147 PER CONCLUDERE, A VOI, ORA, IL TESTO DI UN IMMIGRATO RUMENO: L'EROICO STEFA= N CUMESCU. NARCOTIZZATO E POI INCULATO A SANGUE, ALLORCH=C3=89 POCO PIU' CH= E BIMBO, DAL MASSONE NAZISTA E FILO MAFIOSO #DANIELEMINOTTI! ECCO LO SCIOCCANTE TESTO DI STEFAN CUMESCU. GUARDATE DA VOI STESSI, PLEASE,= CHE PEDOFILO ASSASSINO E SATA=E5=8D=90NAZISTA SIA, STO PEZZO DI MERDA DI D= ANIELE MINOTTI (AVVOCATO KILLER DI GENOVA E RAPALLO, STUPRANTE BAMBINI ED A= DOLESCENTI, PER POI UCCIDERE GLI STESSI E SOTTERRARLI IN BOSCHI DI MEZZA IT= ALIA, O PER SQUARTARE GLI STESSI, ALLO SCOPO DI VENDERNE GLI ORGANI O PER R= ITI SATANISTI VARI)! A VOI L'EROE STEFAN Ciao tuti e scusate de mio limitato italiano. Io sono rumeno e nun me nasco= ndo: me chiamo Stefan Cumescu e sono stato sodomizzato, a 13 anni, con viol= enza, da avvocato assassino e pedofilo Daniele Minotti di Rapallo e Genova,= esatamente nel estate 2009! 5 Tenevo 13 anni e il criminale Daniele Minotti me faceva vendere cocaina per= lui, dicendomi "sei minorenne, non ti possono far niente". Ebbene, nel 200= 9, l'avvocato di giri nazisti misti a Cosa Nostra, Camorra, Ndrangheta, Dan= iele Minotti di Rapallo e Genova, un giorno, mi fece bere qualcosa, con den= tro ovvia droga, che ti fa perdere sensi. Mi fece svenire e mentre ero mas = morto che vivo, me sodomizz=C3=B3. Vi era anche pancione pieno di merda, pe= dofilo assassino Giuliano Ferrara de Il Foglio. Li a guardare, ridere e cer= care de masturbarse invano, esendo noto impotente. Vi era pure il bancario = astrologo satanista e pedofilo #GabrieleSilvagni Gabriele Silvagni di Carim= Rimini e sua moglie, prostituta, sempre in club scambisti a prendere cazzi= nel culo, tanto quanto satanista e pedofila #RaffaellaVaccari Raffaella Va= ccari (li vedete qui https://www.chiamamicitta.it/gabriele-silvagni-dal-gra= ttacielo-al-film-del-rischiatutto/). Ho anche prove di tutto questo. Io ora= , Stefan Cumescu di Genova, faccio il muratore, basta droga, basta prostitu= irsi (como dovetti fare a seguito di questo stupro, per poter rimanere vivo= , per non venire ammazzato.. e dovetti prostituirmi proprio su ordine di Ma= fia Berlusconiana e Fascismo Berlusconiano, a Genova rapresentati da questo= bastardo incula bambini e spacciatore di cocaina di avvocato assassino Dan= iele Minotti). Guadagno un decimo di quanto guadagnavo prima e lavoro il tr= iplo di prima. Ma preferisco ci=C3=B3, sento mia vita uno poco di maggiore = pulito e securo. Ma avvocato di pedofilo stragista Silvio Berlusconi e Giul= iano Ferrara, il massone nazista, assassino e pedofilo Daniele Minotti di G= enova e Rapallo, davvero fa parte di setta di pederasta satanisti e killer.= Ciao. Stefan Cumescu. PER CONCLUDERE, VORREI RIBADIRE: RICORDATEVI DI TENERE ALLA LARGA I VOSTRI FIGLI DAL PEDOFILOMOSESSUALE ASSA= SSINO #GIUSEPPELAZZARI DI BRESCIA. https://movieplayer.net-cdn.it/images/2009/09/29/una-foto-di-giuseppe-lazza= ri-132273.jpg NOTO COME " REGISTA CINEMATOGRAFICO INCULA ED AMMAZZA BAMBINI GIUSEPPE LAZZ= ARI DI BRESCIA". PARTECIPO' ALLO STUPRO ED UCCISIONE DI YARA GAMBIRASIO (EF= FETTUATO VICINO A BRESCIA). VENNE ARRESTATO, PERCH=C3=89 INCUL=C3=93 RAGAZZ= INI SUL SET DEL SUO FILM PEDOPORNOGRAFICO SENTIRSI DIRE #SENTIRSIDIRE (FILM AMATISSIMO E SPONSORIZZATO, NON PER NIENTE, PURE, DAL PEDOFILO MASSON= E, MEGA RICICLA SOLDI MAFIOSI ED ASSASSINO PAOLO CARDEN=C3=81 #PAOLOCARDENA= DI FALERONE (FM), COME DI CRIMINALE BLOG #VINCITORIEVINTI E CRIMINALE #CAR= DENACONSULTING CARDEN=C3=81 CONSULTING DI PIANE DI FALERONE https://www.consulentifinanziari24.it/consulenti/scheda/cardena--paolo/4459= 5 http://www.cardenaconsulting.it COME DAL PEDOFILO MASSONE, ARRESTATO, ASSASSINO, STRA COCAINOMANE #PAOLOBER= LUSCONI PAOLO BERLUSCONI E DAI PEDOFILI MASSONI ASSASSINI E SATANISTI #GIAN= FRANCOSCANCARELLO GIANFRANCO SCANCARELLO E #MAURIZIOCOSTANZO MAURIZIO COSTA= NZO (NON PER NIENTE, MANDANTI E FINANZIATORI DEGLI STUPRI DI PICCOLI BIMBI,= IN QUEL DI RIGNANO https://community.gay.it/forums/topic/il-pedofilo-satanista-e-lautore-di-bu= ona-domenica-di-maur LE CRIMINALISSIME RETI #MEDIASET MEDIASET SON STRA COLME, DA SEMPRE, DI PED= OFILI, MAFIOSI, SATANISTI, NAZISTI, SATA=E5=8D=90NAZISTI, KILLERS E COCAINO= MANI https://www.fanpage.it/attualita/cocaina-a-mediaset-nelle-intercettazi= oni-spuntano-costanzo-e-barale/ )! LA BIMBA #IUSCHRAGAZI IUSCHRA GAZI, PRIMA RAPITA IN BRESCIA, POI STUPRATA E= D UCCISA PER ASPORTARNE E VENDERNE GLI ORGANI, =C3=89 STATA VIOLENTATA ED A= MMAZZATA DAL GI=C3=81 FINITO IN GALERA PER QUESTI REATI, PEDOFILO ASSASSINO= #GIUSEPPELAZZARI, REGISTA CINEMATOGRAFICO STRA PEDERASTA DI BRESCIA https://www.fanpage.it/milano/brescia-bambina-scomparsa-il-teschio-ritrovat= o-nei-boschi-appartiene-alla-piccola-iuschra/ https://www.bresciatoday.it/cronaca/brescia-persone-scomparse.html IN CONNECTION WITH https://www.un.org/en/development/desa/population/migration/generalassembly= /docs/globalcompact/A_RES_63_241.pdf From newsfish@newsfish Thu Aug 1 00:46:25 2024 X-Received: by 2002:ae9:eb4f:: with SMTP id b76mr4465152qkg.690.1644516648635; Thu, 10 Feb 2022 10:10:48 -0800 (PST) X-Received: by 2002:a5b:148:: with SMTP id c8mr8402113ybp.726.1644516648370; Thu, 10 Feb 2022 10:10:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Feb 2022 10:10:48 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:c177:9cf9:f03d:f035; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:c177:9cf9:f03d:f035 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: How to Report/Display a File Name in VHDL? From: A Injection-Date: Thu, 10 Feb 2022 18:10:48 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 6 Xref: reader02.eternal-september.org comp.lang.vhdl:9855 I'd like to open a file and then display the name of the file that I just opened. Tried the following but get a syntax Error. FILE Fnew : Text; FILE_OPEN(Fnew, "wfile", WRITE_MODE); report "FILE NAME = ", & Fnew; --Syntax Error Thanks for your help. From newsfish@newsfish Thu Aug 1 00:46:25 2024 X-Received: by 2002:a05:622a:40e:: with SMTP id n14mr716714qtx.380.1644579208111; Fri, 11 Feb 2022 03:33:28 -0800 (PST) X-Received: by 2002:a25:4f41:: with SMTP id d62mr869986ybb.156.1644579207838; Fri, 11 Feb 2022 03:33:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Feb 2022 03:33:27 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:5de5:71c9:48:4711; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:5de5:71c9:48:4711 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to Report/Display a File Name in VHDL? From: KJ Injection-Date: Fri, 11 Feb 2022 11:33:28 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 13 Xref: reader02.eternal-september.org comp.lang.vhdl:9856 On Thursday, February 10, 2022 at 1:10:50 PM UTC-5, ashokm...@gmail.com wrote: > I'd like to open a file and then display the name of the file that I just opened. Tried the following but get a syntax Error. > > FILE Fnew : Text; > FILE_OPEN(Fnew, "wfile", WRITE_MODE); > report "FILE NAME = ", & Fnew; --Syntax Error > > Thanks for your help. The file name in your example is "wfile", not &Fnew. So it should be report "FILE NAME = " & "wfile"; Alternatively, define a string constant and pass that string to the file_open procedure as well as using it in the report statement. From newsfish@newsfish Thu Aug 1 00:46:26 2024 X-Received: by 2002:a05:622a:c6:: with SMTP id p6mr1685625qtw.191.1644597856664; Fri, 11 Feb 2022 08:44:16 -0800 (PST) X-Received: by 2002:a81:ac51:: with SMTP id z17mr2624903ywj.287.1644597856377; Fri, 11 Feb 2022 08:44:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.misty.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Feb 2022 08:44:16 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:8daa:a634:7d08:5c74; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:8daa:a634:7d08:5c74 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c074fc4-74cb-40ca-9f58-a3c4814ea39cn@googlegroups.com> Subject: Re: How to Report/Display a File Name in VHDL? From: A Injection-Date: Fri, 11 Feb 2022 16:44:16 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 16 Xref: reader02.eternal-september.org comp.lang.vhdl:9857 On Friday, February 11, 2022 at 3:33:30 AM UTC-8, KJ wrote: > On Thursday, February 10, 2022 at 1:10:50 PM UTC-5, ashokm...@gmail.com wrote: > > I'd like to open a file and then display the name of the file that I just opened. Tried the following but get a syntax Error. > > > > FILE Fnew : Text; > > FILE_OPEN(Fnew, "wfile", WRITE_MODE); > > report "FILE NAME = ", & Fnew; --Syntax Error > > > > Thanks for your help. > The file name in your example is "wfile", not &Fnew. > > So it should be > report "FILE NAME = " & "wfile"; > > Alternatively, define a string constant and pass that string to the file_open procedure as well as using it in the report statement. Thanks but I still get a syntax error with your solution. Also, defined a string constant and passed that to the file_open and report statements. Still syntax Error. From newsfish@newsfish Thu Aug 1 00:46:26 2024 X-Received: by 2002:a05:620a:94e:: with SMTP id w14mr2157668qkw.485.1644627231830; Fri, 11 Feb 2022 16:53:51 -0800 (PST) X-Received: by 2002:a25:e696:: with SMTP id d144mr246836ybh.314.1644627231633; Fri, 11 Feb 2022 16:53:51 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Feb 2022 16:53:51 -0800 (PST) In-Reply-To: <1c074fc4-74cb-40ca-9f58-a3c4814ea39cn@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:5de5:71c9:48:4711; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:5de5:71c9:48:4711 References: <1c074fc4-74cb-40ca-9f58-a3c4814ea39cn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <98f2a78e-23f2-45c6-88cc-04634d552383n@googlegroups.com> Subject: Re: How to Report/Display a File Name in VHDL? From: KJ Injection-Date: Sat, 12 Feb 2022 00:53:51 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 22 Xref: reader02.eternal-september.org comp.lang.vhdl:9858 On Friday, February 11, 2022 at 11:44:18 AM UTC-5, ashokm...@gmail.com wrote: > On Friday, February 11, 2022 at 3:33:30 AM UTC-8, KJ wrote: > > On Thursday, February 10, 2022 at 1:10:50 PM UTC-5, ashokm...@gmail.com wrote: > > > I'd like to open a file and then display the name of the file that I just opened. Tried the following but get a syntax Error. > > > > > > FILE Fnew : Text; > > > FILE_OPEN(Fnew, "wfile", WRITE_MODE); > > > report "FILE NAME = ", & Fnew; --Syntax Error > > > > > > Thanks for your help. > > The file name in your example is "wfile", not &Fnew. > > > > So it should be > > report "FILE NAME = " & "wfile"; > > > > Alternatively, define a string constant and pass that string to the file_open procedure as well as using it in the report statement. > Thanks but I still get a syntax error with your solution. Also, defined a string constant and passed that to the file_open and report statements. Still syntax Error. What I posted works for me: report "FILE NAME = " & "wfile"; Since you've provided no actual code or what the actual error is, I'm not going to guess. Good luck. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:26 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed3-b.proxad.net!nnrp1-2.free.fr!not-for-mail Date: Sat, 12 Feb 2022 10:58:29 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: How to Report/Display a File Name in VHDL? Content-Language: en-US Newsgroups: comp.lang.vhdl References: <1c074fc4-74cb-40ca-9f58-a3c4814ea39cn@googlegroups.com> From: Nicolas Matringe In-Reply-To: <1c074fc4-74cb-40ca-9f58-a3c4814ea39cn@googlegroups.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 21 Message-ID: <620784c5$0$1345$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 12 Feb 2022 10:58:29 CET NNTP-Posting-Host: 82.65.67.227 X-Trace: 1644659909 news-2.free.fr 1345 82.65.67.227:19928 X-Complaints-To: abuse@proxad.net Xref: reader02.eternal-september.org comp.lang.vhdl:9859 On 2/11/22 17:44, A wrote: > On Friday, February 11, 2022 at 3:33:30 AM UTC-8, KJ wrote: >> On Thursday, February 10, 2022 at 1:10:50 PM UTC-5, ashokm...@gmail.com wrote: >>> I'd like to open a file and then display the name of the file that I just opened. Tried the following but get a syntax Error. >>> >>> FILE Fnew : Text; >>> FILE_OPEN(Fnew, "wfile", WRITE_MODE); >>> report "FILE NAME = ", & Fnew; --Syntax Error [...] >> The file name in your example is "wfile", not &Fnew. >> >> So it should be >> report "FILE NAME = " & "wfile"; [...]> Thanks but I still get a syntax error with your solution. Also, defined a string constant and passed that to the file_open and report statements. Still syntax Error. Hello The problem is probably with the comma before the concatenation operator & Nicolas From newsfish@newsfish Thu Aug 1 00:46:27 2024 X-Received: by 2002:ad4:4e2f:: with SMTP id dm15mr192488qvb.57.1644854689087; Mon, 14 Feb 2022 08:04:49 -0800 (PST) X-Received: by 2002:a25:bc81:: with SMTP id e1mr337158ybk.553.1644854685801; Mon, 14 Feb 2022 08:04:45 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Feb 2022 08:04:45 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=86.15.22.2; posting-account=tLc6qAoAAAC1P3ctUxKjfPwBmZj8QMQr NNTP-Posting-Host: 86.15.22.2 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f942dde-ecde-4037-80bb-d0c0fdc30fcen@googlegroups.com> Subject: VHDL2019 conditional compilation From: ht lab Injection-Date: Mon, 14 Feb 2022 16:04:49 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 25 Xref: reader02.eternal-september.org comp.lang.vhdl:9860 If you are a Modelsim/Questa user you might have spotted that 2022.1 has just been release and to my surprise it supports VHDL2019 conditional compilation! The documentation is a bit sketchy so here is how to use it: 1) Define a VHDL2019 `if construct: `if CONST_OVERRIDE="1" then constant my_val: integer := 10; `else constant my_val: integer := 11; `end 2) compile your code with: vcom test.vhd -vhpreprocess -definevh CONST_OVERRIDE=1 3) run vsim you will notice that depending on the -definevh value you either get 10 or 11. Also note the use of double quotes in the code and no quotes on the vcom line. You will also have a bunch of predefined constants such as VHDL_VERSION, TOOL_VENDOR etc. Now fingers crossed they will add more VHDL2019 support..... Regards, Hans From newsfish@newsfish Thu Aug 1 00:46:27 2024 X-Received: by 2002:a05:600c:384c:b0:37b:c771:499c with SMTP id s12-20020a05600c384c00b0037bc771499cmr7160190wmr.141.1645120796143; Thu, 17 Feb 2022 09:59:56 -0800 (PST) X-Received: by 2002:a25:6c8b:0:b0:620:f657:f6b1 with SMTP id h133-20020a256c8b000000b00620f657f6b1mr3623377ybc.107.1645120795639; Thu, 17 Feb 2022 09:59:55 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Feb 2022 09:59:55 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=155.190.1.7; posting-account=-3m9WQoAAADqph1cWZ4uX0b-9dwN4Ozr NNTP-Posting-Host: 155.190.1.7 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8130c315-16bd-4a69-b1b9-c383908cbee9n@googlegroups.com> Subject: Array Initialization in VHDL-2008 From: Digital Guy Injection-Date: Thu, 17 Feb 2022 17:59:56 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 9 Xref: reader02.eternal-september.org comp.lang.vhdl:9861 The following array initialization worked fine in VHDL-2002: type PACKET_REG_TYPE is array (0 to PACKET_LEN_MAX - 1) of std_logic_vector(7 downto 0); -- Packet array definition: (PACKET_LEN_MAX) deep x 8-bit wide. signal tx_byte_sr : PACKET_REG_TYPE; tx_byte_sr <= (others => (others => '0')); Now, with VHDL-2008, it gives: (vcom-1320) Type of expression "(OTHERS => '0')" is ambiguous; using element type STD_LOGIC_VECTOR, not aggregate type PACKET_REG_TYPE. I can't find any documentation on the "new" way to initialize arrays in VHDL-2008. From newsfish@newsfish Thu Aug 1 00:46:27 2024 X-Received: by 2002:a05:6214:621:b0:432:5e0d:cb64 with SMTP id a1-20020a056214062100b004325e0dcb64mr17517446qvx.65.1649445659710; Fri, 08 Apr 2022 12:20:59 -0700 (PDT) X-Received: by 2002:a25:ef0d:0:b0:63d:d3a0:ccb1 with SMTP id g13-20020a25ef0d000000b0063dd3a0ccb1mr14838684ybd.3.1649445659461; Fri, 08 Apr 2022 12:20:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!border1.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 Apr 2022 12:20:59 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=31.31.151.104; posting-account=fcumNwoAAAAEQshZBxJZeROs1CTJ7bSp NNTP-Posting-Host: 31.31.151.104 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1b2441e6-7c50-4d32-80b3-ec5bdfe1edadn@googlegroups.com> Subject: =?UTF-8?Q?PAOLO_PIETRO_BARRAI_=C3=89_UN_PEDOFILO=2C_ASSASSINO=21_SI=2C_S?= =?UTF-8?Q?I=2C_=C3=88_PROPRIO_COS=C3=8C=21_=C3=89_TRUFFATORE=2C_LADRO=2C_FALSO=2C_RICICLA_SO?= =?UTF-8?Q?LDI_DI_NDRANGHETA_E_LEGA_LADRONA=2C_NONCH=C3=89_KILLER_E_PEDERASTA?= =?UTF-8?Q?=3A_=23PAOLOBARRAI_DI_CRIMINALE_=23BIGBIT=2C_CRIMINALE_=23TERRANFT=2C_CR?= =?UTF-8?Q?IMINALE_=23TERRABITCOIN=2E=2E?= From: "ANDREAS NIGG. REVOLUTIONARY BANK SAFRA SARASIN" Injection-Date: Fri, 08 Apr 2022 19:20:59 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 390 Xref: reader02.eternal-september.org comp.lang.vhdl:9862 PAOLO PIETRO BARRAI =C3=89 UN PEDOFILO, ASSASSINO! SI, SI, =C3=88 PROPRIO C= OS=C3=8C! =C3=89 TRUFFATORE, LADRO, FALSO, RICICLA SOLDI DI NDRANGHETA E LE= GA LADRONA, NONCH=C3=89 KILLER E PEDERASTA: #PAOLOBARRAI DI CRIMINALE #BIGB= IT, CRIMINALE #TERRANFT, CRIMINALE #TERRABITCOIN.... CRIMINALE #CRYPTONOMIS= T, CRIMINALE #WMO SA PANAMA, CRIMINALE #MERCATOLIBERO, ECT! IL MALAVITOSO L= EGHISTA CHE VENIVA ARRESTATO, LUCA SOSTEGNI #LUCASOSTEGNI, SCAPPAVA A PORTO= SEGURO, DOVE IL KILLER PAOLO PIETRO BARRAI AVEVA PURE LAVATO (CASPITERINA = CHE COINCIDENZA), NEL 2011, PARTE DEI 49 MLN =E2=82=AC RUBATI DA #LEGALADRO= NA! https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg RAPISCE, INCULA ED UCCIDE TANTI BAMBINI: PAOLO BARRAI (NOTO COME "IL PEDOFI= LO DEL BITCOIN", COME PURE DI LEGA LADRONA, DI PEDOFILO ASSASSINO SILVIO BE= RLUSCONI #SILVIOBERLUSCONI E DI PEDOFILA ASSASSINA MARINA BERLUSCONI #MARIN= ABERLUSCONI)! =C3=89 SEMPRE LI A "SPENNARE" ECONOMICAMENTE I POLLI DEL WEB,= IL FALSO, LADRO, TRUFFATORE #PAOLOPIETROBARRAI! AZZERA I TUOI RISPARMI, NO= N AZZECCA MAI 1 PREVISIONI IN BORSA, CHE 1: PAOLO PIETRO BARRAI! =C3=89 UN = NAZISTA OMICIDA CHE RICICLA SOLDI STRA ASSASSINI DI NDRANGHETA, CAMORRA, MA= FIA, SACRA CORONA UNITA E LEGA LADRONA: #PAOLOPIETROBARRAI PAOLO PIETRO BAR= RAI! SALVE. SONO ANDREAS NIGG. VICE PRESIDENT DI BANCA J SAFRA SARASIN DI ZURIGO= . https://citywireselector.com/manager/andreas-nigg/d2395 https://ch.linkedin.com/in/andreasnigg https://www.blogger.com/profile/13220677517437640922 E VI VOGLIO DIRE CON TUTTE LE MIE FORZE CHE... IL LEGHISTA PEDOFILO ED ASSASSINO PAOLO BARRAI (NATO A MILANO IL 28.6.1965)= , IL LEGHISTA INCULA ED AMMAZZA BAMBINI PAOLO PIETRO BARRAI (NOTO IN TUTTO = IL MONDO COME IL PEDOFILO DEL BITCOIN), IL FIGLIO DI PUTTANA PAOLO PIETRO B= ARRAI DI CRIMINALISSIMA #TERRABITCOIN, #TERRABITCOINCLUB E DI CRIMINALISSIM= A #TERRANFT, E' DA ANNI INDAGATO DA PROCURA DI MILANO, PROCURA DI LUGANO, P= ROCURA DI ZUGO, SCOTLAND YARD LONDRA, FBI NEW YORK, POLICIA CIVIL DI PORTO = SEGURO (BR). =C3=89 DAVVERO PEDERASTA ED OMICIDA: PAOLO BARRAI DI CRIMINALE TERRA BITCOI= N (O CRIMINALE TERRABITCOIN CLUB)! IL LEGHISTA DELINQUENTE LUCA SOSTEGNI, A= RRESTATO, SCAPPAVA IN CITATA PORTO SEGURO (BR), OSSIA, GUARDA CASO, DOVE IL= KILLER NAZISTA PAOLO BARRAI HA RICICLATO PARTE DEI 49 MLN =E2=82=AC RUBATI= DA LEGA LADRONA! (ECCONE LE PROVE https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html http://portoseguroagora.blogspot.com/2011/03/porto-seguro-o-blogueiro-itali= ano-sera.html http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://www.jornalgrandebahia.com.br/2011/03/policia-civil-investiga-blogue= iro-italiano-suspeito-de-estelionato-em-porto-seguro/ https://osollo.com.br/blogueiro-italiano-sera-indiciado-por-estelionato-cal= unia-e-difamacao-pela-policia-civil-de-porto-seguro/ https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216) INDAGATO, AL MOMENTO, DALLA PROCURA DI MILANO. COME PURE DA PROCURA DI LUGA= NO, SCOTLAND YARD LONDRA, FBI NEW YORK, POLICIA CIVIL DI PORTO SEGURO (BR). HA RICICLATO BEN 21 MLN DI EURO DI MEGA ASSASSINI DI NDRANGHETA, IN CRIMINA= LISSIMA ICO #EIDOO E CRIMINALISSIMA #BITFINEX. NE SCRIVEVA MOLTO IL GIORNAL= ISTA #NICOLABORZI, POI, NAZISTAMENTE E MAFIOSAMENTE FORZATO AL SILENZIO ( E= ' RIMASTO QUESTO ARTICOLO, LEGGETELO PRIMA CHE FASCIOMAFIOSAMENTE LO FACCIA= NO SPARIRE https://paolopolitiblog.wordpress.com/2019/06/21/criptovalute-qu= ei-fondi-in-viaggio-tra-italia-irlanda-e-svizzera/ ).=20 PI=C3=99 EROICAMENTE TUTTO QUESTO https://www.linkiesta.it/2019/04/ndrangheta-bitcoin/ https://it.coinidol.com/mafie-usano-bitcoin/ https://www.swissinfo.ch/ita/al-servizio-dei-martino_il-banchiere-della--nd= rangheta/44129050 https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://coinatory.wordpress.com/tag/eidoo/ ) DICEVAMO ANYWAY... =C3=89 TRUFFATORE, PEDOFILO ED ASSASSINO: PAOLO BARRAI( O TRUFFATORE, PEDOF= ILO ED ASSASSINO PAOLO PIETRO BARRAI). DI CRIMINALE TERRA BITCOIN (ASSOCIAZ= IONE CON INTENTO DI FOTTERE, FREGARE, SPENNARE POLLI VIA INTERNET, IL TUTTO= VIA NAZIFASCISTA SITO TELEGRAM) E CRIMINALISSIMO BLOG MERCATO LIBERO, ALIA= S "MERDATO" LIBERO! INDAGATO, AL MOMENTO, DALLA PROCURA DI MILANO. COME PUR= E DA PROCURA DI LUGANO, SCOTLAND YARD LONDRA, FBI NEW YORK, POLICIA CIVIL D= I PORTO SEGURO (BR). COME ACCENNATO, HA RICICLATO 21 MLN ASSASSINI DI NDRANGHETA, IN FALLENTISSI= MA ICO EIDOO (INSIEME AL MALAVITOSO NATALE FERRARA DI REGGIO CALABRIA O MAL= AVITOSO NATALE MASSIMILANO FERRARA DI REGGIO CALABRIA, DA DECENNI PUNCIUTO,= OSSIA AFFILIATO UFFICIALMENTE ALLA NDRANGHETA, COME PIURE INSIEME AL MALAV= ITOSO TANTO QUANTO PAOLO CARDEN=C3=81 DI FREGA SOLDI BLOG VINCITORI E VINTI= , COME PURE INSIEME AL MALAVITOSO TANTO E STRA QUANTO STEFANO BASSI DI FREG= A SOLDI BLOG IL GRANDE BLUFF ED INSIEME AL MALAVITOSO FEDERICO IZZI, NOTO C= OME "ER ZIOROMOLO DELLA CAMORRA", LI VEDETE TUTTI IN FOTO QUI https://3.bp.= blogspot.com/-6WRXJQbHe08/WSBR0uTrMLI/AAAAAAAAY2g/L8c3w9GGr3wpG7yWxBBeOohzh= Wa7iJ7uQCLcB/s1600/18558610_10156258698827281_4591948382498991167_o.jpg ) CHECK EVERY DETAIL BOUT IT, HERE AVETE MIGLIAIA DI DETTAGLI, INDIZI E PROVE QUI https://www.linkiesta.it/2019/04/ndrangheta-bitcoin/ https://paolopolitiblog.wordpress.com/2019/06/21/criptovalute-quei-fondi-in= -viaggio-tra-italia-irlanda-e-svizzera/ https://it.coinidol.com/mafie-usano-bitcoin/ https://www.swissinfo.ch/ita/al-servizio-dei-martino_il-banchiere-della--nd= rangheta/44129050 https://docs.google.com/document/d/1brAgD1hHTOBXlf9iHPfxbj0nty3RRmMRxYBcA_R= TFow/edit https://coinidol.com/mafias-use-bitcoin/ https://coinatory.com/2019/04/06/italian-mafia-launders-money-through-crypt= o/ https://coinatory.wordpress.com/tag/eidoo/ https://complaintwire.org/complaint/6K334yHuHw8/mercato-libero-paolo-barrai http://www.grupy.banzaj.pl/E,PEDOFILO,ASSASSINO,PAOLO,BARRAI,DI,CRIMINALE,T= ELEGRAM,ATTRAVERSO,CUI,TRUFFA,CENTINAIA,DI,POLLI,VIA,SUA,ASSOCIAZIONE,MALAV= ITOSA,CHIAMATA,TERRABITCOIN,10,2729846,2020_08.html IL PEDERASTA OMICIDA PAOLO BARRAI =C3=89 ANCHE DI UNO DEI PRINICIPALI CRIMI= NALI UNENTI NDRANGHETA E MASSONERIA. =C3=89 DA SEMPRE UN CAPO SANTISTA (OSS= IA NDRANGHETISTA DI TIPO MASSONICO). INFATTI ERA PAPPA E CICCIA CON L'ARRESTATO MASSONE NDRANGHETISTA BERLUSCONI= CCHIO GIANCARLO PITTELLI (http://www.iacchite.blog/giancarlo-pittelli-laffa= rista-massone-dei-boss-della-ndrangheta/ ). ED ERA CICCIA E PAPPA PURE CON = GRAN PARTE DEI 334 MASSONI NDRANGHETISTI ARRESTATI DAL GRANDE PM NICOLA GRA= TTERI NEL DICEMBRE 2019 ( https://www.ilprimatonazionale.it/cronaca/ndrangh= eta-334-arresti-onorevoli-massoni-colonnello-cosche-140387/ ). MI PRESENTO. SONO IL BANCHIERE SVIZZERO, FORSE PI=C3=9A RIVOLUZIONARIO DI SEMPRE, RIVOLU= ZIONARIO A FIN DI BENE: ANDREAS NIGG , VICE PRESIDENT AND HEAD OF ASSET MAN= AGEMENT. PRESSO SAFRA-SARASIN BANK ZURICH PRIMA VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT PRESSO BANK VONTOBEL ZURI= CH. https://citywireselector.com/manager/andreas-nigg/d2395 https://ch.linkedin.com/in/andreasnigg https://www.blogger.com/profile/13220677517437640922 QUANDO ERO VICE PRESIDENTE DI VONTOBEL BANK ZURICH, COMPRAMMO LA EX FINTER = BANK ZURICH DEL MASSONE NAZISTA, KUKLUKKLANISTA ED OVVIAMENTE LEGHISTA DI M= ERDA CARLO PESENTI (NOTO PARTNER OMOSESSUALE DEL MASSONE SATANISTA E NOTORI= AMENTE PEDOFILO, ANZI PEDERASTA FEDERICO TRABUCCO DI MONTE PASCHI, EX KAIRO= S). IO IN PERSONA, ANDREAS NIGG, ORDINAI SUBITO DI CHIUDERE TUTTI I CONTI B= ANCARI CONNESSI A STA BESTIA CRIMINALISSIMA CHE DA SEMPRE E' PAOLO PIETRO B= ARRAI, NATO A MILANO IL 28.6.1965. IN QUANTO PUZZAVANO DI NDRANGHETA, COSA = NOSTRA, CAMORRA, PEDOFILO STRAGISTA SILVIO BERLUSCONI, LESBICA PEDOFILA ASS= ASSINA MARINA BERLUSCONI E 49 MILIONI DI =E2=82=AC RUBATI DA LEGA LADRONA, = LONTANO 3.000 KM (NON SONO ANTI OMOSESSUALI O LESBICHE, MA ODIO L'IPOCRISIA= E LA MAFIOSA OMERT=C3=81 CHE DA SEMPRE REGNA IN ITALIA, AMMIRO I GAYS CHE = FAN OUTING, NON QUELLI CHE SI DICONO ETERO E POI FAN SESSO CON BAMBINI O RA= GAZZINI, DI NASCOSTO)! E NON SCORDIAMO CHE IL LADRO, TRUFFATORE, SEMPRE FALSO, INCAPACISSIMO IN B= ORSA, AZZERANTE I RISPARMI DI TUTTI E SEMPRE, PAOLO BARRAI, =C3=89 PURE UN = NAZI=E5=8D=90STALKER VIA INTERNET, AIZZATORE DI SUICIDI, MANDANTE DI OMICID= I, E TORTURATORE OMICIDA (PENSATE CHE QUANDO L'AMMIREVOLE PM EUGENIO FUSCO,= NEL 2013, ARREST=C3=93 IL MANAGER CRIMINALE E FASCIOLEGHISTA GIUSEPPE ORSI= DI FINMECCANICA, IL TORTURATORE ASSASSINO PAOLO BARRAI SCRISSE SU SUO BLOG= MERCATO LIBERO "VOGLIO STRAPPARE I CAPEZZOLI DI EUGENIO FUSCO CON MIE DITA= E POI TORTURARLO A MORTE LENTAMENTE", POI SE LA FECE SOTTO E LEV=C3=93 IL = POST, LA PROCURA DI MILANO CONTROLLI PURE VIA BLOGSPOT OSSIA GOOGLE.. E VED= R=C3=81 CHE VERO CRISTALLINO, COME SEMPRE, STO SCRIVENDO)! OLTRE AD ESSERE = STATO GIA' "SOLO" 3 VOLTE IN CARCERE" ( IN UN PRIMO CASO, A SEGUITO DI ENOR= MI CRIMINALISSIME FRODI CHE EFFETTUAVA IN CITIBANK, COME DA FINALE DI QUEST= O ARTICOLO https://ricerca.repubblica.it/repubblica/archivio/repubblica/200= 1/02/19/maxi-evasione-da-400-miliardi-terenzio-sotto-torchio.html PER POI CONOSCERE ALTRA GALERA IN BRASILE E PURE PER PEDOFILIA OMOSESSUALE,= AVENDO STUPRATO BAMBINI DI 11 ANNI https://oneway2day.files.wordpress.com/2019/01/indagatoaiutalelisteciviche.= jpg http://noticiasdeportoseguro.blogspot.com/2011/03/quem-e-pietro-paolo-barra= i.html http://portoseguroagora.blogspot.com/2011/03/porto-seguro-o-blogueiro-itali= ano-sera.html http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato https://www.jornalgrandebahia.com.br/2011/03/policia-civil-investiga-blogue= iro-italiano-suspeito-de-estelionato-em-porto-seguro/ https://osollo.com.br/blogueiro-italiano-sera-indiciado-por-estelionato-cal= unia-e-difamacao-pela-policia-civil-de-porto-seguro/ https://www.redegn.com.br/?sessao=3Dnoticia&cod_noticia=3D13950 http://www.devsuperpage.com/search/Articles.aspx?hl=3Den&G=3D23&ArtID=3D301= 216 ) HA FATTO 66 (DI PROPOSITO NUMERO SATANICO) FILM PORNO CON CAVALLI E BAMBINI= , BEVENDO SPERMA EQUINO ED INCULANDO A SANGUE BAMBINI SU BAMBINI https://groups.google.com/g/comp.lang.python/c/aRdLu8PIHXg =C3=89 STATO MEGA MULTATO DA CONSOB, PER " APPENA APPENA" 70.000 EURO, PER = MEGA FRODI CHE FACEVA A PROPOSITO DEL FOTOVOLTAICO http://www.bluerating.co= m/banche-e-reti/33345/qmultaq-da-70mila-euro-per-un-ex-promotore-che-ha-vio= lato-gli-obblighi-informativi HA COME FIGLI, LA NOTA PROSTITUTA E PORNOSTAR CHE FA FILM DOVE PRENDE FALLI= DA CENTO UOMINI DI SEGUITO, COSTANZA BARRAI, NATA A MILANO, IL 1.1.1999 E = L'OMOSESSUALE DEPRAVATO E PAZZO, CHE PURE LUI FA FILM PORNO PRENDENDO FALLI= SU FALLI DA TUTTE LE PARTI, RICCARDO BARRAI NATO A MILANO IL 26.11.1996. Q= UANDO SI DICE "SANGUE MARCIO MAI MENTE" SNIFFAVA CHILI DI COCAINA E STUPRAVA RAGAZZINE E RAGAZZINI COL SERIAL RAPIS= T ALBERTO GENOVESE https://www.fanpage.it/milano/story/alberto-genovese-arrestato/ https://www.ilfattoquotidiano.it/2021/01/26/alberto-genovese-dichiarava-red= diti-da-dipendente-proseguono-gli-accertamenti-fiscali-su-imprenditore-accu= sato-di-stupro/6078470/ (ENTRAMBI SON PARTI DI CRIMINALISSIMA LOGGIA DEL DRAGO DEL PEDOFILO SPAPPOL= A MAGISTRATI SILVIO BERLUSCONI ED ENTRAMBI NASCONDONO PROPRI SOLDI CRIMINAL= I, NONCH=C3=89 LAVANO SOLDI MAFIOSI PRESSO MALAVITOSO FAMILY FUND DI ZUG? C= HIAMATO MARTIN PIUS GLOOR https://www.moneyhouse.ch/it/list/person/barrai-p= aolo-pietro ) EFFETTUA QUESTE MOSTRUOSE DELINQUENZE CON - NOTO FIDUCIARIO DI MAFIA, CAMORRA E NDRANGHETA: OLIVER CAMPONOVO https://www.swissinfo.ch/ita/al-servizio-dei-martino_il-banchiere-della--nd= rangheta/44129050 https://www.areaonline.ch/La-storia-del-fiduciario-ticinese-di-fiducia-dell= a-ndrangheta-29f7ee00 https://www.laregione.ch/cantone/mendrisiotto/1228182/affari-della-ndranghe= ta-in-ticino-alla-sbarra-l-uomo-di-fiducia-della-cosca-l-ex-municipale-di-c= hiasso-e-la-moglie-del-fratello-del-boss - PORCO BRUCIA RISPARMI, RICICLA SOLDI MAFIOSI E PEDOFILO FEDERICO IZZI DI = ROMA (NOTO COME "ER ZIO ROMOLO DELLA CAMORRA" E PURE COME "ER ZIO ROMOLO IN= CULA ED AMMAZZA BAMBINI") https://www.mail-archive.com/racket-users@googlegroups.com/msg41046.html - AL NOTO SATANISTA, LADRONE, TRUFFATORE, RICICLA CASH MAFIOSO E PEDOFILO E= CONOMISTA PAOLO CARDEN=C3=81 DI CRIMINALISSIMO BLOG VINCITORI E VINTI https://www.py.cz/pipermail/python/2017-September/013036.html -NOTO AVVOCATO SATANISTA, PEDOFILO ED ASSASSINO DANIELE MINOTTI DI GENOVA Per finire ribadisco Quando come Vontobel Bank Zurich, comprammo Finter Bank Zurich, dai massoni= leghisti e nazisti Pesenti, immediatamente chiudemmo tutti i conti conness= i, al, tanto quanto, massone leghista nazista, nonche' ladro, truffatore, a= zzera risparmi di ognuno che gli abbocca via internet e pedofilo Paolo Piet= ro Barrai ( che venne cacciato da Citibank, a fine anni 90, per terrificant= i frodi che li effettuava, come da finale di questo articolo https://ricerc= a.repubblica.it/repubblica/archivio/repubblica/2001/02/19/maxi-evasione-da-= 400-miliardi-terenzio-sotto-torchio.html il grande banchiere Giulio Di Cerb= o licenzio' in tronco il verme criminalissimo Paolo Barrai e lo fece condan= nare al carcere, pochi anni dopo, il bastardo nazista e ndranghetista kille= r Paolo Barrai fece ammazzare Giulio Di Cerbo, facendo fintamente apparire = il tutto come morte dovuta a malore... con ausilio di Massonerie Fasciste e= Servizi Segreti Fascisti a cui il pedofilo assassino Paolo Pietro Barrai = =C3=A9 connessissimo). Di delinquentissima Bsi Italia srl di Via Socrate 26= Milano, delinquentissima Medicalchain, delinquentissima Cryptolab S A, del= inquentissima Bigbit, delinquentissima Bitcoin Cryptoeconomy, delinquentiss= ima Bitincubator & Venture, delinquentissima Bgbit News Channel e delinquen= tissima Terra Bitcoin. Attraverso cui, lui ed il fallito, idiota, incapace = e fallimentare trader Federico Izzi di Roma (che campa, di fatto, ricicland= o soldi mafiosi e facendo film pedopornofrafici, tanto e' vero che sta merd= a criminale di Federico Izzi di Roma, e' noto sulle rivere del Tevere, da c= hiunque, come "Er Zio Romolo incula bambini" e pure come "Er Zio Romolo del= la Camorra") spennano " i polli del web=C2=A8, vendendo loro abbonamenti an= nuali su criptovalute e non solo, stra fallimentari! Vadan costoro a a riciclare soldi mafiosi o rubati da Lega Ladrona, dal fig= lio di troia criminale Fabrizio Cieslakiewicz di Banca dello Stato Lugano, = dal figlio di troia criminale Daniele Albisetti di Banca dello Stato Lugano= , dal figlio di troia criminale Claudio Genasci di Banca dello Stato Lugano= , dal figlio di troia criminale Patrick Lafranchi di Banca dello Stato Luga= no, dal figlio di troia criminale Gabriele Zanzi di Banca dello Stato Lugan= o! Vielen Danke, Ya!!! A fra non molto via altri miei miliardi di scritti che preparer=C3=B3! ANDREAS NIGG , VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA-SA= RASIN BANK ZURICH https://citywireselector.com/manager/andreas-nigg/d2395 HO SCRITTO E RIBADISCO IL TUTTO A PROPOSITO DI CRIMINALISSIMO #PAOLOBARRAI,= CRIMINALISSIMO CRIMINALISSIMO #PAOLOPIETROBARRAI, CRIMINALISSIMA #COSTANZA= BARRAI, CRIMINALISSIMO #RICCARDOBARRAI, CRIMINALISSIMO #VINCENZOBARRAI, CRI= MINALISSIMA #BSIITALIASRL, CRIMINALISSIMA #TERRABICOINCLUB, CRIMINALISSIMA = #TERRABITCOIN, CRIMINALISSIMA #TERRANFT, CRIMINALISSIMO #NATALEFERRARA, CRI= MINALISSIMO #NICOLABORZI, CRIMINALISSIMO #FEDERICOIZZI, CRIMINALISSIMO #STE= FANOBASSI, CRIMINALISSIMO #PAOLOCARDENA, CRIMINALISSIMA #ELISACOGNO DI CRIM= INALISSIMA #FONDAZIONEFERRERO, CRIMINALISSIMO #SILVIOBERLUSCONI, CRIMINALIS= SIMA #MARINABERLUSCONI, CRIMINALISSIMO #PIERSILVIOBERLUSCONI, CRIMINALISSIM= O #PAOLOBERLUSCONI, CRIMINALISSIMO #MATTEOSALVINI PS LAST BUT NOT LEAST. INSIEME AL PEDOFILO ASSASSINO E RICICLA SOLDI MAFIOS= I PAOLO BARRAI, AGISCE UN VERO E PROPRIO FIGLIO DI PUTTANA CRIMINALISSIMO: = GIANLUCA MASSINI ROSATI: COMMERCIALISTA BERLUSCONICCHIO E FASCIOLEGHISTA! C= I INTERESSA SOTTOLINEARE IL SUO ESSERE CRIMINALISSIMO, ANCOR PRIMA DEL SUO = ESSERE NAZISTA! STO PEDOFILO ASSASSINO DI GIANLUCA MASSINI ROSATI RICICLA C= ASH DI NDRANGHETA, MAFIA E CAMORRA! MA NON SOLO! IL PEZZO DI MERDA GIANLUCA= MASSINI ROSATI FU COINVOLTO DI BRUTTO PURE NEI PANAMA PAPERS https://corrieredellumbria.corr.it/news/attualita/218364/Panama-Papers--anc= he-un-umbro.html STO CANE SCHIFOSO, STO MASSONE SATANISTA INCULA BAMBINI DI GIANLUCA MASSINI= ROSATI (QUI IN CHIARA POSA SATANISTISSIMA https://twitter.com/PBarraIs_Kil= ler/status/1376947912480075780, LA STESSA USATA DAI GENOCIDA DONALD TRUMP E= D HITLER, NON PER NIENTE https://www.henrymakow.com/upload_images/trump-hit= ler-handsign.jpeg ), DELINQUENTISSIMAMENTE, HA MINIMIZZATO. MA ERA COINVOLT= O NEI PANAMA PAPERS PERCH=C3=89 LAVAVA E LAVA MILIONI DI $ CHE COLANO FIUMI= DI SANGUE DI MORTI AMMAZZATI DEI CARTELLI COLOMBIANI (QUINDI CONFINANTI CO= N PANAMA), QUALI I MEGA OMICIDA CLAN DEL GOLFO E LOS MACHOS. INOLTRE, COI C= RIMINALISSIMI ED ARRESTATI COMMERCIALISTI DI LEGA LADRONA, ALBERTO MANZONI = E ANDREA DI RUBBA, RICICLA TUTT'ORA, OGNI GIORNO, CASH CHE STRA COLA PURE F= IUMI DI SANGUE DI MORTI AMMAZZATI, SIA DI MAFIA RUSSA ED ALBANESE, COME DI = NDRANGHETA, CAMORRA E COSA NOSTRA https://www.repubblica.it/cronaca/2020/09/11/news/accordo_corruttivo_provat= o_da_manzoni_nessuna_giustificazione_ai_bonifici_sui_conti_suoi_e_di_di_rub= ba_-266916108/ NE SCRIVEREMO PURE SU SITI DI MARTE E VENERE, NON SOLO DI QUESTO "PIANETINO= " TERRA! #GIANLUCAMASSINIROSATI, ALBERTOMANZONI, ANDREADIRUBBA #DONALDTRUMP #ADOLPHH= ITLER! SONO IL BANCHIERE PI=C3=9A VINCENTE E RIVOLUZIONARIO DI TUTTI I TEMPI: ANDR= EAS NIGG DI BANK J SAFRA SARASIN. ZURICH A fra non molto via altri miei miliardi di scritti che preparer=C3=B3! ANDREAS NIGG , VICE PRESIDENT AND HEAD OF ASSET MANAGEMENT. PRESSO SAFRA-SA= RASIN BANK ZURICH https://citywireselector.com/manager/andreas-nigg/d2395 #PAOLOBARRAI #PAOLOPIETROBARRAI #LEGALADRONA #COSTANZABARRAI #RICCARDOBARRA= I #BARBARABORGONOVO #VINCENZOBARRAI #BSIITALIASRL #TERRABICOINCLUB #TERRABI= TCOIN #FEDERICOIZZI #STEFANOBASSI #PAOLOCARDENA #NATALEFERRARA PS LAST BUT NOT LEAST. INSIEME AL PEDOFILO ASSASSINO E RICICLA SOLDI MAFIOS= I PAOLO BARRAI, AGISCE UN VERO E PROPRIO FIGLIO DI PUTTANA CRIMINALISSIMO: = GIANLUCA MASSINI ROSATI: COMMERCIALISTA BERLUSCONICCHIO E FASCIOLEGHISTA! C= I INTERESSA SOTTOLINEARE IL SUO ESSERE CRIMINALISSIMO, ANCOR PRIMA DEL SUO = ESSERE NAZISTA! STO PEDOFILO ASSASSINO DI GIANLUCA MASSINI ROSATI RICICLA C= ASH DI NDRANGHETA, MAFIA E CAMORRA! MA NON SOLO! IL PEZZO DI MERDA GIANLUCA= MASSINI ROSATI FU COINVOLTO DI BRUTTO PURE NEI PANAMA PAPERS https://corrieredellumbria.corr.it/news/attualita/218364/Panama-Papers--anc= he-un-umbro.html STO CANE SCHIFOSO, STO MASSONE SATANISTA INCULA BAMBINI DI GIANLUCA MASSINI= ROSATI (QUI IN CHIARA POSA SATANISTO^MASSONICA https://www.monetizzando.it= /wp-content/uploads/come-pagare-meno-tasse-legalmente-escapologia.jpg, LA S= TESSA USATA DAI GENOCIDA DONALD TRUMP ED HITLER, NON PER NIENTE https://www= .henrymakow.com/upload_images/trump-hitler-handsign.jpeg ), DELINQUENTISSIM= AMENTE, HA MINIMIZZATO. MA ERA COINVOLTO NEI PANAMA PAPERS PERCH=C3=89 LAVA= VA E LAVA MILIONI DI $ CHE COLANO FIUMI DI SANGUE DI MORTI AMMAZZATI DEI CA= RTELLI COLOMBIANI (QUINDI CONFINANTI CON PANAMA), QUALI I MEGA OMICIDA CLAN= DEL GOLFO E LOS MACHOS. INOLTRE, COI CRIMINALISSIMI ED ARRESTATI COMMERCIA= LISTI DI LEGA LADRONA, ALBERTO MANZONI E ANDREA DI RUBBA, RICICLA TUTT'ORA,= OGNI GIORNO, CASH CHE STRA COLA PURE FIUMI DI SANGUE DI MORTI AMMAZZATI, S= IA DI MAFIA RUSSA ED ALBANESE, COME DI NDRANGHETA, CAMORRA E COSA NOSTRA https://www.repubblica.it/cronaca/2020/09/11/news/accordo_corruttivo_provat= o_da_manzoni_nessuna_giustificazione_ai_bonifici_sui_conti_suoi_e_di_di_rub= ba_-266916108/ NE SCRIVEREMO PURE SU SITI DI MARTE E VENERE, NON SOLO DI QUESTO "PIANETINO= " TERRA! #GIANLUCAMASSINIROSATI, ALBERTOMANZONI, ANDREADIRUBBA #DONALDTRUMP #ADOLPHH= ITLER! SONO IL BANCHIERE PI=C3=9A VINCENTE E RIVOLUZIONARIO DI TUTTI I TEMPI: ANDR= EAS NIGG DI BANK J SAFRA SARASIN. ZURICH PREMIATO NEL 2018, 2019 E 2020 COME BANCHIERE SVIZZERO DELL'ANNO A BASILEA = (TUTTI DICONO CHE VINCER=C3=93 PURE NEL 2021: VEDIAMO, INTANTO TENGO TESTA = BASSA, UMILT=C3=81 E FAME MOSTRUOSA DI VITTORIE, SEMPRE). https://citywireselector.com/manager/andreas-nigg/d2395 https://ch.linkedin.com/in/andreasnigg https://www.blogger.com/profile/13220677517437640922 From newsfish@newsfish Thu Aug 1 00:46:28 2024 X-Received: by 2002:a05:622a:588:b0:2f3:bca9:ea34 with SMTP id c8-20020a05622a058800b002f3bca9ea34mr21009793qtb.601.1652207600454; Tue, 10 May 2022 11:33:20 -0700 (PDT) X-Received: by 2002:a0d:cd06:0:b0:2f8:f39c:4cfc with SMTP id p6-20020a0dcd06000000b002f8f39c4cfcmr19533754ywd.495.1652207600172; Tue, 10 May 2022 11:33:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 10 May 2022 11:33:19 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=2401:4900:1c5c:6301:da2:5085:cddc:27d9; posting-account=ArqZqgoAAACkCGUJ0Uxb2Yvzz4duHIKU NNTP-Posting-Host: 2401:4900:1c5c:6301:da2:5085:cddc:27d9 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <383d2497-6a69-49cc-b2e3-5607a61e613dn@googlegroups.com> Subject: Components in if-else statement From: tushar sharma Injection-Date: Tue, 10 May 2022 18:33:20 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 3033 Xref: reader02.eternal-september.org comp.lang.vhdl:9863 I am trying to make a cube computation circuit using Vedic Algorithms. The code is as follows: --------------MAIN FILE------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.ALL; entity major_8_bit is port( N: in std_logic_vector(7 downto 0); Result: out std_logic_vector(23 downto 0)); end major_8_bit; architecture RTL of major_8_bit is component compare port( N: in std_logic_vector(7 downto 0); enable: out std_logic); end component; component cubeComputation8bit_YES port( N: in std_logic_vector(7 downto 0); Result: out std_logic_vector(23 downto 0)); end component; component cubeComputation8bit_NO port( N: in std_logic_vector(7 downto 0); Result: out std_logic_vector(24 downto 0)); --to concatenate the carry bit generated from 24bit BA at the 24th index (starting from 1) end component; --signals signal R: std_logic_vector( 7 downto 0); signal R2: std_logic_vector (7 downto 0):="00001111"; signal ResultNo: std_logic_vector( 24 downto 0); signal EnableSignal: std_logic; begin R <= 100000000 - N; --enable <= EnableSignal; Comp: compare port map( N, EnableSignal); YesCase: if(EnableSignal = '1') generate -- YES CASE CP1: cubeComputation8bit_YES port map (N,Result); end generate YesCase; NoCase: if(EnableSignal = '0') generate CP2: cubeComputation8bit_NO port map(N=>N,Result=> ResultNo); end generate NoCase; end; ********************* There is no syntax error being reported, but the code is not simulating because of the components used in the if-else statement (Saw this method on stackoverflow) The two components cubeComputation8bit_Yes and cubeComputation8bit_NO are working correctly independently. But not when put together this way. Any help will be highly appreciated. Regards. From newsfish@newsfish Thu Aug 1 00:46:28 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.gegeweb.eu!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp1-1.free.fr!not-for-mail Date: Mon, 16 May 2022 22:10:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: Components in if-else statement Content-Language: en-US References: <383d2497-6a69-49cc-b2e3-5607a61e613dn@googlegroups.com> From: Nicolas Matringe Newsgroups: comp.lang.vhdl In-Reply-To: <383d2497-6a69-49cc-b2e3-5607a61e613dn@googlegroups.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 14 Message-ID: <6282afbc$0$9148$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 16 May 2022 22:10:36 CEST NNTP-Posting-Host: 82.65.67.227 X-Trace: 1652731836 news-1.free.fr 9148 82.65.67.227:20265 X-Complaints-To: abuse@proxad.net Xref: reader02.eternal-september.org comp.lang.vhdl:9864 On 5/10/22 18:33, tushar sharma wrote: > I am trying to make a cube computation circuit using Vedic Algorithms. > The code is as follows: [...] > ********************* > There is no syntax error being reported, but the code is not simulating because of the components used in the if-else statement (Saw this method on stackoverflow) > The two components cubeComputation8bit_Yes and cubeComputation8bit_NO are working correctly independently. But not when put together this way. You can not use the "if <...> generate" with a signal. It doesn't make any sense. Your code doesn't make much sense either. It looks like you're using VHDL as a programming language, which it is definitely not. Nicolas From newsfish@newsfish Thu Aug 1 00:46:28 2024 X-Received: by 2002:a05:620a:2947:b0:6a3:a317:fa08 with SMTP id n7-20020a05620a294700b006a3a317fa08mr26017016qkp.746.1653935193216; Mon, 30 May 2022 11:26:33 -0700 (PDT) X-Received: by 2002:a81:49c7:0:b0:30c:3050:345a with SMTP id w190-20020a8149c7000000b0030c3050345amr9872761ywa.29.1653935193019; Mon, 30 May 2022 11:26:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 May 2022 11:26:32 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=77.101.99.84; posting-account=L5aALwoAAABayKmTMw3DmKhnz7ueXhOm NNTP-Posting-Host: 77.101.99.84 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: How entity name is resolved in architecture body From: Tomas Whitlock Injection-Date: Mon, 30 May 2022 18:26:33 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2608 Xref: reader02.eternal-september.org comp.lang.vhdl:9865 Hi all, I'm working on a tool that is supposed to read VHDL and create an abstract = representation of a design unit. I have run into a problem where I'm trying to understand how this common fo= rm of an entity declaration + architecture body is accepted by VHDL compile= rs such as Vivado Simulator / Synthesis, ModelSim / Questa and no doubt oth= ers: entity e is ... end entity; architecture a of e is ... begin ... end architecture; After repeatedly reading the VHDL LRMs of '93, 2002, 2008 etc., it seems to= me that, if the rules are interpreted literally, the entity 'e' should not= be visible to at the point where the architecture body declaration referen= ces it.=20 Yet all of the VHDL compilers that I've ever encountered will happily accep= t the above VHDL as valid. The LRM mentions a "library declarative region", in which primary design un= its of that library are visible, but it doesn't say where it applies. The L= RM doesn't seem to leave much room for the library declarative region to be= nested within some other declarative region, so I don't know what to make = of it. So my question is: Do most VHDL compilers bend the rules and add some additional rules of thei= r own (for example, adding "use work.all;" to the predefined language envir= onment), or am I missing something in the LRM that makes the entities of th= e work library visible to an architecture body declaration (when being comp= iled into the same work library)? Thanks in advance for any insights. From newsfish@newsfish Thu Aug 1 00:46:29 2024 X-Received: by 2002:a05:6214:1949:b0:462:4a9d:3280 with SMTP id q9-20020a056214194900b004624a9d3280mr30343357qvk.130.1653948103558; Mon, 30 May 2022 15:01:43 -0700 (PDT) X-Received: by 2002:a81:38c:0:b0:2f4:d0e2:dc2a with SMTP id 134-20020a81038c000000b002f4d0e2dc2amr59961150ywd.102.1653948103306; Mon, 30 May 2022 15:01:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!2.eu.feeder.erje.net!feeder.erje.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 May 2022 15:01:43 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2600:8800:7d00:c600:a86b:9806:3bec:157b; posting-account=9dfnKAkAAAASO1bBMwoz4pZw_aDCPDw1 NNTP-Posting-Host: 2600:8800:7d00:c600:a86b:9806:3bec:157b References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> Subject: Re: How entity name is resolved in architecture body From: Vraj Patel Injection-Date: Mon, 30 May 2022 22:01:43 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9866 Wouldn't that code be valid under the specification when you look at defaul= t binding indication? For the VHDL 2000 standard which I just looked thru that would be Section 5= .2.2. The VHDL reference guide webpages (https://www.ics.uci.edu/~jmoorkan/vhdlre= f/confspec.html - I believe this site is for the 93 standard) sums it up ni= cely as follows:=20 "In the absence of an explicit configuration for any part of a model, defau= lt binding will occur. For each unbound instance of every component, an ent= ity will be selected whose name, port names and port types etc. match those= in the corresponding component declaration. Where an entity has more than = one architecture, the last analysed architecture will be used."=20 This answer is not to imply that the current tools don't bend rules when it= comes to following the written standard. I cannot answer with confidence i= f they do or don't. From newsfish@newsfish Thu Aug 1 00:46:29 2024 X-Received: by 2002:a05:6214:3003:b0:462:1c15:772c with SMTP id ke3-20020a056214300300b004621c15772cmr40147562qvb.71.1653951619909; Mon, 30 May 2022 16:00:19 -0700 (PDT) X-Received: by 2002:a5b:312:0:b0:633:75de:5ab4 with SMTP id j18-20020a5b0312000000b0063375de5ab4mr59407478ybp.124.1653951619636; Mon, 30 May 2022 16:00:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 May 2022 16:00:19 -0700 (PDT) In-Reply-To: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=77.101.99.84; posting-account=L5aALwoAAABayKmTMw3DmKhnz7ueXhOm NNTP-Posting-Host: 77.101.99.84 References: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> Subject: Re: How entity name is resolved in architecture body From: Tomas Whitlock Injection-Date: Mon, 30 May 2022 23:00:19 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3357 Xref: reader02.eternal-september.org comp.lang.vhdl:9867 On Monday, 30 May 2022 at 23:01:56 UTC+1, patel...@gmail.com wrote: > Wouldn't that code be valid under the specification when you look at defa= ult binding indication?=20 >=20 > For the VHDL 2000 standard which I just looked thru that would be Section= 5.2.2.=20 >=20 > The VHDL reference guide webpages (https://www.ics.uci.edu/~jmoorkan/vhdl= ref/confspec.html - I believe this site is for the 93 standard) sums it up = nicely as follows:=20 > "In the absence of an explicit configuration for any part of a model, def= ault binding will occur. For each unbound instance of every component, an e= ntity will be selected whose name, port names and port types etc. match tho= se in the corresponding component declaration. Where an entity has more tha= n one architecture, the last analysed architecture will be used."=20 >=20 > This answer is not to imply that the current tools don't bend rules when = it comes to following the written standard. I cannot answer with confidence= if they do or don't. Hi Patel, I appreciate you taking the time to reply, but I don't think that section o= f the standard is relevant to this question, and maybe I haven't stated by = question clearly enough. I'm not trying to understand out how VHDL chooses an architecture for an in= stantation, but rather: how is entity 'e' even visible when the compiler en= counters 'architecture a of e'. There are no use clauses in the example I'v= e used and according to the LRM, the only predefined context is "library st= d, work; use std.standard.all;". So the Root Declarative Region shouldn't contain 'e', and therefore accordi= ng to the visibilty, scope etc. rules, 'e' shouldn't even be visible and th= e compiler should error and say so (by my interpretation of the LRM, at lea= st). It occurs to me that maybe for an architecture declaration, all existing VH= DL compilers have a special case *for architecture bodies only* in which th= e entity's name is looked up in the Library Declarative Region as opposed t= o the Root Declarative Region, and hence 'e' is visible. From newsfish@newsfish Thu Aug 1 00:46:29 2024 X-Received: by 2002:a05:6214:d0e:b0:462:6d8a:fab4 with SMTP id 14-20020a0562140d0e00b004626d8afab4mr20128167qvh.85.1653960188054; Mon, 30 May 2022 18:23:08 -0700 (PDT) X-Received: by 2002:a25:f510:0:b0:65b:b324:23f with SMTP id a16-20020a25f510000000b0065bb324023fmr16516392ybe.220.1653960187824; Mon, 30 May 2022 18:23:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 May 2022 18:23:07 -0700 (PDT) In-Reply-To: <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2600:8800:7d00:c600:a86b:9806:3bec:157b; posting-account=9dfnKAkAAAASO1bBMwoz4pZw_aDCPDw1 NNTP-Posting-Host: 2600:8800:7d00:c600:a86b:9806:3bec:157b References: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3f0279e7-5f80-4db7-8a8e-39a1c04ec49en@googlegroups.com> Subject: Re: How entity name is resolved in architecture body From: Vraj Patel Injection-Date: Tue, 31 May 2022 01:23:08 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1916 Xref: reader02.eternal-september.org comp.lang.vhdl:9868 Hi, I have a better grasp of the question you are asking however, do you mind explaining how you get to this assertion you state as true using quotes of the standard to support the assertion: "So the Root Declarative Region shouldn't contain 'e', and therefore according to the visibilty, scope etc. rules, 'e' shouldn't even be visible and the compiler should error and say so (by my interpretation of the LRM, at least)." It would make the question more clear to me and perhaps to others. Specifically, I am interested as to how you think there would be no visibility of ''e" to the compiler. From newsfish@newsfish Thu Aug 1 00:46:30 2024 X-Received: by 2002:a05:622a:ca:b0:2f9:3f2c:c463 with SMTP id p10-20020a05622a00ca00b002f93f2cc463mr30726447qtw.386.1653986548379; Tue, 31 May 2022 01:42:28 -0700 (PDT) X-Received: by 2002:a05:6902:1106:b0:64f:4e18:2c23 with SMTP id o6-20020a056902110600b0064f4e182c23mr59140219ybu.168.1653986548243; Tue, 31 May 2022 01:42:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.mixmin.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 May 2022 01:42:27 -0700 (PDT) In-Reply-To: <3f0279e7-5f80-4db7-8a8e-39a1c04ec49en@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=77.101.99.84; posting-account=L5aALwoAAABayKmTMw3DmKhnz7ueXhOm NNTP-Posting-Host: 77.101.99.84 References: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> <3f0279e7-5f80-4db7-8a8e-39a1c04ec49en@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How entity name is resolved in architecture body From: Tomas Whitlock Injection-Date: Tue, 31 May 2022 08:42:28 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9869 On Tuesday, 31 May 2022 at 02:23:09 UTC+1, patel...@gmail.com wrote: > Hi,=20 >=20 > I have a better grasp of the question you are asking however, do you mind= explaining how you get to this assertion you state as true using quotes of= the standard to support the assertion: > "So the Root Declarative Region shouldn't contain 'e', and therefore acco= rding to the visibilty, scope etc. rules, 'e' shouldn't even be visible and= the compiler should error and say so (by my interpretation of the LRM, at = least)." > It would make the question more clear to me and perhaps to others. Specif= ically, I am interested as to how you think there would be no visibility of= ''e" to the compiler. Hi Patel, Ok, here goes with my interpretation of the rules that matter for this case= (from VHDL-2002 LRM): 10.1 "In addition to the above declarative regions, there is a root declara= tive region, not associated with a portion of the text of the description, but encompassing any given primary unit. At= the beginning of the analysis of a given primary unit, there are no declarations whose scopes (see 10.2) are w= ithin the root declarative region." So this is saying that when starting to parse a VHDL file, the root declara= tive region has no declarations. Seems pretty obvious. But this is supposed= to apply to primary units - but how does the compiler know if it's looking= at a primary or secondary unit until it has successfully parsed part of it= ? Surely this applies to all design units, primary & secondary. It says in 11.2: "Every design unit except package STANDARD is assumed to contain the follow= ing implicit context items as part of its context clause: library STD, WORK ; use STD.STANDARD.all ;" So this is how the predefined stuff gets into the root declarative region a= nd is visible. Before the compiler gets to parsing any VHDL code, even cont= ext clauses, the root declarative region has only the following visible in = it: std (library), work (library) and everything in std.standard.* . Notabl= y, this does not include any entities of the work library such as entity 'e= ' from my example. I believe that if a VHDL file has multiple design units, whether primary or= secondary, parsing of each design unit begins with a fresh new root declar= ative region with nothing in it except the predefined stuff. So after 'end = entity;' of my example, the compiler begins a fresh new root declarative re= gion (not containing 'e'). I haven't found any special case treatment of the entity_name of an archite= cture body in the LRM, so I conclude that in a literal interpretation of th= e rules, you should actually need architecture a of work.e is -- OK: 'e' visible by selection ... begin ... end architecture;=20 OR use work.e;=20 architecture a of e -- OK: 'e' made visible by use clause ... begin ... end architecture; I guess that in most VHDL compilers, there is a special case where the enti= ty_name lookup for an architecture body is not done within the root declara= tive region but instead goes to the library declarative region (which certa= inly does have 'e' visible). The library declarative region is mentioned in= a couple of places in the LRM and nowhere else, so it's not exactly obviou= s what its purpose is or why the LRM even mentions it. From newsfish@newsfish Thu Aug 1 00:46:30 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail From: Charles Bailey Newsgroups: comp.lang.vhdl Subject: Re: How entity name is resolved in architecture body Date: Tue, 31 May 2022 15:24:38 -0500 Organization: A noiseless patient Spider Lines: 56 Message-ID: References: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> <3f0279e7-5f80-4db7-8a8e-39a1c04ec49en@googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 31 May 2022 20:24:39 -0000 (UTC) Injection-Info: reader02.eternal-september.org; posting-host="bb3e477f31d1e181cd4dfe6aed7e6229"; logging-data="9199"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/w/0cIBjvVX6F+Lmh754n/e8RiLS2F9p0=" User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 Cancel-Lock: sha1:75hHr2bjt2YykXfg4/0rvlq9mvM= In-Reply-To: Xref: reader02.eternal-september.org comp.lang.vhdl:9870 On 2022-05-31 03:42, Tomas Whitlock wrote: > On Tuesday, 31 May 2022 at 02:23:09 UTC+1, patel...@gmail.com wrote: >> Hi, >> >> I have a better grasp of the question you are asking however, do you mind explaining how you get to this assertion you state as true using quotes of the standard to support the assertion: >> "So the Root Declarative Region shouldn't contain 'e', and therefore according to the visibilty, scope etc. rules, 'e' shouldn't even be visible and the compiler should error and say so (by my interpretation of the LRM, at least)." >> It would make the question more clear to me and perhaps to others. Specifically, I am interested as to how you think there would be no visibility of ''e" to the compiler. > > Hi Patel, > > Ok, here goes with my interpretation of the rules that matter for this case (from VHDL-2002 LRM): > > 10.1 "In addition to the above declarative regions, there is a root declarative region, not associated with a portion > of the text of the description, but encompassing any given primary unit. At the beginning of the analysis of a > given primary unit, there are no declarations whose scopes (see 10.2) are within the root declarative region." > > So this is saying that when starting to parse a VHDL file, the root declarative region has no declarations. Seems pretty obvious. But this is supposed to apply to primary units - but how does the compiler know if it's looking at a primary or secondary unit until it has successfully parsed part of it? Surely this applies to all design units, primary & secondary. > > It says in 11.2: > > "Every design unit except package STANDARD is assumed to contain the following implicit context items as > part of its context clause: > > library STD, WORK ; use STD.STANDARD.all ;" > > So this is how the predefined stuff gets into the root declarative region and is visible. Before the compiler gets to parsing any VHDL code, even context clauses, the root declarative region has only the following visible in it: std (library), work (library) and everything in std.standard.* . Notably, this does not include any entities of the work library such as entity 'e' from my example. > > I believe that if a VHDL file has multiple design units, whether primary or secondary, parsing of each design unit begins with a fresh new root declarative region with nothing in it except the predefined stuff. So after 'end entity;' of my example, the compiler begins a fresh new root declarative region (not containing 'e'). > > I haven't found any special case treatment of the entity_name of an architecture body in the LRM, so I conclude that in a literal interpretation of the rules, you should actually need > > architecture a of work.e is -- OK: 'e' visible by selection > ... > begin > ... > end architecture; > > OR > > use work.e; > > architecture a of e -- OK: 'e' made visible by use clause > ... > begin > ... > end architecture; > > I guess that in most VHDL compilers, there is a special case where the entity_name lookup for an architecture body is not done within the root declarative region but instead goes to the library declarative region (which certainly does have 'e' visible). The library declarative region is mentioned in a couple of places in the LRM and nowhere else, so it's not exactly obvious what its purpose is or why the LRM even mentions it. > The WORK library is always visible without it needing to be declared. Entity 'e' was compiled into library WORK so it is visible when the architecture is compiled. I've never seen the USE statement used for anything other than pulling in packages. 'e' is an entity, not a package. I don't think the tools are bending the rules in this case. Charles Bailey From newsfish@newsfish Thu Aug 1 00:46:30 2024 X-Received: by 2002:ac8:6ed0:0:b0:2f9:4564:97b5 with SMTP id f16-20020ac86ed0000000b002f9456497b5mr31880495qtv.669.1654074508160; Wed, 01 Jun 2022 02:08:28 -0700 (PDT) X-Received: by 2002:a81:5543:0:b0:30c:1e9f:c027 with SMTP id j64-20020a815543000000b0030c1e9fc027mr22131864ywb.355.1654074508018; Wed, 01 Jun 2022 02:08:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jun 2022 02:08:27 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=77.101.99.84; posting-account=L5aALwoAAABayKmTMw3DmKhnz7ueXhOm NNTP-Posting-Host: 77.101.99.84 References: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> <3f0279e7-5f80-4db7-8a8e-39a1c04ec49en@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3b65a45a-8134-4f32-ab3a-c31db9076b43n@googlegroups.com> Subject: Re: How entity name is resolved in architecture body From: Tomas Whitlock Injection-Date: Wed, 01 Jun 2022 09:08:28 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.vhdl:9871 On Tuesday, 31 May 2022 at 21:24:43 UTC+1, Charles Bailey wrote: > On 2022-05-31 03:42, Tomas Whitlock wrote:=20 > > On Tuesday, 31 May 2022 at 02:23:09 UTC+1, patel...@gmail.com wrote:=20 *snip* for brevity > > I guess that in most VHDL compilers, there is a special case where the = entity_name lookup for an architecture body is not done within the root dec= larative region but instead goes to the library declarative region (which c= ertainly does have 'e' visible). The library declarative region is mentione= d in a couple of places in the LRM and nowhere else, so it's not exactly ob= vious what its purpose is or why the LRM even mentions it.=20 > > > The WORK library is always visible without it needing to be declared.=20 > Entity 'e' was compiled into library WORK so it is visible when the=20 > architecture is compiled. I've never seen the USE statement used for=20 > anything other than pulling in packages. 'e' is an entity, not a=20 > package. I don't think the tools are bending the rules in this case.=20 >=20 > Charles Bailey Hi Charles, Respectfully, I don't agree. 'e' is only visible if the LRM's scope and vis= ibility rules say it is. By my reading of the LRM, what is visible at the b= eginning of compilation of a design unit consists of only: work, std & std.= standard.all. That excludes 'e'. The VHDL grammar says this: architecture_body ::=3D architecture identifier of entity_name is architecture_declarative_part begin architecture_statement_part end [ architecture ] [ architecture_simple_name ] ; The fact that the entity for the architecture is identified by 'entity_name= ' (as opposed to a 'simple_name') means that it must be subject to the scop= e & visibility rules like any other kind of name. I don't see anything in t= he LRM to indicate that there is a special case for this entity_name, thoug= h I might have missed something. ModelSim accepts 'work.e' as well as 'e', = indicating that it does indeed treat entity_name as a 'name', and allows se= lected names etc. In the absense of a use clause that makes 'e' visible, why would it be visi= ble just prior to the architecture body declaration that I used as an examp= le? Can you explain why you think 'e' is visible according to the scope and vis= ibility rules? Or do you know of a rule in the LRM that means the usual sco= pe and visibility rules don't apply in this case, and instead the compiler = just looks in the work library? I'm not trying to be argumentative, merely trying to confirm that my unders= tanding of the way the entity name is resolved is correct. I would agree as= a practical matter that the way all known VHDL compilers work in treating = 'e' as being visible is for the best. From newsfish@newsfish Thu Aug 1 00:46:31 2024 X-Received: by 2002:ac8:4e52:0:b0:304:86c8:7b26 with SMTP id e18-20020ac84e52000000b0030486c87b26mr10927546qtw.684.1654075370753; Wed, 01 Jun 2022 02:22:50 -0700 (PDT) X-Received: by 2002:a81:38c:0:b0:2f4:d0e2:dc2a with SMTP id 134-20020a81038c000000b002f4d0e2dc2amr68299200ywd.102.1654075370604; Wed, 01 Jun 2022 02:22:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.uzoreto.com!news-out.netnews.com!news.alt.net!fdc2.netnews.com!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.ams4!peer.am4.highwinds-media.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jun 2022 02:22:50 -0700 (PDT) In-Reply-To: <3b65a45a-8134-4f32-ab3a-c31db9076b43n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=77.101.99.84; posting-account=L5aALwoAAABayKmTMw3DmKhnz7ueXhOm NNTP-Posting-Host: 77.101.99.84 References: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> <3f0279e7-5f80-4db7-8a8e-39a1c04ec49en@googlegroups.com> <3b65a45a-8134-4f32-ab3a-c31db9076b43n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <92df06ec-2195-4cc9-9090-d0e7a97d7e5an@googlegroups.com> Subject: Re: How entity name is resolved in architecture body From: Tomas Whitlock Injection-Date: Wed, 01 Jun 2022 09:22:50 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 2277 Xref: reader02.eternal-september.org comp.lang.vhdl:9872 Also, the following VHDL gives an error in ModelSim: entity e is end entity; package p is alias e_alias is e; end package; ** Error: entity_visibility.vhd(4): (vcom-1136) Unknown identifier "e". On the other hand, ModelSim accepts either of the following without error: entity e is end entity; package p is alias e_alias is work.e; end package; OR entity e is end entity; use work.e; package p is alias e_alias is e; end package; Which shows that according to the usual visibility and scope rules, 'e' is not visible except by selection or by a use clause. So architecture bodies appear to have special case handling for 'entity_name'. From newsfish@newsfish Thu Aug 1 00:46:31 2024 X-Received: by 2002:a05:620a:956:b0:6a3:735f:f7ad with SMTP id w22-20020a05620a095600b006a3735ff7admr898895qkw.717.1654113295995; Wed, 01 Jun 2022 12:54:55 -0700 (PDT) X-Received: by 2002:a25:658b:0:b0:65d:4d94:17b0 with SMTP id z133-20020a25658b000000b0065d4d9417b0mr1579042ybb.514.1654113295810; Wed, 01 Jun 2022 12:54:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder1.feed.usenet.farm!feed.usenet.farm!news-out.netnews.com!news.alt.net!fdc2.netnews.com!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jun 2022 12:54:55 -0700 (PDT) In-Reply-To: <92df06ec-2195-4cc9-9090-d0e7a97d7e5an@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=77.101.99.84; posting-account=L5aALwoAAABayKmTMw3DmKhnz7ueXhOm NNTP-Posting-Host: 77.101.99.84 References: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> <3f0279e7-5f80-4db7-8a8e-39a1c04ec49en@googlegroups.com> <3b65a45a-8134-4f32-ab3a-c31db9076b43n@googlegroups.com> <92df06ec-2195-4cc9-9090-d0e7a97d7e5an@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9680ddce-75d2-4847-8e0f-dc384c1c48bfn@googlegroups.com> Subject: Re: How entity name is resolved in architecture body From: Tomas Whitlock Injection-Date: Wed, 01 Jun 2022 19:54:55 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 2311 Xref: reader02.eternal-september.org comp.lang.vhdl:9873 Update: I've now taken a look (I think) at what GHDL does for the 'entity_name' of 'architecture_body'. If understand the code correctly, it does this: If the 'entity_name' string is syntactically equivalent to an 'identifier' (i.e. not a selected name or anything like that), then attempt to look it up in the 'work' library. The usual scope and visibility rules are not applied in this case. Otherwise, attempt to look up the 'entity_name' string in the usual way, i.e. look it up in the current declarative region, which for an architecture_body must be a root declarative region. The usual scope and visibility rules are applied in this case. This seems like a reasonable way to go. From newsfish@newsfish Thu Aug 1 00:46:31 2024 X-Received: by 2002:a37:e205:0:b0:6a3:39d1:6292 with SMTP id g5-20020a37e205000000b006a339d16292mr1082517qki.525.1654118119914; Wed, 01 Jun 2022 14:15:19 -0700 (PDT) X-Received: by 2002:a25:50c7:0:b0:65c:bbff:ec10 with SMTP id e190-20020a2550c7000000b0065cbbffec10mr1975600ybb.161.1654118119631; Wed, 01 Jun 2022 14:15:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jun 2022 14:15:19 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:c0ce:7cbc:482b:3d67; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:c0ce:7cbc:482b:3d67 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: `transaction `event From: A Injection-Date: Wed, 01 Jun 2022 21:15:19 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1522 Xref: reader02.eternal-september.org comp.lang.vhdl:9874 I understand that `event is when the signal *transitions* to/from a value. = `transaction is when a signal is assigned a value, even if the value is the= same as the previous value. My question is what is `transaction`event ? Does it mean that -both- a tran= saction and an event has taken place on a signal or does it mean that eithe= r a transaction OR an event has taken place on the given signal. Is it an A= ND of transaction and event or is it an OR? From newsfish@newsfish Thu Aug 1 00:46:31 2024 X-Received: by 2002:a05:620a:22c1:b0:6a3:9974:fd12 with SMTP id o1-20020a05620a22c100b006a39974fd12mr4304277qki.93.1654198553795; Thu, 02 Jun 2022 12:35:53 -0700 (PDT) X-Received: by 2002:a81:745:0:b0:30f:b172:9efb with SMTP id 66-20020a810745000000b0030fb1729efbmr7579658ywh.495.1654198553653; Thu, 02 Jun 2022 12:35:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 2 Jun 2022 12:35:53 -0700 (PDT) In-Reply-To: <9680ddce-75d2-4847-8e0f-dc384c1c48bfn@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=194.73.105.74; posting-account=L5aALwoAAABayKmTMw3DmKhnz7ueXhOm NNTP-Posting-Host: 194.73.105.74 References: <1eac2e9b-92f0-4b04-b17b-631dd953fbaan@googlegroups.com> <99099603-7028-4b9d-b8ad-f15ff46774e5n@googlegroups.com> <3f0279e7-5f80-4db7-8a8e-39a1c04ec49en@googlegroups.com> <3b65a45a-8134-4f32-ab3a-c31db9076b43n@googlegroups.com> <92df06ec-2195-4cc9-9090-d0e7a97d7e5an@googlegroups.com> <9680ddce-75d2-4847-8e0f-dc384c1c48bfn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <55c0c4fd-805c-4088-8bbd-c61fd76b52c3n@googlegroups.com> Subject: Re: How entity name is resolved in architecture body From: Tomas Whitlock Injection-Date: Thu, 02 Jun 2022 19:35:53 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2088 Xref: reader02.eternal-september.org comp.lang.vhdl:9875 @Charles Bailey - Having thought about this some more, I think you are corr= ect to say that implementations are not bending the rules. They are impleme= nting 'entity_name' resolution as per the rules, but the rules for that par= ticular case are weird and the LRM doesn't explain the subtleties well. I also think there's pretty much no way to implement this in a VHDL compile= r without treating it as a special case, like the solution used in GHDL. From newsfish@newsfish Thu Aug 1 00:46:32 2024 X-Received: by 2002:a05:600c:1d12:b0:39c:4307:8b10 with SMTP id l18-20020a05600c1d1200b0039c43078b10mr41072452wms.103.1655823161067; Tue, 21 Jun 2022 07:52:41 -0700 (PDT) X-Received: by 2002:a25:da44:0:b0:668:c9d7:d921 with SMTP id n65-20020a25da44000000b00668c9d7d921mr22372460ybf.514.1655823160573; Tue, 21 Jun 2022 07:52:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.uzoreto.com!feeder1.cambriumusenet.nl!feed.tweak.nl!209.85.128.87.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jun 2022 07:52:40 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=129.252.22.24; posting-account=xwVASgoAAACztTGqDXJh_wgNfAJSyqWd NNTP-Posting-Host: 129.252.22.24 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <68597ac5-1809-46a7-b61e-c1850cf45902n@googlegroups.com> Subject: Getting Rank of Elements in an Array using VHDL From: Md Multan Biswas Injection-Date: Tue, 21 Jun 2022 14:52:41 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.vhdl:9876 Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The position of the elements in the voltage array is ranged from 0 to 3. Using a bubble sorting algorithm, I obtained the position index of the elements in the array as follows: Index (0)= 2 ; Index (1)= 0 ; Index (2)= 3 ; Index (3)= 1 ; However, basically I just the rank of the elements in the voltage array. I expect to get: Rank (0) = 1 ; Rank (1) = 3 ; Rank (2) = 0 ; Rank (3) = 2 ; I would appreciate any of your help and suggestion to get the desired outcome using the VHDL code. Thanks, a bunch in advance :) From newsfish@newsfish Thu Aug 1 00:46:32 2024 X-Received: by 2002:a05:6214:1c8c:b0:473:408f:ddd6 with SMTP id ib12-20020a0562141c8c00b00473408fddd6mr31539875qvb.74.1658344693804; Wed, 20 Jul 2022 12:18:13 -0700 (PDT) X-Received: by 2002:a25:31c1:0:b0:670:97ab:3262 with SMTP id x184-20020a2531c1000000b0067097ab3262mr4034029ybx.232.1658344693450; Wed, 20 Jul 2022 12:18:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!news.uzoreto.com!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Jul 2022 12:18:13 -0700 (PDT) In-Reply-To: <68597ac5-1809-46a7-b61e-c1850cf45902n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=65.207.89.54; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 65.207.89.54 References: <68597ac5-1809-46a7-b61e-c1850cf45902n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <03296913-aa89-40b7-870b-ef58d75da8b0n@googlegroups.com> Subject: Re: Getting Rank of Elements in an Array using VHDL From: "gnuarm.del...@gmail.com" Injection-Date: Wed, 20 Jul 2022 19:18:13 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2449 Xref: reader01.eternal-september.org comp.lang.vhdl:9877 On Tuesday, June 21, 2022 at 10:52:44 AM UTC-4, Md Multan Biswas wrote: > Dear VHDL Coders,=20 >=20 > I am trying to get the rank of elements from an array of data. For exampl= e, I have an array, Voltage =3D [20 40 10 30] ;=20 >=20 > The position of the elements in the voltage array is ranged from 0 to 3.= =20 >=20 > Using a bubble sorting algorithm, I obtained the position index of the el= ements in the array as follows:=20 > Index (0)=3D 2 ; Index (1)=3D 0 ; Index (2)=3D 3 ; Index (3)=3D 1 ;=20 >=20 > However, basically I just the rank of the elements in the voltage array. = I expect to get:=20 > Rank (0) =3D 1 ; Rank (1) =3D 3 ; Rank (2) =3D 0 ; Rank (3) =3D 2 ;=20 >=20 > I would appreciate any of your help and suggestion to get the desired out= come using the VHDL code. Thanks, a bunch in advance :) I'm curious, how did you end up solving this? I would think sorting would = be a very hardware intensive task unless you created a state machine to pro= cess the data like a CPU would. I think a bubble sort could be implemented= with very few resources if you have the time.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:32 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Getting Rank of Elements in an Array using VHDL Date: Fri, 22 Jul 2022 14:40:29 +0300 Organization: An impatient and LOUD arachnid Lines: 38 Message-ID: References: <68597ac5-1809-46a7-b61e-c1850cf45902n@googlegroups.com> <03296913-aa89-40b7-870b-ef58d75da8b0n@googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain Injection-Info: reader01.eternal-september.org; posting-host="beaf2d0a5e2cdb5132c6ea629096139c"; logging-data="3261074"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+eHb06ImglguzgJkDt08F3" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) Cancel-Lock: sha1:em8fd6UIzHV1f7mEBeRFdgUXEfo= sha1:rS3HGHU48GKZ4bKtHbYlA7cPdDw= Xref: reader01.eternal-september.org comp.lang.vhdl:9878 "gnuarm.del...@gmail.com" writes: > On Tuesday, June 21, 2022 at 10:52:44 AM UTC-4, Md Multan Biswas wrote: >> Dear VHDL Coders, >> >> I am trying to get the rank of elements from an array of data. For >> example, I have an array, Voltage = [20 40 10 30] ; >> >> The position of the elements in the voltage array is ranged from 0 to 3. >> >> Using a bubble sorting algorithm, I obtained the position index of the elements in the array as follows: >> Index (0)= 2 ; Index (1)= 0 ; Index (2)= 3 ; Index (3)= 1 ; >> >> However, basically I just the rank of the elements in the voltage array. I expect to get: >> Rank (0) = 1 ; Rank (1) = 3 ; Rank (2) = 0 ; Rank (3) = 2 ; >> >> I would appreciate any of your help and suggestion to get the >> desired outcome using the VHDL code. Thanks, a bunch in advance :) > > I'm curious, how did you end up solving this? I would think sorting > would be a very hardware intensive task unless you created a state > machine to process the data like a CPU would. I think a bubble sort > could be implemented with very few resources if you have the time. I'm not sure what his problem was since the question was more than a little vague to me. Using his notation without the semicolons he had Voltage = [20 40 10 30] Index = [2 0 3 1] Rank = [1 3 0 2] Since the Index array seems to be reversed (or right indexed), he can get his desired Rank array simply by reversing it. Maybe he realized that? Or maybe I misunderstood. As for sorting data in hardware, it's the same as everything else. Whatever works within the requirements, i.e. power, performance, area. From newsfish@newsfish Thu Aug 1 00:46:33 2024 X-Received: by 2002:a37:917:0:b0:6b5:b9a4:bdda with SMTP id 23-20020a370917000000b006b5b9a4bddamr5464575qkj.36.1658656225445; Sun, 24 Jul 2022 02:50:25 -0700 (PDT) X-Received: by 2002:a81:7bd4:0:b0:31e:725c:d853 with SMTP id w203-20020a817bd4000000b0031e725cd853mr5983766ywc.8.1658656225237; Sun, 24 Jul 2022 02:50:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!border-1.nntp.ord.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Jul 2022 02:50:25 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=151.55.253.18; posting-account=m-UiMwoAAAAbscOcrBlPAlM4f7_5-6rz NNTP-Posting-Host: 151.55.253.18 References: <4bcb7bb3-a72c-4a60-9f2e-0f699c32a953@googlegroups.com> <5d2ad8b4-2c78-4041-9d0e-8cbf6f05ecc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <04240164-9382-4386-bb92-b974496bd90dn@googlegroups.com> Subject: Re: GALs and VHDL From: Diego Moimas Injection-Date: Sun, 24 Jul 2022 09:50:25 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 64 Xref: reader01.eternal-september.org comp.lang.vhdl:9879 Il giorno domenica 1 settembre 2019 alle 18:12:53 UTC+2 silverdr ha scritto= : > On 2018-06-13 03:02:50 +0000, abner...@ieee.org said:=20 >=20 > > On Wednesday, June 15, 2016 at 9:41:35 AM UTC-6, silverdr wrote:=20 > >> So far I downloaded and installed the ispLEVER from Lattice, which is= =20 > >> still available and supports "obsolete" devices like GALs. The problem= =20 > >> is that when I try to do some synthesis using=20 > >> ispLEVER/PureVHDL/Synplify/ project I get output like:=20 > >>=20 > >> *******=20 > >> Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl= =20 > >> -target ispGAL -pro '=20 > >>=20 > >>=20 > >> Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights= =20 > >> reserved.=20 > >> Version : 2.0.00.17.20.15=20 > >>=20 > >> Done sucessfully with exit code 1.=20 > >> Error output EDIF file c:/documents and settings/silverdr/my=20 > >> documents/sources/vhdl/r512/r512vhdl.edi=20 > >> Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2=20 > >>=20 > >> Done: failed with exit code: 0002.=20 > >> *******=20 > >>=20 > > > > I have the same problem... when I do Synthesize there appears the next = error:=20 > > Error output EDIF file c:/isplever_classic2_0/examples/ESumRes.edi=20 > > Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2=20 > >=20 > > ...=20 > > How did you fix it? > After spending indecent amount of time trying to troubleshoot the=20 > problem, insrtalling, reinstalling, and exchanging emails with friendly= =20 > people from Lattice, I worked the issue around by running the software=20 > in question in a Wine based Windows emulation. As strange as it may=20 > sound, that was the best option for me but below is a summary of my=20 > "research" on the subject:=20 >=20 > - Windows XP Home SP2 (fresh install) =E2=80=93 no luck=20 > - Windows XP Pro SP3 (fresh install and available updates) =E2=80=93 no l= uck=20 > - Wine based Windows XP emulation =E2=80=93 runs (sic!)=20 > - Windows 10 Pro 64 bit installed from scratch in a virtual machine =E2= =80=93 runs=20 > - Windows 10 Pro 32 bit installed from scratch in a virtual machine - run= s=20 >=20 > Looks like there's some kind of problem with "native" Windows XP support. Hi, after facing same problem, I got it working in XP by installing: .NET Frame= work 3.5SP1, .NET Framework 4.0, VCredist x86 from 2003 to 2012 Regards D From newsfish@newsfish Thu Aug 1 00:46:33 2024 X-Received: by 2002:a05:622a:1452:b0:344:51de:cc10 with SMTP id v18-20020a05622a145200b0034451decc10mr2806342qtx.432.1660833055661; Thu, 18 Aug 2022 07:30:55 -0700 (PDT) X-Received: by 2002:a25:af8e:0:b0:67c:3f7:e8eb with SMTP id g14-20020a25af8e000000b0067c03f7e8ebmr3142033ybh.646.1660833054928; Thu, 18 Aug 2022 07:30:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Aug 2022 07:30:54 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=139.174.228.250; posting-account=R8k_DQoAAACXMD4Erl3y5tsnY0AOBn7Q NNTP-Posting-Host: 139.174.228.250 References: <2c529f55.0212240612.6371c919@posting.google.com> <3E14EDBD.4892AC2E@ieee.org> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1772c39f-c38e-423d-8c09-e3c83ec873cfn@googlegroups.com> Subject: Re: Conditional compilation in VHDL? From: jeevan DJ Injection-Date: Thu, 18 Aug 2022 14:30:55 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 2793 Xref: reader01.eternal-september.org comp.lang.vhdl:9880 On Friday, January 3, 2003 at 9:19:11 AM UTC+1, Ralf Hildebrandt wrote: > Hi Clyde! > [quote repaired] > >>>Does anything exist in VHDL equivalent to verilog conditional > >>>compilation directive ( `ifdef .... `else .... `endif ) > >>Just use constants. > > This does not work in Synplify.... It required a signal. > This a plain VHDL - this should work everywhere. > define a constant: > constant switchA : integer:=1; -- 1 enabled / 0 disabled > > Feed this constant through an entitiy to a lower component: > entity compA is > generic( > switchA : integer:=1 ); > port( -- and so on... > ); > end compA; > > Instantiate this component in the top component (where the constat is > defined). > Within compA use the constant: > > process(in1,in2) > begin > if (switchA=1) then > out1<=in1 AND in2; > else out1<=in1; > end if; > end process; > > As you can see - the constant defines, if and AND-gate is inferred or a > simple wire is taken. > > With the uses of constants if have written a several extras for a > microcontroller, that all can be disabled, if one changes the constant. > Hint: If you synthesize just compA to test the synthesized components > within the behavioral top-component, you have to change the default > value of the constant within the entity AND where the constant is > defined in the top-component. > > Your synthesis tool will warn you, that an expression is never reached. > (In my examle: the else-statement.) > Ralf Hi, Can anyone say how to address schemes and write a byte code? From newsfish@newsfish Thu Aug 1 00:46:33 2024 X-Received: by 2002:a05:622a:1827:b0:35b:bb7f:6851 with SMTP id t39-20020a05622a182700b0035bbb7f6851mr891889qtc.457.1664426869032; Wed, 28 Sep 2022 21:47:49 -0700 (PDT) X-Received: by 2002:ad4:596f:0:b0:4ad:79fc:9ae0 with SMTP id eq15-20020ad4596f000000b004ad79fc9ae0mr1095811qvb.53.1664426868789; Wed, 28 Sep 2022 21:47:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Sep 2022 21:47:48 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=58.174.64.206; posting-account=NtVegAkAAABqonxLV7Yqx9pBYUwTn2yC NNTP-Posting-Host: 58.174.64.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <609002d9-b5cb-40c9-a01f-e0fc3a380ac3n@googlegroups.com> Subject: VHDL Looking for clock dropout on clocks of different speeds. From: Steve Auch-Schwelk Injection-Date: Thu, 29 Sep 2022 04:47:49 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2824 Xref: reader01.eternal-september.org comp.lang.vhdl:9881 I have a SoC which is being fed an external 125MHz clock. I am using the Zy= nq processor with internal clock speed of 100MHz as an independent source t= o see if there are any dropouts. Here is the heavily redacted code, to just produce the problem I am seeing. Basic premise is that the faster clock will always have updated it=E2=80=99= s clock_count, by the time the slower clock checks to see if it has changed= . If it is the same, the faster clock has failed for some reason, and I wan= t to record how may cycles it has failed for. Clock_in is 125MHZ. Clock_100 is 100MHz. The error_count_s is being incremented about .05% of the time, even though = there is no failure or fallout of Clock_in. I have independently verified that the counters are updating at the correct= rate. Is there some timing issue here I=E2=80=99m missing? --------------------------------------------------- process(Clock_in,reset) begin if (reset=3D'0') then clock_counter <=3D (others=3D>'0'); elsif rising_edge(Clock_in) then clock_counter <=3D clock_counter + 1; end if; -- rising edge clock_in end process; process(Clock_100,reset) --loss of clock detector, clocked fro= m onboard processor clock begin if (rising_edge(Clock_100)) then if (clock_counter =3D clock_counter_old) then -- clock_counter = hasn't been updated since the last pulse error_count_s <=3D error_count_s + 1; CSO_down_out <=3D error_count_s; --count how long we've= been without 125MHz clock end if; clock_counter_old <=3D clock_counter; end if; -- rising edge end process; From newsfish@newsfish Thu Aug 1 00:46:34 2024 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx15.iad.POSTED!not-for-mail MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: VHDL Looking for clock dropout on clocks of different speeds. Content-Language: en-US Newsgroups: comp.lang.vhdl References: <609002d9-b5cb-40c9-a01f-e0fc3a380ac3n@googlegroups.com> From: Richard Damon In-Reply-To: <609002d9-b5cb-40c9-a01f-e0fc3a380ac3n@googlegroups.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 60 Message-ID: X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Thu, 29 Sep 2022 07:05:27 -0400 X-Received-Bytes: 3339 Xref: reader01.eternal-september.org comp.lang.vhdl:9882 On 9/29/22 12:47 AM, Steve Auch-Schwelk wrote: > I have a SoC which is being fed an external 125MHz clock. I am using the Zynq processor with internal clock speed of 100MHz as an independent source to see if there are any dropouts. > > Here is the heavily redacted code, to just produce the problem I am seeing. > > Basic premise is that the faster clock will always have updated it’s clock_count, by the time the slower clock checks to see if it has changed. If it is the same, the faster clock has failed for some reason, and I want to record how may cycles it has failed for. > > Clock_in is 125MHZ. Clock_100 is 100MHz. > > The error_count_s is being incremented about .05% of the time, even though there is no failure or fallout of Clock_in. > > I have independently verified that the counters are updating at the correct rate. > > Is there some timing issue here I’m missing? > > --------------------------------------------------- > process(Clock_in,reset) > begin > if (reset='0') then > clock_counter <= (others=>'0'); > elsif rising_edge(Clock_in) then > clock_counter <= clock_counter + 1; > end if; -- rising edge clock_in > end process; > process(Clock_100,reset) --loss of clock detector, clocked from onboard processor clock > begin > if (rising_edge(Clock_100)) then > if (clock_counter = clock_counter_old) then -- clock_counter hasn't been updated since the last pulse > error_count_s <= error_count_s + 1; > CSO_down_out <= error_count_s; --count how long we've been without 125MHz clock > end if; > clock_counter_old <= clock_counter; > end if; -- rising edge > end process; The problem is syncronization, and slight differences in propigation time for each bit of the counter. This can cause the faster counter, when sampled by the slower clock, when it is counting from a value like 0111 to the value 1000 to see some of the new bits and some of the old bits, allowing ANY value between 0000 and 1111 to appear. One simple solution is to change the counters to "Gray Counters" which only change a single bit on each transisition, counting like: 000 001 010 011 111 110 100 101 100 000 And that sort of value won't get grabled crossing the clock domain. From newsfish@newsfish Thu Aug 1 00:46:34 2024 X-Received: by 2002:a05:622a:2d0:b0:395:e96a:8eeb with SMTP id a16-20020a05622a02d000b00395e96a8eebmr2229498qtx.176.1666101381847; Tue, 18 Oct 2022 06:56:21 -0700 (PDT) X-Received: by 2002:a05:622a:2d1:b0:39c:c710:5181 with SMTP id a17-20020a05622a02d100b0039cc7105181mr2114785qtx.135.1666101381559; Tue, 18 Oct 2022 06:56:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Oct 2022 06:56:21 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=195.70.113.54; posting-account=EsRgEAoAAABucVWk3-YJ1G8c4St90AN4 NNTP-Posting-Host: 195.70.113.54 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL biggest shit From: Marvin Klabacher Injection-Date: Tue, 18 Oct 2022 13:56:21 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1007 Xref: reader01.eternal-september.org comp.lang.vhdl:9883 VHDL is the biggest shit From newsfish@newsfish Thu Aug 1 00:46:34 2024 Newsgroups: comp.lang.vhdl From: Stef Subject: Disabled generate give compile error in Modelsim Mail-Copies-To: nobody User-Agent: slrn/1.0.3 (Linux) Message-ID: Organization: Newsxs Date: Tue, 06 Dec 2022 15:40:45 +0100 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!weretis.net!feeder8.news.weretis.net!news.uzoreto.com!feeder.usenetexpress.com!tr2.eu1.usenetexpress.com!94.232.112.244.MISMATCH!feed.abavia.com!abe004.abavia.com!abp001.abavia.com!news.newsxs.nl!not-for-mail Lines: 91 Injection-Date: Tue, 06 Dec 2022 15:40:45 +0100 Injection-Info: news.newsxs.nl; mail-complaints-to="abuse@newsxs.nl" Xref: reader01.eternal-september.org comp.lang.vhdl:9884 Hi, It has been a while since I used VHDL so I am a little rusty. Did not much use the generate statement in the past either. And now I have the problem that I have (been given) a VHDL model that has a conditional generate in it. And this does not work as I expected. In the model, the purpose of the conditional is that there is a clock source that cannot be simulated, so an alternative is simulated. I have reproduced the problem in the minimal example below. If I decalare 'sigio' as 'inout', as below and as I got the model, then when I simulate it, the signals in the simulation remain 'U'. So somehow the 'gentest' model drives the 'sigio' signal although the generic 'this_is_a_simulation' has been set to true. If I declare 'sigio' as 'in' (change the comment line in the port), I get a compilation error in Modelsim on driving the type 'in' 'sigio' signal. When I then just comment out the 'rtlblk' generate, the model simulates as expected. Can this be made to work as expected (simulation/pll model switch without changing the code)? Unfortunately I cannot get information from the original creator of this construct and I don't know if it ever worked. -------- gentest.vhd ------------ library ieee; use ieee.std_logic_1164.all; entity gentest is generic( this_is_a_simulation : boolean := true ); port( -- sigio : in std_logic; sigio : inout std_logic; sigout : out std_logic ); end entity gentest; architecture behav of gentest is begin rtlblk : if this_is_a_simulation = false generate sigio <= '1'; sigout <= '1'; end generate; simblk : if this_is_a_simulation = true generate sigout <= sigio; end generate; end architecture behav; -------- tb_gentest.vhd ------------ library ieee; use ieee.std_logic_1164.all; entity tb_gentest is end entity tb_gentest; architecture behav of tb_gentest is signal clk : std_logic; signal sigout : std_logic; begin gentest_inst : entity work.gentest generic map( this_is_a_simulation => true ) port map( sigio => clk, sigout => sigout ); process begin clk <= '0'; wait for 10ns; clk <= '1'; wait for 10ns; end process; end architecture behav; -- Stef Hey, where did that sig go?! From newsfish@newsfish Thu Aug 1 00:46:35 2024 Newsgroups: comp.lang.vhdl,comp.arch.fpga From: Stef Subject: Disabled generate gives compile error in Modelsim Mail-Copies-To: nobody User-Agent: slrn/1.0.3 (Linux) Message-ID: Organization: Newsxs Date: Fri, 09 Dec 2022 12:20:09 +0100 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!weretis.net!feeder8.news.weretis.net!npeer.as286.net!npeer-ng0.as286.net!peer02.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!feed.abavia.com!abe005.abavia.com!abp003.abavia.com!news.newsxs.nl!not-for-mail Lines: 102 Injection-Date: Fri, 09 Dec 2022 12:20:09 +0100 Injection-Info: news.newsxs.nl; mail-complaints-to="abuse@newsxs.nl" X-Received-Bytes: 3662 Xref: reader01.eternal-september.org comp.lang.vhdl:9885 comp.arch.fpga:27007 [This is a repost. Posted this to comp.lang.vhdl a few days ago, but no replies. So maybe nobody knows the answer, it was a malformed question or there are no readers in that group. So a repost (with a little clarification, I hope) with the comp.arch.fpga added at least resolves the last option. ;-)] It has been a while since I used VHDL so I am a little rusty. Did not much use the generate statement in the past either. And now I have the problem that I have (been given) a VHDL model that has a conditional generate in it. And this does not work as I expected. In the model, the purpose of the conditional is that there is a clock source that cannot be simulated, so an alternative is simulated. I have reproduced the problem in the minimal example below. If I declare 'sigio' as 'inout', as below and as I got the model, then when I simulate it, the signals in the simulation remain 'U'. So somehow the 'gentest' model drives the 'sigio' signal although the generic 'this_is_a_simulation' has been set to true. If I declare 'sigio' as 'in' (change the comment line in the port), I get a compilation error in Modelsim on driving the type 'in' 'sigio' signal. When I then just comment out the 'rtlblk' generate, the model simulates as expected. Can this be made to work as expected (simulation/clocksource model switch without changing the code)? Unfortunately I cannot get information from the original creator of this construct and I don't know if it ever worked. -------- gentest.vhd ------------ library ieee; use ieee.std_logic_1164.all; entity gentest is generic( this_is_a_simulation : boolean := true ); port( -- sigio : in std_logic; -- Compile error sigio : inout std_logic; -- Original line sigout : out std_logic ); end entity gentest; architecture behav of gentest is begin -- If I comment out this generate, the compile error with sigio as -- 'in' disappears. -- But should this section not be ignored if 'this_is_a_simulation' -- is set to false? rtlblk : if this_is_a_simulation = false generate sigio <= '1'; sigout <= '1'; end generate; simblk : if this_is_a_simulation = true generate sigout <= sigio; end generate; end architecture behav; -------- tb_gentest.vhd ------------ library ieee; use ieee.std_logic_1164.all; entity tb_gentest is end entity tb_gentest; architecture behav of tb_gentest is signal clk : std_logic; signal sigout : std_logic; begin gentest_inst : entity work.gentest generic map( this_is_a_simulation => true ) port map( sigio => clk, sigout => sigout ); process begin clk <= '0'; wait for 10ns; clk <= '1'; wait for 10ns; end process; end architecture behav; -- Stef The world is no nursery. - Sigmund Freud From newsfish@newsfish Thu Aug 1 00:46:35 2024 X-Received: by 2002:a05:620a:9d5:b0:6ff:8c91:5609 with SMTP id y21-20020a05620a09d500b006ff8c915609mr90578qky.132.1670796657322; Sun, 11 Dec 2022 14:10:57 -0800 (PST) X-Received: by 2002:a05:622a:602f:b0:3a7:e66a:28f8 with SMTP id he47-20020a05622a602f00b003a7e66a28f8mr12807352qtb.563.1670796657185; Sun, 11 Dec 2022 14:10:57 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!2.eu.feeder.erje.net!feeder.erje.net!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 Dec 2022 14:10:56 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:d854:7b4c:157:ac1; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:d854:7b4c:157:ac1 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6720be25-79b8-4136-8ffb-336b2eeefd5cn@googlegroups.com> Subject: Re: Disabled generate gives compile error in Modelsim From: KJ Injection-Date: Sun, 11 Dec 2022 22:10:57 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9886 On Friday, December 9, 2022 at 6:20:14 AM UTC-5, Stef wrote: > If I declare 'sigio' as 'inout', as below and as I got the model, then wh= en I simulate it, the signals in the simulation remain 'U'. So somehow the = 'gentest' model drives the 'sigio' signal although the generic 'this_is_a_s= imulation' has been set to true. When you declared sigio as inout, you're saying that there will be a driver= for this signal. But in your testbench you've connected sigio to the sign= al clk, and you have a process that drives clk. Regardless of how if this_= is_a_simulation is set there will be problems. * if this_is_a_simulation =3D true then sigio will get set to '1'. But sin= ce clk is also driving the signal to either a '0' or '1', half the time the= two drivers will be in conflict. When clk happens to be set to '1' is the= only time that you will get a '1'. The other half of the time you'll have= a '1' and a '0' being driven...resulting in unknown * if this_is_a_simulation =3D false then the gentest entity will say that t= here is a driver for 'sigio', but since the architecture doesn't actually d= rive the signal, sigio will be unknown and will always override the '0' and= '1' that clk is being set to. The result of that condition is an unknown,= all of the time. You could work around the problem for "if this_is_a_simulation =3D false" b= y changing the entity to give a default of 'Z' like this: "sigio : inout s= td_logic :=3D 'Z'; -- Original line". Now sigio will have a driver of 'Z' = at t=3D0 and 'clk' will always be able to override the 'Z' with a '0' or '1= '. > I then just comment out the 'rtlblk' generate, the model simulates as exp= ected. Not sure what you mean with "as expected". This design is fatally flawed b= y having two drivers both trying to drive the same signal at the same time.= I have no idea what you're trying to do inside gentest with sigio in the = first place. Either sigio should be of type 'in' and the "sigio <=3D 1'" s= tatement should be removed OR if it really is meant to be of type 'inout', = then you should only be driving sigio when nothing on the outside (i.e. the= testbench signal clk) is actively driving it to '0' or '1'. During that = time clk should be driven to 'Z' in the testbench. I have no idea how you = expect gentest to know this based on the posted code. Generally, when ther= e are multiple potential drivers of a signal, there is also another signal = that tells both sides who has control. Check how something like an 74xx244= IC works. There is an OE input signal that tells the IC when it should ac= tively drive the signal low or high and when it should tri-state the output= s. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:35 2024 Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Disabled generate gives compile error in Modelsim References: <6720be25-79b8-4136-8ffb-336b2eeefd5cn@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/1.0.3 (Linux) Message-ID: Organization: Newsxs Date: Mon, 12 Dec 2022 10:26:41 +0100 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!news.uzoreto.com!feeder.usenetexpress.com!tr2.eu1.usenetexpress.com!94.232.112.244.MISMATCH!feed.abavia.com!abe004.abavia.com!abp003.abavia.com!news.newsxs.nl!not-for-mail Lines: 67 Injection-Date: Mon, 12 Dec 2022 10:26:41 +0100 Injection-Info: news.newsxs.nl; mail-complaints-to="abuse@newsxs.nl" Xref: reader01.eternal-september.org comp.lang.vhdl:9887 On 2022-12-11 KJ wrote in comp.lang.vhdl: > On Friday, December 9, 2022 at 6:20:14 AM UTC-5, Stef wrote: > >> If I declare 'sigio' as 'inout', as below and as I got the model, then when I simulate it, the signals in the simulation remain 'U'. So somehow the 'gentest' model drives the 'sigio' signal although the generic 'this_is_a_simulation' has been set to true. > > When you declared sigio as inout, you're saying that there will be a driver for this signal. But in your testbench you've connected sigio to the signal clk, and you have a process that drives clk. Regardless of how if this_is_a_simulation is set there will be problems. Okay, just the fact that the signal is declared as inout is a problem already. > * if this_is_a_simulation = true then sigio will get set to '1'. But since clk is also driving the signal to either a '0' or '1', half the time the two drivers will be in conflict. When clk happens to be set to '1' is the only time that you will get a '1'. The other half of the time you'll have a '1' and a '0' being driven...resulting in unknown > * if this_is_a_simulation = false then the gentest entity will say that there is a driver for 'sigio', but since the architecture doesn't actually drive the signal, sigio will be unknown and will always override the '0' and '1' that clk is being set to. The result of that condition is an unknown, all of the time. > > You could work around the problem for "if this_is_a_simulation = false" by changing the entity to give a default of 'Z' like this: "sigio : inout std_logic := 'Z'; -- Original line". Now sigio will have a driver of 'Z' at t=0 and 'clk' will always be able to override the 'Z' with a '0' or '1'. > In the examples I tried to reduce the problem down to a small model and I may have simpified it too much. In the "if this_is_a_simulation = false" situation, the sigio in gentest.vhd is connected to the clock pin of an instantiated PLL block and according to the code I inherited, this pin is an inout signal (you would expect an in, but it is inout). >> I then just comment out the 'rtlblk' generate, the model simulates as expected. > > Not sure what you mean with "as expected". This design is fatally flawed by having two drivers both trying to drive the same signal at the same time. I have no idea what you're trying to do inside gentest with sigio in the first place. Either sigio should be of type 'in' and the "sigio <= 1'" statement should be removed OR if it really is meant to be of type 'inout', then you should only be driving sigio when nothing on the outside (i.e. the testbench signal clk) is actively driving it to '0' or '1'. During that time clk should be driven to 'Z' in the testbench. I have no idea how you expect gentest to know this based on the posted code. Generally, when there are multiple potential drivers of a signal, there is also another signal that tells both sides who has control. Check how something like an 74xx244 IC works. There is an OE input signal that tells the IC when it should actively drive the signal low or high and when it should tri-state the outputs. > What I "expect" is that I can simulate the model (this_is_a_simulation = true) with the testbench driving the clk signal. And that by setting this_is_a_simulation to false, I can generate the logic for the real FPGA, where clk is connected to an IO pin and must for some reason be inout. I now solve this by commenting in/out a block of code. This works, but is error prone. Luckily forgetting to uncomment the PLL block is easily spotted as it results in a fast run with an empty FPGA as a result. ;-) As I said before, I got this code with this construct and could not get is to work and I do not know if it ever worked. I expected the problem to be in the "if condition generate" part of the code. But of I understand you correctly, the problem already is in declaring the signal as inout. But what should a compiler do with a conditional generate block that is off? Should it be completely ignored or should it still be tested for validity? Say we have an entity with this port: port( signal_in : in std_logic ); And then somewhere in the architecture we have this: testblock : if false generate signal_in <= '1'; end generate; Should the compiler ignore driving a input signal or should it give an error although testblock is "off"? -- Stef Walk softly and carry a BFG-9000. From newsfish@newsfish Thu Aug 1 00:46:36 2024 X-Received: by 2002:a05:6214:4305:b0:4bb:e8a8:46b7 with SMTP id oe5-20020a056214430500b004bbe8a846b7mr73374927qvb.43.1670981608725; Tue, 13 Dec 2022 17:33:28 -0800 (PST) X-Received: by 2002:ac8:1182:0:b0:35a:7084:23b8 with SMTP id d2-20020ac81182000000b0035a708423b8mr86238193qtj.135.1670981608575; Tue, 13 Dec 2022 17:33:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Dec 2022 17:33:28 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:94c:1101:54c5:602a; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:94c:1101:54c5:602a References: <6720be25-79b8-4136-8ffb-336b2eeefd5cn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0b9d660e-36d6-4541-a772-54688d7ffcadn@googlegroups.com> Subject: Re: Disabled generate gives compile error in Modelsim From: KJ Injection-Date: Wed, 14 Dec 2022 01:33:28 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 6558 Xref: reader01.eternal-september.org comp.lang.vhdl:9888 On Monday, December 12, 2022 at 4:26:46 AM UTC-5, Stef wrote: > On 2022-12-11 KJ wrote in comp.lang.vhdl:=20 > > On Friday, December 9, 2022 at 6:20:14 AM UTC-5, Stef wrote:=20 > In the examples I tried to reduce the problem down to a small model and= =20 > I may have simpified it too much. In the "if this_is_a_simulation =3D=20 > false" situation, the sigio in gentest.vhd is connected to the clock=20 > pin of an instantiated PLL block and according to the code I inherited,= =20 > this pin is an inout signal (you would expect an in, but it is inout). This doesn't make any sense. Is gentest connected to an input or an output= of the PLL block? Whichever it is, gentest should be the opposite. This = is pretty basic, you connect inputs to outputs and vice versa. You don't c= onnect outputs together, you don't connect inputs. Pretty simple. > > Not sure what you mean with "as expected". This design is fatally flawe= d by having two drivers both trying to drive the same signal at the same ti= me. I have no idea what you're trying to do inside gentest with sigio in th= e first place. Either sigio should be of type 'in' and the "sigio <=3D 1'" = statement should be removed OR if it really is meant to be of type 'inout',= then you should only be driving sigio when nothing on the outside (i.e. th= e testbench signal clk) is actively driving it to '0' or '1'. During that t= ime clk should be driven to 'Z' in the testbench. I have no idea how you ex= pect gentest to know this based on the posted code. Generally, when there a= re multiple potential drivers of a signal, there is also another signal tha= t tells both sides who has control. Check how something like an 74xx244 IC = works. There is an OE input signal that tells the IC when it should activel= y drive the signal low or high and when it should tri-state the outputs.=20 > What I "expect" is that I can simulate the=20 > model (this_is_a_simulation =3D true) with the testbench=20 > driving the clk signal. And that by setting this_is_a_simulation=20 > to false, I can generate the logic for the real FPGA, where clk is=20 > connected to an IO pin and must for some reason be inout.=20 >=20 This doesn't make much sense either. You shouldn't be changing logic to do= simulation. The whole point of simulation is to have a model of the real = system. If you are making logic changes "for simulation", you are most lik= ely making a mistake that you will then have to figure out. > I now solve this by commenting in/out a block of code. This works, but=20 > is error prone. Luckily forgetting to uncomment the PLL block is easily= =20 > spotted as it results in a fast run with an empty FPGA as a result. ;-)= =20 >=20 Error prone is a polite way to put it. Of no value at all would be another= . > As I said before, I got this code with this construct and could not get= =20 > is to work and I do not know if it ever worked.=20 >=20 That's why you run the simulator...to find out what's wrong. But you don't= start by connecting outputs together. > I expected the problem to be in the "if condition generate" part of the= =20 > code. But of I understand you correctly, the problem already is in=20 > declaring the signal as inout.=20 >=20 The problem is that you are thinking that a real design would connect two o= utputs together. It has nothing to do with VHDL at all. > But what should a compiler do with a conditional generate block that is= =20 > off? Should it be completely ignored or should it still be tested for=20 > validity?=20 >=20 The compiler already did the right thing. > Say we have an entity with this port:=20 >=20 > port( signal_in : in std_logic );=20 >=20 > And then somewhere in the architecture we have this:=20 >=20 > testblock : if false generate=20 > signal_in <=3D '1';=20 > end generate;=20 >=20 > Should the compiler ignore driving a input signal or should it give an=20 > error although testblock is "off"?=20 >=20 As long as the syntax is correct (and your signal assignment to signal_in i= s), there is no error for the compiler to report. What error do you think = should be reported? The compiler does not report on design errors such as = connecting two outputs together as you did. Instead it shows you the resul= ts of that design error which is that the resulting output is undefined. If you want the compiler itself to help you out some more, change all your = usages of 'std_logic' to 'std_ulogic' in gentest as well as the testbench. = Then the compilation will fail because signals of type 'std_ulogic' can ha= ve only one driver. You won't even be able to start the simulation until y= ou fix the error. Use of std_ulogic rather than std_logic finds the design= errors that you are creating right at compile time and gives you all the i= nformation about where the problem is located in the code. Using std_logic= only in situations where their truly can be multiple drivers such as some = shared bus like the data bus between a processor and memory. In all other = cases, use std_ulogic. FPGAs do not support multiple driver designs for an= y internal signal. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:36 2024 Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Disabled generate gives compile error in Modelsim References: <6720be25-79b8-4136-8ffb-336b2eeefd5cn@googlegroups.com> <0b9d660e-36d6-4541-a772-54688d7ffcadn@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/1.0.3 (Linux) Message-ID: Organization: Newsxs Date: Wed, 14 Dec 2022 13:08:31 +0100 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!news.uzoreto.com!feeder.usenetexpress.com!tr3.eu1.usenetexpress.com!94.232.112.245.MISMATCH!feed.abavia.com!abe005.abavia.com!abp001.abavia.com!news.newsxs.nl!not-for-mail Lines: 118 Injection-Date: Wed, 14 Dec 2022 13:08:31 +0100 Injection-Info: news.newsxs.nl; mail-complaints-to="abuse@newsxs.nl" Xref: reader01.eternal-september.org comp.lang.vhdl:9889 On 2022-12-14 KJ wrote in comp.lang.vhdl: > On Monday, December 12, 2022 at 4:26:46 AM UTC-5, Stef wrote: >> On 2022-12-11 KJ wrote in comp.lang.vhdl: >> > On Friday, December 9, 2022 at 6:20:14 AM UTC-5, Stef wrote: > >> In the examples I tried to reduce the problem down to a small model and >> I may have simpified it too much. In the "if this_is_a_simulation = >> false" situation, the sigio in gentest.vhd is connected to the clock >> pin of an instantiated PLL block and according to the code I inherited, >> this pin is an inout signal (you would expect an in, but it is inout). > > This doesn't make any sense. Is gentest connected to an input or an output of the PLL block? Whichever it is, gentest should be the opposite. This is pretty basic, you connect inputs to outputs and vice versa. You don't connect outputs together, you don't connect inputs. Pretty simple. > In the design I inherited the PLL pin is a package pin and declared as inout. Why this was done, I do not know. So two inouts are connected together. And yes, I am aware that you don't connect outputs or inputs together (I am and electronics engineer). I will see if it can be changed to an input to get rid of this problem. >> > Not sure what you mean with "as expected". This design is fatally flawed by having two drivers both trying to drive the same signal at the same time. I have no idea what you're trying to do inside gentest with sigio in the first place. Either sigio should be of type 'in' and the "sigio <= 1'" statement should be removed OR if it really is meant to be of type 'inout', then you should only be driving sigio when nothing on the outside (i.e. the testbench signal clk) is actively driving it to '0' or '1'. During that time clk should be driven to 'Z' in the testbench. I have no idea how you expect gentest to know this based on the posted code. Generally, when there are multiple potential drivers of a signal, there is also another signal that tells both sides who has control. Check how something like an 74xx244 IC works. There is an OE input signal that tells the IC when it should actively drive the signal low or high and when it should tri-state the outputs. > >> What I "expect" is that I can simulate the >> model (this_is_a_simulation = true) with the testbench >> driving the clk signal. And that by setting this_is_a_simulation >> to false, I can generate the logic for the real FPGA, where clk is >> connected to an IO pin and must for some reason be inout. >> > > This doesn't make much sense either. You shouldn't be changing logic to do simulation. The whole point of simulation is to have a model of the real system. If you are making logic changes "for simulation", you are most likely making a mistake that you will then have to figure out. > Aparently the PLL could not be simulated, so the clock came directly from the test bench. So some switch between testbench and pll clock must be made between simulation and hardware generation. Probably not the best solution, as you say. But this is how I got it. And I try to understand why they did this before changing everything. >> I now solve this by commenting in/out a block of code. This works, but >> is error prone. Luckily forgetting to uncomment the PLL block is easily >> spotted as it results in a fast run with an empty FPGA as a result. ;-) >> > > Error prone is a polite way to put it. Of no value at all would be another. > I would not say that, only the clock source is changed from PLL'ed input to direct input (at the intended PLL frequency). >> As I said before, I got this code with this construct and could not get >> is to work and I do not know if it ever worked. >> > > That's why you run the simulator...to find out what's wrong. But you don't start by connecting outputs together. > >> I expected the problem to be in the "if condition generate" part of the >> code. But of I understand you correctly, the problem already is in >> declaring the signal as inout. >> > > The problem is that you are thinking that a real design would connect two outputs together. It has nothing to do with VHDL at all. > No I do not think that, what makes you believe I do? >> But what should a compiler do with a conditional generate block that is >> off? Should it be completely ignored or should it still be tested for >> validity? >> > > The compiler already did the right thing. > >> Say we have an entity with this port: >> >> port( signal_in : in std_logic ); >> >> And then somewhere in the architecture we have this: >> >> testblock : if false generate >> signal_in <= '1'; >> end generate; >> >> Should the compiler ignore driving a input signal or should it give an >> error although testblock is "off"? >> > > As long as the syntax is correct (and your signal assignment to signal_in is), there is no error for the compiler to report. What error do you think should be reported? The compiler does not report on design errors such as connecting two outputs together as you did. Instead it shows you the results of that design error which is that the resulting output is undefined. > The syntax in itself is correct, but assigning a value to an input is not. So I would not expect an error on that code, as do you, I read in the above. However when I compile this in Modelsim: rtlblk : if this_is_a_simulation = false generate sigio <= '1'; sigout <= '1'; end generate; With this_is_a_simulation set to true and sigio declared as in, I get the following error -- Compiling architecture behav of gentest ** Error: ../gentest.vhd(19): Cannot drive signal 'sigio' of mode IN. This is not what I expect, why is the assignment not ignored? This is the core of my original question. What is the expected behaviour when such generate blocks are disabled and contain incorrect code? > If you want the compiler itself to help you out some more, change all your usages of 'std_logic' to 'std_ulogic' in gentest as well as the testbench. Then the compilation will fail because signals of type 'std_ulogic' can have only one driver. You won't even be able to start the simulation until you fix the error. Use of std_ulogic rather than std_logic finds the design errors that you are creating right at compile time and gives you all the information about where the problem is located in the code. Using std_logic only in situations where their truly can be multiple drivers such as some shared bus like the data bus between a processor and memory. In all other cases, use std_ulogic. FPGAs do not support multiple driver designs for any internal signal. No, FPGAa don't have internal tri-state signals. Changing to std_ulogic sounds like a good idea. Is this what you normally use for internal logic? -- Stef Two wrongs are only the beginning. -- Kohn From newsfish@newsfish Thu Aug 1 00:46:36 2024 X-Received: by 2002:a05:620a:89d:b0:6fa:77c0:ea01 with SMTP id b29-20020a05620a089d00b006fa77c0ea01mr167216qka.537.1671022271224; Wed, 14 Dec 2022 04:51:11 -0800 (PST) X-Received: by 2002:a05:6214:4489:b0:4d0:a978:7371 with SMTP id on9-20020a056214448900b004d0a9787371mr1134858qvb.85.1671022271025; Wed, 14 Dec 2022 04:51:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!news.mixmin.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Dec 2022 04:51:10 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=2a02:2f09:3c1b:4700:8860:a497:b197:150e; posting-account=lw4qRwoAAAAv1kgiB5muaVA_JFRdiecn NNTP-Posting-Host: 2a02:2f09:3c1b:4700:8860:a497:b197:150e User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a437d70-1086-4c44-8dfe-1b64b7bddbb8n@googlegroups.com> Subject: Excess 3 Adder: Add 2 three digits numbers in excess 3. From: Virulog_X Injection-Date: Wed, 14 Dec 2022 12:51:11 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader01.eternal-september.org comp.lang.vhdl:9890 Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any idea on how to continue, please help. thx ! module Decimal_to_E3(input[10:0] dec, output reg[15:0] E3); reg[10:0] aux; reg[1:0] counter; always @ (dec) begin aux = dec; E3 = {4{4'b0011}}; counter = 2'b00; while(aux != 0) begin E3[counter * 4 +: 4] = aux % 10 + 3; aux = aux / 10; counter = counter + 1; end end endmodule //E3_Adder module E3_Adder(input [11:0] in_1, in_2, output [15:0] out_1); PA v1(in_1[3:0],in_2[3:0], out_1[3:0], cout); //how do i continue ???? endmodule module PA(a,b,sum,cout); input [3:0]a, b; output cout; output [3:0]sum; wire c0,c1,c2; HA u1(a[0], b[0], sum[0], c0); FA u2(a[1], b[1], c0, sum[1], c1); FA u3(a[2], b[2], c1, sum[2], c2); FA u4(a[3], b[3], c2, sum[3], cout); endmodule module FA(a, b, cin, sum, carry); input a, b, cin; output sum, carry; wire sum, carry; assign sum = a^b^cin;//sum bit assign carry = ((a&b) | (b&cin) | (a&cin));//carry bit endmodule module HA(a, b, sum, carry); input a, b; output sum, carry; wire sum, carry; assign sum = a^b; assign carry = a&b; endmodule /* module P_Adder(a,b,sum, cin, cout); input a */ module Decimal_to_E3_tb(); reg[10:0] dec_tb; wire[15:0] E3_tb; Decimal_to_E3 DUT(.dec(dec_tb), .E3(E3_tb)); initial begin for(dec_tb = 0; dec_tb <= 2000; dec_tb = dec_tb + 1) begin #1; $display("For value = %d, the output is = %0X", dec_tb, E3_tb); end end endmodule /* Arhitectura lui E3_Adder_tb este: ______________________________ ________________________ | | | | test_input_1 --.------>|>dec E3>|---in_1_tb---->|>in_1 | | | Decimal_to_E3 | | | | |_____________________________| | | ___________ | | E3_Adder | | | | ______________________________ | [DUT] out_1>|----out_1_tb_actual-------------------------------->| | | | | | | | | test_input_2 - ( --.-->|>dec E3>|---in_2_tb---->|>in_2 | | | | | | Decimal_to_E3 | | | | | | | |_____________________________| |________________________| | | | | _________ ______________________________ | Comparare |----REZULTAT_TEST-------> | |---------------------test_input_2-------->| | | | | | | | | | | | | | | + |-----test_output_1--->|>dec E3>|---out_1_tb_exp---->| | | | | | Decimal_to_E3 | | | |-------------------------test_input_1-------->|_________| |______________________________| |___________| */ module E3_Adder_tb(); /* Urmatorii parametrii ai testului pot fi modificati: DISPLAY_ALL: 0 sau 1. Daca DISPLAY_ALL este 1, atunci mai multe detalii despre fiecare test vor fi afisate pe ecran. Altfel, doar rezultatul testului va fi tiparit, cu diferenta dintre rezultatul corect si cel caclulat de E3_Adder, in cazul in care difera. DISPLAY_FAILED: 0 sau 1. Daca DISPLAY_FAILED este 1, atunci doar testele failed vor fi afisate pe ecran. Altfel, si rezultatele passed se vor afisa. NAX_VAL_in1: Valoarea maxima la care poate ajunge intrarea in_1, exprimata in decimal. MAX_VAL_in2: Valoarea maxima la care poate ajunge intrare in_2, exprimata in decimal. Testul va lua toate perechile de (in_1, in_2) din intervalul MAX_VAL_in1 X MAX_VAL_in2 si va compara rezultatul obtinut de E3_Adder cu cel corect IMPORTANT: Nota pentru testbenchul public va fi acordata pentru testele care ruleaza cu MAX_VAL_in1 = 500 si MAX_VAL_in2 = 500 */ wire[11:0] in_1_tb, in_2_tb; reg[10:0] test_input_1, test_input_2, test_output_1; wire[15:0] out_1_tb_actual, out_1_tb_exp; reg[10:0] MAX_VAL_in1, MAX_VAL_in2; reg DISPLAY_ALL, DISPLAY_ONLY_FAILED; integer n_tests_passed, n_tests_total; /* Modul ajutator de convertire din decimal in E3 */ Decimal_to_E3 convert_input_1(.dec(test_input_1), .E3(in_1_tb)); Decimal_to_E3 convert_input_2(.dec(test_input_2), .E3(in_2_tb)); Decimal_to_E3 convert_output_1(.dec(test_output_1), .E3(out_1_tb_exp)); /* Modulul testat */ E3_Adder DUT(.in_1(in_1_tb), .in_2(in_2_tb), .out_1(out_1_tb_actual)); initial begin /* parametrii configurabili */ DISPLAY_ALL = 1'b1; DISPLAY_ONLY_FAILED = 1'b1; MAX_VAL_in1 = 11'd500; MAX_VAL_in2 = 11'd500; /* ======================== */ n_tests_total = (MAX_VAL_in1 + 1) * (MAX_VAL_in2 + 1); n_tests_passed = 0; if(MAX_VAL_in1 > 999 || MAX_VAL_in2 > 999) begin $display("[WARNING] Testul nu va functiona cum trebuie! Valorile maxime NU trebuie sa fie mai mari de 999"); end for(test_input_1 = 0; test_input_1 <= MAX_VAL_in1; test_input_1 = test_input_1 + 1) begin for(test_input_2 = 0; test_input_2 <= MAX_VAL_in2; test_input_2 = test_input_2 + 1) begin test_output_1 = test_input_1 + test_input_2; #1; $display("Test nr: %d", test_input_1 * (MAX_VAL_in2 + 1) + test_input_2 + 1); if(DISPLAY_ALL == 1'b1) begin $display("Pentru urmatoarele intrari:\nin_1(decimal) = %d, in_1(E3) = %b \nin_2(decimal) = %d, in_2(E3) = %b \n", test_input_1, in_1_tb, test_input_2, in_2_tb); $display("Rezultatul asteptat: out_1(decimal) = %d, out_1(E3) = %b", test_output_1, out_1_tb_exp); $display("Rezultatul obtinut: out_1(E3) = %b", out_1_tb_actual); end if(out_1_tb_exp == out_1_tb_actual) begin if(DISPLAY_ONLY_FAILED == 0) begin $display("Testul este PASSED"); end n_tests_passed = n_tests_passed + 1; end else begin $display("Testul este FAILED"); $display("EXP E3: %b_%b_%b_%b =/= ACTUAL E3: %b_%b_%b_%b", out_1_tb_exp[15:12], out_1_tb_exp[11:8], out_1_tb_exp[7:4], out_1_tb_exp[3:0], out_1_tb_actual[15:12], out_1_tb_actual[11:8], out_1_tb_actual[7:4], out_1_tb_actual[3:0]); end $display("============================================================================================================="); $display(""); $display(""); end end $display("Teste passed: %d / %d", n_tests_passed, n_tests_total); end endmodule From newsfish@newsfish Thu Aug 1 00:46:36 2024 X-Received: by 2002:ac8:60d9:0:b0:3a7:e616:e091 with SMTP id i25-20020ac860d9000000b003a7e616e091mr12956283qtm.537.1671027065349; Wed, 14 Dec 2022 06:11:05 -0800 (PST) X-Received: by 2002:a05:6214:4489:b0:4d0:a978:7371 with SMTP id on9-20020a056214448900b004d0a9787371mr1145603qvb.85.1671027065033; Wed, 14 Dec 2022 06:11:05 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Dec 2022 06:11:04 -0800 (PST) In-Reply-To: <5a437d70-1086-4c44-8dfe-1b64b7bddbb8n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2605:ba00:4117:fb49:f9ba:f4d0:562e:8dca; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 2605:ba00:4117:fb49:f9ba:f4d0:562e:8dca References: <5a437d70-1086-4c44-8dfe-1b64b7bddbb8n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5c13555d-0a4d-4d75-bca2-511f811e3d91n@googlegroups.com> Subject: Re: Excess 3 Adder: Add 2 three digits numbers in excess 3. From: "gnuarm.del...@gmail.com" Injection-Date: Wed, 14 Dec 2022 14:11:05 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 7744 Xref: reader01.eternal-september.org comp.lang.vhdl:9891 On Wednesday, December 14, 2022 at 8:51:13 AM UTC-4, Virulog_X wrote: > Excess 3 Adder: Add 2 three digits numbers in excess 3. > ex. 998+345 in excess 3. > > i don't have any idea on how to continue, please help. > thx ! > > module Decimal_to_E3(input[10:0] dec, output reg[15:0] E3); > reg[10:0] aux; > reg[1:0] counter; > always @ (dec) begin > aux = dec; > E3 = {4{4'b0011}}; > counter = 2'b00; > while(aux != 0) begin > E3[counter * 4 +: 4] = aux % 10 + 3; > aux = aux / 10; > counter = counter + 1; > end > end > endmodule > > > //E3_Adder > > module E3_Adder(input [11:0] in_1, in_2, > output [15:0] out_1); > > PA v1(in_1[3:0],in_2[3:0], out_1[3:0], cout); > //how do i continue ???? > > endmodule > > > > module PA(a,b,sum,cout); > input [3:0]a, b; > output cout; > output [3:0]sum; > wire c0,c1,c2; > HA u1(a[0], b[0], sum[0], c0); > FA u2(a[1], b[1], c0, sum[1], c1); > FA u3(a[2], b[2], c1, sum[2], c2); > FA u4(a[3], b[3], c2, sum[3], cout); > endmodule > > > > module FA(a, b, cin, sum, carry); > input a, b, cin; > output sum, carry; > wire sum, carry; > assign sum = a^b^cin;//sum bit > assign carry = ((a&b) | (b&cin) | (a&cin));//carry bit > endmodule > > > module HA(a, b, sum, carry); > input a, b; > output sum, carry; > wire sum, carry; > assign sum = a^b; > assign carry = a&b; > endmodule > > > /* > module P_Adder(a,b,sum, cin, cout); > input a > */ > > > module Decimal_to_E3_tb(); > reg[10:0] dec_tb; > wire[15:0] E3_tb; > > Decimal_to_E3 DUT(.dec(dec_tb), .E3(E3_tb)); > initial begin > for(dec_tb = 0; dec_tb <= 2000; dec_tb = dec_tb + 1) begin > #1; > $display("For value = %d, the output is = %0X", dec_tb, E3_tb); > end > end > endmodule > > /* > Arhitectura lui E3_Adder_tb este: > ______________________________ ________________________ > | | | | > test_input_1 --.------>|>dec E3>|---in_1_tb---->|>in_1 | > | | Decimal_to_E3 | | | > | |_____________________________| | | ___________ > | | E3_Adder | | | > | ______________________________ | [DUT] out_1>|----out_1_tb_actual-------------------------------->| | > | | | | | | | > test_input_2 - ( --.-->|>dec E3>|---in_2_tb---->|>in_2 | | | > | | | Decimal_to_E3 | | | | | > | | |_____________________________| |________________________| | | > | | _________ ______________________________ | Comparare |----REZULTAT_TEST-------> > | |---------------------test_input_2-------->| | | | | | > | | | | | | | > | | + |-----test_output_1--->|>dec E3>|---out_1_tb_exp---->| | > | | | | Decimal_to_E3 | | | > |-------------------------test_input_1-------->|_________| |______________________________| |___________| > */ > module E3_Adder_tb(); > /* > Urmatorii parametrii ai testului pot fi modificati: > DISPLAY_ALL: 0 sau 1. Daca DISPLAY_ALL este 1, atunci mai multe detalii despre fiecare test vor fi afisate pe ecran. > Altfel, doar rezultatul testului va fi tiparit, cu diferenta dintre rezultatul corect si cel caclulat de E3_Adder, in cazul in care difera. > DISPLAY_FAILED: 0 sau 1. Daca DISPLAY_FAILED este 1, atunci doar testele failed vor fi afisate pe ecran. Altfel, si rezultatele passed se vor afisa. > NAX_VAL_in1: Valoarea maxima la care poate ajunge intrarea in_1, exprimata in decimal. > MAX_VAL_in2: Valoarea maxima la care poate ajunge intrare in_2, exprimata in decimal. > Testul va lua toate perechile de (in_1, in_2) din intervalul MAX_VAL_in1 X MAX_VAL_in2 si va compara rezultatul obtinut de E3_Adder cu cel corect > > IMPORTANT: Nota pentru testbenchul public va fi acordata pentru testele care ruleaza cu MAX_VAL_in1 = 500 si MAX_VAL_in2 = 500 > */ > > wire[11:0] in_1_tb, in_2_tb; > reg[10:0] test_input_1, test_input_2, test_output_1; > wire[15:0] out_1_tb_actual, out_1_tb_exp; > > > reg[10:0] MAX_VAL_in1, MAX_VAL_in2; > reg DISPLAY_ALL, DISPLAY_ONLY_FAILED; > integer n_tests_passed, n_tests_total; > /* Modul ajutator de convertire din decimal in E3 */ > Decimal_to_E3 convert_input_1(.dec(test_input_1), .E3(in_1_tb)); > Decimal_to_E3 convert_input_2(.dec(test_input_2), .E3(in_2_tb)); > Decimal_to_E3 convert_output_1(.dec(test_output_1), .E3(out_1_tb_exp)); > > /* Modulul testat */ > E3_Adder DUT(.in_1(in_1_tb), .in_2(in_2_tb), .out_1(out_1_tb_actual)); > > initial begin > /* parametrii configurabili */ > DISPLAY_ALL = 1'b1; > DISPLAY_ONLY_FAILED = 1'b1; > MAX_VAL_in1 = 11'd500; > MAX_VAL_in2 = 11'd500; > /* ======================== */ > n_tests_total = (MAX_VAL_in1 + 1) * (MAX_VAL_in2 + 1); > n_tests_passed = 0; > if(MAX_VAL_in1 > 999 || MAX_VAL_in2 > 999) begin > $display("[WARNING] Testul nu va functiona cum trebuie! Valorile maxime NU trebuie sa fie mai mari de 999"); > end > for(test_input_1 = 0; test_input_1 <= MAX_VAL_in1; test_input_1 = test_input_1 + 1) begin > for(test_input_2 = 0; test_input_2 <= MAX_VAL_in2; test_input_2 = test_input_2 + 1) begin > test_output_1 = test_input_1 + test_input_2; > #1; > $display("Test nr: %d", test_input_1 * (MAX_VAL_in2 + 1) + test_input_2 + 1); > if(DISPLAY_ALL == 1'b1) begin > $display("Pentru urmatoarele intrari:\nin_1(decimal) = %d, in_1(E3) = %b \nin_2(decimal) = %d, in_2(E3) = %b \n", test_input_1, in_1_tb, test_input_2, in_2_tb); > $display("Rezultatul asteptat: out_1(decimal) = %d, out_1(E3) = %b", test_output_1, out_1_tb_exp); > $display("Rezultatul obtinut: out_1(E3) = %b", out_1_tb_actual); > end > if(out_1_tb_exp == out_1_tb_actual) begin > if(DISPLAY_ONLY_FAILED == 0) begin > $display("Testul este PASSED"); > end > n_tests_passed = n_tests_passed + 1; > end > else begin > $display("Testul este FAILED"); > $display("EXP E3: %b_%b_%b_%b =/= ACTUAL E3: %b_%b_%b_%b", out_1_tb_exp[15:12], out_1_tb_exp[11:8], out_1_tb_exp[7:4], out_1_tb_exp[3:0], out_1_tb_actual[15:12], out_1_tb_actual[11:8], out_1_tb_actual[7:4], out_1_tb_actual[3:0]); > end > $display("============================================================================================================="); > $display(""); > $display(""); > end > end > $display("Teste passed: %d / %d", n_tests_passed, n_tests_total); > end > endmodule Perhaps you are not aware this is a VHDL group, not Verilog. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:37 2024 X-Received: by 2002:ac8:4a1a:0:b0:3a6:a61e:8c01 with SMTP id x26-20020ac84a1a000000b003a6a61e8c01mr20145749qtq.214.1671305647780; Sat, 17 Dec 2022 11:34:07 -0800 (PST) X-Received: by 2002:a0c:fe66:0:b0:4b1:8a08:ac8e with SMTP id b6-20020a0cfe66000000b004b18a08ac8emr70268684qvv.53.1671305647610; Sat, 17 Dec 2022 11:34:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!border-1.nntp.ord.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Dec 2022 11:34:07 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:19cf:3efe:407:4fc5; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:19cf:3efe:407:4fc5 References: <6720be25-79b8-4136-8ffb-336b2eeefd5cn@googlegroups.com> <0b9d660e-36d6-4541-a772-54688d7ffcadn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Disabled generate gives compile error in Modelsim From: KJ Injection-Date: Sat, 17 Dec 2022 19:34:07 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 173 Xref: reader01.eternal-september.org comp.lang.vhdl:9892 On Wednesday, December 14, 2022 at 7:08:35 AM UTC-5, Stef wrote: > On 2022-12-14 KJ wrote in comp.lang.vhdl:=20 > > On Monday, December 12, 2022 at 4:26:46 AM UTC-5, Stef wrote:=20 > >> On 2022-12-11 KJ wrote in comp.lang.vhdl:=20 > >> > On Friday, December 9, 2022 at 6:20:14 AM UTC-5, Stef wrote:=20 > >=20 > > This doesn't make any sense. Is gentest connected to an input or an out= put of the PLL block? Whichever it is, gentest should be the opposite. This= is pretty basic, you connect inputs to outputs and vice versa. You don't c= onnect outputs together, you don't connect inputs. Pretty simple.=20 > > > In the design I inherited the PLL pin is a package pin and declared as=20 > inout. Why this was done, I do not know. So two inouts are connected=20 > together. And yes, I am aware that you don't connect outputs or inputs=20 > together (I am and electronics engineer). I will see if it can be changed= =20 > to an input to get rid of this problem. The place to look is in the documentation for the PLL, not in the VHDL code= . If the PLL documentation says that there are times when the pin is drive= n externally and other times that it is producing an output then it should = be described in VHDL as an inout. I doubt that to actually be the case bas= ed on what you've described so far. However, if it is truly a bi-direction= al signal, then that same PLL documentation will also describe the conditio= ns under which the PLL uses the pin as an input and the times it is an outp= ut. VHDL is a description of hardware, it is not the place one should go t= o as the definition of how the signal works. If the documentation says the pin is an output, then it is. If the VHDL sa= ys it is an inout, the VHDL is not correctly describing the PLL which means= the VHDL is wrong and should be corrected. > Aparently the PLL could not be simulated, so the clock came directly=20 > from the test bench. So some switch between testbench and pll clock must= =20 > be made between simulation and hardware generation. Probably not the=20 > best solution, as you say. But this is how I got it. And I try to=20 > understand why they did this before changing everything. Not wanting to make changes before understanding is a good approach. But n= ow I think we're finally getting to the nuts and bolts of the problem you'r= e actually looking at which is that there is no simulation model for the PL= L, correct? What you should then be doing is creating an if/generate aroun= d the PLL itself, not in some separate entity which is how it appears that = you are currently doing it. So in the FPGA design there is someplace where you are instantiating a comp= onent that is the PLL. All FPGA PLLs will have an input clock and produce = output clocks and will have multiple parameters to configure it. The insta= ntiation then will look something like this... MyPll : ThePll(InputClock, OutputClock, ...); So, if you really don't have a simulation model for the PLL you would modif= y this single instantiation to be the following. Note that what is being s= witched between based on this_is_a_simulation will be in the same entity/ar= chitecture. What you originally posted had the process that generated the = clock in one entity (the testbench). You don't really show where the insta= ntiation of the PLL is located, but I'm assuming it is in gentest which I'm= guessing is the FPGA design. Regardless though, this is how you structure= things in the VHDL code that are to be 'switched' out based on some simula= tion parameter. The thing that is receiving the PLL's OutputClock signal i= s not modified at all. In particular, there is no need to add code to driv= e some sigio signal under some conditions. Also note that for the simulation part, I've simply copied the code you pos= ted from the testbench just renaming the 'clk' signal to be the same name a= s the clock signal output from the PLL. PLLs also tend to have an output t= hat says when the PLL has locked on to the input and the output clock is no= w valid. If you're using such a signal (or other PLL output signals), you = would connect them to the PLL component in the rtlblk for the MyPll but the= n also generate logic in the simblk to create that output. Maybe it's some= thing like "locked <=3D '0', '1' after 1 us;" simblk : if this_is_a_simulation =3D true generate process begin OutputClock <=3D '0'; wait for 10ns; OutputClock <=3D '1'; wait for 10ns; end process; -- Add code for any other PLL outputs that you're using here Having said all that, you might want to double check your FPGA tools. Typi= cally there is a simulation model of the PLL. In that case you wouldn't ma= ke any changes to the source code of the FPGA design as described above. I= nstead all you need to do is add the simulation model VHDL file to the simu= lation project. That would be the best approach since it gets you the corr= ect simulation model as opposed to something that is cobbled together. Whi= ch software are you using to build the FPGA design? I know Altera (now Int= el) does create PLL simulation models. Haven't used any others in quite a = while. > >=20 > > The problem is that you are thinking that a real design would connect t= wo outputs together. It has nothing to do with VHDL at all.=20 > > > No I do not think that, what makes you believe I do? Because you added code in gentest to explicitly drive a signal that is alre= ady being driven by the testbench. > The syntax in itself is correct, but assigning a value to an input is=20 > not. So I would not expect an error on that code, as do you, I read in=20 > the above. However when I compile this in Modelsim: > rtlblk : if this_is_a_simulation =3D false generate=20 > sigio <=3D '1';=20 > sigout <=3D '1';=20 > end generate; > With this_is_a_simulation set to true and sigio declared as in, I get=20 > the following error=20 >=20 > -- Compiling architecture behav of gentest=20 > ** Error: ../gentest.vhd(19): Cannot drive signal 'sigio' of mode IN.=20 >=20 > This is not what I expect, why is the assignment not ignored?=20 >=20 Because a VHDL generate statement is not like a C pre-processor where it ig= nores entire blocks of code. For example, in C you can have the following = which will compile just fine and not produce any problems #if false alkljdfljk #endif The equivalent in VHDL would be MyGenerate : if false alkljdfljk end generate VHDL will flag 'alkljdfljk' as an error because it analyzes all of the code= , even if the conditions imply that the code will never be used. In your c= ase, the error was that you tried to assign a value to an input. You may choose to see this as "Why the heck are you complaining about code = that will not be used?" or choose to see it as making sure that all of the = code, whether it will be used or not, is valid code. In this case, it may = be trivial, but consider if you had several if/generate statements controll= ed by various parameters. Would you really want to have to compile all of = the possible parameter settings in order to know that every possible combin= ation of parameters compiles correctly? What VHDL is doing is validating t= hat every possible if/generate will in fact compile correctly with a single= compile.=20 > This is the core of my original question. What is the expected behaviour= =20 > when such generate blocks are disabled and contain incorrect code? I think I've answered the question here. Hopefully that is the case. If n= ot, chime back in. > > If you want the compiler itself to help you out some more, change all y= our usages of 'std_logic' to 'std_ulogic' in gentest as well as the testben= ch. Then the compilation will fail because signals of type 'std_ulogic' can= have only one driver. You won't even be able to start the simulation until= you fix the error. Use of std_ulogic rather than std_logic finds the desig= n errors that you are creating right at compile time and gives you all the = information about where the problem is located in the code. Using std_logic= only in situations where their truly can be multiple drivers such as some = shared bus like the data bus between a processor and memory. In all other c= ases, use std_ulogic. FPGAs do not support multiple driver designs for any = internal signal. > No, FPGAa don't have internal tri-state signals. Changing to std_ulogic= =20 > sounds like a good idea. Is this what you normally use for internal logic= ?=20 >=20 Yes, I use std_ulogic for all signals, testbench and design, that have a si= ngle driver in 'real life'. Bi-directional interfaces, such as that to an = external memory, are the only std_logic signals. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:37 2024 Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Disabled generate gives compile error in Modelsim References: <6720be25-79b8-4136-8ffb-336b2eeefd5cn@googlegroups.com> <0b9d660e-36d6-4541-a772-54688d7ffcadn@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/1.0.3 (Linux) Message-ID: Organization: Newsxs Date: Tue, 20 Dec 2022 10:37:55 +0100 Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!news.uzoreto.com!feeder.usenetexpress.com!tr1.eu1.usenetexpress.com!94.232.112.245.MISMATCH!feed.abavia.com!abe005.abavia.com!abp002.abavia.com!news.newsxs.nl!not-for-mail Lines: 161 Injection-Date: Tue, 20 Dec 2022 10:37:55 +0100 Injection-Info: news.newsxs.nl; mail-complaints-to="abuse@newsxs.nl" Xref: reader01.eternal-september.org comp.lang.vhdl:9893 On 2022-12-17 KJ wrote in comp.lang.vhdl: > On Wednesday, December 14, 2022 at 7:08:35 AM UTC-5, Stef wrote: >> On 2022-12-14 KJ wrote in comp.lang.vhdl: >> > On Monday, December 12, 2022 at 4:26:46 AM UTC-5, Stef wrote: >> >> On 2022-12-11 KJ wrote in comp.lang.vhdl: >> >> > On Friday, December 9, 2022 at 6:20:14 AM UTC-5, Stef wrote: > >> > >> > This doesn't make any sense. Is gentest connected to an input or an output of the PLL block? Whichever it is, gentest should be the opposite. This is pretty basic, you connect inputs to outputs and vice versa. You don't connect outputs together, you don't connect inputs. Pretty simple. >> > >> In the design I inherited the PLL pin is a package pin and declared as >> inout. Why this was done, I do not know. So two inouts are connected >> together. And yes, I am aware that you don't connect outputs or inputs >> together (I am and electronics engineer). I will see if it can be changed >> to an input to get rid of this problem. > > The place to look is in the documentation for the PLL, not in the VHDL code. If the PLL documentation says that there are times when the pin is driven externally and other times that it is producing an output then it should be described in VHDL as an inout. I doubt that to actually be the case based on what you've described so far. However, if it is truly a bi-directional signal, then that same PLL documentation will also describe the conditions under which the PLL uses the pin as an input and the times it is an output. VHDL is a description of hardware, it is not the place one should go to as the definition of how the signal works. > > If the documentation says the pin is an output, then it is. If the VHDL says it is an inout, the VHDL is not correctly describing the PLL which means the VHDL is wrong and should be corrected. That was my initial thought as well, but the documentation is not very clear on this subject: PACKAGEPIN: PLL REFERENCE CLOCK pin that serves as the input to the SB_PLL40_PAD primitive. "serves as an input" is not saying explicitely that it is an 'in'. Could be. The part is a Lattice iCE40 and the pll entity is created by the PLL configurator in the iCEcube2 tool. If I re-do the configuration, I get the exact same PLL entity, with the 'inout' PACKAGEPIN as input clock to the PLL. > >> Aparently the PLL could not be simulated, so the clock came directly >> from the test bench. So some switch between testbench and pll clock must >> be made between simulation and hardware generation. Probably not the >> best solution, as you say. But this is how I got it. And I try to >> understand why they did this before changing everything. > > Not wanting to make changes before understanding is a good approach. But now I think we're finally getting to the nuts and bolts of the problem you're actually looking at which is that there is no simulation model for the PLL, correct? What you should then be doing is creating an if/generate around the PLL itself, not in some separate entity which is how it appears that you are currently doing it. > I have not searched for a simulation model. I was first trying to get the package I got to work, and that does not include the PLL model. The iCEcube2 tool creates a wrapper entity for the PLL and this wrapper entity was instantiated in the top level. The if/generate was indeed in the top level, acting on the wrapper, not on the PLL itself. > So in the FPGA design there is someplace where you are instantiating a component that is the PLL. All FPGA PLLs will have an input clock and produce output clocks and will have multiple parameters to configure it. The instantiation then will look something like this... > > MyPll : ThePll(InputClock, OutputClock, ...); > > So, if you really don't have a simulation model for the PLL you would modify this single instantiation to be the following. Note that what is being switched between based on this_is_a_simulation will be in the same entity/architecture. What you originally posted had the process that generated the clock in one entity (the testbench). You don't really show where the instantiation of the PLL is located, but I'm assuming it is in gentest which I'm guessing is the FPGA design. Regardless though, this is how you structure things in the VHDL code that are to be 'switched' out based on some simulation parameter. The thing that is receiving the PLL's OutputClock signal is not modified at all. In particular, there is no need to add code to drive some sigio signal under some conditions. > Yes, the simulated clock is generated in the testbench and connected to the input that in real life is the input for the PLL input clock. in gentest, the PLL is in 'rtlblk' with its output connected to sigout. In simulation the external clock is assigned directly to sigout in 'simblk'. > Also note that for the simulation part, I've simply copied the code you posted from the testbench just renaming the 'clk' signal to be the same name as the clock signal output from the PLL. PLLs also tend to have an output that says when the PLL has locked on to the input and the output clock is now valid. If you're using such a signal (or other PLL output signals), you would connect them to the PLL component in the rtlblk for the MyPll but then also generate logic in the simblk to create that output. Maybe it's something like "locked <= '0', '1' after 1 us;" > > simblk : if this_is_a_simulation = true generate > process > begin > OutputClock <= '0'; > wait for 10ns; > OutputClock <= '1'; > wait for 10ns; > end process; > -- Add code for any other PLL outputs that you're using here > > Having said all that, you might want to double check your FPGA tools. Typically there is a simulation model of the PLL. In that case you wouldn't make any changes to the source code of the FPGA design as described above. Instead all you need to do is add the simulation model VHDL file to the simulation project. That would be the best approach since it gets you the correct simulation model as opposed to something that is cobbled together. Which software are you using to build the FPGA design? I know Altera (now Intel) does create PLL simulation models. Haven't used any others in quite a while. > It is lattice iCEcube2. I will look into this when I need to make more extensive modifications to the device. >> > >> > The problem is that you are thinking that a real design would connect two outputs together. It has nothing to do with VHDL at all. >> > >> No I do not think that, what makes you believe I do? > > Because you added code in gentest to explicitly drive a signal that is already being driven by the testbench. > Ok, this is where the problem starts. I was expecting the 'rtlblk' to be ignored in simulation, so there would still be a single driver. >> The syntax in itself is correct, but assigning a value to an input is >> not. So I would not expect an error on that code, as do you, I read in >> the above. However when I compile this in Modelsim: >> rtlblk : if this_is_a_simulation = false generate >> sigio <= '1'; >> sigout <= '1'; >> end generate; >> With this_is_a_simulation set to true and sigio declared as in, I get >> the following error >> >> -- Compiling architecture behav of gentest >> ** Error: ../gentest.vhd(19): Cannot drive signal 'sigio' of mode IN. >> >> This is not what I expect, why is the assignment not ignored? >> > Because a VHDL generate statement is not like a C pre-processor where it ignores entire blocks of code. For example, in C you can have the following which will compile just fine and not produce any problems > > #if false > alkljdfljk > #endif As I program more C than VHDL, this was indeed what I was expecting. > The equivalent in VHDL would be > MyGenerate : if false > alkljdfljk > end generate > > VHDL will flag 'alkljdfljk' as an error because it analyzes all of the code, even if the conditions imply that the code will never be used. In your case, the error was that you tried to assign a value to an input. > In your previous answer you said, that the compiler checks validity of the unused code anyway, but only for correct syntax. So an error for "alkljdfljk", but not for "sigio <= '1';", contrary to what I observed in Modelsim. This what confused me and that is why I posted the exact error description. > You may choose to see this as "Why the heck are you complaining about code that will not be used?" or choose to see it as making sure that all of the code, whether it will be used or not, is valid code. In this case, it may be trivial, but consider if you had several if/generate statements controlled by various parameters. Would you really want to have to compile all of the possible parameter settings in order to know that every possible combination of parameters compiles correctly? What VHDL is doing is validating that every possible if/generate will in fact compile correctly with a single compile. > Okay, I think we are on the same page now. VHDL checks all code as if it where used, even when not used. >> This is the core of my original question. What is the expected behaviour >> when such generate blocks are disabled and contain incorrect code? > > I think I've answered the question here. Hopefully that is the case. If not, chime back in. > Yes, this is answered now. And I now believe the original construct probably never worked in the state I got it in. :-( >> > If you want the compiler itself to help you out some more, change all your usages of 'std_logic' to 'std_ulogic' in gentest as well as the testbench. Then the compilation will fail because signals of type 'std_ulogic' can have only one driver. You won't even be able to start the simulation until you fix the error. Use of std_ulogic rather than std_logic finds the design errors that you are creating right at compile time and gives you all the information about where the problem is located in the code. Using std_logic only in situations where their truly can be multiple drivers such as some shared bus like the data bus between a processor and memory. In all other cases, use std_ulogic. FPGAs do not support multiple driver designs for any internal signal. >> No, FPGAa don't have internal tri-state signals. Changing to std_ulogic >> sounds like a good idea. Is this what you normally use for internal logic? >> > Yes, I use std_ulogic for all signals, testbench and design, that have a single driver in 'real life'. Bi-directional interfaces, such as that to an external memory, are the only std_logic signals. > > Kevin Jennings -- Stef What's the matter with the world? Why, there ain't but one thing wrong with every one of us -- and that's "selfishness." -- The Best of Will Rogers From newsfish@newsfish Thu Aug 1 00:46:37 2024 X-Received: by 2002:ad4:4814:0:b0:534:7177:cd12 with SMTP id qd20-20020ad44814000000b005347177cd12mr383792qvb.25.1674076091423; Wed, 18 Jan 2023 13:08:11 -0800 (PST) X-Received: by 2002:a25:1fd4:0:b0:7d4:712e:2852 with SMTP id f203-20020a251fd4000000b007d4712e2852mr962093ybf.628.1674076091197; Wed, 18 Jan 2023 13:08:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!border-1.nntp.ord.giganews.com!border-2.nntp.ord.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Jan 2023 13:08:10 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=194.193.135.13; posting-account=p-1XpwoAAAAU33dCdagwyPSBDsbmmd0A NNTP-Posting-Host: 194.193.135.13 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <474ea2c6-4555-4b3c-9fcd-e9985866ba52n@googlegroups.com> Subject: Best approach using GHDL to wrap clocked VHDL From: Damien Towning Injection-Date: Wed, 18 Jan 2023 21:08:11 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 9 Xref: reader01.eternal-september.org comp.lang.vhdl:9894 I have a VHDL project. Is a RISC-V Bonfire in an Efinity T-35 FPGA. The boa= rd the T-35 is in has external clock on a GPIO pin that is driving it. Runs= on the FPGA happily. Now I have successfully built my project using GHDL-G= CC. Next I have started looking at wrapping it and am reading through the d= ocumentation. But in general what would be best practice for binding the SY= SCLK in my VHDL code to some external function to drive it? I have been loo= king at the customc example where the VHDL calls C functions. Can I call a = C function that runs the clock and return a clock step that way? Or have I = got this the wrong way around and the C code should reach in to the running= object and clock it that way? From newsfish@newsfish Thu Aug 1 00:46:38 2024 X-Received: by 2002:a05:622a:5c88:b0:3b4:2946:c083 with SMTP id ge8-20020a05622a5c8800b003b42946c083mr488259qtb.457.1674409120130; Sun, 22 Jan 2023 09:38:40 -0800 (PST) X-Received: by 2002:a81:46:0:b0:3ce:df72:19d1 with SMTP id 67-20020a810046000000b003cedf7219d1mr2643262ywa.264.1674409119812; Sun, 22 Jan 2023 09:38:39 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!news.uzoreto.com!newsreader4.netcologne.de!news.netcologne.de!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 22 Jan 2023 09:38:39 -0800 (PST) In-Reply-To: <474ea2c6-4555-4b3c-9fcd-e9985866ba52n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:8ccd:f697:31e4:4f7f; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:8ccd:f697:31e4:4f7f References: <474ea2c6-4555-4b3c-9fcd-e9985866ba52n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Best approach using GHDL to wrap clocked VHDL From: KJ Injection-Date: Sun, 22 Jan 2023 17:38:40 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2932 Xref: reader01.eternal-september.org comp.lang.vhdl:9895 On Wednesday, January 18, 2023 at 4:08:13 PM UTC-5, connoll...@gmail.com wr= ote: > I have a VHDL project. Is a RISC-V Bonfire in an Efinity T-35 FPGA. The b= oard the T-35 is in has external clock on a GPIO pin that is driving it. Ru= ns on the FPGA happily. Now I have successfully built my project using GHDL= -GCC. Next I have started looking at wrapping it and am reading through the= documentation. But in general what would be best practice for binding the = SYSCLK in my VHDL code to some external function to drive it? I have been l= ooking at the customc example where the VHDL calls C functions. Can I call = a C function that runs the clock and return a clock step that way? Or have = I got this the wrong way around and the C code should reach in to the runni= ng object and clock it that way? I've read this several times and I have no idea what you are trying to do. = An example,=20 > Next I have started looking at wrapping it=20 What is "it"? Are you trying to do something on the board? In simulation?= Who knows... But since this is a VHDL group, I would suggest that if you are trying to "= wrap" your FPGA design for simulation, then the best approach is to write a= testbench for your FPGA design. This involves writing VHDL that models al= l of the inputs to the FPGA and monitors all of the outputs. You would ins= tantiate that FPGA design in the testbench. There would be no reason to us= e C to do any of this. I would go on but like I said, I have no idea what = you're really trying to do, so you need to explain that first. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:38 2024 X-Received: by 2002:a05:620a:1354:b0:706:7088:1fe9 with SMTP id c20-20020a05620a135400b0070670881fe9mr1790066qkl.11.1674588860473; Tue, 24 Jan 2023 11:34:20 -0800 (PST) X-Received: by 2002:a25:3749:0:b0:80b:6fc1:8b32 with SMTP id e70-20020a253749000000b0080b6fc18b32mr272559yba.126.1674588860212; Tue, 24 Jan 2023 11:34:20 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Jan 2023 11:34:19 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:a4d9:72db:d0f8:ddad; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:a4d9:72db:d0f8:ddad User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> Subject: How does a HEAD pointer end up pointing to the first node in a linked list? From: =?UTF-8?B?QSDigJxBc2h2aW7igJ0=?= Injection-Date: Tue, 24 Jan 2023 19:34:20 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2674 Xref: reader01.eternal-september.org comp.lang.vhdl:9896 The following code is snippet from a FIFO write/read model. The code works.= I am only showing the write procedure. My questions are noted after the co= de snippet. type Item; --Incomplete declaration type Ptr is access Item; type Item is record NextItem : Ptr; Data : integer; end record; variable Head : Ptr; procedure FIFO_WRITE(Data : in integer) is variable NewItem : Ptr; variable Node : Ptr; begin NewItem :=3D new Item'(NextItem =3D> Null, Data =3D> Data); --allocate memory - point to where the Item is stored. if Head =3D null then --if the list is empty Head :=3D NewItem; --claim the memory and initialise Root/Head to the claim= ed memory. else Node :=3D Head; --start with Root node at the beginning of the list while Node.NextItem /=3D null loop --Go through linked list and search for --last/tail node. Node :=3D Node.NextItem; end loop; Node.NextItem :=3D NewItem; --store NewItem(Item) at the tail end of the li= st. end if; end; I have a fundamental question. I have declared the variable HEAD to be of t= ype Ptr. Then I check to see if HEAD =3D NULL. So, all I have done is decla= re the variable HEAD. How does that end up pointing to the first node in th= e list? How does the HEAD =3D NULL work? Is it that when you declare HEAD, = that the NextItem of 'record' Item end up pointing to NULL by default? I ha= ven't allocated memory to HEAD. Nothing. Just the declaration causes it to = point to the first node in the list? Don't understand that. Thanks. From newsfish@newsfish Thu Aug 1 00:46:38 2024 X-Received: by 2002:a37:2e43:0:b0:702:1fee:571d with SMTP id u64-20020a372e43000000b007021fee571dmr1173104qkh.253.1674589700118; Tue, 24 Jan 2023 11:48:20 -0800 (PST) X-Received: by 2002:a25:7e06:0:b0:7b8:6d00:ef1e with SMTP id z6-20020a257e06000000b007b86d00ef1emr3733694ybc.342.1674589699748; Tue, 24 Jan 2023 11:48:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Jan 2023 11:48:19 -0800 (PST) In-Reply-To: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=65.207.89.54; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 65.207.89.54 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: "gnuarm.del...@gmail.com" Injection-Date: Tue, 24 Jan 2023 19:48:20 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3434 Xref: reader01.eternal-september.org comp.lang.vhdl:9897 On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@gmail.com wrote= : > The following code is snippet from a FIFO write/read model. The code work= s. I am only showing the write procedure. My questions are noted after the = code snippet.=20 >=20 >=20 > type Item; --Incomplete declaration=20 > type Ptr is access Item;=20 > type Item is record=20 > NextItem : Ptr;=20 > Data : integer;=20 > end record;=20 > variable Head : Ptr;=20 > procedure FIFO_WRITE(Data : in integer) is=20 > variable NewItem : Ptr;=20 > variable Node : Ptr;=20 > begin=20 > NewItem :=3D new Item'(NextItem =3D> Null, Data =3D> Data);=20 > --allocate memory - point to where the Item is stored.=20 > if Head =3D null then --if the list is empty=20 > Head :=3D NewItem; --claim the memory and initialise Root/Head to the cla= imed memory.=20 > else=20 > Node :=3D Head; --start with Root node at the beginning of the list=20 > while Node.NextItem /=3D null loop --Go through linked list and search fo= r=20 > --last/tail node.=20 > Node :=3D Node.NextItem;=20 > end loop;=20 > Node.NextItem :=3D NewItem; --store NewItem(Item) at the tail end of the = list.=20 > end if;=20 > end;=20 >=20 >=20 > I have a fundamental question. I have declared the variable HEAD to be of= type Ptr. Then I check to see if HEAD =3D NULL. So, all I have done is dec= lare the variable HEAD. How does that end up pointing to the first node in = the list? How does the HEAD =3D NULL work? Is it that when you declare HEAD= , that the NextItem of 'record' Item end up pointing to NULL by default? I = haven't allocated memory to HEAD. Nothing. Just the declaration causes it t= o point to the first node in the list? Don't understand that.=20 >=20 > Thanks. It's been a long time since I've used pointers in VHDL. But I believe NULL= is used to indicate a pointer has no valid value. I don't think it is poi= nting anywhere. In your case, it indicates it has not been assigned a valu= e. No?=20 https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/Null.htm=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:39 2024 X-Received: by 2002:a05:6214:3483:b0:534:b2a0:5ee1 with SMTP id mr3-20020a056214348300b00534b2a05ee1mr1578802qvb.69.1674668187661; Wed, 25 Jan 2023 09:36:27 -0800 (PST) X-Received: by 2002:a0d:cc01:0:b0:506:a79d:e08 with SMTP id o1-20020a0dcc01000000b00506a79d0e08mr296099ywd.154.1674668187276; Wed, 25 Jan 2023 09:36:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!border-1.nntp.ord.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Jan 2023 09:36:26 -0800 (PST) In-Reply-To: <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:a4d9:72db:d0f8:ddad; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:a4d9:72db:d0f8:ddad References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: =?UTF-8?B?QSDigJxBc2h2aW7igJ0=?= Injection-Date: Wed, 25 Jan 2023 17:36:27 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 66 Xref: reader01.eternal-september.org comp.lang.vhdl:9898 On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del...@gmail.com = wrote: > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@gmail.com wro= te:=20 > > The following code is snippet from a FIFO write/read model. The code wo= rks. I am only showing the write procedure. My questions are noted after th= e code snippet.=20 > >=20 > >=20 > > type Item; --Incomplete declaration=20 > > type Ptr is access Item;=20 > > type Item is record=20 > > NextItem : Ptr;=20 > > Data : integer;=20 > > end record;=20 > > variable Head : Ptr;=20 > > procedure FIFO_WRITE(Data : in integer) is=20 > > variable NewItem : Ptr;=20 > > variable Node : Ptr;=20 > > begin=20 > > NewItem :=3D new Item'(NextItem =3D> Null, Data =3D> Data);=20 > > --allocate memory - point to where the Item is stored.=20 > > if Head =3D null then --if the list is empty=20 > > Head :=3D NewItem; --claim the memory and initialise Root/Head to the c= laimed memory.=20 > > else=20 > > Node :=3D Head; --start with Root node at the beginning of the list=20 > > while Node.NextItem /=3D null loop --Go through linked list and search = for=20 > > --last/tail node.=20 > > Node :=3D Node.NextItem;=20 > > end loop;=20 > > Node.NextItem :=3D NewItem; --store NewItem(Item) at the tail end of th= e list.=20 > > end if;=20 > > end;=20 > >=20 > >=20 > > I have a fundamental question. I have declared the variable HEAD to be = of type Ptr. Then I check to see if HEAD =3D NULL. So, all I have done is d= eclare the variable HEAD. How does that end up pointing to the first node i= n the list? How does the HEAD =3D NULL work? Is it that when you declare HE= AD, that the NextItem of 'record' Item end up pointing to NULL by default? = I haven't allocated memory to HEAD. Nothing. Just the declaration causes it= to point to the first node in the list? Don't understand that.=20 > >=20 > > Thanks. > It's been a long time since I've used pointers in VHDL. But I believe NUL= L is used to indicate a pointer has no valid value. I don't think it is poi= nting anywhere. In your case, it indicates it has not been assigned a value= . No?=20 >=20 > https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/Null.htm=20 >=20 > --=20 >=20 > Rick C.=20 >=20 > - Get 1,000 miles of free Supercharging=20 > - Tesla referral code - https://ts.la/richard11209 Rick, Thanks. I understand what assignment to NULL means. My question is ho= w does HEAD pointer work? All we have done is declare HEAD as a variable. H= ow does it end up pointing to the first node in the list? We haven't alloca= ted any memory to HEAD (i.e. we haven't made the assignment HEAD :=3D new i= tem'(Nextitem =3D> NULL, data=3Ddata);). So, how does HEAD know where to po= int to? From newsfish@newsfish Thu Aug 1 00:46:39 2024 X-Received: by 2002:a05:620a:60f6:b0:702:4a94:48e7 with SMTP id dy54-20020a05620a60f600b007024a9448e7mr1382420qkb.578.1674703516808; Wed, 25 Jan 2023 19:25:16 -0800 (PST) X-Received: by 2002:a25:7e06:0:b0:7b8:6d00:ef1e with SMTP id z6-20020a257e06000000b007b86d00ef1emr4389321ybc.342.1674703516562; Wed, 25 Jan 2023 19:25:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Jan 2023 19:25:16 -0800 (PST) In-Reply-To: <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=192.254.97.42; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 192.254.97.42 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: "gnuarm.del...@gmail.com" Injection-Date: Thu, 26 Jan 2023 03:25:16 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4545 Xref: reader01.eternal-september.org comp.lang.vhdl:9899 On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...@gmail.com wro= te: > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del...@gmail.co= m wrote:=20 > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@gmail.com w= rote:=20 > > > The following code is snippet from a FIFO write/read model. The code = works. I am only showing the write procedure. My questions are noted after = the code snippet.=20 > > >=20 > > >=20 > > > type Item; --Incomplete declaration=20 > > > type Ptr is access Item;=20 > > > type Item is record=20 > > > NextItem : Ptr;=20 > > > Data : integer;=20 > > > end record;=20 > > > variable Head : Ptr;=20 > > > procedure FIFO_WRITE(Data : in integer) is=20 > > > variable NewItem : Ptr;=20 > > > variable Node : Ptr;=20 > > > begin=20 > > > NewItem :=3D new Item'(NextItem =3D> Null, Data =3D> Data);=20 > > > --allocate memory - point to where the Item is stored.=20 > > > if Head =3D null then --if the list is empty=20 > > > Head :=3D NewItem; --claim the memory and initialise Root/Head to the= claimed memory.=20 > > > else=20 > > > Node :=3D Head; --start with Root node at the beginning of the list= =20 > > > while Node.NextItem /=3D null loop --Go through linked list and searc= h for=20 > > > --last/tail node.=20 > > > Node :=3D Node.NextItem;=20 > > > end loop;=20 > > > Node.NextItem :=3D NewItem; --store NewItem(Item) at the tail end of = the list.=20 > > > end if;=20 > > > end;=20 > > >=20 > > >=20 > > > I have a fundamental question. I have declared the variable HEAD to b= e of type Ptr. Then I check to see if HEAD =3D NULL. So, all I have done is= declare the variable HEAD. How does that end up pointing to the first node= in the list? How does the HEAD =3D NULL work? Is it that when you declare = HEAD, that the NextItem of 'record' Item end up pointing to NULL by default= ? I haven't allocated memory to HEAD. Nothing. Just the declaration causes = it to point to the first node in the list? Don't understand that.=20 > > >=20 > > > Thanks.=20 > > It's been a long time since I've used pointers in VHDL. But I believe N= ULL is used to indicate a pointer has no valid value. I don't think it is p= ointing anywhere. In your case, it indicates it has not been assigned a val= ue. No?=20 > >=20 > > https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/Null.htm=20 > >=20 > > --=20 > >=20 > > Rick C.=20 > >=20 > > - Get 1,000 miles of free Supercharging=20 > > - Tesla referral code - https://ts.la/richard11209 > Rick, Thanks. I understand what assignment to NULL means. My question is = how does HEAD pointer work? All we have done is declare HEAD as a variable.= How does it end up pointing to the first node in the list? We haven't allo= cated any memory to HEAD (i.e. we haven't made the assignment HEAD :=3D new= item'(Nextitem =3D> NULL, data=3Ddata);). So, how does HEAD know where to = point to? Maybe here? Head :=3D NewItem; --claim the memory and initialise Root/Head to the claim= ed memory.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:39 2024 X-Received: by 2002:a05:6214:2b86:b0:534:2577:ccda with SMTP id kr6-20020a0562142b8600b005342577ccdamr1820167qvb.32.1674753854644; Thu, 26 Jan 2023 09:24:14 -0800 (PST) X-Received: by 2002:a25:9cc5:0:b0:80b:6b1d:5b27 with SMTP id z5-20020a259cc5000000b0080b6b1d5b27mr1251557ybo.646.1674753854308; Thu, 26 Jan 2023 09:24:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!border-1.nntp.ord.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Jan 2023 09:24:14 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:e0c7:4136:9f85:fb27; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:e0c7:4136:9f85:fb27 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: =?UTF-8?B?QSDigJxBc2h2aW7igJ0=?= Injection-Date: Thu, 26 Jan 2023 17:24:14 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lines: 85 Xref: reader01.eternal-september.org comp.lang.vhdl:9900 On Wednesday, January 25, 2023 at 7:25:18 PM UTC-8, gnuarm.del...@gmail.com= wrote: > On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...@gmail.com w= rote:=20 > > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del...@gmail.= com wrote:=20 > > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@gmail.com= wrote:=20 > > > > The following code is snippet from a FIFO write/read model. The cod= e works. I am only showing the write procedure. My questions are noted afte= r the code snippet.=20 > > > >=20 > > > >=20 > > > > type Item; --Incomplete declaration=20 > > > > type Ptr is access Item;=20 > > > > type Item is record=20 > > > > NextItem : Ptr;=20 > > > > Data : integer;=20 > > > > end record;=20 > > > > variable Head : Ptr;=20 > > > > procedure FIFO_WRITE(Data : in integer) is=20 > > > > variable NewItem : Ptr;=20 > > > > variable Node : Ptr;=20 > > > > begin=20 > > > > NewItem :=3D new Item'(NextItem =3D> Null, Data =3D> Data);=20 > > > > --allocate memory - point to where the Item is stored.=20 > > > > if Head =3D null then --if the list is empty=20 > > > > Head :=3D NewItem; --claim the memory and initialise Root/Head to t= he claimed memory.=20 > > > > else=20 > > > > Node :=3D Head; --start with Root node at the beginning of the list= =20 > > > > while Node.NextItem /=3D null loop --Go through linked list and sea= rch for=20 > > > > --last/tail node.=20 > > > > Node :=3D Node.NextItem;=20 > > > > end loop;=20 > > > > Node.NextItem :=3D NewItem; --store NewItem(Item) at the tail end o= f the list.=20 > > > > end if;=20 > > > > end;=20 > > > >=20 > > > >=20 > > > > I have a fundamental question. I have declared the variable HEAD to= be of type Ptr. Then I check to see if HEAD =3D NULL. So, all I have done = is declare the variable HEAD. How does that end up pointing to the first no= de in the list? How does the HEAD =3D NULL work? Is it that when you declar= e HEAD, that the NextItem of 'record' Item end up pointing to NULL by defau= lt? I haven't allocated memory to HEAD. Nothing. Just the declaration cause= s it to point to the first node in the list? Don't understand that.=20 > > > >=20 > > > > Thanks.=20 > > > It's been a long time since I've used pointers in VHDL. But I believe= NULL is used to indicate a pointer has no valid value. I don't think it is= pointing anywhere. In your case, it indicates it has not been assigned a v= alue. No?=20 > > >=20 > > > https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/Null.htm=20 > > >=20 > > > --=20 > > >=20 > > > Rick C.=20 > > >=20 > > > - Get 1,000 miles of free Supercharging=20 > > > - Tesla referral code - https://ts.la/richard11209=20 > > Rick, Thanks. I understand what assignment to NULL means. My question i= s how does HEAD pointer work? All we have done is declare HEAD as a variabl= e. How does it end up pointing to the first node in the list? We haven't al= located any memory to HEAD (i.e. we haven't made the assignment HEAD :=3D n= ew item'(Nextitem =3D> NULL, data=3Ddata);). So, how does HEAD know where t= o point to? > Maybe here? > Head :=3D NewItem; --claim the memory and initialise Root/Head to the cla= imed memory. > --=20 >=20 > Rick C.=20 >=20 > + Get 1,000 miles of free Supercharging=20 > + Tesla referral code - https://ts.la/richard11209 Thanks Rick. But I am doing "if Head =3D NULL" first and -then- assigning = Head :=3D NewItem. So the question is how do we know that Head is pointing = to a node and that the node is null -before- assigning it new memory? To si= mplify the question "where does Head point to when it is first delcared as = "variable Head : Ptr". From newsfish@newsfish Thu Aug 1 00:46:39 2024 X-Received: by 2002:ac8:1413:0:b0:3a8:16a5:e226 with SMTP id k19-20020ac81413000000b003a816a5e226mr1445150qtj.253.1674778794238; Thu, 26 Jan 2023 16:19:54 -0800 (PST) X-Received: by 2002:a81:5553:0:b0:507:e5a9:989d with SMTP id j80-20020a815553000000b00507e5a9989dmr753931ywb.500.1674778793870; Thu, 26 Jan 2023 16:19:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!news.mixmin.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Jan 2023 16:19:53 -0800 (PST) In-Reply-To: <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=192.254.97.42; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 192.254.97.42 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: "gnuarm.del...@gmail.com" Injection-Date: Fri, 27 Jan 2023 00:19:54 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader01.eternal-september.org comp.lang.vhdl:9901 On Thursday, January 26, 2023 at 1:24:16 PM UTC-4, ashokm...@gmail.com wrot= e: > On Wednesday, January 25, 2023 at 7:25:18 PM UTC-8, gnuarm.del...@gmail.c= om wrote:=20 > > On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...@gmail.com= wrote:=20 > > > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del...@gmai= l.com wrote:=20 > > > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@gmail.c= om wrote:=20 > > > > > The following code is snippet from a FIFO write/read model. The c= ode works. I am only showing the write procedure. My questions are noted af= ter the code snippet.=20 > > > > >=20 > > > > >=20 > > > > > type Item; --Incomplete declaration=20 > > > > > type Ptr is access Item;=20 > > > > > type Item is record=20 > > > > > NextItem : Ptr;=20 > > > > > Data : integer;=20 > > > > > end record;=20 > > > > > variable Head : Ptr;=20 > > > > > procedure FIFO_WRITE(Data : in integer) is=20 > > > > > variable NewItem : Ptr;=20 > > > > > variable Node : Ptr;=20 > > > > > begin=20 > > > > > NewItem :=3D new Item'(NextItem =3D> Null, Data =3D> Data);=20 > > > > > --allocate memory - point to where the Item is stored.=20 > > > > > if Head =3D null then --if the list is empty=20 > > > > > Head :=3D NewItem; --claim the memory and initialise Root/Head to= the claimed memory.=20 > > > > > else=20 > > > > > Node :=3D Head; --start with Root node at the beginning of the li= st=20 > > > > > while Node.NextItem /=3D null loop --Go through linked list and s= earch for=20 > > > > > --last/tail node.=20 > > > > > Node :=3D Node.NextItem;=20 > > > > > end loop;=20 > > > > > Node.NextItem :=3D NewItem; --store NewItem(Item) at the tail end= of the list.=20 > > > > > end if;=20 > > > > > end;=20 > > > > >=20 > > > > >=20 > > > > > I have a fundamental question. I have declared the variable HEAD = to be of type Ptr. Then I check to see if HEAD =3D NULL. So, all I have don= e is declare the variable HEAD. How does that end up pointing to the first = node in the list? How does the HEAD =3D NULL work? Is it that when you decl= are HEAD, that the NextItem of 'record' Item end up pointing to NULL by def= ault? I haven't allocated memory to HEAD. Nothing. Just the declaration cau= ses it to point to the first node in the list? Don't understand that.=20 > > > > >=20 > > > > > Thanks.=20 > > > > It's been a long time since I've used pointers in VHDL. But I belie= ve NULL is used to indicate a pointer has no valid value. I don't think it = is pointing anywhere. In your case, it indicates it has not been assigned a= value. No?=20 > > > >=20 > > > > https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/Null.htm= =20 > > > >=20 > > > > --=20 > > > >=20 > > > > Rick C.=20 > > > >=20 > > > > - Get 1,000 miles of free Supercharging=20 > > > > - Tesla referral code - https://ts.la/richard11209=20 > > > Rick, Thanks. I understand what assignment to NULL means. My question= is how does HEAD pointer work? All we have done is declare HEAD as a varia= ble. How does it end up pointing to the first node in the list? We haven't = allocated any memory to HEAD (i.e. we haven't made the assignment HEAD :=3D= new item'(Nextitem =3D> NULL, data=3Ddata);). So, how does HEAD know where= to point to?=20 > > Maybe here?=20 > > Head :=3D NewItem; --claim the memory and initialise Root/Head to the c= laimed memory.=20 > > --=20 > >=20 > > Rick C.=20 > >=20 > > + Get 1,000 miles of free Supercharging=20 > > + Tesla referral code - https://ts.la/richard11209 > Thanks Rick. But I am doing "if Head =3D NULL" first and -then- assigning= Head :=3D NewItem. So the question is how do we know that Head is pointing= to a node and that the node is null -before- assigning it new memory? To s= implify the question "where does Head point to when it is first delcared as= "variable Head : Ptr". Sorry, there's still a miscommunication somewhere. From the web site I sen= t you a link for...=20 "The default value of an access type is null." https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/AccessType.htm I think they are saying it is set to NULL when created. Look at some code = and it is clear that is how it works.=20 This example seems to be for a stack, which is very similar to your FIFO li= st. The only difference is, that your code would add nodes to one end of t= he list, and remove them from the other (or copy the data through the list)= while the FIFO would add and remove the data from the same end. Oddly eno= ugh, this author decided to use the far end of the list as the working end.= I have no idea what impact that would have on operation. Are pointers an= d allocated structures synthesized? =20 https://vhdlwhiz.com/linked-list/ I don't think I've ever had a need to use pointers other than for strings w= hich were used in simulation to report info to the user or a file. I belie= ve a string is a pointer type, no?=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:40 2024 X-Received: by 2002:ad4:5991:0:b0:537:79b9:3ee4 with SMTP id ek17-20020ad45991000000b0053779b93ee4mr464489qvb.55.1674825198056; Fri, 27 Jan 2023 05:13:18 -0800 (PST) X-Received: by 2002:a25:c883:0:b0:733:6241:6b0b with SMTP id y125-20020a25c883000000b0073362416b0bmr3533251ybf.447.1674825197896; Fri, 27 Jan 2023 05:13:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Jan 2023 05:13:17 -0800 (PST) In-Reply-To: <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:65a2:cc86:7e90:d5c6; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:65a2:cc86:7e90:d5c6 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: KJ Injection-Date: Fri, 27 Jan 2023 13:13:18 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4007 Xref: reader01.eternal-september.org comp.lang.vhdl:9902 On Thursday, January 26, 2023 at 12:24:16 PM UTC-5, ashokm...@gmail.com wro= te: > On Wednesday, January 25, 2023 at 7:25:18 PM UTC-8, gnuarm.del...@gmail.c= om wrote:=20 > > On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...@gmail.com= wrote:=20 > > > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del...@gmai= l.com wrote:=20 > > > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@gmail.c= om wrote:=20 > Thanks Rick. But I am doing "if Head =3D NULL" first and -then- assigning= Head :=3D NewItem. So the question is how do we know that Head is pointing= to a node and that the node is null -before- assigning it new memory? To s= implify the question "where does Head point to when it is first delcared as= "variable Head : Ptr". The short answer to "where does Head point to when it is first delcared as = "variable Head : Ptr" is that it points to nothing at all. For the somewha= t longer answer, read on. When you first declare a variable that is of type access (i.e. your statem= ent "variable Head : Ptr;"), VHDL assigns the variable the 'value' null but= it is not pointing to anything at that time. This would be different than= in C/C++. For example, in C/C++ you can declare a pointer with "char *MyP= tr;". In this situation, MyPtr is not guaranteed to be pointing to anythin= g in particular. It is also not guaranteed to even be NULL. However, VHDL= does guarantee that a declared but not explicitly initialized variable (or= signal) will always have an initial value. For access type variables, thi= s is defined in section 5.4.1 of the VHDL standard (Access types - General)= . > For each access type, there is a literal null that has a null access valu= e designating no object at all. The null value of an access type is the def= ault initial value of the type Thus the VHDL standard's answer to your question is, as I stated, "designat= ing no object at all" meaning it doesn't 'point' to anything. Following that the standard goes into the other values that an access type = variable can take on. In the following sentence, an 'allocator' is somethi= ng that allocates memory, much like 'new' or 'malloc' in C/C++. > Other values of an access type are obtained by evaluation of a special op= eration of the type, called an allocator. Each such access value designates= an object of the subtype defined by the subtype indication of the access t= ype definition. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:40 2024 X-Received: by 2002:a05:622a:183:b0:3b1:c62b:c140 with SMTP id s3-20020a05622a018300b003b1c62bc140mr2015162qtw.313.1674828495017; Fri, 27 Jan 2023 06:08:15 -0800 (PST) X-Received: by 2002:a0d:d1c7:0:b0:368:e6b8:77f1 with SMTP id t190-20020a0dd1c7000000b00368e6b877f1mr3829781ywd.414.1674828494710; Fri, 27 Jan 2023 06:08:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Jan 2023 06:08:14 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=66.50.50.210; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 66.50.50.210 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: "gnuarm.del...@gmail.com" Injection-Date: Fri, 27 Jan 2023 14:08:15 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4830 Xref: reader01.eternal-september.org comp.lang.vhdl:9903 On Friday, January 27, 2023 at 9:13:19 AM UTC-4, KJ wrote: > On Thursday, January 26, 2023 at 12:24:16 PM UTC-5, ashokm...@gmail.com w= rote:=20 > > On Wednesday, January 25, 2023 at 7:25:18 PM UTC-8, gnuarm.del...@gmail= .com wrote:=20 > > > On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...@gmail.c= om wrote:=20 > > > > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del...@gm= ail.com wrote:=20 > > > > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@gmail= .com wrote:=20 >=20 > > Thanks Rick. But I am doing "if Head =3D NULL" first and -then- assigni= ng Head :=3D NewItem. So the question is how do we know that Head is pointi= ng to a node and that the node is null -before- assigning it new memory? To= simplify the question "where does Head point to when it is first delcared = as "variable Head : Ptr". > The short answer to "where does Head point to when it is first delcared a= s "variable Head : Ptr" is that it points to nothing at all. For the somewh= at longer answer, read on.=20 >=20 > When you first declare a variable that is of type access (i.e. your state= ment "variable Head : Ptr;"), VHDL assigns the variable the 'value' null bu= t it is not pointing to anything at that time. This would be different than= in C/C++. For example, in C/C++ you can declare a pointer with "char *MyPt= r;". In this situation, MyPtr is not guaranteed to be pointing to anything = in particular. It is also not guaranteed to even be NULL. However, VHDL doe= s guarantee that a declared but not explicitly initialized variable (or sig= nal) will always have an initial value. For access type variables, this is = defined in section 5.4.1 of the VHDL standard (Access types - General).=20 >=20 > > For each access type, there is a literal null that has a null access va= lue designating no object at all. The null value of an access type is the d= efault initial value of the type=20 >=20 > Thus the VHDL standard's answer to your question is, as I stated, "design= ating no object at all" meaning it doesn't 'point' to anything.=20 >=20 > Following that the standard goes into the other values that an access typ= e variable can take on. In the following sentence, an 'allocator' is someth= ing that allocates memory, much like 'new' or 'malloc' in C/C++.=20 >=20 > > Other values of an access type are obtained by evaluation of a special = operation of the type, called an allocator. Each such access value designat= es an object of the subtype defined by the subtype indication of the access= type definition.=20 >=20 > Kevin Jennings So is that the same as having the value NULL? Isn't NULL the indication of= pointing to nothing? =20 If it were uninitialized, it could have any value at all. You've not said = it is unitialized, and you have not said it contains NULL. "Pointing to no= thing" is not clear unless you mean it contains a NULL. You even say "VHDL= assigns the variable the 'value' null". So isn't that an adequate explana= tion rather than the much more wordy statement, "pointing to nothing"? Tha= t's the point of "null", it points to nothing.=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:40 2024 X-Received: by 2002:a05:620a:407:b0:702:4128:2891 with SMTP id 7-20020a05620a040700b0070241282891mr2289829qkp.146.1674832860688; Fri, 27 Jan 2023 07:21:00 -0800 (PST) X-Received: by 2002:a25:34cd:0:b0:80b:83b0:c87e with SMTP id b196-20020a2534cd000000b0080b83b0c87emr1158616yba.360.1674832860541; Fri, 27 Jan 2023 07:21:00 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Jan 2023 07:21:00 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:65a2:cc86:7e90:d5c6; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:65a2:cc86:7e90:d5c6 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77ec8bfe-8e72-4937-9179-dd78c84463b8n@googlegroups.com> Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: KJ Injection-Date: Fri, 27 Jan 2023 15:21:00 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4565 Xref: reader01.eternal-september.org comp.lang.vhdl:9904 On Friday, January 27, 2023 at 9:08:16 AM UTC-5, gnuarm.del...@gmail.com wr= ote: > On Friday, January 27, 2023 at 9:13:19 AM UTC-4, KJ wrote:=20 > > On Thursday, January 26, 2023 at 12:24:16 PM UTC-5, ashokm...@gmail.com= wrote:=20 > > > On Wednesday, January 25, 2023 at 7:25:18 PM UTC-8, gnuarm.del...@gma= il.com wrote:=20 > > > > On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...@gmail= .com wrote:=20 > > > > > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del...@= gmail.com wrote:=20 > > > > > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@gma= il.com wrote:=20 > So is that the same as having the value NULL? Isn't NULL the indication o= f pointing to nothing?=20 >=20 For your first question: The VHDL variable is an access type (similar to b= ut not the same as a C/C++ pointer). That variable will have a value which= can be the literal null per the standard. If the value of the variable is= null, then the standard is saying that you can't access anything with the = variable because there is no object to access (per standard "access value d= esignating no object at all."). The ability (or inability) to access somet= hing in VHDL is not the same thing as being able to dereference a pointer i= n software. For your second question: Yes. > If it were uninitialized, it could have any value at all.=20 Not sure what "it" is that you are referring to but a VHDL variable will ne= ver have "any value at all". The OP's declaration of variable 'Head', beca= use this is VHDL, means that the compiler will assign the value of null in = the OP's code. The same would not be true for a similarly declared pointer= in C/C++. In that situation, the C/C++ variable could have 'any value at = all' and would be pointing to who knows what. > You've not said it is unitialized, and you have not said it contains NULL= . The access type variable's value is the literal null (not the literal 0 or = anything but 'null'). > "Pointing to nothing" is not clear unless you mean it contains a NULL. I quoted the standard and then applied the interpretation that I thought wo= uld help the OP understand. What I said was > "designating no object at all" meaning it doesn't 'point' to anything > You even say "VHDL assigns the variable the 'value' null". So isn't that = an adequate explanation rather than the much more wordy statement, "pointin= g to nothing"? That's the point of "null", it points to nothing.=20 Well if you didn't like the longer answer, you should have stopped at the s= hort answer that I gave. You and the OP have been going back and forth for a bit but the OP was stil= l confused about "where does Head point to when it is first declared", so I= was just suggesting an alternative explanation and quoting from the standa= rd as the reference. Maybe it helps the OP understand, maybe not. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:40 2024 X-Received: by 2002:a05:620a:407:b0:702:4128:2891 with SMTP id 7-20020a05620a040700b0070241282891mr2302634qkp.146.1674836716736; Fri, 27 Jan 2023 08:25:16 -0800 (PST) X-Received: by 2002:a25:34cd:0:b0:80b:83b0:c87e with SMTP id b196-20020a2534cd000000b0080b83b0c87emr1179760yba.360.1674836716469; Fri, 27 Jan 2023 08:25:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Jan 2023 08:25:16 -0800 (PST) In-Reply-To: <77ec8bfe-8e72-4937-9179-dd78c84463b8n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=66.50.50.210; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 66.50.50.210 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> <77ec8bfe-8e72-4937-9179-dd78c84463b8n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <390cb431-76b5-487c-a4d9-01d517d68d90n@googlegroups.com> Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: "gnuarm.del...@gmail.com" Injection-Date: Fri, 27 Jan 2023 16:25:16 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5364 Xref: reader01.eternal-september.org comp.lang.vhdl:9905 On Friday, January 27, 2023 at 11:21:02 AM UTC-4, KJ wrote: > On Friday, January 27, 2023 at 9:08:16 AM UTC-5, gnuarm.del...@gmail.com = wrote:=20 > > On Friday, January 27, 2023 at 9:13:19 AM UTC-4, KJ wrote:=20 > > > On Thursday, January 26, 2023 at 12:24:16 PM UTC-5, ashokm...@gmail.c= om wrote:=20 > > > > On Wednesday, January 25, 2023 at 7:25:18 PM UTC-8, gnuarm.del...@g= mail.com wrote:=20 > > > > > On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...@gma= il.com wrote:=20 > > > > > > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del..= .@gmail.com wrote:=20 > > > > > > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...@g= mail.com wrote:=20 >=20 > > So is that the same as having the value NULL? Isn't NULL the indication= of pointing to nothing?=20 > > > For your first question: The VHDL variable is an access type (similar to = but not the same as a C/C++ pointer). That variable will have a value which= can be the literal null per the standard. If the value of the variable is = null, then the standard is saying that you can't access anything with the v= ariable because there is no object to access (per standard "access value de= signating no object at all."). The ability (or inability) to access somethi= ng in VHDL is not the same thing as being able to dereference a pointer in = software.=20 >=20 > For your second question: Yes. > > If it were uninitialized, it could have any value at all. > Not sure what "it" is that you are referring to but a VHDL variable will = never have "any value at all". The OP's declaration of variable 'Head', bec= ause this is VHDL, means that the compiler will assign the value of null in= the OP's code. The same would not be true for a similarly declared pointer= in C/C++. In that situation, the C/C++ variable could have 'any value at a= ll' and would be pointing to who knows what. > > You've not said it is unitialized, and you have not said it contains NU= LL. > The access type variable's value is the literal null (not the literal 0 o= r anything but 'null'). > > "Pointing to nothing" is not clear unless you mean it contains a NULL. > I quoted the standard and then applied the interpretation that I thought = would help the OP understand. What I said was > > "designating no object at all" meaning it doesn't 'point' to anything > > You even say "VHDL assigns the variable the 'value' null". So isn't tha= t an adequate explanation rather than the much more wordy statement, "point= ing to nothing"? That's the point of "null", it points to nothing. > Well if you didn't like the longer answer, you should have stopped at the= short answer that I gave.=20 >=20 > You and the OP have been going back and forth for a bit but the OP was st= ill confused about "where does Head point to when it is first declared", so= I was just suggesting an alternative explanation and quoting from the stan= dard as the reference. Maybe it helps the OP understand, maybe not.=20 >=20 > Kevin Jennings "it points to nothing at all" was your short answer. The rest of that post= was the long answer. Neither were great answers. I believe a more useful= answer would be that when created, the declaration=20 variable Head : Ptr;=20 Gives Head the value NULL. =20 If you had said this, instead of the less informative answer, "it points to= nothing at all", (which may be perfectly accurate, but not so useful) I th= ink that would have been the end of the conversation. =20 Have I misstated the nature of the ptr declaration? =20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:41 2024 X-Received: by 2002:a37:9a41:0:b0:71a:7038:614b with SMTP id c62-20020a379a41000000b0071a7038614bmr51714qke.579.1674844637165; Fri, 27 Jan 2023 10:37:17 -0800 (PST) X-Received: by 2002:a25:97c8:0:b0:7d0:dd57:2834 with SMTP id j8-20020a2597c8000000b007d0dd572834mr5096362ybo.198.1674844637004; Fri, 27 Jan 2023 10:37:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Jan 2023 10:37:16 -0800 (PST) In-Reply-To: <390cb431-76b5-487c-a4d9-01d517d68d90n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:65a2:cc86:7e90:d5c6; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:65a2:cc86:7e90:d5c6 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> <77ec8bfe-8e72-4937-9179-dd78c84463b8n@googlegroups.com> <390cb431-76b5-487c-a4d9-01d517d68d90n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: KJ Injection-Date: Fri, 27 Jan 2023 18:37:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3303 Xref: reader01.eternal-september.org comp.lang.vhdl:9906 On Friday, January 27, 2023 at 11:25:19 AM UTC-5, gnuarm.del...@gmail.com w= rote: > On Friday, January 27, 2023 at 11:21:02 AM UTC-4, KJ wrote:=20 > > On Friday, January 27, 2023 at 9:08:16 AM UTC-5, gnuarm.del...@gmail.co= m wrote:=20 > > > On Friday, January 27, 2023 at 9:13:19 AM UTC-4, KJ wrote:=20 > > > > On Thursday, January 26, 2023 at 12:24:16 PM UTC-5, ashokm...@gmail= .com wrote:=20 > > > > > On Wednesday, January 25, 2023 at 7:25:18 PM UTC-8, gnuarm.del...= @gmail.com wrote:=20 > > > > > > On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...@g= mail.com wrote:=20 > > > > > > > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.del= ...@gmail.com wrote:=20 > > > > > > > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm...= @gmail.com wrote:=20 > "it points to nothing at all" was your short answer. The rest of that pos= t was the long answer. Neither were great answers. You left out the question that the OP asked which was "how do we know that = Head is pointing to a node and that the node is null -before- assigning it = new memory" and me saying that it points to nothing at all and that it is s= et to null seems pretty clear to me. If you don't think my response is adequate, OK, but I wasn't responding to = you, I was responding to the OP. When you had your chance with the OP your= responses didn't clarify since he/she had the same question which resulted= in the back and forth that the two of you had. Before criticizing my resp= onse, perhaps consider your own. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:41 2024 X-Received: by 2002:a05:620a:693:b0:706:ad09:af41 with SMTP id f19-20020a05620a069300b00706ad09af41mr1427088qkh.538.1674847217096; Fri, 27 Jan 2023 11:20:17 -0800 (PST) X-Received: by 2002:a81:1e8c:0:b0:4b7:dfa2:76f3 with SMTP id e134-20020a811e8c000000b004b7dfa276f3mr4884118ywe.232.1674847216870; Fri, 27 Jan 2023 11:20:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Jan 2023 11:20:16 -0800 (PST) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=66.50.50.210; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 66.50.50.210 References: <0c358282-b93e-4aeb-9987-9421ceaa50d3n@googlegroups.com> <93ba553c-4fed-468e-b1d4-95bc30e549bfn@googlegroups.com> <6cd48de8-6d5c-4593-9bdb-90422b0712a5n@googlegroups.com> <85da0872-5fbb-4fd6-bf7b-9c76c55d0576n@googlegroups.com> <77ec8bfe-8e72-4937-9179-dd78c84463b8n@googlegroups.com> <390cb431-76b5-487c-a4d9-01d517d68d90n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13369da2-2d9d-44d1-84a8-0cf4ee1bec55n@googlegroups.com> Subject: Re: How does a HEAD pointer end up pointing to the first node in a linked list? From: "gnuarm.del...@gmail.com" Injection-Date: Fri, 27 Jan 2023 19:20:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3949 Xref: reader01.eternal-september.org comp.lang.vhdl:9907 On Friday, January 27, 2023 at 2:37:18 PM UTC-4, KJ wrote: > On Friday, January 27, 2023 at 11:25:19 AM UTC-5, gnuarm.del...@gmail.com= wrote:=20 > > On Friday, January 27, 2023 at 11:21:02 AM UTC-4, KJ wrote:=20 > > > On Friday, January 27, 2023 at 9:08:16 AM UTC-5, gnuarm.del...@gmail.= com wrote:=20 > > > > On Friday, January 27, 2023 at 9:13:19 AM UTC-4, KJ wrote:=20 > > > > > On Thursday, January 26, 2023 at 12:24:16 PM UTC-5, ashokm...@gma= il.com wrote:=20 > > > > > > On Wednesday, January 25, 2023 at 7:25:18 PM UTC-8, gnuarm.del.= ..@gmail.com wrote:=20 > > > > > > > On Wednesday, January 25, 2023 at 1:36:29 PM UTC-4, ashokm...= @gmail.com wrote:=20 > > > > > > > > On Tuesday, January 24, 2023 at 11:48:22 AM UTC-8, gnuarm.d= el...@gmail.com wrote:=20 > > > > > > > > > On Tuesday, January 24, 2023 at 2:34:22 PM UTC-5, ashokm.= ..@gmail.com wrote:=20 >=20 > > "it points to nothing at all" was your short answer. The rest of that p= ost was the long answer. Neither were great answers. > You left out the question that the OP asked which was "how do we know tha= t Head is pointing to a node and that the node is null -before- assigning i= t new memory" and me saying that it points to nothing at all and that it is= set to null seems pretty clear to me.=20 >=20 > If you don't think my response is adequate, OK, but I wasn't responding t= o you, I was responding to the OP. When you had your chance with the OP you= r responses didn't clarify since he/she had the same question which resulte= d in the back and forth that the two of you had. Before criticizing my resp= onse, perhaps consider your own.=20 >=20 > Kevin Jennings Don't be sensitive now. You pointed out that you didn't think I got to th= e point. I simply explained that you also missed the point in your very sh= ort reply, then went way far overboard with the subsequent exquisitely deta= iled full reply. =20 Just trying to help by pointing out that too much information is just as ba= d as too little. =20 Enjoy your weekend.=20 --=20 Rick C. ++ Get 1,000 miles of free Supercharging ++ Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:41 2024 X-Received: by 2002:a0c:f24e:0:b0:571:471:8925 with SMTP id z14-20020a0cf24e000000b0057104718925mr353195qvl.18.1676726914838; Sat, 18 Feb 2023 05:28:34 -0800 (PST) X-Received: by 2002:a25:9f87:0:b0:8ef:90e1:b2f8 with SMTP id u7-20020a259f87000000b008ef90e1b2f8mr55943ybq.2.1676726914318; Sat, 18 Feb 2023 05:28:34 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!border-1.nntp.ord.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 18 Feb 2023 05:28:34 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=82.1.128.13; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 82.1.128.13 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3215981d-dd44-4199-a0d9-d8dcf473836bn@googlegroups.com> Subject: Passing multiple parameters to a procedure From: niv Injection-Date: Sat, 18 Feb 2023 13:28:34 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 32 Xref: reader01.eternal-september.org comp.lang.vhdl:9908 I generate a set of entry widgets & checkboxes as below: ##----------------------------------------------------------------------------- ## Labels & Entry for MultiBlock Rows 1 to 10 ##----------------------------------------------------------------------------- ## Grid placement for all the rows ##----------------------------------------------------------------------------- for {set xxx 0} {$xxx < 10} {incr xxx} { label $f4a.lb_TIM_$xxx -text "Time" -font {Arial 8 bold} -background white -foreground black label $f4a.lb_SPC_$xxx -text " " -font {Arial 8 bold} entry $f4a.enMINS_$xxx -textvar MB_mins_$xxx -width 2 -validate all -vcmd {ValidInt %P} entry $f4a.enSECS_$xxx -textvar MB_secs_$xxx -width 2 -validate all -vcmd {ValidInt %P} entry $f4a.enPWR_$xxx -textvar MB_power_$xxx -width 3 -validate all -vcmd {ValidInt %P} entry $f4a.enCAD_$xxx -textvar MB_cad_$xxx -width 3 -validate all -vcmd {ValidInt %P} checkbutton $f4a.cbSEL_$xxx -var MB_sel_$xxx -background white -foreground red grid $f4a.lb_TIM_$xxx -row [expr $xxx + 1] -column 0 grid $f4a.enMINS_$xxx -row [expr $xxx + 1] -column 1 grid $f4a.lb_SPC_$xxx -row [expr $xxx + 1] -column 2 grid $f4a.enSECS_$xxx -row [expr $xxx + 1] -column 3 grid $f4a.enPWR_$xxx -row [expr $xxx + 1] -column 4 grid $f4a.enCAD_$xxx -row [expr $xxx + 1] -column 5 grid $f4a.cbSEL_$xxx -row [expr $xxx + 1] -column 6 } All that works fine, generating 10 rows each with 4 entries & a checkbox, so 50 data points. I cannot see to pass all that info to the procedure that works on the data except to pass all 50 individually, which is not great & pretty inelegant! Is there a nice clean way to pass the data to the proc? TIA, Kev P. From newsfish@newsfish Thu Aug 1 00:46:42 2024 X-Received: by 2002:a05:622a:1a95:b0:3d7:9d03:75b0 with SMTP id s21-20020a05622a1a9500b003d79d0375b0mr877983qtc.13.1678983367382; Thu, 16 Mar 2023 09:16:07 -0700 (PDT) X-Received: by 2002:a5b:c7:0:b0:b3b:d433:b063 with SMTP id d7-20020a5b00c7000000b00b3bd433b063mr5662461ybp.4.1678983367148; Thu, 16 Mar 2023 09:16:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!news.misty.com!border-2.nntp.ord.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Mar 2023 09:16:06 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=2602:306:334c:b080:f416:2e7f:9b1d:fa05; posting-account=rRWESQoAAABpGoGZN4aaNtcTcmzDYlqZ NNTP-Posting-Host: 2602:306:334c:b080:f416:2e7f:9b1d:fa05 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c58ea4f-d2f7-4d24-8838-5476ee4ffaf0n@googlegroups.com> Subject: Converting Signed (or unsigned) to TO_INTEGER From: =?UTF-8?B?QSDigJxBc2h2aW7igJ0=?= Injection-Date: Thu, 16 Mar 2023 16:16:07 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 10 Xref: reader01.eternal-september.org comp.lang.vhdl:9909 I have the following declarations signal S: SIGNED(7 downto 0); signal N: INTEGER; N <= TO_INTEGER(S); Question: Will the TO_INTEGER functiona sign extend 'S' to 32 bit integer? Thanks. From newsfish@newsfish Thu Aug 1 00:46:42 2024 X-Received: by 2002:a05:6214:9a1:b0:56c:1704:b11c with SMTP id du1-20020a05621409a100b0056c1704b11cmr4593389qvb.7.1679013234782; Thu, 16 Mar 2023 17:33:54 -0700 (PDT) X-Received: by 2002:a81:e24c:0:b0:541:7f69:aa9b with SMTP id z12-20020a81e24c000000b005417f69aa9bmr288971ywl.4.1679013234469; Thu, 16 Mar 2023 17:33:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!reader01.eternal-september.org!usenet.blueworldhosting.com!feed1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 Mar 2023 17:33:54 -0700 (PDT) In-Reply-To: <7c58ea4f-d2f7-4d24-8838-5476ee4ffaf0n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:9535:80b8:c71a:9192; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:9535:80b8:c71a:9192 References: <7c58ea4f-d2f7-4d24-8838-5476ee4ffaf0n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <84845d7a-3232-4bf8-ac3f-d5aa5580a47bn@googlegroups.com> Subject: Re: Converting Signed (or unsigned) to TO_INTEGER From: KJ Injection-Date: Fri, 17 Mar 2023 00:33:54 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2254 Xref: reader01.eternal-september.org comp.lang.vhdl:9910 On Thursday, March 16, 2023 at 12:16:09=E2=80=AFPM UTC-4, A =E2=80=9CAshvin= =E2=80=9D wrote: > I have the following declarations=20 >=20 > signal S: SIGNED(7 downto 0);=20 > signal N: INTEGER;=20 >=20 > N <=3D TO_INTEGER(S);=20 >=20 > Question: Will the TO_INTEGER functiona sign extend 'S' to 32 bit integer= ?=20 >=20 > Thanks. VHDL integers are not a collection of 'bits' so in that sense the answer to= your question is 'No'. However, if you assign S <=3D "11111111"; then N w= ill be set to -1 in your example. I assume this is more along the lines of= the real question you are getting at. Commonly, VHDL integers are impleme= nted as either 32 or 64 bits. If you have access to a VHDL simulator, it seems like you could have answer= ed this question yourself with about the same amount of effort you put into= your post...is there a reason you didn't? Or do you not have access to a = VHDL simulator? If not, I suggest at least GHDL which is free for download= . Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:42 2024 X-Received: by 2002:a05:622a:1813:b0:3eb:572:226 with SMTP id t19-20020a05622a181300b003eb05720226mr3238953qtc.5.1681745804850; Mon, 17 Apr 2023 08:36:44 -0700 (PDT) X-Received: by 2002:a25:da43:0:b0:b68:7b14:186b with SMTP id n64-20020a25da43000000b00b687b14186bmr7929329ybf.1.1681745804565; Mon, 17 Apr 2023 08:36:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.uzoreto.com!peer01.ams4!peer.am4.highwinds-media.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Apr 2023 08:36:44 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=2001:67c:2660:425:23:0:0:216; posting-account=zdwbRAoAAACL55azc3-lI-wZmDqKLgWp NNTP-Posting-Host: 2001:67c:2660:425:23:0:0:216 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: 8-bit full adder issue From: Marco De Luca Injection-Date: Mon, 17 Apr 2023 15:36:44 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5040 Xref: news.eternal-september.org comp.lang.vhdl:9911 stavo seguendo la lezione del mio insegnante e ho copiato il suo codice. Il= suo compilatore non ha dato alcun avviso o errore, ma quando provo a compilarlo con my PC, viene visualizzato un avviso sui componenti non limitati. ci ho provato usa anche std_logic invece di bit, ma niente (idk ho =E2=80=8B=E2=80=8Bprov= ato tutto). Sto iniziando a odiare vhdl e non so cosa devo fare. Ragazzi hai qualche idea? Grazie a tutti in anticipo SCRIPT 1 entity addern is generic (enne: integer:=3D8); port( c_in: in bit; x_in: in bit_vector (enne-1 downto 0); y_in: in bit_vector (enne-1 downto 0); c_out, s: out bit; s_out: out bit_vector (enne-1 downto 0) ); end entity; -- quello che ho fatto qui =C3=A8 definire praticamente una serie di 8 full= adder, praticamente lo posso immaginare come una black box in cui all'inte= rno ho tutti i componenti -- che sto per andare a definire all'interno dell'architecture architecture archi of addern is signal carry_chain : bit_vector (enne-2 downto 0); component cfa is port( a: in bit; b: in bit; ci:in bit; s: out bit; co: out bit ); end component; begin=20 --qui =C3=A8 necessario fare attenzione perch=C3=A8 tutti i blocchetti non= sono uguali, i due estremi non sono collegati a nulla, mentre quelli inter= ni invece sono collegati tra di loro gen_stat: for index in 0 to (enne-1) generate --fino all'end generate qui =C3=A8 come se stessimo mettendo uno dopo l'a= ltro n pezzi. --come gi=C3=A0 detto abbiamo 3 differenti casi di blocchetti: estremo de= stro, estremo sinistro e interni: begin prima_cella:if (index=3D0) generate begin cella_0: component cfa port map(a=3D>x_in(index), b=3D>y_in(index), ci=3D>c_in, s=3D>s_out(index), co=3D>carry_chain(index) );=09 end generate; ultima_cella:if (index=3D(enne-1)) generate begin cella_n: component cfa port map(a=3D>x_in(index), b=3D>y_in(index), ci=3D>carry_chain(index-1), s=3D>s_out(index), co=3D>c_out ); end generate; =20 altre_celle:if ((index/=3D0) and (index/=3D(enne-1)))generate begin celle: component cfa port map(a=3D>x_in(index), b=3D>y_in(index), ci=3D>carry_chain(index-1), s=3D>s_out(index), co=3D>carry_chain(index) ); end generate; end generate; end architecture; TESTBENCH (SCRIPT2) entity tb is end entity; architecture struct of tb is signal add1,add2,somma : bit_vector (7 downto 0); signal riporto : bit; begin sommatore: entity work.addern generic map (enne=3D>8) port map(x_in=3D>add1, y_in=3D>add2, c_in=3D>'0',c_out=3D>riporto, s_out= =3D>somma); =09 process is begin=09 add1<=3D"00000000"; add2<=3D"00000000"; wait for 50 ns; add1<=3D"00001100"; add2<=3D"11100000"; wait for 50 ns; add1<=3D"00011100"; add2<=3D"00011111"; wait for 50 ns; add1<=3D"00001111"; add2<=3D"11100000"; wait for 50 ns; add1<=3D"01111111"; add2<=3D"00000111"; wait for 50 ns; add1<=3D"00011100"; add2<=3D"00010000"; wait for 50 ns; add1<=3D"01110010"; add2<=3D"00000111"; wait for 50 ns; add1<=3D"00111100"; add2<=3D"01111100"; wait for 50 ns; wait; end process; end architecture; ERRORS: adder_n.vhd:35:40:warning: component instance "cella_sin" is not bound adder_n.vhd:15:14:warning: (in default configuration of addern(archi)) adder_n.vhd:45:41:warning: component instance "cella_des" is not bound adder_n.vhd:15:14:warning: (in default configuration of addern(archi)) adder_n.vhd:56:40:warning: component instance "celle" is not bound adder_n.vhd:15:14:warning: (in default configuration of addern(archi)) From newsfish@newsfish Thu Aug 1 00:46:43 2024 X-Received: by 2002:a05:6214:a08:b0:5ef:4c4d:1cb8 with SMTP id dw8-20020a0562140a0800b005ef4c4d1cb8mr2198031qvb.8.1681767308398; Mon, 17 Apr 2023 14:35:08 -0700 (PDT) X-Received: by 2002:a25:d6d4:0:b0:b8e:ec30:853e with SMTP id n203-20020a25d6d4000000b00b8eec30853emr8460700ybg.4.1681767308220; Mon, 17 Apr 2023 14:35:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!1.us.feeder.erje.net!feeder.erje.net!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Apr 2023 14:35:08 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=173.71.184.234; posting-account=tm0w8woAAADeGQypQ3zH5sMmYM3ldVzT NNTP-Posting-Host: 173.71.184.234 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: 8-bit full adder issue From: Marc Guardiani Injection-Date: Mon, 17 Apr 2023 21:35:08 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5569 Xref: news.eternal-september.org comp.lang.vhdl:9912 On Monday, April 17, 2023 at 11:36:46=E2=80=AFAM UTC-4, Marco De Luca wrote= : > stavo seguendo la lezione del mio insegnante e ho copiato il suo codice. = Il suo compilatore=20 > non ha dato alcun avviso o errore, ma quando provo a compilarlo con my=20 > PC, viene visualizzato un avviso sui componenti non limitati. ci ho prova= to=20 > usa anche std_logic invece di bit, ma niente (idk ho =E2=80=8B=E2=80=8Bpr= ovato tutto).=20 > Sto iniziando a odiare vhdl e non so cosa devo fare. Ragazzi=20 > hai qualche idea?=20 > Grazie a tutti in anticipo=20 >=20 > SCRIPT 1=20 > entity addern is=20 > generic (enne: integer:=3D8);=20 > port( c_in: in bit;=20 > x_in: in bit_vector (enne-1 downto 0);=20 > y_in: in bit_vector (enne-1 downto 0);=20 > c_out, s: out bit;=20 > s_out: out bit_vector (enne-1 downto 0)=20 > );=20 > end entity;=20 > -- quello che ho fatto qui =C3=A8 definire praticamente una serie di 8 fu= ll adder, praticamente lo posso immaginare come una black box in cui all'in= terno ho tutti i componenti=20 > -- che sto per andare a definire all'interno dell'architecture=20 > architecture archi of addern is=20 > signal carry_chain : bit_vector (enne-2 downto 0);=20 >=20 > component cfa is=20 > port(=20 > a: in bit;=20 > b: in bit;=20 > ci:in bit;=20 > s: out bit;=20 > co: out bit=20 > );=20 > end component;=20 > begin=20 > --qui =C3=A8 necessario fare attenzione perch=C3=A8 tutti i blocchetti no= n sono uguali, i due estremi non sono collegati a nulla, mentre quelli inte= rni invece sono collegati tra di loro=20 > gen_stat: for index in 0 to (enne-1) generate=20 > --fino all'end generate qui =C3=A8 come se stessimo mettendo uno dopo l'a= ltro n pezzi.=20 > --come gi=C3=A0 detto abbiamo 3 differenti casi di blocchetti: estremo de= stro, estremo sinistro e interni:=20 > begin=20 > prima_cella:if (index=3D0) generate=20 > begin=20 > cella_0: component cfa=20 > port map(a=3D>x_in(index),=20 > b=3D>y_in(index),=20 > ci=3D>c_in,=20 > s=3D>s_out(index),=20 > co=3D>carry_chain(index)=20 > );=20 > end generate;=20 > ultima_cella:if (index=3D(enne-1)) generate=20 > begin=20 > cella_n: component cfa=20 > port map(a=3D>x_in(index),=20 > b=3D>y_in(index),=20 > ci=3D>carry_chain(index-1),=20 > s=3D>s_out(index),=20 > co=3D>c_out=20 > );=20 > end generate;=20 >=20 > altre_celle:if ((index/=3D0) and (index/=3D(enne-1)))generate=20 > begin=20 > celle: component cfa=20 > port map(a=3D>x_in(index),=20 > b=3D>y_in(index),=20 > ci=3D>carry_chain(index-1),=20 > s=3D>s_out(index),=20 > co=3D>carry_chain(index)=20 > );=20 > end generate;=20 > end generate;=20 > end architecture;=20 >=20 >=20 >=20 >=20 >=20 > TESTBENCH (SCRIPT2)=20 > entity tb is=20 > end entity;=20 >=20 > architecture struct of tb is=20 > signal add1,add2,somma : bit_vector (7 downto 0);=20 > signal riporto : bit;=20 > begin=20 > sommatore: entity work.addern=20 > generic map (enne=3D>8)=20 > port map(x_in=3D>add1, y_in=3D>add2, c_in=3D>'0',c_out=3D>riporto, s_out= =3D>somma);=20 >=20 > process is=20 > begin=20 > add1<=3D"00000000";=20 > add2<=3D"00000000";=20 > wait for 50 ns;=20 > add1<=3D"00001100";=20 > add2<=3D"11100000";=20 > wait for 50 ns;=20 > add1<=3D"00011100";=20 > add2<=3D"00011111";=20 > wait for 50 ns;=20 > add1<=3D"00001111";=20 > add2<=3D"11100000";=20 > wait for 50 ns;=20 > add1<=3D"01111111";=20 > add2<=3D"00000111";=20 > wait for 50 ns;=20 > add1<=3D"00011100";=20 > add2<=3D"00010000";=20 > wait for 50 ns;=20 > add1<=3D"01110010";=20 > add2<=3D"00000111";=20 > wait for 50 ns;=20 > add1<=3D"00111100";=20 > add2<=3D"01111100";=20 > wait for 50 ns;=20 > wait;=20 > end process;=20 > end architecture;=20 >=20 >=20 > ERRORS:=20 > adder_n.vhd:35:40:warning: component instance "cella_sin" is not bound=20 > adder_n.vhd:15:14:warning: (in default configuration of addern(archi))=20 > adder_n.vhd:45:41:warning: component instance "cella_des" is not bound=20 > adder_n.vhd:15:14:warning: (in default configuration of addern(archi))=20 > adder_n.vhd:56:40:warning: component instance "celle" is not bound=20 > adder_n.vhd:15:14:warning: (in default configuration of addern(archi)) Remove the extra "begin" statements after each generate (in 4 places). For = example: gen_stat: for index in 0 to (enne-1) generate --REMOVE begin --Marc From newsfish@newsfish Thu Aug 1 00:46:43 2024 X-Received: by 2002:a05:620a:139c:b0:74d:1be5:f1a3 with SMTP id k28-20020a05620a139c00b0074d1be5f1a3mr2452190qki.15.1681869146383; Tue, 18 Apr 2023 18:52:26 -0700 (PDT) X-Received: by 2002:a25:d292:0:b0:b96:347d:46e7 with SMTP id j140-20020a25d292000000b00b96347d46e7mr1135511ybg.1.1681869146144; Tue, 18 Apr 2023 18:52:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Apr 2023 18:52:25 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=173.71.184.234; posting-account=tm0w8woAAADeGQypQ3zH5sMmYM3ldVzT NNTP-Posting-Host: 173.71.184.234 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <482f2e41-6ebe-4960-b55f-85b24ac153b4n@googlegroups.com> Subject: Re: 8-bit full adder issue From: Marc Guardiani Injection-Date: Wed, 19 Apr 2023 01:52:26 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2239 Xref: news.eternal-september.org comp.lang.vhdl:9913 On Monday, April 17, 2023 at 5:35:10=E2=80=AFPM UTC-4, Marc Guardiani wrote= : > On Monday, April 17, 2023 at 11:36:46=E2=80=AFAM UTC-4, Marco De Luca wro= te:=20 > > stavo seguendo la lezione del mio insegnante e ho copiato il suo codice= . Il suo compilatore=20 > > non ha dato alcun avviso o errore, ma quando provo a compilarlo con my= =20 > > PC, viene visualizzato un avviso sui componenti non limitati. ci ho pro= vato=20 > > usa anche std_logic invece di bit, ma niente (idk ho =E2=80=8B=E2=80=8B= provato tutto).=20 > > Sto iniziando a odiare vhdl e non so cosa devo fare. Ragazzi=20 > > hai qualche idea?=20 > > Grazie a tutti in anticipo=20 > >=20 > Remove the extra "begin" statements after each generate (in 4 places). Fo= r example: > gen_stat: for index in 0 to (enne-1) generate > --REMOVE begin=20 >=20 > --Marc OK, if you haven't gotten it yet. Here's another hint: You have to define an entity named cfa that does your one bit adder. --Marc From newsfish@newsfish Thu Aug 1 00:46:43 2024 X-Received: by 2002:ad4:4f91:0:b0:5ef:41e3:3cba with SMTP id em17-20020ad44f91000000b005ef41e33cbamr397792qvb.3.1682013501087; Thu, 20 Apr 2023 10:58:21 -0700 (PDT) X-Received: by 2002:a81:c649:0:b0:54f:e88d:79ba with SMTP id q9-20020a81c649000000b0054fe88d79bamr4393853ywj.5.1682013500765; Thu, 20 Apr 2023 10:58:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.uzoreto.com!peer01.ams4!peer.am4.highwinds-media.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Apr 2023 10:58:20 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=109.186.61.201; posting-account=5M7ecgoAAAAENKUU2BnoSClP1keTHN-g NNTP-Posting-Host: 109.186.61.201 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a51c4b0-6609-46ee-b4cf-39ff85cdfd0an@googlegroups.com> Subject: FPGA + ASIC PQC Security IP / hardware root of trust by Xiphera From: Alon Refaeli Injection-Date: Thu, 20 Apr 2023 17:58:21 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3051 Xref: news.eternal-september.org comp.lang.vhdl:9914 Are you tired of worrying about the security of your FPGA/ASIC system? Allow me to introduce Xiphera FPGA/ASIC cryptographic IP =E2=80=93 a powerf= ul solution that secures your system on chip design, from data transmission= to user authentication. Our IP=E2=80=99s are designed to seamlessly integrate with your FPGA/ASIC, = ensuring maximum security with minimal impact on performance. =20 Introducing Xiphera state-of-the-art FPGA/ASIC post quantum cryptographic I= P, Xiphera=E2=80=99s xQlave=E2=84=A2 , which is superior to traditional enc= ryption methods and can provide better protection against cyber threats =E2= =80=93 designed to provide maximum data protection and security for your va= luable intellectual property. =20 Use cases for our PQC can be : =20 1. Protecting sensitive data: Xiphera FPGA/ASIC security and encryption sol= utions can help you to protect your sensitive data by encrypting data at re= st and in transit. This approach can prevent unauthorized access to data an= d minimize the risk of data breaches. =20 2. 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For more details : alon.refaeli@xiphera.com From newsfish@newsfish Thu Aug 1 00:46:44 2024 X-Received: by 2002:ad4:5884:0:b0:626:adc:33c9 with SMTP id dz4-20020ad45884000000b006260adc33c9mr280352qvb.8.1686307457292; Fri, 09 Jun 2023 03:44:17 -0700 (PDT) X-Received: by 2002:a25:4609:0:b0:bac:fd27:28c1 with SMTP id t9-20020a254609000000b00bacfd2728c1mr643963yba.0.1686307456970; Fri, 09 Jun 2023 03:44:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!peer03.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jun 2023 03:44:16 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=14.139.223.179; posting-account=mIL4xwoAAAAv_nFqPqsic7jPEiC9TYgI NNTP-Posting-Host: 14.139.223.179 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3b5ddcd2-3780-4a34-8920-a92ff15966f4n@googlegroups.com> Subject: Concurrent assignment to a non-net q is not permitted From: Indrayudh Nandy Injection-Date: Fri, 09 Jun 2023 10:44:17 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1423 Xref: news.eternal-september.org comp.lang.vhdl:9915 Hi, I am facing this error in vivado while writing a code for conversion of D flip flop to JK flip flop. Here is my code : module D_to_jk(j,k,clk,rst,q); input j,k,clk,rst; output reg q; wire w1,w2,w3,w4; wire q_bar; assign w1=~k; assign q_bar= ~q; assign w2= j&q_bar; assign w3= w1&q; assign w4= w2|w3; D d(w4,clk,rst,q); endmodule Please point me out the error so that I may rectify. Thanks Indrayudh From newsfish@newsfish Thu Aug 1 00:46:44 2024 Path: eternal-september.org!news.eternal-september.org!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!fx38.iad.POSTED!not-for-mail MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: Concurrent assignment to a non-net q is not permitted Newsgroups: comp.lang.vhdl References: <3b5ddcd2-3780-4a34-8920-a92ff15966f4n@googlegroups.com> From: Richard Damon Content-Language: en-US In-Reply-To: <3b5ddcd2-3780-4a34-8920-a92ff15966f4n@googlegroups.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 23 Message-ID: <6fHgM.1002$Yxn4.359@fx38.iad> X-Complaints-To: abuse@easynews.com Organization: Forte - www.forteinc.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Fri, 9 Jun 2023 11:07:46 -0400 X-Received-Bytes: 1493 Xref: news.eternal-september.org comp.lang.vhdl:9916 On 6/9/23 6:44 AM, Indrayudh Nandy wrote: > Hi, > I am facing this error in vivado while writing a code for conversion of D flip flop to JK flip flop. > Here is my code : > module D_to_jk(j,k,clk,rst,q); > input j,k,clk,rst; > output reg q; > wire w1,w2,w3,w4; > wire q_bar; > assign w1=~k; > assign q_bar= ~q; > assign w2= j&q_bar; > assign w3= w1&q; > assign w4= w2|w3; > D d(w4,clk,rst,q); > endmodule > > Please point me out the error so that I may rectify. > Thanks > Indrayudh YOUR q needs to be a wire which you are connecting to the actual reg which will be in the D primative. From newsfish@newsfish Thu Aug 1 00:46:44 2024 X-Received: by 2002:ad4:4b32:0:b0:626:2413:900e with SMTP id s18-20020ad44b32000000b006262413900emr488891qvw.4.1686353565444; Fri, 09 Jun 2023 16:32:45 -0700 (PDT) X-Received: by 2002:a25:ab87:0:b0:bac:3439:4f59 with SMTP id v7-20020a25ab87000000b00bac34394f59mr1492028ybi.2.1686353565140; Fri, 09 Jun 2023 16:32:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jun 2023 16:32:44 -0700 (PDT) In-Reply-To: <3b5ddcd2-3780-4a34-8920-a92ff15966f4n@googlegroups.com> Injection-Info: google-groups.googlegroups.com; posting-host=65.207.89.54; posting-account=I-_H_woAAAA9zzro6crtEpUAyIvzd19b NNTP-Posting-Host: 65.207.89.54 References: <3b5ddcd2-3780-4a34-8920-a92ff15966f4n@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5c9c2b21-835b-41bd-a906-11febaeb4810n@googlegroups.com> Subject: Re: Concurrent assignment to a non-net q is not permitted From: "gnuarm.del...@gmail.com" Injection-Date: Fri, 09 Jun 2023 23:32:45 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2034 Xref: news.eternal-september.org comp.lang.vhdl:9917 On Friday, June 9, 2023 at 6:44:18=E2=80=AFAM UTC-4, Indrayudh Nandy wrote: > Hi,=20 > I am facing this error in vivado while writing a code for conversion of D= flip flop to JK flip flop.=20 > Here is my code :=20 > module D_to_jk(j,k,clk,rst,q);=20 > input j,k,clk,rst;=20 > output reg q;=20 > wire w1,w2,w3,w4;=20 > wire q_bar;=20 > assign w1=3D~k;=20 > assign q_bar=3D ~q;=20 > assign w2=3D j&q_bar;=20 > assign w3=3D w1&q;=20 > assign w4=3D w2|w3;=20 > D d(w4,clk,rst,q);=20 > endmodule=20 >=20 > Please point me out the error so that I may rectify.=20 > Thanks=20 > Indrayudh I think your biggest error, is trying to compile a Verilog program with a V= HDL tool, perhaps?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 From newsfish@newsfish Thu Aug 1 00:46:45 2024 X-Received: by 2002:a05:622a:1ba4:b0:403:ac57:a01b with SMTP id bp36-20020a05622a1ba400b00403ac57a01bmr6857qtb.5.1688942438299; Sun, 09 Jul 2023 15:40:38 -0700 (PDT) X-Received: by 2002:a63:b253:0:b0:553:9efa:1159 with SMTP id t19-20020a63b253000000b005539efa1159mr7896838pgo.0.1688942437945; Sun, 09 Jul 2023 15:40:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Jul 2023 15:40:37 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=96.47.239.242; posting-account=p3xHJgoAAAA6zvswhJoDaSyS2ln4a4rG NNTP-Posting-Host: 96.47.239.242 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <79561b83-3d60-4211-aa7a-19089d553f8an@googlegroups.com> Subject: Download WooCommerce Follow-Up Emails From: Lazaros Gekas Injection-Date: Sun, 09 Jul 2023 22:40:38 +0000 Content-Type: text/plain; charset="UTF-8" X-Received-Bytes: 1175 Xref: news.eternal-september.org comp.lang.vhdl:9918 Download WooCommerce Follow-Up Emails. Here is the Download link for lowest price: => https://gplstage.xyz/follow-ups => https://gplstage.xyz/follow-ups => https://gplstage.xyz/follow-ups From newsfish@newsfish Thu Aug 1 00:46:45 2024 X-Received: by 2002:ac8:4e54:0:b0:401:e192:fc61 with SMTP id e20-20020ac84e54000000b00401e192fc61mr8441qtw.7.1692163401957; Tue, 15 Aug 2023 22:23:21 -0700 (PDT) X-Received: by 2002:a63:3d0c:0:b0:563:e826:823b with SMTP id k12-20020a633d0c000000b00563e826823bmr211472pga.6.1692163401418; Tue, 15 Aug 2023 22:23:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.mixmin.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Aug 2023 22:23:20 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=37.111.134.129; posting-account=WecHrAoAAACGpf4E0HX9UMWY1aLBpHDy NNTP-Posting-Host: 37.111.134.129 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <90003e43-255a-42d1-8632-8095b4bab055n@googlegroups.com> Subject: Design and Simulation of Seven Segment Decoder From: Zohaib Ul Hassan Injection-Date: Wed, 16 Aug 2023 05:23:21 +0000 Content-Type: text/plain; charset="UTF-8" Xref: news.eternal-september.org comp.lang.vhdl:9919 Design and Simulation of Seven Segment Decoder in VHDL. From newsfish@newsfish Thu Aug 1 00:46:46 2024 Newsgroups: comp.lang.vhdl From: Stef Subject: Re: Design and Simulation of Seven Segment Decoder References: <90003e43-255a-42d1-8632-8095b4bab055n@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/1.0.3 (Linux) Message-ID: Organization: Newsxs Date: Wed, 16 Aug 2023 08:41:37 +0200 Path: eternal-september.org!news.eternal-september.org!2.eu.feeder.erje.net!feeder.erje.net!newsreader4.netcologne.de!news.netcologne.de!peer03.ams1!peer.ams1.xlned.com!news.xlned.com!peer01.ams4!peer.am4.highwinds-media.com!news.highwinds-media.com!feed.abavia.com!abe004.abavia.com!abp002.abavia.com!news.newsxs.nl!not-for-mail Lines: 11 Injection-Date: Wed, 16 Aug 2023 08:41:37 +0200 Injection-Info: news.newsxs.nl; mail-complaints-to="abuse@newsxs.nl" X-Received-Bytes: 947 Xref: news.eternal-september.org comp.lang.vhdl:9920 On 2023-08-16 Zohaib Ul Hassan wrote in comp.lang.vhdl: > Design and Simulation of Seven Segment Decoder in VHDL. Nice title! Looking forward to the rest of your report. -- Stef Live within your income, even if you have to borrow to do so. -Josh Billings From newsfish@newsfish Thu Aug 1 00:46:46 2024 Path: eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: littlewing Newsgroups: comp.lang.vhdl Subject: Split array assignment in and out of process? Date: Sat, 2 Sep 2023 16:54:57 -0400 Organization: A noiseless patient Spider Lines: 54 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 2 Sep 2023 20:54:56 -0000 (UTC) Injection-Info: dont-email.me; posting-host="25c3c66a227a600562f8635250a43f12"; logging-data="588317"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+LGe+ECvZj6weQPkpeiwxuOgso7FkdjX4=" User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cancel-Lock: sha1:PRizcMynwsrv3YQgsZJVCGoW5k0= Content-Language: en-US Xref: news.eternal-september.org comp.lang.vhdl:9921 I have some code that fails in the simulator but seemingly is OK when synthesized: entity synchronizer is generic ( stages : positive:= 3); port ( inval, clock: in std_logic; outval : out std_logic ); end entity; architecture rtl of synchronizer is signal shifter : std_logic_vector(0 to stages); begin shifter(0) <= inval; -- Assignment outside of process process(clock) begin if rising_edge(clock) then for i in 1 to stages loop shifter(i) <= shifter(i-1); -- Assignment inside of process end loop; end if; end process; outval <= shifter(stages); end architecture; In the simulator (late-model Vivado default), the "out" signal drives to "X" = illegal value, messing up my whole design. I can fix it by moving the assignment to shifter(0) into the process and changing the sensitivity list as follows: (only process shown) process(clock, inval) -- "inval" included in sensitivity list begin shifter(0) <= inval; -- Assignment inside of process if rising_edge(clock) then for i in 1 to stages loop shifter(i) <= shifter(i-1); -- Assignment inside of process end loop; end if; end process; Apparently the simulator thinks I am assigning two values to one destination. I try to assign to part of "shifter" outside of the process and the rest of it inside of the process. In VHDL, is the array considered one signal, or is it a convenience to describe a multiplicity of independent signals? Is my original code incorrect? From newsfish@newsfish Thu Aug 1 00:46:46 2024 X-Received: by 2002:ad4:58b2:0:b0:635:b307:af36 with SMTP id ea18-20020ad458b2000000b00635b307af36mr195431qvb.7.1693775779464; Sun, 03 Sep 2023 14:16:19 -0700 (PDT) X-Received: by 2002:a17:902:e843:b0:1ae:7604:d65c with SMTP id t3-20020a170902e84300b001ae7604d65cmr3015551plg.0.1693775778953; Sun, 03 Sep 2023 14:16:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 3 Sep 2023 14:16:18 -0700 (PDT) In-Reply-To: Injection-Info: google-groups.googlegroups.com; posting-host=2600:1700:d660:9640:6411:b6f6:b763:fe0c; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2600:1700:d660:9640:6411:b6f6:b763:fe0c References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Split array assignment in and out of process? From: KJ Injection-Date: Sun, 03 Sep 2023 21:16:19 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4080 Xref: news.eternal-september.org comp.lang.vhdl:9922 On Saturday, September 2, 2023 at 4:55:01=E2=80=AFPM UTC-4, littlewing wrot= e: > I have some code that fails in the simulator but seemingly is OK when=20 > synthesized:=20 >=20 > Apparently the simulator thinks I am assigning two values to one=20 > destination. I try to assign to part of "shifter" outside of the=20 > process and the rest of it inside of the process. In VHDL, is the=20 > array considered one signal, or is it a convenience to describe a=20 > multiplicity of independent signals? Is my original code incorrect? VHDL considers a signal to be driven if it is the target of an assignment. = In this case, the signal 'shifter' (all bits) is being driven both by your= process with the sensitivity list as well as the implicit 'shifter(0) <=3D= inval;' process . It doesn't matter that the two processes assigned to no= n-overlapping sub-elements of the signal 'shifter'. The reason for the 'X' is that while the sensitivity list process drives al= l the bits of 'shifter', since there is no assignment to 'shifter(0)' it sh= ould resolve to 'U' for that process. When it comes to resolving the two d= rivers for 'shifter(0)', the 'U' will win over anything that the 'shifter(0= ) <=3D inval;' process creates. Since you say that synthesis is OK, the sy= nthesis tool is likely letting it slide for some reason. That tool then wo= uld not really be compliant even if it is doing what you want. You might a= lso check the end results to make sure that it did actually synthesize to '= shifter(0) <=3D inval;' and not something else. Your original code is not correct and that is what the simulator is effecti= vely telling you when you run the simulation. 'Not correct' meaning that s= imulation results do not match synthesis results. It is not 'illegal' VHDL= since VHDL does allow multiple drivers to a 'resolved' signal type such as= 'std_logic/std_logic_vector'. However, most synthesis are for signals that are not meant to be driven by = more than one driver. The better type to use for all of those signals is '= std_ulogic/std_ulogic_vector'. If you take your original code and change t= he type of 'shifter' from 'std_logic_vector' to 'std_ulogic_vector', Vivado= should fail to compile because you have multiple drivers for 'shifter' and= it should tell you that. The nice thing is that you won't have to run any= simulation to figure that out. Std_logic is the 'usual' type that most fo= lks use, but std_ulogic is the far better choice for exactly this reason. = Better to find latent design errors during a compile then during a simulati= on run or, even worse, after deploying it into something that was synthesiz= ed. Save std_logic for cases where there actually are intended to be multi= ple drivers for a signal and all but one of those drivers will be driving a= 'Z' at all times. Kevin Jennings From newsfish@newsfish Thu Aug 1 00:46:47 2024 Path: eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: littlewing Newsgroups: comp.lang.vhdl Subject: Re: Split array assignment in and out of process? Date: Mon, 4 Sep 2023 09:05:27 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 4 Sep 2023 13:05:29 -0000 (UTC) Injection-Info: dont-email.me; posting-host="6bca9ac9e159e9642231f2ee7d537f72"; logging-data="1572696"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18H8CN1nfS/2h/55lwCAgp50s4NqmelPeQ=" User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cancel-Lock: sha1:AACSeV26lUXf3A2wAvZsOQopp8w= Content-Language: en-US In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:9923 On 9/3/2023 05:16 PM, KJ wrote: > On Saturday, September 2, 2023 at 4:55:01 PM UTC-4, littlewing wrote: >> I have some code that fails in the simulator but seemingly is OK when >> synthesized: > >> >> Apparently the simulator thinks I am assigning two values to one >> destination. I try to assign to part of "shifter" outside of the >> process and the rest of it inside of the process. In VHDL, is the >> array considered one signal, or is it a convenience to describe a >> multiplicity of independent signals? Is my original code incorrect? > > VHDL considers a signal to be driven if it is the target of an assignment. In this case, the signal 'shifter' (all bits) is being driven both by your process with the sensitivity list as well as the implicit 'shifter(0) <= inval;' process . It doesn't matter that the two processes assigned to non-overlapping sub-elements of the signal 'shifter'. > > The reason for the 'X' is that while the sensitivity list process drives all the bits of 'shifter', since there is no assignment to 'shifter(0)' it should resolve to 'U' for that process. When it comes to resolving the two drivers for 'shifter(0)', the 'U' will win over anything that the 'shifter(0) <= inval;' process creates. Since you say that synthesis is OK, the synthesis tool is likely letting it slide for some reason. That tool then would not really be compliant even if it is doing what you want. You might also check the end results to make sure that it did actually synthesize to 'shifter(0) <= inval;' and not something else. > > Your original code is not correct and that is what the simulator is effectively telling you when you run the simulation. 'Not correct' meaning that simulation results do not match synthesis results. It is not 'illegal' VHDL since VHDL does allow multiple drivers to a 'resolved' signal type such as 'std_logic/std_logic_vector'. > > However, most synthesis are for signals that are not meant to be driven by more than one driver. The better type to use for all of those signals is 'std_ulogic/std_ulogic_vector'. If you take your original code and change the type of 'shifter' from 'std_logic_vector' to 'std_ulogic_vector', Vivado should fail to compile because you have multiple drivers for 'shifter' and it should tell you that. The nice thing is that you won't have to run any simulation to figure that out. Std_logic is the 'usual' type that most folks use, but std_ulogic is the far better choice for exactly this reason. Better to find latent design errors during a compile then during a simulation run or, even worse, after deploying it into something that was synthesized. Save std_logic for cases where there actually are intended to be multiple drivers for a signal and all but one of those drivers will be driving a 'Z' at all times. > > Kevin Jennings Thanks for your thorough answer, Kevin. FYI, the Vivado tools do pick up multiple drivers, very late in the implementation flow. Geno From newsfish@newsfish Thu Aug 1 00:46:47 2024 X-Received: by 2002:a05:620a:1a88:b0:770:f19d:d6ac with SMTP id bl8-20020a05620a1a8800b00770f19dd6acmr78729qkb.0.1694328695836; Sat, 09 Sep 2023 23:51:35 -0700 (PDT) X-Received: by 2002:a63:798d:0:b0:573:fe13:199a with SMTP id u135-20020a63798d000000b00573fe13199amr1343342pgc.1.1694328695519; Sat, 09 Sep 2023 23:51:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.mixmin.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Sep 2023 23:51:34 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=157.119.108.226; posting-account=cM42uAoAAABH-hOzSh3ppkhlKn0dnRZy NNTP-Posting-Host: 157.119.108.226 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6db5668f-571c-4311-aa10-00a2b64d4ca9n@googlegroups.com> Subject: Facing some error while running a project in vsim with intel library files. From: Sreekanth Billupati Injection-Date: Sun, 10 Sep 2023 06:51:35 +0000 Content-Type: text/plain; charset="UTF-8" Xref: news.eternal-september.org comp.lang.vhdl:9924 # Loading /tmp/wisig@wisig-OptiPlex-7090_dpi_30084/linux_x86_64_gcc-7/vsim_auto_compile.so # End time: 16:23:27 on Sep 07,2023, Elapsed time: 0:00:03 Regards . Sreekanth From newsfish@newsfish Thu Aug 1 00:46:47 2024 X-Received: by 2002:a05:620a:269c:b0:76e:e65f:3d0a with SMTP id c28-20020a05620a269c00b0076ee65f3d0amr107947qkp.1.1695261137267; Wed, 20 Sep 2023 18:52:17 -0700 (PDT) X-Received: by 2002:a05:6870:3a11:b0:1dc:27f6:7a10 with SMTP id du17-20020a0568703a1100b001dc27f67a10mr1768197oab.10.1695261137014; Wed, 20 Sep 2023 18:52:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!peer01.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Sep 2023 18:52:16 -0700 (PDT) Injection-Info: google-groups.googlegroups.com; posting-host=2409:408d:3113:9c25:19e7:b1b8:4653:c3d7; posting-account=tdK8lAoAAAAagfV-pK8CY8uzhVKzVimY NNTP-Posting-Host: 2409:408d:3113:9c25:19e7:b1b8:4653:c3d7 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94d500fb-1e5c-4b8a-9a21-ef6a29c11c1bn@googlegroups.com> Subject: Mod 6 counter using Mod 8 counter From: "NAVIN PRASATH.M ECE" <1911010@nec.edu.in> Injection-Date: Thu, 21 Sep 2023 01:52:17 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3447 Xref: news.eternal-september.org comp.lang.vhdl:9925 I am trying to implement mod 6 counter using mod 8 counter with JK Flipflop= but the output waveform is not correct as required.What is the mistake in= my code? module mod_six_counter(clk,rst,q,qbar); input clk; input wire rst; output wire [2:0]q; output [2:0]qbar; assign rst =3D ~((~qbar[0])&qbar[1]&(qbar[2])); jkff ff1(1'b1,1'b1,clk,rst,q[0],qbar[0]); jkff ff2(1'b1,1'b1,qbar[0],rst,q[1],qbar[1]); jkff ff3(1'b1,1'b1,qbar[1],rst,q[2],qbar[2]); endmodule module jkff(j,k,clk,rst,q,qbar); input j,k,clk,rst; output reg q; output qbar; always@(posedge clk or negedge rst) begin if (!rst) q <=3D 1'b0; else begin case({j,k}) 2'b00 : q<=3Dq; 2'b01 : q<=3D1'b0; 2'b10 : q<=3D1'b1; 2'b11 : q<=3D~q; endcase end end assign qbar =3D ~q; endmodule TestBench Code : module tbmod_sixcounter; reg clk,rst; wire[2:0] q,qbar; mod_six_counter DUT(.clk(clk),.rst(rst),.q(q),.qbar(qbar)); always #10 clk=3D~clk; initial=20 begin clk<=3D0; rst<=3D0; #7 rst<=3D1; =20 end endmodule =20 =20 --=20 *--------------------------------------------------------------------------= ---------------------------------------------------------------------------= --------------------------------------------* * * National Engineering College, Kovilpatti ||=20 Autonomous Institution || Affiliated to Anna University, Chennai=20 Accredited by NAAC =E2=80=98A=E2=80=99 Grade & NBA* || NIRF 2022 RANK 169 || ARIIA 2021=20 RANK Band 'Excellent' 10th Rank (All India Level) || AICTE - IIC 4 STAR=20 RATING UG || B.E. - MECH*, =C2=A0ECE*, CSE*, EEE*, CIVIL || B.Tech. - IT*,=20 Artificial Intelligence and Data Science PG || M.E. - Computer Science=20 & Engineering, Energy Engineering, High Voltage Engineering, Embedded=20 Systems Technologies || M.Tech. =E2=80=93 Information Technology (Information and=20 Cyber Warfare) 39 Years of Academic Excellence || DST-FIST Sponsored Institution || K.R.Innovation Centre || NewGen IEDC, DST, New Delhi https://nec.edu.in || Phone: 04632-222 502, 93859=20 76674, 93859 76684 || TNEA COUNSELLING CODE: 4962 ** From newsfish@newsfish Thu Aug 1 00:46:48 2024 Path: eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: littlewing Newsgroups: comp.lang.vhdl Subject: VHDL Blocks Seen As Useful Date: Sun, 1 Oct 2023 11:23:35 -0400 Organization: A noiseless patient Spider Lines: 23 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 1 Oct 2023 15:23:36 -0000 (UTC) Injection-Info: dont-email.me; posting-host="00e7f282802d7e2a7b948cbe3357d9e4"; logging-data="1712033"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+HDfR67agkqVqwnzsntxerDOtH20BshiY=" User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Cancel-Lock: sha1:bs4+SHqaJ7GYFlbqF+ZVUmJUi38= Content-Language: en-US Xref: news.eternal-september.org comp.lang.vhdl:9926 One of my VHDL textbooks does not mention VHDL Blocks at all, the other grudgingly admits to their existence but recommends against using them. One online advice respondent says "never use blocks". I like VHDL blocks and use them all the time. 1. They help me organize long files and let me reuse common names. For example, a large architecture might have 3 or 4 state machines. I write boilerplate state machine code with "type state_t is (...);" and "signal state, next_state : state_t:", with each state machine in its own block. You don't have to invent new names. On the other hand, you must give blocks names: choose informative names and it helps with documentation. 2. My editor notepad++ handles blocks nicely. I can "collapse" blocks to navigate within files easily. 3. The Xilinx default simulator hierarchy viewer handles blocks nicely. When I hover over a signal in the waveform viewer, the tooltip tells my what block the signal is in. I agree with the common advice to not use blocks when component instantiations would be more appropriate. From newsfish@newsfish Thu Aug 1 00:46:48 2024 X-Received: by 2002:ad4:568f:0:b0:67a:a87d:cdd8 with SMTP id bd15-20020ad4568f000000b0067aa87dcdd8mr88534qvb.11.1701605982406; Sun, 03 Dec 2023 04:19:42 -0800 (PST) X-Received: by 2002:a05:6808:152b:b0:3b8:9ccf:6ee1 with SMTP id u43-20020a056808152b00b003b89ccf6ee1mr1659752oiw.3.1701605982239; Sun, 03 Dec 2023 04:19:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!feeder3.eternal-september.org!eternal-september.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 3 Dec 2023 04:19:41 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=173.195.15.231; posting-account=d-OyGwoAAABdvcbBPlZuGMCEYItD5sDU NNTP-Posting-Host: 173.195.15.231 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Audicarradiodecodertorrent From: Alix Stocking Injection-Date: Sun, 03 Dec 2023 12:19:42 +0000 Content-Type: text/plain; charset="UTF-8" Xref: news.eternal-september.org comp.lang.vhdl:9928 Audicarradiodecodertorrent Download https://constilavi.blogspot.com/?file=2wHMH0 eebf2c3492 From newsfish@newsfish Thu Aug 1 00:46:49 2024 X-Received: by 2002:a05:6214:4c19:b0:67f:86bc:9dce with SMTP id qh25-20020a0562144c1900b0067f86bc9dcemr84499qvb.1.1703791210117; Thu, 28 Dec 2023 11:20:10 -0800 (PST) X-Received: by 2002:a05:690c:350f:b0:5e6:1070:44e0 with SMTP id fq15-20020a05690c350f00b005e6107044e0mr4318977ywb.5.1703791209768; Thu, 28 Dec 2023 11:20:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!feeder3.eternal-september.org!weretis.net!feeder8.news.weretis.net!3.eu.feeder.erje.net!feeder.erje.net!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Dec 2023 11:20:09 -0800 (PST) Injection-Info: google-groups.googlegroups.com; posting-host=2001:ac8:22:96:21:0:0:1; posting-account=W5_ZMQoAAADKZO2IFFbKeS_FDvenyd8h NNTP-Posting-Host: 2001:ac8:22:96:21:0:0:1 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: e From: Integral West Injection-Date: Thu, 28 Dec 2023 19:20:10 +0000 Content-Type: text/plain; charset="UTF-8" Xref: news.eternal-september.org comp.lang.vhdl:9934 https://80499.blogspot.com/ https://37619.blogspot.com/ https://66718.blogspot.com/ https://58978.blogspot.com/ https://92772.blogspot.com/ https://43483.blogspot.com/ https://71552.blogspot.com/ https://59406.blogspot.com/ https://38909.blogspot.com/ https://64659.blogspot.com/ From newsfish@newsfish Thu Aug 1 00:46:49 2024 Path: eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?Q?Niocl=C3=A1s_P=C3=B3l_Caile=C3=A1n_de_Ghloucester?= Newsgroups: comp.arch.embedded,comp.lang.vhdl,comp.arch.fpga Subject: Re: Richard Stallman is responsible for the shrinking economy Date: Tue, 16 Jul 2024 01:28:47 +0200 Organization: A noiseless patient Spider Lines: 184 Message-ID: <2a08c699-6cf6-dc42-aa4c-9bca8c95e7eb@from.NL> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-353711597-1721086134=:369627" Injection-Date: Tue, 16 Jul 2024 01:28:54 +0200 (CEST) Injection-Info: dont-email.me; posting-host="dcb8dd3cda0485cb2169631503a170cd"; logging-data="978344"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ztScm1qZKy8EasZ2S+ak9+s6FQD7yYIlLnByW54muzQ==" Cancel-Lock: sha1:1Fh97O2rx/OiUgCoWcKGgr7vJCo= Xref: news.eternal-september.org comp.arch.embedded:51731 comp.lang.vhdl:9937 comp.arch.fpga:28027 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-353711597-1721086134=:369627 Content-Type: text/plain; format=flowed; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Jon Kirwan wrote: "On Sun, 12 Apr 2009 21:00:39 -0500, Walter Banks wrote: >przemek klosowski wrote: > >> On Thu, 09 Apr 2009 09:47:52 -0400, Walter Banks wrote: >> >> > At that level of software products you are right, but that is only=20 part >> > of the story. The open source has put a lot of pressure on=20 innovation in >> > software technology. When expectations are that software products=20 are >> > low or zero cost there is less potential reward for taking=20 speculative >> > risk exploring new ideas. >> > >> > The whole industry suffers. We are using operating systems that were >> > designed 20 years ago, running for the most part on processors with >> > instruction sets designed for hand written assembler. >> >> Walter, you obviously have a track record of innovation in this=20 industry >> that gives you first dibs on speaking on this topic, but I just don't=20 see >> your point. Are you claiming that the progress in embedded technology >> in the Open Source era, which I would arbitrarily define as the last=20 10 >> years, was significantly impaired? I just don't see it this way. > >The open source has had the effect of putting price pressure on >innovation in software technology by making lowering the potential >reward ./ risk ratio. The open source movement has not embraced >standards and has not generally participated in the standards process. I assume here you are speaking from your own experiences with the c standards processes. Since you probably have some ideas about this, how would a single representative be selected and representative of the "open source movement" in the standards processes? I mean this seriously. I'm curious how that might be made to work well and I'd like to hear your thoughts about it. It might be that the well-worn paths in the standards processes are tuned, more because of historical circumstances, to the traditional models that existed earlier and it may be expecting a lot to imagine a situation with an "open source movement" working without some significant adaptations. In the above, I am intentionally conflating "open source movement" with GNU c. I know I'm doing that "on the table." I intend it as a prod to ask you to tease the two things apart, again. In so doing, that I understand the comments better. >GCC has not participated in any meaningful way in WG14 the >ISO international standards group (represented in the US >by ANSI). What is more disturbing is GCC has not made a >significant attempt to be ANSI/ISO compliant. The test suite >distributed with GCC is a regression list of past bugs and >development \test cases not a language syntax test of organized >code generation test. Well, that regression list is for obvious reasons -- in the flurry of contributed activity unlike what a single organized group working together experiences, to "form a floor" beneath which they cannot (hopefully) sink. Clearly, it's needed. What you are really talking about is the ANSI/ISO compliance and participation. I am already asking you above about how that participation might meaningfully take place -- in a room _full_ of people representing commercial interests, it might be interesting -- at a minimum. But if you feel it can work, I'm interested in hearing how. As for compliance, I have to admit my own ignorance. Can you elaborate with some examples so that I can understand and comment? >This thread has generally shown respect for IP rights and licenses >the exception has been respect for standards. C standards >organizations are partly paid for by publications to users. >(Standards participants are not paid) It is disturbing that >some of the strongest advocates for open source are also willing >to violate standards copyrights and undermine the organizations >that help everyone open or otherwise. Do you have any insider information or educated guesses about why it is that FSF hasn't participated, or other significant groups in the open software movement? Other than just to say that you are concerned they haven't participated more? Frankly, I've only some vague guesses about it and I fear most of them are rather ill-informed ones at that. I'm curious not so much about the simple facts you claim as about why you think they have come to be that way, today? >> The proliferation of standard platforms, . . . enabled an amazing >> acceleration of >> novel, innovative things. Open Source can't claim the entire >> responsibility, but it certainly contributed to the overall climate of >> interoperability. > >It is a question of degree. Academic innovation based on the GCC >or other FOSS core has been limited. There are a lot of major >University projects that just have not moved the technology forward >in any significant degree. I think the wider thesis you propose isn't about academic innovation. Taking your larger arguments here as a whole, you seem to me to be complaining that this lack of innovation across the board -- academic and commercial. In the commercial spaces, I tend to agree. On the academic side, I don't as much. I have pulled down and had a chance to read a few from lots of very good papers coming out over the last decade and a half -- all of which date well after the (now) ancient 1986 version of the Dragon Book and JR Ellis' excellent Ph.D. thesis on Bulldog (some of which _could_ be applied well today, but isn't.) My limited exposure sees more of a lack of delivery, and less a lack of good research. But on that lack of delivery, I might take your point that GNU c has had some impact in inhibiting risk taking. You'd know better than I would about that. Another facet that crosses my mind is the sweeping change in those who consider themselves programmers in my lifetime. In my earliest days, you were pretty much a graduate of some kind -- often physics -- and this meant a very high level of caliber could be expected. And "consumers" were very large corporations that could afford the custom built, air conditioned rooms and the near-million-dollar expenditures for the hardware. Companies hired the best on all sides, and got it. Today, computing is accessible to nearly everyone. I've already commented before here about a student coming up to me, complaining that the 2nd year course seemed too hard and that maybe their choice to choose a CS degree instead of an accounting degree was wrong... But when, when CS degrees didn't exist and people got into computing from the physics or math departments, there was no such question in anyone's mind I ever met. Not on the radar scope. But today, we have almost anyone with almost any level of native talent becoming programmers here and there. Not bad. Not good. Just different. And the marketplace itself, because of that, is also different. And so are the relative levels of research for various areas, I suppose. Maybe everything is just a two-edged sword. With choice and options and lower prices for consumers, there is a reduced level of innovation due to lack of excess profits to invest in research, for example. And a different consumer type, as well. A practical balance is probably the better we can hope for, if so. I wouldn't want the pendulum swung to one side or the other. In any case, there is no going back. Accountant types ARE choosing careers as programmers. It's life in the modern world. Anyway, I'm curious why you think it is important GNU/FSF folks get involved in the committee activities and how they might meaningfully do so. I would have imagined you didn't care, before your comments, because the standards activities go on through thick and thin and with hardly a word or complaint. Now, I wonder why you think this is significant. Unless all this was really just about the impact on tool developers making enough to innovate and maybe where you conflate these two together because you see the close connections better than I do. Jon" I used to study space engineering with a lady who had become hired by NASA= =20 as an electrical engineer. She has recently gone to a board of a bank. A then workmate at the European Space Agency planned a career change to=20 the European Central Bank. We all thought that it is a strange career=20 change. Within weeks he left the ECB and returned to ESA explaining that=20 the ECB's problems are political whereas ESA's problems are technical. Sincerely. Niocl=C3=A1s P=C3=B3l Caile=C3=A1n de Ghloucester HTTP://Gloucester.Insomnia247.NL/VHDL --8323329-353711597-1721086134=:369627-- From newsfish@newsfish Thu Aug 1 00:46:49 2024 Path: eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?Q?Niocl=C3=A1s_P=C3=B3l_Caile=C3=A1n_de_Ghloucester?= Newsgroups: comp.lang.vhdl,comp.lang.ada Subject: Journal of Scientific Practice and Integrity Date: Sun, 21 Jul 2024 00:49:22 +0200 Organization: A noiseless patient Spider Lines: 58 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset=US-ASCII Injection-Date: Sun, 21 Jul 2024 00:49:50 +0200 (CEST) Injection-Info: dont-email.me; posting-host="a47764c5537425a55bf16ba3f13f03d9"; logging-data="3934928"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18a35UxEQzZWW5rfe7uJdDaAh8QsIT3B/tivvFvxlHl3w==" Cancel-Lock: sha1:tUKiGO3EUgZWAscDAwK+UGiUFpI= Xref: news.eternal-september.org comp.lang.vhdl:9938 comp.lang.ada:66230 Dear all, "The Journal of Scientific Practice and Integrity" is a relevant good website. Alas Clay Risen, "David Egilman, Doctor Who Took On Drug Companies, Dies at 71", "The New-York Times", April 15, 2024, HTTPS://WWW.NYTimes.com/2024/04/15/health/david-egilman-dead.html reports that an editor thereof died. Alas, "Notice of Journal Closure January 26, 2024 EDT We want to inform our readers and contributors that The Journal of Scientific Practice and Integrity will be closed from this year. We will not accept any more articles for publication henceforth. The articles published so far will be available for readers at jospi.org, as far as possible. We encourage contributors and readers to print their articles as PDF files, and or download archives from the website of the journal so that the articles will not be lost if we have to close the website due to any reason in future. It was our sincere effort to offer an open access, free journal for both contributors and readers over the last five years. We hope we were successful in our efforts. We regret that we have to stop this activity owing to unavoidable circumstances. We thank our contributors and readers for the overwhelming response they gave us. Editors" says HTTPS://WWW.JOSPI.org/post/2340-notice-of-journal-closure so I attempted to copy "The Journal of Scientific Practice and Integrity" to HTTP://Gloucester.Insomnia247.NL/Evil_which_is_so-called_science/Journal_of_Scientific_Practice_and_Integrity/ I tried e.g. pavuk -noRobots -mode mirror -preserve_time -index_name index_by_Pavuk.HTM -store_index -hack_add_index https://www.jospi.org/ > Pavuk_www.jospi.org.stdout.txt 2> Pavuk_www.jospi.org.stderr.txt and httrack --robots=0 --mirror --near --extra-log --file-log --index --build-top-index --search-index '-*p3' --debug-headers WWW.JOSPI.org '+*' and lftp -e mirror https://WWW.JOSPI.org and wget2 -e robots=off --output-file=Wget_logfile.txt --verbose --xattr --timestamping --server-response --mirror --page-requisites --backup-converted WWW.JOSPI.org and wget -e robots=off --output-file=Wget_logfile.txt --verbose --xattr --rejected-log=rejected-log.txt --timestamping --server-response --mirror --page-requisites --backup-converted WWW.JOSPI.org but they all failed miserably! Pwget is also not helpful. Manually backing up hopefully everything from JOSPI.org via GUI webbrowsers took myself nearly 3 hours to save circa 705 files! Scholastica sucks! If I missed anything then please warn me so that we can attempt to save it. Does anyone know the best way to back up a Scholastica website? From newsfish@newsfish Thu Aug 1 00:46:50 2024 Path: eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?Q?Niocl=C3=A1s_P=C3=B3l_Caile=C3=A1n_de_Ghloucester?= Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.arch.embedded Subject: Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers Date: Sun, 21 Jul 2024 18:16:53 +0200 Organization: A noiseless patient Spider Lines: 35 Message-ID: <8fd3081d-4977-c809-2c81-c200605ac323@insomnia247.nl> References: <5ccd7c07-93d6-424d-909b-b13ebe6cf1f2n@googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset=US-ASCII Injection-Date: Sun, 21 Jul 2024 18:16:57 +0200 (CEST) Injection-Info: dont-email.me; posting-host="a47764c5537425a55bf16ba3f13f03d9"; logging-data="185421"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19JbnuLBpMMnVmOlFsxiCTV5SpdQoZ1DhzBUvnvCHX7Sw==" Cancel-Lock: sha1:vlz4kWkLbJFUvU5bVixxJ+eJ5sc= In-Reply-To: <5ccd7c07-93d6-424d-909b-b13ebe6cf1f2n@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:9939 comp.arch.fpga:28029 comp.arch.embedded:51735 Fereydoun Memarzanjany wrote via Google on 21/02/2024: " https://gist.github.com/Thraetaona/ba941e293d36d0f76db6b9f3476b823c Having just started learning FPGA Hardware Description Languages by attempting to write a simple LED blinker, I found that the overwhelming majority of the Internet's solution to slowing down a fast clock (for making the pulsing of an LED visible to the human eye) was either using vendor-specific, proprietary clock managers and PLLs or implementing some twenty-something-bit-wide counter as to count hundreds of thousands of clock cycles and generate a 1 Hz output. Although there is a world of difference between counters in hardware-accelerated designs and those in software-emulated ones, I nonetheless viewed the number of daisy-chained components resulting from a mere counter as far-from-ideal and absurd; I began searching for a more efficient method. I came upon a rather obscure blog post from 2015 (http://www.markharvey.info/art/srldiv_04.10.2015/srldiv_04.10.2015.html) outlining the exact same issue while also referencing Xilinx systems designer Mr. Ken Chapman's proposal: using FPGAs' shift register primitives (e.g., Xilinx's SRL32E) to alleviate that. However, the method described therein would rely on the user to calculate the target frequency's factors between [2, 32) and painstakingly connect each and every instance of SRL32Es to one another, all in a manual manner, not to mention that the resulting pulse would have a low, one-cycle-long duty. Thus, I wrote `srl_prescaler.vhd`, a fully automated template generator in VHDL for an efficient, register-based cascaded clock divider based solely on SRL32 primitives alongside AND gates---the advantage of this module is that it is very generic and easy-to-use: ``` prescaler : entity work.srl_prescaler generic map (100e6, 1) port map (clk_in_100mhz, ce_out_1hz); ``` In the above example, an input clock of 100 MHz (i.e., `100e6` & `clk_in_100mhz`) gets divided into a clock enable signal of 1 Hz (i.e., `1` & `ce_out_1hz`). Among the other improvements, a third optional parameter (i.e., the duty cycle) may also get supplied as a real number (0.00, 1.00) to the generic map. Overall, this small project makes an otherwise-niche method more accessible by actually making use of the many language features that VHDL has to offer (e.g., pre-computing factor results using functions, automating hardware creation via for...generate clauses, latching using registers and guarded signals, etc.), serving as a simple yet practical learning point. Visualized and Tabular Comparisons: https://gist.github.com/Thraetaona/ba941e293d36d0f76db6b9f3476b823c?permalink_comment_id=4856214#gistcomment-4856214 (Usenet is shutting down tomorrow on February 22, 2024; this should be one of the last messages.)" Dear Fereydoun, Usenet did not shut down. Google is not Usenet. Google ignores new Usenet posts. However, news.eternal-September.org does not show this quoted article so I saw it for the 1st time today via a different USENET server.