Re: Modeling the condition code register in register allocation

On 10 ,q,_,S, 07:38, Roland Lei),a <roland.lei...@googlemail.com> wrote:


> The first variant touches rflags, the second doesn't. As one can
> easily see this will be tricky to model especially when the
> intermediate representation should be as architecture independent as
> possible.
>
> Some ideas or related papers?
Ideas:
1) Create IF_GREATER, IF_EQUAL etc commands in IR - this is the most
architecture independent variant.


2) Use peephole optimisation on generated code/IR
    CMPQ $10, %rax
    SETG %dl ;< Peephole optimizer sees these
    TEST %dl, %dl ;< lines
    JNZ label1 ;<
    JMP label2
;
; and replace triplet SETG/TEST/JNZ (or whatever you use) with JG
;
    CMPQ $10, %rax
    JG label1
    JMP label2


but beware that everything will die if %dl=(d>10) is used somewhere
in label1, label2. So such optimisation only can be used if optimzer
already proved that d variable not used in codeblocks reachable from
label1 and label2

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